74ACTQ374QSC [TI]
ACT SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDSO20, QSOP-20;
| 型号： | 74ACTQ374QSC |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | ACT SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDSO20, QSOP-20 驱动 光电二极管 输出元件 逻辑集成电路 触发器 |
| 文件： | 总12页 (文件大小：221K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
March 1993
54ACQ/74ACQ374 54ACTQ/74ACTQ374
#
Quiet Series Octal D Flip-Flop
with TRI-STATE Outputs
É
General Description
Features
Y
CC
I
and I
reduced by 50%
OZ
The ’ACQ/’ACTQ374 is a high-speed, low-power octal D-
type flip-flop featuring separate D-type inputs for each flip-
flop and TRI-STATE outputs for bus-oriented applications. A
buffered Clock (CP) and Output Enable (OE) are common to
all flip-flops.
Y
Guaranteed simultaneous switching noise level and
dynamic threshold performance
Y
Y
Y
Y
Guaranteed pin-to-pin skew AC performance
Improved latch-up immunity
The ’ACQ/’ACTQ374 utilizes Quiet Series technology to
guarantee quiet output switching and improve dynamic
threshold performance. FACT Quiet SeriesTM features
GTOTM output control and undershoot corrector in addition
to a split ground bus for superior performance.
Buffered positive edge-triggered clock
TRI-STATE outputs drive bus lines or buffer memory
address registers
Y
Y
Y
Y
Outputs source/sink 24 mA
Faster prop delays than the standard ’AC/’ACT374
4 kV minimum ESD immunity
Standard Military Drawing (SMD)
Ð ’ACTQ374: 5962-92189
Ð ’ACQ374: 5962-92179
Logic Symbols
Connection Diagrams
Pin Assignment for DIP,
Flatpak, QSOP and SOIC
IEEE/IEC
TL/F/10238–1
TL/F/10238–3
TL/F/10238–2
Pin Assignment
for LCC
Pin Names
Description
Data Inputs
D –D
0
7
CP
OE
Clock Pulse Input
TRI-STATE Output Enable Input
TRI-STATE Outputs
O –O
0
7
TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.
FACTTM, FACT Quiet SeriesTM, and GTOTM are trademarks of National Semiconductor Corporation.
TL/F/10238–4
C
1995 National Semiconductor Corporation
TL/F/10238
RRD-B30M75/Printed in U. S. A.
Functional Description
Truth Table
The ’ACQ/’ACTQ374 consists of eight edge-triggered flip-
flops with individual D-type inputs and TRI-STATE true out-
puts. The buffered clock and buffered Output Enable are
common to all flip-flops. The eight flip-flops will store the
state of their individual D inputs that meet the setup and
hold time requirements on the LOW-to-HIGH Clock (CP)
transition. With the Output Enable (OE) LOW, the contents
of the eight flip-flops are available at the outputs. When the
OE is HIGH, the outputs go to the high impedance state.
Operation of the OE input does not affect the state of the
flip-flops.
Inputs
Outputs
D
CP
OE
O
n
n
H
L
L
X
L
L
H
L
L
X
H
Z
e
e
e
e
H
L
HIGH Voltage Level
LOW Voltage Level
Immaterial
X
Z
High Impedance
e
L
LOW-to-HIGH Transition
Logic Diagram
TL/F/10238–5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
2
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Recommended Operating
Conditions
Supply Voltage (V
’ACQ
’ACTQ
)
CC
2.0V to 6.0V
4.5V to 5.5V
b
a
0.5V to 7.0V
Supply Voltage (V
)
CC
DC Input Diode Current (I
)
IK
Input Voltage (V )
I
0V to V
0V to V
CC
e b
b
a
V
I
V
I
0.5V
a
20 mA
20 mA
Output Voltage (V
)
O
CC
e
V
CC
0.5V
Operating Temperature (T )
A
74ACQ/ACTQ
54ACQ/ACTQ
b
b
a
0.5V
DC Input Voltage (V )
I
0.5V to V
0.5V to V
CC
b
b
a
40 C to 85 C
§
55 C to 125 C
§
§
DC Output Diode Current (I
)
a
OK
§
e b
b
a
V
V
0.5V
a
20 mA
20 mA
O
O
Minimum Input Edge Rate DV/Dt
’ACQ Devices
e
V
CC
0.5V
a
DC Output Voltage (V
DC Output Source
)
O
0.5V
50 mA
50 mA
CC
V
V
from 30% to 70% of V
@
IN
CC
3.0V, 4.5V, 5.5V
125 mV/ns
CC
g
g
or Sink Current (I
)
O
Minimum Input Edge Rate DV/Dt
’ACTQ devices
DC V
or Ground Current
CC
per Output Pin (I or I
CC
)
V
V
from 0.8V to 2.0V
@
GND
)
IN
4.5V, 5.5V
125 mV/ns
b
a
65 C to 150 C
CC
Storage Temperature (T
§
§
300 mA
STG
Note: All commercial packaging is not recommended for applications requir-
a
ing greater than 2000 temperature cycles from 40 C to 125 C.
g
DC Latch-Up Source or Sink Current
b
§
§
Junction Temperature (T )
J
CDIP
PDIP
175 C
§
140 C
§
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, without
exception, to ensure that the system design is reliable over its power supply,
temperature, and output/input loading variables. National does not recom-
mend operation of FACTTM circuits outside databook specifications.
DC Characteristics for ’ACQ Family Devices
74ACQ
54ACQ
74ACQ
e
a
e
T
A
V
CC
(V)
T
A
55 C to 125 C
e a
Symbol
Parameter
T
25 C
§
Units
Conditions
A
b
b a
40 C to 85 C
§
Guaranteed Limits
§
§
§
Typ
e
0.1V
V
V
V
Minimum High Level
Input Voltage
3.0
4.5
5.5
1.5
2.1
2.1
2.1
V
IH
OUT
b
2.25
2.75
3.15
3.85
3.15
3.85
3.15
3.85
V
V
V
or V
CC
0.1V
e
Maximum Low Level
Input Voltage
3.0
4.5
5.5
1.5
0.9
0.9
0.9
V
OUT
0.1V
IL
b
2.25
2.75
1.35
1.65
1.35
1.65
1.35
1.65
or V
CC
0.1V
e b
OUT
Minimum High Level
Output Voltage
3.0
4.5
5.5
2.99
4.49
5.49
2.9
4.4
5.4
2.9
4.4
5.4
2.9
4.4
5.4
I
50 mA
OH
e
*V
IN
V
or V
IH
12 mA
IL
b
b
b
3.0
4.5
5.5
2.56
3.86
4.86
2.4
3.7
4.7
2.46
3.76
4.76
V
V
I
24 mA
24 mA
OH
e
e
V
OL
Maximum Low Level
Output Voltage
3.0
4.5
5.5
0.002
0.001
0.001
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
I
50 mA
OUT
*V
IN
V or V
IL IH
3.0
4.5
5.5
0.36
0.36
0.36
0.50
0.50
0.50
0.44
0.44
0.44
12 mA
V
I
24 mA
24 mA
OL
e
(Note 1)
I
Maximum Input
Leakage Current
V
V
, GND
IN
I
CC
g
g
g
1.0
5.5
0.1
1.0
mA
*All outputs loaded; thresholds on input associated with output under test.
3
DC Characteristics for ’ACQ Family Devices (Continued)
74ACQ
54ACQ
74ACQ
e
a
e
T
A
V
CC
(V)
T
A
55 C to 125 C
e a
Symbol
Parameter
T
25 C
§
Units
Conditions
A
b
b a
40 C to 85 C
§
Guaranteed Limits
§
§
§
Typ
e
²
I
I
I
Minimum Dynamic
5.5
5.5
50
75
mA
mA
V
V
V
1.65V Max
OLD
OHD
CC
OLD
Output Current
b
b
e
3.85V Min
OHD
50
75
e
Maximum Quiescent
Supply Current
V
CC
IN
5.5
5.5
4.0
80.0
40.0
mA
mA
or GND (Note 1)
e
I
Maximum TRI-STATE
Leakage Current
V (OE)
I
V , V
IL IH
OZ
e
e
g
g
g
2.5
0.25
5.0
V
V
V
CC
, GND
I
V
CC
, GND
O
V
OLP
V
OLV
V
IHD
V
ILD
Quiet Output
Figures 2-12, 13
(Notes 2 and 3)
5.0
5.0
5.0
5.0
1.1
1.5
V
V
V
V
Maximum Dynamic V
OL
OL
Quiet Output
Figures 2-12, 13
(Notes 2 and 3)
b
b
1.2
0.6
Minimum Dynamic V
Minimum High Level
(Notes 2 and 4)
3.1
3.5
1.5
Dynamic Input Voltage
Maximum Low Level
(Notes 2 and 4)
1.9
Dynamic Input Voltage
²
Maximum test duration 2.0 ms, one output loaded at a time.
@
@
3.0V are guaranteed to be less than or equal to the respective limit 5.5V V
Note 1: I and I
IN
.
CC
CC
@ @
for 54ACQ 25 C is identical to 74ACQ 25 C.
§ §
I
CC
Note 2: Plastic DIP Package.
Note 3: Max number of outputs defined as (n). Data inputs are driven 0V to 5V. One output GND.
@
b
Note 4: Max number of data inputs (n) switching. (n 1) inputs switching 0V to 5V (’ACQ). Input-under-test switching: 5V to threshold (V ), 0V to threshold (V ),
ILD
IHD
e
f
1 MHz.
DC Characteristics for ’ACTQ Family Devices
74ACTQ
54ACTQ
74ACTQ
e
a
e
T
A
V
CC
(V)
T
A
55 C to 125 C
e a
Symbol
Parameter
T
25 C
§
Units
Conditions
A
b
b a
40 C to 85 C
§
Guaranteed Limits
§
§
§
Typ
e
0.1V
V
V
V
Minimum High Level
Input Voltage
4.5
5.5
1.5
1.5
2.0
2.0
2.0
2.0
2.0
2.0
V
IH
OUT
V
V
V
b
or V
CC
0.1V
e
Maximum Low Level
Input Voltage
4.5
5.5
1.5
1.5
0.8
0.8
0.8
0.8
0.8
0.8
V
OUT
0.1V
IL
b
or V
CC
0.1V
e b
OUT
Minimum High Level
Output Voltage
4.5
5.5
4.49
5.49
4.4
5.4
4.4
5.4
4.4
5.4
I
50 mA
OH
e
*V
IN
V
or V
IH
24 mA
IL
b
b
4.5
5.5
3.86
4.86
3.70
4.70
3.76
4.76
V
V
I
OH
24 mA
e
e
V
OL
Maximum Low Level
Output Voltage
4.5
5.5
0.001
0.001
0.1
0.1
0.1
0.1
0.1
0.1
I
50 mA
OUT
*V
IN
V or V
IL IH
4.5
5.5
0.36
0.36
0.50
0.50
0.44
0.44
24 mA
V
I
OL
24 mA
e
I
I
Maximum Input
Leakage Current
V
V
, GND
CC
IN
I
g
g
g
g
g
5.5
5.5
0.1
1.0
5.0
1.0
2.5
mA
mA
e
Maximum TRI-STATE
Current
V
V
V , V
IL IH
OZ
I
g
0.25
e
V
, GND
CC
O
*All outputs loaded; thresholds on input associated with output under test.
4
DC Characteristics for ’ACTQ Family Devices (Continued)
74ACTQ
54ACTQ
74ACTQ
e
a
e
T
A
V
CC
(V)
T
A
55 C to 125 C
e a
Symbol
Parameter
T
25 C
§
Units
Conditions
A
b
b a
40 C to 85 C
§
Guaranteed Limits
§
§
§
Typ
e
b
2.1V
I
Maximum
/Input
V
V
CC
CCT
I
5.5
0.6
1.6
50
1.5
75
mA
I
CC
e
²
I
I
I
Minimum Dynamic
5.5
5.5
mA
mA
V
V
V
1.65V Max
e
3.85V Min
OLD
OHD
CC
OLD
Output Current
b
b
50
75
OHD
e
Maximum Quiescent
Supply Current
V
CC
IN
5.5
5.0
5.0
5.0
5.0
4.0
1.5
80.0
40.0
mA
V
or GND (Note 1)
V
V
V
V
Quiet Output
Figures 2-12, 13
(Notes 2 and 3)
OLP
OLV
IHD
ILD
1.1
Maximum Dynamic V
OL
OL
Quiet Output
Figures 2-12, 13
(Notes 2 and 3)
b
b
1.2
0.6
V
Minimum Dynamic V
Minimum High Level
(Notes 2 and 4)
1.9
2.2
V
Dynamic Input Voltage
Maximum Low Level
(Notes 2 and 4)
1.2
0.8
V
Dynamic Input Voltage
²
Maximum test duration 2.0 ms, one output loaded at a time.
@ @
for 54ACTQ 25 C is identical to 74ACTQ 25 C.
§ §
Note 1: I
CC
Note 2: Plastic DIP package.
Note 3: Max number of outputs defined as (n). Data inputs are driven 0V to 3V. One output GND
@
b
Note 4: Max number of data inputs (n) switching. (n 1) inputs switching 0V to 3V (’ACTQ). Input-under-test switching: 3V to threshold (V ), 0V to threshold
ILD
e
(V ), f
IHD
1 MHz.
AC Electrical Characteristics
74ACQ
54ACQ
e b
74ACQ
e b
40 C
T
55 C
T
§
to 125 C
§
A
A
e a
A
V *
CC
(V)
T
25 C
§
50 pF
a
e
a
e
Symbol
Parameter
to 85 C
Units
§
50 pF
§
50 pF
e
C
L
C
C
L
L
Min
Typ
Max
Min
Max
Min
Max
f
Maximum Clock
Frequency
3.3
5.0
75
90
95
95
70
85
max
MHz
ns
t
t
t
, t
PLH PHL
Propagation Delay
3.3
5.0
3.0
2.0
9.5
6.5
13.0
8.5
1.0
1.0
16.5
11.0
3.0
2.0
13.5
9.0
CP to O
n
, t
PZL PZH
Output Enable Time
Output Disable Time
Output to Output Skew**
3.3
5.0
3.0
2.0
9.5
6.5
13.0
8.5
1.0
1.0
16.5
11.5
3.0
2.0
13.5
9.0
ns
, t
PHZ PLZ
3.3
5.0
1.0
1.0
9.5
8.0
14.5
9.5
1.0
1.0
12.0
10.5
1.0
1.0
15.0
10.0
ns
t
t
,
3.3
5.0
1.0
0.5
1.5
1.0
1.5
1.0
OSHL
ns
CP to O
OSLH
n
g
*Voltage Range 5.0 is 5.0V 0.5V
g
Voltage Range 3.3 is 3.3V 0.3V
**Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification
applies to any outputs switching in the same direction, either HIGH to LOW (t
) or LOW to HIGH (t
). Parameter guaranteed by design.
OSLH
OSHL
5
AC Operating Requirements
74ACQ
54ACQ
e b
74ACQ
e b
40 C
T
55 C
T
§
to 125 C
§
A
A
e a
A
V *
CC
(V)
T
25 C
§
50 pF
a
e
a
Symbol
Parameter
to 85 C
Units
§
50 pF
§
e
C
L
e
50 pF
C
C
L
L
Typ
Guaranteed Minimum
t
t
t
Setup Time, HIGH or LOW
3.3
5.0
0
0
3.0
3.0
3.0
3.0
s
ns
ns
ns
D
n
to CP
3.0
3.0
Hold Time, HIGH or LOW
to CP
3.3
5.0
0
1.5
1.5
2.0
1.5
1.5
1.5
h
w
D
n
2.0
CP Pulse Width,
HIGH or LOW
3.3
5.0
2.0
2.0
4.0
4.0
5.0
5.0
4.0
4.0
g
*Voltage Range 5.0 is 5.0V 0.5V
g
Voltage Range 3.3 is 3.3V 0.3V
AC Electrical Characteristics
74ACTQ
54ACTQ
74ACTQ
e b
40 C
e b
T
55 C
T
§
to 125 C
§
A
A
e a
A
V
CC
(V)
*
T
25 C
§
50 pF
a
a
e
Symbol
Parameter
to 85 C
Units
§
50 pF
§
50 pF
e
C
L
e
C
C
L
L
Min
Typ
Max
Min
Max
Min
Max
f
t
Maximum Clock
Frequency
max
5.0
5.0
85
95
80
MHz
ns
, t
PLH PHL
Propagation Delay
2.0
7.0
9.0
2.0
11.5
2.0
9.5
CP to O
n
t
t
, t
PZL PZH
Output Enable Time
Output Disable Time
Output to Output Skew**
5.0
5.0
2.0
1.0
7.5
8.0
9.0
2.0
1.5
11.5
10.5
2.0
1.0
9.5
ns
ns
, t
PHZ PLZ
10.0
10.5
t
t
,
OSHL
5.0
0.5
1.0
1.0
ns
CP to O
OSLH
n
g
*Voltage Range 5.0 is 5.0V 0.5V
**Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification
applies to any outputs switching in the same direction, either HIGH to LOW (t
) or LOW to HIGH (t
). Parameter guaranteed by design.
OSLH
OSHL
AC Operating Requirements
74ACTQ
54ACTQ
e b
74ACTQ
e b
40 C
T
55 C
T
A
§
to 125 C
§
A
e a
A
V *
CC
(V)
T
25 C
§
50 pF
a
e
a
Symbol
Parameter
to 85 C
Units
§
50 pF
§
e
C
L
e
50 pF
C
C
L
L
Typ
Guaranteed Minimum
t
t
t
Setup Time, HIGH or LOW
s
5.0
5.0
5.0
0
3.0
3.5
3.0
ns
ns
ns
D
n
to CP
Hold Time, HIGH or LOW
to CP
h
w
0
1.5
4.0
2.0
5.0
1.5
4.0
D
n
CP Pulse Width,
HIGH or LOW
2.0
g
*Voltage Range 5.0 is 5.0V 0.5V
Capacitance
Symbol
Parameter
Input Capacitance
Power Dissipation Capacitance
Typ
4.5
Units
pF
Conditions
e
e
C
C
V
V
OPEN
5.0V
IN
CC
42.0
pF
PD
CC
6
FACT Noise Characteristics
The setup of a noise characteristics measurement is critical
to the accuracy and repeatability of the tests. The following
is a brief description of the setup used to measure the noise
characteristics of FACT.
6. Set the word generator input levels at 0V LOW and 3V
HIGH for ACT devices and 0V LOW and 5V HIGH for AC
devices. Verify levels with a digital volt meter.
V /V
OLP OLV
and V
/V :
OHP OHV
Equipment:
Determine the quiet output pin that demonstrates the
greatest noise levels. The worst case pin will usually be
the furthest from the ground pin. Monitor the output volt-
ages using a 50X coaxial cable plugged into a standard
SMB type connector on the test fixture. Do not use an
active FET probe.
#
Hewlett Packard Model 8180A Word Generator
PC-163A Test Fixture
Tektronics Model 7854 Oscilloscope
Procedure:
1. Verify Test Fixture Loading: Standard Load 50 pF, 500X.
Measure V
and V
OLV
on the quiet output during the
and V on the quiet out-
#
#
OLP
HL transition. Measure V
2. Deskew the word generator so that no two channels have
greater than 150 ps skew between them. This requires
that the oscilloscope be deskewed first. Swap out the
channels that have more than 150 ps of skew until all
channels being used are within 150 ps. It is important to
deskew the word generator channels before testing. This
will ensure that the outputs switch simultaneously.
OHP
put during the LH transition.
OHV
Verify that the GND reference recorded on the oscillo-
scope has not drifted to ensure the accuracy and repeat-
ability of the measurements.
V
and V
:
IHD
ILD
3. Terminate all inputs and outputs to ensure proper loading
of the outputs and that the input levels are at the correct
voltage.
Monitor one of the switching outputs using a 50X coaxial
cable plugged into a standard SMB type connector on
the test fixture. Do not use an active FET probe.
#
4. Set V
to 5.0V.
First increase the input LOW voltage level, V , until the
IL
output begins to oscillate. Oscillation is defined as noise
#
#
#
CC
5. Set the word generator to toggle all but one output at a
frequency of 1 MHz. Greater frequencies will increase
DUT heating and affect the results of the measurement.
on the output LOW level that exceeds V limits, or on
IL
output HIGH levels that exceed V limits. The input
IH
LOW voltage level at which oscillation occurs is defined
as V
.
ILD
Next increase the input HIGH voltage level on the word
generator, V until the output begins to oscillate. Oscilla-
IH
tion is defined as noise on the output LOW level that
exceeds V limits, or on output HIGH levels that exceed
IL
V
limits. The input HIGH voltage level at which oscilla-
.
IH
tion occurs is defined as V
IHD
Verify that the GND reference recorded on the oscillo-
scope has not drifted to ensure the accuracy and repeat-
ability of the measurements.
TL/F/10238–6
FIGURE 1. Quiet Output Noise Voltage Waveforms
Note A. V
and V
are measured with respect to ground reference.
OLP
OHV
e
Note B. Input pulses have the following characteristics:
f
1 MHz,
k
150 ps.
e
e
3 ns, skew
t
r
3 ns, t
f
TL/F/10238–7
FIGURE 2. Simultaneous Switching Test Circuit
7
Ordering Information
The device number is used to form part of a simplified purchasing code where the package type and temperature range are
defined as follows:
74ACTQ 374
P
C
QR
Temperature Range Family
e
54ACQ Military
e
Special Variations
e
e
74ACQ Commercial
e
74ACTQ Commercial TTL-Compatible
X
QR
Devices shipped in 13 reels
×
Commercial grade device with
burn-in
e
54ACTQ Military TTL-Compatible
e
QB
Military grade device with
environmental and burn-in
processing shipped in tubes
Device Type
Package Code
Temperature Range
e
e
e
e
e
e
e
P
D
F
L
S
QS
Plastic DIP
Ceramic DIP
Flatpak
Leadless Ceramic Chip Carrier (LCC)
Small Outline (SOIC)
Quarter Size Outline Package (QSOP)
b a
C
Commercial ( 40 C to 85 C)
§
§
e
b a
Military ( 55 C to 125 C)
M
§
§
8
Physical Dimensions inches (millimeters)
20-Terminal Ceramic Leadless Chip Carrier (L)
NS Package Number E20A
20-Lead Ceramic Dual-In-Line Package (D)
NS Package Number J20A
9
Physical Dimensions inches (millimeters) (Continued)
20-Lead Small Outline Integrated Circuit (S)
NS Package Number M20B
20-Lead Quarter Size Outline Package (QS)
NS Package Number MQA20
10
Physical Dimensions inches (millimeters) (Continued)
20-Lead Plastic Dual-In-Line Package (P)
NS Package Number N20B
11
Ý
Lit. 114677
Physical Dimensions inches (millimeters) (Continued)
20-Lead Ceramic Flatpak (F)
NS Package Number W20A
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