74ALVCH16244DLRG4 [TI]
16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS; 16位缓冲器/驱动器，具有三态输出
| 型号： | 74ALVCH16244DLRG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS |
| 文件： | 总19页 (文件大小：601K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74ALVCH16244
16-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCES014K–JULY 1995–REVISED OCTOBER 2005
FEATURES
DGG, DGV, OR DL PACKAGE
(TOP VIEW)
•
Member of the Texas Instruments Widebus™
Family
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1OE
1Y1
1Y2
GND
1Y3
1Y4
2OE
1A1
1A2
GND
1A3
1A4
•
•
•
•
Operates From 1.65 V to 3.6 V
Max tpd of 3 ns at 3.3 V
2
3
±24-mA Output Drive at 3.3 V
4
Bus Hold on Data Inputs Eliminates the Need
for External Pullup/Pulldown Resistors
5
6
•
•
Latch-Up Performance Exceeds 250 mA Per
JESD 17
7
V
CC
V
CC
8
2Y1
2Y2
GND
2Y3
2Y4
3Y1
3Y2
GND
3Y3
3Y4
2A1
2A2
GND
2A3
2A4
3A1
3A2
GND
3A3
3A4
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
DESCRIPTION/ORDERING INFORMATION
This 16-bit buffer/driver is designed for 1.65-V to
3.6-V VCC operation.
The SN74ALVCH16244 is designed specifically to
improve the performance and density of 3-state
memory address drivers, clock drivers, and
bus-oriented receivers and transmitters.
V
CC
V
CC
4Y1
4Y2
GND
4Y3
4Y4
4OE
4A1
4A2
GND
4A3
4A4
3OE
The device can be used as four 4-bit buffers, two
8-bit buffers, or one 16-bit buffer. It provides true
outputs and symmetrical active-low output-enable
(OE) inputs.
To ensure the high-impedance state during power up
or power down, OE should be tied to VCC through a
pullup resistor; the minimum value of the resistor is
determined by the current-sinking capability of the
driver.
blank
blank
blank
ORDERING INFORMATION
TA
PACKAGE(1)
ORDERABLE PART NUMBER
SN74ALVCH16244GRDR
SN74ALVCH16244ZRDR
SN74ALVCH16244DL
TOP-SIDE MARKING
FBGA – GRD
Tape and reel
VH244
FBGA – ZRD (Pb-free)
Tube
SSOP – DL
ALVCH16244
ALVCH16244
VH244
Tape and reel
SN74ALVCH16244DLR
SN74ALVCH16244DGGR
74ALVCH16244DGGRE4
SN74ALVCH16244DGVR
74ALVCH16244DGVRE4
SN74ALVCH16244KR
–40°C to 85°C
TSSOP – DGG
TVSOP – DGV
Tape and reel
Tape and reel
Tape and reel
VFBGA – GQL
VH244
VFBGA – ZQL (Pb-free)
74ALVCH16244ZQLR
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright © 1995–2005, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
SN74ALVCH16244
16-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCES014K–JULY 1995–REVISED OCTOBER 2005
DESCRIPTION/ORDERING INFORMATION (CONTINUED)
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors
with the bus-hold circuitry is not recommended.
GQL OR ZQL PACKAGE
TERMINAL ASSIGNMENTS(1)
(TOP VIEW)
(56-Ball GQL/ZQL Package)
1
2 3 4 5 6
1
2
3
4
5
6
A
B
C
D
E
F
G
H
J
A
B
C
D
E
F
1OE
1Y2
1Y4
2Y2
2Y4
3Y1
3Y3
4Y1
4Y3
4OE
NC
NC
NC
NC
2OE
1A2
1A4
2A2
2A4
3A1
3A3
4A1
4A3
3OE
1Y1
1Y3
2Y1
2Y3
3Y2
3Y4
4Y2
4Y4
NC
GND
VCC
GND
GND
VCC
GND
1A1
1A3
2A1
2A3
3A2
3A4
4A2
4A4
NC
G
H
J
GND
VCC
GND
NC
GND
VCC
GND
NC
K
K
ABC
ABC
(1) NC – No internal connection
GRD OR ZRD PACKAGE
(TOP VIEW)
TERMINAL ASSIGNMENTS(1)
(54-Ball GRD/ZRD Package)
1
2
3
4
5
6
1
2
3
4
5
6
A
B
C
D
E
F
1Y1
1Y3
2Y1
2Y3
3Y1
3Y3
4Y1
4Y3
4Y4
NC
1OE
NC
2OE
NC
NC
1A1
1A3
2A1
2A3
3A1
3A3
4A1
4A3
4A4
A
B
C
D
1Y2
1Y4
2Y2
2Y4
3Y2
3Y4
4Y2
NC
1A2
1A4
2A2
2A4
3A2
3A4
4A2
NC
VCC
GND
GND
GND
VCC
NC
VCC
GND
GND
GND
VCC
NC
E
F
G
H
J
G
H
J
4OE
3OE
(1) NC – No internal connection
xxxxx
FUNCTION TABLE
(EACH 4-BIT BUFFER)
INPUTS
OUTPUT
Y
OE
L
A
H
L
H
L
L
H
X
Z
2
SN74ALVCH16244
16-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCES014K–JULY 1995–REVISED OCTOBER 2005
LOGIC DIAGRAM (POSITIVE LOGIC)
1
25
1OE
1A1
3OE
47
46
2
3
5
6
36
35
33
32
13
1Y1
1Y2
1Y3
1Y4
3A1
3A2
3A3
3A4
3Y1
14
1A2
1A3
1A4
3Y2
44
43
16
3Y3
17
3Y4
48
41
24
30
2OE
2A1
2A2
2A3
2A4
4OE
4A1
4A2
4A3
4A4
8
9
19
2Y1
2Y2
2Y3
2Y4
4Y1
40
38
37
29
27
26
20
4Y2
11
12
22
4Y3
23
4Y4
Pin numbers shown are for the DGG, DGV, and DL packages.
3
SN74ALVCH16244
16-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCES014K–JULY 1995–REVISED OCTOBER 2005
Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
MIN
–0.5
–0.5
–0.5
MAX UNIT
VCC
VI
Supply voltage range
Input voltage range(2)
Output voltage range(2)(3)
4.6
4.6
V
V
VO
IIK
VCC + 0.5
-50
V
Input clamp current
VI < 0
mA
mA
mA
mA
IOK
IO
Output clamp current
VO < 0
-50
Continuous output current
Continuous current through each VCC or GND
±50
±100
70
DGG package
DGV package
58
θJA
Package thermal impedance(4)
DL package
63 °C/W
GQL/ZQL package
GRD/ZRD package
42
36
Tstg
Storage temperature range
–65
150
°C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
(3) This value is limited to 4.6 V maximum.
(4) The package thermal impedance is calculated in accordance with JESD 51-7.
Recommended Operating Conditions(1)
MIN
MAX UNIT
VCC
Supply voltage
1.65
3.6
V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
0.65 × VCC
VIH
High-level input voltage
1.7
2
V
0.35 × VCC
0.7
VIL
Low-level input voltage
V
0.8
VI
Input voltage
0
0
VCC
VCC
–4
V
V
VO
Output voltage
VCC = 1.65 V
VCC = 2.3 V
VCC = 2.7 V
VCC = 3 V
–12
–12
–24
4
IOH
High-level output current
Low-level output current
mA
mA
VCC = 1.65 V
VCC = 2.3 V
VCC = 2.7 V
VCC = 3 V
12
IOL
12
24
∆t/∆v
Input transition rise or fall rate
Operating free-air temperature
10 ns/V
85 °C
TA
–40
(1) All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
4
SN74ALVCH16244
16-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCES014K–JULY 1995–REVISED OCTOBER 2005
Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN TYP(1) MAX UNIT
IOH = –100 µA
IOH = –4 mA
IOH = –6 mA
1.65 V to 3.6 V
1.65 V
2.3 V
VCC – 0.2
1.2
2
VOH
2.3 V
1.7
2.2
2.4
2
V
IOH = –12 mA
2.7 V
3 V
IOH = –24 mA
IOL = 100 µA
IOL = 4 mA
3 V
1.65 V to 3.6 V
1.65 V
2.3 V
0.2
0.45
0.4
IOL = 6 mA
VOL
V
2.3 V
0.7
IOL = 12 mA
2.7 V
0.4
IOL = 24 mA
VI = VCC or GND
VI = 0.58 V
3 V
0.55
±5
II
3.6 V
µA
1.65 V
1.65 V
2.3 V
25
–25
45
VI = 1.07 V
VI = 0.7 V
II(hold)
VI = 1.7 V
2.3 V
–45
75
µA
VI = 0.8 V
3 V
VI = 2 V
3 V
–75
VI = 0 to 3.6 V(2)
VO = VCC or GND
VI = VCC or GND,
3.6 V
±500
±10
40
IOZ
3.6 V
µA
µA
µA
ICC
IO = 0
3.6 V
∆ICC
One input at VCC – 0.6 V, Other inputs at VCC or GND
3 V to 3.6 V
750
Control inputs
Data inputs
Outputs
3
6
7
Ci
VI = VCC or GND
3.3 V
3.3 V
pF
pF
Co
VO = VCC or GND
(1) All typical values are at VCC = 3.3 V, TA = 25°C.
(2) This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to
another.
Switching Characteristics
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
VCC = 1.8 V
VCC = 2.7 V
MIN MAX
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
TYP
MIN
1
MAX
MIN
1
MAX
(1)
tpd
ten
tdis
A
Y
Y
Y
3.7
5.7
5.2
3.6
5.4
4.6
3
4.4
4.1
ns
ns
ns
(1)
(1)
OE
OE
1
1
1
1
(1) This information was not available at the time of publication.
5
SN74ALVCH16244
16-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCES014K–JULY 1995–REVISED OCTOBER 2005
Operating Characteristics
TA = 25°C
VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V
PARAMETER
TEST CONDITIONS
UNIT
TYP
TYP
16
4
TYP
(1)
Outputs enabled
Outputs disabled
19
5
Power dissipation
capacitance
Cpd
CL = 50 pF, f = 10 MHz
pF
(1)
(1) This information was not available at the time of publication.
6
SN74ALVCH16244
16-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCES014K–JULY 1995–REVISED OCTOBER 2005
PARAMETER MEASUREMENT INFORMATION
V
LOAD
S1
Open
R
L
From Output
Under Test
TEST
S1
GND
t
Open
V
LOAD
GND
pd
/t
/t
C
t
t
L
PLZ PZL
R
L
(see Note A)
PHZ PZH
LOAD CIRCUIT
INPUT
V
CC
V
M
V
LOAD
C
L
R
L
V
∆
V
I
t /t
r f
1.8 V
V
V
2.7 V
2.7 V
V
/2
/2
2 × V
2 × V
6 V
6 V
1 kΩ
500 Ω
500 Ω
500 Ω
0.15 V
0.15 V
0.3 V
≤2 ns
≤2 ns
≤2.5 ns
≤2.5 ns
30 pF
30 pF
50 pF
50 pF
CC
CC
CC
2.5 V ± 0.2 V
2.7 V
V
CC
CC
CC
1.5 V
1.5 V
3.3 V ± 0.3 V
0.3 V
t
w
V
I
V
I
V
M
V
M
Input
Timing
Input
V
M
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
t
su
t
h
V
I
Output
Control
(low-level
enabling)
Data
Input
V
I
V
V
M
M
V
M
V
M
0 V
0 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
t
t
PLZ
PZL
Output
Waveform 1
S1 at V
LOAD
(see Note B)
V
V
/2
LOAD
V
I
V
M
Input
V
M
V
M
V + V
∆
OL
0 V
OL
t
t
PZH
PHZ
t
t
PHL
PLH
Output
Waveform 2
S1 at GND
V
OH
V
V
OH
V
OH
− V
∆
V
M
Output
V
M
V
M
0 V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω.
O
D. The outputs are measured one at a time, with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
are the same as t
.
dis
.
PLZ
PZL
PLH
PHZ
are the same as t
PZH
en
are the same as t .
PHL pd
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
7
PACKAGE OPTION ADDENDUM
www.ti.com
6-Aug-2007
PACKAGING INFORMATION
Orderable Device
74ALVCH16244DGGRE4
74ALVCH16244DGGRG4
74ALVCH16244DGVRE4
74ALVCH16244DGVRG4
74ALVCH16244DLG4
74ALVCH16244DLRG4
74ALVCH16244GRDR
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
TSSOP
DGG
48
48
48
48
48
48
54
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TSSOP
TVSOP
TVSOP
SSOP
DGG
DGV
DGV
DL
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SSOP
DL
1000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
BGA MI
CROSTA
R JUNI
OR
GRD
1000
TBD
SNPB
Level-1-240C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
74ALVCH16244ZQLR
74ALVCH16244ZRDR
ACTIVE
ACTIVE
BGA MI
CROSTA
R JUNI
OR
ZQL
ZRD
56
54
1000 Green (RoHS &
no Sb/Br)
SNAGCU
SNAGCU
BGA MI
CROSTA
R JUNI
OR
1000 Green (RoHS &
no Sb/Br)
SN74ALVCH16244DGGR
SN74ALVCH16244DGVR
SN74ALVCH16244DL
SN74ALVCH16244DLR
SN74ALVCH16244KR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
NRND
TSSOP
TVSOP
SSOP
DGG
DGV
DL
48
48
48
48
56
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SSOP
DL
1000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
BGA MI
CROSTA
R JUNI
OR
GQL
1000
TBD
SNPB
Level-1-240C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
6-Aug-2007
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
4-Oct-2007
TAPE AND REEL BOX INFORMATION
Device
Package Pins
Site
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) (mm) Quadrant
(mm)
330
330
330
330
330
330
330
(mm)
16
74ALVCH16244GRDR
74ALVCH16244ZQLR
74ALVCH16244ZRDR
GRD
ZQL
ZRD
54
56
54
48
48
48
56
SITE 32
SITE 32
SITE 32
SITE 41
SITE 41
SITE 41
SITE 32
5.8
4.8
8.3
7.3
1.55
1.45
1.55
1.8
8
8
16
16
16
24
24
32
16
Q1
Q1
Q1
Q1
Q1
Q1
Q1
16
16
5.8
8.3
8
SN74ALVCH16244DGGR DGG
SN74ALVCH16244DGVR DGV
24
8.6
15.8
10.1
16.2
7.3
12
12
16
8
24
6.8
1.6
SN74ALVCH16244DLR
SN74ALVCH16244KR
DL
32
11.35
4.8
3.1
GQL
16
1.45
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
4-Oct-2007
Device
Package
Pins
Site
Length (mm) Width (mm) Height (mm)
74ALVCH16244GRDR
74ALVCH16244ZQLR
74ALVCH16244ZRDR
SN74ALVCH16244DGGR
SN74ALVCH16244DGVR
SN74ALVCH16244DLR
SN74ALVCH16244KR
GRD
ZQL
ZRD
DGG
DGV
DL
54
56
54
48
48
48
56
SITE 32
SITE 32
SITE 32
SITE 41
SITE 41
SITE 41
SITE 32
346.0
346.0
346.0
346.0
346.0
346.0
346.0
346.0
346.0
346.0
346.0
346.0
346.0
346.0
33.0
33.0
33.0
41.0
41.0
49.0
33.0
GQL
Pack Materials-Page 2
MECHANICAL DATA
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
0,23
0,13
M
0,07
0,40
24
13
0,16 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
0°–ā8°
0,75
1
12
0,50
A
Seating Plane
0,08
0,15
0,05
1,20 MAX
PINS **
14
16
20
24
38
48
56
DIM
A MAX
A MIN
3,70
3,50
3,70
3,50
5,10
4,90
5,10
4,90
7,90
7,70
9,80
9,60
11,40
11,20
4073251/E 08/00
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
D. Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MSSO001C – JANUARY 1995 – REVISED DECEMBER 2001
DL (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0.025 (0,635)
48
0.0135 (0,343)
0.008 (0,203)
0.005 (0,13)
M
25
0.010 (0,25)
0.005 (0,13)
0.299 (7,59)
0.291 (7,39)
0.420 (10,67)
0.395 (10,03)
Gage Plane
0.010 (0,25)
0°–ā8°
1
24
0.040 (1,02)
0.020 (0,51)
A
Seating Plane
0.004 (0,10)
0.008 (0,20) MIN
PINS **
0.110 (2,79) MAX
28
48
0.630
56
DIM
0.380
(9,65)
0.730
A MAX
A MIN
(16,00) (18,54)
0.370
(9,40)
0.620
0.720
(15,75) (18,29)
4040048/E 12/01
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
D. Falls within JEDEC MO-118
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUARY 1998
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0,27
0,17
M
0,08
0,50
48
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
0,25
1
24
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
48
56
64
DIM
A MAX
12,60
12,40
14,10
13,90
17,10
16,90
A MIN
4040078/F 12/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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