74CB3T1G125DCKRG4 [TI]
具有电平转换器的 3.3V、1:1 (SPST)、单通道 FET 总线开关 | DCK | 5 | -40 to 85;型号: | 74CB3T1G125DCKRG4 |
厂家: | TEXAS INSTRUMENTS |
描述: | 具有电平转换器的 3.3V、1:1 (SPST)、单通道 FET 总线开关 | DCK | 5 | -40 to 85 开关 驱动 总线驱动器 总线收发器 转换器 电平转换器 |
文件: | 总12页 (文件大小:193K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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ꢀꢌ ꢁꢉ ꢍ ꢎ ꢏ ꢎꢇ ꢅꢐ ꢀ ꢀ ꢑꢌ ꢇꢄ ꢒ
ꢌꢇ ꢒ ꢋ ꢔꢕ ꢇꢗ ꢍ ꢎꢙꢘꢁꢇ ꢍ ꢎꢕꢎ ꢍ ꢀ ꢒꢌ ꢏꢇ ꢎꢙ
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SCDS150 − OCTOBER 2003
D
D
Output Voltage Translation Tracks V
D
D
V
Operating Range From 2.3 V to 3.6 V
CC
CC
Supports Mixed-Mode Signal Operation On
All Data I/O Ports
− 5-V Input Down To 3.3-V Output Level
Data I/Os Support 0 to 5-V Signaling Levels
(0.8-V, 1.2-V, 1.5-V, 1.8-V, 2.5-V, 3.3-V, 5-V)
D
D
D
D
Control Inputs Can be Driven by TTL or
5-V/3.3-V CMOS Outputs
Shift With 3.3-V V
CC
− 5-V/3.3-V Input Down To 2.5-V Output
Level Shift With 2.5-V V
I
Supports Partial-Power-Down Mode
off
CC
Operation
D
D
D
D
D
D
5-V Tolerant I/Os With Device Powered-Up
or Powered-Down
Latch-Up Performance Exceeds 250 mA Per
JESD 17
Bidirectional Data Flow, With Near-Zero
Propagation Delay
ESD Performance Tested Per JESD 22
− 2000-V Human-Body Model
(A114-B, Class II)
Low ON-State Resistance (r
)
on
Characteristics (r = 5 Ω Typical)
on
− 1000-V Charged-Device Model (C101)
Low Input/Output Capacitance Minimizes
D
D
Supports Digital Applications: Level
Translation, USB Interface, Bus Isolation
Loading (C
= 5 pF Typical)
io(OFF)
Data and Control Inputs Provide
Undershoot Clamp Diodes
Ideal for Low-Power Portable Equipment
Low Power Consumption
(I
= 20 µA Max)
CC
DBV OR DCK PACKAGE
(TOP VIEW)
1
2
3
5
4
OE
A
GND
V
B
CC
description/ordering information
The SN74CB3T1G125 is a high-speed TTL-compatible FET bus switch with low ON-state resistance (r ),
on
allowing for minimal propagation delay. The device fully supports mixed-mode signal operation on all data I/O
ports by providing voltage translation that tracks V . The SN74CB3T1G125 supports systems using 5-V TTL,
CC
3.3-V LVTTL, and 2.5-V CMOS switching standards, as well as user-defined switching levels (see Figure 1).
The SN74CB3T1G125 is a 1-bit bus switch with a single ouput-enable (OE) input. When OE is low, the bus
switch is ON, and the A port is connected to the B port, allowing bidirectional data flow between ports. When
OE is high, the bus switch is OFF, and a high-impedance state exists between the A and B ports.
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
PACKAGE
T
A
‡
SOT (SOT-23) − DBV
SOT (SC-70) − DCK
Tape and reel
Tape and reel
SN74CB3T1G125DBVR
SN74CB3T1G125DCKR
W25_
−40°C to 85°C
WM_
†
‡
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
The actual top-side marking has one additional character that designates the assembly/test site.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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Copyright 2003, Texas Instruments Incorporated
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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SCDS150 − OCTOBER 2003
description/ordering information (continued)
V
CC
5.5 V
V
≈V
≈V
CC
IN
OUT
CC
≈V
CC
− 1 V
− 1 V
CC
CB3T
0 V
0 V
Input Voltages
Output Voltages
NOTE A: If the input high voltage (V ) level is greater than or equal to V
IH CC
− 1 V, and less than or equal to 5.5 V, then the output high voltage
(V
) level will be equal to approximately the V voltage level.
OH
CC
Figure 1. Typical DC Voltage-Translation Characteristics
This device is fully specified for partial-power-down applications using I . The I feature ensures that
off
off
damaging current will not backflow through the device when it is powered down. The device has isolation during
power off.
To ensure the high-impedance state during power up or power down, OE should be tied to V
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
through a pullup
CC
FUNCTION TABLE
INPUT INPUT/OUTPUT
FUNCTION
OE
L
A
B
Z
A port = B port
Disconnect
H
logic diagram (positive logic)
2
1
4
A
SW
B
OE
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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ꢊ ꢓ ꢋ ꢔꢕꢖ ꢆ ꢓ ꢆ ꢔꢕ ꢍꢗ ꢑꢔꢕ ꢗꢍꢇꢘꢉ ꢎ ꢅꢐꢀ ꢀꢑ ꢌ ꢇꢄ ꢒ ꢑ ꢌꢇ ꢒ ꢋ ꢔꢕ ꢇꢗ ꢍ ꢎꢙꢘꢁꢇ ꢍ ꢎꢕꢎ ꢍ ꢀ ꢒꢌ ꢏꢇ ꢎꢙ
SCDS150 − OCTOBER 2003
simplified schematic, each FET switch (SW)
†
Gate Voltage (V
)
is approximately
G
equal to V
and V > V
CC
+ V when the switch is ON
+ V .
T
CC
T
I
A
B
†
V
G
Control
Circuit
‡
EN
‡
EN is the internal enable signal applied to the switch.
§
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
CC
Control input voltage range, V (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Switch I/O voltage range, V (see Notes 1, 2, and 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Control input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
IN
I/O
IK IN
I/O port clamp current, I
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
I/OK I/O
ON-state switch current, I (see Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Continuous current through V
I/O
or GND terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA
CC
Package thermal impedance, θ (see Note 5): DBV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206°C/W
JA
DCK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252°C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Storage temperature range, T
stg
§
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltages are with respect to ground unless otherwise specified.
2. The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
3. V and V are used to denote specific conditions for V
.
I
O
I/O
4. I and I are used to denote specific conditions for I .
I
O
I/O
5. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 6)
MIN
2.3
1.7
2
MAX
3.6
5.5
5.5
0.7
0.8
5.5
85
UNIT
V
V
Supply voltage
V
CC
V
CC
V
CC
V
CC
V
CC
= 2.3 V to 2.7 V
= 2.7 V to 3.6 V
= 2.3 V to 2.7 V
= 2.7 V to 3.6 V
High-level control input voltage
V
V
IH
0
V
V
Low-level control input voltage
IL
0
Data input/output voltage
0
V
I/O
T
A
Operating free-air temperature
−40
°C
NOTE 6: All unused control inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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ꢊꢓ ꢋꢔꢕ ꢖꢆ ꢓ ꢆ ꢔꢕ ꢍ ꢗꢑꢔꢕ ꢗꢍꢇꢘꢉ ꢎ ꢅꢐ ꢀ ꢀ ꢑꢌ ꢇ ꢄꢒ ꢑ ꢌꢇ ꢒ ꢋ ꢔꢕ ꢇꢗ ꢍꢎ ꢙꢘꢁꢇ ꢍ ꢎꢕꢎ ꢍ ꢀꢒꢌ ꢏ ꢇꢎ ꢙ
SCDS150 − OCTOBER 2003
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
†
PARAMETER
TEST CONDITIONS
MIN TYP
MAX
UNIT
V
= 3 V,
CC
V
V
−1.2
V
IK
I = −18 mA
I
See Figures 3 and 4
OH
V
V
= 3.6 V,
= 3.6 V to 5.5 V or GND
CC
IN
I
Control inputs
10
µA
µA
IN
V = V
CC
− 0.7 V to 5.5 V
− 0.7 V
20
−40
5
I
V
CC
= 3.6 V,
V = 0.7 V to V
I CC
Switch ON,
I
I
V
IN
= V
or GND
CC
V = 0 to 0.7 V
I
V
V
= 3.6 V,
= 0 to 5.5 V,
CC
O
‡
V = 0,
I
10
10
µA
I
OZ
Switch OFF,
V
= V or GND
CC
IN
V
V
= 0,
CC
= 0 to 5.5 V,
I
I
µA
µA
off
O
V = 0,
I
V
= 3.6 V,
CC
= 0,
V = V
CC
or GND
20
20
I
I
I/O
Switch ON or OFF,
CC
V = 5.5 V
I
V
IN
= V
or GND
CC
V
= 3 V to 3.6 V,
CC
§
∆I
CC
Control inputs One input at V
− 0.6 V,
300
µA
CC
Other inputs at V
or GND
CC
V
V
= 3.3 V,
CC
IN
C
C
Control inputs
3
pF
in
= V
or GND
CC
V
CC
V
I/O
= 3.3 V,
= 5.5 V, 3.3 V, or GND,
5
4
pF
pF
io(OFF)
io(ON)
Switch OFF,
V
IN
= V
or GND
CC
V
CC
= 3.3 V,
V
V
I
= 5.5 V or 3.3 V
= GND
I/O
Switch ON,
C
12
5
V
IN
= V
or GND
I/O
CC
V
= 2.3 V,
= 24 mA
8
8
CC
O
TYP at V
= 2.5 V,
CC
I
O
= 16 mA
5
V = 0
I
¶
Ω
r
on
I
I
= 64 mA
= 32 mA
5
5
7
7
V
= 3 V,
O
CC
V = 0
I
O
V
†
‡
§
¶
and I refer to control inputs. V , V , I , and I refer to data pins.
IN
IN
I
O
I
O
All typical values are at V
= 3.3 V (unless otherwise noted), T = 25°C.
CC
For I/O ports, the parameter I
A
includes the input leakage current.
OZ
This is the increase in supply current for each input that is at the specified TTL voltage level, rather than V
or GND.
CC
Measured by the voltage drop between A and B terminals at the indicated current through the switch. ON-state resistance is determined by the
lower of the voltages of the two (A or B) terminals.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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ꢀꢌ ꢁꢉ ꢍ ꢎ ꢏ ꢎꢇ ꢅꢐ ꢀ ꢀ ꢑꢌ ꢇꢄ ꢒ
ꢊ ꢓ ꢋ ꢔꢕꢖ ꢆ ꢓ ꢆ ꢔꢕ ꢍꢗ ꢑꢔꢕ ꢗꢍꢇꢘꢉ ꢎ ꢅꢐꢀ ꢀꢑ ꢌ ꢇꢄ ꢒ ꢑ ꢌꢇ ꢒ ꢋ ꢔꢕ ꢇꢗ ꢍ ꢎꢙꢘꢁꢇ ꢍ ꢎꢕꢎ ꢍ ꢀ ꢒꢌ ꢏꢇ ꢎꢙ
SCDS150 − OCTOBER 2003
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figure 2)
V
= 2.5 V
V
= 3.3 V
CC
0.2 V
CC
0.3 V
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN MAX
MIN MAX
†
t
t
t
A or B
OE
B or A
A or B
A or B
0.15
7.5
0.25
6.5
6
ns
ns
ns
pd
en
1
1
1
1
OE
5.5
dis
†
The propagation delay is the calculated RC time constant of the typical ON-state resistance of the switch and the specified load capacitance,
when driven by an ideal voltage source (zero output impedance).
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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SCDS150 − OCTOBER 2003
PARAMETER MEASUREMENT INFORMATION
V
CC
Input Generator
V
IN
50 Ω
50 Ω
V
G1
TEST CIRCUIT
DUT
2 × V
CC
Open
Input Generator
50 Ω
S1
R
V
V
O
L
I
GND
50 Ω
V
G2
C
R
L
L
(see Note A)
S1
V
I
V
∆
C
R
V
CC
TEST
L
L
2.5 V 0.2 V
3.3 V 0.3 V
Open
Open
500 Ω
500 Ω
3.6 V or GND
5.5 V or GND
30 pF
50 pF
t
pd(s)
2.5 V 0.2 V
3.3 V 0.3 V
2 × V
2 × V
500 Ω
500 Ω
GND
GND
30 pF
50 pF
0.15 V
0.3 V
CC
CC
t
/t
PLZ PZL
2.5 V 0.2 V
3.3 V 0.3 V
Open
Open
500 Ω
500 Ω
3.6 V
5.5 V
30 pF
50 pF
0.15 V
0.3 V
t
/t
PHZ PZH
Output
Control
V
CC
V
CC
/2
V
CC
/2
(V
IN
)
0 V
t
t
PLZ
PZL
Output
Waveform 1
V
V
CC
Output
Control
V
CC
V
/2
CC
S1 at 2 × V
(see Note B)
V
V
+ V
V
CC
/2
V
CC
/2
CC
OL
∆
(V
IN
)
OL
0 V
t
t
PZH
PHZ
t
t
PLH
PHL
Output
Waveform 2
S1 at Open
(see Note B)
V
OH
V
OH
− V
OH
∆
V
/2
Output
CC
V
CC
/2
V
CC
/2
0 V
V
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES (t
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
)
pd(s)
C includes probe and jig capacitance.
L
NOTES: B.
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
D. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
E. The outputs are measured one at a time with one transition per measurement.
F.
G.
H.
t
t
t
and t
and t
and t
are the same as t
are the same as t
are the same as t
.
.
PLZ
PZL
PLH
PHZ
PZH
PHL
dis
en
. The tpd propagation delay is the calculated RC time constant of the typical ON-state
pd(s)
resistance of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance).
I. All parameters and waveforms are not applicable to all devices.
Figure 2. Test Circuit and Voltage Waveforms
6
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ꢀꢁꢂ ꢃ ꢄ ꢅꢆ ꢇꢈ ꢉꢈ ꢊꢋ
ꢀꢌ ꢁꢉ ꢍ ꢎ ꢏ ꢎꢇ ꢅꢐ ꢀ ꢀ ꢑꢌ ꢇꢄ ꢒ
ꢊ ꢓ ꢋ ꢔꢕꢖ ꢆ ꢓ ꢆ ꢔꢕ ꢍꢗ ꢑꢔꢕ ꢗꢍꢇꢘꢉ ꢎ ꢅꢐꢀ ꢀꢑ ꢌ ꢇꢄ ꢒ ꢑ ꢌꢇ ꢒ ꢋ ꢔꢕ ꢇꢗ ꢍ ꢎꢙꢘꢁꢇ ꢍ ꢎꢕꢎ ꢍ ꢀ ꢒꢌ ꢏꢇ ꢎꢙ
SCDS150 − OCTOBER 2003
TYPICAL CHARACTERISTICS
OUTPUT VOLTAGE
vs
OUTPUT VOLTAGE
vs
INPUT VOLTAGE
INPUT VOLTAGE
4.0
3.0
2.0
1.0
0.0
4.0
3.0
2.0
1.0
0.0
V
= 2.3 V
V
= 3 V
CC
= 1 µA
CC
I
T
I
= 1 µA
T = 25°C
A
O
A
O
= 25°C
2.0
4.0
6.0
1.0
3.0
5.0
0.0
0.0
1.0
2.0
3.0
4.0
5.0
6.0
V − Input Voltage − V
I
V − Input Voltage − V
I
Figure 3. Data Output Voltage vs Data Input Voltage
7
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ꢀ ꢁꢂ ꢃꢄ ꢅ ꢆꢇ ꢈ ꢉꢈꢊꢋ
ꢀ ꢌꢁ ꢉꢍ ꢎ ꢏ ꢎꢇ ꢅ ꢐ ꢀ ꢀ ꢑꢌ ꢇ ꢄꢒ
ꢊꢓ ꢋꢔꢕ ꢖꢆ ꢓ ꢆ ꢔꢕ ꢍ ꢗꢑꢔꢕ ꢗꢍꢇꢘꢉ ꢎ ꢅꢐ ꢀ ꢀ ꢑꢌ ꢇ ꢄꢒ ꢑ ꢌꢇ ꢒ ꢋ ꢔꢕ ꢇꢗ ꢍꢎ ꢙꢘꢁꢇ ꢍ ꢎꢕꢎ ꢍ ꢀꢒꢌ ꢏ ꢇꢎ ꢙ
SCDS150 − OCTOBER 2003
TYPICAL CHARACTERISTICS (continued)
OUTPUT VOLTAGE HIGH
vs
OUTPUT VOLTAGE HIGH
vs
SUPPLY VOLTAGE
SUPPLY VOLTAGE
4.0
3.5
4.0
3.5
3.0
2.5
2.0
1.5
V
= 2.3 V to 3.6 V
V
= 2.3 V to 3.6 V
CC
V = 5.5 V
CC
V = 5.5 V
I
I
100 µA
100 µA
T
= 85°C
T
= 25°C
A
A
8 mA
16 mA
24 mA
8 mA
16 mA
24 mA
3.0
2.5
2.0
1.5
2.3
2.5
2.7
CC
2.9
3.1
3.3
3.5
3.7
2.3
2.5
2.7
2.9
3.1
3.3
3.5
3.7
V
− Supply Voltage − V
V
− Supply Voltage − V
CC
OUTPUT VOLTAGE HIGH
vs
SUPPLY VOLTAGE
4.0
3.5
3.0
2.5
2.0
1.5
V
= 2.3 V to 3.6 V
CC
V = 5.5 V
I
A
100 µA
8 mA
16 mA
24 mA
T
= −40°C
3.3
− Supply Voltage − V
2.3
2.5
2.7
2.9
3.1
3.5
3.7
V
CC
Figure 4. V
Values
OH
8
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PACKAGE OPTION ADDENDUM
www.ti.com
25-Feb-2005
PACKAGING INFORMATION
Orderable Device
SN74CB3T1G125DBVR
SN74CB3T1G125DCKR
Status (1)
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SOT-23
DBV
5
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SC70
DCK
5
3000
Pb-Free
(RoHS)
CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional
product content details.
None: Not yet available Lead (Pb-Free).
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,
including bromine (Br) or antimony (Sb) above 0.1% of total product weight.
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MPDS025C – FEBRUARY 1997 – REVISED FEBRUARY 2002
DCK (R-PDSO-G5)
PLASTIC SMALL-OUTLINE PACKAGE
0,30
0,15
M
0,10
0,65
5
4
0,13 NOM
1,40 2,40
1,10 1,80
1
3
Gage Plane
2,15
1,85
0,15
0°–8°
0,46
0,26
Seating Plane
0,10
1,10
0,80
0,10
0,00
4093553-2/D 01/02
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion.
D. Falls within JEDEC MO-203
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