74CBTLV3384PWRE4 [TI]
LOW-VOLTAGE 10-BIT FET BUS SWITCH; 低电压10位FET总线开关
| 型号： | 74CBTLV3384PWRE4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | LOW-VOLTAGE 10-BIT FET BUS SWITCH |
| 文件： | 总9页 (文件大小：227K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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ꢇ ꢋꢌꢍꢈꢋ ꢇꢆꢎꢏ ꢐ ꢑ ꢒ ꢍꢅꢓ ꢆ ꢔ ꢐꢆ ꢅꢕ ꢀ ꢀ ꢌꢓ ꢆꢄ ꢖ
SCDS059G − MARCH 1998 − REVISED JUNE 2004
DBQ, DGV, DW, OR PW PACKAGE
(TOP VIEW)
D
D
D
D
D
5-Ω Switch Connection Between Two Ports
Rail-to-Rail Switching on Data I/O Ports
I
Supports Partial-Power-Down Mode
1OE
1B1
1A1
1A2
1B2
1B3
1A3
1A4
1B4
1B5
1A5
GND
V
CC
1
24
23
22
21
20
19
18
17
16
off
Operation
2B5
2A5
2A4
2B4
2B3
2A3
2A2
2B2
2
3
Latch-Up Performance Exceeds 250 mA Per
JESD 17
4
5
ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
6
7
8
9
description/ordering information
10
11
12
15 2B1
The SN74CBTLV3384 provides ten bits of
high-speed bus switching. The low on-state
resistance of the switch allows connections to be
made with minimal propagation delay.
2A1
2OE
14
13
The device is organized as dual 5-bit bus switches
with separate output-enable (OE) inputs. It can be
used as two 5-bit bus switches or one 10-bit bus switch. When OE is low, the associated 5-bit bus switch is on,
and A port is connected to B port. When OE is high, the switch is open, and the high-impedance state exists
between the two ports.
This device is fully specified for partial-power-down applications using I . The I feature ensures that
off
off
damaging current will not backflow through the device when it is powered down. The device has isolation during
power off.
To ensure the high-impedance state during power up or power down, OE shall be tied to V
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
through a pullup
CC
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
PACKAGE
T
A
QSOP − DBQ
SOIC − DW
Tape and reel
Tube
SN74CBTLV3384DBQR
SN74CBTLV3384DW
SN74CBTLV3384DWR
SN74CBTLV3384PWR
SN74CBTLV3384DGVR
CBTLV3384
CBTLV3384
−40°C to 85°C
Tape and reel
Tape and reel
Tape and reel
TSSOP − PW
TVSOP − DGV
CL384
CL384
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
FUNCTION TABLE
(each 5-bit bus switch)
INPUTS
INPUTS/OUTPUTS
1OE
2OE
L
1B1−1B5
1A1−1A5
1A1−1A5
Z
2B1−2B5
2A1−2A5
Z
L
L
H
H
H
L
2A1−2A5
Z
H
Z
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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Copyright 2004, Texas Instruments Incorporated
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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SCDS059G − MARCH 1998 − REVISED JUNE 2004
logic diagram (positive logic)
3
2
1A1
1A5
1B1
1B5
SW
SW
11
10
1
1OE
2A1
14
15
23
2B1
2B5
SW
SW
22
13
2A5
2OE
simplified schematic, each FET switch
A
B
(OE)
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V
I
Continuous channel current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
IK I/O
Package thermal impedance, θ (see Note 2): DBQ package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61°C/W
JA
DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W
DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
2
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SCDS059G − MARCH 1998 − REVISED JUNE 2004
recommended operating conditions (see Note 3)
MIN
2.3
1.7
2
MAX
UNIT
V
V
Supply voltage
3.6
V
CC
V
= 2.3 V to 2.7 V
= 2.7 V to 3.6 V
= 2.3 V to 2.7 V
= 2.7 V to 3.6 V
CC
CC
CC
CC
High-level control input voltage
V
IH
V
V
V
0.7
0.8
85
V
IL
Low-level control input voltage
Operating free-air temperature
V
T
A
−40
°C
NOTE 3: All unused control inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
†
PARAMETER
TEST CONDITIONS
I = −18 mA
MIN TYP
MAX
−1.2
1
UNIT
V
V
V
V
V
V
V
= 3 V,
IK
CC
CC
CC
CC
CC
I
I
I
I
= 3.6 V,
= 0,
V = V
I CC
or GND
µA
µA
µA
µA
pF
I
V or V = 0 to 3.6 V
10
off
I
O
= 3.6 V,
= 3.6 V,
I
O
= 0,
V = V
I CC
or GND
10
CC
‡
∆I
CC
Control inputs
One input at 3 V,
Other inputs at V
CC
or GND
300
C
C
Control inputs V = 3 V or 0
4.5
10
5
i
I
V
O
= 3 V or 0,
OE = V
CC
pF
io(OFF)
I = 64 mA
8
8
I
V = 0
I
V
CC
= 2.3 V,
I = 24 mA
I
5
TYP at V
CC
= 2.5 V
V = 1.7 V,
I
I = 15 mA
I
27
5
40
7
§
on
Ω
r
I = 64 mA
I
V = 0
I
V
CC
= 3 V
I = 24 mA
I
5
7
V = 2.4 V,
I
I = 15 mA
I
10
15
†
‡
§
All typical values are at V
This is the increase in supply current for each input that is at the specified voltage level, rather than V
Measured by the voltage drop between the A and B terminals at the indicated current through the switch. On-state resistance is determined by
the lower of the voltages of the two (A or B) terminals.
= 3.3 V (unless otherwise noted), T = 25°C.
A
CC
or GND.
CC
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figure 1)
V
= 2.5 V
V
= 3.3 V
CC
0.2 V
CC
0.3 V
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN MAX
MIN MAX
¶
t
t
t
A or B
OE
B or A
A or B
A or B
0.15
5
0.25
4.3
ns
ns
ns
pd
en
1
1
1
1
5.5
5.5
OE
dis
¶
The propagation delay is the calculated RC time constant of the typical on-state resistance of the switch and the specified load capacitance, when
driven by an ideal voltage source (zero output impedance).
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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SCDS059G − MARCH 1998 − REVISED JUNE 2004
PARAMETER MEASUREMENT INFORMATION
2 × V
CC
TEST
S1
S1
t
/t
Open
Open
R
PLH PHL
L
From Output
Under Test
t
/t
2 × V
CC
GND
PLZ PZL
GND
t
/t
PHZ PZH
C
L
R
L
(see Note A)
C
V
∆
R
V
CC
L
L
2.5 V 0.2 V
3.3 V 0.3 V
500 Ω
500 Ω
0.15 V
0.3 V
30 pF
50 pF
LOAD CIRCUIT
V
CC
Timing Input
V
CC
/2
0 V
t
w
t
t
h
su
V
CC
V
CC
V
CC
/2
V
CC
/2
Input
V
CC
/2
V
CC
/2
Data Input
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
V
V
CC
CC
Output
Control
V
CC
/2
V
CC
/2
V
CC
/2
V
/2
Input
CC
0 V
V
0 V
t
t
t
t
t
PZL
PLZ
+ V
PHL
PLH
Output
Waveform 1
V
V
OH
CC
V
V
/2
/2
V
CC
/2
V
CC
/2
/2
Output
CC
S1 at 2 × V
(see Note B)
CC
V
OL
∆
V
OL
OL
t
t
t
PHL
PLH
/2
PZH
PHZ
− V
Output
Waveform 2
S1 at GND
V
V
V
OH
OH
V
OH
∆
V
CC
V
CC
CC
Output
≈0 V
(see Note B)
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A.
C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2 ns, t ≤ 2 ns.
O
r
f
D. The outputs are measured one at a time, with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
are the same as t
.
.
PLZ
PZL
PLH
PHZ
PZH
PHL
dis
are the same as t
en
are the same as t .
pd
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
0,23
0,13
M
0,07
0,40
24
13
0,16 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
0°–ā8°
0,75
1
12
0,50
A
Seating Plane
0,08
0,15
0,05
1,20 MAX
PINS **
14
16
20
24
38
48
56
DIM
A MAX
A MIN
3,70
3,50
3,70
3,50
5,10
4,90
5,10
4,90
7,90
7,70
9,80
9,60
11,40
11,20
4073251/E 08/00
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
D. Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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MSOI004E JANUARY 1995 − REVISED MAY 2002
DBQ (R−PDSO−G**)
PLASTIC SMALL−OUTLINE PACKAGE
0.012 (0,30)
0.008 (0,20)
0.025 (0,64)
24
0.005 (0,13)
13
0.157 (3,99) 0.244 (6,20)
0.150 (3,81) 0.228 (5,80)
0.008 (0,20) NOM
Gauge Plane
1
12
A
0.010 (0,25)
0°−8°
0.035 (0,89)
0.016 (0,40)
0.069 (1,75) MAX
Seating Plane
0.004 (0,10)
0.010 (0,25)
0.004 (0,10)
PINS **
16
20
24
28
DIM
0.197
(5,00)
0.344
(8,74)
0.344
(8,74)
0.394
(10,01)
A MAX
A MIN
0.189
(4,80)
0.337
(8,56)
0.337
(8,56)
0.386
(9,80)
M0−137
VARIATION
D
AB
AD
AE
AF
4073301/F 02/2002
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
D. Falls within JEDEC MO−137.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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Copyright 2004, Texas Instruments Incorporated
相关型号：
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