74HC4538 [TI]
High Speed CMOS Logic Dual Retriggerable Precision Monostable Multivibrator; 高速CMOS逻辑双路可重触发精密单稳多谐振荡器
| 型号： | 74HC4538 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | High Speed CMOS Logic Dual Retriggerable Precision Monostable Multivibrator |
| 文件： | 总11页 (文件大小：66K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CD54HC4538, CD74HC4538,
CD74HCT4538
Data sheet acquired from Harris Semiconductor
SCHS123
High Speed CMOS Logic Dual Retriggerable
Precision Monostable Multivibrator
June 1998
Features
Description
• Retriggerable/Resettable Capability
The
Harris
CD54HC4538,
CD74HC4538
and
CD74HCT4538 are dual retriggerable/resettable monostable
precision multivibrators for fixed voltage timing applications.
• Trigger and Reset Propagation Delays Independent of
[ /Title
(CD54
HC453
8,
CD74
HC453
8,
CD74
HCT45
38)
/Sub-
ject
R , C
X
X
An external resistor (R ) and an external capacitor (C )
X
X
control the timing and the accuracy for the circuit.
• Triggering from the Leading or Trailing Edge
• Q and Q Buffered Outputs Available
• Separate Resets
Adjustment of R and C provides a wide range of output
X
X
pulse widths from the Q and Q terminals. The propagation
delay from trigger input-to-output transition and the
propagation delay from reset input-to-output transition are
• Wide Range of Output-Pulse Widths
• Schmitt Trigger Input on A and B Inputs
independent of R and C .
X
X
Leading-edge triggering (A) and trailing edge triggering (B)
inputs are provided for triggering from either edge of the
input pulse. An unused “A” input should be tied to GND and
• Retrigger Time is Independent of C
X
• Fanout (Over Temperature Range)
an unused B should be tied to V . On power up the IC is
CC
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads reset. Unused resets and sections must be terminated. In
normal operation the circuit retriggers on the application of
each new trigger pulse. To operate in the non-triggerable
mode Q is connected to B when leading edge triggering (A)
is used or Q is connected to A when trailing edge triggering
(B) is used. The period (τ) can be calculated from τ = (0.7)
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
o
o
• Wide Operating Temperature Range . . . -55 C to 125 C
• Balanced Propagation Delay and Transition Times
(High
Speed
CMOS
Logic
• Significant Power Reduction Compared to LSTTL
Logic ICs
R , C ; R
is 5kΩ. C
is 0pF.
X
X
MIN
MIN
Ordering Information
• HC Types
- 2V to 6V Operation
TEMP. RANGE
o
PKG.
NO.
- High Noise Immunity: N = 30%, N = 30% of V
IL IH CC
PART NUMBER
CD54HC4538F
CD74HC4538E
CD74HCT4538E
CD74HC4538M
CD74HCT4538M
NOTES:
( C)
PACKAGE
at V
= 5V
CC
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
16 Ld CERDIP F16.3
• HCT Types
16 Ld PDIP
16 Ld PDIP
16 Ld SOIC
16 Ld SOIC
E16.3
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
E16.3
V = 0.8V (Max), V = 2V (Min)
IL IH
M16.15
M16.15
- CMOS Input Compatibility, I ≤ 1µA at V , V
l
OL OH
Pinout
1. When ordering, use the entire part number. Add the suffix 96 to
obtain the variant in the tape and reel.
CD54HC4538, CD74HC4538, CD74HCT4538
(PDIP, SOIC, CERDIP)
TOP VIEW
2. Wafer and die for this part number is available which meets all
electrical specifications. Please contact your local sales office or
Harris customer service for ordering information.
1C
1
2
3
4
5
6
7
8
16 V
CC
X
1R C
15 2C
X
X
X
1R
1A
14 2R C
X
X
13 2R
12 2A
11 2B
10 2Q
1B
1Q
1Q
9
2Q
GND
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
File Number 1671.2
Copyright © Harris Corporation 1998
1
CD54HC4538, CD74HC4538, CD74HCT4538
Functional Diagram
1Cx
1Rx
V
CC
1
2
1Cx
1RxCx
6
7
4
1A
1Q
1Q
MONO 1
5
3
1B
1R
13
12
2R
2A
10
9
2Q
2Q
MONO 2
11
2B
2Cx
2RxCx
14
15
V
GND = 8
= 16
CC
V
2Cx
2Rx
CC
TRUTH TABLE
R2
INPUTS
OUTPUTS
CL
R1
Q
R
L
A
X
H
X
L
B
X
X
L
Q
L
L
L
Q
H
H
H
CL
p
n
D
X
X
H
CL
CL
Q
p
n
CL
↓
p
n
CL
R1
H
↑
H
CL
NOTE: H = High Level, L = Low Level, ↑ = Transition from Low to
High, ↓ = Transition from High to Low,
One High Level Pulse,
FIGURE 1. FF DETAIL
One Low Level Pulse, X = Irrelevant.
2
CD54HC4538, CD74HC4538, CD74HCT4538
16
V
CC
V
V
CC
CC
V
CC
R
C
X
X
2(14)
COMP II
6(10)
+
R1
Q
Q
1(15)
-
R2
V
CC
7(9)
V
8
CC
HIGH Z
3(13)
R
V
CC
4(12)
5(11)
D R1
CL
R2
Q
Q
A
B
FF
CL
FIGURE 2. LOGIC DIAGRAM (1 MONO)
FUNCTIONAL TERMINAL CONNECTIONS
V
TO
GND TO
TERMINAL NUMBER
INPUT PULSE TO
TERMINAL NUMBER
OTHER
CONNECTIONS
CC
TERMINAL NUMBER
FUNCTION
MONO
MONO
MONO
MONO
MONO
MONO
MONO
MONO
2
1
2
1
2
1
2
1
Leading-Edge
3, 5
11, 13
4
12
Trigger/Retriggerable
Leading-Edge
Trigger/Non-Retriggerable
3
3
3
13
4
5
5
12
11
11
5-7
11-9
Trailing-Edge
Trigger/Retriggerable
13
4
12
Trailing-Edge
13
4-6
12-10
Trigger/Non-Retriggerable
NOTES:
3. A retriggerable one-shot multivibrator has an output pulse width which is extended one full time period (T) after application of the last
trigger pulse.
4. A non-triggerable one-shot multivibrator has a time period (T) referenced from the application of the first trigger pulse.
T
T
FIGURE 3. INPUT PULSE TRAIN
FIGURE 4. RETRIGGERABLE MODE
PULSE WIDTH (A MODE)
FIGURE5. NON-RETRIGGERABLEMODE
PULSE WIDTH
(A MODE)
3
CD54HC4538, CD74HC4538, CD74HCT4538
Absolute Maximum Ratings
Thermal Information
o
o
DC Supply Voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V Thermal Resistance (Typical, Note 7)
θ
( C/W) θ C ( C/W)
JA J
CC
DC Input Diode Current, I
IK
PDIP Package . . . . . . . . . . . . . . . . . . .
SOIC Package. . . . . . . . . . . . . . . . . . .
CERDIP Package . . . . . . . . . . . . . . . .
90
160
130
N/A
N/A
55
For V < -0.5V or V > V
+ 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA
OK
For V < -0.5V or V > V
I
I
CC
DC Output Diode Current, I
o
+ 0.5V . . . . . . . . . . . . . . . . . . . .±20mA
O
O
CC
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150 C
Maximum Storage Temperature Range . . . . . . . . . .-65 C to 150 C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300 C
o
o
DC Output Source or Sink Current per Output Pin, I
O
o
For V > -0.5V or V < V
+ 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
O
O
CC
DC V
or Ground Current, I
. . . . . . . . . . . . . . . . . . . . . . . . .±50mA
CC
CC
(SOIC - Lead Tips Only)
Operating Conditions
o
o
Temperature Range, T . . . . . . . . . . . . . . . . . . . . . . -55 C to 125 C
A
Supply Voltage Range, V
(Note 5)
CC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, V , V . . . . . . . . . . . . . . . . . 0V to V
I
f
O
CC
Input Rise and Fall Times, t , t
r
Reset Input:
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
Trigger Inputs A or B:
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Unlimited (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Unlimited (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Unlimited (Max)
External Timing Resistor, R (Note 6) . . . . . . . . . . . . . . . .5kΩ (Min)
X
External Timing Capacitor, C (Note 6) . . . . . . . . . . . . . . . . . 0 (Min)
X
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
5. Unless otherwise specified, all voltages are referenced to ground.
6. The maximum allowable values of R and C are a function of leakage of capacitor C , the leakage of the HC4538, and leakage due to
X
X
X
board layout and surface resistance. Values of R and C should be chosen so that the maximum current into pin 2 or pin 14 is 30mA.
X
X
Susceptibility to externally induced noise signals may occur for R > 1MΩ.
X
7. θ is measured with the component mounted on an evaluation PC board in free air.
JA
DC Electrical Specifications
TEST
CONDITIONS
o
o
o
o
o
25 C
TYP
-40 C TO 85 C -55 C TO 125 C
V
(V)
CC
PARAMETER
HC TYPES
SYMBOL
V (V)
I
I
(mA)
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
O
High Level Input
Voltage
V
-
-
-
2
4.5
6
1.5
3.15
4.2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1.5
3.15
4.2
-
-
1.5
3.15
4.2
-
-
V
V
V
V
V
V
V
V
V
V
V
V
IH
-
-
-
-
-
-
Low Level Input
Voltage
V
-
2
0.5
0.5
0.5
IL
4.5
6
-
1.35
-
1.35
-
1.35
-
1.8
-
1.8
-
1.8
High Level Output
Voltage
CMOS Loads
V
V
or V
IH IL
-0.02
2
1.9
4.4
5.9
-
-
-
-
-
-
-
1.9
4.4
5.9
-
-
-
-
-
-
-
1.9
4.4
5.9
-
-
-
-
-
-
-
OH
-0.02
-0.02
-
4.5
6
High Level Output
Voltage
TTL Loads
-
-4
4.5
6
3.98
5.48
3.84
5.34
3.7
5.2
-5.2
4
CD54HC4538, CD74HC4538, CD74HCT4538
DC Electrical Specifications (Continued)
TEST
CONDITIONS
o
o
o
o
o
25 C
-40 C TO 85 C -55 C TO 125 C
V
CC
PARAMETER
SYMBOL
V (V)
I
(mA)
(V)
MIN
TYP
MAX
0.1
MIN
MAX
0.1
0.1
0.1
-
MIN
MAX
0.1
0.1
0.1
-
UNITS
I
O
Low Level Output
Voltage
CMOS Loads
V
V
or V
IH IL
0.02
0.02
0.02
-
2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
V
V
OL
4.5
6
0.1
0.1
V
Low Level Output
Voltage
TTL Loads
-
-
V
4
4.5
6
0.26
0.26
±0.1
0.33
0.33
±1
0.4
0.4
±1
V
5.2
-
V
Input Leakage
Current A, B, R
I
V
or
6
µA
I
CC
GND
Input Leakage
-
6
-
-
±0.05
-
±0.5
-
±0.5
µA
Current R C
X
X
(Note 9)
Quiescent Device
Current
I
I
V
GND
or
0
0
6
6
-
-
-
-
8
-
-
80
-
-
160
1
µA
CC
CC
Active Device Current
Q = High & Pins 2, 14
V
or
0.6
0.8
mA
CC
CC
GND
at V /4
CC
HCT TYPES
High Level Input
Voltage
V
-
-
-
-
4.5 to
5.5
2
-
-
-
-
-
0.8
-
2
-
-
0.8
-
2
-
-
0.8
-
V
V
V
IH
Low Level Input
Voltage
V
4.5 to
5.5
IL
High Level Output
Voltage
CMOS Loads
V
V
V
or V
-0.02
4.5
4.5
4.5
4.5
4.4
4.4
4.4
OH
IH
IH
IL
High Level Output
Voltage
TTL Loads
-4
0.02
4
3.98
-
-
-
-
3.84
-
3.7
-
V
V
V
Low Level Output
Voltage
CMOS Loads
V
or V
-
-
0.1
0.26
-
-
0.1
0.33
-
-
0.1
0.4
OL
IL
Low Level Output
Voltage
TTL Loads
Input Leakage
Current
I
V
and
-
-
5.5
5.5
-
-
±0.1
-
-
±1
-
-
±1
µA
µA
I
CC
GND
Input Leakage
-
±0.05
±0.5
±0.5
Current R C
X
X
(Note 9)
Quiescent Device
Current
I
I
V
GND
or
0
0
5.5
5.5
-
-
-
-
8
-
-
80
-
-
160
1
µA
CC
CC
Active Device Current
Q = High & Pins 2, 14
V
or
0.6
0.8
mA
CC
CC
GND
at V /4
CC
Additional Quiescent
Device Current Per
Input Pin: 1 Unit Load
∆I
V
-
4.5 to
5.5
-
100
360
-
450
-
490
µA
CC
(Note 8)
CC
-2.1
NOTES:
8. For dual-supply systems theoretical worst case (V = 2.4V, V
= 5.5V) specification is 1.8mA.
CC
I
9. When testing I the Q output must be high. If Q is low (device not triggered) the pull-up P device will be ON and the low resistance path
IL
to the test pin will cause a current far exceeding the specification.
from V
DD
5
CD54HC4538, CD74HC4538, CD74HCT4538
HCT Input Loading Table
INPUT
UNIT LOADS
All
0.5
NOTE: Unit Load is ∆I
360µA max at 25 C.
limit specified in DC Electrical Table, e.g.
CC
o
Prerequisite for Switching Specifications
o
o
o
o
o
25 C
-40 C TO 85 C
-55 C TO 125 C
PARAMETER
HC TYPES
SYMBOL
V
(V) MIN
TYP
MAX
MIN
TYP
MAX
MIN
TYP
MAX UNITS
CC
Input Pulse Widths
A, B
t
, t
WH WL
2
80
-
-
-
-
-
-
-
-
-
-
-
100
20
17
100
20
17
5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
120
24
20
120
24
20
5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4.5
6
16
14
80
16
14
5
-
-
R
t
2
-
WL
4.5
6
-
-
Reset Recovery Time
t
2
-
REC
4.5
6
5
-
-
5
5
5
5
5
Retrigger Time
(Figure 11)
t
5
-
175
-
-
rr
HCT TYPES
Input Pulse Widths
A, B
t
, t
WH WL
4.5
4.5
4.5
5
16
20
5
-
-
-
-
-
20
25
5
-
-
-
-
-
-
-
-
24
30
5
-
-
-
-
-
-
-
-
ns
ns
ns
ns
R
t
-
-
WL
Reset Recovery Time
t
REC
Retrigger Time
(Figure 11)
t
-
175
-
-
rr
6
CD54HC4538, CD74HC4538, CD74HCT4538
Switching Specifications C = 50pF, Input t , t = 6ns, R = 10KΩ, C = 0
L
r
f
X
X
o
o
-40 C TO
-55 C TO
o
o
o
25 C
85 C
125 C
TEST
SYMBOL CONDITIONS
PARAMETER
HC TYPES
V
(V) MIN
TYP MAX
MIN
MAX
MIN
MAX UNITS
CC
Propagation Delay
A, B to Q
t
C
= 50pF
PLH
L
2
4.5
5
-
-
-
250
50
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
315
63
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
375
75
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ms
%
-
C
= 15pF
-
21
-
L
C = 50pF
6
-
43
250
50
-
54
315
63
-
64
375
75
-
L
A, B to Q
t
t
t
C
= 50pF
2
-
-
PHL
PHL
PLH
L
4.5
5
-
-
C
= 15pF
-
21
-
L
C = 50pF
6
-
43
250
50
-
54
315
63
-
64
375
75
-
L
R to Q
C
= 50pF
2
-
-
L
4.5
5
-
-
C
= 15pF
-
21
-
L
C = 50pF
6
-
43
250
50
-
54
315
63
-
64
375
75
-
L
R to Q
C
= 50pF
2
-
-
L
4.5
5
-
-
C
= 15pF
-
21
-
L
C = 50pF
6
-
43
75
15
13
54
95
19
16
64
110
22
19
0.819
0.805
-
L
Output Transition Time
Output Pulse Width
t
, t
C
= 50pF
2
-
-
TLH THL
L
4.5
6
-
-
-
-
C
= 50pF
-
3
0.64
0.63
-
-
0.78 0.612 0.812 0.605
0.77 0.602 0.798 0.595
τ
L
R
= 10k, C = 0.1µF
X
X
5
-
Output Pulse Width Match,
Same Package
-
±1
-
-
-
-
Power Dissipation Capacitance
Input Capacitance
C
C
C
= 15pF
= 50pF
5
-
-
136
-
-
-
-
-
-
-
-
pF
pF
PD
L
C
10
10
10
10
I
L
HCT TYPES
Propagation Delay
A, B to Q
t
PLH
C
= 50pF
4.5
5
-
-
-
-
-
-
-
23
-
55
-
-
-
-
-
-
-
69
-
-
-
-
-
-
-
83
-
ns
ns
ns
ns
ns
ns
L
C = 15pF
L
A, B to Q
R to Q
t
t
C
= 50pF
4.5
5
55
-
69
-
83
-
PHL
L
C = 15pF
23
-
L
C
= 50pF
4.5
5
40
-
50
-
60
-
PHL
L
C = 15pF
17
L
7
CD54HC4538, CD74HC4538, CD74HCT4538
Switching Specifications C = 50pF, Input t , t = 6ns, R = 10KΩ, C = 0 (Continued)
L
r
f
X
X
o
o
-40 C TO
-55 C TO
o
o
o
25 C
85 C
125 C
TEST
SYMBOL CONDITIONS
PARAMETER
R to Q
V
(V) MIN
TYP MAX
MIN
MAX
63
MIN
MAX UNITS
CC
t
C
= 50pF
4.5
-
-
21
-
50
-
-
-
-
-
75
-
ns
ns
ns
ms
PLH
L
C = 15pF
5
4.5
5
-
-
-
-
-
L
Output Transition Time
Output Pulse Width
t
, t
C
= 50pF
= 50pF
15
19
22
TLH THL
L
L
C
0.63
-
0.77 0.602 0.798 0.595
0.805
τ
R
= 10k, C = 0.1µF
X
X
Output Pulse Width Match,
Same Package
-
-
-
-
±1
-
-
-
-
-
%
Power Dissipation Capacitance
Input Capacitance
NOTES:
C
C
C
= 15pF
= 50pF
5
-
-
134
-
-
-
-
-
-
-
-
pF
pF
PD
L
C
10
10
10
10
I
L
10. C
is used to determine the dynamic power consumption, per one shot.
PD
2
2
11. P = (C
+ C ) V
CC
f ∑(C V
f ) where f = input frequency, f = output frequency, C = output load capacitance,
D
PD
X
i
L
CC
O
i
O
L
I
C
= external capacitance V
= supply voltage assuming f «
X
CC
i
--
τ
Test Circuits and Waveforms
t = 6ns
t = 6ns
t = 6ns
t = 6ns
r
f
r
f
V
3V
CC
90%
50%
10%
2.7V
1.3V
0.3V
INPUT
INPUT
GND
GND
t
t
t
t
THL
TLH
THL
TLH
90%
1.3V
90%
50%
10%
INVERTING
OUTPUT
INVERTING
OUTPUT
10%
t
t
PLH
PHL
t
t
PLH
PHL
FIGURE 6. HC AND HCU TRANSITION TIMES AND PROPAGA-
TION DELAY TIMES, COMBINATION LOGIC
FIGURE 7. HCT TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
8
CD54HC4538, CD74HC4538, CD74HCT4538
Typical Performance Curves
HC4538 - TA11646C
HCT4538 - TA13646C
o
o
T
= 25 C
T = 25 C
A
A
0.70
0.69
0.68
0.67
0.70
0.69
0.68
0.67
10kΩ, 10nF
10kΩ, 10nF
10kΩ, 100nF
100kΩ, 100nF
10kΩ, 100nF
100kΩ, 100nF
100kΩ, 10nF
100kΩ, 10nF
2
3
4
4.5
5
5.5
6
2
3
4
4.5
5
5.5
6
V
, DC SUPPLY VOLTAGE (V)
V , DC SUPPLY VOLTAGE (V)
CC
CC
FIGURE 8. K FACTOR vs DC SUPPLY VOLTAGE (V ) - V
CC
FIGURE 9. K FACTOR vs DC SUPPLY VOLTAGE (V ) - V
CC
4
10
o
HC/HCT4538
o
T
= 25 C
A
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
V
= 5V, T = 25 C
A
CC
R
= 10kΩ
X
3
10
10
V
= 4.5V
CC
2
2kΩ
V
= 5V
CC
10kΩ
100kΩ
2
3
4
5
2
3
4
10
10
10
10
10
10
10
10
10
C , TIMING CAPACITANCE (pF)
C , TIMING CAPACITANCE (pF)
X
X
FIGURE 10. K FACTOR vs C
FIGURE 11. MINIMUM RETRIGGER TIME vs TIMING
CAPACITANCE
X
9
CD54HC4538, CD74HC4538, CD74HCT4538
Power-Down Mode
During a rapid power-down condition, as would occur with a An alternate protection method is shown in Figure 13, where
power-supply short circuit with a poorly filtered power supply, a 51Ω current-limiting resistor is inserted in series with C .
X
the energy stored in C could discharge into Pin 2 or 14. To Note that a small pulse width decrease will occur however,
X
aviod possible device damage in this mode, when C is ≥ and R must be appropriately increased to obtain the origi-
X
X
0.5µF, a protection diode with a 1 ampere or higher rating nally desired pulse width.
(1N5395 or equivalent) and a separate ground return for C
should be provided as shown in Figure 12.
X
V
V
CC
CC
IN5395
R
R
OR
X
X
EQUIVALENT
2(14)
1(15)
2(14)
1(15)
16
16
51Ω
+
C
X
≥0.5µF
C
X
≥0.5µF
8
8
FIGURE 12. RAPID POWER-DOWN PROTECTION CIRCUIT
FIGURE 13. ALTERNATE RAPID POWER-DOWN PROTECTION
CIRCUIT
10
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Copyright 1999, Texas Instruments Incorporated
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