74LVC1G386DBVRE4
更新时间：2024-09-18 14:20:20
品牌：TI
描述：LVC/LCX/Z SERIES, 3-INPUT XOR GATE, PDSO6, GREEN, PLASTIC, SOT-23, 6 PIN
概述
规格参数
数据手册
替代型号74LVC1G386DBVRE4 概述
LVC/LCX/Z SERIES, 3-INPUT XOR GATE, PDSO6, GREEN, PLASTIC, SOT-23, 6 PIN 逻辑芯片 栅极
74LVC1G386DBVRE4 规格参数
| 是否无铅： | 不含铅 | 是否Rohs认证： | 符合 |
| 生命周期： | Obsolete | 零件包装代码： | SOT-23 |
| 包装说明： | LSSOP, TSOP6,.11,37 | 针数： | 6 |
| Reach Compliance Code： | unknown | HTS代码： | 8542.39.00.01 |
| 风险等级： | 5.63 | 系列： | LVC/LCX/Z |
| JESD-30 代码： | R-PDSO-G6 | JESD-609代码： | e4 |
| 长度： | 2.9 mm | 负载电容（CL）： | 50 pF |
| 逻辑集成电路类型： | XOR GATE | 最大I（ol）： | 0.024 A |
| 湿度敏感等级： | 1 | 功能数量： | 1 |
| 输入次数： | 3 | 端子数量： | 6 |
| 最高工作温度： | 85 °C | 最低工作温度： | -40 °C |
| 输出特性： | 3-STATE | 封装主体材料： | PLASTIC/EPOXY |
| 封装代码： | LSSOP | 封装等效代码： | TSOP6,.11,37 |
| 封装形状： | RECTANGULAR | 封装形式： | SMALL OUTLINE, LOW PROFILE, SHRINK PITCH |
| 包装方法： | TAPE AND REEL | 峰值回流温度（摄氏度）： | 260 |
| 电源： | 3.3 V | Prop。Delay @ Nom-Sup： | 5 ns |
| 传播延迟（tpd）： | 12 ns | 认证状态： | Not Qualified |
| 施密特触发器： | NO | 座面最大高度： | 1.45 mm |
| 子类别： | Gates | 最大供电电压 (Vsup)： | 5.5 V |
| 最小供电电压 (Vsup)： | 1.65 V | 标称供电电压 (Vsup)： | 1.8 V |
| 表面贴装： | YES | 技术： | CMOS |
| 温度等级： | INDUSTRIAL | 端子面层： | Nickel/Palladium/Gold (Ni/Pd/Au) |
| 端子形式： | GULL WING | 端子节距： | 0.95 mm |
| 端子位置： | DUAL | 处于峰值回流温度下的最长时间： | NOT SPECIFIED |
| 宽度： | 1.6 mm | Base Number Matches： | 1 |
74LVC1G386DBVRE4 数据手册
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www.ti.com
SCES439E –APRIL 2003–REVISED DECEMBER 2013
Single 3-Input Positive-XOR Gate
Check for Samples: SN74LVC1G386
1
FEATURES
DESCRIPTION
The SN74LVC1G386 device performs the Boolean
function Y = A × B × C in positive logic.
2
•
Available in the Texas Instruments
NanoStar ™ and NanoFree™
Packages
NanoStar™ and NanoFree™ package technology is
a major breakthrough in IC packaging concepts,
using the die as the package.
•
•
•
•
Supports 5-V VCC Operation
Inputs Accept Voltages to 5.5 V
Supports Down Translation to VCC
This device is fully specified for partial-power-down
applications using Ioff. The Ioff circuitry disables the
outputs, preventing damaging current backflow
through the device when it is powered down.
Ioff Supports Live Insertion, Partial-Power-
Down Mode, Back-Drive Protection
•
•
Latch-Up Performance Exceeds 100 mA
Per JESD 78, Class II
ESD Protection Exceeds JESD 22
–
–
–
2000-V Human-Body Model (A114-A)
200-V Machine Model (A115-A)
1000-V Charged-Device Model (C101)
DBV PACKAGE
(TOP VIEW)
DCK PACKAGE
(TOP VIEW)
YZP PACKAGE
(BOTTOM VIEW)
3 4
B
Y
1
2
3
6
5
4
A
GND
B
C
1
2
3
6
5
4
A
GND
B
C
2 5
1 6
GND
VCC
VCC
A
C
VCC
Y
Y
DRY PACKAGE
(TOP VIEW)
DSF PACKAGE
(TOP VIEW)
1
2
3
6
5
4
C
A
GND
B
1
2
3
6
5
4
A
GND
B
C
VCC
Y
VCC
Y
See mechanical drawings for dimensions.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
NanoStar, NanoFree are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2003–2013, Texas Instruments Incorporated
SN74LVC1G386
SCES439E –APRIL 2003–REVISED DECEMBER 2013
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Function Table
INPUTS
OUTPUT
Y
A
L
B
L
C
L
L
H
H
L
L
L
H
L
L
H
H
L
L
H
L
H
H
H
H
H
L
L
H
L
H
H
L
H
H
Logic Diagram (Positive Logic)
A
B
C
Y
Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
MIN
–0.5
–0.5
–0.5
MAX
6.5
UNIT
V
VCC Supply voltage range
VI
Input voltage range(2)
6.5
V
VO
VO
IIK
Voltage range applied to any output in the high-impedance or power-off state(2)
Voltage range applied to any output in the high or low state(2)(3)
6.5
V
–0.5 VCC + 0.5
V
Input clamp current
VI < 0
–50
–50
±50
mA
mA
mA
mA
IOK
IO
Output clamp current
VO < 0
Continuous output current
Continuous current through VCC or GND
±100
165
259
123
DBV package
θJA
Package thermal impedance(4)
DCK package
°C/W
YEP or YZP package
Tstg
Storage temperature range
–65
150
°C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The value of VCC is provided in the recommended operating conditions table.
(4) The package thermal impedance is calculated in accordance with JESD 51-7.
2
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Product Folder Links: SN74LVC1G386
SN74LVC1G386
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SCES439E –APRIL 2003–REVISED DECEMBER 2013
Recommended Operating Conditions(1)
MIN
1.65
MAX UNIT
Operating
5.5
V
VCC
Supply voltage
Data retention only
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
VCC = 4.5 V to 5.5 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
VCC = 4.5 V to 5.5 V
1.5
0.65 × VCC
1.7
VIH
High-level input voltage
V
2
0.7 × VCC
0.35 × VCC
0.7
VIL
Low-level input voltage
V
0.8
0.3 × VCC
5.5
VCC
–4
VI
Input voltage
0
0
V
V
VO
Output voltage
VCC = 1.65 V
VCC = 2.3 V
–8
IOH
High-level output current
Low-level output current
–16
–24
–32
4
mA
mA
VCC = 3 V
VCC = 4.5 V
VCC = 1.65 V
VCC = 2.3 V
8
IOL
16
VCC = 3 V
24
VCC = 4.5 V
32
VCC = 1.8 V ± 0.15 V, 2.5 V ± 0.2 V
VCC = 3.3 V ± 0.3 V
VCC = 5 V ± 0.5 V
20
Δt/Δv Input transition rise or fall rate
10
ns/V
°C
5
TA
Operating free-air temperature
–40
125
(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
Copyright © 2003–2013, Texas Instruments Incorporated
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SCES439E –APRIL 2003–REVISED DECEMBER 2013
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Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
–40°C to 85°C
–40°C to 125°C
MIN
TYP(1)
PARAMETER
TEST CONDITIONS
VCC
UNIT
MAX
MIN
TYP(1)
MAX
1.65 V to
5.5 V
IOH = –100 µA
VCC – 0.1
VCC – 0.1
IOH = –4 mA
IOH = –8 mA
IOH = –16 mA
IOH = –24 mA
IOH = –32 mA
1.65 V
2.3 V
1.2
1.9
2.4
2.3
3.8
1.2
1.9
2.4
2.3
3.8
VOH
V
3 V
4.5 V
1.65 V to
5.5 V
IOL = 100 µA
0.1
0.1
IOL = 4 mA
1.65 V
2.3 V
0.45
0.3
0.45
IOL = 8 mA
0.3
V
VOL
IOL = 16 mA
IOL = 24 mA
IOL = 32 mA
VI = 5.5 V or GND
VI or VO = 5.5 V
0.4
0.4
0.55
0.55
3 V
0.55
0.55
±5
4.5 V
0 to 5.5 V
0
II
All inputs
±5
µA
µA
Ioff
±10
±10
1.65 V to
5.5 V
ICC
VI = 5.5 V or GND, IO = 0
10
10
µA
One input at VCC – 0.6 V,
Other inputs at VCC or GND
ΔICC
3 V to 5.5 V
3.3 V
500
500
µA
pF
Ci
VI = VCC or GND
3.5
(1) All typical values are at VCC = 3.3 V, TA = 25°C.
4
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Product Folder Links: SN74LVC1G386
SN74LVC1G386
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SCES439E –APRIL 2003–REVISED DECEMBER 2013
Switching Characteristics
over recommended operating free-air temperature range, CL = 15 pF (unless otherwise noted) (see Figure 1)
–40°C to 85°C
FROM
(INPUT)
TO
(OUTPUT)
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
VCC = 5 V
± 0.5 V
PARAMETER
UNIT
MIN MAX
MIN MAX
MIN MAX
MIN MAX
tpd
A, B, or C
Y
3
9.4
1.3
5
0.8
4.5
0.5
3.5
ns
Switching Characteristics
over recommended operating free-air temperature range, CL = 30 pF or 50 pF (unless otherwise noted) (see Figure 2)
–40°C to 85°C
FROM
(INPUT)
TO
(OUTPUT)
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
VCC = 5 V
± 0.5 V
PARAMETER
UNIT
MIN MAX
MIN MAX
MIN MAX
MIN MAX
tpd
A, B, or C
Y
3.5
12
1.8
5.5
1.3
5
1
4
ns
Switching Characteristics
over recommended operating free-air temperature range, CL = 30 pF or 50 pF (unless otherwise noted) (see Figure 2)
–40°C to 125°C
FROM
(INPUT)
TO
(OUTPUT)
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
VCC = 5 V
± 0.5 V
PARAMETER
UNIT
MIN MAX
MIN MAX
MIN MAX
MIN MAX
tpd
A, B, or C
Y
3.5
14.8
1.8
7.2
1.3
6.4
1
5.1
ns
Operating Characteristics
TA = 25°C
VCC = 1.8 V
TYP
VCC = 2.5 V
TYP
VCC = 3.3 V
TYP
VCC = 5 V
TYP
PARAMETER
TEST CONDITIONS
UNIT
Cpd
Power dissipation capacitance
f = 10 MHz
17.5
18
19
22
pF
Copyright © 2003–2013, Texas Instruments Incorporated
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SCES439E –APRIL 2003–REVISED DECEMBER 2013
www.ti.com
Parameter Measurement Information
VLOAD
Open
S1
RL
From Output
Under Test
TEST
S1
VLOAD
VLOAD
VLOAD
GND
tPZL (see Notes E and F)
tPLZ (see Notes E and G)
tPHZ/tPZH
CL
(see Note A)
RL
LOAD CIRCUIT
VCC
INPUTS
VM
VLOAD
CL
RL
V∆
VI
tr/tf
VCC
VCC
3 V
VCC
1.8 V ± 0.15 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
5 V ± 0.5 V
≤2 ns
≤2 ns
≤2.5 ns
≤2.5 ns
VCC/2
VCC/2
1.5 V
VCC/2
2 × VCC
2 × VCC
6 V
15 pF
15 pF
15 pF
15 pF
1 MΩ
1 MΩ
1 MΩ
1 MΩ
0.15 V
0.15 V
0.3 V
2 × VCC
0.3 V
VI
Timing Input
Data Input
VM
0 V
tW
tsu
th
VI
VI
Input
VM
VM
VM
VM
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VI
VI
Output
Control
VM
VM
Input
VM
VM
0 V
0 V
tPZL
tPLZ
tPLH
tPHL
VM
Output
Waveform 1
S1 at VLOAD
VOH
VOL
VLOAD/2
VOL
VM
VM
Output
Output
VOL + V∆
(see Note B)
tPHL
tPLH
tPZH
tPHZ
VOH
VOL
Output
Waveform 2
S1 at GND
VOH
VOH – V∆
VM
VM
VM
≈0 V
(see Note B)
VOLTAGE WAVEFORMS
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
ENABLE AND DISABLE TIMES
INVERTING AND NONINVERTING OUTPUTS
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators have the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω.
D. The outputs are measured one at a time, with one transition per measurement.
E. Because this device has open-drain outputs, tPLZ and tPZL are the same as tPD.
F. tPZL is measured at VM.
G. tPLZ is measured at VOL + V∆.
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
6
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Product Folder Links: SN74LVC1G386
SN74LVC1G386
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SCES439E –APRIL 2003–REVISED DECEMBER 2013
Parameter Measurement Information
VLOAD
Open
S1
RL
From Output
Under Test
TEST
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
S1
GND
Open
VLOAD
GND
CL
(see Note A)
RL
LOAD CIRCUIT
INPUTS
VCC
VM
VLOAD
CL
RL
V
D
VI
tr/tf
VCC
VCC
3 V
VCC
1.8 V ± 0.15 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
5 V ± 0.5 V
£2 ns
£2 ns
VCC/2
VCC/2
1.5 V
VCC/2
2 × VCC
2 × VCC
6 V
30 pF
30 pF
50 pF
50 pF
1 kW
0.15 V
0.15 V
0.3 V
500 W
500 W
500 W
£2.5 ns
£2.5 ns
2 × VCC
0.3 V
VI
Timing Input
Data Input
VM
0 V
tW
tsu
th
VI
VI
Input
VM
VM
VM
VM
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VI
VI
Output
Control
VM
VM
Input
VM
VM
0 V
0 V
tPZL
tPLZ
tPLH
tPHL
VM
Output
Waveform 1
S1 at VLOAD
VOH
VOL
VLOAD/2
VOL
VM
VM
Output
Output
VOL + V
D
(see Note B)
tPHL
tPLH
tPZH
tPHZ
VOH
VOL
Output
Waveform 2
S1 at GND
VOH
VOH – V
D
VM
VM
VM
»0 V
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR £ 10 MHz, ZO = 50 W.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 2. Load Circuit and Voltage Waveforms
Copyright © 2003–2013, Texas Instruments Incorporated
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SCES439E –APRIL 2003–REVISED DECEMBER 2013
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REVISION HISTORY
Changes from Revision D (July 2006) to Revision E
Page
•
•
•
•
Updated document to new TI data sheet format. ................................................................................................................. 1
Updated Features. ................................................................................................................................................................ 1
Added ESD warning. ............................................................................................................................................................ 2
Updated operating temperature range. ................................................................................................................................. 3
8
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Jun-2014
PACKAGING INFORMATION
Orderable Device
74LVC1G386DCKRG4
SN74LVC1G386DBVR
SN74LVC1G386DCKR
SN74LVC1G386DRYR
SN74LVC1G386DSFR
SN74LVC1G386YZPR
Status Package Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 85
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
ACTIVE
SC70
SOT-23
SC70
DCK
6
6
6
6
6
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
SNAGCU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
C8R
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
DBV
DCK
DRY
DSF
YZP
3000
3000
5000
5000
3000
Green (RoHS
& no Sb/Br)
(CC62 ~ CC6R)
Green (RoHS
& no Sb/Br)
C8R
SON
Green (RoHS
& no Sb/Br)
C8
SON
Green (RoHS
& no Sb/Br)
C8
DSBGA
Green (RoHS
& no Sb/Br)
(C87 ~ C8N)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Jun-2014
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jun-2014
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74LVC1G386DBVR SOT-23
DBV
DCK
DRY
DSF
YZP
6
6
6
6
6
3000
3000
5000
5000
3000
180.0
180.0
180.0
180.0
178.0
8.4
8.4
9.5
9.5
9.2
3.23
2.41
1.15
1.16
1.02
3.17
2.41
1.6
1.37
1.2
4.0
4.0
4.0
4.0
4.0
8.0
8.0
8.0
8.0
8.0
Q3
Q3
Q1
Q2
Q1
SN74LVC1G386DCKR
SN74LVC1G386DRYR
SN74LVC1G386DSFR
SN74LVC1G386YZPR
SC70
SON
0.75
0.5
SON
1.16
1.52
DSBGA
0.63
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jun-2014
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
SN74LVC1G386DBVR
SN74LVC1G386DCKR
SN74LVC1G386DRYR
SN74LVC1G386DSFR
SN74LVC1G386YZPR
SOT-23
SC70
DBV
DCK
DRY
DSF
YZP
6
6
6
6
6
3000
3000
5000
5000
3000
202.0
202.0
184.0
184.0
220.0
201.0
201.0
184.0
184.0
220.0
28.0
28.0
19.0
19.0
35.0
SON
SON
DSBGA
Pack Materials-Page 2
D: Max = 1.418 mm, Min =1.358 mm
E: Max = 0.918 mm, Min =0.858 mm
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74LVC1G386DBVRE4 替代型号
| 型号 | 制造商 | 描述 | 替代类型 | 文档 |
| SN74LVC1G386DBVR | TI | SINGLE 3-INPUT POSITIVE-XOR GATE | 类似代替 |
|
74LVC1G386DBVRE4 相关器件
| 型号 | 制造商 | 描述 | 价格 | 文档 |
| 74LVC1G386DCKRE4 | TI | LVC/LCX/Z SERIES, 3-INPUT XOR GATE, PDSO6, GREEN, PLASTIC, SC-70, 6 PIN | 获取价格 |
|
| 74LVC1G386DCKRG4 | TI | SINGLE 3-INPUT POSITIVE-XOR GATE | 获取价格 |
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| 74LVC1G386GV | NXP | 3-input EXCLUSIVE-OR gate | 获取价格 |
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| 74LVC1G386GV | NEXPERIA | 3-input EXCLUSIVE-OR gateProduction | 获取价格 |
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| 74LVC1G386GW | NXP | 3-input EXCLUSIVE-OR gate | 获取价格 |
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| 74LVC1G386GW | NEXPERIA | 3-input EXCLUSIVE-OR gateProduction | 获取价格 |
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| 74LVC1G386GW,125 | NXP | 74LVC1G386 - 3-input EXCLUSIVE-OR gate TSSOP 6-Pin | 获取价格 |
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| 74LVC1G386GW-Q100 | NEXPERIA | 3-input EXCLUSIVE-OR gateProduction | 获取价格 |
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| 74LVC1G38GF | NXP | 2-input NAND gate; open drain | 获取价格 |
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| 74LVC1G38GF,132 | NXP | 74LVC1G38 - 2-input NAND gate; open drain SON 6-Pin | 获取价格 |
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