74LVTH16541DGGRG4 [TI]

3.3-V ABT 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS; 3.3 -V ABT 16位缓冲器/驱动器,具有三态输出
74LVTH16541DGGRG4
型号: 74LVTH16541DGGRG4
厂家: TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述:

3.3-V ABT 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS
3.3 -V ABT 16位缓冲器/驱动器,具有三态输出

总线驱动器 总线收发器 逻辑集成电路 光电二极管 输出元件 信息通信管理
文件: 总13页 (文件大小:314K)
中文:  中文翻译
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SN54LVTH16541, SN74LVTH16541  
3.3-V ABT 16-BIT BUFFERS/DRIVERS  
WITH 3-STATE OUTPUTS  
www.ti.com  
SCBS691EMAY 1997REVISED NOVEMBER 2006  
FEATURES  
SN54LVTH16541 . . . WD PACKAGE  
SN74LVTH16541 . . . DGG OR DL PACKAGE  
(TOP VIEW)  
Members of the Texas Instruments Widebus™  
Family  
State-of-the-Art Advanced BiCMOS  
Technology (ABT) Design for 3.3-V Operation  
and Low Static-Power Dissipation  
1OE1  
1Y1  
1OE2  
1A1  
1
2
3
4
5
6
7
8
9
48  
47  
1Y2  
GND  
1Y3  
46 1A2  
Support Mixed-Mode Signal Operation  
(5-V Input and Output Voltages With  
GND  
1A3  
1A4  
45  
44  
43  
42  
3.3-V VCC  
)
1Y4  
Support Unregulated Battery Operation Down  
to 2.7 V  
V
CC  
V
CC  
1Y5  
1Y6  
GND 10  
1Y7  
1Y8  
2Y1  
41 1A5  
40 1A6  
39 GND  
Typical VOLP (Output Ground Bounce) <0.8 V  
at VCC = 3.3 V, TA = 25°C  
Ioff and Power-Up 3-State Support Hot  
Insertion  
1A7  
1A8  
2A1  
11  
12  
13  
38  
37  
36  
Bus Hold on Data Inputs Eliminates the Need  
for External Pullup/Pulldown Resistors  
2Y2 14  
GND 15  
2Y3 16  
2Y4 17  
35 2A2  
34 GND  
33 2A3  
32 2A4  
Distributed VCC and GND Pin Configuration  
Minimizes High-Speed Switching Noise  
Flow-Through Architecture Optimizes PCB  
Layout  
V
CC  
V
CC  
18  
31  
2Y5 19  
2Y6 20  
GND 21  
2Y7 22  
2Y8 23  
2OE1 24  
30 2A5  
29 2A6  
28 GND  
27 2A7  
26 2A8  
25 2OE2  
Latch-Up Performance Exceeds 500 mA Per  
JESD 17  
ESD Protection Exceeds 2000 V Per  
MIL-STD-883, Method 3015; Exceeds 200 V  
Using Machine Model (C = 200 pF, R = 0)  
Package Options Include Plastic Shrink  
Small-Outline (DL) and Thin Shrink  
Small-Outline (DGG) Packages and 380-mil  
Fine-Pitch Ceramic Flat (WD) Package Using  
25-mil Center-to-Center Spacings  
DESCRIPTION/ORDERING INFORMATION  
These 16-bit buffers/drivers are designed specifically for low-voltage (3.3-V) VCC operation, but with the  
capability to provide a TTL interface to a 5-V system environment.  
These devices are noninverting 16-bit buffers composed of two 8-bit sections with separate output-enable  
signals. For either 8-bit buffer section, the two output-enable (1OE1 and 1OE2 or 2OE1 and 2OE2) inputs must  
be low for the corresponding Y outputs to be active. If either output-enable input is high, the outputs of that 8-bit  
buffer section are in the high-impedance state.  
When VCC is between 0 and 1.5 V, the devices are in the high-impedance state during power up or power down.  
However, to ensure the high-impedance state above 1.5 V, OE should be tied to VCC through a pullup resistor;  
the minimum value of the resistor is determined by the current-sinking capability of the driver.  
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.  
These devices are fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry  
disables the outputs, preventing damaging current backflow through the devices when they are powered down.  
The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,  
which prevents driver conflict.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Widebus is a trademark of Texas Instruments.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 1997–2006, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
SN54LVTH16541, SN74LVTH16541  
3.3-V ABT 16-BIT BUFFERS/DRIVERS  
WITH 3-STATE OUTPUTS  
www.ti.com  
SCBS691EMAY 1997REVISED NOVEMBER 2006  
DESCRIPTION/ORDERING INFORMATION (CONTINUED)  
The SN54LVTH16541 is characterized for operation over the full military temperature range of –55°C to 125°C.  
The SN74LVTH16541 is characterized for operation from –40°C to 85°C.  
ORDERING INFORMATION  
TA  
PACKAGE(1)  
ORDERABLE PART NUMBER  
74LVTH16541DLRG4  
TOP-SIDE MARKING  
Reel of 1000  
SN74LVTH16541DLR  
SSOP – DL  
LVTH16541  
SN74LVTH16541DL  
–40°C to 85°C  
Tube of 25  
SN74LVTH16541DLG4  
74LVTH16541DGGRE4  
SN74LVTH16541DGGR  
TSSOP – DGG  
Reel of 2000  
LVTH16541  
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at  
www.ti.com/sc/package.  
FUNCTION TABLE  
(each 8-bit section)  
INPUTS  
OUTPUT  
Y
OE1  
L
OE2  
L
A
L
L
H
Z
Z
L
L
H
X
X
H
X
X
H
2
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SN54LVTH16541, SN74LVTH16541  
3.3-V ABT 16-BIT BUFFERS/DRIVERS  
WITH 3-STATE OUTPUTS  
www.ti.com  
SCBS691EMAY 1997REVISED NOVEMBER 2006  
LOGIC SYMBOL(1)  
1
&
1OE1  
1OE2  
48  
EN1  
24  
25  
&
2OE1  
2OE2  
EN2  
47  
46  
44  
43  
41  
40  
38  
37  
36  
35  
33  
32  
30  
29  
27  
26  
2
1
1
1A1  
1A2  
1A3  
1A4  
1A5  
1A6  
1A7  
1A8  
2A1  
2A2  
2A3  
2A4  
2A5  
2A6  
2A7  
2A8  
1Y1  
3
1Y2  
5
1Y3  
6
1Y4  
8
1Y5  
9
1Y6  
11  
1Y7  
12  
1Y8  
13  
1
2
2Y1  
14  
2Y2  
16  
2Y3  
17  
2Y4  
19  
2Y5  
20  
2Y6  
22  
2Y7  
23  
2Y8  
(1) This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.  
LOGIC DIAGRAM (POSITIVE LOGIC)  
24  
25  
1
1OE1  
1OE2  
2OE1  
2OE2  
48  
47  
2
36  
13  
1A1  
1Y1  
2Y1  
2A1  
To Seven Other Channels  
To Seven Other Channels  
3
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SN54LVTH16541, SN74LVTH16541  
3.3-V ABT 16-BIT BUFFERS/DRIVERS  
WITH 3-STATE OUTPUTS  
www.ti.com  
SCBS691EMAY 1997REVISED NOVEMBER 2006  
Absolute Maximum Ratings(1)  
over operating free-air temperature range (unless otherwise noted)  
MIN  
–0.5  
–0.5  
–0.5  
–0.5  
MAX UNIT  
VCC  
VI  
Supply voltage range  
Input voltage range(2)  
Voltage range applied to any output in the high-impedance or power-off state(2)  
Voltage range applied to any output in the high state(2)  
4.6  
V
V
V
V
7
VO  
VO  
7
VCC + 0.5  
96  
SN54LVTH16541  
IO  
Current into any output in the low state  
Current into any output in the high state(3)  
mA  
mA  
SN74LVTH16541  
SN54LVTH16541  
SN74LVTH16541  
VI < 0  
128  
48  
IO  
64  
IIK  
Input clamp current  
Output clamp current  
–50  
mA  
mA  
IOK  
VO < 0  
–50  
DGG package  
DL package  
89  
θJA  
Package thermal impedance(4)  
Storage temperature range  
°C/W  
°C  
94  
Tstg  
–65  
150  
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings  
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating  
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.  
(2) The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.  
(3) This current flows only when the output is in the high state and VO > VCC  
.
(4) The package thermal impedance is calculated in accordance with JESD 51.  
Recommended Operating Conditions(1)  
SN54LVTH16541  
SN74LVTH16541  
UNIT  
MIN  
2.7  
2
MAX  
MIN  
2.7  
2
MAX  
VCC  
VIH  
VIL  
Supply voltage  
3.6  
3.6  
V
V
High-level input voltage  
Low-level input voltage  
Input voltage  
0.8  
5.5  
–24  
48  
0.8  
5.5  
–32  
64  
V
VI  
V
IOH  
IOL  
High-level output current  
Low-level output current  
Input transition rise or fall rate  
mA  
mA  
ns/V  
µs/V  
°C  
t/v  
Outputs enabled  
10  
10  
t/VCC Power-up ramp rate  
TA Operating free-air temperature  
200  
–55  
200  
–40  
125  
85  
(1) All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,  
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.  
4
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SN54LVTH16541, SN74LVTH16541  
3.3-V ABT 16-BIT BUFFERS/DRIVERS  
WITH 3-STATE OUTPUTS  
www.ti.com  
SCBS691EMAY 1997REVISED NOVEMBER 2006  
Electrical Characteristics  
over recommended operating free-air temperature range (unless otherwise noted)  
SN54LVTH16541  
MIN TYP(1)  
SN74LVTH16541B  
MIN TYP(1) MAX  
–1.2  
PARAMETER  
VIK  
TEST CONDITIONS  
UNIT  
MAX  
VCC = 2.7 V,  
II = –18 mA  
–1.2  
V
VCC = 2.7 V to 3.6 V, IOH = –100 µA  
VCC – 0.2  
VCC – 0.2  
VCC = 2.7 V,  
IOH = –8 mA  
IOH = –24 mA  
IOH = –32 mA  
IOL = 100 µA  
IOL = 24 mA  
IOL = 16 mA  
IOL = 32 mA  
IOL = 48 mA  
IOL = 64 mA  
VI = 5.5 V  
2.4  
2
2.4  
VOH  
V
V
VCC = 3 V  
2
0.2  
0.5  
0.2  
0.5  
0.4  
0.5  
VCC = 2.7 V  
VCC = 3 V  
0.4  
VOL  
0.5  
0.55  
0.55  
10  
VCC = 0 or 3.6 V,  
VCC = 3.6 V,  
10  
Control  
inputs  
VI = VCC or GND  
±1  
±1  
II  
µA  
VI = VCC  
1
1
–5  
Data  
inputs  
VCC = 3.6 V  
VCC = 0,  
VI = 0  
–5  
Ioff  
VI or VO = 0 to 4.5 V  
VI = 0.8 V  
VI = 2 V  
±100  
µA  
µA  
75  
75  
VCC = 3 V  
Data  
–75  
–75  
II(hold)  
inputs  
500  
–750  
VCC = 3.6 V,(2)  
VI = 0 to 3.6 V  
IOZH  
IOZL  
VCC = 3.6 V,  
VCC = 3.6 V,  
VO = 3 V  
5
5
µA  
µA  
VO = 0.5 V  
–5  
–5  
VCC = 0 to 1.5 V, VO = 0.5 V to 3 V,  
OE = don't care  
IOZPU  
IOZPD  
±100(3)  
±100(3)  
±100  
±100  
µA  
µA  
VCC = 1.5 V to 0, VO = 0.5 V to 3 V,  
OE = don't care  
Outputs high  
VCC = 3.6 V,  
0.19  
5
0.19  
5
ICC  
IO = 0,  
Outputs low  
mA  
mA  
VI = VCC or GND  
Outputs disabled  
0.19  
0.19  
VCC = 3 V to 3.6 V, One input at VCC – 0.6 V,  
Other inputs at VCC or GND  
(4)  
ICC  
0.2  
0.2  
CI  
VI = 3 V or 0  
VO = 3 V or 0  
4
9
4
9
pF  
pF  
Co  
(1) All typical values are at VCC = 3.3 V, TA = 25°C.  
(2) This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to  
another.  
(3) On products compliant to MIL-PRF-38535, this parameter is not production tested.  
(4) This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCC or GND.  
5
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SN54LVTH16541, SN74LVTH16541  
3.3-V ABT 16-BIT BUFFERS/DRIVERS  
WITH 3-STATE OUTPUTS  
www.ti.com  
SCBS691EMAY 1997REVISED NOVEMBER 2006  
Switching Characteristics  
over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1)  
SN54LVTH16541  
VCC = 3.3 V  
SN74LVTH16541  
FROM  
(INPUT)  
TO  
(OUTPUT)  
VCC = 3.3 V  
± 0.3 V  
PARAMETER  
VCC = 2.7 V  
MIN  
VCC = 2.7 V UNIT  
± 0.3 V  
MIN  
1
MAX  
3.7  
3.7  
4.8  
4.8  
6.2  
5.7  
MAX MIN TYP(1) MAX MIN MAX  
tPLH  
tPHL  
4
4
1
1
2.4  
2
3.5  
3.5  
4.6  
4.6  
5.9  
5.4  
0.5  
0.5  
3.8  
3.8  
5.5  
5.2  
6.2  
5.5  
0.5  
0.5  
A
Y
Y
Y
ns  
ns  
ns  
ns  
1
tPZH  
1.1  
1.1  
2.1  
1.9  
5.7  
5.4  
6.5  
6
1.2  
1.2  
2.2  
2.2  
2.7  
2.8  
4.1  
3.8  
OE  
OE  
tPZL  
tPHZ  
tPLZ  
tsk(LH)  
tsk(HL)  
(1) All typical values are at VCC = 3.3 V, TA = 25°C.  
6
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SN54LVTH16541, SN74LVTH16541  
3.3-V ABT 16-BIT BUFFERS/DRIVERS  
WITH 3-STATE OUTPUTS  
www.ti.com  
SCBS691EMAY 1997REVISED NOVEMBER 2006  
PARAMETER MEASUREMENT INFORMATION  
6 V  
Open  
TEST  
S1  
S1  
500 Ω  
From Output  
Under Test  
t
pd  
Open  
6 V  
GND  
GND  
t
t
/t  
PLZ PZL  
C = 50 pF  
L
/t  
PHZ PZH  
500 Ω  
(see Note A)  
2.7 V  
0 V  
LOAD CIRCUIT  
1.5 V  
Timing Input  
Data Input  
t
w
t
t
h
su  
2.7 V  
0 V  
2.7 V  
0 V  
1.5 V  
1.5 V  
Input  
1.5 V  
1.5 V  
VOLTAGE WAVEFORMS  
PULSE DURATION  
VOLTAGE WAVEFORMS  
SETUP AND HOLD TIMES  
2.7 V  
0 V  
2.7 V  
0 V  
Output  
Control  
1.5 V  
1.5 V  
Input  
1.5 V  
1.5 V  
t
t
t
t
t
PHL  
PZL  
PLZ  
PLH  
Output  
Waveform 1  
S1 at 6 V  
V
V
3 V  
OH  
1.5 V  
Output  
1.5 V  
1.5 V  
1.5 V  
V
V
+ 0.3 V  
OL  
V
OL  
OL  
(see Note B)  
t
t
t
PZH  
PHZ  
PHL  
PLH  
Output  
Waveform 2  
S1 at GND  
V
V
V
OH  
OH  
− 0.3 V  
OH  
1.5 V  
Output  
1.5 V  
0 V  
(see Note B)  
OL  
VOLTAGE WAVEFORMS  
PROPAGATION DELAY TIMES  
INVERTING AND NONINVERTING OUTPUTS  
VOLTAGE WAVEFORMS  
ENABLE AND DISABLE TIMES  
LOW- AND HIGH-LEVEL ENABLING  
NOTES: A. C includes probe and jig capacitance.  
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.  
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.  
C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, Z = 50 , t 2.5 ns, t 2.5 ns.  
O
r
f
D. The outputs are measured one at a time, with one transition per measurement.  
Figure 1. Load Circuit and Voltage Waveforms  
7
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PACKAGE OPTION ADDENDUM  
www.ti.com  
27-Sep-2007  
PACKAGING INFORMATION  
Orderable Device  
74LVTH16541DGGRE4  
74LVTH16541DGGRG4  
74LVTH16541DLRG4  
SN74LVTH16541DGGR  
SN74LVTH16541DL  
Status (1)  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
Package Package  
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)  
Qty  
Type  
Drawing  
TSSOP  
DGG  
48  
48  
48  
48  
48  
48  
48  
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
TSSOP  
SSOP  
TSSOP  
SSOP  
SSOP  
SSOP  
DGG  
DL  
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
1000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
DGG  
DL  
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
SN74LVTH16541DLG4  
SN74LVTH16541DLR  
DL  
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
DL  
1000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in  
a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2)  
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check  
http://www.ti.com/productcontent for the latest availability information and additional product content details.  
TBD: The Pb-Free/Green conversion plan has not been defined.  
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements  
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered  
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.  
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and  
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS  
compatible) as defined above.  
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame  
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)  
(3)  
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder  
temperature.  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is  
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the  
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take  
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on  
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited  
information may not be available for release.  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI  
to Customer on an annual basis.  
Addendum-Page 1  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
11-Mar-2008  
TAPE AND REEL INFORMATION  
*All dimensions are nominal  
Device  
Package Package Pins  
Type Drawing  
SPQ  
Reel  
Reel  
A0 (mm)  
B0 (mm)  
K0 (mm)  
P1  
W
Pin1  
Diameter Width  
(mm) W1 (mm)  
(mm) (mm) Quadrant  
SN74LVTH16541DGGR TSSOP  
SN74LVTH16541DLR SSOP  
DGG  
DL  
48  
48  
2000  
1000  
330.0  
330.0  
24.4  
32.4  
8.6  
15.8  
16.2  
1.8  
3.1  
12.0  
16.0  
24.0  
32.0  
Q1  
Q1  
11.35  
Pack Materials-Page 1  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
11-Mar-2008  
*All dimensions are nominal  
Device  
Package Type Package Drawing Pins  
SPQ  
Length (mm) Width (mm) Height (mm)  
SN74LVTH16541DGGR  
SN74LVTH16541DLR  
TSSOP  
SSOP  
DGG  
DL  
48  
48  
2000  
1000  
346.0  
346.0  
346.0  
346.0  
41.0  
49.0  
Pack Materials-Page 2  
MECHANICAL DATA  
MSSO001C – JANUARY 1995 – REVISED DECEMBER 2001  
DL (R-PDSO-G**)  
PLASTIC SMALL-OUTLINE PACKAGE  
48 PINS SHOWN  
0.025 (0,635)  
48  
0.0135 (0,343)  
0.008 (0,203)  
0.005 (0,13)  
M
25  
0.010 (0,25)  
0.005 (0,13)  
0.299 (7,59)  
0.291 (7,39)  
0.420 (10,67)  
0.395 (10,03)  
Gage Plane  
0.010 (0,25)  
0°ā8°  
1
24  
0.040 (1,02)  
0.020 (0,51)  
A
Seating Plane  
0.004 (0,10)  
0.008 (0,20) MIN  
PINS **  
0.110 (2,79) MAX  
28  
48  
0.630  
56  
DIM  
0.380  
(9,65)  
0.730  
A MAX  
A MIN  
(16,00) (18,54)  
0.370  
(9,40)  
0.620  
0.720  
(15,75) (18,29)  
4040048/E 12/01  
NOTES: A. All linear dimensions are in inches (millimeters).  
B. This drawing is subject to change without notice.  
C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).  
D. Falls within JEDEC MO-118  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
MECHANICAL DATA  
MTSS003D – JANUARY 1995 – REVISED JANUARY 1998  
DGG (R-PDSO-G**)  
PLASTIC SMALL-OUTLINE PACKAGE  
48 PINS SHOWN  
0,27  
0,17  
M
0,08  
0,50  
48  
25  
6,20  
6,00  
8,30  
7,90  
0,15 NOM  
Gage Plane  
0,25  
1
24  
0°8°  
A
0,75  
0,50  
Seating Plane  
0,10  
0,15  
0,05  
1,20 MAX  
PINS **  
48  
56  
64  
DIM  
A MAX  
12,60  
12,40  
14,10  
13,90  
17,10  
16,90  
A MIN  
4040078/F 12/97  
NOTES: A. All linear dimensions are in millimeters.  
B. This drawing is subject to change without notice.  
C. Body dimensions do not include mold protrusion not to exceed 0,15.  
D. Falls within JEDEC MO-153  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
IMPORTANT NOTICE  
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logic.ti.com  
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www.ti.com/digitalcontrol  
www.ti.com/medical  
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Military  
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Microcontrollers  
RFID  
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Copyright © 2008, Texas Instruments Incorporated  

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