74S225 [TI]
16 】 5 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY WITH 3-STATE OUTPUTS; 16 】 5异步先入，具有三态输出的先出存储器
| 型号： | 74S225 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 16 】 5 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY WITH 3-STATE OUTPUTS |
| 文件： | 总10页 (文件大小：148K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74S225
16 × 5 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY
WITH 3-STATE OUTPUTS
SDLS207B – SEPTEMBER 1976 – REVISED APRIL 1998
N PACKAGE
(TOP VIEW)
Independent Asychronous Inputs and
Outputs
16 Words by 5 Bits
CLKA
V
CC
19 CLKB
1
2
3
4
5
6
7
8
9
10
20
DC to 10-MHz Data Rate
3-State Outputs
IR
UNCK OUT
18 CLR
17
16
15
14
13
12
11
D0
D1
D2
D3
D4
OR
UNCK IN
Q0
Q1
Q2
Packaged in Standard Plastic 300-mil DIPs
description
This 80-bit active-element memory is a monolithic
Schottky-clamped transistor-transistor logic
(STTL) array organized as 16 words by 5 bits. A
memory system using the SN74S225 easily can
be expanded in multiples of 48 words or of 10 bits
as shown in Figure 3. The 3-state outputs
controlled by a single output-enable (OE) input
make bus connection and multiplexing easy.
OE
GND
Q3
Q4
A first-in, first-out (FIFO) memory is a storage device that allows data to be written into and read from its array
at independent data rates. This FIFO is designed to process data at rates from dc to 10 MHz in a bit-parallel
format, word by word.
Reading or writing is done independently, utilizing separate asynchronous data clocks. Data can be written into
the array on the low-to-high transition of either load-clock (CLKA, CLKB) input. Data can be read out of the array
on the low-to-high transition of the unload-clock (UNCK IN) input (normally high). Writing data into the FIFO can
be accomplished in one of two ways:
In applications not requiring a gated clock control, best results are achieved by applying the clock input to
one of the clocks while tying the other clock input high.
In applications needing a gated clock, the load clock (gate control) must be high for the FIFO to load on the
next clock pulse.
CLKA and CLKB can be used interchangeably for either clock gate control or clock input.
Status of the SN74S225 is provided by three outputs. The input-ready (IR) output monitors the status of the last
word location and signifies when the memory is full. This output is high whenever the memory is available to
accept any data. The unload-clock (UNCK OUT) output also monitors the last word location. This output
generatesalow-logic-levelpulse(synchronizedtotheinternalclockpulse)whenthelocationisvacant. Thethird
status output, output ready (OR), is high when the first word location contains valid data and UNCK IN is high.
When UNCK IN goes low, OR will go low and stay low until new valid data is in the first word position. The first
word location is defined as the location from which data is provided to the outputs.
The data outputs are noninverted with respect to the data inputs and are 3-state, with a common control input
(OE). When OE is low, the data outputs are enabled to function as totem-pole outputs. A high logic level forces
each data output to a high-impedance state while all other inputs and outputs remain active.The clear (CLR)
input invalidates all data stored in the memory array by clearing the control logic and setting OR to a low logic
level on the high-to-low transition of a low-active pulse.
The SN74S225 is characterized for operation from 0°C to 70°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 1998, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74S225
16 × 5 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY
WITH 3-STATE OUTPUTS
SDLS207B – SEPTEMBER 1976 – REVISED APRIL 1998
†
logic symbol
FIFO 16 × 5
3
2
9
2
5, 2
1, 3
UNCK OUT
OE
EN6
16
IR
UNCK IN
Z1
3–
17
CTR
OR
18
CT = 0
CLR
G2
G3
CT < 16
CT > 0
1
&
2+
2
CLKA
CLKB
19
C4
Z5
1
4
5
6
7
8
15
14
13
12
11
D0
D1
D2
D3
D4
4D
Q0
Q1
Q2
Q3
Q4
6
†
This symbol is in accordance with ANSI/IEEE Standard 91-1984 and IEC Publication 617-12.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
functional block diagram
Words 3 – 14
Same as 2 or 15
Word 16
(last word)
Word 1
(first word)
Word 15
Word 2
4
15
D0
Q0
Same as Q0
Same as D10
14
5
6
7
8
D1
Q1
13
D2
D3
D4
Q2
12
Q3
11
Q4
9
OE
1
19
CLKA
CLKB
C1
1D
17
OR
R
3
UNCK
OUT
16
UNCK
IN
2
IR
18
CLR
SN74S225
16 × 5 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY
WITH 3-STATE OUTPUTS
SDLS207B – SEPTEMBER 1976 – REVISED APRIL 1998
schematics of inputs and outputs
EQUIVALENT OF ALL INPUTS
EXCEPT DATA INPUTS
V
CC
Input
EQUIVALENT OF
DATA INPUTS
TYPICAL OF
ALL OUTPUTS
V
CC
V
CC
58 Ω NOM
Input
Output
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
CC
Input voltage range, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 5.5 V
I
Off-state output voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 5.5 V
Package thermal impedance, θ (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W
JA
stg
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values are with respect to GND.
2. The package thermal impedance is calculated in accordance with JESD 51, except for through-hole packages, which use a trace
length of zero.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74S225
16 × 5 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY
WITH 3-STATE OUTPUTS
SDLS207B – SEPTEMBER 1976 – REVISED APRIL 1998
recommended operating conditions
MIN NOM
MAX UNIT
V
V
V
Supply voltage
4.75
2
5
5.25
V
V
V
CC
IH
IL
High-level input voltage
Low-level input voltage
0.8
–6.5
–3.2
16
Q outputs
I
High-level output current
mA
OH
OL
All other outputs
Q outputs
I
Low-level output current
mA
All other outputs
8
T
A
Operating free-air temperature
0
70
°C
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
†
PARAMETER
TEST CONDITIONS
I = –18 mA
MIN TYP
MAX
UNIT
V
V
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 4.75 V,
= 4.75 V,
= 4.75 V,
= 4.75 V,
= 4.75 V,
= 5.25 V,
= 5.25 V,
= 5.25 V,
–1.2
V
IK
I
Q outputs
All others
Q outputs
All others
I
I
I
I
= –6.5 mA
= –3.2 mA
= 16 mA
= 8 mA
2.4
2.4
2.9
2.9
OL
OL
OL
OL
V
V
OH
0.35
0.35
0.5
0.5
V
OL
I
I
I
V
= 2.4 V
50
µA
µA
OZH
OZL
I
O
O
V
= 0.5 V
–50
1
V = 5.5 V
I
mA
Data
40
I
V
= 5.25 V,
= 5.25 V,
V = 2.7 V
µA
IH
IL
CC
CC
I
All others
Data
25
–1
I
V
V = 0.5 V
I
mA
All others
–0.25
–100
120
‡
I
I
V
V
= 5.25 V,
= 5.25 V
V = 0
O
–30
mA
mA
OS
CC
§
80
CC
CC
†
‡
§
All typical values are at V
= 5 V, T = 25°C.
A
CC
Duration of the short circuit should not exceed one second.
is measured with all inputs grounded and the outputs open.
I
CC
timing requirements over recommended operating conditions (unless otherwise noted) (see
Figure 1)
MIN NOM
MAX UNIT
f
Clock frequency
Pulse duration
10
MHz
ns
clock
w
CLKA or CLKB high
UNCK IN low
CLR low
25
7
t
40
–20
25
70
Data (see Note 3)
CLR inactive
ns
ns
Setup time before CLKA↑ or CLKB↑
Hold time after CLKA↑ or CLKB↑
t
t
su
h
NOTE 3: Data must be set up within 20 ns after the load-clock positive transition.
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74S225
16 × 5 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY
WITH 3-STATE OUTPUTS
SDLS207B – SEPTEMBER 1976 – REVISED APRIL 1998
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 1)
FROM
(INPUT)
TO
(OUTPUT)
†
PARAMETER
TEST CONDITIONS
MIN TYP
MAX
UNIT
CLKA
CLKB
10
10
10
7
20
20
f
C
C
= 30 pF
MHz
max
L
L
UNCK IN
UNCK OUT
OE
20
t
t
t
t
t
t
t
t
= 30 pF
= 5 pF
14
ns
ns
ns
w
Any Q
Any Q
C
10
25
40
dis
L
C
C
C
C
= 30 pF
25
OE
en
L
L
L
L
50
75
PLH
PHL
PLH
PLH
PHL
UNCK IN
CLKA or CLKB
UNCK IN
= 30 pF
= 30 pF
= 30 pF
ns
ns
ns
Any Q
OR
50
75
190
40
300
60
OR
30
45
CLR
CLKA or CLKB
UNCK IN
CLKA or CLKB
UNCK IN
CLR
OR
35
60
25
45
t
UNCK OUT
IR
C
C
= 30 pF
= 30 pF
ns
ns
PHL
L
L
270
55
400
75
255
16
400
35
IR
t
PLH
OR↑
10
20
Any Q
†
All typical values are at V
= 5 V, T = 25°C.
A
CC
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74S225
16 × 5 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY
WITH 3-STATE OUTPUTS
SDLS207B – SEPTEMBER 1976 – REVISED APRIL 1998
PARAMETER MEASUREMENT INFORMATION
7 V
PARAMETER
S1
Open
t
Open
Closed
Open
S1
PZH
t
t
t
en
dis
pd
t
PZL
t
R1 = 500 Ω
PHZ
t
Closed
Open
PLZ
PLH
PHL
From Output
Under Test
Test Point
R2 = 500 Ω
t
t
C
Open
L
(see Note A)
3.5 V
0.3 V
LOAD CIRCUIT FOR 3-STATE OUTPUTS
High-Level
Pulse
1.3 V
1.3 V
1.3 V
t
w
3.5 V
Timing
Input
3.5 V
0.3 V
1.3 V
Low-Level
Pulse
1.3 V
0.3 V
3.5 V
0.3 V
t
h
t
su
VOLTAGE WAVEFORMS
PULSE DURATION
Data
Input
1.3 V
1.3 V
3.5 V
VOLTAGE WAVEFORMS
SET UP AND HOLD TIMES
Output
Control
1.3 V
1.3 V
0.3 V
3.5 V
3.5 V
t
Input
(see Note C)
PZL
t
1.3 V
1.3 V
PLZ
0.3 V
PHL
Waveform 1
S1 Closed
(see Note B)
t
t
PLH
1.3 V
V
OH
In-Phase
Output
V
OL
0.3 V
1.3 V
1.3 V
1.3 V
t
V
OL
PHZ
t
PZH
t
t
PLH
PHL
V
OH
Waveform 2
S1 Open
(see Note B)
V
OH
1.3 V
Out-of-Phase
Output
0.3 V
1.3 V
0 V
V
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
NOTES: A.
C
L
includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, Z = 50 Ω, t ≤ 2 ns, t ≤ 2 ns.
o
r
f
D. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74S225
16 × 5 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY
WITH 3-STATE OUTPUTS
SDLS207B – SEPTEMBER 1976 – REVISED APRIL 1998
APPLICATION INFORMATION
CLR
CLKA
CLKB
Word 1
Word 2
Word 16
D
Word 3
is Low
UNCK
IN
IR
UNCK
OUT
OR
Q
Word 1
Word 1
Word 2
Word 3
Word
16
Load
Words 3–15
Unload
Word 1
Unload
Words 3–15
Clear
Load
Word 1
Load
Word 2
Load
Word 16
Unload
Word 2
Unload
Word 16
Figure 2. Typical Waveforms for a 16-Word FIFO
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74S225
16 × 5 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY
WITH 3-STATE OUTPUTS
SDLS207B – SEPTEMBER 1976 – REVISED APRIL 1998
APPLICATION INFORMATION
(high)
(high)
NC
(high)
NC
CLKB
CLKA
CLKB
CLKA
CLKB
CLKA
OR
CLK
NC
OR
OR
OR
UNCK
UNCK
UNCK
OUT
OUT
OUT
UNCK
IN
UNCK
IN
UNCK
IN
UNCK IN
IR
IR
IR
D0
D1
D2
D3
D4
Q0
D0
D1
D2
D3
D4
Q0
D0
D1
D2
D3
D4
Q0
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
5-Bit
Data
In
5-Bit
Data
Out
CLR OE
CLR OE
CLR OE
CLR
IR
OE
CLR OE
CLKB
CLR OE
CLKB
CLR OE
CLKB
(high)
(high)
NC
(high)
NC
CLKA
CLKA
CLKA
OR
OR
OR
UNCK
UNCK
UNCK
NC
OUT
OUT
OUT
UNCK
IN
UNCK
IN
UNCK
IN
IR
IR
IR
D0
D1
D2
D3
D4
Q0
D0
D1
D2
D3
D4
Q0
D0
D1
D2
D3
D4
Q0
5-Bit
Data
In
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
5-Bit
Data
Out
Figure 3. Word-Width Expansion: 48 × 10 Bits
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1999, Texas Instruments Incorporated
相关型号：
©2020 ICPDF网 联系我们和版权申明