74VMEH22501DGVRE4 [TI]
8-BIT UNIVERSAL BUS TRANSCEIVER AND TWO 1-BIT BUS TRANSCEIVERS WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND 3-STATE OUTPUTS; 8位通用总线收发器和具备SPLIT LVTTL端口，反馈路径中的两个1位总线收发器和三态输出
| 型号： | 74VMEH22501DGVRE4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 8-BIT UNIVERSAL BUS TRANSCEIVER AND TWO 1-BIT BUS TRANSCEIVERS WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND 3-STATE OUTPUTS |
| 文件： | 总31页 (文件大小：568K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74VMEH22501
www.ti.com
SCES357F –JULY 2001–REVISED FEBRUARY 2010
8-BIT UNIVERSAL BUS TRANSCEIVER AND TWO 1-BIT BUS TRANSCEIVERS
WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND 3-STATE OUTPUTS
Check for Samples: SN74VMEH22501
1
FEATURES
•
Member of the Texas Instruments Widebus™
Family
•
ESD Protection Exceeds JESD 22
–
–
–
2000-V Human-Body Model (A114-A)
200-V Machine Model (A115-A)
•
UBT™ Transceiver Combines D-Type Latches
and D-Type Flip-Flops for Operation in
Transparent, Latched, or Clocked Modes
1000-V Charged-Device Model (C101)
DGG OR DGV PACKAGE
(TOP VIEW)
•
•
•
OEC™ Circuitry Improves Signal Integrity and
Reduces Electromagnetic Interference (EMI)
Compliant With VME64, 2eVME, and 2eSST
Protocol
Bus Transceiver Split LVTTL Port Provides a
Feedback Path for Control and Diagnostics
Monitoring
•
•
•
•
I/O Interfaces Are 5-V Tolerant
B-Port Outputs (–48 mA/64 mA)
Y and A-Port Outputs (–12 mA/12 mA)
Ioff, Power-Up 3-State, and BIAS VCC Support
Live Insertion
•
•
Bus Hold on 3A-Port Data Inputs
26-Ω Equivalent Series Resistor on 3A Ports
and Y Outputs
•
•
•
Flow-Through Architecture Facilitates Printed
Circuit Board Layout
Distributed VCC and GND Pins Minimize
High-Speed Switching Noise
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
DESCRIPTION/ORDERING INFORMATION
The SN74VMEH22501 8-bit universal bus transceiver has two integral 1-bit three-wire bus transceivers and is
designed for 3.3-V VCC operation with 5-V tolerant inputs. The UBT™ transceiver allows transparent, latched, and
flip-flop modes of data transfer, and the separate LVTTL input and outputs on the bus transceivers provide a
feedback path for control and diagnostics monitoring. This device provides a high-speed interface between cards
operating at LVTTL logic levels and VME64, VME64x, or VME320(1) backplane topologies.
(1) VME320 is a patented backplane construction by Arizona Digital, Inc.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2001–2010, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
SN74VMEH22501
SCES357F –JULY 2001–REVISED FEBRUARY 2010
www.ti.com
DESCRIPTION/ORDERING INFORMATION (CONTINUED)
High-speed backplane operation is a direct result of the improved OEC™ circuitry and high drive that has been
designed and tested into the VME64x backplane model. The B-port I/Os are optimized for driving large capacitive
loads and include pseudo-ETL input thresholds (½ VCC ± 50 mV) for increased noise immunity. These
specifications support the 2eVME protocols in VME64x (ANSI/VITA 1.1) and 2eSST protocols in VITA 1.5. With
proper design of a 21-slot VME system, a designer can achieve 320-Mbyte transfer rates on linear backplanes
and, possibly, 1-Gbyte transfer rates on the VME320 backplane.
All inputs and outputs are 5-V tolerant and are compatible with TTL and 5-V CMOS inputs.
Active bus-hold circuitry holds unused or undriven 3A-port inputs at a valid logic state. Bus-hold circuitry is not
provided on 1A or 2A inputs, any B-port input, or any control input. Use of pullup or pulldown resistors with the
bus-hold circuitry is not recommended.
This device is fully specified for live-insertion applications using Ioff, power-up 3-state, and BIAS VCC. The Ioff
circuitry prevents damaging current to backflow through the device when it is powered off/on. The power-up
3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents
driver conflict. The BIAS VCC circuitry precharges and preconditions the B-port input/output connections,
preventing disturbance of active data on the backplane during card insertion or removal, and permits true
live-insertion capability.
When VCC is between 0 and 1.5 V, the device is in the high-impedance state during power up or power down.
However, to ensure the high-impedance state above 1.5 V, output-enable (OE and OEBY) inputs should be tied
to VCC through a pullup resistor and output-enable (OEAB) inputs should be tied to GND through a pulldown
resistor; the minimum value of the resistor is determined by the drive capability of the device connected to this
input.
ORDERING INFORMATION
TA
PACKAGE(1)
ORDERABLE PART NUMBER
TOP-SIDE MARKING
VK501
BGA MicroStar™
Junior – ZQL
Tape and reel
SN74VMEH22501ZQLR
TSSOP – DGG
TVSOP – DGV
VFBGA – GQL
Tape and reel
Tape and reel
Tape and reel
SN74VMEH22501DGGR
SN74VMEH22501DGVR
SN74VMEH22501GQLR
VMEH22501
VK501
0°C to 85°C
VK501
(1) Package drawings, thermal data, and symbolization are available at www.ti.com/sc/packaging.
2
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SCES357F –JULY 2001–REVISED FEBRUARY 2010
GQL OR ZQL PACKAGE
(TOP VIEW)
TERMINAL ASSIGNMENTS(1)
1
1OEBY
1Y
2
3
4
5
NC
6
1OEAB
1B
A
B
C
D
E
F
NC
NC
NC
1A
GND
VCC
GND
GND
VCC
GND
VCC
2Y
2A
BIAS VCC
2OEAB
VCC
2B
3A1
3A2
3A3
3A4
3A5
3A7
DIR
2OEBY
LE
3B1
3B2
3B3
3B4
3B5
3B7
VCC
OE
VCC
G
H
J
CLKBA
3A6
3A8
NC
GND
VCC
GND
NC
GND
VCC
GND
NC
CLKAB
3B6
3B8
K
NC
(1) NC - No internal connection
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SN74VMEH22501
SCES357F –JULY 2001–REVISED FEBRUARY 2010
www.ti.com
FUNCTIONAL DESCRIPTION
The SN74VMEH22501 is a high-drive (–48/64 mA), 8-bit UBT transceiver containing D-type latches and D-type
flip-flops for data-path operation in transparent, latched, or flip-flop modes. Data transmission is true logic. The
device is uniquely partitioned as 8-bit UBT transceivers with two integrated 1-bit three-wire bus transceivers.
Functional Description for Two 1-Bit Bus Transceivers
The OEAB inputs control the activity of the 1B or 2B port. When OEAB is high, the B-port outputs are active.
When OEAB is low, the B-port outputs are disabled.
Separate 1A and 2A inputs and 1Y and 2Y outputs provide a feedback path for control and diagnostics
monitoring. The OEBY inputs control the 1Y or 2Y outputs. When OEBY is low, the Y outputs are active. When
OEBY is high, the Y outputs are disabled.
The OEBY and OEAB inputs can be tied together to form a simple direction control where an input high yields
A data to B bus and an input low yields B data to Y bus.
1-BIT BUS TRANSCEIVER FUNCTION TABLE
INPUTS
OUTPUT
MODE
Isolation
OEAB
OEBY
L
H
L
H
H
L
Z
A data to B bus
True driver
B data to Y bus
H
L
A data to B bus, B data to Y bus
True driver with feedback path
Functional Description for 8-Bit UBT Transceiver
The 3A and 3B data flow in each direction is controlled by the OE and direction-control (DIR) inputs. When OE is
low, all 3A- or 3B-port outputs are active. When OE is high, all 3A- or 3B-port outputs are in the high-impedance
state.
FUNCTION TABLE
INPUTS
OUTPUT
OE DIR
H
L
L
X
H
L
Z
3A data to 3B bus
3B data to 3A bus
The UBT transceiver functions are controlled by latch-enable (LE) and clock (CLKAB and CLKBA) inputs. For
3A-to-3B data flow, the UBT operates in the transparent mode when LE is high. When LE is low, the 3A data is
latched if CLKAB is held at a high or low logic level. If LE is low, the 3A data is stored in the latch/flip-flop on the
low-to-high transition of CLKAB.
The UBT transceiver data flow for 3B to 3A is similar to that of 3A to 3B, but uses CLKBA.
4
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SCES357F –JULY 2001–REVISED FEBRUARY 2010
Table 1. UBT TRANSCEIVER FUNCTION TABLE(1)
INPUTS
CLKAB
OUTPUT
3B
MODE
Isolation
OE
H
L
LE
X
L
3A
X
X
X
L
X
H
L
Z
(2)
B0
Latched storage of 3A data
(3)
L
L
B0
L
H
H
L
X
X
↑
L
H
L
True transparent
L
H
L
L
Clocked storage of 3A data
L
L
↑
H
H
(1) 3A-to-3B data flow is shown; 3B-to-3A data flow is similar, but uses CLKBA.
(2) Output level before the indicated steady-state input conditions were established, provided that CLKAB
was high before LE went low
(3) Output level before the indicated steady-state input conditions were established
The UBT transceiver can replace any of the functions shown in Table 2.
Table 2. SN74VMEH22501 UBT Transceiver
Replacement Functions
FUNCTION
8 BIT
'245, '623, '645
'241, '244, '541
'543
Transceiver
Buffer/driver
Latched transceiver
Latch
'373, '573
'646, '652
'374, '574
Registered transceiver
Flip-flop
SN74VMEH22501 UBT transceiver replaces all above functions
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LOGIC DIAGRAM (POSITIVE LOGIC)
48
1OEAB
1
1OEBY
2
46
1A
1B
3
1Y
41
2OEAB
8
2OEBY
5
43
2A
2B
6
2Y
14
OE
24
DIR
32
CLKAB
11
LE
17
CLKBA
9
40
3A1
1D
C1
CLK
3B1
1D
C1
CLK
To Seven Other Channels
Pin numbers shown are for the DGG and DGV packages.
6
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SCES357F –JULY 2001–REVISED FEBRUARY 2010
Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
VCC
BIAS VCC
,
Supply voltage range
–0.5
4.6
V
VI
Input voltage range(2)
Voltage range applied to any output in the high-impedance or power-off state(2)
–0.5
–0.5
–0.5
–0.5
7
7
V
V
VO
3A port or Y output
B port
VCC + 0.5
4.6
Voltage range applied to any output in the high or low
state(2)
VO
V
3A port or Y output
B port
50
IO
Output current in the low state
Output current in the high state
mA
mA
100
–50
–100
–50
–50
70
3A port or Y output
B port
IO
IIK
Input clamp current
Output clamp current
VI < 0
mA
mA
IOK
VO < 0 or VO > VCC, B port
DGG package
DGV package
GQL/ZQL package
qJA
Package thermal impedance(3)
58
°C/W
°C
42
Tstg
Storage temperature range
–65
150
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
(3) The package thermal impedance is calculated in accordance with JESD 51-7.
Recommended Operating Conditions(1) (2)
MIN
NOM
MAX
UNIT
VCC
BIAS VCC
,
Supply voltage
Input voltage
3.15
3.3
3.45
V
Control inputs or A port
B port
VCC
VCC
5.5
5.5
VI
V
V
Control inputs or A port
B port
2
VIH
High-level input voltage
0.5 VCC + 50 mV
Control inputs or A port
B port
0.8
VIL
IIK
Low-level input voltage
Input clamp current
V
0.5 VCC – 50 mV
–18
–12
–48
12
mA
mA
3A port and Y output
B port
IOH
High-level output current
3A port and Y output
B port
IOL
Low-level output current
mA
64
Δt/Δv
Δt/ΔVCC
TA
Input transition rise or fall rate
Power-up ramp rate
Outputs enabled
10
ns/V
ms/V
°C
20
0
Operating free-air temperature
85
(1) All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
(2) Proper connection sequence for use of the B-port I/O precharge feature is GND and BIAS VCC = 3.3 V first, I/O second, and VCC = 3.3 V
last, because the BIAS VCC precharge circuitry is disabled when any VCC pin is connected. The control inputs can be connected at any
time, but normally are connected during the I/O stage. If B-port precharge is not required, any connection sequence is acceptable, but
generally, GND is connected first.
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Electrical Characteristics
over recommended operating free-air temperature range for A and B ports (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP(1) MAX UNIT
VIK
VCC = 3.15 V,
II = –18 mA
–1.2
V
3A port, any B ports,
and Y outputs
VCC = 3.15 V to 3.45 V,
VCC = 3.15 V
IOH = –100 mA
VCC – 0.2
IOH = –6 mA
IOH = –12 mA
IOH = –24 mA
IOH = –48 mA
2.4
2
3A port and Y outputs
Any B port
VOH
V
2.4
2
VCC = 3.15 V
3A port, any B ports,
and Y outputs
VCC = 3.15 V to 3.45 V,
VCC = 3.15 V
IOL = 100 mA
0.2
IOL = 6 mA
0.55
0.8
0.4
0.55
0.6
±1
3A port and Y outputs
IOL = 12 mA
IOL = 24 mA
IOL = 48 mA
IOL = 64 mA
VI = VCC or GND
VI = 5.5 V
VOL
V
Any B port
VCC = 3.15 V
VCC = 3.45 V,
Control inputs,
1A and 2A
II
mA
mA
mA
VCC = 0 or 3.45 V,
5
3A port, any B port,
and Y outputs
(2)
(2)
IOZH
IOZL
VCC = 3.45 V,
VCC = 3.45 V,
VO = VCC or 5.5 V
VO = GND
5
3A port and Y outputs
Any B port
–5
–20
±10
Ioff
VCC = 0, BIAS VCC = 0,
VCC = 3.15 V,
VI or VO = 0 to 5.5 V
VI = 0.8 V
mA
mA
mA
mA
mA
(3)
(4)
IBHL
IBHH
3A port
3A port
3A port
3A port
75
–75
VCC = 3.15 V,
VI = 2 V
(5)
(6)
IBHLO
IBHHO
VCC = 3.45 V,
VI = 0 to VCC
VI = 0 to VCC
500
VCC = 3.45 V,
–500
V
CC ≤ 1.5 V, VO = 0.5 V to VCC,
(7)
IOZ(PU/PD)
±10
mA
VI = GND or VCC, OE = don't care
Outputs high
30
30
30
VCC = 3.45 V, IO = 0,
VI = VCC or GND
ICC
Outputs low
mA
Outputs disabled
Outputs enabled
VCC = 3.45 V, IO = 0,
VI = VCC or GND,
One data input switching at
one-half clock frequency,
50% duty cycle
76
19
mA/
clock
MHz/
input
ICCD
Outputs disabled
VCC = 3.15 V to 3.45 V, One input at VCC – 0.6 V,
Other inputs at VCC or GND
(8)
ΔICC
750
mA
(1) All typical values are at VCC = 3.3 V, TA = 25°C.
(2) For I/O ports, the parameters IOZH and IOZL include the input leakage current.
(3) The bus-hold circuit can sink at least the minimum low sustaining current at VIL max. IBHL should be measured after lowering VIN to
GND, then raising it to VIL max.
(4) The bus-hold circuit can source at least the minimum high sustaining current at VIH min. IBHH should be measured after raising VIN to
VCC, then lowering it to VIH min.
(5) An external driver must source at least IBHLO to switch this node from low to high.
(6) An external driver must sink at least IBHHO to switch this node from high to low.
(7) High-impedance state during power up or power down
(8) This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCC or GND.
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Electrical Characteristics (continued)
over recommended operating free-air temperature range for A and B ports (unless otherwise noted)
PARAMETER
1A and 2A inputs
Control inputs
1Y or 2Y outputs
3A port
TEST CONDITIONS
MIN TYP(1) MAX UNIT
2.8
Ci
VI = 3.15 V or 0
VO = 3.15 V or 0
VCC = 3.3 V,
pF
2.6
Co
Cio
5.6
pF
pF
7.9
VO = 3.3 V or 0
Any B port
11 12.5
Live-Insertion Specifications
over recommended operating free-air temperature range for B port
PARAMETER
TEST CONDITIONS
MIN TYP(1)
MAX UNIT
VCC = 0 to 3.15 V,
VCC = 3.15 V to 3.45 V(2)
VCC = 0,
BIAS VCC = 3.15 V to 3.45 V, IO(DC) = 0
BIAS VCC = 3.15 V to 3.45 V, IO(DC) = 0
BIAS VCC = 3.15 V to 3.45 V
5
10
mA
mA
V
ICC (BIAS VCC
)
,
VO
IO
1.3
–20
20
1.5
1.7
VO = 0,
BIAS VCC = 3.15 V
BIAS VCC = 3.15 V
–100
100
VCC = 0
mA
VO = 3 V,
(1) All typical values are at VCC = 3.3 V, TA = 25°C.
(2) VCC – 0.5 V < BIAS VCC
Timing Requirements for UBT Transceiver
over recommended operating conditions (unless otherwise noted) (see Figure 1 and Figure 2)
MIN
MAX UNIT
fclock
tw
Clock frequency
Pulse duration
120
MHz
LE high
2.5
3
ns
CLK high or low
Data high
2.1
2.2
2
3A before CLK↑
3A before LE↓
3B before CLK↑
3B before LE↓
3A after CLK↑
3A after LE↓
Data low
CLK high
CLK low
Data high
Data low
CLK high
CLK low
Data high
Data low
CLK high
CLK low
Data high
Data low
CLK high
CLK low
2
tsu
Setup time
ns
2.5
2.7
2
2
0
0
1
1
th
Hold time
ns
0
3B after CLK↑
3B after LE↓
0
1
1
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Switching Characteristics for Bus Transceiver Function
over recommended operating conditions (unless otherwise noted) (see Figure 1 and Figure 2)
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
MIN
TYP
MAX UNIT
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tr
5.1
4.5
7.2
6.1
4.6
3.7
3.3
1.8
8.9
ns
1A or 2A
1A or 2A
OEAB
1B or 2B
1Y or 2Y
1B or 2B
1B or 2B
7.8
14.5
ns
13
8.1
ns
7.4
9.7
ns
OEAB
4.8
Transition time, B port (10%–90%)
Transition time, B port (90%–10%)
4.3
4.3
ns
ns
tf
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
1.6
1.6
1.2
1.8
1.4
1.7
5.6
ns
1B or 2B
1Y or 2Y
1Y or 2Y
1Y or 2Y
5.6
5.6
ns
OEBY
OEBY
4.9
5.4
ns
4.5
10
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Switching Characteristics for UBT Transceiver
over recommended operating conditions (unless otherwise noted) (see Figure 1 and Figure 2)
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
MIN
TYP
MAX UNIT
fmax
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tr
120
5.5
4.7
6
MHz
9.3
ns
3A
LE
3B
3B
3B
3B
3B
8.3
10.6
ns
4.9
5.8
4.6
4.6
3.5
4.8
2.4
8.7
10.1
ns
CLKAB
OE
8.4
9.3
ns
8.5
9.3
ns
OE
5.7
Transition time, B port (10%–90%)
Transition time, B port (90%–10%)
4.3
4.3
ns
ns
tf
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
1.7
1.7
1.7
1.7
1.4
1.4
1.5
2.1
1.8
2.3
5.9
ns
3B
3A
3A
3A
3A
3A
5.9
5.9
ns
LE
CLKBA
OE
5.9
5.5
ns
5.5
6.2
ns
5.5
6.2
ns
OE
5.6
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Skew Characteristics for Bus Transceiver
for specific worst-case VCC and temperature within the recommended ranges of supply voltage and operating free-air
temperature (see Figure 1 and Figure 2)
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
MIN
MAX UNIT
tsk(LH)
tsk(HL)
tsk(LH)
tsk(HL)
0.8
ns
1A or 2A
1B or 2B
1B or 2B
1Y or 2Y
0.7
0.7
ns
0.6
1A or 2A
1B or 2B
1A or 2A
1B or 2B
1B or 2B
1Y or 2Y
1B or 2B
1Y or 2Y
1.7
ns
(1)
tsk(t)
1.2
2.8
ns
tsk(pp)
1.4
(1) tsk(t) – Output-to-output skew is defined as the absolute value of the difference between the actual propagation delay for all outputs of
the same packaged device. The specifications are given for specific worst-case VCC and temperature and apply to any outputs switching
in opposite directions, both low to high (LH) and high to low (HL) [tsk(t)].
Skew Characteristics for UBT
for specific worst-case VCC and temperature within the recommended ranges of supply voltage and operating free-air
temperature (see Figure 1 and Figure 2)
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
MIN
MAX UNIT
tsk(LH)
tsk(HL)
tsk(LH)
tsk(HL)
tsk(LH)
tsk(HL)
tsk(LH)
tsk(HL)
1.3
ns
3A
3B
3B
3A
3A
1.1
0.8
ns
CLKAB
3B
0.8
0.7
ns
0.6
0.7
ns
CLKBA
0.6
3A
CLKAB
3B
3B
3B
3A
3A
3B
3B
3A
3A
1.9
2.1
ns
(1)
tsk(t)
1.2
CLKBA
3A
1
2.8
CLKAB
3B
2.7
ns
tsk(pp)
1.3
CLKBA
1.2
(1) tsk(t) – Output-to-output skew is defined as the absolute value of the difference between the actual propagation delay for all outputs of
the same packaged device. The specifications are given for specific worst-case VCC and temperature and apply to any outputs switching
in opposite directions, both low to high (LH) and high to low (HL) [tsk(t)].
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SCES357F –JULY 2001–REVISED FEBRUARY 2010
PARAMETER MEASUREMENT INFORMATION
A PORT
6 V
Open
S1
500 Ω
From Output
Under Test
TEST
/t
S1
GND
t
Open
6 V
GND
Open
PLH PHL
C = 50 pF
L
t
t
/t
PLZ PZL
500 Ω
(see Note A)
/t
PHZ PZH
B-to-A Skew
LOAD CIRCUIT
t
w
3 V
0 V
3 V
0 V
1.5 V
Input
1.5 V
Timing
Input
1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
t
su
t
h
3 V
0 V
Data
Input
3 V
0 V
V
/2
V /2
CC
CC
1.5 V
1.5 V
Output Control
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
t
t
PZL
PLZ
Output
Waveform 1
S1 at 6 V
3 V
V
3 V
0 V
1.5 V
Input
V
V
+ 0.3 V
V /2
CC
V /2
CC
OL
(see Note B)
OL
t
t
PZH
PHZ
t
t
PHL
PLH
Output
Waveform 2
S1 at GND
V
OH
V
V
OH
- 0.3 V
OH
1.5 V
Output
1.5 V
1.5 V
≈0 V
(see Note B)
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≈ 10 MHz, Z = 50 Ω, t ≈ 2 ns, t ≈ 2 ns.
O
r
f
D. The outputs are measured one at a time, with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
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PARAMETER MEASUREMENT INFORMATION
B PORT
6 V
Open
S1
500 Ω
From Output
Under Test
TEST
/t
S1
GND
t
Open
6 V
GND
Open
PLH PHL
C = 50 pF
L
t
t
/t
PLZ PZL
500 Ω
(see Note A)
/t
PHZ PZH
A-to-B Skew
LOAD CIRCUIT
t
w
3 V
0 V
3 V
0 V
Input
1.5 V
1.5 V
Timing
Input
1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
t
su
t
h
3 V
0 V
Data
Input
3 V
0 V
1.5 V
1.5 V
1.5 V
1.5 V
Output Control
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
t
t
PLZ
PZL
Output
Waveform 1
S1 at 6 V
3 V
3 V
0 V
V
/2
CC
Input
1.5 V
1.5 V
V
+ 0.3 V
OL
V
(see Note B)
OL
OH
t
t
PHZ
PZH
t
t
PHL
PLH
Output
Waveform 2
S1 at GND
V
V
V
OH
V
OH
- 0.3 V
V
/2
CC
Output
V /2
CC
V /2
CC
≈0 V
(see Note B)
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≈ 10 MHz, Z = 50 Ω, t ≈ 2 ns, t ≈ 2 ns.
O
r
f
D. The outputs are measured one at a time, with one transition per measurement.
Figure 2. Load Circuit and Voltage Waveforms
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SCES357F –JULY 2001–REVISED FEBRUARY 2010
Distributed-Load Backplane Switching Characteristics
The preceding switching characteristics tables show the switching characteristics of the device into the lumped
load shown in the parameter measurement information (PMI) (see Figure 1 and Figure 2). All logic devices
currently are tested into this type of load. However, the designer's backplane application probably is a distributed
load. For this reason, this device has been designed for optimum performance in the VME64x backplane as
shown in Figure 3.
5 V
5 V
330 Ω
0.42”
330 Ω
0.42”
0.42”
0.84”
0.84”
0.42”
†
Z
O
470 Ω
470 Ω
Conn.
Conn.
Conn.
Conn.
Conn.
Conn.
‡
Z
O
1.5”
1.5”
1.5”
1.5”
1.5”
1.5”
Rcvr
Rcvr
Rcvr
Rcvr
Rcvr
Drvr
Slot 1
Slot 2
Slot 3
Slot 19
Slot 20
Slot 21
†
‡
Unloadedbackplane trace natural impedence (Z ) is 45 Ω. 45 Ω to 60 Ω is allowed, with 50 Ω being ideal.
O
Card stub natural impedence (Z ) is 60 Ω.
O
Figure 3. VME64x Backplane
The following switching characteristics tables derived from TI-SPICE models show the switching characteristics
of the device into the backplane under full and minimum loading conditions, to help the designer better
understand the performance of the VME device in this typical backplane. See www.ti.com/sc/etl for more
information.
Driver in Slot 11, With Receiver Cards in All Other Slots (Full Load)
Switching Characteristics for Bus Transceiver Function
over recommended operating conditions (unless otherwise noted) (see Figure 3)
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
MIN TYP(1)
MAX UNIT
tPLH
tPHL
5.9
5.5
8.5
ns
1A or 2A
1B or 2B
8.7
(2)
tr
Transition time, B port (10%–90%)
Transition time, B port (90%–10%)
9
8.6
9
11.4
10.8
ns
ns
(2)
tf
8.9
(1) All typical values are at VCC = 3.3 V, TA = 25°C. All values are derived from TI-SPICE models.
(2) All tr and tf times are taken at the first receiver.
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Switching Characteristics for UBT
over recommended operating conditions (unless otherwise noted) (see Figure 3)
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
MIN TYP(1)
MAX UNIT
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
6.2
5.6
6.1
5.6
6.2
5.7
8.9
ns
9
3A
LE
3B
3B
3B
9.1
ns
9
9.1
ns
9
CLKAB
(2)
tr
Transition time, B port (10%–90%)
Transition time, B port (90%–10%)
9
8.6
9
11.4
10.8
ns
ns
(2)
tf
8.9
(1) All typical values are at VCC = 3.3 V, TA = 25°C. All values are derived from TI-SPICE models.
(2) All tr and tf times are taken at the first receiver.
Skew Characteristics for Bus Transceiver
for specific worst-case VCC and temperature within the recommended ranges of supply voltage and operating free-air
temperature (see Figure 3)
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
MIN TYP(1)
MAX UNIT
tsk(LH)
tsk(HL)
2.5
ns
3
1A or 2A
1B or 2B
(2)
tsk(t)
1A or 2A
1A or 2A
1B or 2B
1B or 2B
1
ns
ns
tsk(pp)
0.5
3.4
(1) All typical values are at VCC = 3.3 V, TA = 25°C. All values are derived from TI-SPICE models.
(2) tsk(t) – Output-to-output skew is defined as the absolute value of the difference between the actual propagation delay for all outputs of
the same packaged device. The specifications are given for specific worst-case VCC and temperature and apply to any outputs switching
in opposite directions, both low to high (LH) and high to low (HL) [tsk(t)].
Skew Characteristics for UBT
for specific worst-case VCC and temperature within the recommended ranges of supply voltage and operating free-air
temperature (see Figure 3)
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
MIN TYP(1)
MAX UNIT
tsk(LH)
tsk(HL)
tsk(LH)
tsk(HL)
2.4
ns
3A
3B
3B
3.4
2.7
ns
CLKAB
3.4
3A
3B
3B
3B
3B
1
(2)
tsk(t)
ns
1
CLKAB
3A
0.5
0.6
3.4
ns
tsk(pp)
CLKAB
3.5
(1) All typical values are at VCC = 3.3 V, TA = 25°C. All values are derived from TI-SPICE models.
(2) tsk(t) – Output-to-output skew is defined as the absolute value of the difference between the actual propagation delay for all outputs of
the same packaged device. The specifications are given for specific worst-case VCC and temperature and apply to any outputs switching
in opposite directions, both low to high (LH) and high to low (HL) [tsk(t)].
Driver in Slot 1, With One Receiver in Slot 21 (Minimum Load)
Switching Characteristics for Bus Transceiver Function
over recommended operating conditions (unless otherwise noted) (see Figure 3)
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SCES357F –JULY 2001–REVISED FEBRUARY 2010
Switching Characteristics for Bus Transceiver Function (continued)
over recommended operating conditions (unless otherwise noted) (see Figure 3)
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
MIN TYP(1)
MAX UNIT
tPLH
tPHL
5.5
5.3
7.4
ns
1A or 2A
1B or 2B
7.4
(2)
tr
Transition time, B port (10%–90%)
Transition time, B port (90%–10%)
3.9
3.7
3.4
3.4
4.4
4.8
ns
ns
(2)
tf
(1) All typical values are at VCC = 3.3 V, TA = 25°C. All values are derived from TI-SPICE models.
(2) All tr and tf times are taken at the first receiver.
Switching Characteristics for UBT
over recommended operating conditions (unless otherwise noted) (see Figure 3)
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
MIN TYP(1)
MAX UNIT
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
5.8
5.5
5.9
5.5
5.9
5.5
7.9
ns
3A
LE
3B
3B
3B
7.7
8
ns
7.8
8.1
ns
CLKAB
7.7
(2)
tr
Transition time, B port (10%–90%)
Transition time, B port (90%–10%)
3.9
3.7
3.4
3.4
4.4
4.8
ns
ns
(2)
tf
(1) All typical values are at VCC = 3.3 V, TA = 25°C. All values are derived from TI-SPICE models.
(2) All tr and tf times are taken at the first receiver.
Skew Characteristics for Bus Transceiver
for specific worst-case VCC and temperature within the recommended ranges of supply voltage and operating free-air
temperature (see Figure 3)
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
MIN TYP(1)
MAX UNIT
tsk(LH)
tsk(HL)
1.7
ns
1A or 2A
1B or 2B
2.1
(2)
tsk(t)
1A or 2A
1A or 2A
1B or 2B
1B or 2B
1
ns
ns
tsk(pp)
0.2
2.1
(1) All typical values are at VCC = 3.3 V, TA = 25°C. All values are derived from TI-SPICE models.
(2) tsk(t) – Output-to-output skew is defined as the absolute value of the difference between the actual propagation delay for all outputs of
the same packaged device. The specifications are given for specific worst-case VCC and temperature and apply to any outputs switching
in opposite directions, both low to high (LH) and high to low (HL) [tsk(t)].
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Skew Characteristics for UBT
for specific worst-case VCC and temperature within the recommended ranges of supply voltage and operating free-air
temperature (see Figure 3)
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
MIN TYP(1)
MAX UNIT
tsk(LH)
tsk(HL)
tsk(LH)
tsk(HL)
2
ns
3A
3B
3B
2.3
2.1
ns
CLKAB
2.4
3A
3B
3B
3B
3B
1
(2)
tsk(t)
ns
1
CLKAB
3A
0.2
0.2
2.5
ns
tsk(pp)
CLKAB
2.9
(1) All typical values are at VCC = 3.3 V, TA = 25°C. All values are derived from TI-SPICE models.
(2) tsk(t) – Output-to-output skew is defined as the absolute value of the difference between the actual propagation delay for all outputs of
the same packaged device. The specifications are given for specific worst-case VCC and temperature and apply to any outputs switching
in opposite directions, both low to high (LH) and high to low (HL) [tsk(t)].
By simulating the performance of the device using the VME64x backplane (see Figure 3), the maximum peak
current in or out of the B-port output, as the devices switch from one logic state to another, was found to be
equivalent to driving the lumped load shown in Figure 4.
5 V
165 Ω
From Output
Under Test
235 Ω
390 pF
LOAD CIRCUIT
Figure 4. Equivalent AC Peak Output-Current Lumped Load
In general, the rise- and fall-time distribution is shown in Figure 5. Since VME devices were designed for use into
distributed loads like the VME64x backplane (B/P), there are significant differences between low-to-high (LH) and
high-to-low (HL) values in the lumped load shown in the PMI (see Figure 1 and Figure 2).
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6.4
6.2
6.0
5.8
5.6
5.4
5.2
5.0
LH
HL
Full B/P Load
Minimum B/P Load
PMI Lumped Load
Figure 5.
Characterization-laboratory data in Figure 6 and Figure 7 show the absolute ac peak output current, with different
supply voltages, as the devices change output logic state. A typical nominal process is shown to demonstrate the
devices' peak ac output drive capability.
137
162
136
160
135
158
134
156
133
154
132
152
131
150
130
148
129
146
128
3.15
3.30
3.45
144
3.15
3.30
- V
3.45
V
- V
CC
V
CC
Figure 6.
Figure 7.
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TYPICAL CHARACTERISTICS
SUPPLY CURRENT
vs
SUPPLY CURRENT
vs
FREQUENCY
FREQUENCY
B TO A
A TO B
35
30
V
CC
= 3.15 V
30
25
20
15
10
5
25
V = 3.45 V
CC
V
CC
= 3.3 V
V
CC
= 3.3 V
20
15
10
5
V
CC
= 3.45 V
V
CC
= 3.15 V
20
40
60
80
100
120
20
40
60
80
100
120
f - Switching Frequency - MHz
f − Switching Frequency − MHz
Figure 8.
Figure 9.
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TYPICAL CHARACTERISTICS
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
300
250
200
150
100
50
V
= 3.15 V
CC
V
CC
= 3.3 V
V
= 3.45 V
CC
0
0
10
20
30
40
50
60
70
80
90
100
I
- High-Level Output Current - mA
OH
Figure 10. VOL vs IOL
<br/>
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
V
= 3.45 V
CC
V
CC
= 3.3 V
V
= 3.15 V
CC
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
I
- Low-Level Output Current - mA
OL
Figure 11. VOH vs IOH
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VMEbus Summary
In 1981, the VMEbus was introduced as a backplane bus architecture for industrial and commercial applications.
The data-transfer protocols used to define the VMEbus came from the Motorola™ VERSA bus architecture that
owed its heritage to the then recently introduced Motorola 68000 microprocessor. The VMEbus, when
introduced, defined two basic data-transfer operations: single-cycle transfers consisting of an address and a data
transfer, and a block transfer (BLT) consisting of an address and a sequence of data transfers. These transfers
were asynchronous, using a master-slave handshake. The master puts address and data on the bus and waits
for an acknowledgment. The selected slave either reads or writes data to or from the bus, then provides a
data-acknowledge (DTACK*) signal. The VMEbus system data throughput was 40 Mbyte/s. Previous to the
VMEbus, it was not uncommon for the backplane buses to require elaborate calculations to determine loading
and drive current for interface design. This approach made designs difficult and caused compatibility problems
among manufacturers. To make interface design easier and to ensure compatibility, the developers of the
VMEbus architecture defined specific delays based on a 21-slot terminated backplane and mandated the use of
certain high-current TTL drivers, receivers, and transceivers.
In 1989, multiplexing block transfer (MBLT) effectively increased the number of bits from 32 to 64, thereby
doubling the transfer rate. In 1995, the number of handshake edges was reduced from four to two in the
double-edge transfer (2eVME) protocol, doubling the data rate again. In 1997, the VMEbus International Trade
Association (VITA) established a task group to specify a synchronous protocol to increase data-transfer rates to
320 Mbyte/s, or more. The unreleased specification, VITA 1.5 [double-edge source synchronous transfer
(2eSST)], is based on the asynchronous 2eVME protocol. It does not wait for acknowledgement of the data by
the receiver and requires incident-wave switching. Sustained data rates of 1 Gbyte/s, more than ten times faster
than traditional VME64 backplanes, are possible by taking advantage of 2eSST and the 21-slot VME320
star-configuration backplane. The VME320 backplane approximates a lumped load, allowing substantially
higher-frequency operation over the VME64x distributed-load backplane. Traditional VME64 backplanes with no
changes theoretically can sustain 320 Mbyte/s.
From BLT to 2eSST – A Look at the Evolution of VMEbus Protocols by John Rynearson, Technical Director,
VITA, provides additional information on VMEbus and can be obtained at www.vita.com.
Maximum Data Transfer Rates
FREQUENCY (MHz)
DATA BITS
PER CYCLE PER CLOCK CYCLE
DATA TRANSFERS
PER SYSTEM
(Mbyte/s)
DATE
TOPOLOGY
PROTOCOL
BACKPLANE
CLOCK
10
1981
1989
1995
1997
1999
VMEbus IEEE-1014
VME64
BLT
32
64
64
64
64
1
40
80
10
10
MBLT
2eVME
2eSST
2eSST
1
10
VME64x
2
160
10
20
VME64x
2-No Ack
2-No Ack
160–320
320–1000
10–20
20–62.5
20–40
40–125
VME320
Applicability
Target applications for VME backplanes include industrial controls, telecommunications, simulation, high-energy
physics, office automation, and instrumentation systems.
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PACKAGE OPTION ADDENDUM
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8-Feb-2010
PACKAGING INFORMATION
Orderable Device
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
PREVIEW
ACTIVE
ACTIVE
NRND
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
74VMEH22501DGGRE4
74VMEH22501DGGRG4
74VMEH22501DGVRE4
74VMEH22501DGVRG4
SN74VMEH22501DGG
SN74VMEH22501DGGR
SN74VMEH22501DGVR
SN74VMEH22501GQLR
TSSOP
DGG
48
48
48
48
48
48
48
56
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TSSOP
TVSOP
TVSOP
TSSOP
TSSOP
TVSOP
DGG
DGV
DGV
DGG
DGG
DGV
GQL
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
BGA MI
CROSTA
R JUNI
OR
1000
TBD
SNPB
Level-1-240C-UNLIM
SN74VMEH22501ZQLR
ACTIVE
BGA MI
CROSTA
R JUNI
OR
ZQL
56
1000 Green (RoHS &
no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
8-Feb-2010
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Feb-2010
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74VMEH22501DGGR TSSOP
SN74VMEH22501DGVR TVSOP
DGG
DGV
GQL
48
48
56
2000
2000
1000
330.0
330.0
330.0
24.4
16.4
16.4
8.6
7.1
4.8
15.8
10.2
7.3
1.8
1.6
12.0
12.0
8.0
24.0
16.0
16.0
Q1
Q1
Q1
SN74VMEH22501GQLR BGA MI
1.45
CROSTA
R JUNI
OR
SN74VMEH22501ZQLR BGA MI
ZQL
56
1000
330.0
16.4
4.8
7.3
1.45
8.0
16.0
Q1
CROSTA
R JUNI
OR
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Feb-2010
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
SN74VMEH22501DGGR
SN74VMEH22501DGVR
TSSOP
TVSOP
DGG
DGV
GQL
48
48
56
2000
2000
1000
346.0
346.0
346.0
346.0
346.0
346.0
41.0
33.0
33.0
SN74VMEH22501GQLR BGA MICROSTAR
JUNIOR
SN74VMEH22501ZQLR BGA MICROSTAR
JUNIOR
ZQL
56
1000
346.0
346.0
33.0
Pack Materials-Page 2
MECHANICAL DATA
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
0,23
0,13
M
0,07
0,40
24
13
0,16 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
0°–ā8°
0,75
1
12
0,50
A
Seating Plane
0,08
0,15
0,05
1,20 MAX
PINS **
14
16
20
24
38
48
56
DIM
A MAX
A MIN
3,70
3,50
3,70
3,50
5,10
4,90
5,10
4,90
7,90
7,70
9,80
9,60
11,40
11,20
4073251/E 08/00
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
D. Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUARY 1998
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0,27
0,17
M
0,08
0,50
48
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
0,25
1
24
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
48
56
64
DIM
A MAX
12,60
12,40
14,10
13,90
17,10
16,90
A MIN
4040078/F 12/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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相关型号：
74VMEH22501DGVRG4
8-BIT UNIVERSAL BUS TRANSCEIVER AND TWO 1-BIT BUS TRANSCEIVERS WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND 3-STATE OUTPUTS
TI
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