8407201RAS2035 [TI]
HC/UH SERIES, 8-BIT DRIVER, TRUE OUTPUT, CDIP20, 0.300 INCH, CERAMIC, DIP-20;
| 型号： | 8407201RAS2035 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | HC/UH SERIES, 8-BIT DRIVER, TRUE OUTPUT, CDIP20, 0.300 INCH, CERAMIC, DIP-20 驱动 CD 输出元件 逻辑集成电路 |
| 文件： | 总10页 (文件大小：154K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN54HC373, SN74HC373
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCLS140B – DECEMBER 1982 – REVISED MAY 1997
SN54HC373 . . . J OR W PACKAGE
SN74HC373 . . . DB, DW, N, OR PW PACKAGE
(TOP VIEW)
Eight High-Current Latches in a Single
Package
High-Current 3-State True Outputs Can
Drive up to 15 LSTTL Loads
OE
1Q
1D
2D
2Q
3Q
3D
4D
4Q
V
CC
8Q
8D
1
2
3
4
5
6
7
8
9
20
19
18
Full Parallel Access for Loading
Package Options Include Plastic
17 7D
16 7Q
15 6Q
14 6D
Small-Outline (DW), Shrink Small-Outline
(DB), Thin Shrink Small-Outline (PW), and
Ceramic Flat (W) Packages, Ceramic Chip
Carriers (FK), and Standard Plastic (N) and
Ceramic (J) 300-mil DIPs
13
5D
12 5Q
11 LE
description
GND 10
These 8-bit latches feature 3-state outputs
designed specifically for driving highly capacitive
or relatively low-impedance loads. They are
particularly suitable for implementing buffer
registers, I/O ports, bidirectional bus drivers, and
working registers.
SN54HC373 . . . FK PACKAGE
(TOP VIEW)
3
2
1
20 19
18
8D
7D
7Q
2D
2Q
3Q
3D
4D
4
5
6
7
8
The eight latches of the ’HC373 are transparent
D-type latches. While the latch-enable (LE) input
is high, the Q outputs follow the data (D) inputs.
When LE is taken low, the Q outputs are latched
at the levels that were set up at the D inputs.
17
16
15 6Q
14
9 10 11 12 13
6D
An output-enable (OE) input places the eight
outputs in either a normal logic state (high or low
logic levels) or the high-impedance state. In the
high-impedance state, the outputs neither load
nor drive the bus lines significantly. The
high-impedance state and increased drive
provide the capability to drive bus lines without
interface or pullup components.
OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered
while the outputs are off.
The SN54HC373 is characterized for operation over the full military temperature range of –55°C to 125°C. The
SN74HC373 is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 1997, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54HC373, SN74HC373
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCLS140B – DECEMBER 1982 – REVISED MAY 1997
FUNCTION TABLE
(each latch)
INPUTS
OUTPUT
Q
OE
L
LE
H
H
L
D
H
L
H
L
L
L
X
X
Q
0
H
X
Z
†
logic symbol
1
EN
OE
LE
11
C1
3
2
5
1D
2D
3D
4D
5D
6D
1D
1Q
2Q
3Q
4Q
5Q
6Q
4
7
6
8
9
13
14
12
15
17
18
16
19
7D
8D
7Q
8Q
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
logic diagram (positive logic)
1
OE
11
LE
C1
1D
2
1Q
3
1D
To Seven Other Channels
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54HC373, SN74HC373
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCLS140B – DECEMBER 1982 – REVISED MAY 1997
†
absolute maximum ratings over operating free-air temperature range
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
CC
I
Input clamp current, I (V < 0 or V > V ) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
IK
I
CC
Output clamp current, I
(V < 0 or V > V ) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
OK
O O CC
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±35 mA
Continuous current through V
Package thermal impedance, θ (see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115°C/W
O
O
CC
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±70 mA
JA
DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51, except for through-hole packages, which use a trace
length of zero.
recommended operating conditions
SN54HC373
MIN NOM
SN74HC373
MIN NOM
UNIT
MAX
MAX
V
V
Supply voltage
2
1.5
3.15
4.2
0
5
6
2
1.5
3.15
4.2
0
5
6
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 2 V
High-level input voltage
= 4.5 V
= 6 V
V
V
IH
= 2 V
0.5
1.35
1.8
0.5
1.35
1.8
V
IL
Low-level input voltage
= 4.5 V
= 6 V
0
0
0
0
V
V
Input voltage
0
V
V
0
V
V
V
V
I
CC
CC
Output voltage
0
0
O
CC
CC
V
CC
V
CC
V
CC
= 2 V
0
1000
500
400
125
0
1000
500
400
85
t
Input transition (rise and fall) time
Operating free-air temperature
= 4.5 V
= 6 V
0
0
ns
t
0
0
T
–55
–40
°C
A
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54HC373, SN74HC373
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCLS140B – DECEMBER 1982 – REVISED MAY 1997
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
T
= 25°C
SN54HC373
SN74HC373
A
PARAMETER
TEST CONDITIONS
V
UNIT
CC
MIN
TYP
MAX
MIN
1.9
4.4
5.9
3.7
5.2
MAX
MIN
1.9
MAX
2 V
4.5 V
6 V
1.9 1.998
4.4 4.499
5.9 5.999
I
= –20 µA
4.4
OH
V
V = V or V
IH
5.9
V
OH
OL
I
IL
IL
I
I
= –6 mA
4.5 V
6 V
3.98
5.48
4.3
5.8
3.84
5.34
OH
= –7.8 mA
OH
2 V
0.002
0.001
0.001
0.17
0.1
0.1
0.1
0.1
0.1
0.1
I
= 20 µA
4.5 V
6 V
OL
V
V = V or V
0.1
0.1
0.1
V
I
IH
I
I
= 6 mA
4.5 V
6 V
0.26
0.26
±100
±0.5
8
0.4
0.33
0.33
±1000
±5
OL
= 7.8 mA
0.15
0.4
OL
I
I
I
V = V
I
or 0
6 V
±0.1
±1000
±10
160
10
nA
µA
µA
pF
I
CC
CC
V
O
= V
or 0
6 V
±0.01
OZ
CC
CC
V = V
I
or 0,
I
O
= 0
6 V
80
C
2 V to 6 V
3
10
10
i
timing requirements over recommended operating free-air temperature range (unless otherwise
noted)
T
= 25°C
SN54HC373
SN74HC373
A
V
UNIT
CC
MIN
80
16
14
50
10
9
MAX
MIN
120
24
MAX
MIN
100
20
MAX
2 V
4.5 V
6 V
t
w
t
su
t
h
Pulse duration, LE high
Setup time, data before LE↓
Hold time, data after LE↓
ns
20
17
2 V
75
63
4.5 V
6 V
15
13
ns
ns
13
11
2 V
20
10
10
26
24
4.5 V
6 V
13
12
13
12
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54HC373, SN74HC373
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCLS140B – DECEMBER 1982 – REVISED MAY 1997
switching characteristics over recommended operating free-air temperature range, C = 50 pF
L
(unless otherwise noted) (see Figure 1)
T
A
= 25°C
TYP
58
15
13
73
18
15
65
17
14
50
15
13
28
8
SN54HC373
SN74HC373
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
V
UNIT
CC
MIN
MAX
150
30
MIN
MAX
225
45
MIN
MAX
190
38
2 V
4.5 V
6 V
D
Q
26
38
32
t
pd
ns
2 V
175
35
265
53
220
44
LE
OE
OE
Any Q
Any Q
Any Q
Any Q
4.5 V
6 V
30
45
38
2 V
150
30
225
45
190
38
t
t
t
4.5 V
6 V
ns
ns
ns
en
dis
t
26
38
32
2 V
150
30
225
45
190
38
4.5 V
6 V
26
38
32
2 V
60
90
75
4.5 V
6 V
12
18
15
6
10
15
13
switching characteristics over recommended operating free-air temperature range, C = 150 pF
L
(unless otherwise noted) (see Figure 1)
T
A
= 25°C
TYP
82
SN54HC373
SN74HC373
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
V
UNIT
CC
MIN
MAX
200
40
MIN
MAX
300
60
MIN
MAX
250
50
2 V
4.5 V
6 V
D
Q
22
19
34
51
43
t
pd
ns
2 V
100
24
225
45
335
67
285
57
LE
OE
Any Q
Any Q
Any Q
4.5 V
6 V
20
38
57
48
2 V
90
200
40
300
60
250
50
t
t
4.5 V
6 V
23
ns
ns
en
19
34
51
43
2 V
45
210
42
315
63
265
53
4.5 V
6 V
17
t
13
36
53
45
operating characteristics, T = 25°C
A
PARAMETER
Power dissipation capacitance per latch
TEST CONDITIONS
TYP
UNIT
C
No load
100
pF
pd
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54HC373, SN74HC373
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCLS140B – DECEMBER 1982 – REVISED MAY 1997
PARAMETER MEASUREMENT INFORMATION
V
CC
PARAMETER
R
C
L
S1
S2
L
50 pF
or
150 pF
t
Open
Closed
Closed
Open
S1
S2
PZH
Test
Point
t
t
1 kΩ
1 kΩ
en
R
t
L
PZL
From Output
Under Test
t
t
Open
Closed
Open
PHZ
PLZ
50 pF
C
dis
L
Closed
(see Note A)
50 pF
or
150 pF
t
or t
––
Open
Open
pd
t
LOAD CIRCUIT
V
CC
Reference
Input
50%
V
CC
0 V
High-Level
Pulse
50%
50%
t
t
h
su
0 V
V
CC
t
Data
Input
w
90%
90%
50%
10%
50%
10%
V
CC
Low-Level
Pulse
0 V
50%
50%
t
t
f
r
0 V
VOLTAGE WAVEFORMS
SETUP AND HOLD AND INPUT RISE AND FALL TIMES
VOLTAGE WAVEFORMS
PULSE DURATIONS
Output
V
CC
V
CC
Control
(Low-Level
Enabling)
Input
50%
50%
50%
50%
0 V
0 V
t
t
PLH
PHL
90%
t
t
PLZ
PZL
V
V
OH
≈ V
CC
50%
≈ V
CC
Output
Waveform 1
(See Note B)
In-Phase
Output
90%
t
50%
10%
50%
10%
10%
90%
OL
V
OL
t
r
f
t
t
t
PZH
PHL
90%
PLH
V
V
OH
V
Output
Waveform 2
(See Note B)
OH
90%
t
Out-of-
Phase
Output
50%
10%
50%
10%
50%
≈ 0 V
OL
t
t
PHZ
f
r
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES FOR 3-STATE OUTPUTS
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
NOTES: A.
C includes probe and test-fixture capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR ≤ 1 MHz, Z = 50 Ω, t = 6 ns, t = 6 ns.
O
r
f
D. The outputs are measured one at a time with one input transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
are the same as t
are the same as t
are the same as t
.
dis
en
.
pd
PLZ
PZL
PLH
PHZ
PZH
PHL
.
Figure 1. Load Circuit and Voltage Waveforms
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1998, Texas Instruments Incorporated
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SN54HC373, Octal D-type Transparent Latches With 3-State Outputs
Device Status: Active
> Description
> Features
> Datasheets
Parameter Name SN54HC373
Voltage Nodes (V) 6, 5, 2
> Pricing/Samples/Availability
> Application Notes
> Related Documents
> Training
Vcc range (V)
Input Level
Output Level
No. of Outputs
Logic
2.0 to 6.0
CMOS
CMOS
8
True
Description
These 8-bit latches feature 3-state outputs designed specifically for driving highly capacitive
or relatively low-impedance loads. They are particularly suitable for implementing buffer
registers, I/O ports, bidirectional bus drivers, and working registers.
The eight latches of the 'HC373 are transparent D-type latches. While the latch-enable (LE)
input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs
are latched at the levels that were set up at the D inputs.
An output-enable (OE\) input places the eight outputs in either a normal logic state (high or
low logic levels) or the high-impedance state. In the high-impedance state, the outputs
neither load nor drive the bus lines significantly. The high-impedance state and increased
drive provide the capability to drive bus lines without interface or pullup components.
OE\ does not affect the internal operations of the latches. Old data can be retained or new
data can be entered while the outputs are off.
The SN54HC373 is characterized for operation over the full military temperature range of -
55°C to 125°C. The SN74HC373 is characterized for operation from -40°C to 85°C.
Features
l
l
l
l
Eight High-Current Latches in a Single Package
High-Current 3-State True Outputs Can Drive up to 15 LSTTL Loads
Full Parallel Access for Loading
Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline (DB),
Thin Shrink Small-Outline (PW), and Ceramic Flat (W) Packages, Ceramic Chip
Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs
To view the following documents, Acrobat Reader 3.x is required.
To download a document to your hard drive, right-click on the link and choose 'Save'.
Datasheets
Full datasheet in Acrobat PDF: scls140b.pdf (107 KB)
Full datasheet in Zipped PostScript: scls140b.psz (110 KB)
Pricing/Samples/Availability
Price/unit
USD (100-999)
Orderable Device Package Pins Temp (ºC) Status
Pack Qty DSCC Number Availability / Samples
84072012A
FK
20 -55 TO 125 ACTIVE 10.77
1
1
1
1
1
1
1
Check stock or order
Check stock or order
Check stock or order
Check stock or order
Check stock or order
JM38510/65403B2A FK
JM38510/65403BRA J
20 -55 TO 125 ACTIVE 14.45
20 -55 TO 125 ACTIVE 8.10
20 -55 TO 125 ACTIVE 1.79
20 -55 TO 125 ACTIVE 10.77
20 -55 TO 125 ACTIVE 2.10
20 -55 TO 125 ACTIVE 12.11
SN54HC373J
J
SNJ54HC373FK
SNJ54HC373J
SNJ54HC373W
FK
J
84072012A
8407201RAS2035 Check stock or order
8407201SA Check stock or order
W
Application Reports
View Application Reports for Digital Logic
l CMOS Power Consumption And CPD Calculation (SCAA035B - Updated: 06/01/1997)
l Designing With Logic (SDYA009C - Updated: 06/01/1997)
l HCMOS Design Considerations (SCLA007 - Updated: 04/01/1996)
l Implications Of Slow Or Floating CMOS Inputs (SCBA004C - Updated: 02/01/1998)
l Input And Output Characteristics Of Digital Integrated Circuits (SDYA010 - Updated: 10/01/1996)
l Live Insertion (SDYA012 - Updated: 10/01/1996)
l SN54/74HCT CMOS Logic Family Applications And Restrictions (SCLA011 - Updated: 05/01/1996)
l Using High Speed CMOS And Advanced CMOS In Systems With Multiple Vcc (SCLA008 - Updated: 04/01/1996)
Related Documents
l Documentation Rules (SAP) And Ordering Information (SZZU001B, 4 KB - Updated: 05/06/1999)
l Logic Selection Guide Second Half 2000 (SDYU001N, 5035 KB - Updated: 04/17/2000)
l MicroStar Junior BGA Design Summary (SCET004, 284 KB - Updated: 07/28/2000)
l More Power In Less Space - Technical Article (SCAU001A, 850 KB - Updated: 03/01/1996)
Table Data Updated on: 9/8/2000
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