概述
数据手册ABT18646 概述
WITH 18-BIT TRANSCEIVER AND REGISTER 内置18位收发器和寄存器
ABT18646 数据手册
通过下载ABT18646数据手册来全面了解它。这个PDF文档包含了所有必要的细节，如产品概述、功能特性、引脚定义、引脚排列图等信息。
PDF下载SN74ABT18646
SCAN TEST DEVICE
WITH 18-BIT TRANSCEIVER AND REGISTER
SCBS131A – AUGUST 1992 – REVISED JANUARY 2002
Member of the Texas Instruments
Widebus Family
SCOPE Instruction Set
– IEEE Std 1149.1-1990 Required
Instructions, Optional INTEST, and
P1149.1A CLAMP and HIGHZ
– Parallel Signature Analysis at Inputs
With Masking Option
– Pseudorandom Pattern Generation From
Outputs
– Sample Inputs/Toggle Outputs
– Binary Count From Outputs
– Device Identification
Compatible With IEEE Std 1149.1-1990
(JTAG) Test Access Port and
Boundary-Scan Architecture
Includes D-Type Flip-Flops and Control
Circuitry to Provide Multiplexed
Transmission of Stored and Real-Time Data
Two Boundary-Scan Cells Per I/O for
Greater Flexibility
– Even-Parity Opcodes
PM PACKAGE
(TOP VIEW)
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
1A3
1A4
1A5
GND
1A6
1A7
1A8
1A9
1B4
1B5
1B6
GND
1B7
1B8
1B9
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
2
3
4
5
6
7
8
V
CC
9
V
2B1
2B2
2B3
2B4
GND
2B5
2B6
2B7
CC
10
11
12
13
14
15
16
2A1
2A2
2A3
GND
2A4
2A5
2A6
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
description
This scan test device with a 18-bit bus transceiver and register is a member of the Texas Instruments SCOPE
testability IC family. This device supports IEEE Std 1149.1-1990 boundary scan to facilitate testing of complex
circuit board assemblies. Scan access to the test circuitry is accomplished via the four-wire test access port
(TAP) interface.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SCOPE and Widebus are trademarks of Texas Instruments.
Copyright 2002, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ABT18646
SCAN TEST DEVICE
WITH 18-BIT TRANSCEIVER AND REGISTER
SCBS131A – AUGUST 1992 – REVISED JANUARY 2002
description (continued)
In the normal mode, this device is an 18-bit bus transceiver and register that allows for multiplexed transmission
of data directly from the input bus or from the internal registers. It can be used either as two 9-bit transceivers
or one 18-bit transceiver. The test circuitry can be activated by the TAP to take snapshot samples of the data
appearing at the device pins or to perform a self-test on the boundary test cells. Activating the TAP in the normal
mode does not affect the functional operation of the SCOPE bus transceivers and registers.
Transceiver function is controlled by output-enable (OE) and direction (DIR) inputs. When OE is low, the
transceiver is active and operates in the A-to-B direction when DIR is high or in the B-to-A direction when DIR
is low. When OE is high, both the A and B outputs are in the high-impedance state, effectively isolating both
buses.
Data flow is controlled by clock (CLKAB and CLKBA) and select (SAB and SBA) inputs. Data on the A bus is
clocked into the associated registers on the low-to-high transition of CLKAB. When SAB is low, real-time A data
is selected for presentation to the B bus (transparent mode). When SAB is high, stored A data is selected for
presentation to the B bus (registered mode). The function of the CLKBA and SBA inputs mirrors that of CLKAB
and SAB, respectively. Figure 1 illustrates the four fundamental bus-management functions that can be
performed with the SN74ABT18646.
In the test mode, the normal operation of the SCOPE bus transceivers and registers is inhibited, and the test
circuitry is enabled to observe and control the I/O boundary of the device. When enabled, the test circuitry can
perform boundary scan test operations according to the protocol described in IEEE Std 1149.1-1990.
Four dedicated test pins are used to observe and control the operation of the test circuitry: test data input (TDI),
test data output (TDO), test mode select (TMS), and test clock (TCK). Additionally, the test circuitry can perform
othertestingfunctions, suchasparallelsignatureanalysisondatainputsandpseudorandompatterngeneration
from data outputs. All testing and scan operations are synchronized to the TAP interface.
Additional flexibility is provided in the test mode through the use of two boundary scan cells (BSCs) for each
I/O pin. This allows independent test data to be captured and forced at either bus (A or B). A PSA/COUNT
instruction is also included to ease the testing of memories and other circuits where a binary count addressing
scheme is useful.
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
T
A
PACKAGE
–40°C to 85°C
LQFP – PM
Tray
SN74ABT18646PM
ABT18646
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB
design guidelines are available at www.ti.com/sc/package.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ABT18646
SCAN TEST DEVICE
WITH 18-BIT TRANSCEIVER AND REGISTER
SCBS131A – AUGUST 1992 – REVISED JANUARY 2002
FUNCTION TABLE
(normal mode, each 9-bit section)
INPUTS
DATA I/O
OPERATION OR FUNCTION
OE
X
X
H
H
L
DIR
X
CLKAB
CLKBA
SAB
X
SBA
X
A1–A9
Input
B1–B9
Unspecified
Input
†
†
†
↑
X
↑
Store A, B unspecified
Store B, A unspecified
Store A and B data
†
X
X
↑
X
X
Unspecified
Input
X
↑
X
X
Input
X
L
X
X
X
L
L
X
X
X
X
X
X
Input disabled
Output
Input disabled
Input
Isolation, hold storage
Real-time B data to A bus
Stored B data to A bus
Real-time A data to B bus
Stored A data to B bus
L
X
L
L
L
X
H
Output
Input disabled
Output
L
H
H
L
X
Input
L
H
X
Input disabled
Output
†
The data output functions can be enabled or disabled by various signals at the OE and DIR inputs. Data input functions are always enabled; i.e.,
data at the bus terminals is stored on every low-to-high transition of the clock inputs.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ABT18646
SCAN TEST DEVICE
WITH 18-BIT TRANSCEIVER AND REGISTER
SCBS131A – AUGUST 1992 – REVISED JANUARY 2002
DIR CLKAB CLKBA SAB
SBA
L
DIR
H
CLKAB CLKBA SAB
SBA
X
OE
L
OE
L
L
X
X
X
X
X
L
REAL-TIME TRANSFER
BUS B TO BUS A
REAL-TIME TRANSFER
BUS A TO BUS B
DIR CLKAB CLKBA SAB
SBA
X
DIR
L
CLKAB CLKBA SAB
SBA
H
OE
X
OE
L
X
X
X
X
X
X
X
↑
X
X
L
X
X
X
H
X
H
X
X
↑
L
H
X
↑
↑
STORAGE FROM
A, B, OR A AND B
TRANSFER STORED DATA
TO A AND/OR B
Figure 1. Bus-Management Functions
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ABT18646
SCAN TEST DEVICE
WITH 18-BIT TRANSCEIVER AND REGISTER
SCBS131A – AUGUST 1992 – REVISED JANUARY 2002
functional block diagram
Boundary-Scan Register
62
1OE
53
55
54
59
60
1DIR
1CLKBA
1SBA
1CLKAB
1SAB
C1
1D
63
51
1A1
1B1
C1
1D
1 of 9 Channels
21
2OE
30
27
28
2DIR
2CLKBA
2SBA
23
22
2CLKAB
2SAB
C1
1D
10
40
2A1
2B1
C1
1D
1 of 9 Channels
Bypass Register
Boundary-Control
Register
Identification
Register
V
CC
58
TDO
24
Instruction
Register
TDI
V
CC
56
TMS
TCK
TAP
Controller
26
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ABT18646
SCAN TEST DEVICE
WITH 18-BIT TRANSCEIVER AND REGISTER
SCBS131A – AUGUST 1992 – REVISED JANUARY 2002
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
CC
Input voltage range, V : Except I/O ports (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
I
I/O ports (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 5.5 V
Voltage range applied to any output in the high state or power-off state, V
. . . . . . . . . . . . . . –0.5 V to 5.5 V
O
Current into any output in the low state, I
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
O
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –18 mA
IK
OK
I
Output clamp current, I
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
O
Package thermal impedance, θ (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34°C/W
Storage temperature range, T
JA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
MIN
4.5
2
MAX
UNIT
V
V
V
V
V
Supply voltage
5.5
CC
High-level input voltage
Low-level input voltage
Input voltage
V
IH
0.8
V
IL
0
V
CC
V
I
I
I
High-level output current
Low-level output current
Input transition rise or fall rate
Operating free-air temperature
–32
64
mA
mA
ns/V
°C
OH
OL
∆t/∆v
10
T
–40
85
A
NOTE 3: All unused inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ABT18646
SCAN TEST DEVICE
WITH 18-BIT TRANSCEIVER AND REGISTER
SCBS131A – AUGUST 1992 – REVISED JANUARY 2002
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Note 4)
†
PARAMETER
TEST CONDITIONS
MIN TYP
MAX
UNIT
V
V
V
V
V
V
V
= 4.5 V,
= 4.5 V,
= 4.5 V,
= 4.5 V,
I = –18 mA
–1.2
V
IK
CC
CC
CC
CC
I
I
I
I
= –3 mA
= –32 mA
= 64 mA
2.5
2
OH
OH
OL
V
V
OH
OL
0.55
±1
CLK, DIR, OE, S, TCK
A or B ports
I
I
V
CC
= 5.5 V,
V = V
or GND
µA
I
CC
±100
10
I
I
I
I
I
I
I
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 5.5 V,
= 5.5 V,
= 5.5 V,
= 5.5 V,
= 0,
V = V
I
,
TDI, TMS
µA
µA
µA
µA
µA
µA
mA
IH
CC
V = GND,
I
TDI, TMS
–150
50
IL
‡
V
= 2.7 V
OZH
O
O
‡
V
= 0.5 V
–50
±100
50
OZL
off
V or V ≤ 5.5 V
I
O
= 5.5 V,
= 5.5 V,
V
= 5.5 V,
Outputs high
CEX
O
O
§
V
= 2.5 V
–50
–200
5.5
O
Outputs high
Outputs low
V
I
= 5.5 V,
= 0,
CC
O
¶
38
I
A or B ports
mA
CC
V = V
I
or GND
CC
Outputs disabled
5
2
#
V
= 5.5 V,
One input at 3.4 V,
Other inputs at V
Control inputs
A or B ports
TDO
or GND
CC
mA
pF
pF
pF
∆I
CC
CC
V = 2.5 V or 0.5 V,
C
C
C
3
i
I
V
= 2.5 V or 0.5 V,
= 2.5 V or 0.5 V,
10
8
io
o
O
O
V
NOTE 4: Preliminary specifications based on SPICE analysis
†
‡
§
¶
#
All typical values are at V
= 5 V, T = 25°C.
A
OZL
CC
and I
The parameters I
include the input leakage current.
OZH
Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
If both A and B ports are low, I is 76 mA.
CCL
This is the increase in supply current for each input that is at the specified TTL voltage level rather than V
or GND.
CC
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (normal mode) (see Note 4 and Figure 2)
MIN
MAX
UNIT
MHz
ns
f
t
t
t
Clock frequency
Pulse duration
Setup time
CLKAB or CLKBA
100
clock
CLKAB or CLKBA high or low
A before CLKAB↑ or B before CLKBA↑
A after CLKAB↑ or B after CLKBA↑
4
4.5
0
w
ns
su
h
Hold time
ns
NOTE 4: Preliminary specifications based on SPICE analysis
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ABT18646
SCAN TEST DEVICE
WITH 18-BIT TRANSCEIVER AND REGISTER
SCBS131A – AUGUST 1992 – REVISED JANUARY 2002
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (test mode) (see Note 4 and Figure 2)123
MIN
MAX
UNIT
MHz
ns
f
t
Clock frequency
Pulse duration
TCK
50
clock
TCK high or low
8
4.5
7.5
3
w
A, B, CLK, DIR, OE, or S before TCK↑
TDI before TCK↑
t
Setup time
ns
su
h
TMS before TCK↑
A or B after TCK↑
CLK, DIR, OE, or S after TCK↑
TDI after TCK↑
0.5
0
t
Hold time
ns
0.5
0.5
50
1
TMS after TCK↑
t
t
Delay time
Rise time
Power up to TCK↑
ns
d
V
CC
power up
µs
r
NOTE 4: Preliminary specifications based on SPICE analysis
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (normal mode) (see Note 4 and Figure 2)
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
MIN
MAX
UNIT
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
CLKAB or CLKBA
100
2
MHz
max
PLH
PHL
PLH
PHL
PLH
PHL
PZH
PZL
PZH
PZL
PHZ
PLZ
PHZ
PLZ
5.4
6.6
8
A or B
B or A
B or A
B or A
B or A
B or A
B or A
B or A
ns
ns
ns
ns
ns
ns
ns
2
2.5
2.5
2
CLKAB or CLKBA
SAB or SBA
DIR
7.4
7.5
8
2
2
8
3
9.1
8.6
9.3
11.1
8.8
10.5
8.5
2.5
3
OE
3.5
3
DIR
3.5
2
OE
NOTE 4: Preliminary specifications based on SPICE analysis
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ABT18646
SCAN TEST DEVICE
WITH 18-BIT TRANSCEIVER AND REGISTER
SCBS131A – AUGUST 1992 – REVISED JANUARY 2002
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (test mode) (see Note 4 and Figure 2)123
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
MIN
MAX
UNIT
f
t
t
t
t
t
t
t
t
t
t
t
t
TCK
50
2.5
2.5
2
MHz
max
PLH
PHL
PLH
PHL
PZH
PZL
PZH
PZL
PHZ
PLZ
PHZ
PLZ
13.5
12.5
6.5
6.5
13.8
14.5
7
TCK↓
A or B
TDO
ns
ns
ns
ns
ns
ns
TCK↓
TCK↓
TCK↓
TCK↓
TCK↓
2
4.5
5
A or B
TDO
2
3
7.5
17
4
A or B
TDO
3
16
3
9
3
7.5
NOTE 4: Preliminary specifications based on SPICE analysis
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ABT18646
SCAN TEST DEVICE
WITH 18-BIT TRANSCEIVER AND REGISTER
SCBS131A – AUGUST 1992 – REVISED JANUARY 2002
PARAMETER MEASUREMENT INFORMATION
7 V
Open
TEST
/t
S1
S1
500 Ω
From Output
Under Test
t
Open
7 V
PLH PHL
GND
t
/t
PLZ PZL
C
= 50 pF
t
/t
Open
L
PHZ PZH
500 Ω
(see Note A)
3 V
0 V
LOAD CIRCUIT
Timing Input
Data Input
1.5 V
t
w
t
t
h
su
3 V
0 V
3 V
0 V
Input
1.5 V
1.5 V
1.5 V
1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
3 V
0 V
3 V
0 V
Output
Control
1.5 V
1.5 V
1.5 V
1.5 V
Input
t
PZL
t
t
t
PHL
PLH
PHL
t
PLZ
Output
Waveform 1
S1 at 7 V
3.5 V
V
V
OH
1.5 V
1.5 V
1.5 V
1.5 V
Output
V
V
+ 0.3 V
OL
V
OL
OL
(see Note B)
t
PHZ
t
PLH
t
PZH
Output
Waveform 2
S1 at Open
(see Note B)
V
OH
V
V
OH
– 0.3 V
OH
1.5 V
1.5 V
Output
≈0 V
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. includes probe and jig capacitance.
C
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
Figure 2. Load Circuit and Voltage Waveforms
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
1-May-2006
PACKAGING INFORMATION
Orderable Device
SN74ABT18646PM
SN74ABT18646PMG4
Status (1)
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
LQFP
PM
64
160 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
LQFP
PM
64
160 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MTQF008A – JANUARY 1995 – REVISED DECEMBER 1996
PM (S-PQFP-G64)
PLASTIC QUAD FLATPACK
0,27
0,17
0,50
M
0,08
33
48
49
32
64
17
0,13 NOM
1
16
7,50 TYP
Gage Plane
10,20
SQ
9,80
0,25
12,20
SQ
0,05 MIN
0°–7°
11,80
1,45
1,35
0,75
0,45
Seating Plane
0,08
1,60 MAX
4040152/C 11/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
D. May also be thermally enhanced plastic with leads connected to the die pads.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
orders and should verify that such information is current and complete. All products are sold subject to TI’s terms
and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for
their products and applications using TI components. To minimize the risks associated with customer products
and applications, customers should provide adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,
copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process
in which TI products or services are used. Information published by TI regarding third-party products or services
does not constitute a license from TI to use such products or services or a warranty or endorsement thereof.
Use of such information may require a license from a third party under the patents or other intellectual property
of the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of information in TI data books or data sheets is permissible only if reproduction is without
alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction
of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for
such altered documentation.
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that
product or service voids all express and any implied warranties for the associated TI product or service and
is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.
Following are URLs where you can obtain information on other Texas Instruments products and application
solutions:
Products
Applications
Audio
Amplifiers
amplifier.ti.com
www.ti.com/audio
Data Converters
dataconverter.ti.com
Automotive
www.ti.com/automotive
DSP
dsp.ti.com
Broadband
Digital Control
Military
www.ti.com/broadband
www.ti.com/digitalcontrol
www.ti.com/military
Interface
Logic
interface.ti.com
logic.ti.com
Power Mgmt
Microcontrollers
power.ti.com
Optical Networking
Security
www.ti.com/opticalnetwork
www.ti.com/security
www.ti.com/telephony
www.ti.com/video
microcontroller.ti.com
Telephony
Video & Imaging
Wireless
www.ti.com/wireless
Mailing Address:
Texas Instruments
Post Office Box 655303 Dallas, Texas 75265
Copyright 2006, Texas Instruments Incorporated
ABT18646 相关器件
| 型号 | 制造商 | 描述 | 价格 | 文档 |
| ABT22V10-7/10A/B | ETC | Low Noise. High Drive. Metastable Immune. PLD | 获取价格 |
|
| ABT22V10-7A | ETC | Fuse-Programmable PLD | 获取价格 |
|
| ABT22V10-7D | ETC | Fuse-Programmable PLD | 获取价格 |
|
| ABT22V10-7N | ETC | Fuse-Programmable PLD | 获取价格 |
|
| ABT22V10A/BLA | ETC | Fuse-Programmable PLD | 获取价格 |
|
| ABT22V10A5 | NXP | 5V high-speed universal PLD device with live insertion capability | 获取价格 |
|
| ABT22V10A5/A7 | NXP | 5v High-Speed Universal PLD With Live Insertion Capability | 获取价格 |
|
| ABT22V10A5A | NXP | 5V high-speed universal PLD device with live insertion capability | 获取价格 |
|
| ABT22V10A5A-T | NXP | OT PLD, 8ns, PQCC28 | 获取价格 |
|
| ABT22V10A7 | NXP | 5V high-speed universal PLD device with live insertion capability | 获取价格 |
|
ABT18646 相关文章
Bourns 密封通孔金属陶瓷微调电位计产品选型手册(英文版)
- 2024-09-20
- 6
Bourns 精密环境传感器产品选型手册(英文版)
- 2024-09-20
- 9
Bourns POWrTher 负温度系数(NTC)热敏电阻手册 (英文版)
- 2024-09-20
- 8
Bourns GMOV 混合过压保护组件产品选型手册(英文版)
- 2024-09-20
- 6
