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ADC3421-Q1

ZHCSKL4 –DECEMBER 2019

ADC3421-Q1 车用、四通道、12 位、25MSPS 模数转换器

1 特性

3 说明

1

•

符合面向汽车标准

ADC3421-Q1 是一款汽车级、高线性度、超低功耗、

四通道、12 位、25MSPS 模数转换器 (ADC)。该器件

专门用于支持具有宽动态范围需求且要求苛刻的高输入

频率信号。输入时钟分频器使得系统时钟架构设计更加

灵活，SYSREF 输入可实现系统完全同步。ADC3421-

Q1 支持串行低压差分信令 (LVDS)，从而减少接口线

路的数量，实现高系统集成密度。串行 LVDS 接口为

双线制，通过两个 LVDS 对串行输出每个 ADC 数据。

内部锁相环 (PLL) 会将传入的 ADC 采样时钟加倍，以

获得串行输出各通道的 12 位输出数据时所使用的位时

钟。除了串行数据流之外，数据帧和位时钟也作为

LVDS 输出进行传送。

–

温度等级 1：–40°C 至 125°C T_A

•

四通道

12 位分辨率

单电源：1.8V

串行 LVDS 接口

支持 1 分频、2 分频和 4 分频的灵活输入时钟缓冲

器

•

f_IN= 10MHz 时，SNR = 71.1dBFS，

SFDR = 90dBc

超低功耗：

–

25MSPS 时为每通道 44mW

•

通道隔离：105dB

内部抖动和斩波

支持多芯片同步

器件信息⁽¹⁾

器件型号

封装

封装尺寸（标称值）

ADC3421-Q1

VQFNP (56)

8.00mm x 8.00mm

(1) 如需了解所有可用封装，请见数据表末尾的可订购产品附录。

2 应用

•

固态激光雷达

电机控制反馈

无损检测

雷达和智能天线阵列

军需品指导

10MHz IF 时的频谱

（SFDR = 90dBc，SNR = 71.2dBFS，

SINAD = 71.1dBFS，THD = 89dBc）

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

0

2.5

5 7.5

Frequency (MHz)

10

12.5

D802

1

本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确

性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SBAS958

ADC3421-Q1

ZHCSKL4 –DECEMBER 2019

www.ti.com.cn

8.2 Functional Block Diagram ....................................... 18

8.3 Feature Description................................................. 19

8.4 Device Functional Modes........................................ 23

8.5 Programming........................................................... 26

8.6 Register Maps......................................................... 31

Applications and Implementation ...................... 53

9.1 Application Information............................................ 53

9.2 Typical Applications ................................................ 54

1

2

3

4

5

6

特性.......................................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

Pin Configuration and Functions......................... 3

Specifications......................................................... 5

6.1 Absolute Maximum Ratings ...................................... 5

6.2 ESD Ratings.............................................................. 5

6.3 Recommended Operating Conditions....................... 5

6.4 Thermal Information.................................................. 6

6.5 Electrical Characteristics: General............................ 6

6.6 Electrical Characteristics: AC Performance.............. 7

6.7 Digital Characteristics ............................................... 9

6.8 Timing Requirements: General ................................. 9

6.9 Timing Requirements: LVDS Output....................... 10

6.10 Typical Characteristics.......................................... 11

Parameter Measurement Information ................ 16

7.1 Timing Diagrams..................................................... 16

Detailed Description ............................................ 18

8.1 Overview ................................................................. 18

9

10 Power Supply Recommendations ..................... 56

11 Layout................................................................... 57

11.1 Layout Guidelines ................................................. 57

11.2 Layout Example .................................................... 57

12 器件和文档支持 ..................................................... 58

12.1 接收文档更新通知 ................................................. 58

12.2 支持资源................................................................ 58

12.3 商标....................................................................... 58

12.4 静电放电警告......................................................... 58

12.5 Glossary................................................................ 58

13 机械、封装和可订购信息....................................... 58

7

8

4 修订历史记录

注：之前版本的页码可能与当前版本有所不同。

日期

修订版本

说明

2019 年 12 月

*

初始发行版。

2

ADC3421-Q1

www.ti.com.cn

ZHCSKL4 –DECEMBER 2019

5 Pin Configuration and Functions

RWE Package

VQFNP-56

Top View

DA1P

DA1M

DA0P

DA0M

DVDD

AVDD

INAM

INAP

1

42

41

40

39

38

37

36

35

34

33

32

31

30

29

DD0M

DD0P

DD1M

DD1P

DVDD

PDN

2

3

4

5

6

7

AVDD

INDM

INDP

Thermal Pad

8

9

AVDD

INBP

10

11

12

13

14

AVDD

INCP

INBM

AVDD

INCM

AVDD

Not to scale

3

ADC3421-Q1

ZHCSKL4 –DECEMBER 2019

www.ti.com.cn

Pin Functions

I/O

DESCRIPTION

NAME

NO.

6, 7, 10, 11, 14,

15, 20, 23, 28, 29,

32, 33, 36

AVDD

I

Analog 1.8-V power supply

CLKM

CLKP

DA0M

DA0P

DA1M

DA1P

DB0M

DB0P

DB1M

DB1P

DC0M

DC0P

DC1M

DC1P

DD0M

DD0P

DD1M

DD1P

DCLKM

DCLKP

DVDD

FCLKM

FCLKP

INAM

INAP

21

I

Negative differential clock input for the ADC

Positive differential clock input for the ADC

Negative serial LVDS output for wire-0 of channel A

Positive serial LVDS output for wire-0 of channel A

Negative serial LVDS output for wire-1 of channel A

Positive serial LVDS output for wire-1 of channel A

Negative serial LVDS output for wire-0 of channel B

Positive serial LVDS output for wire-0 of channel B

Negative serial LVDS output for wire-1 of channel B

Positive serial LVDS output for wire-1 of channel B

Negative serial LVDS output for wire-0 of channel C

Positive serial LVDS output for wire-0 of channel C

Negative serial LVDS output for wire-1 of channel C

Positive serial LVDS output for wire-1 of channel C

Negative serial LVDS output for wire-0 of channel D

Positive serial LVDS output for wire-0 of channel D

Negative serial LVDS output for wire-1 of channel D

Positive serial LVDS output for wire-1 of channel D

Negative bit clock output

22

I

4

O

I

3

2

1

56

55

54

53

46

45

44

43

42

41

40

39

51

50

Positive bit clock output

5, 38, 47, 52

Digital 1.8-V power supply

49

48

8

O

I

Negative frame clock output

Positive frame clock output

Negative differential analog input for channel A

Positive differential analog input for channel A

Negative differential analog input for channel B

Positive differential analog input for channel B

Negative differential analog input for channel C

Positive differential analog input for channel C

Negative differential analog input for channel D

Positive differential analog input for channel D

9

I

INBM

INBP

13

12

30

31

35

34

I

INCM

INCP

I

INDM

INDP

I

Power-down control. This pin can be configured using the SPI. This pin has an internal

150-kΩ pulldown resistor.

PDN

37

I

RESET

SCLK

24

16

17

19

I

Hardware reset; active high. This pin has an internal 150-kΩ pulldown resistor.

Serial interface clock input. This pin has an internal 150-kΩ pulldown resistor.

Serial interface data input. This pin has an internal 150-kΩ pulldown resistor.

Serial interface data output

SDATA

SDOUT

I

O

Serial interface enable; active low.

This pin has an internal 150-kΩ pullup resistor to AVDD.

SEN

18

I

SYSREFM

SYSREFP

VCM

26

25

27

—

I

Negative external SYSREF input

Positive external SYSREF input

Common-mode voltage for analog inputs

Connect thermal pad to ground.

O

—

Thermal Pad

4

ADC3421-Q1

www.ti.com.cn

ZHCSKL4 –DECEMBER 2019

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

MAX

UNIT

V

Analog supply voltage range, AVDD

–0.3

2.1

Digital supply voltage range, DVDD

2.1

V

INAP, INBP, INCP, INDP, INAM, INBM, INCM, INDM

min (1.9, AVDD + 0.3)

CLKP, CLKM

AVDD + 0.3

3.9

Voltage applied to

input pins

V

SYSREFP, SYSREFM

SCLK, SEN, SDATA, RESET, PDN

Operating junction, T_J

Storage, T_stg

150

Temperature

ºC

–65

150

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

VALUE

UNIT

Human-body model (HBM), per AEC Q100-002⁽¹⁾

HBM ESD Classification Level 2

±2000

V_(ESD)

Electrostatic discharge

V

Charged-device model (CDM), per AEC Q100-011

CDM ESD Classification Level C5

±750

(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

6.3 Recommended Operating Conditions⁽¹⁾

over operating free-air temperature range (unless otherwise noted)

MIN

NOM

MAX

UNIT

Supplies

AVDD

Analog supply voltage range

Digital supply voltage range

1.7

1.8

1.9

V

DVDD

Analog Input

For input frequencies < 450 MHz

For input frequencies < 600 MHz

2

1

V_ID

Differential input voltage

V_PP

V

V_IC

Input common-mode voltage

Input clock frequency

VCM ± 0.025

Clock Input

Sampling clock frequency

Sine wave, ac-coupled

LPECL, ac-coupled

15⁽²⁾

25

MSPS

V_PP

0.2

1.5

1.6

Input clock amplitude (differential)

LVDS, ac-coupled

0.7

Input clock duty cycle

35%

50%

0.95

65%

Input clock common-mode voltage

V

Digital Outputs

Maximum external load capacitance

C_LOAD

3.3

pF

from each output pin to GND

R_LOAD

Temperature

T_JOperating Junction Temperature

Single-ended load resistance

100

Ω

–40

125

°C

(1) After power-up, use only the RESET pin to reset the device for the first time; see the Register Initialization section for details.

(2) See 表 1 for details.

5

ADC3421-Q1

ZHCSKL4 –DECEMBER 2019

www.ti.com.cn

6.4 Thermal Information

ADC3421-Q1

THERMAL METRIC⁽¹⁾

RWE (VQFNP)

UNIT

56 PINS

20.3

8.8

R_θJA

Junction-to-ambient thermal resistance

°C/W

R_θJC(top)

R_θJB

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

5.6

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

0.1

ψ_JB

5.6

R_θJC(bot)

0.7

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report.

6.5 Electrical Characteristics: General

Typical values are over the operating free-air temperature range, at T_A= 25°C, full temperature range is T_MIN= –40°C to T_MAX

= 125°C, maximum sampling rate, 50% clock duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS differential input, unless

otherwise noted.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

MSPS

Bits

ADC clock frequency

25

Resolution

12

1.8-V analog supply current

1.8-V digital supply current

Total power dissipation

Global power-down dissipation

Standby power-down dissipation

54

45

71

mA

177

5

240

17

mW

34

75

Analog Input

Differential input full-scale

Input resistance

2.0

6.6

3.7

0.95

10

V_PP

kΩ

r_i

Differential at dc

c_i

Input capacitance

pF

V_OC(VCM)

VCM common-mode voltage output

VCM output current capability

Input common-mode current

V

mA

Per analog input pin

1.5

µA/MSPS

50-Ω differential source driving 50-Ω termination

across INP and INM

Analog input bandwidth (3 dB)

540

MHz

DC accuracy

E_O

Offset error

–25

–2

25

2

mV

α_EO

Temperature coefficient of offset error

± 0.024

mV/°C

Gain error as a result of internal

reference inaccuracy alone

E_G(REF)

%FS

E_G(CHAN)

Gain error of channel alone

–2

%FS

α_(EGCHAN)

Temperature coefficient of E_G(CHAN)

±0.008

Δ%FS/Ch

Channel-to-channel Isolation

Near channel

f_IN= 10 MHz

105

95

Far channel

Near channel

f_IN= 100 MHz

Far channel

105

94

Near channel

f_IN= 200 MHz

Crosstalk⁽¹⁾

dB

Far channel

105

92

Near channel

f_IN= 230 MHz

Far channel

105

85

Near channel

f_IN= 300 MHz

Far channel

105

(1) Crosstalk is measured with a –1-dBFS input signal on the aggressor channel and no input on the victim channel.

6

ADC3421-Q1

www.ti.com.cn

ZHCSKL4 –DECEMBER 2019

6.6 Electrical Characteristics: AC Performance

Typical values are over the operating free-air temperature range, at T_A= 25°C, full temperature range is T_MIN= –40°C to T_MAX

= 125°C, ADC sampling rate = 25 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS differential input,

unless otherwise noted.

DITHER ON

MIN

DITHER OFF

MIN MAX

PARAMETER

TEST CONDITIONS

UNIT

TYP

70.9

70.7

70.4

70.3

69.7

68.9

70.2

70.1

69.8

69.6

69.2

68.3

–141.5

MAX

TYP

71.1

70.9

70.6

70.5

69.9

69.1

70.5

70.3

70.0

69.8

69.3

68.5

–141.7

–141.5

–141.2

–141.1

–140.5

–139.7

71.1

70.9

70

f_IN= 10 MHz

f_IN= 20 MHz

f_IN= 70 MHz

f_IN= 100 MHz

f_IN= 170 MHz

f_IN= 230 MHz

f_IN= 10 MHz

f_IN= 20 MHz

f_IN= 70 MHz

f_IN= 100 MHz

f_IN= 170 MHz

f_IN= 230 MHz

f_IN= 10 MHz

f_IN= 20 MHz

f_IN= 70 MHz

f_IN= 100 MHz

f_IN= 170 MHz

f_IN= 230 MHz

f_IN= 10 MHz

f_IN= 20 MHz

f_IN= 70 MHz

f_IN= 100 MHz

f_IN= 170 MHz

f_IN= 230 MHz

f_IN= 10 MHz

f_IN= 20 MHz

f_IN= 70 MHz

f_IN= 100 MHz

f_IN= 170 MHz

f_IN= 230 MHz

f_IN= 10 MHz

f_IN= 20 MHz

f_IN= 70 MHz

f_IN= 100 MHz

f_IN= 170 MHz

f_IN= 230 MHz

68.9

Signal-to-noise ratio

(from 1-MHz offset)

dBFS

SNR

Signal-to-noise ratio

(full Nyquist band)

dBFS

dBFS/Hz

dBFS

Bits

–141.3 –139.5

–141.0

–140.9

–140.3

–139.5

71

Noise spectral density

(averaged across Nyquist zone)

NSD⁽¹⁾

67.9

70.8

69.5

70.5

69.6

68.7

11.5

11.4

11.3

11.1

93

Signal-to-noise and distortion

ratio

SINAD⁽¹⁾

ENOB⁽¹⁾

SFDR

70.7

69.8

68.7

11.5

11.4

11.3

11.1

90

11

Effective number of bits

84

91

85

93

88

Spurious-free dynamic range

dBc

85

82

86

85

82

(1) Reported from a 1-MHz offset.

7

ADC3421-Q1

ZHCSKL4 –DECEMBER 2019

www.ti.com.cn

Electrical Characteristics: AC Performance (continued)

Typical values are over the operating free-air temperature range, at T_A= 25°C, full temperature range is T_MIN= –40°C to T_MAX

= 125°C, ADC sampling rate = 25 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS differential input,

unless otherwise noted.

DITHER ON

MIN

DITHER OFF

MIN MAX

PARAMETER

TEST CONDITIONS

UNIT

TYP

93

100

93

94

86

96

91

93

85

89

82

99

98

96

95

92

97

90

89

84

80

MAX

TYP

92

94

92

93

85

82

90

85

88

82

89

82

92

91

92

93

90

91

86

83

85

80

83

79

f_IN= 10 MHz

f_IN= 20 MHz

f_IN= 70 MHz

f_IN= 100 MHz

f_IN= 170 MHz

f_IN= 230 MHz

f_IN= 10 MHz

f_IN= 20 MHz

f_IN= 70 MHz

f_IN= 100 MHz

f_IN= 170 MHz

f_IN= 230 MHz

f_IN= 10 MHz

f_IN= 20 MHz

f_IN= 70 MHz

f_IN= 100 MHz

f_IN= 170 MHz

f_IN= 230 MHz

f_IN= 10 MHz

f_IN= 20 MHz

f_IN= 70 MHz

f_IN= 100 MHz

f_IN= 170 MHz

f_IN= 230 MHz

83

82

86

78

Second-order harmonic

distortion

HD2

dBc

HD3

Non

Third-order harmonic distortion

dBc

Spurious-free dynamic range

HD2, HD3 (excluding HD2, HD3)

THD

Total harmonic distortion

dBc

f_IN1= 45 MHz,

f_IN2= 50 MHz

–98

–91

–98

–91

Two-tone, third-order

intermodulation distortion

IMD3

dBFS

f_IN1= 185 MHz,

f_IN2= 190 MHz

8

ADC3421-Q1

www.ti.com.cn

ZHCSKL4 –DECEMBER 2019

6.7 Digital Characteristics

The dc specifications refer to the condition where the digital outputs are not switching, but are permanently at a valid logic

level 0 or 1. AVDD = DVDD = 1.8 V, and –1-dBFS differential input, unless otherwise noted.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Digital Inputs (RESET, SCLK, SDATA, SEN, PDN)

All digital inputs support 1.8-V and

3.3-V CMOS logic levels

V_IH

V_IL

High-level input voltage

Low-level input voltage

1.3

V

All digital inputs support 1.8-V and

3.3-V CMOS logic levels

0.4

RESET, SDATA, SCLK,

PDN

SEN⁽¹⁾

V_HIGH= 1.8 V

V_LOW= 0 V

10

0

µA

High-level input

current

I_IH

RESET, SDATA, SCLK,

PDN

0

Low-level input

current

I_IL

SEN

V_LOW= 0 V

10

DigitaL Inputs (SYSREFP, SYSREFM)

V_IH

V_IL

High-level input voltage

1.3

0.5

0.9

V

Low-level input voltage

Common-mode voltage for SYSREF

Digital Outputs (CMOS Interface, SDOUT)

V_OH

V_OL

High-level output voltage

Low-level output voltage

DVDD – 0.1

DVDD

0

V

0.1

Digital Outputs (LVDS Interface)

V_ODH

V_ODL

V_OCM

High-level output differential voltage

With an external 100-Ω termination

280

350

–350

1.05

460

mV

V

Low-level output differential voltage

Output common-mode voltage

–460

–280

(1) SEN has an internal 150-kΩ pullup resistor to AVDD. SPI pins (SEN, SCLK, SDATA) can be driven by 1.8 V or 3.3 V CMOS buffers.

6.8 Timing Requirements: General

Typical values are at T_A= 25°C, AVDD = DVDD = 1.8 V, and –1-dBFS differential input, unless otherwise noted. Minimum

and maximum values are across the full temperature range: T_MIN= –40°C to T_MAX= 125°C.

MIN

TYP

1.44

±70

±150

130

35

MAX

UNIT

ns

t_A

Aperture delay

1.24

1.64

Aperture delay matching between two channels of the same device

Aperture delay variation between two devices at same temperature and supply voltage

Aperture jitter

ps

t_J

f_Srms

µs

Time to valid data after exiting standby power-down mode

200

450

Wake-up time:

ADC latency⁽¹⁾

Time to valid data after exiting global power-down mode

(in this mode, both channels power down)

85

9

µs

Clock

cycles

2-wire mode (default)

1-wire mode

:

Clock

cycles

8

t_{SU_SYSREF}

Setup time for SYSREF referenced to input clock rising edge

Hold time for SYSREF referenced to input clock rising edge

1000

100

ps

SYSREF reference time:

t_{H_SYSREF}

(1) Overall latency = ADC latency + t_PDI

.

9

ADC3421-Q1

ZHCSKL4 –DECEMBER 2019

www.ti.com.cn

6.9 Timing Requirements: LVDS Output⁽¹⁾⁽²⁾

Typical values are at T_A= 25°C, AVDD = DVDD = 1.8 V, and –1-dBFS differential input, 6x Serialization (2-Wire Mode),

C_LOAD= 3.3 pF⁽³⁾, and R_LOAD= 100 Ω⁽⁴⁾, unless otherwise noted.. Minimum and maximum values are across the full

temperature range: T_MIN= –40°C to T_MAX= 125°C.

MIN

1.3

TYP

1.48

3.06

1.57

3.12

MAX

UNIT

1-wire mode

2-wire mode

1-wire mode

2-wire mode

Data setup time: data valid to zero-crossing of differential

output clock (CLKOUTP – CLKOUTM)⁽⁵⁾⁽⁶⁾

t_SU

ns

2.61

1.32

2.75

Data hold time: zero-crossing of differential output clock

(CLKOUTP – CLKOUTM) to data becoming invalid⁽⁵⁾⁽⁶⁾

t_HO

ns

Clock propagation delay: input clock falling edge cross-over to 1-wire mode

frame clock rising edge cross-over

(15 MSPS < sampling frequency < 25 MSPS)

0.1 × t_S+ t_DELAY

0.61 × t_S+ t_DELAY

ns

t_PDI

2-wire mode

t_DELAY

Delay time

3

4.5

5.9

LVDS bit clock duty cycle: duty cycle of differential clock

(CLKOUTP – CLKOUTM)

49%

t_FALL

t_RISE

,

Data fall time, data rise time: rise time measured from –100 mV to 100 mV,

15 MSPS ≤ Sampling frequency ≤ 25 MSPS

0.11

ns

t_CLKRISE

t_CLKFALL

,

Output clock rise time, output clock fall time: rise time measured from

–100 mV to 100 mV, 15 MSPS ≤ Sampling frequency ≤ 25 MSPS

(1) Measurements are done with a transmission line of a 100-Ω characteristic impedance between the device and load. Setup and hold time

specifications take into account the effect of jitter on the output data and clock.

(2) Timing parameters are ensured by design and characterization and are not tested in production.

(3) C_LOADis the effective external single-ended load capacitance between each output pin and ground.

(4) R_LOADis the differential load resistance between the LVDS output pair.

(5) Data valid refers to a logic high of 100 mV and a logic low of –100 mV.

(6) Write relevant register settings as mentioned in 表 22.

10

ADC3421-Q1

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6.10 Typical Characteristics

typical values are at T_A= 25°C, ADC sampling rate = 25 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1-

dBFS differential input, 2-V_PPfull-scale, 32k-point FFT, chopper disabled, and SNR reported with a 1-MHz offset from dc

when chopper is disabled and from f_S/ 2 when chopper is enabled (unless otherwise noted).

0

-10

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-100

-110

-120

0

2.5

5 7.5

Frequency (MHz)

10

12.5

0

2.5

5 7.5

Frequency (MHz)

10

12.5

D801

D802

SFDR = 95 dBc, SNR = 71 dBFS, SINAD = 71 dBFS,

THD = 94 dBc, HD2 = 106 dBc, HD3 = 95 dBc

SFDR = 90 dBc, SNR = 71.2 dBFS, SINAD = 71.1 dBFS,

THD = 89 dBc, HD2 = 90 dBc, HD3 = 106 dBc

图 1. FFT for 10-MHz Input Signal (Dither On)

图 2. FFT for 10-MHz Input Signal (Dither Off)

0

-10

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-100

-110

-120

0

2.5

5 7.5

Frequency (MHz)

10

12.5

0

2.5

5 7.5

Frequency (MHz)

10

12.5

D803

D804

SFDR = 92 dBc, SNR = 70.5 dBFS, SINAD = 70.3 dBFS,

THD = 91 dBc, HD2 = 105 dBc, HD3 = 92 dBc

SFDR = 91 dBc, SNR = 70.7 dBFS, SINAD = 70.6 dBFS,

THD = 88 dBc, HD2 = 91 dBc, HD3 = 101 dBc

图 3. FFT for 70-MHz Input Signal (Dither On)

图 4. FFT for 70-MHz Input Signal (Dither Off)

0

-10

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-100

-110

-120

0

2.5

5 7.5

Frequency (MHz)

10

12.5

0

2.5

5 7.5

Frequency (MHz)

10

12.5

D805

D806

SFDR = 87 dBc, SNR = 69.8 dBFS, SINAD = 69.7 dBFS,

THD = 85 dBc, HD2 = 90 dBc, HD3 = 87 dBc

SFDR = 85 dBc, SNR = 70 dBFS, SINAD = 69.8 dBFS,

THD = 86 dBc, HD2 = 85 dBc, HD3 = 92 dBc

图 5. FFT for 170-MHz Input Signal (Dither On)

图 6. FFT for 170-MHz Input Signal (Dither Off)

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ZHCSKL4 –DECEMBER 2019

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Typical Characteristics (接下页)

typical values are at T_A= 25°C, ADC sampling rate = 25 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1-

dBFS differential input, 2-V_PPfull-scale, 32k-point FFT, chopper disabled, and SNR reported with a 1-MHz offset from dc

when chopper is disabled and from f_S/ 2 when chopper is enabled (unless otherwise noted).

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-100

-110

-120

0

2.5

5 7.5

Frequency (MHz)

10

12.5

0

2.5

5 7.5

Frequency (MHz)

10

12.5

D807

D808

SFDR = 77 dBc, SNR = 68.2 dBFS, SINAD = 67.7 dBFS,

THD = 75 dBc, HD2 = 77 dBc, HD3 = 83 dBc

SFDR = 75 dBc, SNR = 68.4 dBFS, SINAD = 67.5 dBFS,

THD = 74 dBc, HD2 = 75 dBc, HD3 = 80 dBc

图 7. FFT for 270-MHz Input Signal (Dither On)

图 8. FFT for 270-MHz Input Signal (Dither Off)

0

-10

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-100

-110

-120

0

2.5

5 7.5

Frequency (MHz)

10

12.5

0

2.5

5 7.5

Frequency (MHz)

10

12.5

D809

D810

SFDR = 67 dBc, SNR = 66.4 dBFS, SINAD = 66.4 dBFS,

THD = 93 dBc, HD2 = 67 dBc, HD3 = 88 dBc

SFDR = 66 dBc, SNR = 66.5 dBFS, SINAD = 66.5 dBFS,

THD = 87 dBc, HD2 = 66 dBc, HD3 = 93 dBc

图 9. FFT for 450-MHz Input Signal (Dither On)

图 10. FFT for 450-MHz Input Signal (Dither Off)

0

-10

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-100

-110

-120

0

2.5

5 7.5

Frequency (MHz)

10

12.5

0

2.5

5 7.5

Frequency (MHz)

10

12.5

D811

D812

f_IN1= 46 MHz, f_IN2= 50 MHz, IMD3 = 90,

each tone at = –7 dBFS

f_IN1= 46 MHz, f_IN2= 50 MHz, IMD3 = 105,

each tone at = –36 dBFS

图 11. FFT for Two-Tone Input Signal

图 12. FFT for Two-Tone Input Signal

(–7 dBFS at 46 MHz and 50 MHz)

(–36 dBFS at 46 MHz and 50 MHz)

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Typical Characteristics (接下页)

typical values are at T_A= 25°C, ADC sampling rate = 25 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1-

dBFS differential input, 2-V_PPfull-scale, 32k-point FFT, chopper disabled, and SNR reported with a 1-MHz offset from dc

when chopper is disabled and from f_S/ 2 when chopper is enabled (unless otherwise noted).

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-100

-110

-120

0

2.5

5 7.5

Frequency (MHz)

10

12.5

0

2.5

5 7.5

Frequency (MHz)

10

12.5

D813

D814

f_IN1= 184.5 MHz, f_IN2= 189.5 MHz, IMD3 = 91,

each tone at = –7 dBFS

f_IN1= 184.5 MHz, f_IN2= 189.5 MHz, IMD3 = 98 dBFS,

each tone at –36 dBFS

图 13. FFT for Two-Tone Input Signal

图 14. FFT for Two-Tone Input Signal

(–7 dBFS at 185 MHz and 190 MHz)

(–36 dBFS at 185 MHz and 190 MHz)

-85

-90

-95

-100

-105

-110

-100

-105

-35

-31

-27

Each Tone Amplitude (dBFS)

-23

-19

-15

-11

-7

-35

-31

-27

Each Tone Amplitude (dBFS)

-23

-19

-15

-11

-7

D815

D816

图 15. Intermodulation Distortion vs Input Amplitude

图 16. Intermodulation Distortion vs Input Amplitude

(46 MHz and 50 MHz)

(185 MHz and 190 MHz)

72

100

Dither_EN

Dither_DIS

Dither_EN

Dither_DIS

95

90

85

80

75

70

65

60

71

70

69

68

67

66

0

50

100

150

Frequency (MHz)

200

250

300

350

400

0

50

100

150

Frequency (MHz)

200

250

300

350

400

D80117

D818

图 17. Signal-to-Noise Ratio vs Input Frequency

图 18. Spurious-Free Dynamic Range vs

Input Frequency

13

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ZHCSKL4 –DECEMBER 2019

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Typical Characteristics (接下页)

typical values are at T_A= 25°C, ADC sampling rate = 25 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1-

dBFS differential input, 2-V_PPfull-scale, 32k-point FFT, chopper disabled, and SNR reported with a 1-MHz offset from dc

when chopper is disabled and from f_S/ 2 when chopper is enabled (unless otherwise noted).

73

72

71

70

69

68

250

200

150

100

50

72.5

280

240

200

160

120

80

SNR (dBFS)

SFDR (dBc)

SFDR (dBFS)

SNR (dBFS)

SFDR (dBc)

SFDR (dBFS)

72

71.5

71

70.5

70

69.5

69

40

0

-70

-60

-50

-40 -30

Amplitude (dBFS)

-20

-10

0

-70

-60

-50

-40 -30

Amplitude (dBFS)

-20

-10

0

D819

D820

图 19. Performance vs Input Amplitude (30 MHz)

图 20. Performance vs Input Amplitude (170 MHz)

78

76

74

72

70

68

105

SNR

SFDR

76

88

SNR

SFDR

100

95

74

72

70

68

66

86

84

82

80

78

90

85

80

0.85

0.9

0.95

1

Input Common-Mode Voltage (V)

1.05

1.1

0.85

0.9

0.95

1

Input Common-Mode Voltage (V)

1.05

1.1

D821

D822

图 21. Performance vs Input Common-Mode Voltage

图 22. Performance vs Input Common-Mode Voltage (170

MHz)

(30 MHz)

105

72

AVDD=1.7 V

AVDD=1.75 V

AVDD=1.8 V

AVDD=1.85 V

AVDD=1.9 V

AVDD=1.7 V

AVDD=1.75 V

AVDD=1.8 V

AVDD=1.85 V

AVDD=1.9 V

101

97

93

89

85

71.6

71.2

70.8

70.4

70

-40

-20

0

20

40 60

Temperature (°C)

80

100 120 140

-40

-20

0

20

40 60

Temperature (°C)

80

100 120 140

D900

D901

图 23. Spurious-Free Dynamic Range vs

AVDD Supply and Temperature (30 MHz)

图 24. Signal-to-Noise Ratio vs

AVDD Supply and Temperature (30 MHz)

14

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Typical Characteristics (接下页)

typical values are at T_A= 25°C, ADC sampling rate = 25 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1-

dBFS differential input, 2-V_PPfull-scale, 32k-point FFT, chopper disabled, and SNR reported with a 1-MHz offset from dc

when chopper is disabled and from f_S/ 2 when chopper is enabled (unless otherwise noted).

99

97

95

93

91

89

87

71.1

71.05

71

DVDD=1.7 V

DVDD=1.75 V

DVDD=1.8 V

DVDD=1.85 V

DVDD=1.9 V

DVDD = 1.7 V

DVDD = 1.75 V

DVDD = 1.8 V

DVDD = 1.85 V

DVDD = 1.9 V

70.95

70.9

70.85

70.8

70.75

70.7

70.65

70.6

-40

-20

0

20

40 60

Temperature (°C)

80

100 120 140

-40

-20

0

20

40 60

Temperature (°C)

80

100 120 140

D902

D904

图 25. Spurious-Free Dynamic Range vs

图 26. Signal-to-Noise Ratio vs

DVDD Supply and Temperature (30 MHz)

75

74

73

72

71

70

69

68

67

100

96

92

88

84

80

76

72

68

76

100

SNR

SFDR

SNR

SFDR

73

70

67

64

61

58

90

80

70

60

50

40

0.2 0.4 0.6 0.8

1

Differential Clock Amplitude (Vpp)

1.2 1.4 1.6 1.8

2

2.2

0.2 0.4 0.6 0.8

1

Differential Clock Amplitude (Vpp)

1.2 1.4 1.6 1.8

2

2.2

D827

D828

图 27. Performance vs Clock Amplitude (40 MHz)

图 28. Performance vs Clock Amplitude (150 MHz)

70.6

70.4

70.2

70

90

71.5

71.3

71.1

70.9

70.7

70.5

100

SNR

SFDR

SNR

SFDR

88

98

96

94

92

90

86

84

82

80

78

69.8

69.6

69.4

30

35

40

45

Input Clock Duty Cycle (%)

50

55

60

65

70

30

35

40

45

Input Clock Duty Cycle (%)

50

55

60

65

70

D829

D830

图 29. Performance vs Clock Duty Cycle (30 MHz)

图 30. Performance vs Clock Duty Cycle (150 MHz)

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Typical Characteristics (接下页)

typical values are at T_A= 25°C, ADC sampling rate = 25 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1-

dBFS differential input, 2-V_PPfull-scale, 32k-point FFT, chopper disabled, and SNR reported with a 1-MHz offset from dc

when chopper is disabled and from f_S/ 2 when chopper is enabled (unless otherwise noted).

0.15

0.1

0.05

0

0.05

0

-0.05

-0.1

-0.15

-0.05

-0.1

-0.15

0

512 1024 1536 2048 2560 3072 3584 4096

Output Code (LSB)

0

512 1024 1536 2048 2560 3072 3584 4096

Output Code (LSB)

D001

D1002

图 31. Integral Nonlinearity for a 20-MHz Input

图 32. Differential Nonlinearity for a 20-MHz Input

7 Parameter Measurement Information

7.1 Timing Diagrams

DAn_P

DBn_P

Logic 0

V_ODL= -350 mV⁽¹⁾

Logic 1

V_ODH= +350 mV⁽¹⁾

DAn_M

DBn_M

V_OCM

GND

(1) With an external 100-Ω termination.

图 33. Serial LVDS Output Voltage Levels

16

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Timing Diagrams (接下页)

CLKIN

FCLK

DCLK

Dx0P

1-Wire (12x Serialization)

D

9

D D

10 11

D

0

D

1

D

2

D

3

D

4

D

5

D

6

D

7

D

8

D

9

D D

10 11

D

0

Dx0M

DCLK

Dx0P

Dx0M

D

5

D

0

D

1

D

2

D

3

D

4

D

5

D

0

2-Wire (6x Serialization)

Dx1P

Dx1M

D

11

D

6

D

7

D

8

D

9

D

10

D

11

D

6

SAMPLE N-1

SAMPLE N

SAMPLE N+1

图 34. Output Timing Diagram

DCLK

t _HO

Dx0P

Dx0M

t _SU

图 35. Setup and Hold Time

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ZHCSKL4 –DECEMBER 2019

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8 Detailed Description

8.1 Overview

The ADC3421-Q1 is an automotive-grade, high-linearity, ultra-low power, quad-channel, 12-bit, 25-MSPS analog-

to-digital converter (ADC). The device is designed specifically to support demanding, high input frequency signals

with large dynamic range requirements. An input clock divider gives more flexibility for system clock architecture

design, and the SYSREF input enables complete system synchronization. The ADC3421-Q1 supports a serial

low-voltage differential signaling (LVDS) interface in order to reduce the number of interface lines, thus allowing

for high system integration density. The serial LVDS interface is two-wire, where each ADC data are serialized

and output over two LVDS pairs. An internal phase-locked loop (PLL) multiplies the incoming ADC sampling

clock to derive the bit clock that is used to serialize the 12-bit output data from each channel. In addition to the

serial data streams, the frame and bit clocks are also transmitted as LVDS outputs.

8.2 Functional Block Diagram

DA0P

DA0M

INAP

INAM

12-Bit

ADC

Digital Encoder

and Serializer

DA1P

DA1M

DB0P

DB0M

Digital Encoder

and Serializer

INBP

INBM

12-Bit

ADC

DB1P

DB1M

Bit Clock

CLKP

CLKM

Divide

by 1,2,4

DCLKP

DCLKM

PLL

Frame Clock

FCLKP

FCLKM

SYSREFP

SYSREFM

DC0P

DC0M

INCP

INCM

12-Bit

ADC

Digital Encoder

and Serializer

DC1P

DC1M

DD0P

DD0M

INDP

INDM

12-Bit

ADC

Digital Encoder

and Serializer

DD1P

DD1M

Common

Mode

Configuration

Registers

VCM

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8.3 Feature Description

8.3.1 Analog Inputs

The ADC3421-Q1 analog signal inputs are designed to be driven differentially. Each input pin (INP, INM) must

swing symmetrically between (VCM + 0.5 V) and (VCM – 0.5 V), resulting in a 2-V_PP(default) differential input

swing. The input sampling circuit has a 3-dB bandwidth that extends up to 540 MHz (50-Ω source driving 50-Ω

termination between INP and INM).

8.3.2 Clock Input

The device clock inputs can be driven differentially (sine, LVPECL, or LVDS) or single-ended (LVCMOS), with

little or no difference in performance between them. The common-mode voltage of the clock inputs is set to

0.95 V using internal 5-kΩ resistors. The self-bias clock inputs of the ADC3421-Q1 can be driven by the

transformer-coupled, sine-wave clock source or by the ac-coupled, LVPECL and LVDS clock sources, as shown

in 图 36, 图 37, and 图 38. See 图 39 for details regarding the internal clock buffer.

0.1 …F

Z_O

CLKP

Differential

Sine-Wave

Clock Input

Typical LVDS

Clock Input

R_T

TI Device

100 Ω

0.1 …F

TI Device

0.1 …F

Z_O

CLKM

NOTE: R_T= termination resistor, if necessary.

图 36. Differential Sine-Wave Clock Driving Circuit

图 37. LVDS Clock Driving Circuit

0 …F

Z_O

CLKP

150 Ω

Typical LVPECL

Clock Input

100 Ω

TI Device

CLKM

0 …F

Z_O

150 Ω

图 38. LVPECL Clock Driving Circuit

19

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ZHCSKL4 –DECEMBER 2019

www.ti.com.cn

Clock Buffer

L_PKG

2 nH

20 Ω

CLKP

C_BOND

1 pF

5 kΩ

C_EQ

R_ESR

100 Ω

0.95 V

C_EQ

L_PKG

2 nH

5 kΩ

20 Ω

CLKM

C_BOND

1 pF

R_ESR

100 Ω

NOTE: C_EQis 1 pF to 3 pF and is the equivalent input capacitance of the clock buffer.

图 39. Internal Clock Buffer

A single-ended CMOS clock can be ac-coupled to the CLKP input, with CLKM connected to ground with a 0.1-μF

capacitor, as shown in 图 40. However, for best performance the clock inputs must be driven differentially,

thereby reducing susceptibility to common-mode noise. For high input frequency sampling, TI recommends using

a clock source with very low jitter. Band-pass filtering of the clock source can help reduce the effects of jitter.

There is no change in performance with a non-50% duty cycle clock input.

0.1 …F

CMOS

Clock Input

CLKP

TI Device

0.1 …F

CLKM

图 40. Single-Ended Clock Driving Circuit

8.3.2.1 SNR and Clock Jitter

The signal-to-noise ratio of the ADC is limited by three different factors, as shown in 公式 1. Quantization noise

(typically 74 dB for a 12-bit ADC) and thermal noise limit SNR at low input frequencies, and the clock jitter sets

SNR for higher input frequencies.

2

SNR_{Quantization_Noise}

SNR_{Thermal_Noise}

SNR_Jitter

20

≈

’

÷

◊

≈

’

÷

◊

≈

’

÷

-

∆

20

∆

SNR_ADC[dBc] = -20 ∂log 10

+ 10

∆

«

∆

«

∆

«

÷

◊

(1)

(2)

The SNR limitation resulting from sample clock jitter can be calculated with 公式 2.

SNR_Jitter[dBc] = -20 ∂log 2p∂ f ∂ t

(

)

in Jitter

20

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ZHCSKL4 –DECEMBER 2019

The total clock jitter (T_Jitter) has two components: the internal aperture jitter (130 fs for the device) which is set by

the noise of the clock input buffer and the external clock. T_Jittercan be calculated with 公式 3.

2

t_Jitter

=

t

+ t

(

)

(

)

Aperture _ ADC

Jitter,Ext.Clock _Input

(3)

External clock jitter can be minimized by using high-quality clock sources and jitter cleaners as well as band-pass

filters at the clock input; a faster clock slew rate improves the ADC aperture jitter. The devices have a typical

thermal noise of 70.6 dBFS and internal aperture jitter of 130 fs. The SNR, depending on the amount of external

jitter for different input frequencies, is shown in 图 41.

71.0

70.5

70.0

69.5

69.0

68.5

Ext Clock Jitter

35 fs

50 fs

68.0

67.5

67.0

66.5

66.0

65.5

65.0

100 fs

150 fs

200 fs

10

100

Input Frequency (MHz)

1000

D00316

图 41. SNR vs Frequency for Different Clock Jitter

8.3.3 Digital Output Interface

The devices offer two different output format options, thus making interfacing to a field-programmable gate array

(FPGA) or an application-specific integrated circuit (ASIC) easy. Each option can be easily programmed using

the serial interface, as shown in 表 1. The output interface options are:

•

One-wire, 1x frame clock, 12x serialization with the DDR bit clock and

Two-wire, 1x frame clock, 6x serialization with the DDR bit clock.

表 1. Interface Rates

RECOMMENDED SAMPLING

FREQUENCY (MSPS)

BIT CLOCK

FREQUENCY

(MHz)

FRAME CLOCK

FREQUENCY

(MHz)

SERIAL DATA

RATE PER

WIRE (Mbps)

INTERFACE

OPTIONS

SERIALIZATION

MINIMUM

MAXIMUM

15

90

150

60

15

25

20

180

300

120

One-wire

12x

6x

25

Two-wire

(Default after

Reset)

20⁽¹⁾

25

75

25

150

(1) Use the LOW SPEED ENABLE register bits for low speed operation; see .

8.3.3.1 One-Wire Interface: 12x Serialization

In this interface option, the device outputs the data of each ADC serially on a single LVDS pair (one-wire). The

data are available at the rising and falling edges of the bit clock (DDR bit clock). The ADC outputs a new word at

the rising edge of every frame clock, starting with the LSB. The data rate is 12x sample frequency (12x

serialization).

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ZHCSKL4 –DECEMBER 2019

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8.3.3.2 Two-Wire Interface: 6x Serialization

In two-wire interface ,the output data rate is 6x sample frequency because six data bits are output every clock

cycle on each differential pair. Each ADC sample is sent over the two wires with the six MSBs on Dx1P, Dx1M

and the six LSBs on Dx0P, Dx0M, as shown in 图 42.

CLKIN

FCLK

DCLK

1-Wire (12x Serialization)

Dx0P

Dx0M

D

9

D D

10 11

D

0

D

1

D

2

D

3

D

4

D

5

D

6

D

7

D

8

D

9

D D

10 11

D

0

DCLK

Dx0P

Dx0M

D

5

D

0

D

1

D

2

D

3

D

4

D

5

D

0

2-Wire (6x Serialization)

Dx1P

Dx1M

D

11

D

6

D

7

D

8

D

9

D

10

D

11

D

6

SAMPLE N-1

SAMPLE N

SAMPLE N+1

图 42. Output Timing Diagram

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8.4 Device Functional Modes

8.4.1 Input Clock Divider

The devices are equipped with an optional internal divider on the clock input. The clock divider allows operation

with a faster input clock (divide by 2 and divide by 4 options programmable using SPI), thus simplifying the

system clock distribution design.

8.4.2 Chopper Functionality

The devices are equipped with an internal chopper front-end. Enabling the chopper function swaps the ADC

noise spectrum by shifting the 1/f noise from dc to f_S/ 2. 图 43 shows the noise spectrum with the chopper off

and 图 44 shows the noise spectrum with the chopper on. This function is especially useful in applications

requiring good ac performance at low input frequencies or in dc-coupled applications. The chopper can be

enabled via SPI register writes and is recommended for input frequencies below 30 MHz. The chopper function

creates a spur at f_S/ 2 that must be filtered out digitally.

0

-10

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-100

-110

-120

0

2.5

5 7.5

Frequency (MHz)

10

12.5

0

2.5

5 7.5

Frequency (MHz)

10

12.5

D905

D906

SNR = 71.1 dBFS, SINAD = 71.1 dBFS

SFDR = 97 dBc ,THD = 95 dBc

SNR = 71 dBFS, SINAD = 71 dBFS

SFDR = 96 dBc, THD = 97 dBc

图 43. Chopper Off

图 44. Chopper On

8.4.3 Power-Down Control

The power-down functions of the ADC3421-Q1 can be controlled either through the parallel control pin (PDN) or

through an SPI register setting (see register 15h). The PDN pin can also be configured via SPI to a global power-

down or standby functionality, as shown in 表 2.

表 2. Power-Down Modes

FUNCTION

Global power-down

Standby

POWER CONSUMPTION (mW)

WAKE-UP TIME (µs)

5

85

35

34

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8.4.4 Internal Dither Algorithm

The ADC3421-Q1 uses an internal dither algorithm to achieve high SFDR and a clean spectrum. However, the

dither algorithm marginally degrades SNR, creating a trade-off between SNR and SFDR. If desired, the dither

algorithm can be turned off by using the DIS DITH CHx registers bits. 图 45 and 图 46 show the effect of using

dither algorithms.

0

-10

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-100

-110

-120

0

2.5

5 7.5

Frequency (MHz)

10

12.5

0

2.5

5 7.5

Frequency (MHz)

10

12.5

D801

D802

SFDR = 95 dBc, SNR = 71 dBFS, SINAD = 71 dBFS,

THD = 94 dBc, HD2 = 106 dBc, HD3 = 95 dBc

SFDR = 90 dBc, SNR = 71.2 dBFS, SINAD = 71.1 dBFS,

THD = 89 dBc, HD2 = 90 dBc, HD3 = 106 dBc

图 45. FFT for 10-MHz Input Signal

图 46. FFT for 10-MHz Input Signal

(Chopper On, Dither On)

(Chopper On, Dither Off)

8.4.5 Summary of Performance Mode Registers

表 3 lists the location, value, and functions of performance mode registers in the device.

表 3. Performance Modes

MODE

REGISTER SETTINGS

DESCRIPTION

Special modes

Registers 139 (bit 3), 239 (bit 3), 439 (bit 3), and 539 (bit 3)

Always write 1 for best performance

Registers 1 (bits 7:0), 134 (bits 5 and 3), 234 (bits 5 and 3),

434 (bits 5 and 3), and 534 (bits 5 and 3)

Disable dither

Disable dither to improve SNR

Disable chopper Registers 122 (bit 1), 222 (bit 1), 422 (bit 1), and 522 (bit 1)

Disable chopper (shifts 1/f noise floor at dc)

Registers 11Dh (bit 1), 21Dh (bit 1), 31Dh (bit 7 and bit 1), 41Dh

High IF modes

(bit 1), 51Dh (bit 1), 308h (bits 7-6), 608h (bits 7-6) and 61Dh

(bit 7 and bit 1)

Improves HD3 by a couple of dB for IF > 100 MHz

8.4.6 Device Diagnostic Modes

The device offers various diagnostic modes to check proper device operation at system level. These modes can

be enabled using the SPI. Outputs of these modes are stored in diagnostic read-only registers.

8.4.6.1 Internal Reference and Clock Status Check

Device is equipped with a mode to verify presence of a valid input clock, as well as status of on-chip ADC

reference. When a valid clock input clock is absent at input clock pins (CLKP,CLKM) of ADC, device sets register

bit CLK STATUS to ‘1’. Similarly, if internal reference block is malfunctioning for a channel, device sets register

bits REF STATUS CHx to ‘1’. To read the status of internal reference from these pins:

1. First enable reference status check by setting register bit EN REF STATUS CHECK to ‘1’.

2. Read back register bits REF STATUS CHx on SDATA pin for desired channel (x = A, B, C or D).

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8.4.6.2 DC Input check

In this mode, an internally generated DC voltage can be forced by device to its analog inputs. Before forcing

internal DC voltage, analog inputs must float. To enable forcing internal DC voltage, register bit EN DC FORCE

must be set HIGH. Forced voltage is programmable by register bits DC FORCE[2:0], applied to all four channels

together. In terms of output code, typical value of programmed DC voltage is given by equation mentioned below:

Output code= 368 × DC FORCE[2:0] + 745.

Output code is available on LVDS data outputs.

8.4.6.3 Mean and Variance Measurement

Mean and variance values of the ADC output can be analyzed using the on-chip statistical module available for

individual channel for a programmable length of samples. These values are stored in register bits MEAN[11:0]

and VAR[11:0] in 2s complement format. Equation for computing mean and variance values respectively are

given below:

0

5(J)

/A=J = T = Í

0

•

J=1

0

: ;

|5 J F T|

8=NE=J?A = Í

0

J=1

Where S(n) is n^thsample, N is total number of samples used for computation, programmed by register bits

SAMPLES FOR STATS[1:0].

Follow steps mentioned below to read the mean and variance:

1. Enable Statistical Module by setting bit EN STATS to ‘1’.

2. Select desired channel through bits STATS CH SEL[1:0].

3. Program number of samples, N, using register bits SAMPLES FOR STATS[1:0].

4. Wait for at least 4N samples for module to compute and update the results.

5. Disable Statistical Module by resetting EN STATS bit to ‘0’.

6. Read back mean and variance values from register bits MEAN[11:0] and VAR[11:0]. These values are in 2s

complement format.

8.4.6.4 Temperature Sensor

The device is equipped with a temperature sensor to measure internal junction temperature.

The temperature sensor output is a 9-bit digital data available in 2s complement format directly representing

temperature in degree Celsius units. Temperature data is internally updated every 1024×T_CLK× 16 seconds

where T_CLKperiod of sampling clock in seconds. Follow the steps mentioned below to read temperature sensor’s

output:

1. Enable temperature sensor by setting bits EN TEMP SENSE and EN TEMP SENSE CONV to ‘1’.

2. Wait for at least 1024 × T_CLK× 16 seconds for temperature sensor to update the data.

3. Disable temperature sensor by resetting the bit EN TEMP SENSE to ‘0’.

4. Load temperature sensor's data to register bits TEMPDATA[8:0] by setting register bit EN TEMP DATA

READOUT to '1'.

5. Readout 9-bit temperature data from register bits TEMPDATA[8:0] located in register addresses 10h and

11h.

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8.5 Programming

The ADC3421-Q1 can be configured using a serial programming interface, as described in this section.

8.5.1 Serial Interface

The device has a set of internal registers that can be accessed by the serial interface formed by the SEN (serial

interface enable), SCLK (serial interface clock), SDATA (serial interface data), and SDOUT (serial interface data

output) pins. Serially shifting bits into the device is enabled when SEN is low. Serial data SDATA are latched at

every SCLK rising edge when SEN is active (low). The serial data are loaded into the register at every 24th

SCLK rising edge when SEN is low. When the word length exceeds a multiple of 24 bits, the excess bits are

ignored. Data can be loaded in multiples of 24-bit words within a single active SEN pulse. The interface can

function with SCLK frequencies from 20 MHz down to very low speeds (of a few hertz) and also with a non-50%

SCLK duty cycle.

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Programming (接下页)

8.5.1.1 Register Initialization

After power-up, the internal registers must be initialized to their default values through a hardware reset by

applying a high pulse on the RESET pin (of durations greater than 10 ns), as shown in 图 47. Notice that when

hardware reset is applied for "first time after powering up the device", the SEN pin must be in low logic state.

However, this requirement is applicable only for first hardware reset after power-up. Any subsequent hardware

reset does not require SEN to be in low logic state and works independent to it. If required, the serial interface

registers can be cleared during operation either:

1. Through a hardware reset, or

2. By applying a software reset. When using the serial interface, set the RESET bit (D0 in register address 06h)

high. This setting initializes the internal registers to the default values and then self-resets the RESET bit low.

In this case, the RESET pin is kept low.

8.5.1.1.1 Serial Register Write

The device internal register can be programmed with these steps:

1. Drive the SEN pin low,

2. Set the R/W bit to 0 (bit A15 of the 16-bit address),

3. Set bit A14 in the address field to 1,

4. Initiate a serial interface cycle by specifying the address of the register (A13 to A0) whose content must be

written, and

5. Write the 8-bit data that are latched in on the SCLK rising edge.

图 47 and 表 4 show the timing requirements for the serial register write operation.

AVDD, DVDD

Register Address [13:0]

Register Data [7:0]

SDATA

R/W

= 0

1

A13 A12 A11

A1

A0

D7

D6

D5

D4

D3

D2

D1

t_DH

D0

t_SCLK

t_DSU

SCLK

SEN

t_SLOADH

t_SLOADS

RESET

First Hardware Reset after power-up needs SEN to be in low logic state

图 47. Serial Register Write Timing Diagram

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Programming (接下页)

表 4. Serial Interface Timing⁽¹⁾

MIN

TYP

MAX

UNIT

MHz

ns

f_SCLK

t_SLOADS

t_SLOADH

t_DSU

SCLK frequency (equal to 1 / t_SCLK

)

> dc

25

20

SEN to SCLK setup time

SCLK to SEN hold time

SDIO setup time

25

ns

25

ns

t_DH

SDIO hold time

25

ns

(1) Typical values are at 25°C, full temperature range is from T_MIN= –40°C to T_MAX= 125°C, and AVDD = DVDD = 1.8 V, unless otherwise

noted.

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8.5.1.1.2 Serial Register Readout

The device includes a mode where the contents of the internal registers can be read back using the SDOUT pin.

This readback mode may be useful as a diagnostic check to verify the serial interface communication between

the external controller and the ADC. The procedure to read the contents of the serial registers is as follows:

1. Drive the SEN pin low.

2. Set the R/W bit (A15) to 1. This setting disables any further writes to the registers.

3. Set bit A14 in the address field to 1.

4. Initiate a serial interface cycle specifying the address of the register (A13 to A0) whose content must be read.

5. The device outputs the contents (D7 to D0) of the selected register on the SDOUT pin.

6. The external controller can latch the contents at the SCLK rising edge.

7. To enable register writes, reset the R/W register bit to 0.

When READOUT is disabled, the SDOUT pin is in a high-impedance mode. If serial readout is not used, the

SDOUT pin must float. 图 48 shows a timing diagram of the serial register read operation. Data appear on the

SDOUT pin at the SCLK falling edge with an approximate delay (t_{SD_DELAY}) of 20 ns, as shown in 图 49.

Register Address [13:0]

Register Data: Don‘t Care

D5 D4 D3 D2

SDATA

R/W

= 1

A13 A12 A11

A1

A0

D7

D6

D1

D0

1

Register Read Data [7:0]

SDOUT

SCLK

D5

D4

D3

D2

SEN

图 48. Serial Register Read Timing Diagram

SCLK

t_{SD_DELAY}

SDOUT

图 49. SDOUT Timing Diagram

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8.5.2 Register Initialization

After power-up, the internal registers must be initialized to their default values through a hardware reset by

applying a high pulse on the RESET pin, as shown in 图 50 and 表 5.

Power

Supplies

t₁

RESET

t₂

t₃

Start of

SPI cyles

SEN

SEN has to be

LOW when first

Hardware Reset

is being applied.

图 50. Initialization of Serial Registers after Power-Up

表 5. Power-Up Timing

MIN

TYP

MAX

UNIT

ms

ns

t₁

t₂

t₃

Power-on delay from power-up to active high RESET pulse

Reset pulse duration: active high RESET pulse duration

Register write delay from RESET disable to SEN active

1

10

100

ns

If required, the serial interface registers can be cleared during operation either:

1. Through hardware reset, or

2. By applying a software reset. When using the serial interface, set the RESET bit (D0 in register address 06h)

high. This setting initializes the internal registers to the default values and then self-resets the RESET bit low.

In this case, the RESET pin is kept low.

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8.6 Register Maps

表 6. Register Map Summary

REGISTER

REGISTER DATA

ADDRESS,

A[13:0] (Hex)

7

6

5

4

3

2

1

0

Register 01h

Register 02h

Register 03h

Register 04h

Register 05h

DIS DITH CHA

DIS DITH CHB

DIS DITH CHC

DIS DITH CHD

STATS CH SEL[1:0]

0

ODD EVEN

FLIP WIRE

1W-2W

TEST

PATTERN EN

Register 06h

Register 07h

Register 09h

0

RESET

0

OVR ON LSB

ALIGN TEST

PATTERN

DATA

FORMAT

Register 0Ah

Register 0Bh

Register 0Eh

Register 0Fh

CHA TEST PATTERN

CHB TEST PATTERN

CHD TEST PATTERN

CHC TEST PATTERN 0

CUSTOM PATTERN[11:4]

0

CUSTOM PATTERN[3:0]

0

REF STATUS

CHB OR

TEMPDATA [2] TEMPDATA [1] TEMPDATA [0]

REF STATUS

CHD OR

REF STATUS

CHA OR

REF STATUS

CHC OR

TEMPDATA [3]

Register 10h

Register 11h

Register 13h

CLK STATUS

TEMPDATA[6:4]

0

TEMPDATA [8:7]

0

EN REF

STATUS

CHECK

EN DC FORCE

EN STATS

LOW SPEED ENABLE

EN TEMP

DATA

READOUT

EN TEMP

SENS CONV

EN TEMP

SENSE

Register 14h

Register 15h

0

CONFIG PDN

CHA PDN

CHB PDN

CHC PDN

CHD PDN

STANDBY

GLOBAL PDN

0

Register 16h

Register 17h

Register 18h

Register 19h

Register 25h

Register 27h

Register 4Bh

MEAN[5:0]

0

MEAN[11:6]

VAR[5:0]

0

VAR[11:6]

LVDS SWING

CLK DIV

0

SAMPLES FOR STATS[1:0]

HIGH IF

0

Register 11Dh

Register 122h

0

MODE0

DIS CHOP

CHA

0

Register 134h

Register 139h

0

DIS DITH CHA

0

DIS DITH CHA

SP1 CHA

0

HIGH IF

MODE1

Register 21Dh

Register 222h

0

DIS CHOP

CHD

Register 234h

Register 239h

Register 308h

0

DIS DITH CHD

0

DIS DITH CHD

0

SP1 CHD

0

HIGH IF MODE <5:4>

HIGH IF

MODE4

HIGH IF

MODE4

Register 31Dh

Register 41Dh

0

HIGH IF

MODE2

0

DIS CHOP

CHB

Register 422h

Register 434h

0

DIS DITH CHB

0

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Register Maps (接下页)

表 6. Register Map Summary (接下页)

REGISTER

REGISTER DATA

ADDRESS,

A[13:0] (Hex)

7

6

0

5

0

4

0

3

SP1 CHB

0

2

0

1

0

Register 439h

Register 51Dh

0

HIGH IF

MODE3

DIS CHOP

CHC

Register 522h

0

Register 534h

Register 539h

Register 608h

0

DIS DITH CHC

0

DIS DITH CHC

0

SP1 CHC

0

HIGH IF MODE <7:6>

HIGH IF

MODE5

HIGH IF

MODE5

Register 61Dh

0

Register 70Ah

Register 71Ah

0

PDN SYSREF

0

DC FORCE[2:0]

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8.6.1 Serial Register Description

8.6.1.1 Register 01h (address = 01h)

图 51. Register 01h

7

6

5

4

3

2

1

0

DIS DITH CHA

R/W-0h

DIS DITH CHB

R/W-0h

DIS DITH CHC

R/W-0h

DIS DITH CHD

R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

表 7. Register 01h Field Descriptions

Bit

Field

Type

Reset

Description

7-6

DIS DITH CHA

R/W

0h

These bits enable or disable the on-chip dither. Control this bit

along with bits 5 and 3 of register 134h.

00 = Default

11 = Dither is disabled for channel A. In this mode, SNR typically

improves by 0.2 dB at 70 MHz.

5-4

3-2

1-0

DIS DITH CHB

DIS DITH CHC

DIS DITH CHD

R/W

0h

These bits enable or disable the on-chip dither. Control this bit

along with bits 5 and 3 of register 434h.

00 = Default

11 = Dither is disabled for channel B. In this mode, SNR typically

improves by 0.2 dB at 70 MHz.

These bits enable or disable the on-chip dither. Control this bit

along with bits 5 and 3 of register 534h.

00 = Default

11 = Dither is disabled for channel B. In this mode, SNR typically

improves by 0.2 dB at 70 MHz.

These bits enable or disable the on-chip dither. Control this bit

along with bits 5 and 3 of register 234h.

00 = Default

11 = Dither is disabled for channel B. In this mode, SNR typically

improves by 0.2 dB at 70 MHz.

8.6.1.2 Register 02h (address = 02h)

图 52. Register 02h

7

6

5

0

4

0

3

0

2

0

1

0

STATS CH SEL[1:0]

R/W-0h

W-0h

R/W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

表 8. Register 02h Field Descriptions

Bit

Field

Type

Reset

Description

7-6

STATS CH SEL[1:0]

R/W

0h

These bits select desired channel for statistical data computation

00 = Channel A,

01 = Channel B,

10 = Channel C,

11 = Channel D

5-0

0

W

0h

Must write 0.

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8.6.1.3 Register 03h (address = 03h)

图 53. Register 03h

7

0

6

0

5

0

4

0

3

0

2

0

1

0

ODD EVEN

R/W-0h

W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

表 9. Register 03h Field Descriptions

Bit

7-6

0

Field

Type

W

Reset

0h

Description

0

Must write 0.

ODD EVEN

R/W

0h

This bit selects the bit sequence on the output wires (in 2-wire

mode only).

0 = Bits 0, 1, 2, and so forth appear on wire-0; bits 7, 8, 9, and

so forth appear on wire-1.

1 = Bits 0, 2, 4, and so forth appear on wire-0; bits 1, 3, 5, and

so forth appear on wire-1.

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8.6.1.4 Register 04h (address = 04h)

图 54. Register 04h

7

0

6

0

5

0

4

0

3

0

2

0

1

0

FLIP WIRE

R/W-0h

W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

表 10. Register 04h Field Descriptions

Bit

7-1

0

Field

Type

W

Reset

0h

Description

0

Must write 0.

FLIP WIRE

R/W

0h

This bit flips the data on the output wires. Valid only in two wire

configuration.

0 = Default

1 = Data on output wires is flipped. Pin D0x becomes D1x, and

vice versa.

8.6.1.5 Register 05h (address = 05h)

图 55. Register 05h

7

0

6

0

5

0

4

0

3

0

2

0

1

0

1W-2W

R/W-0h

W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

表 11. Register 05h Field Descriptions

Bit

7-1

0

Field

0

Type

W

Reset

0h

Description

Must write 0.

1W-2W

R/W

0h

This bit transmits output data on either one or two wires.

0 = Output data are transmitted on two wires (Dx0P, Dx0M and

Dx1P, Dx1M)

1 = Output data are transmitted on one wire (Dx0P, Dx0M).

8.6.1.6 Register 06h (address = 06h)

图 56. Register 06h

7

0

6

0

5

0

4

0

3

0

2

0

1

0

TEST PATTERN EN

R/W-0h

RESET

R/W-0h

W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

表 12. Register 06h Field Descriptions

Bit

7-2

1

Field

Type

W

Reset

0h

Description

0

Must write 0.

TEST PATTERN EN

R/W

0h

This bit enables test pattern selection for the digital outputs.

0 = Normal output

1 = Test pattern output enabled

0

RESET

R/W

0h

This bit applies a software reset.

This bit resets all internal registers to the default values and self-

clears to 0.

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8.6.1.7 Register 07h (address = 07h)

图 57. Register 07h

7

0

6

0

5

0

4

0

3

0

2

0

1

0

OVR ON LSB

R/W-0h

W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

表 13. Register 07h Field Descriptions

Bit

7-1

0

Field

Type

W

Reset

0h

Description

0

Must write 0.

OVR ON LSB

R/W

0h

This bit provides OVR information on the LSB bits.

0 = Output data bit 0 functions as the LSB of the 12-bit data

1 = Output data bit 0 carries the overrange (OVR) information

8.6.1.8 Register 09h (address = 09h)

图 58. Register 09h

7

0

6

0

5

0

4

0

3

0

2

0

1

0

ALIGN TEST PATTERN

R/W-0h

DATA FORMAT

R/W-0h

W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

表 14. Register 09h Field Descriptions

Bit

7-2

1

Field

Type

W

Reset

0h

Description

0

Must write 0.

ALIGN TEST PATTERN

R/W

0h

This bit aligns the test patterns across the outputs of both

channels.

0 = Test patterns of both channels are free running

1 = Test patterns of both channels are aligned

0

DATA FORMAT

R/W

0h

This bit selects th digital output data format.

0 = Twos complement

1 = Offset binary

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8.6.1.9 Register 0Ah (address = 0Ah)

图 59. Register 0Ah

7

6

5

4

3

2

1

0

CHA TEST PATTERN

R/W-0h

CHB TEST PATTERN

R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

表 15. Register 0Ah Field Descriptions

Bit

Field

Type

Reset

Description

7-4

CHA TEST PATTERN

R/W

0h

These bits control the test pattern for channel A after the TEST

PATTERN EN bit is set.

0000 = Normal operation

0001 = All 0's

0010 = All 1's

0011 = Toggle pattern: data alternate between 101010101010

and 010101010101

0100 = Digital ramp: data increment by 1 LSB every clock cycle

from code 0 to 4095

0101 = Custom pattern: output data are the same as

programmed by the CUSTOM PATTERN register bits

0110 = Deskew pattern: data are AAAh

1000 = PRBS pattern: data are a sequence of pseudo random

numbers

1001 = 8-point sine-wave: data are a repetitive sequence of the

following eight numbers that form a sine-wave: 0, 599, 2048,

3496, 4095, 3496, 2048, and 599

Others = Do not use

3-0

CHB TEST PATTERN

R/W

0h

These bits control the test pattern for channel B after the TEST

PATTERN EN bit is set.

0000 = Normal operation

0001 = All 0's

0010 = All 1's

0011 = Toggle pattern: data alternate between 101010101010

and 010101010101

0100 = Digital ramp: data increment by 1 LSB every clock cycle

from code 0 to 4095

0101 = Custom pattern: output data are the same as

programmed by the CUSTOM PATTERN register bits

0110 = Deskew pattern: data are AAAh

1000 = PRBS pattern: data are a sequence of pseudo random

numbers

1001 = 8-point sine-wave: data are a repetitive sequence of the

following eight numbers that form a sine-wave: 0, 599, 2048,

3496, 4095, 3496, 2048, and 599

Others = Do not use

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8.6.1.10 Register 0Bh (address = 0Bh)

图 60. Register 0Bh

7

6

5

4

3

2

1

0

CHC TEST PATTERN

R/W-0h

CHD TEST PATTERN

R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

表 16. Register 0Bh Field Descriptions

Bit

Field

Type

Reset

Description

7-4

CHC TEST PATTERN

R/W

0h

These bits control the test pattern for channel C after the TEST

PATTERN EN bit is set.

0000 = Normal operation

0001 = All 0's

0010 = All 1's

0011 = Toggle pattern: data alternate between 101010101010

and 010101010101.

0100 = Digital ramp: data increment by 1 LSB every clock cycle

from code 0 to 4095.

0110 = Custom pattern: output data are the same as

programmed by the CUSTOM PATTERN register bits.

1000 = Deskew pattern: data are AAAh.

1010 = PRBS pattern: data are a sequence of pseudo random

numbers.

1011 = 8-point sine wave: data are a repetitive sequence of the

following eight numbers that form a sine-wave: 0, 599, 2048,

3496, 4095, 3496, 2048, 599.

Others = Do not use

3-0

CHD TEST PATTERN

R/W

0h

These bits control the test pattern for channel D after the TEST

PATTERN EN bit is set.

0000 = Normal operation

0001 = All 0's

0010 = All 1's

0011 = Toggle pattern: data alternate between 101010101010

and 010101010101.

0100 = Digital ramp: data increment by 1 LSB every clock cycle

from code 0 to 4095.

0110 = Custom pattern: output data are the same as

programmed by the CUSTOM PATTERN register bits.

1000 = Deskew pattern: data are AAAh.

1010 = PRBS pattern: data are a sequence of pseudo random

numbers.

1011 = 8-point sine wave: data are a repetitive sequence of the

following eight numbers that form a sine-wave: 0, 599, 2048,

3496, 4095, 3496, 2048, 599.

Others = Do not use

8.6.1.11 Register 0Eh (address = 0Eh)

图 61. Register 0Eh

7

6

5

4

3

2

1

0

CUSTOM PATTERN[11:4]

R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

表 17. Register 0Eh Field Descriptions

Bit

Field

Type

Reset

Description

7-0

CUSTOM PATTERN[11:4]

R/W

0h

These bits set the 12-bit custom pattern (bits 11-4) for all

channels.

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8.6.1.12 Register 0Fh (address = 0Fh)

图 62. Register 0Fh

7

6

5

4

3

0

2

0

1

0

CUSTOM PATTERN[3:0]

R/W-0h

0

W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

表 18. Register 0Fh Field Descriptions

Bit

Field

Type

Reset

Description

7-4

CUSTOM PATTERN[3:0]

R/W

0h

These bits set the 12-bit custom pattern (bits 3-0) for all

channels.

3-0

0

W

0h

Must write 0.

8.6.1.13 Register 10h (address = 10h)

图 63. Register 10h

7

6

5

4

3

2

1

0

REF STATUS

CHB OR

REF STATUS

CHD OR

REF STATUS

CHA OR

CLK STATUS

TEMPDATA [6:4]

REF STATUS

CHC OR

TEMPDATA [2] TEMPDATA [1] TEMPDATA [0]

TEMPDATA [3]

Read Only Read Only Read Only

Read Only

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

表 19. Register 10h Field Descriptions

Bit

Field

Type

Reset

Description

7-5, 0

REF STATUS CHB, REF STATUS

CHD, REF STATUS CHA, REF

STATUS CHC

Read

Only

0h

When internal reference diagnostic is enabled by setting EN

REF STATUS CHECK bit to ‘1’, these bits carry status of

internal reference for corresponding channel.

See Internal Reference and Clock Status Check for details.

Note that these bits are multiplexed with temperature sensor’s

data and carry TEMPDATA[3:0] if temperature sensor’s is

enabled.

4

CLK STATUS

Read

Only

0h

This bit indicates presence of input clock. By default, device sets

this bit 0. If input clock is absent, this bit becomes '1'

7-5, 3-1, 0 TEMPDATA [6:0]

Read

Only

When temperature sensor’s data is being read, these bits carry

seven MSBs of temperature sensor’s 9-bit data. Remaining two

LSBs are available on address 11h bit 5:4.

See Temperature Sensor for details of operation.

8.6.1.14 Register 11h (address = 11h)

图 64. Register 11h

7

0

6

0

5

4

3

0

2

0

1

0

TEMPDATA [8:7]

Read Only

W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

表 20. Register 11h Field Descriptions

Bit

7-6

5-4

Field

Type

Reset

0h

Description

0

W

Must write 0.

TEMPDATA [8:7]

Read

Only

0h

These bits represent digital equivalent of temperature in 2s

complement format.

3-0

0

W

0h

Must write 0.

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ZHCSKL4 –DECEMBER 2019

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8.6.1.15 Register 13h (address = 13h)

图 65. Register 13h

7

0

6

5

4

3

0

2

0

1

0

EN REF

STATUS

CHECK

LOW SPEED ENABLE

EN DC FORCE

R/W-0h

EN STATS

R/W-0h

W-0h

R/W-0h

W-0h

R/W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

表 21. Register 13h Field Descriptions

Bit

7

Field

Type

W

Reset

0h

Description

0

Must write 0.

6

EN REF STATUS CHECK

R/W

0h

This Bit Enables reference diagnostic check. Must be set to '1'

before reading reference status from REF STATUS CHECK CHx

bits.

5

4

EN DC FORCE

EN STATS

R/W

0h

This Bit Enables internal DC voltage force diagnostic check

together for all channels. Must be set to '1' before forcing

internal DC voltage through DC FORCE[2:0] bits.

This bit enables inter Statistics Module for mean and variance

computation. After this bit is set to '1', statistical module for

desired channel can be selected by using bits STATS CH

SEL[1:0]

3-2

1-0

0

W

0h

Must write 0.

LOW SPEED ENABLE

R/W

Enables low speed operation in 1-wire and 2-wire mode.

Depending upon sampling frequency, write this bit as per 表 22

表 22. LOW SPEED ENABLE Register Settings across f_S

f_S, MSPS

REGISTER BIT LOW SPEED ENABLE

1- Wire Mode 2-Wire Mode

10 11

10 Not supported

MIN

20

MAX

25

15

20

8.6.1.16 Register 14h (address = 14h)

图 66. Register 14h

7

0

6

5

4

0

3

0

2

1

0

EN TEMP

SENS CONV

EN TEMP

SENSE

EN TEMP

DATA

READOUT

W-0h

R/W-0h

W-0h

R/W-0h

W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

表 23. Register 14h Field Descriptions

Bit

7

Field

Type

W

Reset

0h

Description

0

Must write 0.

6

EN TEMP SENS CONV

R/W

0h

This bit enables the temperature-to-digital conversion process of

temperature sensor. This bit can be set to '1' after temperature

sensor is enabled by setting EN TEMP SENSE bit to '1'.

5

4-3

2

EN TEMP SENSE

R/W

W

0h

This bit enables temperature sensor present inside device

Must write 0.

0

EN TEMP DATA READOUT

R/W

This bit places the 9-bit digital equivalent of temperature on

register bits TEMPDATA[8:0].

1-0

0

W

0h

Must write 0.

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ZHCSKL4 –DECEMBER 2019

8.6.1.17 Register 15h (address = 15h)

图 67. Register 15h

7

6

5

4

3

2

1

0

CONFIG PDN

CHA PDN

W-0h

CHB PDN

R/W-0h

CHC PDN

R/W-0h

CHD PDN

W-0h

STANDBY

R/W-0h

GLOBAL PDN

R/W-0h

0

W-0h

R/W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

表 24. Register 15h Field Descriptions

Bit

Field

Type

Reset

Description

7

CHA PDN

W

0h

0 = Normal operation

1 = Power-down channel A

6

5

4

3

CHB PDN

CHC PDN

CHD PDN

STANDBY

R/W

W

0h

0 = Normal operation

1 = Power-down channel B

0 = Normal operation

1 = Power-down channel C

0 = Normal operation

1 = Power-down channel D

R/W

The ADCs of both channels enter standby.

0 = Normal operation

1 = Standby

2

GLOBAL PDN

R/W

0h

0 = Normal operation

1 = Global power-down

1

0

W

0h

Must write 0.

CONFIG PDN PIN

R/W

This bit configures the PDN pin as either a global power-down or

standby pin.

0 = Logic high voltage on the PDN pin sends the device into

global power-down

1 = Logic high voltage on the PDN pin sends the device into

standby

8.6.1.18 Register 16h (address = 16h)

图 68. Register 16h

7

6

5

4

3

2

1

0

MEAN[5:0]

Read Only

W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

表 25. Register 16h Field Descriptions

Bit

Field

Type

Reset

Description

7-2

MEAN[5:0]

Read

Only

0h

These bits represent mean value in 2s complement format

computed over programmed number of samples by statistical

module.

1-0

0

W

0h

Must write 0.

8.6.1.19 Register 17h (address = 17h)

图 69. Register 17h

7

0

6

0

5

4

3

2

1

0

MEAN[11:6]

Read Only

W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

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表 26. Register 17h Field Descriptions

Bit

7-6

5-0

Field

Type

Reset

0h

Description

0

W

Must write 0.

MEAN[11:6]

Read

Only

0h

These bits represent mean value in 2s complement format

computed over programmed number of samples by statistical

module.

8.6.1.20 Register 18h (address = 18h)

图 70. Register 18h

7

6

5

4

3

2

1

0

VAR[5:0]

Read Only

W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

表 27. Register 18h Field Descriptions

Bit

Field

Type

Reset

Description

7-2

VAR[5:0]

Read

Only

0h

These bits represent variance value in 2s complement format

computed over programmed number of samples by statistical

module

1-0

0

W

0h

Must write 0.

8.6.1.21 Register 19h (address = 19h)

图 71. Register 19h

7

0

6

0

5

4

3

2

1

0

VAR[11:6]

Read Only

W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

表 28. Register 19h Field Descriptions

Bit

7-6

5-0

Field

Type

Reset

0h

Description

0

W

Must write 0.

VAR[11:6]

Read

Only

0h

These bits represent variance value in 2s complement format

computed over programmed number of samples by statistical

module

8.6.1.22 Register 25h (address = 25h)

图 72. Register 25h

7

6

5

4

3

2

1

0

LVDS SWING

R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

表 29. Register 25h Field Descriptions

Bit

Field

Type

Reset

Description

7-0

LVDS SWING

R/W

0h

These bits control the swing of the LVDS outputs (including the

data output, bit clock, and frame clock).

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8.6.1.23 Register 27h (address = 27h)

图 73. Register 27h

7

6

5

0

4

0

3

0

2

0

1

0

CLK DIV

R/W-0h

0

W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

表 30. Register 27h Field Descriptions

Bit

Field

Type

Reset

Description

7-6

CLK DIV

R/W

0h

These bits select the internal clock divider for the input sampling

clock.

00 = Divide-by-1

01 = Divide-by-1

10 = Divide-by-2

11 = Divide-by-4

5-0

0

W

0h

Must write 0.

8.6.1.24 Register 4Bh (address = 4Bh)

图 74. Register 4Bh

7

0

6

0

5

0

4

0

3

0

2

0

1

0

SAMPLES FOR STATS[1:0]

R/W-0h

W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

表 31. Register 4Bh Field Descriptions

Bit

7-2

1-0

Field

Type

W

Reset

0h

Description

0

Must write 0.

SAMPLES FOR STATS[1:0]

R/W

0h

These bits program number of samples to be used by statistical

module for computation of mean and variance.

00=256,

01=1024,

10=4096,

11=16384

8.6.1.25 Register 11Dh (address = 11Dh)

图 75. Register 11Dh

7

0

6

0

5

0

4

0

3

0

2

0

1

0

HIGH IF MODE0

R/W-0h

W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

表 32. Register 11Dh Field Descriptions

Bit

7-2

1

Field

Type

Reset

Description

0

W

0h

Must write 0.

HIGH IF MODE0

Set all register bits belonging to HIGH IF MODE as logic HIGH

to improve HD3 by a couple of dB for IF > 100 MHz.

0

W

0h

Must write 0.

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8.6.1.26 Register 122h (address = 122h)

图 76. Register 122h

7

0

6

0

5

0

4

0

3

0

2

0

1

0

DIS CHOP CHA

R/W-0h

W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

表 33. Register 122h Field Descriptions

Bit

7-2

1

Field

Type

W

Reset

0h

Description

0

Must write 0.

DIS CHOP CHA

R/W

0h

This bit disables the chopper.

Set this bit to shift the 1/f noise floor at dc.

0 = 1/f noise floor is centered at f_S/ 2 (default)

1 = Chopper mechanism is disabled; 1/f noise floor is centered

at dc

0

W

0h

Must write 0.

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8.6.1.27 Register 134h (address = 134h)

图 77. Register 134h

7

0

6

0

5

4

0

3

2

0

1

0

DIS DITH CHA

R/W-0h

DIS DITH CHA

R/W-0h

0

W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

表 34. Register 134h Field Descriptions

Bit

7-6

5

Field

Type

W

Reset

0h

Description

0

Must write 0.

DIS DITH CHA

R/W

0h

Set this bit along with bits 7 and 6 of register 01h.

00 = Default

11 = Dither is disabled for channel A. In this mode, SNR typically

improves by 0.2 dB at 70 MHz.

4

3

0

W

0h

Must write 0.

DIS DITH CHA

R/W

Set this bit along with bits 7 and 6 of register 01h.

00 = Default

11 = Dither is disabled for channel A. In this mode, SNR typically

improves by 0.2 dB at 70 MHz.

2-0

0

W

0h

Must write 0.

8.6.1.28 Register 139h (address = 139h)

图 78. Register 139h

7

0

6

0

5

0

4

0

3

2

0

1

0

SP1 CHA

R/W-0h

W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

表 35. Register 139h Field Descriptions

Bit

7-4

3

Field

0

Type

W

Reset

0h

Description

Must write 0.

SP1 CHA

R/W

0h

This bit sets the special mode for best performance on channel

A.

Always write 1 after reset.

2-0

0

W

0h

Must write 0.

8.6.1.29 Register 21Dh (address = 21Dh)

图 79. Register 21Dh

7

0

6

0

5

0

4

0

3

0

2

0

1

0

HIGH IF MODE1

R/W-0h

W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

表 36. Register 21Dh Field Descriptions

Bit

7-2

1

Field

Type

W

Reset

0h

Description

0

Must write 0.

HIGH IF MODE1

R/W

0h

Set all register bits belonging to HIGH IF MODE as logic HIGH

to improve HD3 by a couple of dB for IF > 100 MHz.

0

W

0h

Must write 0.

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8.6.1.30 Register 222h (address = 222h)

图 80. Register 222h

7

0

6

0

5

0

4

0

3

0

2

0

1

0

DIS CHOP CHD

R/W-0h

W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

表 37. Register 222h Field Descriptions

Bit

7-2

1

Field

Type

W

Reset

0h

Description

0

Must write 0.

DIS CHOP CHD

R/W

0h

This bit disables the chopper.

Set this bit to shift the 1/f noise floor at dc.

0 = 1/f noise floor is centered at f_S/ 2 (default)

1 = Chopper mechanism is disabled; 1/f noise floor is centered

at dc

0

W

0h

Must write 0.

8.6.1.31 Register 234h (address = 234h)

图 81. Register 234h

7

0

6

0

5

4

0

3

2

0

1

0

DIS DITH CHD

R/W-0h

DIS DITH CHD

R/W-0h

W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

表 38. Register 234h Field Descriptions

Bit

7-6

5

Field

Type

W

Reset

0h

Description

0

Must write 0.

DIS DITH CHD

R/W

0h

Set this bit with bits 1 and 0 of register 01h.

00 = Default

11 = Dither is disabled for channel D. In this mode, SNR

typically improves by 0.2 dB at 70 MHz.

4

3

0

W

0h

Must write 0.

DIS DITH CHD

R/W

Set this bit with bits 1 and 0 of register 01h.

00 = Default

11 = Dither is disabled for channel D. In this mode, SNR

typically improves by 0.2 dB at 70 MHz.

2-0

0

W

0h

Must write 0.

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8.6.1.32 Register 239h (address = 239h)

图 82. Register 239h

7

0

6

0

5

0

4

0

3

2

0

1

0

SP1 CHD

R/W-0h

0

W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

表 39. Register 239h Field Descriptions

Bit

7-4

3

Field

0

Type

W

Reset

0h

Description

Must write 0.

SP1 CHD

R/W

0h

This bit sets the special mode for best performance on channel

D.

Always write 1 after reset.

2-0

0

W

0h

Must write 0.

8.6.1.33 Register 308h (address = 308h)

图 83. Register 308h

7

6

5

0

4

0

3

0

2

0

1

0

HIGH IF MODE<5:4>

W-0h W-0h

W-0h

R/W-0h

W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

表 40. Register 308h Field Descriptions

Bit

Field

Type

Reset

Description

7-6

HIGH IF MODE<5:4>

R/W

0h

Set all register bits belonging to HIGH IF MODE as logic HIGH

to improve HD3 by a couple of dB for IF > 100 MHz.

5-0

0

W

0h

Must write 0.

8.6.1.34 Register 31Dh (address = 31Dh)

图 84. Register 31Dh

7

6

0

5

0

4

0

3

0

2

0

1

0

HIGH IF

MODE4

HIGH IF

MODE4

R/W-0h

W-0h

R/W-0h

W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

表 41. Register 31Dh Field Descriptions

Bit

Field

Type

Reset

Description

7

HIGH IF MODE4

R/W

0h

Set all register bits belonging to HIGH IF MODE as logic HIGH

to improve HD3 by a couple of dB for IF > 100 MHz.

6-2

1

0

W

0h

Must write 0.

HIGH IF MODE4

R/W

Set all register bits belonging to HIGH IF MODE as logic HIGH

to improve HD3 by a couple of dB for IF > 100 MHz.

0

W

0h

Must write 0.

8.6.1.35 Register 41Dh (address = 41Dh)

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图 85. Register 41Dh

7

0

6

0

5

0

4

0

3

0

2

0

1

0

HIGH IF MODE2

R/W-0h

W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

表 42. Register 41Dh Field Descriptions

Bit

7-2

1

Field

Type

W

Reset

0h

Description

0

Must write 0.

HIGH IF MODE2

R/W

0h

Set all register bits belonging to HIGH IF MODE as logic HIGH

to improve HD3 by a couple of dB for IF > 100 MHz.

0

W

0h

Must write 0.

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ZHCSKL4 –DECEMBER 2019

8.6.1.36 Register 422h (address = 422h)

图 86. Register 422h

7

0

6

0

5

0

4

0

3

0

2

0

1

0

DIS CHOP CHB

R/W-0h

0

W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

表 43. Register 422h Field Descriptions

Bit

7-2

1

Field

Type

W

Reset

0h

Description

0

Must write 0.

DIS CHOP CHB

R/W

0h

This bit disables the chopper.

Set this bit to shift the 1/f noise floor at dc.

0 = 1/f noise floor is centered at f_S/ 2 (default)

1 = Chopper mechanism is disabled; 1/f noise floor is centered

at dc

0

W

0h

Must write 0.

8.6.1.37 Register 434h (address = 434h)

图 87. Register 434h

7

0

6

0

5

4

0

3

2

0

1

0

DIS DITH CHB

R/W-0h

DIS DITH CHB

R/W-0h

W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

表 44. Register 434h Field Descriptions

Bit

7-6

5

Field

Type

W

Reset

0h

Description

0

Must write 0.

DIS DITH CHB

R/W

0h

Set this bit with bits 5 and 4 of register 01h.

00 = Default

11 = Dither is disabled for channel B. In this mode, SNR typically

improves by 0.2 dB at 70 MHz.

4

3

0

W

0h

Must write 0.

DIS DITH CHB

R/W

Set this bit with bits 5 and 4 of register 01h.

00 = Default

11 = Dither is disabled for channel B. In this mode, SNR typically

improves by 0.2 dB at 70 MHz.

2-0

0

W

0h

Must write 0.

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8.6.1.38 Register 439h (address = 439h)

图 88. Register 439h

7

0

6

0

5

0

4

0

3

2

0

1

0

SP1 CHB

R/W-0h

W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

表 45. Register 439h Field Descriptions

Bit

7-4

3

Field

0

Type

W

Reset

0h

Description

Must write 0.

SP1 CHB

R/W

0h

This bit sets the special mode for best performance on channel

B.

Always write 1 after reset.

2-0

0

W

0h

Must write 0.

8.6.1.39 Register 51Dh (address = 51Dh)

图 89. Register 51Dh

7

0

6

0

5

0

4

0

3

0

2

0

1

0

HIGH IF MODE3

R/W-0h

W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

表 46. Register 51Dh Field Descriptions

Bit

7-2

1

Field

Type

W

Reset

0h

Description

0

Must write 0.

HIGH IF MODE3

R/W

0h

Set all register bits belonging to HIGH IF MODE as logic HIGH

to improve HD3 by a couple of dB for IF > 100 MHz.

0

W

0h

Must write 0.

8.6.1.40 Register 522h (address = 522h)

图 90. Register 522h

7

0

6

0

5

0

4

0

3

0

2

0

1

0

DIS CHOP CHC

R/W-0h

W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

表 47. Register 522h Field Descriptions

Bit

7-2

1

Field

Type

W

Reset

0h

Description

0

Must write 0.

DIS CHOP CHC

R/W

0h

This bit disables the chopper.

Set this bit to shift the 1/f noise floor at dc.

0 = 1/f noise floor is centered at f_S/ 2 (default)

1 = Chopper mechanism is disabled; 1/f noise floor is centered

at dc

0

W

0h

Must write 0.

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8.6.1.41 Register 534h (address = 534h)

图 91. Register 534h

7

0

6

0

5

4

0

3

2

0

1

0

DIS DITH CHC

R/W-0h

DIS DITH CHC

R/W-0h

0

W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

表 48. Register 534h Field Descriptions

Bit

7-6

5

Field

Type

W

Reset

0h

Description

0

Must write 0.

DIS DITH CHC

R/W

0h

Set this bit with bits 3 and 2 of register 01h.

00 = Default

11 = Dither is disabled for channel C. In this mode, SNR

typically improves by 0.2 dB at 70 MHz.

4

3

0

W

0h

Must write 0.

DIS DITH CHC

R/W

Set this bit with bits 3 and 2 of register 01h.

00 = Default

11 = Dither is disabled for channel C. In this mode, SNR

typically improves by 0.2 dB at 70 MHz.

2-0

0

W

0h

Must write 0.

8.6.1.42 Register 539h (address = 539h)

图 92. Register 539h

7

0

6

0

5

0

4

0

3

2

0

1

0

SP1 CHC

R/W-0h

W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

表 49. Register 539h Field Descriptions

Bit

7-4

3

Field

0

Type

W

Reset

0h

Description

Must write 0.

SP1 CHC

R/W

0h

This bit sets the special mode for best performance on channel

C.

Always write 1 after reset.

2-0

0

W

0h

Must write 0.

8.6.1.43 Register 608h (address = 608h)

图 93. Register 608h

7

6

5

0

4

0

3

0

2

0

1

0

HIGH IF MODE<7:6>

W-0h W-0h

W-0h

R/W-0h

W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

表 50. Register 608h Field Descriptions

Bit

Field

Type

Reset

Description

7-6

HIGH IF MODE<7:6>

R/W

0h

Set all register bits belonging to HIGH IF MODE as logic HIGH

to improve HD3 by a couple of dB for IF > 100 MHz.

5-0

0

W

0h

Must write 0.

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ZHCSKL4 –DECEMBER 2019

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8.6.1.44 Register 61Dh (address = 61Dh)

图 94. Register 61Dh

7

6

0

5

0

4

0

3

0

2

0

1

0

HIGH IF

MODE5

HIGH IF

MODE5

PDN SYSREF

R/W-0h

W-0h

R/W-0h

W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

表 51. Register 61Dh Field Descriptions

Bit

Field

Type

Reset

Description

7

HIGH IF MODE5

R/W

0h

Set all register bits belonging to HIGH IF MODE as logic HIGH

to improve HD3 by a couple of dB for IF > 100 MHz.

6-2

1

0

W

0h

Must write 0.

HIGH IF MODE5

R/W

Set all register bits belonging to HIGH IF MODE as logic HIGH

to improve HD3 by a couple of dB for IF > 100 MHz.

0

W

0h

Must write 0.

8.6.1.45 Register 70Ah (address = 70Ah)

图 95. Register 70Ah

7

0

6

0

5

0

4

0

3

0

2

0

1

0

PDN SYSREF

R/W-0h

W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

表 52. Register 70Ah Field Descriptions

Bit

7-1

0

Field

Type

W

Reset

0h

Description

0

Must write 0.

PDN SYSREF

R/W

0h

If the SYSREF pins are not used in the system, the SYSREF

buffer must be powered down by setting this bit.

0 = Normal operation

1 = Powers down the SYSREF buffer

8.6.1.46 Register 71Ah (address = 71Ah)

图 96. Register 71Ah

7

0

6

0

5

0

4

0

3

2

1

0

DC FORCE[2:0]

R/W-0h

W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

表 53. Register 71Ah Field Descriptions

Bit

7-4

3-1

Field

Type

W

Reset

0h

Description

0

Must write 0.

DC FORCE[2:0]

R/W

0h

These Bits force internal DC voltage to ADC's analog inputs

together for all channels. Minimum DC voltage corresponds to

output code 745 and max DC voltage to output code 3332

typically following the equation:

Output Code = 368 × DC FORCE[2:0] + 745

0

W

0h

Must write 0.

52

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ZHCSKL4 –DECEMBER 2019

9 Applications and Implementation

注

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

9.1 Application Information

Typical applications involving transformer-coupled circuits are discussed in this section. Transformers (such as

ADT1-1WT or WBC1-1) can be used up to 250 MHz to achieve good phase and amplitude balances at ADC

inputs. When designing the dc driving circuits, the ADC input impedance must be considered. 图 97 and 图 98

show the impedance (Z_in= R_in|| C_in) across the ADC input pins.

10

6

5

4

3

2

1

0.1

0.01

0

100 200 300 400 500 600 700 800 900 1000

Frequency (MHz)

0

100 200 300 400 500 600 700 800 900 1000

Frequency (MHz)

D024

D00215

图 97. Differential Input Resistance, R_IN

图 98. Differential Input Capacitance, C_IN

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9.2 Typical Applications

9.2.1 Driving Circuit Design: Low Input Frequencies

0.1 µF

INP

50 ꢀ

0.1 µF

50 Ω

22 pF

50 Ω

25 Ω

TI Device

50 ꢀ

1:1

INM

0.1 µF

VCM

图 99. Driving Circuit for Low Input Frequencies

9.2.1.1 Design Requirements

For optimum performance, the analog inputs must be driven differentially. An optional 5-Ω to 15-Ω resistor in

series with each input pin can be kept to damp out ringing caused by package parasitic. The drive circuit may

have to be designed to minimize the impact of kick-back noise generated by sampling switches opening and

closing inside the ADC, as well as ensuring low insertion loss over the desired frequency range and matched

impedance to the source.

9.2.1.2 Detailed Design Procedure

A typical application involving using two back-to-back coupled transformers is illustrated in 图 99. The circuit is

optimized for low input frequencies. An external R-C-R filter using 50-Ω resistors and a 22-pF capacitor is used

with the series inductor (39 nH), this combination helps absorb the sampling glitches.

9.2.1.3 Application Curve

图 100 shows the performance obtained by using the circuit shown in 图 99.

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

0

2.5

5 7.5

Frequency (MHz)

10

12.5

D801

SFDR = 95 dBc, SNR = 71 dBFS, SINAD = 71 dBFS,

THD = 94 dBc, HD2 = 106 dBc, HD3 = 95 dBc

图 100. Performance FFT at 10 MHz (Low Input Frequency)

54

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Typical Applications (接下页)

9.2.2 Driving Circuit Design: Input Frequencies Between 100 MHz to 230 MHz

0.1 µF

10 ꢀ

0.1 µF

INP

15 Ω

25 Ω

0.1 pF

TI Device

10 pF

56 nH

25 Ω

15 Ω

1:1

INM

10 ꢀ

0.1 µF

VCM

图 101. Driving Circuit for Mid-Range Input Frequencies (100 MHz < f_IN< 230 MHz)

9.2.2.1 Design Requirements

See the Design Requirements section for further details.

9.2.2.2 Detailed Design Procedure

When input frequencies are between 100 MHz to 230 MHz, an R-LC-R circuit can be used to optimize

performance, as shown in 图 101.

9.2.2.3 Application Curve

图 102 shows the performance obtained by using the circuit shown in 图 101.

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

0

2.5

5 7.5

Frequency (MHz)

10

12.5

D805

SFDR = 87 dBc, SNR = 69.8 dBFS, SINAD = 69.7 dBFS,

THD = 85 dBc, HD2 = 90 dBc, HD3 = 87 dBc

图 102. Performance FFT at 170 MHz (Mid Input Frequency)

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ZHCSKL4 –DECEMBER 2019

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Typical Applications (接下页)

9.2.3 Driving Circuit Design: Input Frequencies Greater than 230 MHz

0.1 µF

10 Ω

INP

0.1 µF

25 ꢀ

TI Device

10 Ω

INM

1:1

0.1 µF

VCM

图 103. Driving Circuit for High Input Frequencies (f_IN> 230 MHz)

9.2.3.1 Design Requirements

See the Design Requirements section for further details.

9.2.3.2 Detailed Design Procedure

For high input frequencies (> 230 MHz), using the R-C-R or R-LC-R circuit does not show significant

improvement in performance. However, a series resistance of 10 Ω can be used as shown in 图 103.

9.2.3.3 Application Curve

图 104 shows the performance obtained by using the circuit shown in 图 103.

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

0

2.5

5 7.5

Frequency (MHz)

10

12.5

D809

SFDR = 67 dBc, SNR = 66.4 dBFS, SINAD = 66.4 dBFS,

THD = 93 dBc, HD2 = 67 dBc, HD3 = 88 dBc

图 104. Performance FFT at 450 MHz (High Input Frequency)

10 Power Supply Recommendations

The device requires a 1.8-V nominal supply for AVDD and DVDD. There are no specific sequence power-supply

requirements during device power-up. AVDD and DVDD can power up in any order.

56

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11 Layout

11.1 Layout Guidelines

The ADC3421-Q1 EVM layout can be used as a reference layout to obtain the best performance. A layout

diagram of the EVM top layer is provided in 图 105. Some important points to remember during laying out the

board are:

1. Analog inputs are located on opposite sides of the device pin out to ensure minimum crosstalk on the

package level. To minimize crosstalk onboard, the analog inputs must exit the pin out in opposite directions,

as shown in the reference layout of 图 105 as much as possible.

2. In the device pin out, the sampling clock is located on a side perpendicular to the analog inputs in order to

minimize coupling between them. This configuration is also maintained on the reference layout of 图 105 as

much as possible.

3. Keep digital outputs away from the analog inputs. When these digital outputs exit the pin out, the digital

output traces must not be kept parallel to the analog input traces because this configuration can result in

coupling from digital outputs to analog inputs and degrade performance. All digital output traces to the

receiver [such as a field-programmable gate array (FPGA) or an application-specific integrated circuit (ASIC)]

must be matched in length to avoid skew among outputs.

4. At each power-supply pin (AVDD and DVDD), keep a 0.1-µF decoupling capacitor close to the device. A

separate decoupling capacitor group consisting of a parallel combination of 10-µF, 1-µF, and 0.1-µF

capacitors can be kept close to the supply source.

11.2 Layout Example

Sampling

Clock

Routing

Analog

Input

Routing

ADC34xx

Digital

Output

Routing

图 105. Typical Layout of the ADC3421-Q1 Board

57

ADC3421-Q1

ZHCSKL4 –DECEMBER 2019

www.ti.com.cn

12 器件和文档支持

12.1 接收文档更新通知

要接收文档更新通知，请导航至 ti.com. 上的器件产品文件夹。单击右上角的通知我进行注册，即可每周接收产品

信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

12.2 支持资源

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight

from the experts. Search existing answers or ask your own question to get the quick design help you need.

Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do

not necessarily reflect TI's views; see TI's Terms of Use.

12.3 商标

E2E is a trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

12.4 静电放电警告

ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可

能会损坏集成电路。

ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可

能会导致器件与其发布的规格不相符。

12.5 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

13 机械、封装和可订购信息

以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且

不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。

58

PACKAGE MATERIALS INFORMATION

www.ti.com

4-Feb-2022

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

AD3421QRWERQ1

VQFNP

RWE

56

2000

330.0

16.4

8.3

2.25

12.0

16.0

Q2

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

4-Feb-2022

*All dimensions are nominal

Device

Package Type Package Drawing Pins

VQFNP RWE 56

SPQ

Length (mm) Width (mm) Height (mm)

350.0 350.0 43.0

AD3421QRWERQ1

2000

Pack Materials-Page 2

GENERIC PACKAGE VIEW

RWE 56

8 x 8, 0.5 mm pitch

VQFNP - 0.9 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

Images above are just a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

4224587/A

www.ti.com

重要声明和免责声明

TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，

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您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成

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TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	AD3421QRWETQ1
厂家：	TEXAS INSTRUMENTS
描述：	汽车类、四通道、12 位、25MSPS 模数转换器 (ADC) \| RWE \| 56 \| -40 to 125 转换器模数转换器
文件：	总64页 (文件大小：3115K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AD3421QRWETQ1 [TI]

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