AD7524AN_技术文档

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SGLS028A − SEPTEMBER 1989 − REVISED MARCH 1995

D

Advanced LinCMOS Silicon-Gate

J PACKAGE

(TOP VIEW)

Technology

Easily interfaced to Microprocessors

On-Chip Data Latches

R

OUT1

OUT2

GND

DB7

DB6

DB5

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

FB

Monotonicity Over Entire A/D Conversion

Range

REF

V

DD

WR

CS

DB0

DB1

DB2

Segmented High-Order Bits Ensure

Low-Glitch Output

Designed to Be interchangeable With

Analog Devices AD7524, PMI PM-7524, and

Micro Power Systems MP7524

DB4

DB3

D

Fast Control Signaling for Digital Signal

Processor Applications Including Interface

With SMJ320

FK PACKAGE

(TOP VIEW)

KEY PERFORMANCE SPECIFICATIONS

Resolution

8 Bits

Linearity error

1/2 LSB Max

5 mW Max

100 ns Max

80 ns Max

3

4

2

1

20 19

18

Power dissipation at V

Settling time

= 5 V

V

GND

DB7

NC

DD

WR

NC

17

16

15

14

5

6

7

8

Propagation delay

CS

DB6

DB5

DB0

9 10 11 12 13

description

The AD7524M is an Advanced LinCMOS 8-bit

digital-to-analog converter (DAC) designed for

easy interface to most popular microprocessors.

NC−No internal connection

The AD7524M is an 8-bit multiplying DAC with input latches and with a load cycle similar to the write cycle of

a random access memory. Segmenting the high-order bits minimizes glitches during changes in the

most-significant bits, which produce the highest glitch impulse. The AD7524M provides accuracy to 1/2 LSB

without the need for thin-film resistors or laser trimming, while dissipating less than 5 mW typically.

Featuring operation from a 5-V to 15-V single supply, the AD7524M interfaces easily to most microprocessor

buses or output ports. Excellent multiplying (2 or 4 quadrant) makes the AD7524M an ideal choice for many

microprocessor-controlled gain-setting and signal-control applications.

The AD7524M is characterized for operation from −55°C to 125°C.

AVAILABLE OPTIONS

PACKAGE

CERAMIC CHIP

T

A

CERAMIC DIP

(J)

CARRIER

(FK)

−55°C to 125°C

AD7524MFK

AD7524MJ

Advanced LinCMOS is a trademark of Texas Instruments Incorporated.

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Copyright  1995, Texas Instruments Incorporated

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1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

^{POST OFFICE BOX 1443}• HOUSTON, TEXAS 77251−1443

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SGLS028A − SEPTEMBER 1989 − REVISED MARCH 1995

functional block diagram

R

15

REF

2R

16

R

FB

S-1

S-2

S-3

S-8

R

1

2

OUT1

OUT2

12

13

CS

3

Data Latches

GND

WR

4

5

6

11

DB7

(MSB)

DB6

DB5

DB0

(LSB)

Data Inputs

operating sequence

t

(CS)

su

t (CS)

h

CS

10%

t

(WR)

w

WR

10%

t

(D)

su

t (D)

h

DB0−DB7

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

^{POST OFFICE BOX 1443}• HOUSTON, TEXAS 77251−1443

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SGLS028A − SEPTEMBER 1989 − REVISED MARCH 1995

†

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 17 V

DD

Voltage between R and GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 V

FB

Digital input voltage range, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to V +0.3 V

I

DD

Reference voltage range, V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 V

ref

Peak digital input current, I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 µA

I

Operating free-air temperature range, T

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55°C to 125°C

A

Storage temperature range, T

Case temperature for 60 seconds, T : FK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C

Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: J package . . . . . . . . . . . . . . . . . . . . . 300°C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C

stg

C

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

recommended operating conditions

V

= 5 V

V

= 15 V

DD

MIN NOM

DD

MIN NOM

UNIT

MAX

Supply voltage, V

DD

4.75

2.4

5

5.25

14.5

13.5

15

10

15.5

V

Reference voltage, V

ref

10

High-level input voltage, V

IH

V

Low-level input volage, V

IL

0.8

1.5

V

CS setup time, t

40

0

40

0

ns

°C

su(CS)

h(CS)

CS hold time, t

Data bus input setup time, t

su(D)

25

Data bus input hold time, t

h(D)

10

Pulse duration, WR low, t

w(WR)

40

Operating free-air temperature, T

−55

125

−55

125

A

3

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

^{POST OFFICE BOX 1443}• HOUSTON, TEXAS 77251−1443

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SGLS028A − SEPTEMBER 1989 − REVISED MARCH 1995

electrical characteristics over recommended operating free-air temperature range, V = 10 V,

ref

OUT1 and OUT2 at GND (unless otherwise noted)

V

= 5 V

DD

TYP

V

= 15 V

TYP

DD

PARAMETER

TEST CONDITIONS

UNIT

µA

MIN

MAX

10

MIN

MAX

10

Full-range

I

High-level input current

Low-level input current

V = V

DD

IH

I

25°C

Full-range

25°C

1

−10

−1

−10

−1

V = 0

I

µA

IL

DB0−DB7 at 0,

WR and CS at 0 V

Full-range

25°C

400

50

200

50

OUT1

V

ref

=

10 V

Output leakage

current

I

nA

pkg

DD

DB0−DB7 at V

DD,

WR and CS at 0

Full-range

400

200

OUT2

V

ref

=

10 V

25°C

50

2

50

2

Quiescent DB0−DB7 at V min or V max

mA

IH

IL

Full-range

25°C

500

100

0.16

0.02

500

100

0.04

0.02

I

Supply current

Standby

DB0−DB7 at 0 V or V

µA

DD

Full-range

25°C

%/%

pF

Supply voltage sensitivity,

k

∆V = 10%

DD

SVS

∆gain/∆V

0.002

0.001

DD

Input capacitance, DB0−DB7,

WR, CS

C

V = 0

I

5

pF

i

OUT1

30

120

30

120

30

DB0−DB7 at 0, WR and CS at 0 V

OUT2

OUT1

OUT2

Output

capacitance

C

pF

o

DB0−DB7 at V , WR and CS at 0 V

DD

Reference input impedance

(REF to GND)

5

20

5

20

kΩ

operating characteristics over recommended operating free-air temperature range, V = 10 V,

ref

OUT1 and OUT2 at GND (unless otherwise noted)

V

= 5 V

V

DD

MIN

= 15 V

CC

MIN

PARAMETER

TEST CONDITIONS

UNIT

MAX

Linearity error

Gain error

0.2

1.4

1

0.2 %FSR

0.6

Full range

See Note 1

See Note 2

%FSR

25°C

0.5

Settling time (to 1/2 LSB)

100

80

ns

Propagation delay from digital input to

90% of final analog output current

80

Full range

0.5

V

=

10 V (100 kHz sinewave),

ref

Feedthrough at OUT1 or OUT2

Temperature coefficient of gain

%FSR

WR and CS at 0, DB0−DB7 at 0

25°C

0.25

%FSR/

°C

T

A

= 25°C to t

min

or t

max

0.004

0.001

NOTES: 1. Gain error is measured using the internal feedback resistor. Nominal Full Scale Range (FSR) = V − 1 LSB.

ref

2. OUT1 load = 100 Ω, C

ext

= 13 pF, WR at 0 V, CS at 0 V, DB0−DB7 at 0 V to V

or V to 0 V.

DD

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

^{POST OFFICE BOX 1443}• HOUSTON, TEXAS 77251−1443

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SGLS028A − SEPTEMBER 1989 − REVISED MARCH 1995

PRINCIPLES OF OPERATION

The AD7524M is an 8-bit multiplying D/A converter consisting of an inverted R-2R ladder, analog switches, and

data input latches. Binary weighted currents are switched between the OUT1 and OUT2 bus lines, thus

maintaining a constant current in each ladder leg independent of the switch state. The high-order bits are

decoded and these decoded bits, through a modification in the R-2R ladder, control three equally weighted

current sources. Most applications only require the addition of an external operational amplifier and a voltage

reference.

The equivalent circuit for all digital inputs low is seen in Figure 1. With all digital inputs low, the entire reference

current, I , is switched to OUT2. The current source 1/256 represents the constant current flowing through the

ref

termination resistor of the R-2R ladder, while the current source I

represents leakage currents to the

Ikg

substrate. The capacitances appearing at OUT1 and OUT2 are dependent upon the digital input code. With all

digital inputs high, the off-state switch capacitance (30 pF maximum) appears at OUT2 and the on-state switch

capacitance (120 pF maximum) appears at OUT1. With all digital inputs low, the situation is reversed as shown

in Figure 1. Analysis of the circuit for all digital inputs high is similar to Figure 1; however, in this case, I would

ref

be switched to OUT1.

Interfacing the AD7524M D/A converter to a microprocessor is accomplished via the data bus and the CS and

WR control signals. When CS and WR are both low, the AD7524M analog output responds to the data activity

on the DB0−DB7 data bus inputs. In this mode, the input latches are transparent and input data directly affects

the analog output. When either the CS signal or WR signal goes high, the data on the DB0−DB7 inputs are

latched until the CS and WR signals go low again. When CS is high, the data inputs are disabled regardless

of the state of the WR signal.

The AD7524M is capable of performing 2-quadrant or full 4-quadrant multiplication. Circuit configurations for

2-quadrant or 4-quadrant multiplication are shown in Figures 2 and 3. Input coding for unipolar and bipolar

operation are summarized in Tables 1 and 2, respectively.

5

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

^{POST OFFICE BOX 1443}• HOUSTON, TEXAS 77251−1443

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SGLS028A − SEPTEMBER 1989 − REVISED MARCH 1995

PRINCIPLES OF OPERATION

R

FB

R

OUT1

I

30 pF

1kg

REF

OUT2

120 pF

1/256

I

Figure 1. AD7524M Equivalent Circuit With All Digital Inputs Low

V

ref

V

DD

R

= 2 kΩ

R

A

B

(see Note A)

C (see Note B)

R

FB

DB0−DB7

OUT1

OUT2

−

+

Output

CS

WR

GND

Figure 2. Unipolar Operation (2-Quadrant Multiplication)

V

ref

V

DD

20 kΩ

R

= 2 kΩ

R

A

B

20 kΩ

(see Note A)

−

+

C (see Note B)

R

FB

OUT1

Output

10 kΩ

DB0−DB7

−

+

CS

OUT2

5 kΩ

WR

GND

Figure 3. Bipolar Operation (4-Quadrant Operation)

NOTES: A.

R and R used only if gain adjustment is required.

A B

B. C phase compensation (10 − 15 pF) is required when using high-speed amplifiers to prevent ringing or oscillation.

6

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^{POST OFFICE BOX 1443}• HOUSTON, TEXAS 77251−1443

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SGLS028A − SEPTEMBER 1989 − REVISED MARCH 1995

PRINCIPLES OF OPERATION

Table 1. Unipolar Binary Code

DIGITAL INPUT

(see NOTE 3)

ANALOG OUTPUT

MSB

LSB

11111111

10000001

10000000

01111111

00000001

00000000

−V (255/256)

ref

−V (129/256)

ref

−V (128/256) = −V /2

ref ref

−V (127/256)

ref

−V (1/256)

ref

0

NOTES: 3. LSB = 1/256 (V ).

ref

Table 2. Bipolar (Offset Binary) Code

DIGITAL INPUT

(see NOTE 4)

ANALOG OUTPUT

MSB

LSB

11111111

10000001

10000000

01111111

00000001

00000000

V

(127/128)

(128)

ref

V

0

ref

−V (128)

ref

−V (127/128)

−V

ref

NOTES: 4. LSB = 1/128 (V ).

ref

microprocessor interfaces

Data Bus

D0−D7

Z-80A

WR

DB0−DB7

AD7524M

OUT1

OUT2

WR

CS

Decode

Logic

IORQ

A0−A15

Address Bus

Figure 4. AD7524M−Z-80A Interface

7

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^{POST OFFICE BOX 1443}• HOUSTON, TEXAS 77251−1443

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SGLS028A − SEPTEMBER 1989 − REVISED MARCH 1995

PRINCIPLES OF OPERATION

Data Bus

D0−D7

6800

DB0−DB7

AD7524M

CS

Φ2

OUT1

OUT2

WR

Decode

Logic

VMA

A0−A15

Address Bus

Figure 5. AD7524M−6800 Interface

A8−A15

Address Bus

Decode

Logic

8-Bit

Latch

8051

CS

AD7524M

OUT1

OUT2

WR

ALE

WR

DB0−DB7

Address/Data Bus

AD0−AD7

Figure 6. AD7524M−8051 Interface

8

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

^{POST OFFICE BOX 1443}• HOUSTON, TEXAS 77251−1443

PACKAGE OPTION ADDENDUM

www.ti.com

1-Dec-2005

PACKAGING INFORMATION

Orderable Device

Status ⁽¹⁾

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

LCCC

CDIP

LCCC

CDIP

Drawing

5962-87700012A

5962-8770001EA

AD7524MFKB

AD7524MJ

OBSOLETE

FK

J

20

16

20

16

TBD

Call TI

FK

J

AD7524MJB

J

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan

-

The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS

&

no Sb/Br)

-

please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

Addendum-Page 1

IMPORTANT NOTICE

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Applications

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www.ti.com/audio

amplifier.ti.com

dataconverter.ti.com

www.dlp.com

Communications and Telecom www.ti.com/communications

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DLP® Products

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power.ti.com

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www.ti.com/automotive

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RFID

microcontroller.ti.com

www.ti-rfid.com

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Wireless

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www.ti.com/wireless-apps

RF/IF and ZigBee® Solutions www.ti.com/lprf

TI E2E Community Home Page

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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	AD7524AN
厂家：	TEXAS INSTRUMENTS
描述：	ADVANCED LINCMOS 8-BIT MULTIPLING 高级LinCMOS 8位复接转换器数模转换器光电二极管
文件：	总12页 (文件大小：253K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AD7524AN [TI]

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