ADC08060CIMT/NOPB [TI]
具有内部采样保持功能的 8 位、60MSPS 1.3mW/MSPS 模数转换器 (ADC) | PW | 24 | -40 to 85;
| 型号： | ADC08060CIMT/NOPB |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有内部采样保持功能的 8 位、60MSPS 1.3mW/MSPS 模数转换器 (ADC) | PW | 24 | -40 to 85 光电二极管 转换器 模数转换器 |
| 文件： | 总32页 (文件大小：1460K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ADC08060
www.ti.com
SNAS120H –OCTOBER 2000–REVISED MARCH 2013
ADC08060 8-Bit, 20 MSPS to 60 MSPS, 1.3 m W/MSPS A/D Converter with Internal Sample-
and-Hold
Check for Samples: ADC08060
1
FEATURES
DESCRIPTION
The ADC08060 is a low-power, 8-bit, monolithic
analog-to-digital converter with an on-chip track-and-
hold circuit. Optimized for low cost, low power, small
size and ease of use, this product operates at
conversion rates of 20 MSPS to 70 MSPS with
outstanding dynamic performance over its full
operating range while consuming just 1.3 mW per
MHz of clock frequency. That's just 78 mW of power
at 60 MSPS. Raising the PD pin puts the ADC08060
into a Power Down mode where it consumes just 1
mW.
2
•
Single-Ended Input
•
•
•
•
Internal Sample-and-Hold Function
Low Voltage (Single +3V) Operation
Small Package
Power-Down Feature
KEY SPECIFICATION
•
•
•
•
•
•
Resolution: 8 bits
Maximum Sampling Frequency: 60 MSPS (min)
DNL: 0.4 LSB(typ)
The unique architecture achieves 7.5 Effective Bits
with 25 MHz input frequency. The excellent DC and
AC characteristics of this device, together with its low
power consumption and single +3V supply operation,
make it ideally suited for many imaging and
communications applications, including use in
portable equipment. Furthermore, the ADC08060 is
resistant to latch-up and the outputs are short-circuit
proof. The top and bottom of the ADC08060's
reference ladder are available for connections,
enabling a wide range of input possibilities. The
digital outputs are TTL/CMOS compatible with a
separate output power supply pin to support
interfacing with 3V or 2.5V logic. The output coding is
straight binary and the digital inputs (CLK and PD)
are TTL/CMOS compatible.
ENOB 7.5bits (typ) at fIN = 25 MHz
THD: -60 dB (typ)
Power Consumption
–
–
Operating: 1.3 mW/MSPS (typ)
Power Down Mode: 1 mW (typ)
APPLICATIONS
•
•
•
•
•
Digital Imaging Systems
Communication Systems
Portable Instrumentation
Viterbi Decoders
Set-Top Boxes
The ADC08060 is offered in a 24-lead TSSOP
package and is specified over the industrial
temperature range of −40°C to +85°C.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2000–2013, Texas Instruments Incorporated
ADC08060
SNAS120H –OCTOBER 2000–REVISED MARCH 2013
www.ti.com
Block Diagram
DR V
(pin
18)
D
V
A
V
RT
1
7
8
ENCODER
& ERROR
CORRECTION
COARSE/FINE
COMPARATORS
1
1
7
8
8
DAT
OUTPUT
DRIVERS
A
SWITCHES
MUX
OU
V
RM
T
1
7
8
ENCODER
& ERROR
CORRECTION
COARSE/FINE
COMPARATORS
25
6
CLOCK
GEN
V
RB
CL
K
AGN
D
P
D
DR
V
IN
V
IN
GND
GND
(pin 17)
Pin Configuration
Figure 1. 24-Lead TSSOP
See PW Package
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Pin No.
SNAS120H –OCTOBER 2000–REVISED MARCH 2013
PIN DESCRIPTIONS AND EQUIVALENT CIRCUITS
Symbol
Equivalent Circuit
Description
6
VIN
Analog signal input. Conversion range is VRB to VRT.
Analog Input that is the high (top) side of the reference ladder
of the ADC. Nominal range is 1.0V to VA. Voltage on VRT and
VRB inputs define the VIN conversion range. Bypass well. See
THE ANALOG INPUT for more information.
3
9
VRT
Mid-point of the reference ladder. This pin should be bypassed
to a clean, quiet point in the analog ground plane with a 0.1
µF capacitor.
VRM
Analog Input that is the low side (bottom) of the reference
ladder of the ADC. Nominal range is 0.0V to (VRT – 1.0V).
Voltage on VRT and VRB inputs define the VIN conversion
range. Bypass well. See THE ANALOG INPUT for more
information.
10
23
VRB
PD
V
A
Power Down input. When this pin is high, the converter is in
the Power Down mode and the data output pins hold the last
conversion result.
CMOS/TTL compatible digital clock Input. VIN is sampled on
the falling edge of CLK input.
24
CLK
GND
13 thru 16
and
19 thru 22
Conversion data digital Output pins. D0 is the LSB, D7 is the
MSB. Valid data is output just after the rising edge of the CLK
input.
D0–D7
7
VIN GND
VA
Reference ground for the single-ended analog input, VIN.
Positive analog supply pin. Connect to a clean, quiet voltage
source of +3V. VA should be bypassed with a 0.1 µF ceramic
chip capacitor for each pin, plus one 10 µF capacitor. See
POWER SUPPLY CONSIDERATIONS for more information.
1, 4, 12
Power supply for the output drivers. If connected to VA,
decouple well from VA.
18
DR VD
17
DR GND
AGND
The ground return for the output driver supply.
The ground return for the analog supply.
2, 5, 8, 11
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
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(1)(2)(3)
Absolute Maximum Ratings
Supply Voltage (VA)
3.8V
VA + 0.3V
Driver Supply Voltage (DR VD)
Voltage on Any Input or Output Pin
−0.3V to VA
VA to AGND
Reference Voltage (VRT, VRB
)
CLK, OE Voltage Range
−0.3V to
(VA + 0.3V)
Digital Output Voltage (VOH, VOL
)
DR GND to DR VD
±25 mA
(4)
Input Current at Any Pin
(4)
Package Input Current
±50 mA
(5)
Power Dissipation at TA = 25°C
See
(6)
ESD Susceptibility
Human Body Model
Machine Model
2500V
250V
(7)
Soldering Temperature, Infrared, 10 seconds
Storage Temperature
235°C
−65°C to +150°C
(1) All voltages are measured with respect to GND = AGND = DR GND = 0V, unless otherwise specified.
(2) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur, including inoperability and degradation of
device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or
other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The recommended Operating
Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions.
(3) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
(4) When the input voltage at any pin exceeds the power supplies (that is, less than AGND or DR GND, or greater than VA or DR VD), the
current at that pin should be limited to 25 mA. The 50 mA maximum package input current rating limits the number of pins that can
safely exceed the power supplies with an input current of 25 mA to two.
(5) The absolute maximum junction temperature (TJmax) for this device is 150°C. The maximum allowable power dissipation is dictated by
TJmax, the junction-to-ambient thermal resistance (θJA), and the ambient temperature (TA), and can be calculated using the formula
PDMAX = (TJmax − TA) / θJA. The values for maximum power dissipation will be reached only when this device is operated in a severe
fault condition (e.g., when input or output pins are driven beyond the power supply voltages, or the power supply polarity is reversed).
Obviously, such conditions should always be avoided.
(6) Human body model is 100 pF capacitor discharged through a 1.5 kΩ resistor. Machine model is 220 pF discharged through ZERO
Ohms.
(7) See AN-450, “Surface Mounting Methods and Their Effect on Product Reliability” ().
(1)(2)
Operating Ratings
Operating Temperature Range
−40°C ≤ TA ≤ +85°C
+2.7V to +3.6V
+2.4V to VA
Supply Voltage (VA)
Driver Supply Voltage (DR VD)
Ground Difference |GND - DR GND|
0V to 300 mV
Upper Reference Voltage (VRT
)
1.0V to (VA + 0.1V)
0V to (VRT − 1.0V)
VRB to VRT
Lower Reference Voltage (VRB
)
VIN Voltage Range
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur, including inoperability and degradation of
device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or
other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The recommended Operating
Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions.
(2) All voltages are measured with respect to GND = AGND = DR GND = 0V, unless otherwise specified.
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Converter Electrical Characteristics
The following specifications apply for VA = DR VD = +3.0VDC, VRT = +1.9V, VRB = 0.3V, CL = 10 pF, fCLK = 60 MHz at 50% duty
(1)(2)(3)
cycle. Boldface limits apply for TJ = TMIN to TMAX: all other limits TA = 25°C
Units
(Limits)
(4)
(4)
Symbol
Parameter
Conditions
Typical
Limits
DC ACCURACY
INL
Integral Non-Linearity
±0.5
±0.4
±1.3
LSB (max)
+1.0
−0.9
LSB (max)
LSB (min)
DNL
Differential Non-Linearity
Missing Codes
0
(max)
FSE
ZSE
Full Scale Error
18
26
±28
±35
mV (max)
mV (max)
Zero Scale Offset Error
ANALOG INPUT AND REFERENCE CHARACTERISTICS
VRB
VRT
V (min)
V (max)
VIN
CIN
Input Voltage
1.6
(CLK LOW)
(CLK HIGH)
3
4
pF
VIN Input Capacitance
VIN = 0.75V +0.5 Vrms
pF
RIN
RIN Input Resistance
Full Power Bandwidth
>1
200
MΩ
BW
MHz
VA
V (max)
V (min)
V (max)
V (min)
V (min)
V (max)
Ω (min)
Ω (max)
mA (min)
mA (max)
VRT
Top Reference Voltage
1.9
0.3
1.6
220
7.3
1.0
V
RT − 1.0
VRB
Bottom Reference Voltage
0
1.0
VRT - VRB Reference Delta
2.3
150
300
5.3
RREF
Reference Ladder Resistance
VRT to VRB
IREF
Reference Ladder Current
10.6
(1) The Electrical characteristics tables list ensured specifications under the listed Recommended Conditions except as otherwise modified
or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations for room temperature only
and are not ensured.
(2) The analog inputs are protected as shown below. Input voltage magnitudes up to VA + 300 mV or to 300 mV below GND will not
damage this device. However, errors in the A/D conversion can occur if the input goes above DR VD or below GND by more than 100
mV. For example, if VA is 2.7VDC the full-scale input voltage must be ≤2.6VDC to ensure accurate conversions.
(3) To ensure accuracy, it is required that VA and DR VD be well bypassed. Each supply pin must be decoupled with separate bypass
capacitors.
(4) Typical figures are at TJ = 25°C, and represent most likely parametric norms at specific conditions at the time of product characterization
and are not ensured. Test limits are specified to TI's AOQL (Average Outgoing Quality Level).
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Converter Electrical Characteristics (continued)
The following specifications apply for VA = DR VD = +3.0VDC, VRT = +1.9V, VRB = 0.3V, CL = 10 pF, fCLK = 60 MHz at 50% duty
cycle. Boldface limits apply for TJ = TMIN to TMAX: all other limits TA = 25°C (1)(2)(3)
Units
(Limits)
(4)
(4)
Symbol
Parameter
Conditions
Typical
Limits
CLK, PD DIGITAL INPUT CHARACTERISTICS
VIH
VIL
IIH
Logical High Input Voltage
Logical Low Input Voltage
Logical High Input Current
Logical Low Input Current
Logic Input Capacitance
DR VD = VA = 3.3V
2.0
0.8
V (min)
V (max)
nA
DR VD = VA = 2.7V
VIH = DR VD = VA = 3.3V
VIL = 0V, DR VD = VA = 2.7V
10
−50
3
IIL
nA
CIN
pF
DIGITAL OUTPUT CHARACTERISTICS
VOH
VOL
High Level Output Voltage
Low Level Output Voltage
VA = DR VD = 2.7V, IOH = −400 µA
2.6
0.4
2.4
0.5
V (min)
V (max)
VA = DR VD = 2.7V, IOL = 1.0 mA
DYNAMIC PERFORMANCE
fIN = 4.4 MHz, VIN = −0.25 dBFS
fIN = 10 MHz, VIN = −0.25 dBFS
fIN = 25 MHz, VIN = −0.25 dBFS
fIN = 29 MHz, VIN = −0.25 dBFS
fIN = 4.4 MHz, VIN = −0.25 dBFS
fIN = 10 MHz, VIN = −0.25 dBFS
fIN = 25 MHz, VIN = −0.25 dBFS
fIN = 29 MHz, VIN = −0.25 dBFS
fIN = 4.4 MHz, VIN = −0.25 dBFS
fIN = 10 MHz, VIN = −0.25 dBFS
fIN = 25 MHz, VIN = −0.25 dBFS
fIN = 29 MHz, VIN = −0.25 dBFS
fIN = 4.4 MHz, VIN = −0.25 dBFS
fIN = 10 MHz, VIN = −0.25 dBFS
fIN = 25 MHz, VIN = −0.25 dBFS
fIN = 29 MHz, VIN = −0.25 dBFS
fIN = 4.4 MHz, VIN = −0.25 dBFS
fIN = 10 MHz, VIN = −0.25 dBFS
fIN = 25 MHz, VIN = −0.25 dBFS
fIN = 29 MHz, VIN = −0.25 dBFS
fIN = 4.4 MHz, VIN = −0.25 dBFS
fIN = 10 MHz, VIN = −0.25 dBFS
fIN = 25 MHz, VIN = −0.25 dBFS
fIN = 29 MHz, VIN = −0.25 dBFS
fIN = 4.4 MHz, VIN = −0.25 dBFS
fIN = 10 MHz, VIN = −0.25 dBFS
fIN = 25 MHz, VIN = −0.25 dBFS
fIN = 29 MHz, VIN = −0.25 dBFS
7.6
7.6
7.5
7.4
47
Bits
Bits (min)
Bits
7.1
ENOB
SINAD
SNR
Effective Number of Bits
Bits
dB
47
44.5
44.6
dB (min)
dB
Signal-to-Noise & Distortion
Signal-to-Noise Ratio
47
46
dB
47
dB
47
dB (min)
dB
47
46
dB
64
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
63
SFDR
THD
Spurious Free Dynamic Range
Total Harmonic Distortion
2nd Harmonic Distortion
60
54
−64
−63
-57
−54
-70
−65
-64
−54
−72
−70
-68
−65
HD2
HD3
IMD
3rd Harmonic Distortion
Intermodulation Distortion
f1 = 11 MHz, VIN = −6.25 dBFS
f2 = 12 MHz, VIN = −6.25 dBFS
-55
dBc
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Converter Electrical Characteristics (continued)
The following specifications apply for VA = DR VD = +3.0VDC, VRT = +1.9V, VRB = 0.3V, CL = 10 pF, fCLK = 60 MHz at 50% duty
cycle. Boldface limits apply for TJ = TMIN to TMAX: all other limits TA = 25°C (1)(2)(3)
Units
(Limits)
(4)
(4)
Symbol
Parameter
Conditions
Typical
Limits
POWER SUPPLY CHARACTERISTICS
DC Input
25
25
31
1
mA (max)
mA
IA
Analog Supply Current
fIN = 10 MHz, VIN = −3 dBFS
DC Input
0.3
4.4
25.3
29.4
0.2
76
mA (max)
mA
DR ID
Output Driver Supply Current
(5)
fIN = 10 MHz, VIN = 3 dBFS
DC Input
32
mA (max)
IA + DRID Total Operating Current
fIN = 10 MHz, VIN = −3 dBFS, PD = Low
CLK Low, PD = Hi
mA (max)
DC Input
96
mW (max)
mW
PC
Power Consumption
fIN = 10 MHz, VIN = −3 dBFS, PD = Low
CLK Low, PD = Hi
88
0.6
54
mW
PSRR1
PSRR2
Power Supply Rejection Ratio
Power Supply Rejection Ratio
FSE change with 2.7V to 3.3V change in VA
dB
SNR change with 200 mV at 200 kHz on
supply
45
dB
AC ELECTRICAL CHARACTERISTICS
fC1
fC2
tCL
tCH
tOH
tOD
Maximum Conversion Rate
Minimum Conversion Rate
Minimum Clock Low Time
Minimum Clock High Time
Output Hold Time
70
20
60
MHz (min)
MHz
6.7
6.7
ns (min)
ns (min)
ns
CLK Rise to Data Invalid
CLK Rise to Data Valid
4.4
8.2
2.5
1.5
2
Output Delay
12
ns (max)
Clock Cycles
ns
Pipeline Delay (Latency)
Sampling (Aperture) Delay
Aperture Jitter
tAD
tAJ
CLK Fall to Acquisition of Data
ps rms
(5) IDR is the current consumed by the switching of the output drivers and is primarily determined by the load capacitance on the output
pins, the supply voltage, VDR, and the rate at which the outputs are switching (which is signal dependent), IDR = VDR (CO x fO + C1 x f1
+ … + C71 x f7) where VDR is the output driver power supply voltage, Cn is the total capacitance on any given output pin, and fn is the
average frequency at which that pin is toggling.
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Typical Performance Characteristics
VA = DR VD = 3V, fCLK = 60 MHz, fIN = 10 MHz, unless otherwise stated
INL
vs.
Temperature
INL
Figure 2.
Figure 3.
INL
vs.
INL
vs.
Sample Rate
Supply Voltage
Figure 4.
DNL
Figure 5.
DNL
vs.
Temperature
Figure 6.
Figure 7.
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Typical Performance Characteristics (continued)
VA = DR VD = 3V, fCLK = 60 MHz, fIN = 10 MHz, unless otherwise stated
DNL
DNL
vs.
Sample Rate
vs.
Supply Voltage
Figure 8.
Figure 9.
SNR
vs.
Temperature
SNR
vs.
Supply Voltage
Figure 10.
Figure 11.
SNR
vs.
Sample Rate
SNR
vs.
Input Frequency
Figure 12.
Figure 13.
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Typical Performance Characteristics (continued)
VA = DR VD = 3V, fCLK = 60 MHz, fIN = 10 MHz, unless otherwise stated
SNR
Distortion
vs.
Temperature
vs.
Clock Duty Cycle
Figure 14.
Figure 15.
Distortion
vs.
Supply Voltage
Distortion
vs.
Sample Rate
Figure 16.
Figure 17.
Distortion
vs.
Input Frequency
Distortion
vs.
Clock Duty Cycle
Figure 18.
Figure 19.
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Typical Performance Characteristics (continued)
VA = DR VD = 3V, fCLK = 60 MHz, fIN = 10 MHz, unless otherwise stated
SINAD/ENOB
SINAD/ENOB
vs.
Supply Voltage
vs.
Temperature
Figure 20.
Figure 21.
SINAD/ENOB
vs.
Sample Rate
SINAD/ENOB
vs.
Clock Duty Cycle
Figure 22.
Figure 23.
SINAD/ENOB
vs.
Input Frequency
Power Consumption
vs.
Sample Rate
Figure 24.
Figure 25.
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Typical Performance Characteristics (continued)
VA = DR VD = 3V, fCLK = 60 MHz, fIN = 10 MHz, unless otherwise stated
Spectral Response @ fIN = 10.1 MHz
Spectral Response @ fIN = 25 MHz
Figure 26.
Figure 27.
Intermodulation Distortion (IMD)
Figure 28.
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Specification Definitions
APERTURE (SAMPLING) DELAY is that time required after the fall of the clock input for the sampling switch to
open. The Sample/Hold circuit effectively stops capturing the input signal and goes into the “hold” mode tAD after
the clock goes low.
APERTURE JITTER is the variation in aperture delay from sample to sample. Aperture jitter shows up as noise
at the output.
CLOCK DUTY CYCLE is the ratio of the time that the clock waveform is at a logic high to the total time of one
clock period.
DIFFERENTIAL NON-LINEARITY (DNL) is the measure of the maximum deviation from the ideal step size of 1
LSB. Measured at 60 MSPS with a ramp input.
EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE BITS) is another method of specifying Signal-to-Noise
and Distortion Ratio, or SINAD. ENOB is defined as (SINAD – 1.76) / 6.02 and says that the converter is
equivalent to a perfect ADC of this (ENOB) number of bits.
FULL-POWER BANDWIDTH is the frequency at which the reconstructed output fundamental drops 3 dB below
its low frequency value for a full scale input.
FULL-SCALE ERROR is a measure of how far the last code transition is from the ideal 1½ LSB below VRT and
is defined as:
Vmax + 1.5 LSB – VRT
where
•
Vmax is the voltage at which the transition to the maximum (full scale) code occurs
(1)
INTEGRAL NON-LINEARITY (INL) is a measure of the deviation of each individual code from a line drawn from
zero scale (½ LSB below the first code transition) through positive full scale (½ LSB above the last code
transition). The deviation of any given code from this straight line is measured from the center of that code value.
The end point test method is used. Measured at 60 MSPS with a ramp input.
INTERMODULATION DISTORTION (IMD) is the creation of additional spectral components as a result of the
interaction between two sinusoidal frequencies that are applied to the ADC input at the same time. IMD is the
ratio of the power in the second and third order intermodulation products to the total power in the original
frequencies.
MISSING CODES are those output codes that are skipped and will never appear at the ADC outputs. These
codes cannot be reached with any input value.
POWER SUPPLY REJECTION RATIO (PSRR) is a measure of how well the ADC rejects a change in the power
supply voltage. For the ADC08060, PSRR1 is the ratio of the change in d.c. power supply voltage to the resulting
change in Full-Scale Error, expressed in dB. PSRR2 is a measure of how well an a.c. signal riding upon the
power supply is rejected and is here defined as:
where
•
SNR0 is the SNR measured with no noise or signal on the supply lines and SNR1 is the SNR measured with a
200 kHz, 200 mVP-P signal riding upon the supply lines (2)
OUTPUT DELAY is the time delay after the rising edge of the input clock before the data changes at the output
pins.
OUTPUT HOLD TIME is the length of time that the output data is valid after the rise of the input clock.
PIPELINE DELAY (LATENCY) is the number of clock cycles between initiation of conversion and when that data
is presented to the output driver stage. New data is available at every clock cycle, but the data lags the
conversion by the Pipeline Delay plus the Output Delay.
SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in dB, of the rms value of the input signal frequency at
the output to the rms value of the sum of all other spectral components below one-half the sampling frequency,
not including harmonics or d.c.
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SIGNAL TO NOISE PLUS DISTORTION (S/(N+D) or SINAD) is the ratio, expressed in dB, of the rms value of
the input signal frequency at the output to the rms value of all of the other spectral components below half the
clock frequency, including harmonics but excluding d.c.
SPURIOUS FREE DYNAMIC RANGE (SFDR) is the difference, expressed in dB, between the rms values of the
input signal frequency at the output and the peak spurious signal, where a spurious signal is any signal present
in the output spectrum that is not present at the input.
TOTAL HARMONIC DISTORTION (THD) is the ratio, expressed in dB, of the total of the first nine harmonic
levels at the output to the level of the fundamental at the output. THD is calculated as
where
•
•
f1 is the RMS power of the fundamental (input) frequency
f2 through f10 is the power in the first 9 harmonics in the output spectrum
(3)
ZERO SCALE OFFSET ERROR is the error in the input voltage required to cause the first code transition. It is
defined as
VOFF = VZT − VRB
where
•
VZT is the first code transition input voltage
(4)
Timing Diagram
Figure 29. ADC08060 Timing Diagram
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FUNCTIONAL DESCRIPTION
The ADC08060 uses a new, unique architecture that achieves over 7.4 effective bits at input frequencies up to
30 MHz.
The analog input signal that is within the voltage range set by VRT and VRB is digitized to eight bits. Output format
is straight binary. Input voltages below VRB will cause the output word to consist of all zeroes. Input voltages
above VRB will cause the output word to consist of all ones.
Incorporating a switched capacitor bandgap, the ADC08060 exhibits a power consumption that is proportional to
frequency, limiting power consumption to what is needed at the clock rate that is used. This and its excellent
performance over a wide range of clock frequencies makes it an ideal choice as a single ADC for many 8-bit
needs.
Data is acquired at the falling edge of the clock and the digital equivalent of that data is available at the digital
outputs 2.5 clock cycles plus tOD later. The ADC08060 will convert as long as the clock signal is present. The
output coding is straight binary.
The device is in the active state when the Power Down pin (PD) is low. When the PD pin is high, the device is in
the power down mode, where the output pins hold the last conversion before the PD pin went high and the
device consumes just 1 mW.
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APPLICATIONS INFORMATION
REFERENCE INPUTS
The reference inputs VRT and VRB are the top and bottom of the reference ladder, respectively. Input signals
between these two voltages will be digitized to 8 bits. External voltages applied to the reference input pins should
be within the range specified in the Operating Ratings (1.0V to (VA + 0.1V) for VRT and 0V to (VRT − 1.0V) for
VRB). Any device used to drive the reference pins should be able to source sufficient current into the VRT pin and
sink sufficient current from the VRB pin.
The reference bias circuit of Figure 30 is very simple and the performance is adequate for many applications.
However, circuit tolerances will lead to a wide reference voltage range. Superior performance can generally be
achieved by driving the reference pins with a low impedance source.
The circuit of Figure 31 will allow a more accurate setting of the reference voltages. The upper amplifier must be
able to source the reference current as determined by the value of the reference resistor and the value of (VRT
-
VRB). The lower amplifier must be able to sink this reference current. Both should be stable with a capacitive
load. The LM8272 was chosen because of its rail-to-rail input and output capability, its high current output and its
ability to drive large capacitance loads. Of course, the divider resistors at the amplifier input could be changed to
suit your reference voltage needs, or the divider can be replaced with potentiometers or DACs for precise
settings. The bottom of the ladder (VRB) may simply be returned to ground if the minimum input signal excursion
is 0V. Be sure that the driving sources can source sufficient current into the VRT pin and sink enough current from
the VRB pin to keep these pins stable.
VRT should always be more positive than VRB at least by the minimum VRT - VRB difference in Electrical
Characteristics to minimize noise. Furthermore, the difference between VRT and VRB should not exceed the
maximum value specified in Electrical Characteristics to avoid signal distortion.
VRM (pin 9) is the center of the reference ladder and should be bypassed to a clean, quiet point in the analog
ground plane with a 0.1 µF capacitor. DO NOT allow this pin to float.
Choke
+3
V
+
+
+
10 mF
10 mF
10 mF
0.1 mF
0.1 mF
0.1 mF
1
4
12
18
DR
V
V
A
D
6
7
+3
V
V
IN
V
GND
IN
110
1
%
13
14
15
16
19
20
21
22
1.5V
D7
,
nomina
D6
D5
D4
D3
D2
D1
D0
R
T
V
3
9
l
+
10 mF
0.1 mF
ADC08060
220
1
%
0.1 mF
10
23
V
RB
PD
2
AGND
DR GND CLK
17 24
5
8 11
Because of the ladder and external resistor tolerances, the reference voltage can vary too much for some
applications.
Figure 30. Simple, low component count reference biasing.
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+3V
Choke
+
+
10 mF
10 mF
470W
+3V
+
1 mF
10 mF
604W
0.1 mF
0.1 mF
LM4040-2.5
1
4
12
18
DR V
3
2
8
1/2 LM8272
+
V
1
6
7
A
D
V
IN
-
4
0.1 mF
V
GND
IN
0.01 mF
13
14
15
16
19
20
21
22
D7
D6
D5
D4
D3
D2
D1
D0
V
RT
3
1 mF
4.7k
9
1.62k
ADC08060
0.1 mF
4.7k
10
V
RB
1 mF
0.01 mF
0.1 mF
6
5
23
-
7
PD
2
AGND
11
DR GND CLK
17 24
+
1/2 LM8272
5
8
309W
Driving the reference to force desired values requires driving with a low impedance source.
Figure 31.
THE ANALOG INPUT
The analog input of the ADC08060 is a switch followed by an integrator. The input capacitance changes with the
clock level, appearing as 3 pF when the clock is low, and 4 pF when the clock is high. The sampling nature of
the analog input causes current spikes that result in voltage spikes at the analog input pin. Any circuit used to
drive the analog input must be able to drive that input and to settle within the clock high time. The LMH6702 has
been found to be a good amplifier to drive the ADC08060.
Figure 32 shows an example of an input circuit using the LMH6702. Any input amplifier should incorporate some
gain as operational amplifiers exhibit better phase margin and transient response with gains above 2 or 3 than
with unity gain. If an overall gain of less than 3 is required, attenuate the input and operate the amplifier at a
higher gain, as shown in Figure 32.
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Choke
+3V
+
+5V
+
10 mF
10 mF
0.1 mF
Gain
Adjust
0.1 mF
0.1 mF
12
200
1
4
12
18
DR V
D
-
22
V
*
6
7
A
10
LMH6702
+
V
V
IN
IN
240
Signal
Input
10 pF
GND
13
14
15
16
19
20
21
22
100
47
D7
D6
D5
D4
D3
D2
D1
D0
0.1 mF
ADC08060
0.33 mF
V
RT
3
9
*
*
V
RM
4.7k
+3V
1k
1k
Offset
Adjust
10
23
-5V
V
17
RB
DR GND
Ground connections marked with —*“
should enter the ground plane at a
common point
PD
CLK
AGND
7 8 11
24
2
5
The input amplifier should incorporate some gain for best performance (see text).
Figure 32.
The RC at the amplifier output filters the clock rate energy that comes out of the analog input due to the input
sampling circuit. The optimum time constant for this circuit depends not only upon the amplifier and ADC, but
also on the circuit layout and board material. A resistor value should be chosen between 18Ω and 47Ω and the
capacitor value chose according to the formula
(5)
This will provide optimum SNR performance. Best THD performance is realized when the capacitor and resistor
values are both zero. To optimize SINAD, reduce the capacitor or resistor value until SINAD performance is
optimized. That is, until SNR = −THD. This value will usually be in the range of 40% to 65% of the value
calculated with the above formula. An accurate calculation is not possible because of the board material and
layout dependence.
The above is intended for oversampling or Nyquist applications. There should be no resistor or capacitor
between the ADC input and any amplifier for undersampling applications.
The circuit of Figure 32 has both gain and offset adjustments. If you eliminate these adjustments normal circuit
tolerances may cause signal clipping unless care is exercised in the worst case analysis of component
tolerances and the input signal excursion is appropriately limited to account for the worst case conditions. Of
course, this means that the designer will not be able to depend upon getting a full scale output with maximum
signal input.
POWER SUPPLY CONSIDERATIONS
A/D converters draw sufficient transient current to corrupt their own power supplies if not adequately bypassed. A
10 µF tantalum or aluminum electrolytic capacitor should be placed within an inch (2.5 cm) of the A/D power
pins, with a 0.1 µF ceramic chip capacitor placed within one centimeter of the converter's power supply pins.
Leadless chip capacitors are preferred because they have low lead inductance.
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While a single voltage source is recommended for the VA and DR VD supplies of the ADC08060, these supply
pins should be well isolated from each other to prevent any digital noise from being coupled into the analog
portions of the ADC. A choke or 27Ω resistor is recommended between these supply lines with adequate bypass
capacitors close to the supply pins.
As is the case with all high speed converters, the ADC08060 should be assumed to have little power supply
rejection. None of the supplies for the converter should be the supply that is used for other digital circuitry in any
system with a lot of digital power being consumed. The ADC supplies should be the same supply used for other
analog circuitry.
No pin should ever have a voltage on it that is in excess of the supply voltage or below ground by more than 300
mV, not even on a transient basis. This can be a problem upon application of power and power shut-down. Be
sure that the supplies to circuits driving any of the input pins, analog or digital, do not come up any faster than
does the voltage at the ADC08060 power pins.
THE DIGITAL INPUT PINS
The ADC08060 has two digital input pins: The PD pin and the Clock pin.
The PD Pin
The Power Down (PD) pin, when high, puts the ADC08060 into a low power mode where power consumption is
reduced to 1 mW. Output data is valid and accurate about 1 microsecond after the PD pin is brought low.
The digital output pins retain the last conversion output code when either the clock is stopped or the PD pin is
high.
The ADC08060 Clock
Although the ADC08060 is tested and its performance is ensured with a 60 MHz clock, it typically will function
well with clock frequencies from 20 MHz to 70 MHz.
Halting the clock will provide nearly as much power saving as raising the PD pin high. Typical power
consumption with a stopped clock is 3 mW, compared to 1 mW when PD is high. The digital outputs will remain
in the same state as they were before the clock was halted.
Once the clock is restored (or the PD pin is brought low), there is a time of about 1 µs before the output data is
valid. However, because of the linear relationship between total power consumption and clock frequency, the
part requires about 1 µs after the clock is restarted or substantially changed in frequency before the part returns
to its specified accuracy.
The low and high times of the clock signal can affect the performance of any A/D Converter. Because achieving
a precise duty cycle is difficult, the ADC08060 is designed to maintain performance over a range of duty cycles.
While it is specified and performance is ensured with a 50% clock duty cycle and 60 Msps, ADC08060
performance is typically maintained with clock high and low times of 3.3 ns, corresponding to a clock duty cycle
range of 40% to 50% with a 60 MHz clock. Note that the clock minimum high and low times may not be used
simultaneously.
The CLOCK line should be series terminated at the clock source in the characteristic impedance of that line. If
the clock line is longer than
where
•
•
tr is the clock rise time
tPD is the propagation rate of the signal along the trace
(6)
If the clock source is used to drive more than just the ADD08060, the CLOCK pin should be a.c. terminated with
a series RC to ground such that the resistor value is equal to the characteristic impedance of the clock line and
the capacitor value is
where
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•
•
tPD is the signal propagation rate down the clock line, "L" is the line length
ZO is the characteristic impedance of the clock line
(7)
This termination should be located as close as possible to, but within one centimeter of, the ADC08060 clock pin.
Further, the termination should be beyond the ADC08060 clock pin as seen from the clock source. Typical tPD is
about 150 ps/inch on FR-4 board material. For FR-4 board material, the value of C becomes
where
•
L is the length of the clock line in inches
(8)
LAYOUT AND GROUNDING
Proper grounding and proper routing of all signals are essential to ensure accurate conversion. A combined
analog and digital ground plane should be used.
Since digital switching transients are composed largely of high frequency components, total ground plane copper
weight will have little effect upon the logic-generated noise because of the skin effect. Total surface area is more
important than is total ground plane volume. Capacitive coupling between the typically noisy digital circuitry and
the sensitive analog circuitry can lead to poor performance that may seem impossible to isolate and remedy. The
solution is to keep the analog circuitry well separated from the digital circuitry.
The DR GND connection to the ground plane should not use the same feedthrough used by other ground
connections.
High power digital components should not be located on or near a straight line between the ADC (or any linear
component) and the power supply area as the resulting common return current path could cause fluctuation in
the analog “ground” return of the ADC.
Generally, analog and digital lines should cross each other at 90° to avoid getting digital noise into the analog
path. In high frequency systems, however, avoid crossing analog and digital lines altogether. Clock lines should
be isolated from ALL other lines, analog AND digital. Even the generally accepted 90° crossing should be
avoided as even a little coupling can cause problems at high frequencies. Best performance at high frequencies
is obtained with a straight signal path.
The analog input should be isolated from noisy signal traces to avoid coupling of spurious signals into the input.
Any external component (e.g., a filter capacitor) connected between the converter's input and ground should be
connected to a very clean point in the analog ground plane.
Figure 33 gives an example of a suitable layout. All analog circuitry (input amplifiers, filters, reference
components, etc.) should be placed together away from any digital components.
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Single
Ground
Plane
ADC Clock
Source
Locate driving amplifier
near ADC input pin
R
F
Locate Clock Source
near ADC clock pin
R
IN
ADC
08060
R
C
Locate power supply on
the digital side of the
ADC
LMH6702
Figure 33. Layout Example
DYNAMIC PERFORMANCE
The ADC08060 is a.c. tested and its dynamic performance is ensured. To meet the published specifications, the
clock source driving the CLK input must exhibit less than 10 ps (rms) of jitter. For best a.c. performance, isolating
the ADC clock from any digital circuitry should be done with adequate buffers, as with a clock tree. See
Figure 34.
It is good practice to keep the ADC clock line as short as possible and to keep it well away from any other
signals. Other signals can introduce jitter into the clock signal. The clock signal can also introduce noise into the
analog path.
Figure 34. Isolating the ADC Clock from Digital Circuitry
COMMON APPLICATION PITFALLS
Driving the inputs (analog or digital) beyond the power supply rails. For proper operation, all inputs should
not go more than 300 mV below the ground pins or 300 mV above the supply pins. Exceeding these limits on
even a transient basis may cause faulty or erratic operation. It is not uncommon for high speed digital circuits
(e.g., 74F and 74AC devices) to exhibit undershoot that goes more than a volt below ground. A 51Ω resistor in
series with the offending digital input will usually eliminate the problem.
Care should be taken not to overdrive the inputs of the ADC08060. Such practice may lead to conversion
inaccuracies and even to device damage.
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Attempting to drive a high capacitance digital data bus. The more capacitance the output drivers must
charge for each conversion, the more instantaneous digital current is required from DR VD and DR GND. These
large charging current spikes can couple into the analog section, degrading dynamic performance. Buffering the
digital data outputs (with a 74F541, for example) may be necessary if the data bus capacitance exceeds 10 pF.
Dynamic performance can also be improved by adding 100Ω series resistors at each digital output, reducing the
energy coupled back into the converter input pins.
Using an inadequate amplifier to drive the analog input. As explained in THE ANALOG INPUT, the
capacitance seen at the input alternates between 3 pF and 4 pF with the clock. This dynamic capacitance is
more difficult to drive than is a fixed capacitance, and should be considered when choosing a driving device. The
LMH6702 has been found to be a good device for driving the ADC08060.
Driving the VRT pin or the VRB pin with devices that can not source or sink the current required by the
ladder.As mentioned in REFERENCE INPUTS, care should be taken to see that any driving devices can source
sufficient current into the VRT pin and sink sufficient current from the VRB pin. If these pins are not driven with
devices than can handle the required current, these reference pins will not be stable, resulting in a reduction of
dynamic performance.
Using a clock source with excessive jitter, using an excessively long clock signal trace, or having other
signals coupled to the clock signal trace. This will cause the sampling interval to vary, causing excessive
output noise and a reduction in SNR performance. The use of simple gates with RC timing is generally
inadequate as a clock source.
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SNAS120H –OCTOBER 2000–REVISED MARCH 2013
REVISION HISTORY
Changes from Revision G (March 2013) to Revision H
Page
•
Changed layout of National Data Sheet to TI format .......................................................................................................... 22
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
ADC08060CIMT/NOPB
ADC08060CIMTX/NOPB
ACTIVE
TSSOP
TSSOP
PW
24
24
61
RoHS & Green
SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 85
-40 to 85
ADC08060
CIMT
ACTIVE
PW
2500 RoHS & Green
SN
ADC08060
CIMT
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
ADC08060CIMTX/NOPB TSSOP
PW
24
2500
330.0
16.4
6.95
8.3
1.6
8.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
*All dimensions are nominal
Device
Package Type Package Drawing Pins
TSSOP PW 24
SPQ
Length (mm) Width (mm) Height (mm)
367.0 367.0 35.0
ADC08060CIMTX/NOPB
2500
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
TUBE
*All dimensions are nominal
Device
Package Name Package Type
PW TSSOP
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
ADC08060CIMT/NOPB
24
61
495
8
2514.6
4.06
Pack Materials-Page 3
PACKAGE OUTLINE
PW0024A
TSSOP - 1.2 mm max height
S
C
A
L
E
2
.
0
0
0
SMALL OUTLINE PACKAGE
SEATING
PLANE
C
6.6
6.2
TYP
A
0.1 C
PIN 1 INDEX AREA
22X 0.65
24
1
2X
7.15
7.9
7.7
NOTE 3
12
B
13
0.30
24X
4.5
4.3
NOTE 4
0.19
1.2 MAX
0.1
C A B
0.25
GAGE PLANE
0.15
0.05
(0.15) TYP
SEE DETAIL A
0.75
0.50
0 -8
A
20
DETAIL A
TYPICAL
4220208/A 02/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.
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EXAMPLE BOARD LAYOUT
PW0024A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
SYMM
24X (1.5)
(R0.05) TYP
24
1
24X (0.45)
22X (0.65)
SYMM
12
13
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
15.000
(PREFERRED)
SOLDER MASK DETAILS
4220208/A 02/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
PW0024A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
24X (1.5)
SYMM
(R0.05) TYP
24
1
24X (0.45)
22X (0.65)
SYMM
12
13
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
4220208/A 02/2017
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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