ADC0808CCVX/NOPB [TI]
具有 0.75 LSB INL 的 8 位单通道 µP 兼容型模数转换器 | FN | 28 | -40 to 85;
| 型号： | ADC0808CCVX/NOPB |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有 0.75 LSB INL 的 8 位单通道 µP 兼容型模数转换器 | FN | 28 | -40 to 85 转换器 模数转换器 |
| 文件： | 总18页 (文件大小：353K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ADC0808,ADC0809
ADC0808/ADC0809 8-Bit P Compatible A/D Converters with 8-Channel
Multiplexer
Literature Number: SNAS535G
July 8, 2009
ADC0808/ADC0809
8-Bit μP Compatible A/D Converters with 8-Channel
Multiplexer
General Description
Features
The ADC0808, ADC0809 data acquisition component is a
monolithic CMOS device with an 8-bit analog-to-digital con-
verter, 8-channel multiplexer and microprocessor compatible
control logic. The 8-bit A/D converter uses successive ap-
proximation as the conversion technique. The converter fea-
tures a high impedance chopper stabilized comparator, a
256R voltage divider with analog switch tree and a successive
approximation register. The 8-channel multiplexer can direct-
ly access any of 8-single-ended analog signals.
Easy interface to all microprocessors
■
■
Operates ratiometrically or with 5 VDC or analog span
adjusted voltage reference
No zero or full-scale adjust required
8-channel multiplexer with address logic
0V to VCC input range
■
■
■
■
■
■
Outputs meet TTL voltage level specifications
ADC0808 equivalent to MM74C949
ADC0809 equivalent to MM74C949-1
The device eliminates the need for external zero and full-scale
adjustments. Easy interfacing to microprocessors is provided
by the latched and decoded multiplexer address inputs and
latched TTL TRI-STATE outputs.
Key Specifications
Resolution
Total Unadjusted Error
Single Supply
Low Power
8 Bits
±½ LSB and ±1 LSB
5 VDC
■
The design of the ADC0808, ADC0809 has been optimized
by incorporating the most desirable aspects of several A/D
conversion techniques. The ADC0808, ADC0809 offers high
speed, high accuracy, minimal temperature dependence, ex-
cellent long-term accuracy and repeatability, and consumes
minimal power. These features make this device ideally suit-
ed to applications from process and machine control to con-
sumer and automotive applications. For 16-channel multi-
plexer with common output (sample/hold port) see ADC0816
data sheet. (See AN-247 for more information.)
■
■
15 mW
■
Conversion Time
100 μs
■
Block Diagram
567201
See Ordering Information
© 2009 National Semiconductor Corporation
5672
www.national.com
Connection Diagrams
Dual-In-Line Package
Molded Chip Carrier Package
567211
Order Number ADC0808CCN or ADC0809CCN
See NS Package NA28E
567212
Order Number ADC0808CCV or ADC0809CCV
See NS Package V28A
Ordering Information
Temperature Range
−40°C to +85°C
V28A Molded Chip Carrier
Package Outline
NA28E Molded DIP
V28A Molded Chip Carrier
(Tape and Reel)
ADC0808CCVX
ADC0809CCVX
±½ LSB Unadjusted
±1 LSB Unadjusted
ADC0808CCN
ADC0809CCN
ADC0808CCV
ADC0809CCV
Error
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2
Absolute Maximum Ratings
(Notes 2, 1)
Operating Conditions
(Notes 1, 2)
Temperature Range
TMIN≤TA≤TMAX
−40°C≤TA≤+85°C
4.5 VDC to 6.0 VDC
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
ꢀ
Range of VCC
Supply Voltage (VCC) (Note 3)
Voltage at Any Pin
6.5V
−0.3V to (VCC
+0.3V)
Except Control Inputs
Voltage at Control Inputs
−0.3V to +15V
(START, OE, CLOCK, ALE, ADD A, ADD B, ADD C)
Storage Temperature Range
Package Dissipation at TA=25°C
Lead Temp. (Soldering, 10 seconds)
Dual-In-Line Package (plastic)
Molded Chip Carrier Package
Vapor Phase (60 seconds)
Infrared (15 seconds)
−65°C to +150°C
875 mW
260°C
215°C
220°C
400V
ESD Susceptibility (Note 8)
Electrical Characteristics – Converter Specifications
Converter Specifications: VCC=5 VDC=VREF+, VREF(−)=GND, TMIN≤TA≤TMAX and fCLK=640 kHz unless otherwise stated.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
ADC0808
Total Unadjusted Error
25°C
LSB
LSB
±½
±¾
TMIN to TMAX
ꢀ(Note 5)
ADC0809
Total Unadjusted Error
ꢀ(Note 5)
0°C to 70°C
TMIN to TMAX
±1
LSB
LSB
±1¼
Input Resistance
From Ref(+) to Ref(−)
(Note 4) V(+) or V(−)
Measured at Ref(+)
1.0
2.5
kΩ
VDC
V
Analog Input Voltage Range
Voltage, Top of Ladder
GND − 0.1
VCC + 0.1
VCC + 0.1
VREF(+)
VCC
(VCC/2) − 0.1 VCC/2 (VCC/2) + 0.1
Voltage, Center of Ladder
V
VREF(−)
IIN
Voltage, Bottom of Ladder
Comparator Input Current
Measured at Ref(−)
fc=640 kHz, (Note 6)
−0.1
−2
0
V
±0.5
2
μA
Electrical Characteristics – Digital Levels and DC Specifications
Digital Levels and DC Specifications: ADC0808CCN, ADC0808CCV, ADC0809CCN and ADC0809CCV, 4.75≤VCC≤5.25V,
−40°C≤TA≤+85°C unless otherwise noted
Symbol
Parameter
Conditions
Min
Typ
Max
Units
ANALOG MULTIPLEXER
VCC=5V, VIN=5V,
TA=25°C
IOFF(+)
OFF Channel Leakage Current
OFF Channel Leakage Current
10
200
1.0
nA
TMIN to TMAX
VCC=5V, VIN=0,
TA=25°C
μA
IOFF(−)
−200
−1.0
−10
nA
TMIN to TMAX
μA
CONTROL INPUTS
VIN(1)
VIN(0)
Logical “1” Input Voltage
Logical “0” Input Voltage
(VCC − 1.5)
V
V
1.5
3
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Symbol
IIN(1)
IIN(0)
ICC
Parameter
Conditions
VIN=15V
Min
Typ
Max
Units
Logical “1” Input Current (The Control
Inputs)
1.0
μA
Logical “0” Input Current (The Control
Inputs)
VIN=0
−1.0
μA
Supply Current
fCLK=640 kHz
0.3
3.0
mA
DATA OUTPUTS AND EOC (INTERRUPT)
VCC = 4.75V
IOUT = −360µA
IOUT = −10µA
VOUT(1)
Logical “1” Output Voltage
2.4
4.5
V
V
VOUT(0)
VOUT(0)
Logical “0” Output Voltage
IO=1.6 mA
IO=1.2 mA
VO=5V
0.45
0.45
3
V
V
Logical “0” Output Voltage EOC
μA
μA
IOUT
TRI-STATE Output Current
VO=0
−3
Electrical Characteristics – Timing Specifications
Timing Specifications VCC=VREF(+)=5V, VREF(−)=GND, tr=tf=20 ns and TA=25°C unless otherwise noted.
Symbol
tSTCLK
Parameter
Conditions
MIn
Typ
Max
900
200
200
50
Units
ns
Start Time Delay from Clock
Minimum Start Pulse Width
Minimum ALE Pulse Width
Minimum Address Set-Up Time
Minimum Address Hold Time
(Figure 5)
(Figure 5)
(Figure 5)
(Figure 5)
(Figure 5)
300
tWS
tWALE
ts
100
100
25
ns
ns
ns
tH
25
50
ns
tD
Analog MUX Delay Time From ALE RS=0Ω (Figure 5)
1
2.5
250
250
116
1280
μs
ns
ns
tH1, tH0
t1H, t0H
tc
CL=50 pF, RL=10k (Figure 8)
OE Control to Q Logic State
OE Control to Hi-Z
Conversion Time
125
125
100
640
CL=10 pF, RL=10k (Figure 8)
fc=640 kHz, (Figure 5) (Note 7)
90
10
μs
kHz
fc
Clock Frequency
Clock
Periods
tEOC
EOC Delay Time
(Figure 5)
0
8 + 2 μS
CIN
Input Capacitance
At Control Inputs
10
10
15
15
pF
pF
COUT
TRI-STATE Output Capacitance
At TRI-STATE Outputs
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating
the device beyond its specified operating conditions.
Note 2: All voltages are measured with respect to GND, unless otherwise specified.
Note 3: A Zener diode exists, internally, from VCC to GND and has a typical breakdown voltage of 7 VDC
.
Note 4: Two on-chip diodes are tied to each analog input which will forward conduct for analog input voltages one diode drop below ground or one diode drop
greater than the VCCn supply. The spec allows 100 mV forward bias of either diode. This means that as long as the analog VIN does not exceed the supply voltage
by more than 100 mV, the output code will be correct. To achieve an absolute 0VDC to 5VDC input voltage range will therefore require a minimum supply voltage
of 4.900 VDC over temperature variations, initial tolerance and loading.
Note 5: Total unadjusted error includes offset, full-scale, linearity, and multiplexer errors. See Figure 3. None of these A/Ds requires a zero or full-scale adjust.
However, if an all zero code is desired for an analog input other than 0.0V, or if a narrow full-scale span exists (for example: 0.5V to 4.5V full-scale) the reference
voltages can be adjusted to achieve this. See Figure 13.
Note 6: Comparator input current is a bias current into or out of the chopper stabilized comparator. The bias current varies directly with clock frequency and has
little temperature dependence (Figure 6). See paragraph 4.0.
Note 7: The outputs of the data register are updated one clock cycle before the rising edge of EOC.
Note 8: Human body model, 100 pF discharged through a 1.5 kΩ resistor.
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4
The bottom resistor and the top resistor of the ladder network
in Figure 1 are not the same value as the remainder of the
network. The difference in these resistors causes the output
characteristic to be symmetrical with the zero and full-scale
points of the transfer curve. The first output transition occurs
when the analog signal has reached +½ LSB and succeeding
output transitions occur every 1 LSB later up to full-scale.
Functional Description
MULTIPLEXER
The device contains an 8-channel single-ended analog signal
multiplexer. A particular input channel is selected by using the
address decoder. Table 1 shows the input states for the ad-
dress lines to select any channel. The address is latched into
the decoder on the low-to-high transition of the address latch
enable signal.
The successive approximation register (SAR) performs 8 it-
erations to approximate the input voltage. For any SAR type
converter, n-iterations are required for an n-bit converter. Fig-
ure 2 shows a typical example of a 3-bit converter. In the
ADC0808, ADC0809, the approximation technique is extend-
ed to 8 bits using the 256R network.
TABLE 1. Analog Channel Selection
ADDRESS LINE
SELECTED ANALOG
CHANNEL
C
B
L
A
The A/D converter's successive approximation register (SAR)
is reset on the positive edge of the start conversion start pulse.
The conversion is begun on the falling edge of the start con-
version pulse. A conversion in process will be interrupted by
receipt of a new start conversion pulse. Continuous conver-
sion may be accomplished by tying the end-of-conversion
(EOC) output to the SC input. If used in this mode, an external
start conversion pulse should be applied after power up. End-
of-conversion will go low between 0 and 8 clock pulses after
the rising edge of start conversion.
IN0
IN1
IN2
IN3
IN4
IN5
IN6
IN7
L
L
L
H
L
L
L
H
H
L
L
H
L
H
H
H
H
L
H
L
H
H
H
The most important section of the A/D converter is the com-
parator. It is this section which is responsible for the ultimate
accuracy of the entire converter. It is also the comparator drift
which has the greatest influence on the repeatability of the
device. A chopper-stabilized comparator provides the most
effective method of satisfying all the converter requirements.
CONVERTER CHARACTERISTICS
The Converter
The heart of this single chip data acquisition system is its 8-
bit analog-to-digital converter. The converter is designed to
give fast, accurate, and repeatable conversions over a wide
range of temperatures. The converter is partitioned into 3 ma-
jor sections: the 256R ladder network, the successive ap-
proximation register, and the comparator. The converter's
digital outputs are positive true.
The chopper-stabilized comparator converts the DC input sig-
nal into an AC signal. This signal is then fed through a high
gain AC amplifier and has the DC level restored. This tech-
nique limits the drift component of the amplifier since the drift
is a DC component which is not passed by the AC amplifier.
This makes the entire A/D converter extremely insensitive to
temperature, long term drift and input offset errors.
The 256R ladder network approach (Figure 1) was chosen
over the conventional R/2R ladder because of its inherent
monotonicity, which guarantees no missing digital codes.
Monotonicity is particularly important in closed loop feedback
control systems. A non-monotonic relationship can cause os-
cillations that will be catastrophic for the system. Additionally,
the 256R network does not cause load variations on the ref-
erence voltage.
Figure 4 shows a typical error curve for the ADC0808 as
measured using the procedures outlined in AN-179.
5
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567202
FIGURE 1. Resistor Ladder and Switch Tree
567213
567214
FIGURE 2. 3-Bit A/D Transfer Curve
FIGURE 3. 3-Bit A/D Absolute Accuracy Curve
567215
FIGURE 4. Typical Error Curve
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6
Timing Diagram
567204
FIGURE 5.
7
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Typical Performance Characteristics
567216
FIGURE 6. Comparator IIN vs. VIN
(VCC=VREF=5V)
567217
FIGURE 7. Multiplexer RON vs. VIN
(VCC=VREF=5V)
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8
TRI-STATE Test Circuits and Timing Diagrams
t1H, tH1
t0H, tH0
567218
567221
t1H, CL = 10 pF
t0H, CL = 10 pF
567222
567219
tH0, CL = 50 pF
tH1, CL = 50 pF
567223
FIGURE5867.2T20RI-STATE Test Circuits and Timing Diagrams
proportion of full-scale, reference requirements are greatly
reduced, eliminating a large source of error and cost for many
applications. A major advantage of the ADC0808, ADC0809
is that the input voltage range is equal to the supply range so
the transducers can be connected directly across the supply
and their outputs connected directly into the multiplexer in-
puts, (Figure 9).
Applications Information
OPERATION
1.0 RATIOMETRIC CONVERSION
The ADC0808, ADC0809 is designed as a complete Data
Acquisition System (DAS) for ratiometric conversion systems.
In ratiometric systems, the physical variable being measured
is expressed as a percentage of full-scale which is not nec-
essarily related to an absolute standard. The voltage input to
the ADC0808 is expressed by the equation
Ratiometric transducers such as potentiometers, strain
gauges, thermistor bridges, pressure transducers, etc., are
suitable for measuring proportional relationships; however,
many types of measurements must be referred to an absolute
standard such as voltage or current. This means a system
reference must be used which relates the full-scale voltage to
the standard volt. For example, if VCC=VREF=5.12V, then the
full-scale range is divided into 256 standard steps. The small-
est standard step is 1 LSB which is then 20 mV.
(1)
VIN= Input voltage into the ADC0808
Vfs= Full-scale voltage
2.0 RESISTOR LADDER LIMITATIONS
VZ= Zero voltage
The voltages from the resistor ladder are compared to the
selected into 8 times in a conversion. These voltages are
coupled to the comparator via an analog switch tree which is
referenced to the supply. The voltages at the top, center and
bottom of the ladder must be controlled to maintain proper
operation.
DX= Data point being measured
DMAX= Maximum data limit
DMIN= Minimum data limit
A good example of a ratiometric transducer is a potentiometer
used as a position sensor. The position of the wiper is directly
proportional to the output voltage which is a ratio of the full-
scale voltage across it. Since the data is represented as a
The top of the ladder, Ref(+), should not be more positive than
the supply, and the bottom of the ladder, Ref(−), should not
be more negative than ground. The center of the ladder volt-
9
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age must also be near the center of the supply because the
analog switch tree changes from N-channel switches to P-
channel switches. These limitations are automatically satis-
fied in ratiometric systems and can be easily met in ground
referenced systems.
Figure 10 shows a ground referenced system with a separate
supply and reference. In this system, the supply must be
trimmed to match the reference voltage. For instance, if a
5.12V is used, the supply should be adjusted to the same
voltage within 0.1V.
567207
FIGURE 9. Ratiometric Conversion System
The ADC0808 needs less than a milliamp of supply current
so developing the supply from the reference is readily ac-
complished. In Figure 11 a ground referenced system is
shown which generates the supply from the reference. The
buffer shown can be an op amp of sufficient drive to supply
the milliamp of supply current and the desired bus drive, or if
a capacitive bus is driven by the outputs a large capacitor will
supply the transient supply current as seen in Figure 12. The
LM301 is overcompensated to insure stability when loaded by
the 10 μF output capacitor.
The top and bottom ladder voltages cannot exceed VCC and
ground, respectively, but they can be symmetrically less than
VCC and greater than ground. The center of the ladder voltage
should always be near the center of the supply. The sensitivity
of the converter can be increased, (i.e., size of the LSB steps
decreased) by using a symmetrical reference system. In Fig-
ure 13, a 2.5V reference is symmetrically centered about
VCC/2 since the same current flows in identical resistors. This
system with a 2.5V reference allows the LSB bit to be half the
size of a 5V reference system.
567224
FIGURE 10. Ground Referenced
Conversion System Using Trimmed Supply
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10
567225
FIGURE 11. Ground Referenced Conversion System with
Reference Generating VCC Supply
567226
FIGURE 12. Typical Reference and Supply Circuit
11
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567227
RA=RB
*Ratiometric transducers
FIGURE 13. Symmetrically Centered Reference
3.0 CONVERTER EQUATIONS
VREF(+)÷512)
The transition between adjacent codes N and N+1 is given
by:
4.0 ANALOG COMPARATOR INPUTS
The dynamic comparator input current is caused by the peri-
odic switching of on-chip stray capacitances. These are con-
nected alternately to the output of the resistor ladder/switch
tree network and to the comparator input as part of the oper-
ation of the chopper stabilized comparator.
(2)
The center of an output code N is given by:
The average value of the comparator input current varies di-
rectly with clock frequency and with VIN as shown in
Figure 6.
(3)
The output code N for an arbitrary input are the integers within
the range:
If no filter capacitors are used at the analog inputs and the
signal source impedances are low, the comparator input cur-
rent should not introduce converter errors, as the transient
created by the capacitance discharge will die out before the
comparator output is strobed.
(4)
Where: VIN=Voltage at comparator input
VREF(+)=Voltage at Ref(+)
If input filter capacitors are desired for noise reduction and
signal conditioning they will tend to average out the dynamic
comparator input current. It will then take on the characteris-
tics of a DC bias current whose effect can be predicted
conventionally.
VREF(−)=Voltage at Ref(−)
VTUE=Total unadjusted error voltage (typically
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12
Typical Application
567210
*Address latches needed for 8085 and SC/MP interfacing the ADC0808 to a microprocessor
TABLE 2. Microprocessor Interface Table
READ WRITE INTERRUPT (COMMENT)
PROCESSOR
8080
MEMR
RD
MEMW
WR
INTR (Thru RST Circuit)
INTR (Thru RST Circuit)
INT (Thru RST Circuit, Mode 0)
SA (Thru Sense A)
8085
Z-80
RD
WR
SC/MP
6800
NRDS
VMA•φ2•R/W
NWDS
VMA•φ•R/W
IRQA or IRQB (Thru PIA)
13
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Physical Dimensions inches (millimeters) unless otherwise noted
Molded Dual-In-Line Package (N)
Order Number ADC0808CCN or ADC0809CCN
NS Package Number NA28E
Molded Chip Carrier (V)
Order Number ADC0808CCV or ADC0809CCV
NS Package Number V28A
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14
15
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amplifier.ti.com
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logic.ti.com
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microcontroller.ti.com
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