ADC08351 [TI]
8 位、42MSPS 模数转换器 (ADC);
| 型号： | ADC08351 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 8 位、42MSPS 模数转换器 (ADC) 转换器 模数转换器 |
| 文件： | 总27页 (文件大小：1185K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ADC08351
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SNAS026E –JUNE 2000–REVISED MARCH 2013
ADC08351 8-Bit, 42 MSPS, 40 mW A/D Converter
Check for Samples: ADC08351
1
FEATURES
DESCRIPTION
The ADC08351 is an easy to use low power, low
cost, small size, 42 MSPS analog-to-digital converter
that digitizes signals to 8 bits. The ADC08351 uses
an unique architecture that achieves 7.2 Effective Bits
with a 4.4 MHz input and 42 MHz clock frequency
and 6.8 Effective Bits with a 21 MHz input and 42
MHz clock frequency. Output formatting is straight
binary coding.
2
•
•
•
•
•
Low Input Capacitance
Internal Sample-and-Hold Function
Single +3V Operation
Power Down Feature
TRI-STATE Outputs
KEY SPECIFICATIONS
To minimize system cost and power consumption, the
ADC08351 requires minimal external components
and includes input biasing to allow optional a.c. input
signal coupling. The user need only provide a +3V
supply and a clock. Many applications require no
separate reference or driver components.
•
•
•
Resolution: 8 Bits
Maximum Sampling Frequency: 42MSPS (min)
ENOB @ fCLK = 42 MHz,
fIN = 4.4 MHz: 7.2 Bits (typ)
•
•
Ensured No Missing Codes
The excellent dc and ac characteristics of this device,
together with its low power consumption and +3V
single supply operation, make it ideally suited for
many video and imaging applications, including use in
portable equipment. Total power consumption is
reduced to less than 7 mW in the power-down mode.
Furthermore, the ADC08351 is resistant to latch-up
and the outputs are short-circuit proof.
Power Consumption: 40 mW (typ); 48 mW
(max) (Excluding Reference Current)
APPLICATIONS
•
•
•
•
•
•
•
•
•
Video Digitization
Digital Still Cameras
Set Top Boxes
Fabricated on a 0.35 micron CMOS process, the
ADC08351 is offered in TSSOP and WQFN (a
molded lead frame-based chip-scale package), and is
designed to operate over the industrial temperature
range of −40°C to +85°C.
Digital Camcorders
Communications
Medical Imaging
Personal Computer Video
CCD Imaging
Electro-Optics
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2000–2013, Texas Instruments Incorporated
ADC08351
SNAS026E –JUNE 2000–REVISED MARCH 2013
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ADC08351 Block Diagram
Pin Configuration
Figure 1. 20-Pin TSSOP - Top View
Figure 2. 24-Pin WQFN (CSP) - Bottom View
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PIN DESCRIPTIONS AND EQUIVALENT CIRCUITS(1)
Pin
No.
Symbol
Equivalent Circuit
Description
17
(17)
VIN
Analog signal input. Conversion range is 0.5 VP-P to 0.68 VA.
Positive reference voltage input. Operating range of this
voltage is 0.75V to VA. This pin should be bypassed with a 10
µF tantalum or aluminum electrolytic capacitor and a 0.1 µF
ceramic chip capacitor.
14
(14)
VREF
CMOS/TTL compatible digital input that, when low, enables
the digital outputs of the ADC08351. When high, the outputs
are in a high impedance state.
1
(22)
OE
12
(11)
CMOS/TTL compatible digital clock input. VIN is sampled on
the falling edge of CLK input.
CLK
CMOS/TTL compatible digital input that, when high, puts the
ADC08351 into the power down mode, where it consumes
minimal power. When this pin is low, the ADC08351 is in the
normal operating mode.
15
(15)
PD
3 thru
10
(1 thru
8)
Conversion data digital output pins. D0 is the LSB, D7 is the
MSB. Valid data is output just after the rising edge of the CLK
input. These pins are enabled by bringing the OE pin low.
D0–D7
Positive digital supply pin. Connect to a clean, quiet voltage
source of +3V. VA and VD should have a common supply and
be separately bypassed with a 10 µF tantalum or aluminum
electrolytic capacitor and a 0.1 µF ceramic chip capacitor.
See Layout and Grounding for more information.
11, 13
(10, 12)
VD
DGND
VA
2, 20
(21, 23)
The ground return for the digital supply. AGND and DGND
should be connected together close to the ADC08351.
Positive analog supply pin. Connected to a clean, quiet
voltage source of +3V. VA and VD should have a common
supply and be separately bypassed with a 10 µF tantalum or
aluminum electrolytic capacitor and a 0.1 µF ceramic chip
capacitor. See Layout and Grounding for more information.
16
(16)
The ground return for the analog supply. AGND and DGND
should be connected together close to the ADC08351
package.
18, 19
(18, 19)
AGND
(1) WQFN pins in parentheses
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
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Absolute Maximum Ratings(1)(2)(3)
Supply Voltage (VA, VD)
4.2V
−0.3V to 4.2V
±100 mV
Voltage on Any Input or Output Pin
Ground Difference (AGND–DGND)
CLK, OE Voltage Range
−0.5 to (VA + 0.5V)
VD to DGND
±25 mA
Digital Output Voltage (VOH, VOL
Input Current at Any Pin(4)
Package Input Current(4)
)
±50 mA
Package Dissipation at TA = 25°C
ESD Susceptibility(6)
See(5)
Human Body Model
Machine Model
4000V
200V
Soldering Temp., Infrared, 10 sec.(7)
Storage Temperature
235°C
−65°C to +150°C
(1) All voltages are measured with respect to GND = AGND = DGND = 0V, unless otherwise specified.
(2) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see the
Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance characteristics may
degrade when the device is not operated under the listed test conditions.
(3) If Military/Aerospace specified devices are required, please contact the TI Sales Office/ Distributors for availability and specifications.
(4) When the input voltage at any pin exceeds the power supplies (that is, less than AGND or DGND, or greater than VA or VD), the current
at that pin should be limited to 25 mA. The 50 mA maximum package input current rating limits the number of pins that can safely
exceed the power supplies with an input current of 25 mA to two.
(5) The absolute maximum junction temperature (TJmax) for this device is 150°C. The maximum allowable power dissipation is dictated by
TJmax, the junction-to-ambient thermal resistance (θJA), and the ambient temperature (TA), and can be calculated using the formula
PDMAX = (TJmax - TA)/θJA. For the 20-pin TSSOP, θJA is 135°C/W, so PDMAX = 926 mW at 25°C and 481 mW at the maximum
operating ambient temperature of 85°C. Note that the power dissipation of this device under normal operation will typically be about 68
mW (40 mW quiescent power + 23 mW reference ladder power + 5 mW due to 1 TTL loan on each digital output). The values for
maximum power dissipation listed above will be reached only when the ADC08351 is operated in a severe fault condition (e.g., when
input or output pins are driven beyond the power supply voltages, or the power supply polarity is reversed). Obviously, such conditions
should always be avoided.
(6) Human body model is 100 pF capacitor discharged through a 1.5 kΩ resistor. Machine model is 220 pF discharged through ZERO
Ohms.
(7) See AN-450, “Surface Mounting Methods and Their Effect on Product Reliability”, or the section entitled “Surface Mount” found in any
post 1986 Texas Instruments Linear Data Book, for other methods of soldering surface mount devices.
Operating Ratings(1)(2)
Operating Temperature Range
−40°C TA ≤ +85°C
+2.7V to +3.6V
0V to 100 mV
Supply Voltage (VA, VD)
Ground Difference |DGND–AGND|
VIN Voltage Range (VP-P
)
0.5V to 0.68 VA
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see the
Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance characteristics may
degrade when the device is not operated under the listed test conditions.
(2) All voltages are measured with respect to GND = AGND = DGND = 0V, unless otherwise specified.
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Converter Electrical Characteristics
The following specifications apply for VA = VD = +3.0 VDC, VREF = 2.4V, VIN = 1.63 VP-P, OE = 0V, CL = 20 pF, fCLK = 42 MHz,
50% duty cycle, unless otherwise specified.
Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25°C(1)(2)
Units
(Limits)
Symbol
Parameter
Conditions
Typical(3) Limits(3)
DC Accuracy
INL
Integral Non Linearity Error
Differential Non Linearity
±0.7
±0.6
±1.4
+1.3
−1.0
0
LSB (max)
LSB (max)
LSB (min)
(max)
DNL
Missing Codes
EZ
Zero Scale Offset Error
Full Scale Offset Error
−17
−7
mV
EFS
mV
Video Accuracy
DP
DG
Differential Phase Error
Differential Gain Error
fCLK = 20 MHz, Video Ramp Input
fCLK = 20 MHz, Video Ramp Input
1.0
1.5
Degree
%
Analog Input and Reference Characteristics
(CLK LOW)
(CLK HIGH)
4
11
pF
pF
kΩ
MHz
V
CIN
VIN Input Capacitance
VIN = 1.5V + 0.7 Vrms
RIN
RIN Input Resistance
Full-Power Bandwidth
7.2
FPBW
120
0.735
VA
VREF
IREF
Reference Input Voltage
Reference Input Current
At pin 14
V
7.7
mA
Power Supply Characteristics
PD = Low
10.5
1
mA
mA
IA
Analog Supply Current
Digital Supply Current
PD = High
PD = Low, No Digital Output Load
PD = High
2.9
0.5
13.4
40.2
<7
mA
ID
mA
Total Operating Current
Excluding Reference Current, VIN = 0 VDC
PD = Low (excluding reference current)
16
48
mA (max)
mW (max)
mW
Power Consumption (active)
Power Consumption (power down) PD = High (excluding reference current)
(1) All inputs are protected as shown below. Input voltage magnitudes up to 500 mV above the supply voltage or 500 mV below GND will
not damage this device. However, errors in the A/D conversion can occur if the input goes above VA or below AGND by more than 300
mV. As an example, if VA is 3.0 VDC, the full-scale input voltage must be ≤3.3 VDC to ensure accurate conversions.
(2) To ensure accuracy, it is required that VA and VD be well bypassed. Each VA and VD pin must be decoupled with separate bypass
capacitors.
(3) Typical figures are at TJ = 25°C, and represent most likely parametric norms. Test limits are ensured to TI's AOQL (Average Outgoing
Quality Level).
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Converter Electrical Characteristics (continued)
The following specifications apply for VA = VD = +3.0 VDC, VREF = 2.4V, VIN = 1.63 VP-P, OE = 0V, CL = 20 pF, fCLK = 42 MHz,
50% duty cycle, unless otherwise specified.
Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25°C(1)(2)
Units
(Limits)
Symbol
Parameter
Conditions
Typical(3) Limits(3)
CLK, OE Digital Input Characteristics
VIH
VIL
IIH
Logical High Input Voltage
Logical Low Input Voltage
Logical High Input Current
Logic Low Input Current
Logic Input Capacitance
VD = VA = 3V
VD = VA = 3V
2.0
V (min)
V (max)
µA
1.0
VIH = VD = VA = 3.3V
10
−10
10
IIL
VIL = 0V, VD = VA = 3.3V
µA
CIN
pF
Digital Output Characteristics
IOH High Level Output Current
IOL
VD = 2.7V, VOH = VD −0.5V
VD = 2.7V, OE = DGND, VOL = 0.4V
VD = 2.7V, IOH = −360 µA
−1.1
mA (min)
Low Level Output Current
High Level Output Voltage
Low Level Output Voltage
1.8
mA (min)
VOH
VOL
2.65
0.2
V
V
VD = 2.7V, IOL = 1.6 mA
IOZH
IOZL
,
TRI-STATE Output Current
OE = VD = 3.3V, VOH = 3.3V or VOL = 0V
±10
µA
AC Electrical Characteristics
fC1
fC2
tOD
Maximum Conversion Rate
42
MHz (min)
MHz
Minimum Conversion Rate
Output Delay
2
CLK High to Data Valid
14
2.5
2
19
ns (max)
Clock Cycles
ns
Pipline Delay (Latency)
Sampling (Aperture) Delay
Output Hold Time
tDS
tOH
tEN
tDIS
CLK Low to Acquisition of Data
CLK High to Data Invalid
9
ns
OE Low to Data Valid
OE High to High Z State
Loaded as in Figure 20
14
10
7.2
7.2
6.8
45
45
43
44
45
44
−57
−51
−46
57
54
49
ns
Loaded as in Figure 20
ns
fCLK = 30 MHz, fIN = 1 MHz
fCLK = 42 MHz, fIN = 4.4 MHz
fCLK = 42 MHz, fIN = 21 MHz
fCLK = 30 MHz, fIN = 1 MHz
fCLK = 42 MHz, fIN = 4.4 MHz
fCLK = 42 MHz, fIN = 21 MHz
fCLK = 30 MHz, fIN = 1 MHz
fCLK = 42 MHz, fIN = 4.4 MHz
fCLK = 42 MHz, fIN = 21 MHz
fCLK = 30 MHz, fIN = 1 MHz
fCLK = 42 MHz, fIN = 4.4 MHz
fCLK = 42 MHz, fIN = 21 MHz
fCLK = 30 MHz, fIN = 1 MHz
fCLK = 42 MHz, fIN = 4.4 MHz
fCLK = 42 MHz, fIN = 21 MHz
Bits
ENOB
SINAD
SNR
Effective Number of Bits
Signal-to-Noise & Distortion
Signal-to-Noise Ratio
Bits
6.1
38.5
41
Bits (min)
dB
dB
dB (min)
dB
dB
dB (min)
dB
THD
Total Harmonic Distortion
Spurious Free Dynamic Range
dB
−41
41
dB (min)
dB
SFDR
dB
dB (min)
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Typical Performance Characteristics
VA = VD = VD I/O = 3V, fCLK = 42 MHz, unless otherwise specified
DNL @ 42 MSPS
DNL vs Sample Rate
Figure 3.
Figure 4.
DNL vs VA
DNL vs Temperature
Figure 5.
Figure 6.
INL @ 42 MSPS
INL vs Sample Rate
Figure 7.
Figure 8.
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Typical Performance Characteristics (continued)
VA = VD = VD I/O = 3V, fCLK = 42 MHz, unless otherwise specified
INL vs VA
INL vs Temperature
Figure 9.
Figure 10.
SINAD and ENOB vs fIN
SINAD and ENOB vs fCLK
Figure 11.
Figure 12.
SNR vs fIN
SINAD and ENOB vs
Clock Duty Cycle
Figure 13.
Figure 14.
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Typical Performance Characteristics (continued)
VA = VD = VD I/O = 3V, fCLK = 42 MHz, unless otherwise specified
THD vs fIN
(ID) + (IA) vs fCLK
Figure 15.
tOD vs VD
Figure 16.
Spectral Response @ 42 MSPS
Figure 17.
Figure 18.
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Specification Definitions
ANALOG INPUT BANDWIDTH is a measure of the frequency at which the reconstructed output fundamental
drops 3 dB below its low frequency value for a full scale input. The test is performed with fIN equal to 100 kHz
plus integer multiples of fCLK. The input frequency at which the output is −3 dB relative to the low frequency input
signal is the full power bandwidth.
DIFFERENTIAL GAIN ERROR is the percentage difference between the output amplitudes of a high frequency
reconstructed sine wave at two different dc input levels.
DIFFERENTIAL NON-LINEARITY (DNL) is the measure of the maximum deviation from the ideal step size of 1
LSB.
DIFFERENTIAL PHASE ERROR is the difference in the output phase of a reconstructed small signal sine wave
at two different dc input levels.
EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE BITS) is another method of specifying Signal-to-Noise
and Distortion Ratio, or SINAD. ENOB is defined as (SINAD - 1.76)/6.02 and says that the converter is
equivalent to a perfect ADC of this (ENOB) number of bits.
FULL POWER BANDWIDTH is a measure of the frequency at which the reconstructed output fundamental
drops 3 dB below its low frequency value for a full scale input. The test is performed with fIN equal to 100KHz
plus integer multiples of fCLK The input frequency at which the output is —3 dB relative to the low frequency input
signal is the full power bandwidth.
FULL SCALE OFFSET ERROR is the difference between the analog input voltage that just causes the output
code to transition to the full scale code (all 1's in the case of the ADC08351) and the ideal value of 1½ LSB
below the value of VREF
.
INTEGRAL NON-LINEARITY (INL) is a measure of the deviation of each individual code from a line drawn from
zero scale (½ LSB below the first code transition) through positive full scale (½ LSB above the last code
transition). The deviation of any given code from this straight line is measured from the center of that code value.
The end point test method is used.
OUTPUT DELAY is the time delay after the rising edge of the input clock before the data update is present at the
output pins.
OUTPUT HOLD TIME is the length of time that the output data is valid after the rise of the input clock.
PIPELINE DELAY (LATENCY) is the number of clock cycles between initiation of conversion and the availability
of that conversion result at the output. New data is available at every clock cycle, but the data lags the
conversion by the pipeline delay.
SAMPLING (APERTURE) DELAY is that time required after the fall of the clock input for the sampling switch to
open. The sample is effectively taken this amount of time after the fall of the clock input.
SIGNAL TO NOISE RATIO (SNR) is the ratio of the rms value of the input signal to the rms value of the other
spectral components below one-half the sampling frequency, not including harmonics or dc.
SIGNAL TO NOISE PLUS DISTORTION (S/(N+D) or SINAD) is the ratio of the rms value of the input signal to
the rms value of all of the other spectral components below half the clock frequency, including harmonics but
excluding dc.
SPURIOUS FREE DYNAMIC RANGE (SFDR) is the difference, expressed in dB, between the rms values of the
input signal and the peak spurious signal, where a spurious signal is any signal present in the output spectrum
that is not present at the input.
TOTAL HARMONIC DISTORTION (THD) is the ratio of the rms total of the first six harmonic components to the
rms value of the input signal.
ZERO SCALE OFFSET ERROR is the difference between the analog input voltage that just causes the output
code to transition to the first code and the ideal value of ½ LSB for that transition.
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Timing Diagram
Figure 19. ADC08351 Timing Diagram
Figure 20. tEN, tDIS Test Circuit
FUNCTIONAL DESCRIPTION
The ADC08351 achieves 6.8 effective bits at 21 MHz input frequency with 42 MHz clock frequency digitizing to
eight bits the analog signal at VIN that is within the nominal voltage range of 0.5 VP-P to 0.68 VA.
Input voltages below 0.0665 times the reference voltage will cause the output word to consist of all zeroes, while
input voltages above ¾ of the reference voltage will cause the output word to consist of all ones. For example,
with a VREF of 2.4V, input voltages below 160 mV will result in an output word of all zeroes, while input voltages
above 1.79V will result in an output word of all ones.
The output word rate is the same as the clock frequency. Data is acquired at the falling edge of the clock and the
digital equivalent of that data is available at the digital outputs 2.5 clock cycles plus tOD later. The ADC08351 will
convert as long as the clock signal is present at the CLK pin, but the data will not appear at the outputs unless
the OE pin is low. The digital outputs are in the high impedance state when the OE pin or when the PD pin is
high.
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APPLICATIONS INFORMATION
(All schematic pin numbers refer to the TSSOP.)
THE ADC REFERENCE AND THE ANALOG INPUT
The capacitance seen at the input changes with the clock level, appearing as 4 pF when the clock is low, and 11
pF when the clock is high. Since a dynamic capacitance is more difficult to drive than is a fixed capacitance,
choose an amplifier that can drive this type of load. The CLC409, CLC440, LM6152, LM6154, LM6181 and
LM6182 are good devices for driving analog input of the ADC08351. Do not drive the input beyond the supply
rails.
The maximum peak-to-peak input level without clipping of the reconstructed output is determined by the values
of the resistor string between VREF and AGND. The bottom of the reference ladder has a voltage of 0.0665 times
VREF, while the top of the reference ladder has a voltage of 0.7468 times VREF. The maximum peak-to-peak input
level works out to be about 68% of the value of VREF. The relationship between the input peak-to-peak voltage
and VREF is
(1)
We do not recommend opertaing with input levels below 1 VP-P because the signal-to-noise ratio will degrade
considerably due to the quantization noise. However, the ADC08351 will give adequate results in many
applications with signal levels down to about 0.5 VP-P (VREF = 0.735V). Very good performance can be obtained
with reference voltages up to the supply voltage (VA = VREF = 3V, 2.04 VP-P).
As with all sampling ADCs, the opening and closing of the switches associated with the sampling causes an
output of energy from the analog input, VIN. The reference ladder also has switches associated with it, so the
reference source must be able to supply sufficient current to hold VREF steady.
The analog input of the ADC08351 is self-biased with an 18 kΩ pull-up resistor to VREF and a 12 kΩ pull-down
resistor to AGND. This allows for either a.c. or d.c. coupling of the input signal. These two resistors provide a
convenient way to ensure a signal that is less than full scale will be centered within the input common mode
range of the converter. However, the high values of these resistors and the energy coming from this input means
that performance will be improved with d.c. coupling.
The driving circuit at the signal input must be able to sink and source sufficient current at the signal frequency to
prevent distortion from being introduced at the input.
POWER SUPPLY CONSIDERATIONS
A tantalum or aluminum electrolytic capacitor of 5 µF to 10 µF should be placed within a centimeter of each of
the A/D power pins, with a 0.1 µF ceramic chip capacitor placed within ½ centimeter of each of the power pins.
Leadless chip capacitors are preferred because they provide lower lead inductance than do their leaded
counterparts.
While a single voltage source should be used for the analog and digital supplies of the ADC08351, these supply
pins should be decoupled from each other to prevent any digital noise from being coupled to the analog power
pins. A ferrite bead between the analog and digital supply pins would help to isolate the two supplies.
The converter digital supply should not be the supply that is used for other digital circuitry on the board. It should
be the same supply used for the A/D analog supply, decoupled from the A/D analog supply pin, as described
above. A common analog supply should be used for both VA and VD, and each of these pins should be
separately bypassed with a 0.1 µF ceramic capacitor and with low ESR a 10 µF capacitor.
As is the case with all high speed converters, the ADC08351 is sensitive to power supply noise. Accordingly, the
noise on the analog supply pin should be minimized, keeping it below 200 mVP-P at 100 kHz. Of course, higher
frequency noise on the power supply should be even more severely limited.
No pin should ever have a voltage on it that is in excess of the supply voltages. This can be a problem upon
application of power to a circuit. Be sure that the supplies to circuits driving the CLK, OE, analog input and
reference pins do not come up any faster than does the voltage at the ADC08351 power pins.
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LAYOUT AND GROUNDING
Proper grounding and proper routing of all signals is essential to ensure accurate conversion. Separate analog
and digital ground planes that are connected beneath the ADC08351 are required to meet data sheet limits. The
analog and digital grounds may be in the same layer, but should be separated from each other and should never
overlap each other.
Capacitive coupling between the typically noisy digital ground plane and the sensitive analog circuitry can lead to
poor performance that may seem impossible to isolate and remedy. The solution is to keep the analog circuitry
well separated from the digital circuitry and from the digital ground plane.
The back of the WQFN package has a large metal area inside the area bounded by the pins. This metal area is
connected to the die substrate (ground). This pad may be left floating if desired. If it is connected to anything, it
should be to ground near the connection between analog and digital ground planes. Soldering this metal pad to
ground will help keep the die cooler and could yield improved performance because of the lower impedance
between die and board grounds. However, a poor layout could compromise performance.
Figure 21. Layout examples showing separate analog and digital ground planes connected below the
ADC08351.
Generally, analog and digital lines should cross each other at 90 degrees to avoid getting digital noise into the
analog path. To maximize accuracy in video (high frequency) systems, however, avoid crossing analog and
digital lines altogether. Furthermore, it is important to keep any clock lines isolated from ALL other lines, including
other digital lines. Even the generally accepted 90 degree crossing should be avoided as even a little coupling
can cause problems at high frequencies.
Best performance at high frequencies and at high resolution is obtained with a straight signal path. That is, the
signal path through all components should form a straight line wherever possible.
Be especially careful with the layout of inductors. Mutual inductance can change the characteristics of the circuit
in which they are used. Inductors should not be placed side by side, even with just a small part of their bodies
beside each other.
The analog input should be isolated from noisy signal traces to avoid coupling of spurious signals into the input.
Any external component (e.g., a filter capacitor) connected between the converter's input and ground should be
connected to a very clean point in the analog ground plane.
Figure 21 gives an example of a suitable layout. All analog circuitry (input amplifiers, filters, reference
components, etc.) should be placed on or over the analog ground plane. All digital circuitry and I/O lines should
be placed over the digital ground plane.
All ground connections should have a low inductance path to ground.
DYNAMIC PERFORMANCE
The ADC08351 is ac tested and its dynamic performance is ensured. To meet the published specifications, the
clock source driving the CLK input must be free of jitter. For best ac performance, isolating the ADC clock from
any digital circuitry should be done with adequate buffers, as with a clock tree. See Figure 22.
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It is good practice to keep the ADC clock line as short as possible and to keep it well away from any other
signals. Other signals can introduce jitter into the clock signal. Even lines with 90° crossings have capacitive
coupling, so try to avoid even these 90° crossings of the clock line.
Figure 22. Isolating the ADC Clock from Digital Circuitry
Digital circuits create substantial supply and ground current transients. The logic noise thus generated could
have significant impact upon system noise performance. The best logic family to use in systems with A/D
converters is one which employs non-saturating transistor designs, or has low noise characteristics, such as the
74HC(T) and 74AC(T)Q families. The worst noise generators are logic families that draw the largest supply
current transients during clock or signal edges, like the 74F and the 74AC(T) families. In general, slower logic
families, such as 74LS and 74HC(T) will produce less high frequency noise than do high speed logic families,
such as the 74F and 74AC(T) families.
Since digital switching transients are composed largely of high frequency components, total ground plane copper
weight will have little effect upon the logic-generated noise. This is because of the skin effect. Total surface area
is more important than is total ground plane volume.
An effective way to control ground noise is by connecting the analog and digital ground planes together beneath
the ADC with a copper trace that is narrow compared with the rest of the ground plane. This narrowing beneath
the converter provides a fairly high impedance to the high frequency components of the digital switching currents,
directing them away from the analog pins. The relatively lower frequency analog ground currents do not create a
significant variation across the impedance of this relatively narrow ground connection.
TYPICAL APPLICATION CIRCUITS
Figure 23 shows a simple interface for a low impedance source located close to the converter. As discussed in
The ADC Reference and The Analog Input, the series capacitor is optional. Notice the isolation of the ADC clock
signal from the clock signals going elsewhere in the system. The reference input of this circuit is shown
connected to the 3V supply.
Video ADCs tend to have input current transients that can upset a driving source, causing distortion of the driving
signal. The resistor at the ADC08351 input isolates the amplifier's output from the current transients at the input
to the converter.
When the signal source is not located close to the converter, the signal should be buffered. Figure 24 shows an
example of an appropriate buffer. The amplifier provides a gain of two to compensate for transmission losses.
Operational amplifiers have better linearity when they operate with gain, so the input is attenuated with the 68Ω
and 30Ω resistors at the non-inverting input. The 330Ω resistor in parallel with these two resistors provides for a
75Ω cable termination. Replacing this 330Ω resistor with one of 100Ω will provide a 50Ω termination.
The circuit shown has a nominal gain of two. You can provide a gain adjustment by changing the 110Ω feedback
resistor to a 100Ω resistor in series with a 20Ω potentiometer.
The offset adjustment is used to bring the input signal within the common mode range of the converter. If a fixed
offset is desired, the potentiometer and the 3.3k resistor may be replaced with a single resistor of 3k to 4k to the
appropriate supply. The resistor value and the supply polarity used will depend upon the amount and polarity of
offset needed.
The CLC409 shown in Figure 24 was chosen for a low cost solution with good overall performance.
14
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Figure 25 shows an inverting DC coupled circuit. The above comments regarding Figure 24 generally apply to
this circuit as well.
Figure 23. AC Coupled Circuit for a Low Impedance Source Located Near the Converter
Figure 24. Non-inverting Input Circuit for Remote Signal Source
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Figure 25. Inverting Circuit with Bias Adjust
ACCURATELY EVALUATING THE ADC
If a signal that is spectrally impure is presented to the ADC, the output from the ADC cannot be pure. Nearly all
signal generators in use today produce signals that are not spectrally pure enough to adequately evaluate
present-day ADCs. This is especially true at higher frequencies and at high resolutions.
To ensure that the signal you are presenting to the ADC being evaluated is spectrally pure, use a bandpass filter
between the signal generator and the ADC input. One such possible filter is the elliptic filter shown in Figure 26.
This elliptic filter has a cutoff frequency of about 11MHz and is suitable for input frequencies of 5MHz to 10MHz. It
should be driven by a generator of 75Ω source impedance and teminated with 75Ω. This termination may be provided
by the ADC evaluation circuit.
Figure 26. Elliptic Filter
In addition to being used to eliminate undesired frequencies from a desired signal, this filter can be used to filter
a square wave, reducing 3rd and higher harmonics to negligible levels.
When evaluating dynamic performance of an ADC, repeatability of measurements could be a problem unless
coherent sampling is used.
and ADC08351 evaluation system is available that can simplify evaluation of this product.
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COMMON APPLICATION PITFALLS
Driving the inputs (analog or digital) beyond the power supply rails. For proper operation, all inputs should
not go more than 300 mV beyond the supply rails. That is, more than 300 mV below the ground pins or 300 mV
above the supply pins. Exceeding these limits on even a transient basis may cause faulty or erratic operation. It
is not uncommon for high speed digital circuits (e.g., 74F and 74AC devices) to exhibit undershoot that goes
more than a volt below ground or above the power supply. Since these conditions are of very short duration with
very fast rise and fall times, they can inject noise into the system and may be difficult to detect with an
oscilloscope. A resistor of about 50Ω to 100Ω in series with the offending digital input will usually eliminate the
problem.
Care should be taken not to overdrive the inputs of the ADC08351 (or any device) with a device that is powered
from supplies outside the range of the ADC08351 supply. Such practice may lead to conversion inaccuracies and
even to device damage.
Attempting to drive a high capacitance digital data bus. The more capacitance the output drivers have to
charge for each conversion, the more instantaneous digital current is required from VD and DGND. These large
charging current spikes can couple into the analog section, degrading dynamic performance. While adequate
bypassing and maintaining separate analog and digital ground planes will reduce this problem on the board, this
coupling can still occur on the ADC08351 die. Buffering the digital data outputs (with a 74ACQ541, for example)
may be necessary if the data bus to be driven is heavily loaded.
Dynamic performance can also be improved by adding series resistors at each digital output, reducing the
energy coupled back into the converter output pins by limiting the output slew rate. A reasonable value for these
resistors is about 47Ω.
Using an inadequate amplifier to drive the analog input. As explained in Power Supply Considerations, the
capacitance seen at the input alternates between 4 pF and 11 pF with the clock. This dynamic capacitance is
more difficult to drive than a fixed capacitance, so care should be taken in choosing a driving device. The
CLC409, CLC440, LM6152, LM6154, LM6181 and LM6182 are good devices for driving the ADC08351. Also, an
amplifier with insufficient gain-bandwidth may limit the overall frequency response of the overall circuit.
Using an operational amplifier in an insufficient gain configuration to drive the analog input. Operational
amplifiers, while some may be unity gain stable, generally exhibit more distortion at low in-circuit gains than at
higher gains.
Using a clock source with excessive jitter, using excessively long clock signal trace, or having other
signals coupled to the clock signal trace. This will cause the sampling interval to vary, causing excessive
output noise and a reduction in SNR performance. Simple gates with RC timing is generally inadequate.
Not considering the timing relationships, especially tOD. Timing is always important and gets more critical
with higher speeds. If the output data is latched or looked at when that data is in transition, you may see
excessive noise and distortion of the output signal.
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REVISION HISTORY
Changes from Revision D (March 2013) to Revision E
Page
•
Changed layout of National Data Sheet to TI format .......................................................................................................... 17
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
ADC08351CILQX/NOPB
ADC08351CIMTCX/NOPB
ACTIVE
ACTIVE
WQFN
NHW
PW
24
20
4500 RoHS & Green
2500 RoHS & Green
SN
Level-3-260C-168 HR
Level-1-260C-UNLIM
-40 to 85
-40 to 85
08351
TSSOP
SN
ADC08351
CIMTC
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
ADC08351CILQX/NOPB WQFN
ADC08351CIMTCX/NOPB TSSOP
NHW
PW
24
20
4500
2500
330.0
330.0
12.4
16.4
4.3
5.3
7.1
1.3
1.6
8.0
8.0
12.0
16.0
Q1
Q1
6.95
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
ADC08351CILQX/NOPB
ADC08351CIMTCX/NOPB
WQFN
NHW
PW
24
20
4500
2500
356.0
367.0
356.0
367.0
35.0
35.0
TSSOP
Pack Materials-Page 2
PACKAGE OUTLINE
PW0020A
TSSOP - 1.2 mm max height
S
C
A
L
E
2
.
5
0
0
SMALL OUTLINE PACKAGE
SEATING
PLANE
C
6.6
6.2
TYP
A
0.1 C
PIN 1 INDEX AREA
18X 0.65
20
1
2X
5.85
6.6
6.4
NOTE 3
10
B
11
0.30
20X
4.5
4.3
NOTE 4
0.19
1.2 MAX
0.1
C A B
(0.15) TYP
SEE DETAIL A
0.25
GAGE PLANE
0.15
0.05
0.75
0.50
A
20
0 -8
DETAIL A
TYPICAL
4220206/A 02/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.
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EXAMPLE BOARD LAYOUT
PW0020A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
SYMM
20X (1.5)
(R0.05) TYP
20
1
20X (0.45)
SYMM
18X (0.65)
11
10
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
15.000
(PREFERRED)
SOLDER MASK DETAILS
4220206/A 02/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
PW0020A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
20X (1.5)
SYMM
(R0.05) TYP
20
1
20X (0.45)
SYMM
18X (0.65)
10
11
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
4220206/A 02/2017
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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MECHANICAL DATA
NHW0024B
LQA24A (Rev B)
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IC 1-CH 8-BIT RESISTANCE LADDER ADC, PARALLEL ACCESS, PDSO20, TSSOP-20, Analog to Digital Converter
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