ADC08500 [TI]
8 位、500MSPS 模数转换器 (ADC);
| 型号： | ADC08500 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 8 位、500MSPS 模数转换器 (ADC) 转换器 模数转换器 |
| 文件： | 总46页 (文件大小：956K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ADC08500
www.ti.com
SNAS373E –MAY 2007–REVISED APRIL 2013
ADC08500 High Performance, Low Power 8-Bit, 500 MSPS A/D Converter
Check for Samples: ADC08500
1
FEATURES
DESCRIPTION
The ADC08500 is a low power, high performance
CMOS analog-to-digital converter that digitizes
signals to 8 bits resolution at sampling rates up to
500 MSPS. Consuming a typical 0.8 Watts at 500
MSPS from a single 1.9 Volt supply, this device is
ensured to have no missing codes over the full
operating temperature range. The unique folding and
interpolating architecture, the fully differential
comparator design, the innovative design of the
internal sample-and-hold amplifier and the self-
calibration scheme enable a very flat response of all
dynamic parameters beyond Nyquist, producing a
high 7.5 ENOB with a 250 MHz input signal and a
500 MHz sample rate while providing a 10-18 B.E.R.
Output formatting is offset binary and the LVDS
digital outputs are compatible with IEEE 1596.3-1996,
with the exception of an adjustable common mode
voltage between 0.8V and 1.2V.
2
•
•
•
•
•
•
•
Internal Sample-and-Hold
Single +1.9V ±0.1V Operation
Choice of SDR or DDR Output Clocking
Multiple ADC Synchronization Capability
Ensured No Missing Codes
Serial Interface for Extended Control
Fine Adjustment of Input Full-Scale Range and
Offset
•
Duty Cycle Corrected Sample Clock
APPLICATIONS
•
•
•
•
•
Direct RF Down Conversion
Digital Oscilloscopes
Satellite Set-top Boxes
Communications Systems
Test Instrumentation
The converter has a 1:2 demultiplexer that feeds two
LVDS buses and reduces the output data rate on
each bus to half the sampling rate.
KEY SPECIFICATIONS
The converter typically consumes less than 3.5 mW
in the Power Down Mode and is available in a 128-
lead, thermally enhanced exposed pad HLQFP and
operates over the Industrial (-40°C ≤ TA ≤ +85°C)
temperature range.
•
•
•
•
•
•
Resolution 8 Bits
Max Conversion Rate 500 MSPS (min)
Bit Error Rate 10-18 (typ)
ENOB @ 250 MHz Input 7.5 Bits (typ)
DNL ±0.15 LSB (typ)
Power Consumption
–
–
Operating 0.8 W (typ)
Power Down Mode 3.5 mW (typ)
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007–2013, Texas Instruments Incorporated
ADC08500
SNAS373E –MAY 2007–REVISED APRIL 2013
www.ti.com
Block Diagram
V
V
+
+
-
IN
S/H
D
OUT
1:2 DEMUX
& LATCH
-
8-BIT
ADC
IN
Data Bus Output
16 LVDS Pairs
D
OUTD
V
BG
V
REF
CLK+
CLK-
Output
Clock
Generator
DCLK+
DCLK-
CLK/2
2
Control
Inputs
OR
Control
Logic
CalRun
Serial
Interface
3
Figure 1.
2
Submit Documentation Feedback
Copyright © 2007–2013, Texas Instruments Incorporated
Product Folder Links: ADC08500
ADC08500
www.ti.com
SNAS373E –MAY 2007–REVISED APRIL 2013
Pin Configuration
D2+
96
GND
1
2
3
4
5
6
7
8
V
A
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
D2-
D3+
D3-
D4+
D4-
D5+
D5-
OUTV/SCLK
OutEdge/DDR/SDATA
V
A
GND
V
CMO
V
A
V
DR
GND
9
V
-
IN
DR GND
D6+
D6-
D7+
D7-
DCLK+
DCLK-
OR-
OR+
NC
10
11
12
V
+
IN
GND
V
A
13
14
15
16
17
18
19
20
FSR/ECE
DCLK_RST
V
A
V
A
ADC08500
CLK+
CLK-
V
NC
NC
NC
DR GND
A
GND 21
NC
NC
23
GND
22
*
V
DR
24
25
26
27
28
29
30
31
32
V
A
NC
NC
NC
NC
NC
NC
NC
NC
PD
GND
V
A
NC
CAL
V
BG
R
EXT
* Exposed pad on back of package must be soldered to ground plane to ensure rated performance.
Figure 2. 128-Lead HLQFP
See NNB0128A Package
Copyright © 2007–2013, Texas Instruments Incorporated
Submit Documentation Feedback
3
Product Folder Links: ADC08500
ADC08500
SNAS373E –MAY 2007–REVISED APRIL 2013
www.ti.com
PIN DESCRIPTIONS AND EQUIVALENT CIRCUITS
Pin Functions
Pin No.
Symbol
Equivalent Circuit
Description
V
A
Output Voltage Amplitude and Serial Interface Clock. Tie this
pin high for normal differential DCLK and data amplitude.
Ground this pin for a reduced differential output amplitude and
reduced power consumption. See The LVDS Outputs. When
the extended control mode is enabled, this pin functions as the
SCLK input which clocks in the serial data. See
50k
3
OutV / SCLK
NORMAL/EXTENDED CONTROL for details on the extended
control mode. See THE SERIAL INTERFACE for description of
the serial interface.
GND
V
A
DCLK Edge Select, Double Data Rate Enable and Serial Data
Input. This input sets the output edge of DCLK+ at which the
output data transitions. When this pin is floating or connected to
1/2 the supply voltage, DDR clocking is enabled. See Double
Data Rate. When the extended control mode is enabled, this
pin functions as the SDATA input. See NORMAL/EXTENDED
CONTROL for details on the extended control mode. See THE
SERIAL INTERFACE for description of the serial interface.
50k
50k
200k
8 pF
DDR
OutEdge / DDR /
SDATA
4
GND
SDATA
V
A
DCLK Reset. A positive pulse on this pin is used to reset and
synchronize the DCLK outs of multiple converters. See
MULTIPLE ADC SYNCHRONIZATION for detailed description.
15
26
DCLK_RST
PD
V
A
Power Down Pin. A logic high on the PD pin puts the entire
device into the Power Down Mode.
Calibration Cycle Initiate. A minimum tCAL_L input clock cycles
logic low followed by a minimum of tCAL_H input clock cycles
high on this pin initiates the self calibration sequence. See Self
Calibration for an overview of self-calibration and On-Command
Calibration for a description of on-command calibration.
30
CAL
GND
Full Scale Range Select and Extended Control Enable. In non-
extended control mode, a logic low on this pin sets the full-scale
differential input range to a reduced VIN input level . A logic high
on this pin sets the full-scale differential input range to a higher
VIN input level. See Converter Electrical Characteristics. To
enable the extended control mode, whereby the serial interface
and control registers are employed, allow this pin to float or
connect it to a voltage equal to VA/2. See
V
A
50k
50k
200k
8 pF
14
FSR/ECE
NORMAL/EXTENDED CONTROL for information on the
extended control mode.
GND
V
A
Calibration Delay and Serial Interface Chip Select. With a logic
high or low on pin 14, this pin functions as Calibration Delay
and sets the number of clock cycles after power up before
calibration begins. See Self-Calibration. With pin 14 floating,
this pin acts as the enable pin for the serial interface input and
the CalDly value becomes "0" (short delay with no provision for
a long power-up calibration delay).
50k
50k
127
CalDly / SCS
GND
4
Submit Documentation Feedback
Copyright © 2007–2013, Texas Instruments Incorporated
Product Folder Links: ADC08500
ADC08500
www.ti.com
SNAS373E –MAY 2007–REVISED APRIL 2013
PIN DESCRIPTIONS AND EQUIVALENT CIRCUITS (continued)
Pin Functions
Pin No.
Symbol
Equivalent Circuit
Description
V
A
LVDS Clock input pins for the ADC. The differential clock signal
must be a.c. coupled to these pins. The input signal is sampled
on the falling edge of CLK+. See Acquiring the Input for a
description of acquiring the input and THE CLOCK INPUTS for
an overview of the clock inputs.
18
19
CLK+
CLK-
50k
50k
AGND
100
V
BIAS
V
A
AGND
V
A
50k
Analog signal inputs to the ADC. The differential full-scale input
range of this input is programmable using the FSR pin 14 in
normal mode and the Input Full-Scale Voltage Adjust register in
the extended control mode. Refer to the VIN specification in the
Converter Electrical Characteristics for the full-scale input range
in the normal mode. Refer to REGISTER DESCRIPTION for the
full-scale input range in the extended control mode.
AGND
100
V
CMO
11
10
VIN
+
Control from V
CMO
VIN−
V
A
50k
AGND
V
A
V
CMO
Common Mode Voltage. This pin is the common mode output in
d.c. coupling mode and also serves as the a.c. coupling mode
select pin. When d.c. coupling is used, the voltage output at this
pin is required to be the common mode input voltage at VIN
and VIN− when d.c. coupling is used. This pin should be
grounded when a.c. coupling is used at the analog inputs. This
pin is capable of sourcing or sinking 100 μA. See THE
ANALOG INPUT.
+
200k
7
VCMO
Enable AC
Coupling
8 pF
GND
V
A
31
VBG
Bandgap output voltage capable of 100 μA source/sink.
Calibration Running indication. This pin is at a logic high when
calibration is running.
126
CalRun
GND
Copyright © 2007–2013, Texas Instruments Incorporated
Submit Documentation Feedback
5
Product Folder Links: ADC08500
ADC08500
SNAS373E –MAY 2007–REVISED APRIL 2013
www.ti.com
PIN DESCRIPTIONS AND EQUIVALENT CIRCUITS (continued)
Pin Functions
Pin No.
Symbol
Equivalent Circuit
Description
V
A
External bias resistor connection.
V
32
REXT
Nominal value is 3.3 kOhms (±0.1%) to ground. See Self-
Calibration.
GND
Temperature Diode Positive (Anode) and Negative (Cathode).
These pins may be used for die temperature measurements,
however no specified accuracy is implied or ensured. See
Thermal Management.
Tdiode_P
Tdiode_N
34
35
Tdiode_P
Tdiode_N
83
84
85
86
89
90
91
92
93
94
95
96
100
101
102
103
D7-
D7+
D6-
D6+
D5-
D5+
D4-
D4+
D3-
D3+
D2-
D2+
D1-
D1+
D0-
D0+
Input channel LVDS Data Outputs that are not delayed in the
output demultiplexer. Compared with the Dd outputs, these
outputs represent the later time samples. These outputs should
always be terminated with a 100Ω differential resistor.
VDR
-
+
-
104
105
106
107
111
112
113
114
115
116
117
118
122
123
124
125
Dd7-
Dd7+
Dd6-
Dd6+
Dd5-
Dd5+
Dd4-
Dd4+
Dd3-
Dd3+
Dd2-
Dd2+
Dd1-
Dd1+
Dd0-
Dd0+
+
Input channel LVDS Data Outputs that are delayed by one CLK
cycle in the output demultiplexer. Compared with the D outputs,
these outputs represent the earlier time sample. These outputs
should always be terminated with a 100Ω differential resistor.
DR GND
6
Submit Documentation Feedback
Copyright © 2007–2013, Texas Instruments Incorporated
Product Folder Links: ADC08500
ADC08500
www.ti.com
SNAS373E –MAY 2007–REVISED APRIL 2013
PIN DESCRIPTIONS AND EQUIVALENT CIRCUITS (continued)
Pin Functions
Pin No.
Symbol
Equivalent Circuit
Description
Out Of Range output. A differential high at these pins indicates
that the differential input is out of range (outside the range
±VIN/2 as programmed by the FSR pin in non-extended control
mode or the Input Full-Scale Voltage Adjust register setting in
the extended control mode).
VDR
79
80
OR+
OR-
-
+
-
Differential Clock outputs used to latch the output data. Delayed
and non-delayed data outputs are supplied synchronous to this
signal. This signal is at 1/2 the input clock rate in SDR mode
and at 1/4 the input clock rate in the DDR mode. The DCLK
outputs are not active during a calibration cycle, therefore this is
not recommended as a system clock.
82
81
DCLK+
DCLK-
+
DR GND
2, 5, 8, 13,
16, 17, 20,
25, 28, 33,
128
VA
Analog power supply pins. Bypass these pins to ground.
40, 51 ,62,
73, 88, 99,
110, 121
Output Driver power supply pins. Bypass these pins to DR
GND.
VDR
GND
1, 6, 9, 12,
21, 24, 27,
41
Ground return for VA.
42, 53, 64,
74, 87, 97,
108, 119
DR GND
Ground return for VDR.
22, 23, 29,
36–39,
43–50, 52,
54–61, 63,
65–72,
NC
No Connection. Make no connection to these pins.
75–78, 98,
109, 120
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Copyright © 2007–2013, Texas Instruments Incorporated
Submit Documentation Feedback
7
Product Folder Links: ADC08500
ADC08500
SNAS373E –MAY 2007–REVISED APRIL 2013
www.ti.com
(1)(2)(3)
Absolute Maximum Ratings
Supply Voltage (VA, VDR
)
2.2V
0V to 100 mV
−0.15V to (VA +0.15V)
-0.15V to 2.5V
0V to 100 mV
±25 mA
Supply Difference VDR - VA
Voltage on Any Input Pin (Except VIN+, VIN- )
Voltage on VIN+, VIN- (Maintaining Common Mode)
Ground Difference |GND - DR GND|
(4)
Input Current at Any Pin
(4)
Package Input Current
±50 mA
Power Dissipation at TA = 85°C
2.0 W
(5)
ESD Susceptibility
Human Body Model
Machine Model
2500V
250V
Storage Temperature
−65°C to +150°C
(1) All voltages are measured with respect to GND = DR GND = 0V, unless otherwise specified.
(2) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.
(3) If Military/Aerospace specified devices are required, please contact the TI Sales Office/Distributors for availability and specifications.
(4) When the input voltage at any pin exceeds the power supply limits (that is, less than GND or greater than VA), the current at that pin
should be limited to 25 mA. The 50 mA maximum package input current rating limits the number of pins that can safely exceed the
power supplies with an input current of 25 mA to two. This limit is not placed upon the power, ground and digital output pins.
(5) Human body model is 100 pF capacitor discharged through a 1.5 kΩ resistor. Machine model is 220 pF discharged through ZERO
Ohms.
(1)(2)
Operating Ratings
Ambient Temperature Range
−40°C ≤ TA ≤ +85°C
+1.8V to +2.0V
+1.8V to VA
Supply Voltage (VA)
Driver Supply Voltage (VDR
)
Analog Input Common Mode Voltage
VCMO ±50 mV
VIN+, VIN- Voltage Range (Maintaining Common Mode)
0V to 2.15V
(100% duty cycle)
0V to 2.5V
(10% duty cycle)
Ground Difference (|GND - DR GND|)
CLK Pins Voltage Range
0V
0V to VA
Differential CLK Amplitude
0.4VP-P to 2.0VP-P
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.
(2) All voltages are measured with respect to GND = DR GND = 0V, unless otherwise specified.
Package Thermal Resistance(1)
Package
θJA
θJC (Top of Package)
θJ-PAD (Thermal Pad)
128-Lead Exposed Pad
HLQFP
25°C / W
10°C / W
2.8°C / W
(1) Soldering process must comply with TI's Reflow Temperature Profile specifications. Refer to www.TI.com/packaging.
Reflow temperature profiles are different for lead-free and non-lead-free packages.
8
Submit Documentation Feedback
Copyright © 2007–2013, Texas Instruments Incorporated
Product Folder Links: ADC08500
ADC08500
www.ti.com
SNAS373E –MAY 2007–REVISED APRIL 2013
Converter Electrical Characteristics
The following specifications apply after calibration for VA = VDR = +1.9VDC, OutV = 1.9V, VIN FSR (a.c. coupled) = differential
870 mVP-P, CL = 10 pF, Differential, a.c. coupled Sinewave Input Clock, fCLK = 500 MHz at 0.5VP-P with 50% duty cycle,
VBG = Floating, Non-Extended Control Mode, SDR Mode, REXT = 3300Ω ±0.1%, Analog Signal Source Impedance = 100Ω
(1)(2)
Differential. Boldface limits apply for TA = TMIN to TMAX. All other limits TA = 25°C, unless otherwise noted. See
Units
(Limits)
(3)
(3)
Symbol
Parameter
Conditions
Typical
Limits
STATIC CONVERTER CHARACTERISTICS
DC Coupled, 1MHz Sine Wave
OverRanged
INL
Integral Non-Linearity
±0.3
±0.9
LSB (max)
DC Coupled, 1MHz Sine Wave Over
Ranged
DNL
Differential Non-Linearity
Resolution with No Missing Codes
Offset Error
±0.15
±0.6
8
LSB (max)
Bits
−1.5
0.5
LSB (min)
LSB (max)
VOFF
-0.5
±45
VOFF_ADJ Input Offset Adjustment Range
Extended Control Mode
Extended Control Mode
mV
(4)
PFSE
Positive Full-Scale Error
Negative Full-Scale Error
±25
±25
±15
mV (max)
mV (max)
%FS
(4)
NFSE
FS_ADJ
Full-Scale Adjustment Range
±20
DYNAMIC CONVERTER CHARACTERISTICS
FPBW
B.E.R.
Full Power Bandwidth
Bit Error Rate
1.7
10-18
±0.5
7.5
7.5
7.5
47
GHz
Error/Sample
dBFS
Gain Flatness
d.c. to 500 MHz
fIN = 50 MHz, VIN = FSR − 0.5 dB
fIN = 124 MHz, VIN = FSR − 0.5 dB
fIN = 248 MHz, VIN = FSR − 0.5 dB
fIN = 50 MHz, VIN = FSR − 0.5 dB
fIN = 124 MHz, VIN = FSR − 0.5 dB
fIN = 248 MHz, VIN = FSR − 0.5 dB
fIN = 50 MHz, VIN = FSR − 0.5 dB
fIN = 124 MHz, VIN = FSR − 0.5 dB
fIN = 248 MHz, VIN = FSR − 0.5 dB
fIN = 50 MHz, VIN = FSR − 0.5 dB
fIN = 124 MHz, VIN = FSR − 0.5 dB
fIN = 248 MHz, VIN = FSR − 0.5 dB
Bits
ENOB
SINAD
SNR
Effective Number of Bits
7.1
7.1
Bits (min)
Bits (min)
dB
Signal-to-Noise Plus Distortion Ratio
Signal-to-Noise Ratio
47
44.5
44.5
dB (min)
dB (min)
dB
47
48
47.5
47.5
-55
-56
-56
45.3
45.3
dB (min)
dB (min)
dB
THD
Total Harmonic Distortion
−47.5
−47.5
dB (max)
dB (max)
(1) The analog inputs are protected as shown below. Input voltage magnitudes beyond the Absolute Maximum Ratings may damage this
device.
V
A
TO INTERNAL
CIRCUITRY
I / O
GND
(2) To ensure accuracy, it is required that VA and VDR be well bypassed. Each supply pin must be decoupled with separate bypass
capacitors. Additionally, achieving rated performance requires that the backside exposed pad be well grounded.
(3) Typical figures are at TA = 25°C, and represent most likely parametric norms. Test limits are specified to TI's AOQL (Average Outgoing
Quality Level).
(4) Calculation of Full-Scale Error for this device assumes that the actual reference voltage is exactly its nominal value. Full-Scale Error for
this device, therefore, is a combination of Full-Scale Error and Reference Voltage Error. See Transfer Characteristic Figure 4. For
relationship between Gain Error and Full-Scale Error, see Specification Definitions for Gain Error.
Copyright © 2007–2013, Texas Instruments Incorporated
Submit Documentation Feedback
9
Product Folder Links: ADC08500
ADC08500
SNAS373E –MAY 2007–REVISED APRIL 2013
www.ti.com
Converter Electrical Characteristics (continued)
The following specifications apply after calibration for VA = VDR = +1.9VDC, OutV = 1.9V, VIN FSR (a.c. coupled) = differential
870 mVP-P, CL = 10 pF, Differential, a.c. coupled Sinewave Input Clock, fCLK = 500 MHz at 0.5VP-P with 50% duty cycle,
VBG = Floating, Non-Extended Control Mode, SDR Mode, REXT = 3300Ω ±0.1%, Analog Signal Source Impedance = 100Ω
Differential. Boldface limits apply for TA = TMIN to TMAX. All other limits TA = 25°C, unless otherwise noted. See (1)(2)
Units
(Limits)
(3)
(3)
Symbol
Parameter
Conditions
Typical
Limits
fIN = 50 MHz, VIN = FSR − 0.5 dB
fIN = 124 MHz, VIN = FSR − 0.5 dB
fIN = 248 MHz, VIN = FSR − 0.5 dB
fIN = 50 MHz, VIN = FSR − 0.5 dB
fIN = 124 MHz, VIN = FSR − 0.5 dB
fIN = 248 MHz, VIN = FSR − 0.5 dB
fIN = 50 MHz, VIN = FSR − 0.5 dB
fIN = 124 MHz, VIN = FSR − 0.5 dB
fIN = 248 MHz, VIN = FSR − 0.5 dB
−60
−60
−60
−65
−65
−65
55
dB
2nd Harm Second Harmonic Distortion
dB
dB
dB
3rd Harm
Third Harmonic Distortion
dB
dB
dB
SFDR
IMD
Spurious-Free dynamic Range
Intermodulation Distortion
56
47.5
47.5
dB (min)
dB (min)
56
fIN1 = 121 MHz, VIN = FSR − 7 dB
fIN2 = 126 MHz, VIN = FSR − 7 dB
-50
dB
(VIN+) − (VIN−) > + Full Scale
(VIN+) − (VIN−) < − Full Scale
255
0
Out of Range Output Code
(In addition to OR Output high)
ANALOG INPUT AND REFERENCE CHARACTERISTICS
570
730
790
950
mVP-P (min)
mVP-P (max)
mVP-P (min)
mVP-P (max)
FSR pin 14 Low
650
Full Scale Analog Differential Input
Range
VIN
FSR pin 14 High
870
V
CMO − 50
mV (min)
mV (max)
VCMI
CIN
Analog Input Common Mode Voltage
Analog Input Capacitance, Normal
VCMO
VCMO + 50
Differential
0.02
1.6
pF
pF
(5)(6)
operation
Each input pin to ground
94
Ω (min)
Ω (max)
RIN
Differential Input Resistance
100
106
ANALOG OUTPUT CHARACTERISTICS
0.95
1.45
V (min)
V (max)
VCMO
Common Mode Output Voltage
ICMO = ±100 µA
1.26
VA = 1.8V
VA = 2.0V
0.60
0.66
V
V
VCMO input threshold to set DC
Coupling mode
VCMO_LVL
TC VCMO
Common Mode Output Voltage
Temperature Coefficient
TA = −40°C to +85°C
118
ppm/°C
pF
CLOAD
VCMO
Maximum VCMO load Capacitance
Bandgap Reference Output Voltage
80
1.20
1.33
V (min)
V (max)
VBG
IBG = ±100 µA
1.26
28
Bandgap Reference Voltage
Temperature Coefficient
TA = −40°C to +85°C
IBG = ±100 µA
TC VBG
CLOAD VBG
ppm/°C
pF
Maximum Bandgap Reference Load
Capacitance
80
TEMPERATURE DIODE CHARACTERISTICS
192 µA vs. 12 µA,
TJ = 25°C
71.23
85.54
mV
mV
ΔVBE
Temperature Diode Voltage
192 µA vs. 12 µA,
TJ = 85°C
(5) The analog and clock input capacitances are die capacitances only. Additional package capacitances of 0.65 pF differential and 0.95 pF
each pin to ground are isolated from the die capacitances by lead and bond wire inductances.
(6) This parameter is specified by design and is not tested in production.
10
Submit Documentation Feedback
Copyright © 2007–2013, Texas Instruments Incorporated
Product Folder Links: ADC08500
ADC08500
www.ti.com
SNAS373E –MAY 2007–REVISED APRIL 2013
Converter Electrical Characteristics (continued)
The following specifications apply after calibration for VA = VDR = +1.9VDC, OutV = 1.9V, VIN FSR (a.c. coupled) = differential
870 mVP-P, CL = 10 pF, Differential, a.c. coupled Sinewave Input Clock, fCLK = 500 MHz at 0.5VP-P with 50% duty cycle,
VBG = Floating, Non-Extended Control Mode, SDR Mode, REXT = 3300Ω ±0.1%, Analog Signal Source Impedance = 100Ω
Differential. Boldface limits apply for TA = TMIN to TMAX. All other limits TA = 25°C, unless otherwise noted. See (1)(2)
Units
(Limits)
(3)
(3)
Symbol
Parameter
Conditions
Typical
Limits
CHANNEL-TO-CHANNEL CHARACTERISTICS
Offset Error Match
1
1
LSB
LSB
Positive Full-Scale Error Match
Negative Full-Scale Error Match
Phase Matching (I, Q)
Zero offset selected in Control Register
Zero offset selected in Control Register
FIN = 1.0 GHz
1
LSB
< 1
Degree
CLOCK INPUT CHARACTERISTICS
0.4
2.0
VP-P (min)
VP-P (max)
Sine Wave Clock
0.6
0.6
VID
Differential Clock Input Level
0.4
2.0
VP-P (min)
VP-P (max)
Square Wave Clock
II
Input Current
VIN = 0 or VIN = VA
Differential
±1
0.02
1.5
µA
pF
pF
(7)(8)
CIN
Input Capacitance
Each input to ground
DIGITAL CONTROL PIN CHARACTERISTICS
(9)
VIH
VIL
CIN
Logic High Input Voltage
Logic Low Input Voltage
See
0.85 x VA
0.15 x VA
V (min)
V (max)
pF
(9)
See
(8)(10)
Input Capacitance
Each input to ground
1.2
DIGITAL OUTPUT CHARACTERISTICS
400
920
280
720
mVP-P (min)
mVP-P (max)
mVP-P (min)
mVP-P (max)
Measured differentially, OutV = VA, VBG
= Floating,
710
(11)
VOD
LVDS Differential Output Voltage
Measured differentially, OutV = GND,
510
±1
(11)
VBG = Floating,
Change in LVDS Output Swing
Between Logic Levels
Δ VO DIFF
mV
VOS
VOS
Output Offset Voltage, see Figure 3
Output Offset Voltage, see Figure 3
VBG = Floating
800
mV
mV
(11)
VBG = VA
1200
Output Offset Voltage Change Between
Logic Levels
Δ VOS
±1
mV
IOS
Output Short Circuit Current
Differential Output Impedance
Cal_Run High level output
Cal_Run Low level output
Output+ & Output- connected to 0.8V
±4
mA
Ohms
V
ZO
100
1.65
0.15
(9)
VOH
VOL
IOH = -400 uA
1.5
0.3
(9)
IOH = 400 uA
V
POWER SUPPLY CHARACTERISTICS
PD = Low
PD = High
340
1.8
408
157
mA (max)
mA
IA
Analog Supply Current
PD = Low
PD = High
112
0.012
mA (max)
mA
IDR
Output Driver Supply Current
(7) The analog and clock input capacitances are die capacitances only. Additional package capacitances of 0.65 pF differential and 0.95 pF
each pin to ground are isolated from the die capacitances by lead and bond wire inductances.
(8) This parameter is specified by design and is not tested in production.
(9) This parameter is specified by design and/or characterization and is not tested in production.
(10) The digital control pin capacitances are die capacitances only. Additional package capacitance of 1.6 pF each pin to ground are isolated
from the die capacitances by lead and bond wire inductances.
(11) Tying VBG to the supply rail will increase the output offset voltage (VOS) by 400 mV (typical), as shown in the VOS specification above.
Tying VBG to the supply rail will also affect the differential LVDS output voltage (VOD), causing it to increase by 40mV (typical).
Copyright © 2007–2013, Texas Instruments Incorporated
Submit Documentation Feedback
11
Product Folder Links: ADC08500
ADC08500
SNAS373E –MAY 2007–REVISED APRIL 2013
www.ti.com
Converter Electrical Characteristics (continued)
The following specifications apply after calibration for VA = VDR = +1.9VDC, OutV = 1.9V, VIN FSR (a.c. coupled) = differential
870 mVP-P, CL = 10 pF, Differential, a.c. coupled Sinewave Input Clock, fCLK = 500 MHz at 0.5VP-P with 50% duty cycle,
VBG = Floating, Non-Extended Control Mode, SDR Mode, REXT = 3300Ω ±0.1%, Analog Signal Source Impedance = 100Ω
Differential. Boldface limits apply for TA = TMIN to TMAX. All other limits TA = 25°C, unless otherwise noted. See (1)(2)
Units
(Limits)
(3)
(3)
Symbol
PD
Parameter
Power Consumption
Conditions
Typical
Limits
1.0
PD = Low
PD = High
0.8
3.5
W (max)
mW
Change in Full Scale Error with change
in VA from 1.8V to 2.0V
PSRR1
PSRR2
D.C. Power Supply Rejection Ratio
A.C. Power Supply Rejection Ratio
30
51
dB
dB
248 MHz, 50mVP-P riding on VA
AC ELECTRICAL CHARACTERISTICS
fCLK1
fCLK2
Maximum Input Clock Frequency
Minimum Input Clock Frequency
500
MHz (min)
MHz
200
50
200 MHz ≤ Input clock frequency ≤ 800
MHz
20
80
% (min)
% (max)
Input Clock Duty Cycle
(12)
(12)
tCL
Input Clock Low Time
Input Clock High Time
See
500
500
400
400
ps (min)
ps (min)
(12)
tCH
See
45
55
% (min)
% (max)
(12)
DCLK Duty Cycle
See
50
(12)
tRS
tRH
Reset Setup Time
Reset Hold Time
See
150
250
ps
ps
(12)
See
Synchronizing Edge to DCLK Output
Delay
tSD
tOD + tOSK
CLK± Cycles
(min)
(13)
tRPW
Reset Pulse Width
See
4
tLHT
tHLT
Differential Low to High Transition Time 10% to 90%, CL = 2.5 pF
Differential High to Low Transition Time 10% to 90%, CL = 2.5 pF
250
250
ps
ps
50% of DCLK transition to 50% of Data
transition, SDR Mode
and DDR Mode, 0° DCLK
tOSK
DCLK to Data Output Skew
±50
ps (max)
(12)
(12)
tSU
tH
tAD
tAJ
Data to DCLK Set-Up Time
DCLK to Data Hold Time
Sampling (Aperture) Delay
Aperture Jitter
DDR Mode, 90° DCLK
1.7
1.9
1.3
0.4
ns
ns
(12)
DDR Mode, 90° DCLK
Input CLK+ Fall to Acquisition of Data
ns
ps rms
Input Clock to Data Output Delay (in
addition to Pipeline Delay)
50% of Input Clock transition to 50% of
Data transition
tOD
3.1
ns
D Outputs
13
14
(13)(14)
Pipeline Delay (Latency)
CLK± Cycles
Dd Outputs
Differential VIN step from ±1.2V to 0V to
get accurate conversion
Over Range Recovery Time
1
CLK± Cycle
ns
PD low to Rated Accuracy Conversion
(Wake-Up Time)
tWU
500
(12)
fSCLK
tSSU
tSH
Serial Clock Frequency
See
100
2.5
1
MHz
ns (min)
(12)
Data to Serial Clock Setup Time
Data to Serial Clock Hold Time
Serial Clock Low Time
See
(12)
See
ns (min)
4
4
ns (min)
Serial Clock High Time
ns (min)
tCAL
Calibration Cycle Time
1.4 x 105
CLK± Cycles
(12) This parameter is specified by design and/or characterization and is not tested in production.
(13) This parameter is specified by design and is not tested in production.
(14) The ADC08500 has two LVDS output buses, which each clock data out at one half the sample rate. The data at each bus is clocked out
at one half the sample rate. The second bus (D0 through D7) has a pipeline latency that is one clock cycle less than the latency of the
first bus (Dd0 through Dd7)
12
Submit Documentation Feedback
Copyright © 2007–2013, Texas Instruments Incorporated
Product Folder Links: ADC08500
ADC08500
www.ti.com
SNAS373E –MAY 2007–REVISED APRIL 2013
Converter Electrical Characteristics (continued)
The following specifications apply after calibration for VA = VDR = +1.9VDC, OutV = 1.9V, VIN FSR (a.c. coupled) = differential
870 mVP-P, CL = 10 pF, Differential, a.c. coupled Sinewave Input Clock, fCLK = 500 MHz at 0.5VP-P with 50% duty cycle,
VBG = Floating, Non-Extended Control Mode, SDR Mode, REXT = 3300Ω ±0.1%, Analog Signal Source Impedance = 100Ω
Differential. Boldface limits apply for TA = TMIN to TMAX. All other limits TA = 25°C, unless otherwise noted. See (1)(2)
Units
(Limits)
(3)
(3)
Symbol
tCAL_L
tCAL_H
Parameter
CAL Pin Low Time
Conditions
See Figure 11(13)
Typical
Limits
80
CLK± Cycles
(min)
CLK± Cycles
(min)
CAL Pin High Time
See Figure 11(13)
80
CalDly = Low
See Self-Calibration, Figure 11,
CLK± Cycles
(min)
225
(15)
(15)
Calibration delay determined by CalDly
(pin 127)
tCalDly
CalDly = High
See Self-Calibration, Figure 11,
CLK± Cycles
(max)
231
(15) Tying VBG to the supply rail will increase the output offset voltage (VOS) by 400 mV (typical), as shown in the VOS specification above.
Tying VBG to the supply rail will also affect the differential LVDS output voltage (VOD), causing it to increase by 40mV (typical).
Specification Definitions
APERTURE (SAMPLING) DELAY is the amount of delay, measured from the sampling edge of the CLK input,
after which the signal present at the input pin is sampled inside the device.
APERTURE JITTER (tAJ) is the variation in aperture delay from sample to sample. Aperture jitter shows up as
input noise.
Bit Error Rate (B.E.R.) is the probability of error and is defined as the probable number of word errors on the
ADC output per unit of time divided by the number of words seen in that amount of time. A B.E.R. of 10-18
corresponds to a statistical error in one word about every four (4) years.
CLOCK DUTY CYCLE is the ratio of the time that the clock wave form is at a logic high to the total time of one
clock period.
DIFFERENTIAL NON-LINEARITY (DNL) is the measure of the maximum deviation from the ideal step size of 1
LSB. Measured at sample rate = 500 MSPS with a 1MHz input sinewave.
EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE BITS) is another method of specifying Signal-to-Noise
and Distortion Ratio, or SINAD. ENOB is defined as (SINAD − 1.76) / 6.02 and says that the converter is
equivalent to a perfect ADC of this (ENOB) number of bits.
FULL POWER BANDWIDTH (FPBW) is a measure of the frequency at which the reconstructed output
fundamental drops 3 dB below its low frequency value for a full scale input.
GAIN ERROR is the deviation from the ideal slope of the transfer function. It can be calculated from Offset and
Full-Scale Errors:
Positive Gain Error = Offset Error − Positive Full-Scale Error
Negative Gain Error = −(Offset Error − Negative Full-Scale Error)
Gain Error = Negative Full-Scale Error − Positive Full-Scale Error = Positive Gain Error + Negative Gain
Error
INTEGRAL NON-LINEARITY (INL) is a measure of worst case deviation of the ADC transfer function from an
ideal straight line drawn through the ADC transfer function. The deviation of any given code from this straight line
is measured from the center of that code value step. The best fit method is used.
INTERMODULATION DISTORTION (IMD) is the creation of additional spectral components as a result of two
sinusoidal frequencies being applied to the ADC input at the same time. It is defined as the ratio of the power in
the second and third order intermodulation products to the power in one of the original frequencies. IMD is
usually expressed in dBFS.
Copyright © 2007–2013, Texas Instruments Incorporated
Submit Documentation Feedback
13
Product Folder Links: ADC08500
ADC08500
SNAS373E –MAY 2007–REVISED APRIL 2013
www.ti.com
LSB (LEAST SIGNIFICANT BIT) is the bit that has the smallest value or weight of all bits. This value is
VFS / 2n
where
•
•
VFS is the differential full-scale amplitude VIN as set by the FSR input
"n" is the ADC resolution in bits, which is 8 for the ADC08500.
(1)
LVDS DIFFERENTIAL OUTPUT VOLTAGE (VOD) is the absolute value of the difference between the VD+ & VD-
outputs; each measured with respect to Ground.
VD+
VD-
VOD
VD+
VOS
VD-
GND
VOD = | VD+ - VD- |
Figure 3.
LVDS OUTPUT OFFSET VOLTAGE (VOS) is the midpoint between the D+ and D- pins output voltage
referenced to ground. i.e., [(VD+) +( VD-)]/2.
MISSING CODES are those output codes that are skipped and will never appear at the ADC outputs. These
codes cannot be reached with any input value.
MSB (MOST SIGNIFICANT BIT) is the bit that has the largest value or weight. Its value is one half of full scale.
NEGATIVE FULL-SCALE ERROR (NFSE) is a measure of how far the first code transition is from the ideal 1/2
LSB above a differential -VIN/2. For the ADC08500 the reference voltage is assumed to be ideal, so this error is a
combination of full-scale error and reference voltage error.
OFFSET ERROR (VOFF) is a measure of how far the mid-scale point is from the ideal zero voltage differential
input.
Offset Error = Actual Input causing average of 8k samples to result in an average code of 127.5.
OUTPUT DELAY (tOD) is the time delay after the falling edge of DCLK before the data update is present at the
output pins.
OVER-RANGE RECOVERY TIME is the time required after the differential input voltages goes from ±1.2V to 0V
for the converter to recover and make a conversion with its rated accuracy.
PIPELINE DELAY (LATENCY) is the number of clock cycles between initiation of conversion and when that data
is presented to the output driver stage. New data is available at every clock cycle, but the data lags the
conversion by the Pipeline Delay plus the tOD
.
POSITIVE FULL-SCALE ERROR (PFSE) is a measure of how far the last code transition is from the ideal 1-1/2
LSB below a differential +VIN/2 . For the ADC08500 the reference voltage is assumed to be ideal, so this error is
a combination of full-scale error and reference voltage error.
POWER SUPPLY REJECTION RATIO (PSRR) can be one of two specifications. PSRR1 (DC PSRR) is the ratio
of the change in full-scale error that results from a power supply voltage change from 1.8V to 2.0V. PSRR2 (AC
PSRR) is a measure of how well an a.c. signal riding upon the power supply is rejected from the output and is
measured with a 248 MHz, 50 mVP-P signal riding upon the power supply. It is the ratio of the output amplitude of
that signal at the output to its amplitude on the power supply pin. PSRR is expressed in dB.
SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in dB, of the rms value of the input signal at the output
to the rms value of the sum of all other spectral components below one-half the sampling frequency, not
including harmonics or d.c.
14
Submit Documentation Feedback
Copyright © 2007–2013, Texas Instruments Incorporated
Product Folder Links: ADC08500
ADC08500
www.ti.com
SNAS373E –MAY 2007–REVISED APRIL 2013
SIGNAL TO NOISE PLUS DISTORTION (S/(N+D) or SINAD) is the ratio, expressed in dB, of the rms value of
the input signal at the output to the rms value of all of the other spectral components below half the clock
frequency, including harmonics but excluding d.c.
SPURIOUS-FREE DYNAMIC RANGE (SFDR) is the difference, expressed in dB, between the rms values of the
input signal at the output and the peak spurious signal, where a spurious signal is any signal present in the
output spectrum that is not present at the input, excluding d.c.
TOTAL HARMONIC DISTORTION (THD) is the ratio expressed in dB, of the rms total of the first nine harmonic
levels at the output to the level of the fundamental at the output. THD is calculated as
2
2
f10
A
+ . . . + A
f2
THD = 20 x log
2
A
f1
where
•
•
Af1 is the RMS power of the fundamental (output) frequency
Af2 through Af10 are the RMS power of the first 9 harmonic frequencies in the output spectrum.
(2)
– Second Harmonic Distortion (2nd Harm) is the difference, expressed in dB, between the RMS power in the
input frequency seen at the output and the power in its 2nd harmonic level at the output.
– Third Harmonic Distortion (3rd Harm) is the difference expressed in dB between the RMS power in the input
frequency seen at the output and the power in its 3rd harmonic level at the output.
Transfer Characteristic
IDEAL
POSITIVE
FULL-SCALE
TRANSITION
Output
Code
ACTUAL
POSITIVE
FULL-SCALE
TRANSITION
1111 1111 (255)
1111 1110 (254)
1111 1101 (253)
POSITIVE
FULL-SCALE
ERROR
MID-SCALE
TRANSITION
1000 0000 (128)
0111 1111 (127)
OFFSET
ERROR
IDEAL NEGATIVE
FULL-SCALE TRANSITION
ACTUAL NEGATIVE
FULL-SCALE TRANSITION
NEGATIVE
FULL-SCALE
ERROR
0000 0010 (2)
0000 0001 (1)
0000 0000 (0)
(V +) < (V -)
(V +) > (V -)
IN IN
IN
IN
0.0V
-V /2
+V /2
IN
IN
Differential Analog Input Voltage (+V /2) - (-V /2)
IN
IN
Figure 4. Input / Output Transfer Characteristic
Copyright © 2007–2013, Texas Instruments Incorporated
Submit Documentation Feedback
15
Product Folder Links: ADC08500
ADC08500
SNAS373E –MAY 2007–REVISED APRIL 2013
TEST CIRCUIT DIAGRAMS
Timing Diagrams
www.ti.com
Sample N
D
Sample N-1
Dd
V
IN
Sample N+1
t
AD
CLK, CLK
D, Dd
t
OD
Sample N-18 and
Sample N-17
Sample N-16 and Sample N-15
Sample N-14 and Sample N-13
t
OSK
DCLK+, DCLK-
(OutEdge = 0)
DCLK+, DCLK-
(OutEdge = 1)
Figure 5. ADC08500 Timing — SDR Clocking
Sample N
D
Sample N-1
Dd
V
IN
Sample N+1
t
AD
CLK, CLK
D, Dd
t
OD
Sample N-18 and
Sample N-17
Sample N-16 and Sample N-15
Sample N-14 and Sample N-13
t
OSK
DCLK+, DCLK-
(0°Phase)
t
t
H
SU
DCLK+, DCLK-
(90°Phase)
Figure 6. ADC08500 Timing — DDR Clocking
Single Register Access
SCS
1
12 13
16 17
32
SCLK
SDATA
Register Address
Fixed Header Pattern
Register Write Data
t
MSB
LSB
SH
t
SSU
Figure 7. Serial Interface Timing
16
Submit Documentation Feedback
Copyright © 2007–2013, Texas Instruments Incorporated
Product Folder Links: ADC08500
ADC08500
www.ti.com
SNAS373E –MAY 2007–REVISED APRIL 2013
Synchronizing Edge
CLK
t
RH
t
RS
t
AD
DCLK_RST
DCLK+
t
RPW
Figure 8. Clock Reset Timing in DDR Mode
Synchronizing Edge
CLK
t
RH
t
RS
t
SD
DCLK_RST
t
RPW
DCLK+
OUTEDGE
Figure 9. Clock Reset Timing in SDR Mode with OUTEDGE Low
Synchronizing Edge
CLK
t
RH
t
RS
t
SD
DCLK_RST
t
RPW
DCLK+
OUTEDGE
Figure 10. Clock Reset Timing in SDR Mode with OUTEDGE High
Copyright © 2007–2013, Texas Instruments Incorporated
Submit Documentation Feedback
17
Product Folder Links: ADC08500
ADC08500
SNAS373E –MAY 2007–REVISED APRIL 2013
www.ti.com
t
CAL
t
CAL
CalRun
t
t
CalDly
CAL_H
Calibration Delay
determined by
CalDly Pin (127)
CAL
t
CAL_L
POWER
SUPPLY
Figure 11. Self Calibration and On-Command Calibration Timing
18
Submit Documentation Feedback
Copyright © 2007–2013, Texas Instruments Incorporated
Product Folder Links: ADC08500
ADC08500
www.ti.com
SNAS373E –MAY 2007–REVISED APRIL 2013
Typical Performance Characteristics
VA = VDR= 1.9V, fCLK= 500 MHz, TA= 25°C unless otherwise stated.
INL vs. CODE
INL vs. TEMPERATURE
Figure 12.
Figure 13.
DNL vs. CODE
DNL vs. TEMPERATURE
Figure 14.
Figure 15.
POWER CONSUMPTION vs. SAMPLE RATE
ENOB vs. TEMPERATURE
Figure 16.
Figure 17.
Copyright © 2007–2013, Texas Instruments Incorporated
Submit Documentation Feedback
19
Product Folder Links: ADC08500
ADC08500
SNAS373E –MAY 2007–REVISED APRIL 2013
www.ti.com
Typical Performance Characteristics (continued)
VA = VDR= 1.9V, fCLK= 500 MHz, TA= 25°C unless otherwise stated.
ENOB vs. SUPPLY VOLTAGE
ENOB vs. INPUT FREQUENCY
Figure 18.
Figure 19.
SNR vs. TEMPERATURE
SNR vs. SUPPLY VOLTAGE
Figure 20.
Figure 21.
SNR vs. INPUT FREQUENCY
THD vs. TEMPERATURE
Figure 22.
Figure 23.
20
Submit Documentation Feedback
Copyright © 2007–2013, Texas Instruments Incorporated
Product Folder Links: ADC08500
ADC08500
www.ti.com
SNAS373E –MAY 2007–REVISED APRIL 2013
Typical Performance Characteristics (continued)
VA = VDR= 1.9V, fCLK= 500 MHz, TA= 25°C unless otherwise stated.
THD vs. SUPPLY VOLTAGE
THD vs. INPUT FREQUENCY
Figure 24.
Figure 25.
SFDR vs. TEMPERATURE
SFDR vs. SUPPLY VOLTAGE
Figure 26.
Figure 27.
SFDR vs. INPUT FREQUENCY
Spectral Response at fIN = 98 MHz
Figure 28.
Figure 29.
Copyright © 2007–2013, Texas Instruments Incorporated
Submit Documentation Feedback
21
Product Folder Links: ADC08500
ADC08500
SNAS373E –MAY 2007–REVISED APRIL 2013
www.ti.com
Typical Performance Characteristics (continued)
VA = VDR= 1.9V, fCLK= 500 MHz, TA= 25°C unless otherwise stated.
Spectral Response at fIN = 248 MHz
FULL POWER BANDWIDTH
Figure 30.
Figure 31.
22
Submit Documentation Feedback
Copyright © 2007–2013, Texas Instruments Incorporated
Product Folder Links: ADC08500
ADC08500
www.ti.com
SNAS373E –MAY 2007–REVISED APRIL 2013
FUNCTIONAL DESCRIPTION
The ADC08500 is a versatile A/D Converter with an innovative architecture permitting very high speed operation.
The controls available ease the application of the device to circuit solutions. Optimum performance requires
adherence to the provisions discussed here and in the Applications Information Section.
While it is generally poor practice to allow an active pin to float, pins 4 and 14 of the ADC08500 are designed to
be left floating without jeopardy. In all discussions throughout this data sheet, whenever a function is called by
allowing a pin to float, connecting that pin to a potential of one half the VA supply voltage will have the same
effect as allowing it to float.
OVERVIEW
The ADC08500 uses a calibrated folding and interpolating architecture that achieves 7.5 effective bits. The use
of folding amplifiers greatly reduces the number of comparators and power consumption. Interpolation reduces
the number of front-end amplifiers required, minimizing the load on the input signal and further reducing power
requirements. In addition to other things, on-chip calibration reduces the INL bow often seen with folding
architectures. The result is an extremely fast, high performance, low power converter.
The analog input signal that is within the converter's input voltage range is digitized to eight bits at speeds of 200
MSPS to 500 MSPS, typical. Differential input voltages below negative full-scale will cause the output word to
consist of all zeroes. Differential input voltages above positive full-scale will cause the output word to consist of
all ones. Either of these conditions at the input will cause the OR (Out of Range) output to be activated. This
single OR output indicates when the output code from one or both of the channels is below negative full scale or
above positive full scale.
The converter has a 1:2 demultiplexer that feeds two LVDS output buses. The data on these buses provide an
output word rate on each bus at half the ADC sampling rate and must be interleaved by the user to provide
output words at the full conversion rate.
The output levels may be selected to be normal or reduced. Using reduced levels saves power but could result in
erroneous data capture of some or all of the bits, especially at higher sample rates and in marginally designed
systems.
Self-Calibration
A self-calibration is performed upon power-up and can also be invoked by the user upon command. Calibration
trims the 100Ω analog input differential termination resistor and minimizes full-scale error, offset error, DNL and
INL, resulting in maximizing SNR, THD, SINAD (SNDR) and ENOB. Internal bias currents are also set with the
calibration process. All of this is true whether the calibration is performed upon power up or is performed upon
command. Running the self calibration is an important part of this chip's functionality and is required in order to
obtain adequate performance. In addition to the requirement to be run at power-up, self calibration must be re-
run whenever the sense of the FSR pin is changed. For best performance, we recommend that self calibration be
run 20 seconds or more after application of power and whenever the operating temperature changes
significantly, according to the particular system design requirements. See On-Command Calibration for more
information. Calibration can not be initiated or run while the device is in the power-down mode. See Power Down
for information on the interaction between Power Down and Calibration.
In normal operation, calibration is performed just after application of power and whenever a valid calibration
command is given, which is holding the CAL pin low for at least tCAL_L clock cycles, then hold it high for at least
another tCAL_H clock cycles as defined in the Converter Electrical Characteristics. The time taken by the
calibration procedure is specified as tCALin Converter Electrical Characteristics. Holding the CAL pin high upon
power up will prevent the calibration process from running until the CAL pin experiences the above-mentioned
tCAL_L clock cycles followed by tCAL_H clock cycles.
CalDly (pin 127) is used to select one of two delay times after the application of power before the start of
calibration. This calibration delay time is depedent on the setting of the CalDly pin and is specified as tCalDly in the
Converter Electrical Characteristics. These delay values allow the power supply to come up and stabilize before
calibration takes place. If the PD pin is high upon power-up, the calibration delay counter will be disabled until the
PD pin is brought low. Therefore, holding the PD pin high during power up will further delay the start of the
power-up calibration cycle. The best setting of the CalDly pin depends upon the power-on settling time of the
power supply.
Copyright © 2007–2013, Texas Instruments Incorporated
Submit Documentation Feedback
23
Product Folder Links: ADC08500
ADC08500
SNAS373E –MAY 2007–REVISED APRIL 2013
www.ti.com
Calibration Operation Notes:
•
During the calibration cycle, the OR output may be active as a result of the calibration algorithm. All data on
the output pins and the OR output are invalid during the calibration cycle.
•
During the power-up calibration and during the on-command calibration, all clocks are halted on chip,
including internal clocks and DCLK, while the input termination resistor is trimmed to a value that is equal to
REXT / 33. This is to reduce noise during the input resistor calibration portion of the calibration cycle.
This external resistor is located between pin 32 and ground. REXT must be 3300 Ω ±0.1%. With this value, the
input termination resistor is trimmed to be 100 Ω. Because REXT is also used to set the proper current for the
Track and Hold amplifier, for the preamplifiers and for the comparators, other values of REXT should not be
used.
•
•
Because the DCLK output is halted during calibration, it is recommended that this DCLK output not be used
as a system clock.
The CalRun output is high whenever the calibration procedure is running. This is true whether the calibration
is done at power-up or on-command.
Acquiring the Input
Data is acquired at the falling edge of CLK+ (pin 18) and the digital equivalent of that data is available at the
digital outputs 13 clock cycles later for the D output bus and 14 clock cycles later for the Dd output bus. There is
an additional internal delay called tOD before the data is available at the outputs. See the Timing DiagramsTiming
Diagram. The ADC08500 will convert as long as the clock signal is present. The fully differential comparator
design and the innovative design of the sample-and-hold amplifier, together with self calibration, enables a very
flat SINAD/ENOB response beyond 500 MHz. The ADC08500 output data signaling is LVDS and the output
format is offset binary.
Control Modes
Much of the user control can be accomplished with several control pins that are provided. Examples include
initiation of the calibration cycle, power down mode and full scale range setting. However, the ADC08500 also
provides an Extended Control mode whereby a serial interface is used to access register-based control of
several advanced features. The Extended Control mode is not intended to be enabled and disabled dynamically.
Rather, the user is expected to employ either the normal control mode or the Extended Control mode at all times.
When the device is in the Extended Control mode, pin-based control of several features is replaced with register-
based control and those pin-based controls are disabled. These pins are OutV (pin 3), OutEdge/DDR (pin 4),
FSR (pin 14) and CalDly (pin 127). See NORMAL/EXTENDED CONTROL for details on the Extended Control
mode.
The Analog Inputs
The ADC08500 must be driven with a differential input signal. Operation with a single-ended signal is not
recommended. It is important that the inputs either be a.c. coupled to the inputs with the VCMO pin grounded, or
d.c. coupled with the VCMO pin left floating. An input common mode voltage equal to the VCMO output must be
provided when d.c. coupling is used.
The input full-scale range is programmable in the normal mode by setting a level on pin 14 (FSR) as defined in
by the specification VIN in the Converter Electrical Characteristics. The full-scale range setting operates equally
on both ADCs.
In the Extended Control mode, programming the Input Full-Scale Voltage Adjust register allows the input full-
scale range to be adjusted as described in REGISTER DESCRIPTION and THE ANALOG INPUT.
Clocking
The ADC08500 must be driven with an a.c. coupled, differential clock signal. THE CLOCK INPUTS describes the
use of the clock input pins. A differential LVDS output clock is available for use in latching the ADC output data
into whatever receives that data.
The ADC08500 offers two options for output clocking. These options include a choice of which DCLK edge the
output data transitions on and a choice of Single Data Rate (SDR) or Double Data Rate (DDR) outputs.
24
Submit Documentation Feedback
Copyright © 2007–2013, Texas Instruments Incorporated
Product Folder Links: ADC08500
ADC08500
www.ti.com
SNAS373E –MAY 2007–REVISED APRIL 2013
The ADC08500 also has the option to use a duty cycle corrected clock receiver as part of the input clock circuit.
This feature is enabled by default and provides improved ADC clocking. This circuitry allows the ADC to be
clocked with a signal source having a duty cycle ratio of 20 / 80 % (worst case).
OutEdge Setting
To help ease data capture in the SDR mode, the output data may be caused to transition on either the positive or
the negative edge of the output data clock (DCLK). This is chosen with the OutEdge input (pin 4). A high on the
OutEdge input causes the output data to transition on the rising edge of DCLK, while grounding this input causes
the output to transition on the falling edge of DCLK. See Output Edge Synchronization.
Double Data Rate
A choice of single data rate (SDR) or double data rate (DDR) output is offered. With single data rate the DCLK
frequency is the same as the data rate of the two output buses. With double data rate the DCLK frequency is half
the data rate and data is sent to the outputs on both DCLK edges. DDR clocking is enabled in non-Extended
Control mode by allowing pin 4 to float.
The LVDS Outputs
The data outputs, the Out Of Range (OR) and DCLK, are LVDS. Output current sources provide 3 mA of output
current to a differential 100 Ohm load when the OutV input (pin 14) is high or 2.2 mA when the OutV input is low.
For short LVDS lines and low noise systems, satisfactory performance may be realized with the OutV input low,
which results in lower power consumption. If the LVDS lines are long and/or the system in which the ADC08500
is used is noisy, it may be necessary to tie the OutV pin high. The LVDS data output have a typical common
mode voltage of 800 mV when the VBG pin is unconnected and floating. This common mode voltage can be
increased to 1.2V by tying the VBG pin to VA if a higher common mode is required.
NOTE
Tying the VBG pin to VA will also increase the differential LVDS output voltage by up to 40
mV.
Power Down
The ADC08500 is in the active state when the Power Down pin (PD) is low. When the PD pin is high, the device
is in the power down mode, the output pins are put into a high impedance state and the device power
consumption is reduced to a minimal level. Upon return to normal operation, the pipeline will contain meaningless
information.
If the PD input is brought high while a calibration is running, the device will not go into power down until the
calibration sequence is complete. However, if power is applied and PD is already high, the device will not begin
the calibration sequence until the PD input goes low. If a manual calibration is requested while the device is
powered down, the calibration will not begin at all. That is, the manual calibration input is completely ignored in
the power down state.
NORMAL/EXTENDED CONTROL
The ADC08500 may be operated in one of two modes. In the simpler "normal" control mode, the user affects
available configuration and control of the device through several control pins. The "extended control mode"
provides additional configuration and control options through a serial interface and a set of 3 registers. The two
control modes are selected with pin 14 (FSR/ECE: Extended Control Enable). The choice of control modes is
required to be a fixed selection and is not intended to be switched dynamically while the device is operational.
Table 1 shows how several of the device features are affected by the control mode chosen.
Copyright © 2007–2013, Texas Instruments Incorporated
Submit Documentation Feedback
25
Product Folder Links: ADC08500
ADC08500
SNAS373E –MAY 2007–REVISED APRIL 2013
www.ti.com
Table 1. Features and Modes
Feature
Normal Control Mode
Extended Control Mode
Selected with nDE in the Configuration
Register (Addr-1h; bit-10). When the device
is in DDR mode, address 1h, bit-8 must be
set to 0b.
DDR Clocking selected with pin 4 floating.
SDR clocking selected when pin 4 not
floating.
SDR or DDR Clocking
Selected with DCP in the Configuration
Register (Addr- 1h; bit-11).
DDR Clock Phase
Not Selectable (0° Phase Only)
SDR Data transitions with rising edge of
DCLK+ when pin 4 is high and on falling
edge when low.
SDR Data transitions with rising or falling
DCLK edge
Selected with OE in the Configuration
Register (Addr- 1h; bit-8).
Normal differential data and DCLK amplitude
selected when pin 3 is high and reduced
amplitude selected when low.
Selected with the OV in the Configuration
Register (Addr- 1h; bit-9).
LVDS output level
Short delay selected when pin 127 is low and
longer delay selected when high.
Power-On Calibration Delay
Short delay only.
Up to 512 step adjustments over a nominal
Normal input full-scale range selected when range specified in REGISTER
Full-Scale Range
Input Offset Adjust
pin 14 is high and reduced range when low.
Selected range applies to both channels.
DESCRIPTION. Selected using the Input
Full-Scale Adjust register (Addr- 3h; bits-7
thru 15).
512 steps of adjustment using the Input
Offset register (Addr- 2h; bits-7 thru 15) as
specified in REGISTER DESCRIPTION.
Not possible
The default state of the Extended Control Mode is set upon power-on reset (internally performed by the device)
and is shown in Table 2.
Table 2. Extended Control Mode Operation
(Pin 14 Floating)
Feature
Extended Control Mode Default State
DDR Clocking
SDR or DDR Clocking
DDR Clock Phase
Data changes with DCLK edge (0° phase)
Normal amplitude
LVDS Output Amplitude
(710 mVP-P
)
Calibration Delay
Full-Scale Range
Input Offset Adjust
Short Delay
700 mV nominal for both channels
No adjustment for either channel
THE SERIAL INTERFACE
NOTE
During the initial write using the serial interface, all 3 user registers must be written with
desired or default values. Once all registers have been written once, other desired settings
can be loaded.
The 3-pin serial interface is enabled only when the device is in the Extended Control mode. The pins of this
interface are Serial Clock (SCLK), Serial Data (SDATA) and Serial Interface Chip Select (SCS). Three write only
registers are accessible through this serial interface.
SCS: This signal should be asserted low while accessing a register through the serial interface. Setup and hold
times with respect to the SCLK must be observed.
SCLK: Serial data input is accepted at the rising edge of this signal. There is no minimum frequency requirement
for SCLK.
SDATA: Each register access requires a specific 32-bit pattern at this input. This pattern consists of a header,
register address and register value. The data is shifted in MSB first. Setup and hold times with respect to the
SCLK must be observed. See Figure 7.
26
Submit Documentation Feedback
Copyright © 2007–2013, Texas Instruments Incorporated
Product Folder Links: ADC08500
ADC08500
www.ti.com
SNAS373E –MAY 2007–REVISED APRIL 2013
Each Register access consists of 32 bits, as shown in Figure 7 of the Timing Diagrams. The fixed header pattern
is 0000 0000 0001 (eleven zeros followed by a 1). The loading sequence is such that a "0" is loaded first. These
12 bits form the header. The next 4 bits are the address of the register that is to be written to and the last 16 bits
are the data written to the addressed register. The addresses of the various registers are indicated in Table 3.
Refer to REGISTER DESCRIPTION for information on the data to be written to the registers.
Subsequent register accesses may be performed immediately, starting with the 33rd SCLK. This means that the
SCS input does not have to be de-asserted and asserted again between register addresses. It is possible,
although not recommended, to keep the SCS input permanently enabled (at a logic low) when using extended
control.
NOTE
The Serial Interface should not be written to when calibrating the ADC. Doing so will
impair the performance of the device until it is re-calibrated correctly. Programming the
serial registers will also reduce dynamic performance of the ADC for the duration of the
register access time.
Table 3. Register Addresses
4-Bit Address
Loading Sequence:
A3 loaded after Fixed Header Pattern, A0 loaded last
A3
0
A2
0
A1
0
A0
0
Hex
0h
Register Addressed
Reserved
0
0
0
1
1h
Configuration
Input Offset
0
0
1
0
2h
Input Full-Scale Voltage
Adjust
0
0
1
1
3h
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
4h
5h
6h
7h
8h
9h
Ah
Bh
Ch
Dh
Eh
Fh
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
REGISTER DESCRIPTION
Three write-only registers provide several control and configuration options in the Extended Control Mode. These
registers have no effect when the device is in the Normal Control Mode. Each register description below also
shows the Power-On Reset (POR) state of each control bit.
Copyright © 2007–2013, Texas Instruments Incorporated
Submit Documentation Feedback
27
Product Folder Links: ADC08500
ADC08500
SNAS373E –MAY 2007–REVISED APRIL 2013
www.ti.com
Table 4. Configuration Register
Addr: 1h (0001b)
W only (0xB2FF)
D15
1
D14
0
D13
1
D12
D11
D10
nDE
D9
D8
DCS
DCP
OV
OE
D7
1
D6
1
D5
1
D4
1
D3
1
D2
1
D1
1
D0
1
Bit 15
Bit 14
Bit 13
Bit 12
Must be set to 1b
Must be set to 0b
Must be set to 1b
DCS: Duty Cycle Stabilizer. When this bit is set to 1b, a duty cycle stabilization circuit is applied to the clock
input. When this bit is set to 0b the stabilization circuit is disabled.
Bit 11
DCP: DDR Clock Phase. This bit only has an effect in the DDR mode. When this bit is set to 0b, the DCLK
edges are time-aligned with the data bus edges ("0° Phase"). When this bit is set to 1b, the DCLK edges are
placed in the middle of the data bit-cells ("90° Phase"), using the one-half speed DCLK shown in Figure 6 as
the phase reference.
POR State: 0b
Bit 10
nDE: DDR Enable. When this bit is set to 0b, data bus clocking follows the DDR (Dual Data Rate) mode
whereby a data word is output with each rising and falling edge of DCLK. When this bit is set to a 1b, data bus
clocking follows the SDR (single data rate) mode whereby each data word is output with either the rising or
falling edge of DCLK , as determined by the OutEdge bit.
POR State: 0b
Bit 9
Bit 8
OV: Output Voltage. This bit determines the LVDS outputs' voltage amplitude and has the same function as the
OutV pin that is used in the normal control mode. When this bit is set to 1b, the standard output amplitude of
710 mVP-P is used. When this bit is set to 0b, the reduced output amplitude of 510 mVP-P is used.
POR State: 1b
OE: Output Edge. This bit selects the DCLK edge with which the data words transition in the SDR mode and
has the same effect as the OutEdge pin in the normal control mode. When this bit is 1b, the data outputs
change with the rising edge of DCLK+. When this bit is 0b, the data output change with the falling edge of
DCLK+.
POR State: 0b
Bits 7:0
Must be set to 1b.
Table 5. Input Offset
Addr: 2h (0010b)
W only (0x007F)
D15
D14
D13
D12
D11
D10
D9
D8
(MSB)
Offset Value
(LSB)
D7
D6
1
D5
1
D4
1
D3
1
D2
1
D1
1
D0
1
Sign
Bits 15:8
Offset Value. The input offset of the I-Channel ADC is adjusted linearly and monotonically by the value in this
field. 00h provides a nominal zero offset, while FFh provides a nominal 45 mV of offset. Thus, each code step
provides 0.176 mV of offset.
POR State: 0000 0000b
Bit 7
Sign bit. 0b gives positive offset, 1b gives negative offset resulting in total offset adjustment of ±45 mV.
POR State: 0b
Bit 6:0
Must be set to 1b
28
Submit Documentation Feedback
Copyright © 2007–2013, Texas Instruments Incorporated
Product Folder Links: ADC08500
ADC08500
www.ti.com
SNAS373E –MAY 2007–REVISED APRIL 2013
Table 6. Input Full-Scale Voltage Adjust
Addr: 3h (0011b)
W only (0x807F)
D15
D14
D13
D12
D11
D10
D9
D8
(MSB)
Adjust Value
D7
D6
1
D5
1
D4
1
D3
1
D2
1
D1
1
D0
1
(LSB)
Bit 15:7
Full Scale Voltage Adjust Value. The input full-scale voltage of the I-Channel ADC is adjusted linearly and
monotonically from the nominal 700 mVP-P differential by the value in this field.
0000 0000 0
1000 0000 0
1111 1111 1
560 mVP-P
700 mVP-P
840 mVP-P
For best performance, it is recommended that the value in this field be limited to the range of 0110 0000 0b to
1110 0000 0b. i.e., limit the amount of adjustment to ±15%. The remaining ±5% headroom allows for the ADC's
own full scale variation. A gain adjustment does not require ADC re-calibration.
POR State: 1000 0000 0b (no adjustment)
Must be set to 1b
Bits 6:0
Note Regarding Extended Mode Offset Correction
When using the Input channel Offset Adjust register, the following information should be noted.
For offset values of +0000 0000 and -0000 0000, the actual offset is not the same. By changing only the sign bit
in this case, an offset step in the digital output code of about 1/10th of an LSB is experienced. This is shown
more clearly in the Figure below.
Figure 32. Extended Mode Offset Behavior
MULTIPLE ADC SYNCHRONIZATION
The ADC08500 has the capability to precisely reset its sampling clock input to DCLK output relationship as
determined by the user-supplied DCLK_RST pulse. This allows multiple ADCs in a system to have their DCLK
(and data) outputs transition at the same time with respect to the shared CLK input that all the ADCs use for
sampling.
The DCLK_RST signal must observe some timing requirements that are shown in Figure 8, Figure 9, and
Figure 10 of the Timing Diagrams. The DCLK_RST pulse must be of a minimum width and its de-assertion edge
must observe setup and hold times with respect to the CLK input rising edge. These timing specifications are
listed as tRH, tRS, and tRPW in the Converter Electrical CharacteristicsConverter Electrical Characteristics.
Copyright © 2007–2013, Texas Instruments Incorporated
Submit Documentation Feedback
29
Product Folder Links: ADC08500
ADC08500
SNAS373E –MAY 2007–REVISED APRIL 2013
www.ti.com
The DCLK_RST signal can be asserted asynchronous to the input clock. If DCLK_RST is asserted, the DCLK
output is held in a designated state. The state in which DCLK is held during the reset period is determined by the
mode of operation (SDR/DDR) and the setting of the Output Edge configuration pin or bit. (Refer to Figure 8,
Figure 9, and Figure 10 for the DCLK reset conditions). Therefore, depending upon when the DCLK_RST signal
is asserted, there may be a narrow pulse on the DCLK line during this reset event. When the DCLK_RST signal
is de-asserted in synchronization with the CLK rising edge, the next CLK falling edge synchronizes the DCLK
output with those of other ADC08500s in the system. The DCLK output is enabled again after a constant delay
which is equal to the CLK input to DCLK output delay (tAD). The device always exhibits this delay characteristic in
normal operation.
The DCLK_RST pin should NOT be brought high while the calibration process is running (while CalRun is high).
Doing so could cause a digital glitch in the digital circuitry, resulting in corruption and invalidation of the
calibration.
Applications Information
THE REFERENCE VOLTAGE
The voltage reference for the ADC08500 is derived from a 1.254V bandgap reference which is made available at
pin 31, VBG, for user convenience. This output has an output current capability of ±100 μA and should be
buffered if more current than this is required.
The internal bandgap-derived reference voltage has a nominal value of VIN, as determined by the FSR pin and
described in The Analog Inputs.
There is no provision for the use of an external reference voltage, but the full-scale input voltage can be adjusted
through a Configuration Register in the Extended Control mode, as explained in NORMAL/EXTENDED
CONTROL.
Differential input signals up to the chosen full-scale level will be digitized to 8 bits. Signal excursions beyond the
full-scale range will be clipped at the output. These large signal excursions will also activate the OR output for
the time that the signal is out of range. See Out Of Range (OR) Indication.
One extra feature of the VBG pin is that it can be used to raise the common mode voltage level of the LVDS
outputs. The output offset voltage (VOS) is typically 800 mV when the VBG pin is used as an output or left
unconnected. To raise the LVDS offset voltage to a typical value of 1200 mV the VBG pin can be connected
directly to the supply rails.
THE ANALOG INPUT
The analog input is a differential one to which the signal source may be a.c. coupled or d.c. coupled. In the
normal mode, the full-scale input range is selected using the FSR pin as specified in the Converter Electrical
Characteristics. In the Extended Control mode, the full-scale input range is selected by programming the Full-
Scale Voltage Adjust register through the Serial Interface. For best performance when adjusting the input full-
scale range in the Extended Control, refer to REGISTER DESCRIPTION for guidelines on limiting the amount of
adjustment.
Table 7 gives the input to output relationship with the FSR pin high when the normal (non-extended) mode is
used. With the FSR pin grounded, the millivolt values in Table 7 are reduced to 75% of the values indicated. In
the Extended Control Mode, these values will be determined by the full scale range and offset settings in the
Control Registers.
Table 7. DIFFERENTIAL INPUT TO OUTPUT RELATIONSHIP (Non-Extended Control Mode, FSR High)
VIN
+
VIN
−
Output Code
0000 0000
0100 0000
V
CM − 217.5 mV
VCM + 217.5 mV
VCM + 109 mV
V
CM − 109 mV
0111 1111 /
1000 0000
VCM
VCM
VCM + 109 mV
V
CM − 109 mV
1100 0000
1111 1111
VCM + 217.5 mV
VCM − 217.5 mV
30
Submit Documentation Feedback
Copyright © 2007–2013, Texas Instruments Incorporated
Product Folder Links: ADC08500
ADC08500
www.ti.com
SNAS373E –MAY 2007–REVISED APRIL 2013
The buffered analog inputs simplify the task of driving these inputs and the RC pole that is generally used at
sampling ADC inputs is not required. If it is desired to use an amplifier circuit before the ADC, use care in
choosing an amplifier with adequate noise and distortion performance and adequate gain at the frequencies used
for the application.
Note that a precise d.c. common mode voltage must be present at the ADC inputs. This common mode voltage,
VCMO, is provided on-chip when a.c. input coupling is used and the input signal is a.c. coupled to the ADC.
When the inputs are a.c. coupled, the VCMO output must be grounded, as shown in Figure 33. This causes the
on-chip VCMO voltage to be connected to the inputs through on-chip 50k-Ohm resistors.
C
C
couple
couple
V
+
IN
V
-
IN
V
CMO
ADC08500
Figure 33. Differential Input Drive
When the d.c. coupled mode is used, a common mode voltage must be provided at the differential inputs. This
common mode voltage should track the VCMO output pin. Note that the VCMO output potential will change with
temperature. The common mode output of the driving device should track this change.
Full-scale distortion performance falls off rapidly as the input common mode voltage deviates from VCMO
This is a direct result of using a very low supply voltage to minimize power. Keep the input common
voltage within 50 mV of VCMO
.
.
Performance is as good in the d.c. coupled mode as it is in the a.c. coupled mode, provided the input common
mode voltage at both analog inputs remain within 50 mV of VCMO
.
Handling Single-Ended Input Signals
There is no provision for the ADC08500 to adequately process single-ended input signals. The best way to
handle single-ended signals is to convert them to differential signals before presenting them to the ADC.
a.c. Coupled Input
The easiest way to accomplish single-ended a.c. input to differential a.c. signal is by using an appropriate balun,
as shown in Figure 34.
C
couple
couple
V
+
IN
50W
Source
100W
1:2 Balun
V
-
IN
C
ADC08500
Figure 34. Single-Ended to Differential signal conversion using a balun
Figure 34 is a generic depiction of a single-ended to differential signal conversion using a balun. The circuitry
specific to the balun will depend upon the type of balun selected and the overall board layout. It is recommended
that the system designer contact the manufacturer of the balun they have selected to aid in designing the best
performing single-ended to differential conversion circuit using that particular balun.
Copyright © 2007–2013, Texas Instruments Incorporated
Submit Documentation Feedback
31
Product Folder Links: ADC08500
ADC08500
SNAS373E –MAY 2007–REVISED APRIL 2013
www.ti.com
When selecting a balun, it is important to understand the input architecture of the ADC. There are specific balun
parameters of which the system designer should be mindful. A designer should match the impedance of their
analog source to the ADC08500's on-chip 100Ω differential input termination resistor. The range of this input
termination resistor is described in the electrical table as the specification RIN.
Also, the phase and amplitude balance are important. The lowest possible phase and amplitude imbalance is
desired when selecting a balun. The phase imbalance should be no more than ±2.5° and the amplitude
imbalance should be limited to less than 1dB at the desired input frequency range. Finally, when selecting a
balun, the VSWR (Voltage Standing Wave Ratio), bandwidth and insertion loss of the balun should also be
considered. The VSWR aids in determining the overall transmission line termination capability of the balun when
interfacing to the ADC input. The insertion loss should be considered so that the signal at the balun output is
within the specified input range of the ADC as described in the Converter Electrical Characteristics as the
specification VIN.
d.c. Coupled Input
When d.c. coupling to the ADC08500 analog inputs is required, single-ended to differential conversion may be
easily accomplished with the LMH6555. An example of this type of circuit is shown in Figure 35. In such
applications, the LMH6555 performs the task of single-ended to differential conversion while delivering low
distortion and noise, as well as output balance, that supports the operation of the ADC08500. Connecting the
ADC08500 VCMO pin to the VCM_REF pin of the LMH6555, through an appropriate buffer, will ensure that the
common mode input voltage is as needed for optimum performance of the ADC08500. The LMV321 was chosen
to buffer VCMO for its low voltage operation and reasonable offset voltage.
Be sure that the current drawn from the VCMO output does not exceed 100 μA.
3.3V
LMH6555
RF1
RT2
50W
V -
IN
RG1
-
+
Signal
Input
50W
RT1
50W
RG2
V +
IN
RF2
VCM_REF
+
-
V
CMO
LMV321
Figure 35. Example of Servicing the Analog Input with VCMO
In Figure 35, RADJ-and RADJ+ are used to adjust the differential offset that can be measured at the ADC inputs
VIN+ / VIN-. An unadjusted positive offset with reference to VIN-greater than |15mV| should be reduced with a
resistor in the RADJ-position. Likewise, an unadjusted negative offset with reference to VIN-greater than |15mV|
should be reduced with a resistor in the RADJ+ position. Table 8 gives suggested RADJ-and RADJ+ values for
various unadjusted differential offsets to bring the VIN+ / VIN-offset back to within |15mV|.
Table 8. D.C. Coupled Offset Adjustment
Unadjusted Offset Reading
0mV to 10mV
Resistor Value
no resistor needed
20.0kΩ
11mV to 30mV
31mV to 50mV
10.0kΩ
51mV to 70mV
6.81kΩ
71mV to 90mV
4.75kΩ
91mV to 110mV
3.92kΩ
32
Submit Documentation Feedback
Copyright © 2007–2013, Texas Instruments Incorporated
Product Folder Links: ADC08500
ADC08500
www.ti.com
SNAS373E –MAY 2007–REVISED APRIL 2013
Out Of Range (OR) Indication
When the conversion result is clipped the Out of Range output is activated such that OR+ goes high and OR-
goes low. This output is active as long as accurate data on either or both of the buses would be outside the
range of 00h to FFh.
Full-Scale Input Range
As with all A/D Converters, the input range is determined by the value of the ADC's reference voltage. The
reference voltage of the ADC08500 is derived from an internal band-gap reference. The FSR pin controls the
effective reference voltage of the ADC08500 such that the differential full-scale input range at the analog inputs
is a normal amplitude with the FSR pin high, or a reduced amplitude with FSR pin low as defined by the
specification VIN in the Converter Electrical Characteristics. Best SNR is obtained with FSR high, but better
distortion and SFDR are obtained with the FSR pin low.
THE CLOCK INPUTS
The ADC08500 has differential LVDS clock inputs, CLK+ and CLK-, which must be driven with an a.c. coupled,
differential clock signal. Although the ADC08500 is tested and its performance is ensured with a differential 500
MHz clock, it typically will function well with clock frequencies indicated in the Converter Electrical
Characteristics. The clock inputs are internally terminated and biased. The clock signal must be capacitively
coupled to the clock pins as indicated in Figure 36.
Operation up to the sample rates indicated in the Converter Electrical Characteristics is typically possible if the
maximum ambient temperatures indicated are not exceeded. Operating at higher sample rates than indicated for
the given ambient temperature may result in reduced device reliability and product lifetime. This is because of the
higher power consumption and die temperatures at high sample rates. Important also for reliability is proper
thermal management . See Thermal Management.
C
C
couple
couple
CLK+
CLK-
ADC08500
Figure 36. Differential (LVDS) Clock Connection
The differential Clock line pair should have a characteristic impedance of 100Ω and be terminated at the clock
source in that (100Ω) characteristic impedance. The clock line should be as short and as direct as possible. The
ADC08500 clock input is internally terminated with an untrimmed 100Ω resistor.
Insufficient clock levels will result in poor dynamic performance. Excessively high clock levels could cause a
change in the analog input offset voltage. To avoid these problems, keep the clock level within the range
specified as VID in the Converter Electrical Characteristics.
The low and high times of the input clock signal can affect the performance of any A/D Converter. The
ADC08500 features a duty cycle clock correction circuit which can maintain performance over temperature. The
ADC will meet its performance specification if the input clock high and low times are maintained within the duty
cycle range as specified in the Converter Electrical Characteristics.
Copyright © 2007–2013, Texas Instruments Incorporated
Submit Documentation Feedback
33
Product Folder Links: ADC08500
ADC08500
SNAS373E –MAY 2007–REVISED APRIL 2013
www.ti.com
High speed, high performance ADCs such as the ADC08500 require a very stable clock signal with minimum
phase noise or jitter. ADC jitter requirements are defined by the ADC resolution (number of bits), maximum ADC
input frequency and the input signal amplitude relative to the ADC input full scale range. The maximum jitter (the
sum of the jitter from all sources) allowed to prevent a jitter-induced reduction in SNR is found to be
tJ(MAX) = (VIN(P-P) / VINFSR) x (1/(2(N+1) x π x fIN))
where
•
•
•
•
tJ(MAX) is the rms total of all jitter sources in seconds
VIN(P-P) is the peak-to-peak analog input signal
VINFSR is the full-scale range of the ADC
"N" is the ADC resolution in bits and fIN is the maximum input frequency, in Hertz, at the ADC analog input. (3)
Note that the maximum jitter described above is the RSS sum of the jitter from all sources, including that in the
ADC clock, that added by the system to the ADC clock and input signals and that added by the ADC itself. Since
the effective jitter added by the ADC is beyond user control, the best the user can do is to keep the sum of the
externally added clock jitter and the jitter added by the analog circuitry to the analog signal to a minimum.
Input clock amplitudes above those specified in the Converter Electrical CharacteristicsConverter Electrical
Characteristics may result in increased input offset voltage. This would cause the converter to produce an output
code other than the expected 127/128 when both input pins are at the same potential.
CONTROL PINS
Six control pins (without the use of the serial interface) provide a wide range of possibilities in the operation of
the ADC08500 and facilitate its use. These control pins provide Full-Scale Input Range setting, Self Calibration,
Calibration Delay, Output Edge Synchronization choice, LVDS Output Level choice and a Power Down feature.
Full-Scale Input Range Setting
The input full-scale range can be selected with the FSR control input (pin 14) in the normal mode of operation.
The is specified as VIN in the Converter Electrical Characteristics. In the extended control mode, the input full-
scale range may be programmed using the Full-Scale Adjust Voltage register. See THE ANALOG INPUT for
more information.
Self Calibration
The ADC08500 self-calibration must be run to achieve specified performance. The calibration procedure is run
upon power-up and can be run any time on command. The calibration procedure is exactly the same whether
there is a clock present upon power up or if the clock begins some time after application of power. The CalRun
output indicator is high while a calibration is in progress.
It is important that no digital activity take place on any of the digital input lines during the calibration process,
except that there must be a stable, constant frequency CLK signal present and that SCLK may be active if the
Enhanced Mode is selected. Specifically, none of the following actions are allowed during the calibration process:
•
•
•
•
•
•
•
•
Changing OUTV
Changing OutEdge or SDATA sense
Changing between SDR and DDR
Changing FSE or ECE
Changing DCLK_RST
Changing SCS
Raising PD high
Raising CAL high
Doing any of these actions can cause faulty calibration.
Power-On Calibration
Power-on calibration begins after a time delay following the application of power. This time delay is determined
by the setting of CalDly, as described in Calibration Delay, below.
34
Submit Documentation Feedback
Copyright © 2007–2013, Texas Instruments Incorporated
Product Folder Links: ADC08500
ADC08500
www.ti.com
SNAS373E –MAY 2007–REVISED APRIL 2013
The calibration process will be not be performed if the CAL pin is high at power up. In this case, the calibration
cycle will not begin until the on-command calibration conditions are met. The ADC08500 will function with the
CAL pin held high at power up, but no calibration will be done and performance will be impaired. A manual
calibration, however, may be performed after powering up with the CAL pin high. See On-Command Calibration.
The internal power-on calibration circuitry comes up in an unknown logic state. If the clock is not running at
power up and the power on calibration circuitry is active, it will hold the analog circuitry in power down and the
power consumption will typically be less than 200 mW. The power consumption will be normal after the clock
starts.
On-Command Calibration
To initiate an on-command calibration, bring the CAL pin high for a minimum of tCAL_H input clock cycles after it
has been low for a minimum of tCAL_L input clock cycles. Holding the CAL pin high upon power up will prevent
execution of power-on calibration until the CAL pin is low for a minimum of tCAL_L input clock cycles, then brought
high for a minimum of another tCAL_H input clock cycles. The calibration cycle will begin tCAL_H input clock cycles
after the CAL pin is thus brought high. The CalRun signal should be monitored to determine when the calibration
cycle has completed.
The minimum tCAL_H and tCAL_L input clock cycle sequences are required to ensure that random noise does not
cause a calibration to begin when it is not desired. As mentioned in Self-Calibration for best performance, a self
calibration should be performed 20 seconds or more after power up and repeated when the operating
temperature changes significantly according to the particular system performance requirements. ENOB drops
slightly as junction temperature increases and executing a new self calibration cycle will essentially eliminate the
change.
During a Power-On calibration cycle, both the ADC and the input termination resistor are calibrated. As dynamic
performance changes slightly with junction temperature, an On-Command calibration can be executed to bring
the performance of the ADC in line.
Calibration Delay
The CalDly input (pin 127) is used to select one of two delay times after the application of power to the start of
calibration, as described in Self-Calibration. The calibration delay values allow the power supply to come up and
stabilize before calibration takes place. With no delay or insufficient delay, calibration would begin before the
power supply is stabilized at its operating value and result in non-optimal calibration coefficients. If the PD pin is
high upon power-up, the calibration delay counter will be disabled until the PD pin is brought low. Therefore,
holding the PD pin high during power up will further delay the start of the power-up calibration cycle. The best
setting of the CalDly pin depends upon the power-on settling time of the power supply.
Note that the calibration delay selection is not possible in the Extended Control mode and the short delay time is
used.
Output Edge Synchronization
DCLK signals are available to help latch the converter output data into external circuitry. The output data can be
synchronized with either edge of these clock signals. That is, the output data transition can be set to occur with
either the rising edge or the falling edge of the DCLK signal, so that either edge of that clock signal can be used
to latch the output data into the receiving circuit.
When OutEdge (pin 4) is high, the output data is synchronized with (changes with) the rising edge of the DCLK+
(pin 82). When OutEdge is low, the output data is synchronized with the falling edge of DCLK+.
At the very high speeds of which the ADC08500 is capable, slight differences in the lengths of the clock and data
lines can mean the difference between successful and erroneous data capture. The OutEdge pin is used to
capture data on the DCLK edge that best suits the application circuit and layout.
LVDS Output Level Control
The output level can be set to one of two levels with OutV (pin3). The strength of the output drivers is greater
with OutV high. With OutV low there is less power consumption in the output drivers, but the lower output level
means decreased noise immunity.
Copyright © 2007–2013, Texas Instruments Incorporated
Submit Documentation Feedback
35
Product Folder Links: ADC08500
ADC08500
SNAS373E –MAY 2007–REVISED APRIL 2013
www.ti.com
For short LVDS lines and low noise systems, satisfactory performance may be realized with the FSR input low. If
the LVDS lines are long and/or the system in which the ADC08500 is used is noisy, it may be necessary to tie
the FSR pin high.
Power Down Feature
The Power Down pin (PD) suspends device operation and puts the ADC08500 into a minimum power
consumption state. See Power Down for details on the power down feature.
The digital data (+/-) output pins are put into a high impedance state when the PD pin is high. Upon return to
normal operation, the pipeline will contain meaningless information and must be flushed.
If the PD input is brought high while a calibration is running, the device will not go into power down until the
calibration sequence is complete. However, if power is applied and PD is already high, the device will not begin
the calibration sequence until the PD input goes low. If a manual calibration is requested while the device is
powered down, the calibration will not begin at all. That is, the manual calibration input is completely ignored in
the power down state.
THE DIGITAL OUTPUTS
The ADC08500 demultiplexes the output data of the ADC onto two LVDS output buses. The results of
successive conversions started on the odd falling edges of the CLK+ pin are available on one of the two LVDS
buses, while the results of conversions started on the even falling edges of the CLK+ pin are available on the
other LVDS bus. This means that, the word rate at each LVDS bus is 1/2 the ADC08500 input clock rate and the
two buses must be multiplexed to obtain the entire 0.5 GSPS conversion result.
Since the minimum recommended input clock rate for this device is 200 MSPS, the effective rate can be reduced
to as low as 100 MSPS by using the results available on just one of the the two LVDS buses and a 200 MHz
input clock, decimating the 200 MSPS data by two.
There is one LVDS output clock pair (DCLK+/-) available for use to latch the LVDS outputs on all buses. Whether
the data is sent at the rising or falling edge of DCLK is determined by the sense of the OutEdge pin, as described
in Output Edge Synchronization.
DDR (Double Data Rate) clocking can also be used. In this mode a word of data is presented with each edge of
DCLK, reducing the DCLK frequency to 1/4 the input clock frequency. See TEST CIRCUIT DIAGRAMS for
details.
The OutV pin is used to set the LVDS differential output levels. See LVDS Output Level Control.
The output format is Offset Binary. Accordingly, a full-scale input level with VIN+ positive with respect to VIN− will
produce an output code of all ones, a full-scale input level with VIN− positive with respect to VIN+ will produce an
output code of all zeros and when VIN+ and VIN− are equal, the output code will vary between codes 127 and
128.
POWER CONSIDERATIONS
A/D converters draw sufficient transient current to corrupt their own power supplies if not adequately bypassed. A
33 µF capacitor should be placed within an inch (2.5 cm) of the A/D converter power pins. A 0.1 µF capacitor
should be placed as close as possible to each VA pin, preferably within one-half centimeter. Leadless chip
capacitors are preferred because they have low lead inductance.
The VA and VDR supply pins should be isolated from each other to prevent any digital noise from being coupled
into the analog portions of the ADC. A ferrite choke, such as the JW Miller FB20009-3B, is recommended
between these supply lines when a common source is used for them.
The Power Supply
As is the case with all high speed converters, the ADC08500 should be assumed to have little power supply
noise rejection. Any power supply used for digital circuitry in a system where a lot of digital power is being
consumed should not be used to supply power to the ADC08500. The ADC supplies should be the same supply
used for other analog circuitry, if not a dedicated supply.
36
Submit Documentation Feedback
Copyright © 2007–2013, Texas Instruments Incorporated
Product Folder Links: ADC08500
ADC08500
www.ti.com
SNAS373E –MAY 2007–REVISED APRIL 2013
Because switching power supplies produce ringing energy at frequencies much higher than their switching rate,
which can impact the noise performance of high frequency systems, the use of such supplies is not
recommended in high frequency systems. However, realizing that linear supplies may not be practical, it is
important that care be exercised in the placement and layout of any switching supplies. Application Note AN-
1149 (Literature Number SNVA021) can help.
The ADC08500 is specified to operate with a supply voltage of 1.9V ±0.1V. It is very important to note that, while
this device will function with slightly higher supply voltages, these higher supply voltages may reduce product
lifetime.
No pin should ever have a voltage on it that is in excess of the supply voltage or below ground by more than 150
mV, not even on a transient basis. This can be a problem upon application of power and power shut-down. Be
sure that the supplies to circuits driving any of the input pins, analog or digital, do not come up any faster than
does the voltage at the ADC08500 power pins.
The Absolute Maximum Ratings should be strictly observed, even during power up and power down. A power
supply that produces a voltage spike at turn-on and/or turn-off of power can destroy the ADC08500. The circuit of
Figure 37 will provide supply overshoot protection.
Many linear regulators will produce output spiking at power-on unless there is a minimum load provided. Active
devices draw very little current until their supply voltages reach a few hundred millivolts. The result can be a turn-
on spike that can destroy the ADC08500, unless a minimum load is provided for the supply. The 100Ω resistor at
the regulator output provides a minimum output current during power-up to ensure there is no turn-on spiking.
In the circuit of Figure 37, an LM317 linear regulator is satisfactory if its input supply voltage is 4V to 5V . If a
3.3V supply is used, an LM1086 linear regulator is recommended.
Linear
Regulator
1.9V
to ADC
V
IN
+
10 mF
210
110
+
33 mF
100
+
10 mF
Figure 37. Non-Spiking Power Supply
The output drivers should have a supply voltage, VDR, that is within the range specified in the Operating Ratings
table. This voltage should not exceed the VA supply voltage.
If the power is applied to the device without a clock signal present, the current drawn by the device might be
below 200 mA. This is because the ADC08500 gets reset through clocked logic and its initial state is random. If
the reset logic comes up in the "on" state, it will cause most of the analog circuitry to be powered down, resulting
in less than 100 mA of current draw. This current is greater than the power down current because not all of the
ADC is powered down. The device current will be normal after the clock is established.
Thermal Management
The ADC08500 is capable of impressive speeds and performance at very low power levels for its speed.
However, the power consumption is still high enough to require attention to thermal management. For reliability
reasons, the die temperature should be kept to a maximum of 130°C. That is, TA (ambient temperature) plus
ADC power consumption times θJA (junction to ambient thermal resistance) should not exceed 130°C. This is not
a problem if the ambient temperature is kept to a maximum of +85°C as specified in the Operating Ratings
section.
Please note that the following are general recommendations for mounting exposed pad devices onto a PCB. This
should be considered the starting point in PCB and assembly process development. It is recommended that the
process be developed based upon past experience in package mounting.
Copyright © 2007–2013, Texas Instruments Incorporated
Submit Documentation Feedback
37
Product Folder Links: ADC08500
ADC08500
SNAS373E –MAY 2007–REVISED APRIL 2013
www.ti.com
The package of the ADC08500 has an exposed pad on its back that provides the primary heat removal path as
well as excellent electrical grounding to the printed circuit board. The land pattern design for lead attachment to
the PCB should be the same as for a conventional HLQFP, but the exposed pad must be attached to the board
to remove the maximum amount of heat from the package, as well as to ensure best product parametric
performance.
To maximize the removal of heat from the package, a thermal land pattern must be incorporated on the PC
board within the footprint of the package. The exposed pad of the device must be soldered down to ensure
adequate heat conduction out of the package. The land pattern for this exposed pad should be at least as large
as the 5 x 5 mm of the exposed pad of the package and be located such that the exposed pad of the device is
entirely over that thermal land pattern. This thermal land pattern should be electrically connected to ground. A
clearance of at least 0.5 mm should separate this land pattern from the mounting pads for the package pins.
5.0 mm, min
0.25 mm, typ
0.33 mm, typ
1.2 mm, typ
Figure 38. Recommended Package Land Pattern
Since a large aperture opening may result in poor release, the aperture opening should be subdivided into an
array of smaller openings, similar to the land pattern of Figure 38.
To minimize junction temperature, it is recommended that a simple heat sink be built into the PCB. This is done
by including a copper area of about 2 square inches (6.5 square cm) on the opposite side of the PCB. This
copper area may be plated or solder coated to prevent corrosion, but should not have a conformal coating, which
could provide some thermal insulation. Thermal vias should be used to connect these top and bottom copper
areas. These thermal vias act as "heat pipes" to carry the thermal energy from the device side of the board to the
opposite side of the board where it can be more effectively dissipated. The use of 9 to 16 thermal vias is
recommended.
The thermal vias should be placed on a 1.2 mm grid spacing and have a diameter of 0.30 to 0.33 mm. These
vias should be barrel plated to avoid solder wicking into the vias during the soldering process as this wicking
could cause voids in the solder between the package exposed pad and the thermal land on the PCB. Such voids
could increase the thermal resistance between the device and the thermal land on the board, which would cause
the device to run hotter.
If it is desired to monitor die temperature, a temperature sensor may be mounted on the heat sink area of the
board near the thermal vias. .Allow for a thermal gradient between the temperature sensor and the ADC08500
die of θJ-PAD times typical power consumption = 2.8 x 1.6 = 4.5°C. Allowing for a 5.5°C (including an extra 1°C)
temperature drop from the die to the temperature sensor, then, would mean that maintaining a maximum pad
temperature reading of 124.5°C will ensure that the die temperature does not exceed 130°C, assuming that the
exposed pad of the ADC08500 is properly soldered down and the thermal vias are adequate. (The inaccuracy of
the temperature sensor is additional to the above calculation).
LAYOUT AND GROUNDING
Proper grounding and routing of all signals are essential to ensure accurate conversion. A single ground plane
should be used instead of splitting the ground plane into analog and digital areas.
38
Submit Documentation Feedback
Copyright © 2007–2013, Texas Instruments Incorporated
Product Folder Links: ADC08500
ADC08500
www.ti.com
SNAS373E –MAY 2007–REVISED APRIL 2013
Since digital switching transients are composed largely of high frequency components, the skin effect tells us that
total ground plane copper weight will have little effect upon the logic-generated noise. Total surface area is more
important than is total ground plane volume. Coupling between the typically noisy digital circuitry and the
sensitive analog circuitry can lead to poor performance that may seem impossible to isolate and remedy. The
solution is to keep the analog circuitry well separated from the digital circuitry.
High power digital components should not be located on or near any linear component or power supply trace or
plane that services analog or mixed signal components as the resulting common return current path could cause
fluctuation in the analog input “ground” return of the ADC, causing excessive noise in the conversion result.
Generally, we assume that analog and digital lines should cross each other at 90° to avoid getting digital noise
into the analog path. In high frequency systems, however, avoid crossing analog and digital lines altogether.
Clock lines should be isolated from ALL other lines, analog AND digital. The generally accepted 90° crossing
should be avoided as even a little coupling can cause problems at high frequencies. Best performance at high
frequencies is obtained with a straight signal path.
The analog input should be isolated from noisy signal traces to avoid coupling of spurious signals into the input.
This is especially important with the low level drive required of the ADC08500. Any external component (e.g., a
filter capacitor) connected between the converter's input and ground should be connected to a very clean point in
the analog ground plane. All analog circuitry (input amplifiers, filters, etc.) should be separated from any digital
components.
DYNAMIC PERFORMANCE
The ADC08500 is a.c. tested and its dynamic performance is ensured. To meet the published specifications and
avoid jitter-induced noise, the clock source driving the CLK input must exhibit low rms jitter. The allowable jitter is
a function of the input frequency and the input signal level, as described in THE CLOCK INPUTS
It is good practice to keep the ADC clock line as short as possible, to keep it well away from any other signals
and to treat it as a transmission line. Other signals can introduce jitter into the clock signal. The clock signal can
also introduce noise into the analog path if not isolated from that path.
Best dynamic performance is obtained when the exposed pad at the back of the package has a good connection
to ground. This is because this path from the die to ground is a lower impedance than offered by the package
pins.
USING THE SERIAL INTERFACE
The ADC08500 may be operated in the non-extended control (non-Serial Interface) mode or in the extended
control mode. Table 9 and Table 10 describe the functions of pins 3, 4, 14 and 127 in the non-extended control
mode and the extended control mode, respectively.
Non-Extended Control Mode Operation
Non-extended control mode operation means that the Serial Interface is not active and all controllable functions
are controlled with various pin settings. That is, the full-scale range, the power on calibration delay, the output
voltage and the input coupling (a.c. or d.c.). The non-extended control mode is used by setting pin 14 high or
low, as opposed to letting it float. Table 9 indicates the pin functions of the ADC08500 in the non-extended
control mode.
Table 9. Non-Extended Control Mode Operation
(Pin 14 High or Low)
Pin
3
Low
High
Floating
n/a
Reduced VOD
Normal VOD
4
OutEdge = Neg OutEdge = Pos
DDR
n/a
127
CalDly Short
CalDly Long
Extended
Control Mode
14
Reduced VIN
Normal VIN
Copyright © 2007–2013, Texas Instruments Incorporated
Submit Documentation Feedback
39
Product Folder Links: ADC08500
ADC08500
SNAS373E –MAY 2007–REVISED APRIL 2013
www.ti.com
Pin 3 can be either high or low in the non-extended control mode. Pin 14 must not be left floating to select this
mode. See NORMAL/EXTENDED CONTROL for more information.
Pin 4 can be high or low or can be left floating in the non-extended control mode. In the non-extended control
mode, pin 4 high or low defines the edge at which the output data transitions. See Output Edge Synchronization
for more information. If this pin is floating, the output clock (DCLK) is a DDR (Double Data Rate) clock (see
Double Data Rate) and the output edge synchronization is irrelevant since data is clocked out on both DCLK
edges.
40
Submit Documentation Feedback
Copyright © 2007–2013, Texas Instruments Incorporated
Product Folder Links: ADC08500
ADC08500
www.ti.com
SNAS373E –MAY 2007–REVISED APRIL 2013
Pin 127 in the non-extended control mode sets the calibration delay. Pin 127 is not designed to remain floating.
Table 10. Extended Control Mode Operation
(Pin 14 Floating)
Pin
3
Function
SCLK (Serial Clock)
4
SDATA (Serial Data)
127
SCS (Serial Interface Chip Select)
COMMON APPLICATION PITFALLS
Failure to write all register locations when using extended control mode. When using the serial interface, all
3 user registers must be written at least once with the default or desired values before calibration and
subsequent use of the ADC. Once all registers have been written once, other desired settings can be loaded.
Driving the inputs (analog or digital) beyond the power supply rails. For device reliability, no input should go
more than 150 mV below the ground pins or 150 mV above the supply pins. Exceeding these limits on even a
transient basis may not only cause faulty or erratic operation, but may impair device reliability. It is not
uncommon for high speed digital circuits to exhibit undershoot that goes more than a volt below ground.
Controlling the impedance of high speed lines and terminating these lines in their characteristic impedance
should control overshoot.
Care should be taken not to overdrive the inputs of the ADC08500. Such practice may lead to conversion
inaccuracies and even to device damage.
Incorrect analog input common mode voltage in the d.c. coupled mode. As discussed in The Analog Inputs
and THE ANALOG INPUT, the Input common mode voltage must remain within 50 mV of the VCMO output ,
which has a variability with temperature that must also be tracked. Distortion performance will be degraded if the
input common mode voltage is more than 50 mV from VCMO
.
Using an inadequate amplifier to drive the analog input. Use care when choosing a high frequency amplifier
to drive the ADC08500 as many high speed amplifiers will have higher distortion than will the ADC08500,
resulting in overall system performance degradation.
Driving the VBG pin to change the reference voltage. As mentioned in THE REFERENCE VOLTAGE, the
reference voltage is intended to be fixed by FSR pin or Full-Scale Voltage Adjust register settings. Over driving
this pin will not change the full scale value, but can otherwise upset operation.
Driving the clock input with an excessively high level signal. The ADC clock level should not exceed the
level described in the Operating Ratings Table or the input offset could change.
Inadequate clock levels. As described in THE CLOCK INPUTS, insufficient clock levels can result in poor
performance. Excessive clock levels could result in the introduction of an input offset.
Using a clock source with excessive jitter, using an excessively long clock signal trace, or having other
signals coupled to the clock signal trace. This will cause the sampling interval to vary, causing excessive
output noise and a reduction in SNR performance.
Failure to provide adequate heat removal. As described in Thermal Management, it is important to provide
adequate heat removal to ensure device reliability. This can be done either with adequate air flow or the use of a
simple heat sink built into the board. The backside pad should be grounded for best performance.
Copyright © 2007–2013, Texas Instruments Incorporated
Submit Documentation Feedback
41
Product Folder Links: ADC08500
ADC08500
SNAS373E –MAY 2007–REVISED APRIL 2013
www.ti.com
REVISION HISTORY
Changes from Revision D (April 2013) to Revision E
Page
•
Changed layout of National Data Sheet to TI format .......................................................................................................... 41
42
Submit Documentation Feedback
Copyright © 2007–2013, Texas Instruments Incorporated
Product Folder Links: ADC08500
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
ADC08500CIYB/NOPB
ACTIVE
HLQFP
NNB
128
60
RoHS & Green
SN
Level-3-260C-168 HR
-40 to 85
ADC08500CIYB
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Jun-2023
TRAY
L - Outer tray length without tabs
KO -
Outer
tray
height
W -
Outer
tray
width
Text
P1 - Tray unit pocket pitch
CW - Measurement for tray edge (Y direction) to corner pocket center
CL - Measurement for tray edge (X direction) to corner pocket center
Chamfer on Tray corner indicates Pin 1 orientation of packed units.
*All dimensions are nominal
Device
Package Package Pins SPQ Unit array
Max
matrix temperature
(°C)
L (mm)
W
K0
P1
CL
CW
Name
Type
(mm) (µm) (mm) (mm) (mm)
ADC08500CIYB/NOPB
NNB
HLQFP
128
60
5 X 12
150
322.6 135.9 7620 25.4
17.8 17.55
Pack Materials-Page 1
MECHANICAL DATA
NNB0128A
VNX128A (Rev B)
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license
is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you
will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these
resources.
TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with
such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for
TI products.
TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2023, Texas Instruments Incorporated
相关型号：
©2020 ICPDF网 联系我们和版权申明