ADC088S102CIMTX/NOPB [TI]
8 通道、500 kSPS 至 1MSPS、8 位模数转换器 | PW | 16 | -40 to 105;
| 型号： | ADC088S102CIMTX/NOPB |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 8 通道、500 kSPS 至 1MSPS、8 位模数转换器 | PW | 16 | -40 to 105 光电二极管 转换器 模数转换器 |
| 文件： | 总28页 (文件大小：783K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ADC088S102
www.ti.com
SNAS339B –SEPTEMBER 2005–REVISED MARCH 2013
ADC088S102 8-Channel, 500 kSPS to 1 MSPS, 8-Bit A/D Converter
Check for Samples: ADC088S102
1
FEATURES
DESCRIPTION
The ADC088S102 is a low-power, eight-channel
CMOS 8-bit analog-to-digital converter specified for
conversion throughput rates of 500 kSPS to 1 MSPS.
2
•
•
•
•
•
Eight Input Channels
Variable Power Management
Independent Analog and Digital Supplies
SPI/QSPI/MICROWIRE/DSP Compatible
Packaged in 16-Lead TSSOP
The converter is based on
a
successive-
approximation register architecture with an internal
track-and-hold circuit. It can be configured to accept
up to eight input signals at inputs IN0 through IN7.
The output serial data is straight binary and is
compatible with several standards, such as SPI,
QSPI, MICROWIRE, and many common DSP serial
interfaces.
APPLICATIONS
•
•
•
•
•
Automotive Navigation
Portable Systems
Medical Instruments
The ADC088S102 may be operated with independent
analog and digital supplies. The analog supply (VA)
can range from +2.7V to +5.25V, and the digital
supply (VD) can range from +2.7V to VA. Normal
power consumption using a +3V or +5V supply is 1.8
mW and 8.0 mW, respectively. The power-down
feature reduces the power consumption to 0.03 µW
using a +3V supply and 0.15 µW using a +5V supply.
Mobile Communications
Instrumentation and Control Systems
KEY SPECIFICATIONS
•
•
•
•
Conversion Rate: 500 kSPS to 1 MSPS
DNL (VA = VD = 5.0 V): ±0.3 LSB (max)
INL (VA = VD = 5.0 V): ±0.2 LSB (max)
Power Consumption
The ADC088S102 is packaged in a 16-lead TSSOP
package. Operation is specified over the extended
industrial temperature range of −40°C to +105°C.
–
–
3V Supply: 1.8 mW (typ)
5V Supply: 8.0 mW (typ)
Connection Diagram
CS
1
16
15
14
13
12
11
10
9
SCLK
DOUT
DIN
2
V
A
AGND
IN0
3
4
5
6
7
8
V
D
ADC088S102
IN1
DGND
IN7
IN2
IN3
IN6
IN4
IN5
Figure 1. 16-Lead TSSOP
See Package Number PW0016A
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2005–2013, Texas Instruments Incorporated
ADC088S102
SNAS339B –SEPTEMBER 2005–REVISED MARCH 2013
www.ti.com
Block Diagram
IN0
10-BIT
SUCCESSIVE
APPROXIMATION
ADC
V
.
.
.
A
MUX
T/H
AGND
AGND
IN7
V
D
SCLK
CS
CONTROL
LOGIC
ADC088S102
DIN
DOUT
DGND
Pin Descriptions and Equivalent Circuits
Pin No.
ANALOG I/O
4 - 11
Symbol
Equivalent Circuit
Description
IN0 to IN7
Analog inputs. These signals can range from 0V to VREF.
DIGITAL I/O
Digital clock input. The specified performance range of frequencies
for this input is 8 MHz to 16 MHz. This clock directly controls the
conversion and readout processes.
16
SCLK
Digital data output. The output samples are clocked out of this pin on
the falling edges of the SCLK pin.
15
14
DOUT
DIN
Digital data input. The ADC088S102's Control Register is loaded
through this pin on rising edges of the SCLK pin.
Chip select. On the falling edge of CS, a conversion process begins.
Conversions continue as long as CS is held low.
1
CS
POWER SUPPLY
Positive analog supply pin. This voltage is also used as the
reference voltage. This pin should be connected to a quiet +2.7V to
+5.25V source and bypassed to GND with 1 µF and 0.1 µF
monolithic ceramic capacitors located within 1 cm of the power pin.
2
VA
VD
Positive digital supply pin. This pin should be connected to a +2.7V
to VA supply, and bypassed to GND with a 0.1 µF monolithic ceramic
capacitor located within 1 cm of the power pin.
13
3
AGND
DGND
The ground return for the analog supply and signals.
The ground return for the digital supply and signals.
12
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
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Absolute Maximum Ratings(1)(2)
Analog Supply Voltage VA
Digital Supply Voltage VD
−0.3V to 6.5V
−0.3V to VA + 0.3V, max 6.5V
Voltage on Any Pin to GND
Input Current at Any Pin(3)
Package Input Current(3)
−0.3V to VA +0.3V
±10 mA
±20 mA
Power Dissipation at TA = 25°C
ESD Susceptibility
See(4)
Human Body Model
Machine Model
2500V
250V
For soldering specifications:
see product folder at http://www.ti.com/lit/SNOA549C
Junction Temperature
Storage Temperature
+150°C
−65°C to +150°C
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see the
Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance characteristics may
degrade when the device is not operated under the listed test conditions.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
(3) When the input voltage at any pin exceeds the power supplies (that is, VIN < AGND or VIN > VA or VD), the current at that pin should be
limited to 10 mA. The 20 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies
with an input current of 10 mA to two.
(4) The absolute maximum junction temperature (TJmax) for this device is 150°C. The maximum allowable power dissipation is dictated by
TJmax, the junction-to-ambient thermal resistance (θJA), and the ambient temperature (TA), and can be calculated using the formula
PDMAX = (TJmax − TA)/θJA. In the 16-pin TSSOP, θJA is 96°C/W, so PDMAX = 1,200 mW at 25°C and 625 mW at the maximum
operating ambient temperature of 105°C. Note that the power consumption of this device under normal operation is a maximum of 12
mW. The values for maximum power dissipation listed above will be reached only when the ADC088S102 is operated in a severe fault
condition (e.g. when input or output pins are driven beyond the power supply voltages, or the power supply polarity is reversed).
Obviously, such conditions should always be avoided.
Operating Ratings(1)(2)
Operating Temperature
VA Supply Voltage
VD Supply Voltage
Digital Input Voltage
Analog Input Voltage
Clock Frequency
−40°C ≤ TA ≤ +105°C
+2.7V to +5.25V
+2.7V to VA
0V to VA
0V to VA
8 MHz to 16 MHz
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see the
Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance characteristics may
degrade when the device is not operated under the listed test conditions.
(2) All voltages are measured with respect to GND = 0V, unless otherwise specified.
Package Thermal Resistance
Package
θJA
16-lead TSSOP on 4-layer, 2 oz. PCB
96°C / W
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ADC088S102 Converter Electrical Characteristics(1)
The following specifications apply for VA = VD = +2.7V to +5.25V, AGND = DGND = 0V, fSCLK = 8 MHz to 16 MHz, fSAMPLE
=
500 kSPS to 1 MSPS, and CL = 50pF, unless otherwise noted. Boldface limits apply for TA = TMIN to TMAX: all other limits TA
= 25°C.
Limits
Parameter
Test Conditions
Typ
Units
(2)
STATIC CONVERTER CHARACTERISTICS
Resolution with No Missing Codes
8
Bits
Integral Non-Linearity (End Point
Method)
INL
±0.05
±0.2
LSB (max)
DNL
Differential Non-Linearity
Offset Error
±0.06
+0.6
±0.3
±0.7
±0.2
±0.6
±0.2
LSB (max)
LSB (max)
LSB (max)
LSB (max)
LSB (max)
VOFF
OEM
FSE
Offset Error Match
Full Scale Error
±0.02
+0.5
FSEM
Full Scale Error Match
±0.02
DYNAMIC CONVERTER CHARACTERISTICS
FPBW
SINAD
SNR
Full Power Bandwidth (−3dB)
Signal-to-Noise Plus Distortion Ratio
Signal-to-Noise Ratio
8
MHz
dB (min)
dB (min)
dB (max)
dB (min)
Bits (min)
dB
fIN = 40.2 kHz, −0.02 dBFS
fIN = 40.2 kHz, −0.02 dBFS
fIN = 40.2 kHz, −0.02 dBFS
fIN = 40.2 kHz, −0.02 dBFS
fIN = 40.2 kHz
49.6
49.6
−71.2
67.9
7.95
69.6
49.2
49.3
−63.7
63.9
7.88
THD
Total Harmonic Distortion
SFDR
ENOB
ISO
Spurious-Free Dynamic Range
Effective Number of Bits
Channel-to-Channel Isolation
fIN = 20 kHz
Intermodulation Distortion, Second
Order Terms
fa = 19.5 kHz, fb = 20.5 kHz
fa = 19.5 kHz, fb = 20.5 kHz
−75.5
−71.8
dB
dB
IMD
Intermodulation Distortion, Third Order
Terms
ANALOG INPUT CHARACTERISTICS
VIN
Input Range
0 to VA
V
µA (max)
pF
IDCL
DC Leakage Current
±1
Track Mode
Hold Mode
33
3
CINA
Input Capacitance
pF
DIGITAL INPUT CHARACTERISTICS
VA = VD = +2.7V to +3.6V
VA = VD = +4.75V to +5.25V
VA = VD = +2.7V to +5.25V
VIN = 0V or VD
2.1
2.4
0.8
±1
4
V (min)
V (min)
VIH
Input High Voltage
VIL
Input Low Voltage
Input Current
V (max)
µA (max)
pF (max)
IIN
±0.01
2
CIND
Digital Input Capacitance
DIGITAL OUTPUT CHARACTERISTICS
VOH
Output High Voltage
ISOURCE = 200 µA
V
D − 0.5
V (min)
V (max)
µA (max)
pF (max)
VOL
Output Low Voltage
ISINK = 200 µA to 1.0 mA,
0.4
IOZH, IOZL
COUT
Hi-Impedance Output Leakage Current
Hi-Impedance Output Capacitance(1)
Output Coding
±1
2
4
Straight (Natural) Binary
(1) Data sheet min/max specification limits are ensured by design, test, or statistical analysis.
(2) Tested limits are ensured to TI's AOQL (Average Outgoing Quality Level).
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ADC088S102 Converter Electrical Characteristics(1) (continued)
The following specifications apply for VA = VD = +2.7V to +5.25V, AGND = DGND = 0V, fSCLK = 8 MHz to 16 MHz, fSAMPLE
=
500 kSPS to 1 MSPS, and CL = 50pF, unless otherwise noted. Boldface limits apply for TA = TMIN to TMAX: all other limits TA
= 25°C.
Limits
Parameter
Test Conditions
Typ
Units
(2)
POWER SUPPLY CHARACTERISTICS (CL = 10 pF)
2.7
V (min)
V (max)
VA, VD
Analog and Digital Supply Voltages
VA ≥ VD
5.25
VA = VD = +2.7V to +3.6V,
fSAMPLE = 1 MSPS, fIN = 40 kHz
0.6
1.6
10
1.2
2.2
mA (max)
mA (max)
nA
Total Supply Current
Normal Mode ( CS low)
VA = VD = +4.75V to +5.25V,
fSAMPLE = 1 MSPS, fIN = 40 kHz
IA + ID
VA = VD = +2.7V to +3.6V,
fSCLK = 0 kSPS
Total Supply Current
Shutdown Mode (CS high)
VA = VD = +4.75V to +5.25V,
fSCLK = 0 kSPS
30
nA
VA = VD = +3.0V
fSAMPLE = 1 MSPS, fIN = 40 kHz
1.8
8.0
0.03
0.15
3.6
mW (max)
mW (max)
µW
Power Consumption
Normal Mode ( CS low)
VA = VD = +5.0V
fSAMPLE = 1 MSPS, fIN = 40 kHz
11.0
PC
VA = VD = +3.0V
fSCLK = 0 kSPS
Power Consumption
Shutdown Mode (CS high)
VA = VD = +5.0V
fSCLK = 0 kSPS
µW
AC ELECTRICAL CHARACTERISTICS
fSCLKMIN
fSCLK
Minimum Clock Frequency
Maximum Clock Frequency
0.8
50
8
16
500
1
MHz (min)
MHz (max)
kSPS (min)
MSPS (max)
SCLK cycles
% (min)
Sample Rate
Continuous Mode
fS
tCONVERT
DC
Conversion (Hold) Time
SCLK Duty Cycle
13
40
60
3
30
70
% (max)
tACQ
Acquisition (Track) Time
Throughput Time
Aperture Delay
SCLK cycles
SCLK cycles
ns
Acquisition Time + Conversion Time
16
tAD
4
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ADC088S102 Timing Specifications
The following specifications apply for VA = VD = +2.7V to +5.25V, AGND = DGND = 0V, fSCLK = 8 MHz to 16 MHz, fSAMPLE
=
500 kSPS to 1 MSPS, and CL = 50pF. Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25°C.
Limits
Parameter
Test Conditions
Typ
0
Units
(1)
tCSH
tCSS
tEN
CS Hold Time after SCLK Rising Edge
10
ns (min)
ns (min)
CS Setup Time prior to SCLK Rising
Edge
5
10
30
27
CS Falling Edge to DOUT enabled
5
ns (max)
ns (max)
DOUT Access Time after SCLK Falling
Edge
tDACC
17
DOUT Hold Time after SCLK Falling
Edge
tDHLD
tDS
4
ns (typ)
ns (min)
DIN Setup Time prior to SCLK Rising
Edge
3
3
10
tDH
tCH
tCL
DIN Hold Time after SCLK Rising Edge
SCLK High Time
10
0.4 x tSCLK
0.4 x tSCLK
20
ns (min)
ns (min)
ns (min)
ns (max)
ns (max)
SCLK Low Time
DOUT falling
DOUT rising
2.4
0.9
CS Rising Edge to DOUT High-
Impedance
tDIS
20
(1) Tested limits are ensured to TI's AOQL (Average Outgoing Quality Level).
Timing Diagrams
Power
Down
Power Up
Power Up
Hold
Track
Track
Hold
CS
8
9
10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
SCLK
Control register
ADD2
ADD1
ADD0
ADD2
ADD1
ADD0
DIN
DOUT
FOUR ZEROS
DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
SIX ZEROS
DB9 DB8 DB7
Figure 2. ADC088S102 Operational Timing Diagram
CS
t
t
CONVERT
ACQ
t
CH
SCLK
1
2
3
4
5
6
7
8
DACC
14
15
16
t
t
t
DIS
t
t
DHLD
CL
EN
DOUT
FOUR ZEROS
DB9
DB8
DB7
DB6
B1 DB0
TWO ZEROS
t
DH
t
DS
DONTC
DONTC DONTC
ADD2
ADD1
ADD0
DONTC DONTC
DIN
Figure 3. ADC088S102 Serial Timing Diagram
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SCLK
CS
t
CSS
t
CSH
CS
Figure 4. SCLK and CS Timing Parameters
Specification Definitions
ACQUISITION TIME is the time required for the ADC to acquire the input voltage. During this time, the hold
capacitor is charged by the input voltage.
APERTURE DELAY is the time between the fourth falling edge of SCLK and the time when the input signal is
internally acquired or held for conversion.
CONVERSION TIME is the time required, after the input voltage is acquired, for the ADC to convert the input
voltage to a digital word.
CHANNEL-TO-CHANNEL ISOLATION is resistance to coupling of energy from one channel into another
channel.
CROSSTALK is the coupling of energy from one channel into another channel. This is similar to Channel-to-
Channel Isolation, except for the sign of the data.
DIFFERENTIAL NON-LINEARITY (DNL) is the measure of the maximum deviation from the ideal step size of 1
LSB.
DUTY CYCLE is the ratio of the time that a repetitive digital waveform is high to the total time of one period. The
specification here refers to the SCLK.
EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE BITS) is another method of specifying Signal-to-Noise
and Distortion or SINAD. ENOB is defined as (SINAD - 1.76) / 6.02 and says that the converter is equivalent to a
perfect ADC of this (ENOB) number of bits.
FULL POWER BANDWIDTH is a measure of the frequency at which the reconstructed output fundamental
drops 3 dB below its low frequency value for a full scale input.
GAIN ERROR is the deviation of the last code transition (111...110) to (111...111) from the ideal (VREF - 1.5
LSB), after adjusting for offset error.
INTEGRAL NON-LINEARITY (INL) is a measure of the deviation of each individual code from a line drawn from
negative full scale (½ LSB below the first code transition) through positive full scale (½ LSB above the last code
transition). The deviation of any given code from this straight line is measured from the center of that code value.
INTERMODULATION DISTORTION (IMD) is the creation of additional spectral components as a result of two
sinusoidal frequencies being applied to an individual ADC input at the same time. It is defined as the ratio of the
power in either the second or the third order intermodulation products to the sum of the power in both of the
original frequencies. Second order products are fa ± fb, where fa and fb are the two sine wave input frequencies.
Third order products are (2fa ± fb ) and (fa ± 2fb). IMD is usually expressed in dB.
MISSING CODES are those output codes that will never appear at the ADC outputs. The ADC088S102 is
specified not to have any missing codes.
OFFSET ERROR is the deviation of the first code transition (000...000) to (000...001) from the ideal (i.e. GND +
0.5 LSB).
SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in dB, of the rms value of the input signal to the rms
value of the sum of all other spectral components below one-half the sampling frequency, not including
harmonics or d.c.
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SIGNAL TO NOISE PLUS DISTORTION (S/N+D or SINAD) Is the ratio, expressed in dB, of the rms value of the
input signal to the rms value of all of the other spectral components below half the clock frequency, including
harmonics but excluding d.c.
SPURIOUS FREE DYNAMIC RANGE (SFDR) is the difference, expressed in dB, between the rms values of the
input signal and the peak spurious signal where a spurious signal is any signal present in the output spectrum
that is not present at the input, including harmonics but excluding d.c.
TOTAL HARMONIC DISTORTION (THD) is the ratio, expressed in dBc, of the rms total of the first five harmonic
components at the output to the rms level of the input signal frequency as seen at the output. THD is calculated
as
2
2
A
+3+ A
f2
f6
THD = 20 x log
10
2
A
f1
where
•
Af1 is the RMS power of the input frequency at the output and Af2 through Af6 are the RMS power in the first 5
harmonic frequencies.
THROUGHPUT TIME is the minimum time required between the start of two successive conversions. It is the
acquisition time plus the conversion time.
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Typical Performance Characteristics
VA = VD = +5.0V, TA = +25°C, fSAMPLE = 1 MSPS, fSCLK = 16 MHz, fIN = 40.2 kHz unless otherwise stated.
DNL
DNL
Figure 5.
INL
Figure 6.
INL
Figure 7.
Figure 8.
DNL vs. Supply
INL vs. Supply
Figure 9.
Figure 10.
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Typical Performance Characteristics (continued)
VA = VD = +5.0V, TA = +25°C, fSAMPLE = 1 MSPS, fSCLK = 16 MHz, fIN = 40.2 kHz unless otherwise stated.
SNR vs. Supply
THD vs. Supply
Figure 11.
Figure 12.
ENOB vs. Supply
DNL vs. VD with VA = 5.0 V
Figure 13.
Figure 14.
INL vs. VD with VA = 5.0 V
DNL vs. SCLK Duty Cycle
Figure 15.
Figure 16.
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Typical Performance Characteristics (continued)
VA = VD = +5.0V, TA = +25°C, fSAMPLE = 1 MSPS, fSCLK = 16 MHz, fIN = 40.2 kHz unless otherwise stated.
INL vs. SCLK Duty Cycle
SNR vs. SCLK Duty Cycle
Figure 17.
Figure 18.
THD vs. SCLK Duty Cycle
ENOB vs. SCLK Duty Cycle
Figure 19.
Figure 20.
DNL vs. SCLK
INL vs. SCLK
Figure 21.
Figure 22.
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Typical Performance Characteristics (continued)
VA = VD = +5.0V, TA = +25°C, fSAMPLE = 1 MSPS, fSCLK = 16 MHz, fIN = 40.2 kHz unless otherwise stated.
SNR vs. SCLK
THD vs. SCLK
Figure 23.
Figure 24.
ENOB vs. SCLK
DNL vs. Temperature
Figure 25.
Figure 26.
INL vs. Temperature
SNR vs. Temperature
Figure 27.
Figure 28.
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Typical Performance Characteristics (continued)
VA = VD = +5.0V, TA = +25°C, fSAMPLE = 1 MSPS, fSCLK = 16 MHz, fIN = 40.2 kHz unless otherwise stated.
THD vs. Temperature
ENOB vs. Temperature
Figure 29.
Figure 30.
SNR vs. Input Frequency
THD vs. Input Frequency
Figure 31.
Figure 32.
ENOB vs. Input Frequency
Power Consumption vs. SCLK
Figure 33.
Figure 34.
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FUNCTIONAL DESCRIPTION
The ADC088S102 is a successive-approximation analog-to-digital converter designed around a charge-
redistribution digital-to-analog converter.
ADC088S102 OPERATION
Simplified schematics of the ADC088S102 in both track and hold operation are shown in Figure 35 and Figure 36
respectively. In Figure 35, the ADC088S102 is in track mode: switch SW1 connects the sampling capacitor to
one of eight analog input channels through the multiplexer, and SW2 balances the comparator inputs. The
ADC088S102 is in this state for the first three SCLK cycles after CS is brought low.
Figure 36 shows the ADC088S102 in hold mode: switch SW1 connects the sampling capacitor to ground,
maintaining the sampled voltage, and switch SW2 unbalances the comparator. The control logic then instructs
the charge-redistribution DAC to add or subtract fixed amounts of charge to or from the sampling capacitor until
the comparator is balanced. When the comparator is balanced, the digital word supplied to the DAC is the digital
representation of the analog input voltage. The ADC088S102 is in this state for the last thirteen SCLK cycles
after CS is brought low.
IN0
CHARGE
REDISTRIBUTION
DAC
MUX
SAMPLING
CAPACITOR
CONTRO
SW1
+
-
IN7
L
LOGI
C
SW2
AGND
V
/2
A
Figure 35. ADC088S102 in Track Mode
IN0
IN7
CHARGE
REDISTRIBUTION
DAC
MUX
SAMPLING
CAPACITOR
SW1
+
-
CONTROL
LOGIC
SW2
AGND
V
/2
A
Figure 36. ADC088S102 in Hold Mode
SERIAL INTERFACE
An operational timing diagram and a serial interface timing diagram for the ADC088S102 are shown in The
Timing Diagrams section. CS, chip select, initiates conversions and frames the serial data transfers. SCLK (serial
clock) controls both the conversion process and the timing of serial data. DOUT is the serial data output pin,
where a conversion result is sent as a serial data stream, MSB first. Data to be written to the ADC088S102's
Control Register is placed on DIN, the serial data input pin. New data is written to DIN with each conversion.
A serial frame is initiated on the falling edge of CS and ends on the rising edge of CS. Each frame must contain
an integer multiple of 16 rising SCLK edges. The ADC's DOUT pin is in a high impedance state when CS is high
and is active when CS is low. Thus, CS acts as an output enable. Similarly, SCLK is internally gated off when CS
is brought high.
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SNAS339B –SEPTEMBER 2005–REVISED MARCH 2013
During the first 3 cycles of SCLK, the ADC is in the track mode, acquiring the input voltage. For the next 13
SCLK cycles the conversion is accomplished and the data is clocked out. SCLK falling edges 1 through 4 clock
out leading zeros, falling edges 5 through 12 clock out the conversion result, MSB first, and falling edges 13
through 16 clock out trailing zeros. If there is more than one conversion in a frame (continuous conversion
mode), the ADC will re-enter the track mode on the falling edge of SCLK after the N*16th rising edge of SCLK
and re-enter the hold/convert mode on the N*16+4th falling edge of SCLK. "N" is an integer value.
The ADC088S102 enters track mode under three different conditions. In Figure 2, CS goes low with SCLK high
and the ADC enters track mode on the first falling edge of SCLK. In the second condition, CS goes low with
SCLK low. Under this condition, the ADC automatically enters track mode and the falling edge of CS is seen as
the first falling edge of SCLK. In the third condition, CS and SCLK go low simultaneously and the ADC enters
track mode. While there is no timing restriction with respect to the falling edges of CS and SCLK, see Figure 4
for setup and hold time requirements for the falling edge of CS with respect to the rising edge of SCLK.
During each conversion, data is clocked into a control register through the DIN pin on the first 8 rising edges of
SCLK after the fall of CS. The control register is loaded with data indicating the input channel to be converted on
the subsequent conversion (see Table 1 Table 2 Table 3).
The user does not need to incorporate a power-up delay or dummy conversions as the ADC088S102 is able to
acquire the input signal to full resolution in the first conversion immediately following power-up. The first
conversion result after power-up will be that of IN0.
Table 1. Control Register Bits
Bit 7 (MSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
DONTC
DONTC
ADD2
ADD1
ADD0
DONTC
DONTC
DONTC
Table 2. Control Register Bit Descriptions
Bit #:
Symbol:
Description
7, 6, 2, 1, 0
DONTC
ADD2
ADD1
ADD0
Don't care. The values of these bits do not affect the device.
5
4
3
These three bits determine which input channel will be sampled and converted at the next
conversion cycle. The mapping between codes and channels is shown in Table 3.
Table 3. Input Channel Selection
ADD2
ADD1
ADD0
Input Channel
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
IN0 (Default)
IN1
IN2
IN3
IN4
IN5
IN6
IN7
ADC088S102 TRANSFER FUNCTION
The output format of the ADC088S102 is straight binary. Code transitions occur midway between successive
integer LSB values. The LSB width for the ADC088S102 is VA / 256. The ideal transfer characteristic is shown in
Figure 37. The transition from an output code of 0000 0000 to a code of 0000 0001 is at 1/2 LSB, or a voltage of
VA / 512. Other code transitions occur at steps of one LSB.
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111...111
111...110
111...000
011...111
ö
1 LSB = VA / 1024
000...010
000...001
000...000
+VA - 1.5LSB
0.5LSB
0V
ANALOG INPUT
Figure 37. Ideal Transfer Characteristic
ANALOG INPUTS
An equivalent circuit for one of the ADC088S102's input channels is shown in Figure 38. Diodes D1 and D2
provide ESD protection for the analog inputs. The operating range for the analog inputs is 0 V to VA. Going
beyond this range will cause the ESD diodes to conduct and result in erratic operation.
The capacitor C1 in Figure 38 has a typical value of 3 pF and is mainly the package pin capacitance. Resistor R1
is the on resistance of the multiplexer and track / hold switch and is typically 500 ohms. Capacitor C2 is the
ADC088S102 sampling capacitor, and is typically 30 pF. The ADC088S102 will deliver best performance when
driven by a low-impedance source (less than 100 ohms). This is especially important when using the
ADC088S102 to sample dynamic signals. Also important when sampling dynamic signals is a band-pass or low-
pass filter which reduces harmonics and noise in the input. These filters are often referred to as anti-aliasing
filters.
V
A
C2
30 pF
D1
D2
R1
V
IN
C1
3 pF
Conversion Phase - Switch Open
Track Phase - Switch Closed
Figure 38. Equivalent Input Circuit
DIGITAL INPUTS AND OUTPUTS
The ADC088S102's digital inputs (SCLK, CS, and DIN) have an operating range of 0 V to VA. They are not prone
to latch-up and may be asserted before the digital supply (VD) without any risk. The digital output (DOUT)
operating range is controlled by VD. The output high voltage is VD - 0.5V (min) while the output low voltage is
0.4V (max).
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ADC088S102
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SNAS339B –SEPTEMBER 2005–REVISED MARCH 2013
Applications Information
TYPICAL APPLICATION CIRCUIT
A typical application is shown in Figure 39. The split analog and digital supply pins are both powered in this
example by the TI LP2950 low-dropout voltage regulator. The analog supply is bypassed with a capacitor
network located close to the ADC088S102. The digital supply is separated from the analog supply by an isolation
resistor and bypassed with additional capacitors. The ADC088S102 uses the analog supply (VA) as its reference
voltage, so it is very important that VA be kept as clean as possible. Due to the low power requirements of the
ADC088S102, it is also possible to use a precision reference as a power supply.
To minimize the error caused by the changing input capacitance of the ADC088S102, a capacitor is connected
from each input pin to ground. The capacitor, which is much larger than the input capacitance of the
ADC088S102 when in track mode, provides the current to quickly charge the sampling capacitor of the
ADC088S102. An isolation resistor is added to isolate the load capacitance from the input source.
51W
LP2950
5V
1 mF
0.1 mF
1.0 mF
0.1 mF
1.0 mF
0.1 mF
V
D
V
A
22W
SCLK
CS
INPUT
IN0
.
.
.
MICROPROCESSOR
DSP
1 nF
ADC088S102
DIN
IN7
DOUT
DGND
AGND
Figure 39. Typical Application Circuit
POWER SUPPLY CONSIDERATIONS
There are three major power supply concerns with this product: power supply sequencing, power management,
and the effect of digital supply noise on the analog supply.
Power Supply Sequence
The ADC088S102 is a dual-supply device. The two supply pins share ESD resources, so care must be exercised
to ensure that the power is applied in the correct sequence. To avoid turning on the ESD diodes, the digital
supply (VD) cannot exceed the analog supply (VA) by more than 300 mV, not even on a transient basis.
Therefore, VA must ramp up before or concurrently with VD.
Power Management
The ADC088S102 is fully powered-up whenever CS is low and fully powered-down whenever CS is high, with
one exception. If operating in continuous conversion mode, the ADC088S102 automatically enters power-down
mode between SCLK's 16th falling edge of a conversion and the SCLK's 1st falling edge of the subsequent
conversion (see Figure 2).
In continuous conversion mode, the ADC088S102 can perform multiple conversions back to back. Each
conversion requires 16 SCLK cycles and the ADC088S102 will perform conversions continuously as long as CS
is held low. Continuous mode offers maximum throughput.
In burst mode, the user may trade off throughput for power consumption by performing fewer conversions per
unit time. This means spending more time in power-down mode and less time in normal mode. By utilizing this
technique, the user can achieve very low sample rates while still utilizing an SCLK frequency within the electrical
specifications. The Power Consumption vs. SCLK curve in the Typical Performance Curves section shows the
typical power consumption of the ADC088S102. To calculate the power consumption (PC), simply multiply the
fraction of time spent in the normal mode (tN) by the normal mode power consumption (PN), and add the fraction
of time spent in shutdown mode (tS) multiplied by the shutdown mode power consumption (PS) as shown in
Figure 40.
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tN
tS
PC =
ì PN +
ì PS
tN + tS
tN + tS
Figure 40. Power Consumption Equation
Power Supply Noise Considerations
The charging of any output load capacitance requires current from the digital supply, VD. The current pulses
required from the supply to charge the output capacitance will cause voltage variations on the digital supply. If
these variations are large enough, they could degrade SNR and SINAD performance of the ADC. Furthermore, if
the analog and digital supplies are tied directly together, the noise on the digital supply will be coupled directly
into the analog supply, causing greater performance degradation than would noise on the digital supply alone.
Similarly, discharging the output capacitance when the digital output goes from a logic high to a logic low will
dump current into the die substrate, which is resistive. Load discharge currents will cause "ground bounce" noise
in the substrate that will degrade noise performance if that current is large enough. The larger the output
capacitance, the more current flows through the die substrate and the greater the noise coupled into the analog
channel.
The first solution to keeping digital noise out of the analog supply is to decouple the analog and digital supplies
from each other or use separate supplies for them. To keep noise out of the digital supply, keep the output load
capacitance as small as practical. If the load capacitance is greater than 50 pF, use a 100 Ω series resistor at
the ADC output, located as close to the ADC output pin as practical. This will limit the charge and discharge
current of the output capacitance and improve noise performance. Since the series resistor and the load
capacitance form a low frequency pole, verify signal integrity once the series resistor has been added.
LAYOUT AND GROUNDING
Capacitive coupling between the noisy digital circuitry and the sensitive analog circuitry can lead to poor
performance. The solution is to keep the analog circuitry separated from the digital circuitry and the clock line as
short as possible.
Digital circuits create substantial supply and ground current transients. The logic noise generated could have
significant impact upon system noise performance. To avoid performance degradation of the ADC088S102 due
to supply noise, do not use the same supply for the ADC088S102 that is used for digital logic.
Generally, analog and digital lines should cross each other at 90° to avoid crosstalk. However, to maximize
accuracy in high resolution systems, avoid crossing analog and digital lines altogether. It is important to keep
clock lines as short as possible and isolated from ALL other lines, including other digital lines. In addition, the
clock line should also be treated as a transmission line and be properly terminated.
The analog input should be isolated from noisy signal traces to avoid coupling of spurious signals into the input.
Any external component (e.g., a filter capacitor) connected between the converter's input pins and ground or to
the reference input pin and ground should be connected to a very clean point in the ground plane.
We recommend the use of a single, uniform ground plane and the use of split power planes. The power planes
should be located within the same board layer. All analog circuitry (input amplifiers, filters, reference
components, etc.) should be placed over the analog power plane. All digital circuitry and I/O lines should be
placed over the digital power plane. Furthermore, all components in the reference circuitry and the input signal
chain that are connected to ground should be connected together with short traces and enter the analog ground
plane at a single, quiet point.
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ADC088S102
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SNAS339B –SEPTEMBER 2005–REVISED MARCH 2013
REVISION HISTORY
Changes from Revision A (March 2013) to Revision B
Page
•
Changed layout of National Data Sheet to TI format .......................................................................................................... 18
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
ADC088S102CIMT/NOPB
ADC088S102CIMTX/NOPB
ACTIVE
TSSOP
TSSOP
PW
16
16
92
RoHS & Green
SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 105
-40 to 105
088S102
CIMT
ACTIVE
PW
2500 RoHS & Green
SN
088S102
CIMT
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
ADC088S102CIMTX/
NOPB
TSSOP
PW
16
2500
330.0
12.4
6.95
5.6
1.6
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
TSSOP PW 16
SPQ
Length (mm) Width (mm) Height (mm)
367.0 367.0 35.0
ADC088S102CIMTX/
NOPB
2500
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TUBE
T - Tube
height
L - Tube length
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device
Package Name Package Type
PW TSSOP
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
ADC088S102CIMT/NOPB
16
92
495
8
2514.6
4.06
Pack Materials-Page 3
PACKAGE OUTLINE
PW0016A
TSSOP - 1.2 mm max height
S
C
A
L
E
2
.
5
0
0
SMALL OUTLINE PACKAGE
SEATING
PLANE
C
6.6
6.2
TYP
A
0.1 C
PIN 1 INDEX AREA
14X 0.65
16
1
2X
5.1
4.9
4.55
NOTE 3
8
9
0.30
16X
4.5
4.3
NOTE 4
1.2 MAX
0.19
B
0.1
C A B
(0.15) TYP
SEE DETAIL A
0.25
GAGE PLANE
0.15
0.05
0.75
0.50
A
20
0 -8
DETAIL A
TYPICAL
4220204/A 02/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.
www.ti.com
EXAMPLE BOARD LAYOUT
PW0016A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
SYMM
16X (1.5)
(R0.05) TYP
16
1
16X (0.45)
SYMM
14X (0.65)
8
9
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
15.000
(PREFERRED)
SOLDER MASK DETAILS
4220204/A 02/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
PW0016A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
16X (1.5)
SYMM
(R0.05) TYP
16
1
16X (0.45)
SYMM
14X (0.65)
8
9
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
4220204/A 02/2017
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license
is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you
will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these
resources.
TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with
such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for
TI products.
TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2022, Texas Instruments Incorporated
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