ADC08DJ5200RFAAVT [TI]
具有双通道 5.2GSPS 或单通道 10.4GSPS 的射频采样 8 位 ADC | AAV | 144 | -40 to 85;型号: | ADC08DJ5200RFAAVT |
厂家: | TEXAS INSTRUMENTS |
描述: | 具有双通道 5.2GSPS 或单通道 10.4GSPS 的射频采样 8 位 ADC | AAV | 144 | -40 to 85 射频 |
文件: | 总163页 (文件大小:6388K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
ADC08DJ5200RF
ZHCSN42A –AUGUST 2021 –REVISED MAY 2022
ADC08DJ5200RF 10.4GSPS 单通道或5.2GSPS 双通道、8 位
射频采样模数转换器(ADC)
1 特性
3 说明
• ADC 内核:
ADC08DJ5200RF 器件是一款射频采样千兆采样模数
转换器 (ADC),可对从直流到 10GHz 以上的输入频率
进行直接采样。ADC08DJ5200RF 可配置为双通道
5.2GSPS ADC 或单通道 10.4GSPS ADC。支持高达
10GHz 的可用输入频率范围,可对频率捷变系统的
L、S、C 和X 频带进行直接射频采样。
– 8 位分辨率
– 单通道模式下的采样率高达10.4 GSPS
– 双通道模式下的采样率高达5.2 GSPS
• 性能规格:
– 本底噪声(-20 dBFS,VFS = 1VPP-DIFF):
• 双通道模式:-143.4 dBFS/Hz
• 单通道模式:-146.2 dBFS/Hz
– ENOB(双通道,FIN = 2.4GHz,TYP):7.8
位
ADC08DJ5200RF 使用具有多达 16 个串行通道的高速
JESD204C 输出接口,支持高达 17.16Gbps 的线路速
率。通过 JESD204C 子类 1 支持确定性延迟和多器件
同步。JESD204C 接口可进行配置,对线路速率和通
道数进行权衡。支持 8b/10b 和 64b/66b 数据编码方
案。64b/66b 编码支持前向纠错 (FEC),可改进误码
率。此接口向后兼容JESD204B 接收器。
• VCMI 为0V 时的缓冲模拟输入:
– 模拟输入带宽(-3dB):8.1 GHz
– 可用输入频率范围:> 10 GHz
– 满量程输入电压(VFS,默认值):0.8 VPP
• 无噪声孔径延迟(tAD) 调节:
无噪声孔径延迟调节和 SYSREF 窗口等创新的同步特
性可简化多通道应用的系统设计。可编程 FIR 滤波器
可实现片上均衡。
– 精确采样控制:19 fs 步长
– 简化同步和交错
器件信息
封装(1)
– 温度和电压不变延迟
• 简便易用的同步特性:
– 自动SYSREF 计时校准
– 样片标记时间戳
• JESD204C 串行数据接口:
封装尺寸(标称值)
器件型号
ADC08DJ5200RF
FCBGA (144) 10.00mm × 10.00mm
(1) 如需了解所有可用封装,请参阅产品说明书末尾的封装选项附
录。
– 最大通道速率:17.16 Gbps
– 支持64b/66b 和8b/10b 编码
– 8b/10b 模式兼容JESD204B
• 峰值射频输入功率(Diff):+26.5 dBm(+ 27.5
dBFS,560x 满量程功率)
• 可实现均衡的可编程FIR 滤波器
• 功耗:3.8W
• 电源:1.1V/1.9V
2 应用
• 示波器和宽带数字转换器
• 通信测试仪(802.11ad,5G)
• 电子战(信号情报、电子情报)
• 卫星通信(SATCOM)
• 射频采样软件定义无线电(SDR)
• 光谱测量
ADC08DJ5200RF 方框图
本文档旨在为方便起见,提供有关TI 产品中文版本的信息,以确认产品的概要。有关适用的官方英文版本的最新信息,请访问
www.ti.com,其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前,请务必参考最新版本的英文版本。
English Data Sheet: SLVSEO1
ADC08DJ5200RF
ZHCSN42A –AUGUST 2021 –REVISED MAY 2022
www.ti.com.cn
Table of Contents
7.4 Device Functional Modes..........................................76
7.5 Programming............................................................ 90
7.6 SPI Register Map......................................................92
8 Application Information Disclaimer...........................145
8.1 Application Information........................................... 145
8.2 Typical Applications................................................ 145
8.3 Initialization Set Up................................................. 147
9 Power Supply Recommendations..............................148
9.1 Power Sequencing..................................................149
10 Layout.........................................................................150
10.1 Layout Guidelines................................................. 150
10.2 Layout Example.................................................... 152
11 Device and Documentation Support........................155
11.1 Device Support......................................................155
11.2 Documentation Support........................................ 155
11.3 Receiving Notification of Documentation Updates156
11.4 Support Resources............................................... 156
11.5 Trademarks........................................................... 156
11.6 Electrostatic Discharge Caution............................156
11.7 术语表................................................................... 156
12 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 8
6.1 Absolute Maximum Ratings........................................ 8
6.2 ESD Ratings............................................................... 8
6.3 Recommended Operating Conditions.........................9
6.4 Thermal Information....................................................9
6.5 Electrical Characteristics: DC Specifications............ 10
6.6 Electrical Characteristics: Power Consumption........ 12
6.7 Electrical Characteristics: AC Specifications
(Dual-Channel Mode)..................................................13
6.8 Electrical Characteristics: AC Specifications
(Single-Channel Mode)............................................... 19
6.9 Timing Requirements................................................26
6.10 Switching Characteristics........................................27
6.11 Typical Characteristics............................................ 30
7 Detailed Description......................................................52
7.1 Overview...................................................................52
7.2 Functional Block Diagram.........................................53
7.3 Feature Description...................................................54
Information.................................................................. 156
4 Revision History
注:以前版本的页码可能与当前版本的页码不同
Changes from Revision * (August 2021) to Revision A (May 2022)
Page
• Added plots 图6-123 through 图6-126 to show overdrive recovery................................................................30
• Change four TAD_COARSE LSBs per 256 tCLK cycles to 384 tCLK cycles in Aperture Delay Ramp Control
(TAD_RAMP) ...................................................................................................................................................59
• Changed TAD Register to properly show TAD_FINE register bits....................................................................92
• Changed PFIR_AB2 to PFIR_B2 in PFIR_B2 ................................................................................................. 92
• Added the JMODE register table information................................................................................................... 92
• Removed registers 0x102-0x152 as these should be reserved .......................................................................92
• Added note 1 to 表7-130..................................................................................................................................92
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5 Pin Configuration and Functions
1
2
3
4
5
6
7
8
9
10
11
12
A
B
C
D
E
F
AGND
AGND
AGND
INA+
INAœ
AGND
AGND
DA3+
DA3œ
DA2+
DA2œ
DGND
TMSTP+
TMSTPœ
AGND
AGND
SYNCSE
VA11
AGND
AGND
VA19
VA19
VA19
VA19
VA19
VA19
VA19
VA19
AGND
INB+
AGND
VA11
VA11
VA11
VA11
VA11
VA11
VA11
VA11
AGND
INBœ
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
PD
AGND
NCOA0
NCOA1
CALTRIG
CALSTAT
VD11
DA7+
ORA0
ORA1
SCS
DA7œ
VD11
DGND
VD11
DGND
DGND
VD11
DGND
VD11
DB7œ
DB3œ
DA6+
VD11
DGND
VD11
DGND
DGND
VD11
DGND
VD11
DB6+
DB2+
DA6œ
DA5+
DA5œ
DA4+
DA4œ
DB4œ
DB4+
DB5œ
DB5+
DB6œ
DB2œ
DGND
DA1+
DA1œ
DA0+
DA0œ
DB0œ
DB0+
DB1œ
DB1+
DGND
BG
VA11
AGND
VA19
VA19
CLK+
AGND
AGND
VA19
AGND
AGND
VA19
SCLK
G
H
J
CLKœ
SDI
AGND
VD11
SDO
AGND
VA11
VA11
NCOB1
NCOB0
AGND
ORB1
ORB0
DB7+
DB3+
K
SYSREF+
SYSREFœ
AGND
TDIODE+
AGND
AGND
TDIODEœ
AGND
AGND
L
AGND
AGND
M
AGND
DGND
Not to scale
图5-1. AAV Package, 144-Ball Flip Chip BGA, Top View
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表5-1. Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
A1, A2, A3,
A6, A7, B2,
B3, B4, B5,
B6, B7, C6,
D1, D6, E1,
E6, F2, F3, F6,
G2, G3, G6,
H1, H6, J1, J6,
L2, L3, L4, L5,
L6, L7, M1,
M2, M3, M6,
M7
Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit
board.
AGND
—
Band-gap voltage output. This pin is capable of sourcing only small currents and driving limited
capacitive loads, as specified in the Recommended Operating Conditions table. This pin can be
left disconnected if not used.
BG
C3
F7
E7
O
O
I
Foreground calibration status output or device alarm output. Functionality is programmed through
CAL_STATUS_SEL. This pin can be left disconnected if not used.
CALSTAT
CALTRIG
Foreground calibration trigger input. This pin is only used if hardware calibration triggering is
selected in CAL_TRIG_EN, otherwise software triggering is performed using CAL_SOFT_TRIG.
Tie this pin to GND if not used.
Device (sampling) clock positive input. The clock signal is strongly recommended to be AC-
coupled to this input for best performance. In single-channel mode, the analog input signal is
sampled on both the rising and falling edges. In dual-channel mode, the analog signal is sampled
on the rising edge. This differential input has an internal untrimmed 100-Ωdifferential termination
and is self-biased to the optimal input common-mode voltage as long as DEVCLK_LVPECL_EN is
set to 0.
CLK+
F1
I
Device (sampling) clock negative input. TI strongly recommends using AC-coupling for best
performance.
G1
E12
F12
C12
D12
A10
A11
A8
I
CLK–
DA0+
DA0–
DA1+
DA1–
DA2+
DA2–
DA3+
DA3–
DA4+
DA4–
DA5+
High-speed serialized data output for channel A, lane 0, positive connection. This differential
output must be AC-coupled and must always be terminated with a 100-Ωdifferential termination
at the receiver. This pin can be left disconnected if not used.
O
O
O
O
O
O
O
O
O
O
O
High-speed serialized data output for channel A, lane 0, negative connection. This pin can be left
disconnected if not used.
High-speed serialized data output for channel A, lane 1, positive connection. This differential
output must be AC-coupled and must always be terminated with a 100-Ωdifferential termination
at the receiver. This pin can be left disconnected if not used.
High-speed serialized data output for channel A, lane 1, negative connection. This pin can be left
disconnected if not used.
High-speed serialized-data output for channel A, lane 2, positive connection. This differential
output must be AC-coupled and must always be terminated with a 100-Ωdifferential termination
at the receiver. This pin can be left disconnected if not used.
High-speed serialized-data output for channel A, lane 2, negative connection. This pin can be left
disconnected if not used.
High-speed serialized-data output for channel A, lane 3, positive connection. This differential
output must be AC-coupled and must always be terminated with a 100-Ωdifferential termination
at the receiver. This pin can be left disconnected if not used.
High-speed serialized-data output for channel A, lane 3, negative connection. This pin can be left
disconnected if not used.
A9
High-speed serialized data output for channel A, lane 4, positive connection. This differential
output must be AC-coupled and must always be terminated with a 100-Ωdifferential termination
at the receiver. This pin can be left disconnected if not used.
E11
F11
C11
High-speed serialized data output for channel A, lane 4, negative connection. This pin can be left
disconnected if not used.
High-speed serialized data output for channel A, lane 5, positive connection. This differential
output must be AC-coupled and must always be terminated with a 100-Ωdifferential termination
at the receiver. This pin can be left disconnected if not used.
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表5-1. Pin Functions (continued)
PIN
I/O
DESCRIPTION
NAME
NO.
High-speed serialized data output for channel A, lane 5, negative connection. This pin can be left
disconnected if not used.
D11
O
DA5–
High-speed serialized data output for channel A, lane 6, positive connection. This differential
output must be AC-coupled and must always be terminated with a 100-Ωdifferential termination
at the receiver. This pin can be left disconnected if not used.
DA6+
DA6–
DA7+
DA7–
DB0+
DB0–
DB1+
DB1–
DB2+
DB2–
DB3+
DB3–
DB4+
DB4–
DB5+
DB5–
DB6+
DB6–
DB7+
DB7–
B10
B11
B8
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
High-speed serialized data output for channel A, lane 6, negative connection. This pin can be left
disconnected if not used.
High-speed serialized data output for channel A, lane 7, positive connection. This differential
output must be AC-coupled and must always be terminated with a 100-Ωdifferential termination
at the receiver. This pin can be left disconnected if not used.
High-speed serialized data output for channel A, lane 7, negative connection. This pin can be left
disconnected if not used.
B9
High-speed serialized data output for channel B, lane 0, positive connection. This differential
output must be AC-coupled and must always be terminated with a 100-Ωdifferential termination
at the receiver. This pin can be left disconnected if not used.
H12
G12
K12
J12
M10
M11
M8
High-speed serialized data output for channel B, lane 0, negative connection. This pin can be left
disconnected if not used.
High-speed serialized data output for channel B, lane 1, positive connection. This differential
output must be AC-coupled and must always be terminated with a 100-Ωdifferential termination
at the receiver. This pin can be left disconnected if not used.
High-speed serialized data output for channel B, lane 1, negative connection. This pin can be left
disconnected if not used.
High-speed serialized data output for channel B, lane 2, positive connection. This differential
output must be AC-coupled and must always be terminated with a 100-Ωdifferential termination
at the receiver. This pin can be left disconnected if not used.
High-speed serialized data output for channel B, lane 2, negative connection. This pin can be left
disconnected if not used.
High-speed serialized data output for channel B, lane 3, positive connection. This differential
output must be AC-coupled and must always be terminated with a 100-Ωdifferential termination
at the receiver. This pin can be left disconnected if not used.
High-speed serialized data output for channel B, lane 3, negative connection. This pin can be left
disconnected if not used.
M9
High-speed serialized data output for channel B, lane 4, positive connection. This differential
output must be AC-coupled and must always be terminated with a 100-Ωdifferential termination
at the receiver. This pin can be left disconnected if not used.
H11
G11
K11
J11
L10
L11
L8
High-speed serialized data output for channel B, lane 4, negative connection. This pin can be left
disconnected if not used.
High-speed serialized data output for channel B, lane 5, positive connection. This differential
output must be AC-coupled and must always be terminated with a 100-Ωdifferential termination
at the receiver. This pin can be left disconnected if not used.
High-speed serialized data output for channel B, lane 5, negative connection. This pin can be left
disconnected if not used.
High-speed serialized data output for channel B, lane 6, positive connection. This differential
output must be AC-coupled and must always be terminated with a 100-Ωdifferential termination
at the receiver. This pin can be left disconnected if not used.
High-speed serialized data output for channel B, lane 6, negative connection. This pin can be left
disconnected if not used.
High-speed serialized data output for channel B, lane 7, positive connection. This differential
output must be AC-coupled and must always be terminated with a 100-Ωdifferential termination
at the receiver. This pin can be left disconnected if not used.
High-speed serialized data output for channel B, lane 7, negative connection. This pin can be left
disconnected if not used.
L9
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表5-1. Pin Functions (continued)
PIN
I/O
DESCRIPTION
NAME
NO.
A12, B12, D9,
D10, F9, F10,
G9, G10, J9,
J10, L12, M12
Digital supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit
board.
DGND
—
Channel A analog input positive connection. INA± is recommended for use in single channel
mode for optimal performance. The differential full-scale input voltage is determined by the
FS_RANGE_A register (see the Full-Scale Voltage (VFS) Adjustment section). This input is
terminated to ground through a 50-Ωtermination resistor. The input common-mode voltage is
typically be set to 0 V (GND) and must follow the recommendations in the Recommended
Operating Conditions table. This pin can be left disconnected if not used.
INA+
INA–
INB+
INB–
A4
A5
M4
M5
I
I
I
I
Channel A analog input negative connection. INA± is recommended for use in single channel
mode for optimal performance. See INA+ (pin A4) for detailed description. This input is terminated
to ground through a 50-Ωtermination resistor. This pin can be left disconnected if not used.
Channel B analog input positive connection. INA± is recommended for use in single channel
mode for optimal performance. The differential full-scale input voltage is determined by the
FS_RANGE_B register (see the Full-Scale Voltage (VFS) Adjustment section). This input is
terminated to ground through a 50-Ωtermination resistor. The input common-mode voltage must
typically be set to 0 V (GND) and must follow the recommendations in the Recommended
Operating Conditions table. This pin can be left disconnected if not used.
Channel B analog input negative connection. INA± is recommended for use in single channel
mode for optimal performance. See INB+ for detailed description. This input is terminated to
ground through a 50-Ωtermination resistor. This pin can be left disconnected if not used.
NCOA0
NCOA1
NCOB0
NCOB1
C7
D7
K7
J7
I
I
I
I
Not used. Tie this pin to GND.
Not used. Tie this pin to GND.
Not used. Tie this pin to GND.
Not used. Tie this pin to GND.
Fast overrange detection status for channel A for the OVR_T0 threshold. When the analog input
exceeds the threshold programmed into OVR_T0, this status indicator goes high. The minimum
pulse duration is set by OVR_N. See the ADC Overrange Detection section for more information.
This pin can be left disconnected if not used.
ORA0
ORA1
ORB0
ORB1
C8
D8
K8
J8
O
O
O
O
Fast overrange detection status for channel A for the OVR_T1 threshold. When the analog input
exceeds the threshold programmed into OVR_T1, this status indicator goes high. The minimum
pulse duration is set by OVR_N. See the ADC Overrange Detection section for more information.
This pin can be left disconnected if not used.
Fast overrange detection status for channel B for the OVR_T0 threshold. When the analog input
exceeds the threshold programmed into OVR_T0, this status indicator goes high. The minimum
pulse duration is set by OVR_N. See the ADC Overrange Detection section for more information.
This pin can be left disconnected if not used.
Fast overrange detection status for channel B for the OVR_T1 threshold. When the analog input
exceeds the threshold programmed into OVR_T1, this status indicator goes high. The minimum
pulse duration is set by OVR_N. See the ADC Overrange Detection section for more information.
This pin can be left disconnected if not used.
This pin disables all analog circuits and serializer outputs when set high for temperature diode
calibration or to reduce power consumption when the device is not being used. Tie this pin to GND
if not used.
PD
K6
F8
I
I
Serial interface clock. This pin functions as the serial-interface clock input that clocks the serial
programming data in and out. The Using the Serial Interface section describes the serial interface
in more detail. Supports 1.1-V and 1.8-V CMOS levels.
SCLK
Serial interface chip select active low input. The Using the Serial Interface section describes the
serial interface in more detail. Supports 1.1-V and 1.8-V CMOS levels. This pin has a 82-kΩ
pullup resistor to VD11.
SCS
SDI
E8
G8
H8
I
I
Serial interface data input. The Using the Serial Interface section describes the serial interface in
more detail. Supports 1.1-V and 1.8-V CMOS levels.
Serial interface data output. The Using the Serial Interface section describes the serial interface in
more detail. This pin is high impedance during normal device operation. This pin outputs 1.9-V
CMOS levels during serial interface read operations. This pin can be left disconnected if not used.
SDO
O
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表5-1. Pin Functions (continued)
PIN
I/O
DESCRIPTION
NAME
NO.
Single-ended JESD204C SYNC signal. This input is an active low input that is used to initialize
the JESD204C serial link in 8B/10B modes when SYNC_SEL is set to 0. The 64B/66B modes do
not use the SYNC signal for initialization, however it may be used for NCO synchronization. When
toggled low in 8B/10B modes this input initiates code group synchronization (see the Code Group
Synchronization (CGS) section). After code group synchronization, this input must be toggled high
to start the initial lane alignment sequence (see the Initial Lane Alignment Sequence (ILAS)
section). A differential SYNC signal can be used instead by setting SYNC_SEL to 1 and using
TMSTP± as a differential SYNC input. Tie this pin to GND if differential SYNC (TMSTP±) is used
as the JESD204C SYNC signal.
SYNCSE
C2
I
The SYSREF positive input is used to achieve synchronization and deterministic latency across
the JESD204C interface. This differential input (SYSREF+ to SYSREF–) has an internal
untrimmed 100-Ωdifferential termination and can be AC-coupled when SYSREF_LVPECL_EN is
set to 0. This input is self-biased when SYSREF_LVPECL_EN is set to 0. The termination
changes to 50 Ωto ground on each input pin (SYSREF+ and SYSREF–) and can be DC-
coupled when SYSREF_LVPECL_EN is set to 1. This input is not self-biased when
SYSREF_LVPECL_EN is set to 1 and must be biased externally to the input common-mode
voltage range provided in the Recommended Operating Conditions table.
SYSREF+
K1
I
L1
K2
K3
I
I
I
SYSREF negative input
SYSREF–
TDIODE+
TDIODE–
Temperature diode positive (anode) connection. An external temperature sensor can be
connected to TDIODE+ and TDIODE–to monitor the junction temperature of the device. This pin
can be left disconnected if not used.
Temperature diode negative (cathode) connection. This pin can be left disconnected if not used.
Timestamp input positive connection or differential JESD204C SYNC positive connection. This
input is a timestamp input, used to mark a specific sample, when TIMESTAMP_EN is set to 1.
This differential input is used as the JESD204C SYNC signal input when SYNC_SEL is set 1. This
input can be used as both a timestamp and differential SYNC input at the same time, allowing
feedback of the SYNC signal using the timestamp mechanism. TMSTP± uses active low signaling
when used as a JESD204C SYNC. For additional usage information, see the Timestamp section.
TMSTP_RECV_EN must be set to 1 to use this input. This differential input (TMSTP+ to
TMSTP–) has an internal untrimmed 100-Ωdifferential termination and can be AC-coupled when
TMSTP_LVPECL_EN is set to 0. The termination changes to 50 Ωto ground on each input pin
(TMSTP+ and TMSTP–) and can be DC coupled when TMSTP_LVPECL_EN is set to 1. This pin
is not self-biased and therefore must be externally biased for both AC- and DC-coupled
configurations. The common-mode voltage must be within the range provided in the
Recommended Operating Conditions table when both AC and DC coupled. This pin can be left
disconnected and disabled (TMSTP_RECV_EN = 0) if SYNCSE is used for JESD204C SYNC and
timestamp is not required.
TMSTP+
B1
I
Timestamp input positive connection or differential JESD204C SYNC negative connection. This
pin can be left disconnected and disabled (TMSTP_RECV_EN = 0) if SYNCSE is used for
JESD204C SYNC and timestamp is not required.
C1
I
I
TMSTP–
C5, D2, D3,
D5, E5, F5,
G5, H5, J2, J3,
J5, K5
VA11
1.1-V analog supply
1.9-V analog supply
1.1-V digital supply
C4, D4, E2,
E3, E4, F4,
G4, H2, H3,
H4, J4, K4
VA19
VD11
I
I
C9, C10, E9,
E10, G7, H7,
H9, H10, K9,
K10
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.3
–0.3
–1.32
–0.1
MAX
2.35
1.32
1.32
1.32
0.1
UNIT
V
VA19(2)
VA11(2)
VDD
Supply voltage range
VD11(3)
Voltage between VD11 and VA11
VGND
Voltage between AGND and DGND
V
DA[7:0]+, DA[7:0]–, DB[7:0]+, DB[7:0]–,
TMSTP+, TMSTP–(3)
VD11 +
0.5(5)
–0.5
–0.5
–0.5
–1
VA11 + 0.5(4)
CLK+, CLK–, SYSREF+, SYSREF–(2)
VA19 +
0.5(6)
BG, TDIODE+, TDIODE–(2)
VPIN
Pin voltage range
V
INA+, INA–, INB+, INB–(2)
1
CALSTAT, CALTRIG, NCOA0, NCOA1,
NCOB0, NCOB1, ORA0, ORA1, ORB0, ORB1,
PD, SCLK, SCS, SDI, SDO, SYNCSE (2)
VA19 +
0.5(6)
–0.5
IMAX(ANY)
IMAX(INx)
25
50
mA
mA
Peak input current (any input except INA+, INA–, INB+, INB–)
Peak input current (INA+, INA–, INB+, INB–)
–25
–50
differential with ZS-DIFF = 100 Ω, up to 21
26.5
16.4
100
dBm
dBm
mA
days(7)
PMAX(INx)
Peak RF input power (INA+, INA–, INB+, INB–)
Single-ended with ZS-SE = 50 Ω
Peak total input current (sum of absolute value of all currents forced in or out, not including power-
supply current)
IMAX(ALL)
Tj
Junction temperature
Storage temperature
150
150
°C
°C
Tstg
–65
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated
under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) Measured to AGND.
(3) Measured to DGND.
(4) Maximum voltage not to exceed VA11 absolute maximum rating.
(5) Maximum voltage not to exceed VD11 absolute maximum rating.
(6) Maximum voltage not to exceed VA19 absolute maximum rating.
(7) Tested continuously for 21 days with FIN = 1.2 GHz on a typical device. At the end of testing, the device was not damaged. During the
overdrive, the ADC is still properly converting the input signal, although it will be saturated for voltages beyond the input fullscale.
6.2 ESD Ratings
VALUE
±2000
±500
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
1.8
1.05
1.05
–50
0
NOM
1.9
1.1
1.1
0
MAX
2.0
UNIT
VA19, analog 1.9-V supply(2)
VDD
Supply voltage range
VA11, analog 1.1-V supply(2)
VD11, digital 1.1-V supply(3)
INA+, INA–, INB+, INB–(2)
CLK+, CLK–, SYSREF+, SYSREF–(2) (4)
TMSTP+, TMSTP–(3) (5)
1.15
1.15
100
V
mV
V
VCMI
Input common-mode voltage
0.3
0.3
0.55
0.55
0
CLK+ to CLK–, SYSREF+ to SYSREF–,
TMSTP+ to TMSTP–
0.4
1.0
2.0
VID
Input voltage, peak-to-peak differential
VPP-DIFF
0.8(6)
INA+ to INA–, INB+ to INB–
TDIODE+ to TDIODE–
IC_TD
CL
Temperature diode input current
BG maximum load capacitance
BG maximum output current
Input clock duty cycle
100
µA
pF
µA
%
50
100
70
IO
DC
TA
30
50
Operating free-air temperature
Operating junction temperature
85
°C
°C
–40
TJ
125(1)
(1) Prolonged use above junction temperature of 105°C may increase the device failure-in-time (FIT) rate.
(2) Measured to AGND.
(3) Measured to DGND.
(4) TI strongly recommends that CLK± be AC-coupled with DEVCLK_LVPECL_EN set to 0 to allow CLK± to self-bias to the optimal input
common-mode voltage for best performance. TI recommends AC-coupling for SYSREF± unless DC-coupling is required, in which
case, the LVPECL input mode must be used (SYSREF_LVPECL_EN = 1).
(5) TMSTP± does not have internal biasing that requires TMSTP± to be biased externally whether AC-coupled with TMSTP_LVPECL_EN
= 0 or DC-coupled with TMSTP_LVPECL_EN= 1.
(6) The ADC output code saturates when VID for INA± or INB± exceeds the programmed full-scale voltage(VFS) set by FS_RANGE_A for
INA± or FS_RANGE_B for INB±.
6.4 Thermal Information
ADC08DJ5200RF
THERMAL METRIC(1)
AAV or ZEG (FCBGA)
UNIT
144 PINS
23.9
0.8
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
8.4
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.23
8.4
ψJT
ψJB
RθJC(bot)
n/a
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics: DC Specifications
typical values at TA = 25°C, VA19 = 1.9 V, VA11 = 1.1 V, VD11 = 1.1 V, default full-scale voltage, fIN = 347 MHz, AIN = –1
dBFS, fCLK = 5.2 GHz, filtered 1-VPP sine-wave clock, JMODE = 6, Dither enabled with default settings, VA11, VD11 and
VS11 noise suppression ON (EN_VA11_NOISE_SUPPR = EN_VD11_NOISE_SUPPR = EN_VS11_NOISE_SUPPR = 1),
and background calibration (unless otherwise noted); minimum and maximum values are at nominal supply voltages and
over the operating free-air temperature range provided in the Recommended Operating Conditions table
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DC ACCURACY
Resolution
Resolution with no missing codes
8
0.08
Bits
Maximum positive excursion from ideal step size
Maximum negative excursion from ideal step size
DNL
Differential nonlinearity
LSB
–0.08
Maximum positive excursion from ideal transfer
function
0.1
LSB
LSB
INL
Integral nonlinearity
Maximum negative excursion from ideal transfer
function
–0.15
ANALOG INPUTS (INA+, INA–, INB+, INB–)
CAL_OS = 0
CAL_OS = 1
±0.50
±0.15
mV
mV
VOFF
Offset error
Input offset voltage adjustment
range
Available offset correction range (see OS_CAL or
OADJ_x_INx)
VOFF_ADJ
±50
mV
Foreground calibration at nominal temperature only
Foreground calibration at each temperature
11
-2.7
VOFF_DRIFT
Offset drift
µV/°C
Foreground and FGOS calibration at each
temperature
0
825
Default full-scale voltage (FS_RANGE_A =
FS_RANGE_B = 0xA000)
775
875
550
Analog differential input full-scale
range
Maximum full-scale voltage (FS_RANGE_A =
FS_RANGE_B = 0xFFFF)
VFS
1000
1060
500
mVPPDIFF
Minimum full-scale voltage (FS_RANGE_A =
FS_RANGE_B = 0x2000)
Default FS_RANGE_A and FS_RANGE_B setting,
foreground calibration at each temperature, inputs
driven by a 50-Ωsource, includes effect of RIN drift
Analog differential input full-scale
range drift
VFS_DRIFT
0.055
%/°C
Analog differential input full-scale
range matching
Matching between INA± and INB±, default setting,
dual-channel mode
VFS_MATCH
RIN
0.4%
50
Single-ended input resistance to
AGND
Each input pin is terminated to AGND, measured at
TA = 25°C
48
52
Ω
Input termination linear temperature
coefficient
RIN_TEMPCO
14.7
mΩ/°C
Single-channel mode measured at DC
Dual-channel mode measured at DC
0.4
0.4
CIN
Single-ended input capacitance
pF
TEMPERATURE DIODE CHARACTERISTICS (TDIODE+, TDIODE–)
Forced forward current of 100 µA. Offset voltage
(approximately 0.792 V at 0°C) varies with process
and must be measured for each part. Offset
measurement must be done with the device
unpowered or with the PD pin asserted to minimize
device self-heating.
Temperature diode voltage slope
mV/°C
ΔVBE
–1.65
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6.5 Electrical Characteristics: DC Specifications (continued)
typical values at TA = 25°C, VA19 = 1.9 V, VA11 = 1.1 V, VD11 = 1.1 V, default full-scale voltage, fIN = 347 MHz, AIN = –1
dBFS, fCLK = 5.2 GHz, filtered 1-VPP sine-wave clock, JMODE = 6, Dither enabled with default settings, VA11, VD11 and
VS11 noise suppression ON (EN_VA11_NOISE_SUPPR = EN_VD11_NOISE_SUPPR = EN_VS11_NOISE_SUPPR = 1),
and background calibration (unless otherwise noted); minimum and maximum values are at nominal supply voltages and
over the operating free-air temperature range provided in the Recommended Operating Conditions table
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
BAND-GAP VOLTAGE OUTPUT (BG)
VBG
Reference output voltage
Reference output temperature drift
1.1
V
IL ≤100 µA
IL ≤100 µA
VBG_DRIFT
µV/°C
–123
CLOCK INPUTS (CLK+, CLK–, SYSREF+, SYSREF–, TMSTP+, TMSTP–)
Differential termination with DEVCLK_LVPECL_EN
= 0, SYSREF_LVPECL_EN = 0, and
TMSTP_LVPECL_EN = 0
100
50
ZT
Internal termination
Ω
Single-ended termination to GND (per pin) with
DEVCLK_LVPECL_EN = 0, SYSREF_LVPECL_EN
= 0, and TMSTP_LVPECL_EN = 0
Self-biasing common-mode voltage for CLK± when
AC-coupled (DEVCLK_LVPECL_EN must be set to
0)
0.3
Self-biasing common-mode voltage for SYSREF±
when AC-coupled (SYSREF_LVPECL_EN must be
set to 0) and with receiver enabled
Input common-mode voltage, self-
biased
0.28
0.28
VCM
V
(SYSREF_RECV_EN = 1)
Self-biasing common-mode voltage for SYSREF±
when AC-coupled (SYSREF_LVPECL_EN must be
set to 0) and with receiver disabled
(SYSREF_RECV_EN = 0)
CL_DIFF
CL_SE
Differential input capacitance
Single-ended input capacitance
Between positive and negative differential input pins
Each input to ground
0.04
0.5
pF
pF
SERDES OUTPUTS (DA[7:0]+, DA[7:0]–, DB[7:0]+, DB[7:0]–)
Differential output voltage, peak-to-
peak
VOD
550
600
650 mVPP-DIFF
100-Ωload
VCM
Output common-mode voltage
Differential output impedance
AC coupled
VD11 / 2
100
V
ZDIFF
Ω
CMOS INTERFACE: SCLK, SDI, SDO, SCS, PD, NCOA0, NCOA1, NCOB0, NCOB1, CALSTAT, CALTRIG, ORA0, ORA1, ORB0, ORB1, SYNCSE
VIH
VIL
IIH
High-level input voltage
Low-level input voltage
High-level input current
Low-level input current
Input capacitance
required input voltage
required input voltage
0.7
V
V
0.45
40
µA
µA
pF
V
IIL
–40
CI
3.4
VOH
VOL
High-level output voltage
Low-level output voltage
1.65
ILOAD = –400 µA
ILOAD = 400 µA
150
mV
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6.6 Electrical Characteristics: Power Consumption
typical values at TA = 25°C, VA19 = 1.9 V, VA11 = 1.1 V, VD11 = 1.1 V, default full-scale voltage, fIN = 347 MHz, AIN = –1
dBFS, fCLK = 5.2 GHz, filtered 1-VPP sine-wave clock, JMODE = 6, Dither enabled with default settings, VA11, VD11 and
VS11 noise suppression ON (EN_VA11_NOISE_SUPPR = EN_VD11_NOISE_SUPPR = EN_VS11_NOISE_SUPPR = 1),
and background calibration (unless otherwise noted); minimum and maximum values are at nominal supply voltages and
over the operating free-air temperature range provided in the Recommended Operating Conditions table
PARAMETER
TEST CONDITIONS
MIN
TYP
950
870
1010
3.8
MAX
UNIT
mA
mA
mA
W
IVA19
IVA11
IVD11
PDIS
IVA19
IVA11
IVD11
PDIS
IVA19
IVA11
IVD11
PDIS
IVA19
IVA11
IVD11
PDIS
1.9-V analog supply current
1.1-V analog supply current
1.1-V digital supply current
Power dissipation
Power mode 1: JMODE 6 (single-channel
mode, 16 lanes, 8B/10B encoding),
foreground calibration
1.9-V analog supply current
1.1-V analog supply current
1.1-V digital supply current
Power dissipation
925
870
960
3.7
1050
1000
1150
4.2
mA
mA
mA
W
Power mode 2: JMODE 44 (single-
channel mode, 8 lanes, 64B/66B
encoding), foreground calibration
1.9-V analog supply current
1.1-V analog supply current
1.1-V digital supply current
Power dissipation
1255
1050
1160
4.65
44
mA
mA
mA
W
Power mode 3: JMODE 6 (single-channel
mode, 16 lanes, 8B/10B encoding),
background calibration
1.9-V analog supply current
1.1-V analog supply current
1.1-V digital supply current
Power dissipation
mA
mA
mA
W
27
Power mode 7: PD pin held high, clock
disabled
33
0.15
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6.7 Electrical Characteristics: AC Specifications (Dual-Channel Mode)
typical values at TA = 25°C, VA19 = 1.9 V, VA11 = 1.1 V, VD11 = 1.1 V, default full-scale voltage, fIN = 347 MHz, AIN = –1
dBFS, fCLK = 5.2GHz, filtered 1-VPP sine-wave clock, JMODE = 8, Dither enabled with default settings, VA11, VD11 and VS11
noise suppression ON (EN_VA11_NOISE_SUPPR = EN_VD11_NOISE_SUPPR = EN_VS11_NOISE_SUPPR = 1), and
background calibration (unless otherwise noted); minimum and maximum values are at nominal supply voltages and over the
operating free-air temperature range provided in the Recommended Operating Conditions table
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Foreground calibration
Background calibration
8.1
Full-power input bandwidth
FPBW
XTALK
GHz
(–3 dB)(1)
8.1
Aggressor = 1 GHz, –1 dBFS
Aggressor = 3 GHz, –1 dBFS
Aggressor = 6 GHz, –1 dBFS
–81
–76
–69
Channel-to-channel
crosstalk
dB
Errors/
sample
CER
Code error rate
Maximum CER, does not include JESD204C interface BER
10–18
DC input noise standard
deviation
No input, foreground calibration, excludes DC offset, includes fixed
interleaving spur (fS / 2 spur)
NOISEDC
0.26
LSB
Noise spectral density,
excludes fixed interleaving
spur (fS / 2 spur)
Maximum full-scale voltage (VFS = 1.0 VPP), AIN = –20 dBFS
Default full-scale voltage (VFS = 0.8 VPP), AIN = –20 dBFS
–143.4
dBFS/
Hz
NSD
NF
–143.2
31.6
29.9
48.8
49
Maximum full-scale voltage (VFS = 1.0 VPP), AIN = –20 dBFS
Default full-scale voltage (VFS = 0.8 VPP), AIN = –20 dBFS
AIN = –1 dBFS
dB
Noise figure, ZS = 100 Ω
AIN = –3 dBFS
fIN = 347 MHz
49.0
49.1
48.7
48.9
49.0
48.6
48.8
49.0
49.0
48.1
48.5
49.0
47.7
48.2
48.9
47.1
47.8
48.9
AIN = –12 dBFS
AIN = –3 dBFS, VFS = 1.0 VPP
AIN = –1 dBFS
fIN = 997 MHz
fIN = 2397 MHz
AIN = –3 dBFS
AIN = –12 dBFS
AIN = –1 dBFS
AIN = –3 dBFS
AIN = –12 dBFS
AIN = –3 dBFS, VFS = 1.0 VPP
AIN = –1 dBFS
AIN = –3 dBFS
AIN = –12 dBFS
AIN = –1 dBFS
AIN = –3 dBFS
AIN = –12 dBFS
AIN = –1 dBFS
AIN = –3 dBFS
AIN = –12 dBFS
46.5
Signal-to-noise ratio,
excluding DC, HD2 to
HD9, fS / 2, fS / 2 –fIN
SNR
dBFS
,
fIN = 4197 MHz
fIN = 5997 MHz
fIN = 7597 MHz
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6.7 Electrical Characteristics: AC Specifications (Dual-Channel Mode) (continued)
typical values at TA = 25°C, VA19 = 1.9 V, VA11 = 1.1 V, VD11 = 1.1 V, default full-scale voltage, fIN = 347 MHz, AIN = –1
dBFS, fCLK = 5.2GHz, filtered 1-VPP sine-wave clock, JMODE = 8, Dither enabled with default settings, VA11, VD11 and VS11
noise suppression ON (EN_VA11_NOISE_SUPPR = EN_VD11_NOISE_SUPPR = EN_VS11_NOISE_SUPPR = 1), and
background calibration (unless otherwise noted); minimum and maximum values are at nominal supply voltages and over the
operating free-air temperature range provided in the Recommended Operating Conditions table
PARAMETER
TEST CONDITIONS
MIN
TYP
48.5
48.8
48.9
48.9
48.4
48.8
48.9
48.4
48.7
48.9
48.9
47.6
48.2
48.8
45.5
47.4
48.8
45.8
47.4
48.7
7.8
MAX
UNIT
AIN = –1 dBFS
AIN = –3 dBFS
fIN = 347 MHz
fIN = 997 MHz
fIN = 2397 MHz
AIN = –12 dBFS
AIN = –3 dBFS, VFS = 1.0 VPP
AIN = –1 dBFS
AIN = –3 dBFS
AIN = –12 dBFS
AIN = –1 dBFS
45.5
AIN = –3 dBFS
Signal-to-noise and
distortion ratio, excluding DC
and fS / 2 fixed spurs
AIN = –12 dBFS
AIN = –3 dBFS, VFS = 1.0 VPP
AIN = –1 dBFS
SINAD
dBFS
fIN = 4197 MHz
fIN = 5997 MHz
fIN = 7597 MHz
AIN = –3 dBFS
AIN = –12 dBFS
AIN = –1 dBFS
AIN = –3 dBFS
AIN = –12 dBFS
AIN = –1 dBFS
AIN = –3 dBFS
AIN = –12 dBFS
AIN = –1 dBFS
7.8
AIN = –3 dBFS
fIN = 347 MHz
fIN = 997 MHz
fIN = 2397 MHz
7.8
AIN = –12 dBFS
AIN = –3 dBFS, VFS = 1.0 VPP
AIN = –1 dBFS
7.8
7.7
7.8
AIN = –3 dBFS
AIN = -12 dBFS
7.9
7.27
7.8
AIN = –1 dBFS
7.8
AIN = –3 dBFS
Effective number of bits,
excluding DC and fS / 2 fixed
spurs
7.8
AIN = –12 dBFS
AIN = –3 dBFS, VFS = 1.0 VPP
AIN = –1 dBFS
ENOB
bits
7.8
7.6
fIN = 4197 MHz
fIN = 5997 MHz
fIN = 7597 MHz
7.7
AIN = –3 dBFS
7.8
AIN = –12 dBFS
AIN = –1 dBFS
7.3
7.6
AIN = –3 dBFS
7.8
AIN = –12 dBFS
AIN = –1 dBFS
7.3
7.6
AIN = –3 dBFS
7.8
AIN = –12 dBFS
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6.7 Electrical Characteristics: AC Specifications (Dual-Channel Mode) (continued)
typical values at TA = 25°C, VA19 = 1.9 V, VA11 = 1.1 V, VD11 = 1.1 V, default full-scale voltage, fIN = 347 MHz, AIN = –1
dBFS, fCLK = 5.2GHz, filtered 1-VPP sine-wave clock, JMODE = 8, Dither enabled with default settings, VA11, VD11 and VS11
noise suppression ON (EN_VA11_NOISE_SUPPR = EN_VD11_NOISE_SUPPR = EN_VS11_NOISE_SUPPR = 1), and
background calibration (unless otherwise noted); minimum and maximum values are at nominal supply voltages and over the
operating free-air temperature range provided in the Recommended Operating Conditions table
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
65
AIN = –1 dBFS
68
AIN = –3 dBFS
fIN = 347 MHz
fIN = 997 MHz
fIN = 2397 MHz
68
AIN = –12 dBFS
AIN = –3 dBFS, VFS = 1.0 VPP
AIN = –1 dBFS
67
63
69
AIN = –3 dBFS
68
AIN = –12 dBFS
AIN = –1 dBFS
52
67
69
AIN = –3 dBFS
Spurious-free dynamic
range, excluding DC and fS
2 fixed spurs
69
AIN = –12 dBFS
AIN = –3 dBFS, VFS = 1.0 VPP
AIN = –1 dBFS
SFDR
/
dBFS
69
59
fIN = 4197 MHz
fIN = 5997 MHz
fIN = 7597 MHz
63
AIN = –3 dBFS
68
AIN = –12 dBFS
AIN = –1 dBFS
52
58
AIN = –3 dBFS
68
AIN = –12 dBFS
AIN = –1 dBFS
53
61
AIN = –3 dBFS
69
AIN = –12 dBFS
AIN = –1 dBFS
AIN = –3 dBFS
–74
–76
–78
–75
–74
–76
–75
–74
–74
–78
–75
–61
–65
–77
–55
–60
–73
–64
–69
–75
fIN = 347 MHz
fIN = 997 MHz
fIN = 2397 MHz
AIN = –12 dBFS
AIN = –3 dBFS, VFS = 1.0 VPP
AIN = –1 dBFS
AIN = –3 dBFS
AIN = –12 dBFS
AIN = –1 dBFS
-55
AIN = –3 dBFS
AIN = –12 dBFS
AIN = –3 dBFS, VFS = 1.0 VPP
AIN = –1 dBFS
2nd-order harmonic
distortion
HD2
dBFS
fIN = 4197 MHz
fIN = 5997 MHz
fIN = 7597 MHz
AIN = –3 dBFS
AIN = –12 dBFS
AIN = –1 dBFS
AIN = –3 dBFS
AIN = –12 dBFS
AIN = –1 dBFS
AIN = –3 dBFS
AIN = –12 dBFS
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6.7 Electrical Characteristics: AC Specifications (Dual-Channel Mode) (continued)
typical values at TA = 25°C, VA19 = 1.9 V, VA11 = 1.1 V, VD11 = 1.1 V, default full-scale voltage, fIN = 347 MHz, AIN = –1
dBFS, fCLK = 5.2GHz, filtered 1-VPP sine-wave clock, JMODE = 8, Dither enabled with default settings, VA11, VD11 and VS11
noise suppression ON (EN_VA11_NOISE_SUPPR = EN_VD11_NOISE_SUPPR = EN_VS11_NOISE_SUPPR = 1), and
background calibration (unless otherwise noted); minimum and maximum values are at nominal supply voltages and over the
operating free-air temperature range provided in the Recommended Operating Conditions table
PARAMETER
TEST CONDITIONS
AIN = –1 dBFS
AIN = –3 dBFS
MIN
TYP
–66
–72
–73
–70
–63
–79
–75
–71
–72
–80
–73
–65
–65
–75
–53
–61
–71
–53
–62
–87
–73
–73
–78
–73
–69
–71
–79
–70
–74
–75
–74
–67
–68
–74
–67
–69
–74
–62
–64
–72
MAX
UNIT
fIN = 347 MHz
fIN = 997 MHz
fIN = 2397 MHz
AIN = –12 dBFS
AIN = –3 dBFS, VFS = 1.0 VPP
AIN = –1 dBFS
AIN = –3 dBFS
AIN = –12 dBFS
AIN = –1 dBFS
-55
AIN = –3 dBFS
AIN = –12 dBFS
AIN = –3 dBFS, VFS = 1.0 VPP
AIN = –1 dBFS
HD3
3rd-order harmonic distortion
dBFS
fIN = 4197 MHz
fIN = 5997 MHz
fIN = 7597 MHz
AIN = –3 dBFS
AIN = –12 dBFS
AIN = –1 dBFS
AIN = –3 dBFS
AIN = –12 dBFS
AIN = –1 dBFS
AIN = –3 dBFS
AIN = –12 dBFS
AIN = –1 dBFS
AIN = –3 dBFS
fIN = 347 MHz
fIN = 997 MHz
fIN = 2397 MHz
AIN = –12 dBFS
AIN = –3 dBFS, VFS = 1.0 VPP
AIN = –1 dBFS
AIN = –3 dBFS
AIN = –12 dBFS
AIN = –1 dBFS
-52
AIN = –3 dBFS
AIN = –12 dBFS
AIN = –3 dBFS, VFS = 1.0 VPP
AIN = –1 dBFS
fS / 2 –fIN input signal
dependent interleaving spur
dBFS
fS / 2 –fIN
fIN = 4197 MHz
fIN = 5997 MHz
AIN = –3 dBFS
AIN = –12 dBFS
AIN = –1 dBFS
AIN = –3 dBFS
AIN = –12 dBFS
AIN = –1 dBFS
fIN = 7597 MHz
AIN = –3 dBFS
AIN = –12 dBFS
fS / 2 fixed interleaving spur,
independent of input signal
fS / 2
-52
dBFS
AIN = –20 dBFS
–76
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6.7 Electrical Characteristics: AC Specifications (Dual-Channel Mode) (continued)
typical values at TA = 25°C, VA19 = 1.9 V, VA11 = 1.1 V, VD11 = 1.1 V, default full-scale voltage, fIN = 347 MHz, AIN = –1
dBFS, fCLK = 5.2GHz, filtered 1-VPP sine-wave clock, JMODE = 8, Dither enabled with default settings, VA11, VD11 and VS11
noise suppression ON (EN_VA11_NOISE_SUPPR = EN_VD11_NOISE_SUPPR = EN_VS11_NOISE_SUPPR = 1), and
background calibration (unless otherwise noted); minimum and maximum values are at nominal supply voltages and over the
operating free-air temperature range provided in the Recommended Operating Conditions table
PARAMETER
TEST CONDITIONS
AIN = –1 dBFS
AIN = –3 dBFS
MIN
TYP
–70
–70
–70
–70
–68
–71
–68
–72
–72
–70
–71
–69
–71
–69
–65
–70
–70
–69
–71
–70
MAX
UNIT
fIN = 347 MHz
fIN = 997 MHz
fIN = 2397 MHz
AIN = –12 dBFS
AIN = –3 dBFS, VFS = 1.0 VPP
AIN = –1 dBFS
AIN = –3 dBFS
AIN = –12 dBFS
AIN = –1 dBFS
-60
AIN = –3 dBFS
Worst spur, excluding DC,
HD2, HD3, fS / 2 and fS / 2 -
fIN spurs
AIN = –12 dBFS
AIN = –3 dBFS, VFS = 1.0 VPP
AIN = –1 dBFS
SPUR
dBFS
fIN = 4197 MHz
fIN = 5997 MHz
fIN = 7597 MHz
AIN = –3 dBFS
AIN = –12 dBFS
AIN = –1 dBFS
AIN = –3 dBFS
AIN = –12 dBFS
AIN = –1 dBFS
AIN = –3 dBFS
AIN = –12 dBFS
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6.7 Electrical Characteristics: AC Specifications (Dual-Channel Mode) (continued)
typical values at TA = 25°C, VA19 = 1.9 V, VA11 = 1.1 V, VD11 = 1.1 V, default full-scale voltage, fIN = 347 MHz, AIN = –1
dBFS, fCLK = 5.2GHz, filtered 1-VPP sine-wave clock, JMODE = 8, Dither enabled with default settings, VA11, VD11 and VS11
noise suppression ON (EN_VA11_NOISE_SUPPR = EN_VD11_NOISE_SUPPR = EN_VS11_NOISE_SUPPR = 1), and
background calibration (unless otherwise noted); minimum and maximum values are at nominal supply voltages and over the
operating free-air temperature range provided in the Recommended Operating Conditions table
PARAMETER
TEST CONDITIONS
MIN
TYP
–80
–77
–77
–79
–80
–82
–73
–69
–70
–83
–69
–67
–74
–73
–59
–66
–72
–46
–53
–79
MAX
UNIT
AIN = –7 dBFS per tone
AIN = –9 dBFS per tone
AIN = –18 dBFS per tone
AIN = –9 dBFS per tone, VFS = 1.0 VPP
AIN = –7 dBFS per tone
AIN = –9 dBFS per tone
AIN = –18 dBFS per tone
AIN = –7 dBFS per tone
AIN = –9 dBFS per tone
AIN = –18 dBFS per tone
AIN = –9 dBFS per tone, VFS = 1.0 VPP
AIN = –7 dBFS per tone
AIN = –9 dBFS per tone
AIN = –18 dBFS per tone
AIN = –7 dBFS per tone
AIN = –9 dBFS per tone
AIN = –18 dBFS per tone
AIN = –7 dBFS per tone
AIN = –9 dBFS per tone
AIN = –18 dBFS per tone
f1 = 343 MHz,
f2 = 353 MHz
f1 = 993 MHz,
f2 = 1003 MHz
f1 = 2393 MHz,
f2 = 2403 MHz
3rd-order intermodulation
distortion
IMD3
dBFS
f1 = 4193 MHz,
f2 = 4203 MHz
f1 = 5993 MHz,
f2 = 6003 MHz
f1 = 7593 MHz,
f2 = 7603 MHz
(1) Full-power input bandwidth (FPBW) is defined as the input frequency where the reconstructed output of the ADC has dropped 3 dB
below the power of a full-scale input signal at a low input frequency. Useable bandwidth may exceed the –3-dB, full-power input
bandwidth.
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6.8 Electrical Characteristics: AC Specifications (Single-Channel Mode)
typical values at TA = 25°C, VA19 = 1.9 V, VA11 = 1.1 V, VD11 = 1.1 V, default full-scale voltage, input signal applied to INA±,
fIN = 347 MHz, AIN = –1 dBFS, fCLK = 5.2 GHz, filtered 1-VPP sine-wave clock, JMODE = 6, Dither enabled with default
settings, VA11, VD11 and VS11 noise suppression ON (EN_VA11_NOISE_SUPPR = EN_VD11_NOISE_SUPPR =
EN_VS11_NOISE_SUPPR = 1), and background calibration (unless otherwise noted); minimum and maximum values are at
nominal supply voltages and over the operating free-air temperature range provided in the Recommended Operating
Conditions table
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Foreground calibration
Background calibration
7.9
Full-power input bandwidth
(–3 dB)(1)
FPBW
GHz
7.9
Errors/
sample
CER
Code error rate
Maximum CER, does not include JESD204C interface BER
10–18
DC input noise standard
deviation
No input, foreground calibration, excludes DC offset, includes fixed
interleaving spurs (fS / 2 and fS / 4 spurs), OS_CAL enabled
NOISEDC
0.15
LSB
Noise spectral density,
excludes fixed interleaving
spurs (fS / 2 and fS / 4 spur)
Maximum full-scale voltage (VFS = 1.0 VPP), AIN = –20 dBFS
Default full-scale voltage (VFS = 0.8 VPP), AIN = –20 dBFS
–146.2
dBFS/
Hz
NSD
NF
–146.0
28.7
27.1
48.7
48.9
49.0
49.0
48.7
48.8
49.0
48.6
48.7
49.0
48.9
48.2
48.5
48.9
47.7
48.1
49.0
47.1
47.7
48.9
Maximum full-scale voltage (VFS = 1.0 VPP), AIN = –20 dBFS
Default full-scale voltage (VFS = 0.8 VPP), AIN = –20 dBFS
AIN = –1 dBFS
dB
Noise figure, ZS = 100 Ω
AIN = –3 dBFS
fIN = 347 MHz
AIN = –12 dBFS
AIN = –3 dBFS, VFS = 1.0 VPP
AIN = –1 dBFS
fIN = 997 MHz
fIN = 2397 MHz
AIN = –3 dBFS
AIN = –12 dBFS
AIN = –1 dBFS
AIN = –3 dBFS
AIN = –12 dBFS
AIN = –3 dBFS, VFS = 1.0 VPP
AIN = –1 dBFS
AIN = –3 dBFS
AIN = –12 dBFS
AIN = –1 dBFS
AIN = –3 dBFS
AIN = –12 dBFS
AIN = –1 dBFS
AIN = –3 dBFS
AIN = –12 dBFS
46.8
Signal-to-noise ratio,
excluding DC, HD2 to
HD9, fS / 2, fS / 4, fS / 2 –
fIN, fS / 4 ± fIN
SNR
dBFS
fIN = 4197 MHz
fIN = 5997 MHz
fIN = 7597 MHz
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6.8 Electrical Characteristics: AC Specifications (Single-Channel Mode) (continued)
typical values at TA = 25°C, VA19 = 1.9 V, VA11 = 1.1 V, VD11 = 1.1 V, default full-scale voltage, input signal applied to INA±,
fIN = 347 MHz, AIN = –1 dBFS, fCLK = 5.2 GHz, filtered 1-VPP sine-wave clock, JMODE = 6, Dither enabled with default
settings, VA11, VD11 and VS11 noise suppression ON (EN_VA11_NOISE_SUPPR = EN_VD11_NOISE_SUPPR =
EN_VS11_NOISE_SUPPR = 1), and background calibration (unless otherwise noted); minimum and maximum values are at
nominal supply voltages and over the operating free-air temperature range provided in the Recommended Operating
Conditions table
PARAMETER
TEST CONDITIONS
MIN
TYP
48.2
48.5
48.8
48.7
47.9
48.4
48.8
47.3
47.8
48.7
48.0
46.5
47.3
48.6
45.5
46.9
48.7
44.9
46.3
48.6
7.7
MAX
UNIT
AIN = –1 dBFS
AIN = –3 dBFS
fIN = 347 MHz
fIN = 997 MHz
fIN = 2397 MHz
AIN = –12 dBFS
AIN = –3 dBFS, VFS = 1.0 VPP
AIN = –1 dBFS
AIN = –3 dBFS
AIN = –12 dBFS
AIN = –1 dBFS
44.5
AIN = –3 dBFS
Signal-to-noise and
distortion ratio, excluding DC
and fS / 2 fixed spurs
AIN = –12 dBFS
AIN = –3 dBFS, VFS = 1.0 VPP
AIN = –1 dBFS
SINAD
dBFS
fIN = 4197 MHz
fIN = 5997 MHz
fIN = 7597 MHz
AIN = –3 dBFS
AIN = –12 dBFS
AIN = –1 dBFS
AIN = –3 dBFS
AIN = –12 dBFS
AIN = –1 dBFS
AIN = –3 dBFS
AIN = –12 dBFS
AIN = –1 dBFS
7.7
AIN = –3 dBFS
fIN = 347 MHz
fIN = 997 MHz
fIN = 2397 MHz
7.8
AIN = –12 dBFS
AIN = –3 dBFS, VFS = 1.0 VPP
AIN = –1 dBFS
7.8
7.7
7.7
AIN = –3 dBFS
7.8
AIN = –12 dBFS
AIN = –1 dBFS
7.1
7.6
7.7
AIN = –3 dBFS
Effective number of bits,
excluding DC and fS / 2 fixed
spurs
7.8
AIN = –12 dBFS
AIN = –3 dBFS, VFS = 1.0 VPP
AIN = –1 dBFS
ENOB
bits
7.7
7.4
fIN = 4197 MHz
fIN = 5997 MHz
fIN = 7597 MHz
7.6
AIN = –3 dBFS
7.8
AIN = –12 dBFS
AIN = –1 dBFS
7.3
7.5
AIN = –3 dBFS
7.8
AIN = –12 dBFS
AIN = –1 dBFS
7.2
7.4
AIN = –3 dBFS
7.8
AIN = –12 dBFS
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6.8 Electrical Characteristics: AC Specifications (Single-Channel Mode) (continued)
typical values at TA = 25°C, VA19 = 1.9 V, VA11 = 1.1 V, VD11 = 1.1 V, default full-scale voltage, input signal applied to INA±,
fIN = 347 MHz, AIN = –1 dBFS, fCLK = 5.2 GHz, filtered 1-VPP sine-wave clock, JMODE = 6, Dither enabled with default
settings, VA11, VD11 and VS11 noise suppression ON (EN_VA11_NOISE_SUPPR = EN_VD11_NOISE_SUPPR =
EN_VS11_NOISE_SUPPR = 1), and background calibration (unless otherwise noted); minimum and maximum values are at
nominal supply voltages and over the operating free-air temperature range provided in the Recommended Operating
Conditions table
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
63
AIN = –1 dBFS
66
AIN = –3 dBFS
fIN = 347 MHz
fIN = 997 MHz
fIN = 2397 MHz
70
AIN = –12 dBFS
AIN = –3 dBFS, VFS = 1.0 VPP
AIN = –1 dBFS
65
60
63
AIN = –3 dBFS
69
AIN = –12 dBFS
AIN = –1 dBFS
46
56
59
AIN = –3 dBFS
Spurious free dynamic
range, excluding DC, fS / 4
and fS / 2 fixed spurs
67
AIN = –12 dBFS
AIN = –3 dBFS, VFS = 1.0 VPP
AIN = –1 dBFS
SFDR
dBFS
58
55
fIN = 4197 MHz
fIN = 5997 MHz
fIN = 7597 MHz
57
AIN = –3 dBFS
65
AIN = –12 dBFS
AIN = –1 dBFS
53
56
AIN = –3 dBFS
65
AIN = –12 dBFS
AIN = –1 dBFS
51
54
AIN = –3 dBFS
63
AIN = –12 dBFS
AIN = –1 dBFS
–74
–75
–82
–77
–77
–77
–82
–71
–76
–85
–75
–63
–64
–80
–62
–65
–80
–68
–72
–83
AIN = –3 dBFS
fIN = 347 MHz
fIN = 997 MHz
fIN = 2397 MHz
AIN = –12 dBFS
AIN = –3 dBFS, VFS = 1.0 VPP
AIN = –1 dBFS
AIN = –3 dBFS
AIN = –12 dBFS
AIN = –1 dBFS
-55
AIN = –3 dBFS
AIN = –12 dBFS
AIN = –3 dBFS, VFS = 1.0 VPP
AIN = –1 dBFS
2nd-order harmonic
distortion
HD2
dBFS
fIN = 4197 MHz
fIN = 5997 MHz
fIN = 7597 MHz
AIN = –3 dBFS
AIN = –12 dBFS
AIN = –1 dBFS
AIN = –3 dBFS
AIN = –12 dBFS
AIN = –1 dBFS
AIN = –3 dBFS
AIN = –12 dBFS
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6.8 Electrical Characteristics: AC Specifications (Single-Channel Mode) (continued)
typical values at TA = 25°C, VA19 = 1.9 V, VA11 = 1.1 V, VD11 = 1.1 V, default full-scale voltage, input signal applied to INA±,
fIN = 347 MHz, AIN = –1 dBFS, fCLK = 5.2 GHz, filtered 1-VPP sine-wave clock, JMODE = 6, Dither enabled with default
settings, VA11, VD11 and VS11 noise suppression ON (EN_VA11_NOISE_SUPPR = EN_VD11_NOISE_SUPPR =
EN_VS11_NOISE_SUPPR = 1), and background calibration (unless otherwise noted); minimum and maximum values are at
nominal supply voltages and over the operating free-air temperature range provided in the Recommended Operating
Conditions table
PARAMETER
TEST CONDITIONS
MIN
TYP
–65
–71
–76
–68
–63
–78
–76
–70
–73
–83
–74
–70
–66
–75
–55
–62
–71
–53
–64
–86
–68
–68
–73
–67
–62
–63
–75
–56
–60
–68
–59
–56
–58
–67
–54
–56
–68
–52
–55
–64
MAX
UNIT
AIN = –1 dBFS
AIN = –3 dBFS
fIN = 347 MHz
fIN = 997 MHz
fIN = 2397 MHz
AIN = –12 dBFS
AIN = –3 dBFS, VFS = 1.0 VPP
AIN = –1 dBFS
AIN = –3 dBFS
AIN = –12 dBFS
AIN = –1 dBFS
-55
AIN = –3 dBFS
AIN = –12 dBFS
AIN = –3 dBFS, VFS = 1.0 VPP
AIN = –1 dBFS
HD3
3rd-order harmonic distortion
dBFS
fIN = 4197 MHz
fIN = 5997 MHz
fIN = 7597 MHz
AIN = –3 dBFS
AIN = –12 dBFS
AIN = –1 dBFS
AIN = –3 dBFS
AIN = –12 dBFS
AIN = –1 dBFS
AIN = –3 dBFS
AIN = –12 dBFS
AIN = –1 dBFS
AIN = –3 dBFS
fIN = 347 MHz
fIN = 997 MHz
fIN = 2397 MHz
AIN = –12 dBFS
AIN = –3 dBFS, VFS = 1.0 VPP
AIN = –1 dBFS
AIN = –3 dBFS
AIN = –12 dBFS
AIN = –1 dBFS
-46
AIN = –3 dBFS
AIN = –12 dBFS
AIN = –3 dBFS, VFS = 1.0 VPP
AIN = –1 dBFS
fS / 2 –fIN input signal
dependent interleaving spur
dBFS
fS / 2 –fIN
fIN = 4197 MHz
fIN = 5997 MHz
fIN = 7597 MHz
AIN = –3 dBFS
AIN = –12 dBFS
AIN = –1 dBFS
AIN = –3 dBFS
AIN = –12 dBFS
AIN = –1 dBFS
AIN = –3 dBFS
AIN = –12 dBFS
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6.8 Electrical Characteristics: AC Specifications (Single-Channel Mode) (continued)
typical values at TA = 25°C, VA19 = 1.9 V, VA11 = 1.1 V, VD11 = 1.1 V, default full-scale voltage, input signal applied to INA±,
fIN = 347 MHz, AIN = –1 dBFS, fCLK = 5.2 GHz, filtered 1-VPP sine-wave clock, JMODE = 6, Dither enabled with default
settings, VA11, VD11 and VS11 noise suppression ON (EN_VA11_NOISE_SUPPR = EN_VD11_NOISE_SUPPR =
EN_VS11_NOISE_SUPPR = 1), and background calibration (unless otherwise noted); minimum and maximum values are at
nominal supply voltages and over the operating free-air temperature range provided in the Recommended Operating
Conditions table
PARAMETER
TEST CONDITIONS
MIN
TYP
–74
–74
–80
–74
–71
–70
–77
–69
–74
–79
–75
–69
–69
–77
–70
–69
–78
–67
–68
–77
–64
–73
MAX
UNIT
AIN = –1 dBFS
AIN = –3 dBFS
fIN = 347 MHz
fIN = 997 MHz
fIN = 2397 MHz
AIN = –12 dBFS
AIN = –3 dBFS, VFS = 1.0 VPP
AIN = –1 dBFS
AIN = –3 dBFS
AIN = –12 dBFS
AIN = –1 dBFS
-50
AIN = –3 dBFS
AIN = –12 dBFS
AIN = –3 dBFS, VFS = 1.0 VPP
AIN = –1 dBFS
fS / 4 ± fIN input signal
dependent interleaving spur
fS / 4 ± fIN
dBFS
fIN = 4197 MHz
fIN = 5997 MHz
fIN = 7597 MHz
AIN = –3 dBFS
AIN = –12 dBFS
AIN = –1 dBFS
AIN = –3 dBFS
AIN = –12 dBFS
AIN = –1 dBFS
AIN = –3 dBFS
AIN = –12 dBFS
AIN = –20 dBFS, OS_CAL disabled
AIN = –20 dBFS, OS_CAL enabled
fS / 2 fixed interleaving spur,
independent of input signal
fS / 2
fS / 4
dBFS
dBFS
fS / 4 fixed interleaving spur,
independent of input signal
-50
AIN = –20 dBFS
–66
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6.8 Electrical Characteristics: AC Specifications (Single-Channel Mode) (continued)
typical values at TA = 25°C, VA19 = 1.9 V, VA11 = 1.1 V, VD11 = 1.1 V, default full-scale voltage, input signal applied to INA±,
fIN = 347 MHz, AIN = –1 dBFS, fCLK = 5.2 GHz, filtered 1-VPP sine-wave clock, JMODE = 6, Dither enabled with default
settings, VA11, VD11 and VS11 noise suppression ON (EN_VA11_NOISE_SUPPR = EN_VD11_NOISE_SUPPR =
EN_VS11_NOISE_SUPPR = 1), and background calibration (unless otherwise noted); minimum and maximum values are at
nominal supply voltages and over the operating free-air temperature range provided in the Recommended Operating
Conditions table
PARAMETER
TEST CONDITIONS
MIN
TYP
–70
–71
–71
–70
–68
–72
–68
–73
–73
–71
–72
–68
–71
–68
–65
–70
–71
–67
–71
–72
MAX
UNIT
AIN = –1 dBFS
AIN = –3 dBFS
fIN = 347 MHz
fIN = 997 MHz
fIN = 2397 MHz
AIN = –12 dBFS
AIN = –3 dBFS, VFS = 1.0 VPP
AIN = –1 dBFS
AIN = –3 dBFS
AIN = –12 dBFS
AIN = –1 dBFS
-58
AIN = –3 dBFS
Worst spur, excluding DC,
HD2, HD3, fS / 2, fS / 4, fS / 2
- fIN, and fS / 4 ± fIN
AIN = –12 dBFS
AIN = –3 dBFS, VFS = 1.0 VPP
AIN = –1 dBFS
SPUR
dBFS
fIN = 4197 MHz
fIN = 5997 MHz
fIN = 7597 MHz
AIN = –3 dBFS
AIN = –12 dBFS
AIN = –1 dBFS
AIN = –3 dBFS
AIN = –12 dBFS
AIN = –1 dBFS
AIN = –3 dBFS
AIN = –12 dBFS
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6.8 Electrical Characteristics: AC Specifications (Single-Channel Mode) (continued)
typical values at TA = 25°C, VA19 = 1.9 V, VA11 = 1.1 V, VD11 = 1.1 V, default full-scale voltage, input signal applied to INA±,
fIN = 347 MHz, AIN = –1 dBFS, fCLK = 5.2 GHz, filtered 1-VPP sine-wave clock, JMODE = 6, Dither enabled with default
settings, VA11, VD11 and VS11 noise suppression ON (EN_VA11_NOISE_SUPPR = EN_VD11_NOISE_SUPPR =
EN_VS11_NOISE_SUPPR = 1), and background calibration (unless otherwise noted); minimum and maximum values are at
nominal supply voltages and over the operating free-air temperature range provided in the Recommended Operating
Conditions table
PARAMETER
TEST CONDITIONS
MIN
TYP
–77
–81
–77
–82
–80
–82
–73
–69
–70
–84
–69
–68
–75
–73
-60
MAX
UNIT
AIN = –7 dBFS per tone
AIN = –9 dBFS per tone
AIN = –18 dBFS per tone
AIN = –9 dBFS per tone, VFS = 1.0 VPP
AIN = –7 dBFS per tone
AIN = –9 dBFS per tone
AIN = –18 dBFS per tone
AIN = –7 dBFS per tone
AIN = –9 dBFS per tone
AIN = –18 dBFS per tone
AIN = –9 dBFS per tone, VFS = 1.0 VPP
AIN = –7 dBFS per tone
AIN = –9 dBFS per tone
AIN = –18 dBFS per tone
AIN = –7 dBFS per tone
AIN = –9 dBFS per tone
AIN = –18 dBFS per tone
AIN = –7 dBFS per tone
AIN = –9 dBFS per tone
AIN = –18 dBFS per tone
f1 = 343 MHz,
f2 = 353 MHz
f1 = 993 MHz,
f2 = 1003 MHz
f1 = 2393 MHz,
f2 = 2403 MHz
3rd-order intermodulation
distortion
IMD3
dBFS
f1 = 4193 MHz,
f2 = 4203 MHz
f1 = 5993 MHz,
f2 = 6003 MHz
–67
–72
–49
–55
–81
f1 = 7593 MHz,
f2 = 7603 MHz
(1) Full-power input bandwidth (FPBW) is defined as the input frequency where the reconstructed output of the ADC has dropped 3 dB
below the power of a full-scale input signal at a low input frequency. Useable bandwidth may exceed the –3-dB, full-power input
bandwidth.
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6.9 Timing Requirements
typical values at TA = 25°C, VA19 = 1.9 V, VA11 = 1.1 V, VD11 = 1.1 V, default full-scale voltage, fIN = 347 MHz, AIN = –1
dBFS, fCLK = 5.2 GHz, filtered 1-VPP sine-wave clock, JMODE = 6, Dither enabled with default settings, VA11, VD11 and
VS11 noise suppression ON (EN_VA11_NOISE_SUPPR = EN_VD11_NOISE_SUPPR = EN_VS11_NOISE_SUPPR = 1),
and background calibration (unless otherwise noted); minimum and maximum values are at nominal supply voltages and
over the operating free-air temperature range provided in the Recommended Operating Conditions table
MIN
NOM
MAX
UNIT
DEVICE (SAMPLING) CLOCK (CLK+, CLK–)
fCLK
Input clock frequency (CLK±), both single-channel and dual-channel modes(1)
tCLK
Input clock period (CLK±), both single-channel and dual-channel modes(1)
SYSREF (SYSREF+, SYSREF–)
800
192
5200
1250
MHz
ps
Width of invalid SYSREF capture region of CLK± period, indicating setup or hold time
tINV(SYSREF)
tINV(TEMP)
tINV(VA11)
48
0.02
ps
violation, as measured by SYSREF_POS status register, SYSREF_ZOOM = 1(2)
Drift of invalid SYSREF capture region over temperature, positive number indicates a
shift toward MSB of SYSREF_POS register, SYSREF_ZOOM = 1
ps/°C
ps/mV
Drift of invalid SYSREF capture region over VA11 supply voltage, positive number
indicates a shift toward MSB of SYSREF_POS register, SYSREF_ZOOM = 1
-0.03
SYSREF_ZOOM = 0
Delay of SYSREF_POS LSB(3)
39
24
tSTEP(SP)
ps
SYSREF_ZOOM = 1
Minimum SYSREF± assertion duration with SYSREF Windowing after SYSREF± rising
edge event
5*TCLK
+4.5
t(PH_SYS)
t(PL_SYS)
ns
ns
Minimum SYSREF± de-assertion duration with SYSREF Windowing after SYSREF±
falling edge event
5*TCLK
+4.5
JESD204B SYNC TIMING (SYNCSE OR TMSTP±)
t(SYNCSE)
SYNCSE minimum assertion time to trigger link resynchronization
4
Frames
SERIAL PROGRAMMING INTERFACE (SCLK, SDI, SCS)
fCLK(SCLK)
t(PH)
Serial clock frequency
15.625
MHz
ns
Serial clock high value pulse duration
Serial clock low value pulse duration
Setup time from SCS to rising edge of SCLK
Hold time from rising edge of SCLK to SCS
Setup time from SDI to rising edge of SCLK
Hold time from rising edge of SCLK to SDI
32
32
30
30
25
3
t(PL)
ns
tSU(SCS)
tH(SCS)
tSU(SDI)
tH(SDI)
ns
ns
ns
ns
(1) Unless functionally limited to a smaller range in the Operating Modes table based on programmed JMODE.
(2) Use SYSREF_POS to select an optimal SYSREF_SEL value for the SYSREF capture, see the SYSREF Position Detector and
Sampling Position Selection (SYSREF Windowing) section for more information on SYSREF windowing. The invalid region, specified
by tINV(SYSREF), indicates the portion of the CLK± period(tCLK), as measured by SYSREF_SEL, that may result in a setup and hold
violation. Verify that the timing skew between SYSREF± and CLK± over system operating conditions from the nominal conditions (that
used to find optimal SYSREF_SEL) does not result in the invalid region occurring at the selected SYSREF_SEL position in
SYSREF_POS, otherwise a temperature dependent SYSREF_SEL selection may be needed to track the skew between CLK± and
SYSREF±.
(3) It is recommended to use SYSREF_ZOOM = 0 below fCLK = 3GHz and SYSREF_ZOOM = 1 above fCLK = 3GHz
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6.10 Switching Characteristics
typical values at TA = 25°C, VA19 = 1.9 V, VA11 = 1.1 V, VD11 = 1.1 V, default full-scale voltage, fIN = 347 MHz, AIN = –1
dBFS, fCLK = 5.2 GHz, filtered 1-VPP sine-wave clock, JMODE = 6, Dither enabled with default settings, VA11, VD11 and
VS11 noise suppression ON (EN_VA11_NOISE_SUPPR = EN_VD11_NOISE_SUPPR = EN_VS11_NOISE_SUPPR = 1),
and background calibration (unless otherwise noted); minimum and maximum values are at nominal supply voltages and
over the operating free-air temperature range provided in the Recommended Operating Conditions table
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DEVICE (SAMPLING) CLOCK (CLK+, CLK–)
Sampling (aperture) delay from the CLK±
rising edge (dual-channel mode) or rising
and falling edge (single-channel mode) to
sampling instant
TAD_COARSE = 0x00, TAD_FINE =
0x00, and TAD_INV = 0
tAD
360
289
ps
ps
Coarse adjustment (TAD_COARSE =
0xFF)
Maximum tAD adjust programmable delay,
tTAD(MAX)
not including clock inversion (TAD_INV = 0)
Fine adjustment (TAD_FINE = 0xFF)
Coarse adjustment (TAD_COARSE)
Fine adjustment (TAD_FINE)
4.9
1.13
19
ps
ps
fs
tTAD(STEP)
tAD adjust programmable delay step size
Aperture jitter, rms
Minimum tAD adjust coarse setting
(TAD_COARSE = 0x00, TAD_INV = 0),
dither disabled (ADC_DITH_EN = 0)
tAJ
50
60
fs
fs
Minimum tAD adjust coarse setting
(TAD_COARSE = 0x00, TAD_INV = 0),
dither enabled (ADC_DITH_EN = 1)
tAJ
Aperture jitter, rms
Aperture jitter, rms
Maximum tAD adjust coarse setting
(TAD_COARSE = 0xFF) excluding
TAD_INV (TAD_INV = 0), dither disabled
(ADC_DITH_EN = 0)
tAJ
65(3)
fs
fs
Maximum tAD adjust coarse setting
(TAD_COARSE = 0xFF) excluding
TAD_INV (TAD_INV = 0), dither enabled
(ADC_DITH_EN = 1)
tAJ
Aperture jitter, rms
74(3)
SERIAL DATA OUTPUTS (DA[7:0]+, DA[7:0]–, DB[7:0]+, DB[7:0]–)
fSERDES
UI
Serialized output bit rate
1
17.16
1000
Gbps
ps
Serialized output unit interval
58.2
20% to 80%, 8H8L test pattern, 13.0
Gbps
tTLH
Low-to-high transition time (differential)
High-to-low transition time (differential)
Data dependent jitter, peak-to-peak
Data dependent jitter, peak-to-peak
Even-odd jitter, peak-to-peak
18.6
18.4
7.1
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
20% to 80%, 8H8L test pattern, 13.0
Gbps
tTHL
PRBS-7 test pattern, JMODE = 5, 13.0
Gbps
DDJ
DDJ
DCD
DCD
EBUJ
EBUJ
RJ
PRBS-9 test pattern, JMODE = 44,
10.725 Gbps
7.1
PRBS-7 test pattern, JMODE = 5, 13.0
Gbps
0.22
0.06
1.7
PRBS-9 test pattern, JMODE = 44,
10.725 Gbps
Even-odd jitter, peak-to-peak
Effective bounded uncorrelated jitter, peak- PRBS-7 test pattern, JMODE = 5, 13.0
to-peak Gbps
Effective bounded uncorrelated jitter, peak- PRBS-9 test pattern, JMODE = 44,
0.30
0.75
1.1
to-peak
10.725 Gbps
8H8L test pattern, JMODE = 5, 13.0
Gbps
Unbounded random jitter, RMS
8H8L test pattern, JMODE = 44, 10.725
Gbps
RJ
Unbounded random jitter, RMS
Total jitter, peak-to-peak, with unbounded
random jitter portion defined with respect to
a BER = 1e-15 (Q = 7.94)
PRBS-7 test pattern, JMODE = 5, 13.0
Gbps
TJ
TJ
18.5
25.4
ps
ps
Total jitter, peak-to-peak, with unbounded
random jitter portion defined with respect to
a BER = 1e-15 (Q = 7.94)
PRBS-9 test pattern, JMODE = 44,
10.725 Gbps
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6.10 Switching Characteristics (continued)
typical values at TA = 25°C, VA19 = 1.9 V, VA11 = 1.1 V, VD11 = 1.1 V, default full-scale voltage, fIN = 347 MHz, AIN = –1
dBFS, fCLK = 5.2 GHz, filtered 1-VPP sine-wave clock, JMODE = 6, Dither enabled with default settings, VA11, VD11 and
VS11 noise suppression ON (EN_VA11_NOISE_SUPPR = EN_VD11_NOISE_SUPPR = EN_VS11_NOISE_SUPPR = 1),
and background calibration (unless otherwise noted); minimum and maximum values are at nominal supply voltages and
over the operating free-air temperature range provided in the Recommended Operating Conditions table
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ADC CORE LATENCY
JMODE = 5, 44
-9.5
-10
tCLK cycles
tCLK cycles
tCLK cycles
tCLK cycles
tCLK cycles
tCLK cycles
tCLK cycles
JMODE = 7
Deterministic delay from the CLK± edge
that samples the reference sample to the
CLK± edge that samples SYSREF going
high(1)
JMODE = 6, 50
JMODE = 8, 51
JMODE = 34
JMODE = 35
JMODE = 45
-13.5
-14
tADC
6.5
6
-10.0
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6.10 Switching Characteristics (continued)
typical values at TA = 25°C, VA19 = 1.9 V, VA11 = 1.1 V, VD11 = 1.1 V, default full-scale voltage, fIN = 347 MHz, AIN = –1
dBFS, fCLK = 5.2 GHz, filtered 1-VPP sine-wave clock, JMODE = 6, Dither enabled with default settings, VA11, VD11 and
VS11 noise suppression ON (EN_VA11_NOISE_SUPPR = EN_VD11_NOISE_SUPPR = EN_VS11_NOISE_SUPPR = 1),
and background calibration (unless otherwise noted); minimum and maximum values are at nominal supply voltages and
over the operating free-air temperature range provided in the Recommended Operating Conditions table
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
JESD204C AND SERIALIZER LATENCY
JMODE = 5
143
191
143
102
103
179
267
268
168
215
168
119
119
202
291
291
JMODE = 6, 8
JMODE = 7
Delay from the CLK± rising edge that
samples SYSREF high to the first bit of the
multiframe (8B/10B encoding) or extended
multiblock (64B/66B encoding) on the
JESD204C serial output lane
JMODE = 34
JMODE = 35
JMODE = 44, 45
JMODE = 50
JMODE = 51
tTX
tCLK cycles
corresponding to the reference sample of
(2)
tADC
SERIAL PROGRAMMING INTERFACE (SDO)
Delay from the falling edge of the 16th SCLK cycle during read operation for SDO
transition from tri-state to valid data
t(OZD)
1
ns
t(ODZ)
t(OD)
Delay from the SCS rising edge for SDO transition from valid data to tri-state
Delay from the falling edge of SCLK during read operation to SDO valid
10
12
ns
ns
1
(1) tADC is an exact, unrounded, deterministic delay. The delay can be negative if the reference sample is sampled after the SYSREF high
capture point, in which case the total latency is smaller than the delay given by tTX
.
(2) The values given for tTX include deterministic and non-deterministic delays. Over process, temperature, and voltage, the delay will
vary. JESD204B accounts for these variations when operating in subclass-1 mode in order to achieve deterministic latency. Proper
receiver RBD values must be chosen such that the elastic buffer release point does not occur within the invalid region of the local
multiframe clock (LMFC) cycle.
(3) tAJ increases because of additional attenuation on the internal clock path.
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6.11 Typical Characteristics
typical values at TA = 25°C, VA19 = 1.9 V, VA11 = VD11 = 1.1 V, default full-scale voltage (FS_RANGE_A = FS_RANGE_B =
0xA000), input signal applied to INA± in single-channel modes, fIN = 347 MHz, AIN = –1 dBFS, fCLK = 5.2GHz, filtered, 1-VPP
sine-wave clock, JMODE = 7, dither enabled with default settings, VA11, VD11 and VS11 noise suppression ON
(EN_VA11_NOISE_SUPPR = EN_VD11_NOISE_SUPPR = EN_VS11_NOISE_SUPPR = 1), and background calibration
(unless otherwise noted); SNR results exclude DC, HD2 to HD9 and interleaving spurs; SINAD, ENOB, and SFDR results
exclude DC and fixed-frequency interleaving spurs
Relative to 0 Hz, FG calibration
Dual channel mode, JMODE 8
图6-1. Input Amplitude vs Input Frequency
图6-2. Crosstalk vs Input Frequency
图6-3. DNL vs ADC Code
图6-4. INL vs ADC Code
图6-5. DES Mode: Single Tone FFT at 347 MHz
图6-6. DES Mode: Single Tone FFT at 897 MHz
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6.11 Typical Characteristics (continued)
typical values at TA = 25°C, VA19 = 1.9 V, VA11 = VD11 = 1.1 V, default full-scale voltage (FS_RANGE_A = FS_RANGE_B =
0xA000), input signal applied to INA± in single-channel modes, fIN = 347 MHz, AIN = –1 dBFS, fCLK = 5.2GHz, filtered, 1-VPP
sine-wave clock, JMODE = 7, dither enabled with default settings, VA11, VD11 and VS11 noise suppression ON
(EN_VA11_NOISE_SUPPR = EN_VD11_NOISE_SUPPR = EN_VS11_NOISE_SUPPR = 1), and background calibration
(unless otherwise noted); SNR results exclude DC, HD2 to HD9 and interleaving spurs; SINAD, ENOB, and SFDR results
exclude DC and fixed-frequency interleaving spurs
图6-7. DES Mode: Single Tone FFT at 2397 MHz
图6-8. DES Mode: Single Tone FFT at 4197 MHz
图6-9. DES Mode: Single Tone FFT at 5597 MHz
图6-10. DES Mode: Single Tone FFT at 7997 MHz
each tone at -7 dBFS, 100 MHz Tone Spacing
each tone at -7 dBFS, 100 MHz Tone Spacing
图6-11. DES Mode: Two Tone FFT at 347 MHz
图6-12. DES Mode: Two Tone FFT at 897 MHz
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6.11 Typical Characteristics (continued)
typical values at TA = 25°C, VA19 = 1.9 V, VA11 = VD11 = 1.1 V, default full-scale voltage (FS_RANGE_A = FS_RANGE_B =
0xA000), input signal applied to INA± in single-channel modes, fIN = 347 MHz, AIN = –1 dBFS, fCLK = 5.2GHz, filtered, 1-VPP
sine-wave clock, JMODE = 7, dither enabled with default settings, VA11, VD11 and VS11 noise suppression ON
(EN_VA11_NOISE_SUPPR = EN_VD11_NOISE_SUPPR = EN_VS11_NOISE_SUPPR = 1), and background calibration
(unless otherwise noted); SNR results exclude DC, HD2 to HD9 and interleaving spurs; SINAD, ENOB, and SFDR results
exclude DC and fixed-frequency interleaving spurs
each tone at -7 dBFS, 100 MHz Tone Spacing
each tone at -7dBFS, 100MHz Tone Spacing
图6-13. DES Mode: Two Tone FFT at 2397 MHz
图6-14. DES Mode: Two Tone FFT at 4197 MHz
each tone at -7 dBFS, 100 MHz Tone Spacing
each tone at -7 dBFS, 100 MHz Tone Spacing
图6-15. DES Mode: Two Tone FFT at 5597 MHz
图6-16. DES Mode: Two Tone FFT at 7997 MHz
图6-17. Dual Channel Mode: Single Tone FFT at 347 MHz
图6-18. Dual Channel Mode: Single Tone FFT at 897 MHz
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6.11 Typical Characteristics (continued)
typical values at TA = 25°C, VA19 = 1.9 V, VA11 = VD11 = 1.1 V, default full-scale voltage (FS_RANGE_A = FS_RANGE_B =
0xA000), input signal applied to INA± in single-channel modes, fIN = 347 MHz, AIN = –1 dBFS, fCLK = 5.2GHz, filtered, 1-VPP
sine-wave clock, JMODE = 7, dither enabled with default settings, VA11, VD11 and VS11 noise suppression ON
(EN_VA11_NOISE_SUPPR = EN_VD11_NOISE_SUPPR = EN_VS11_NOISE_SUPPR = 1), and background calibration
(unless otherwise noted); SNR results exclude DC, HD2 to HD9 and interleaving spurs; SINAD, ENOB, and SFDR results
exclude DC and fixed-frequency interleaving spurs
图6-19. Dual Channel Mode: Single Tone FFT at 2397 MHz
图6-20. Dual Channel Mode: Single Tone FFT at 4197 MHz
图6-21. Dual Channel Mode: Single Tone FFT at 5597 MHz
图6-22. Dual Channel Mode: Single Tone FFT at 7997 MHz
each tone at -7 dBFS, 100 MHz Tone Spacing
each tone at -7 dBFS, 100 MHz Tone Spacing
图6-23. Dual Channel Mode: Two Tone FFT at 347 MHz
图6-24. Dual Channel Mode: Two Tone FFT at 897 MHz
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6.11 Typical Characteristics (continued)
typical values at TA = 25°C, VA19 = 1.9 V, VA11 = VD11 = 1.1 V, default full-scale voltage (FS_RANGE_A = FS_RANGE_B =
0xA000), input signal applied to INA± in single-channel modes, fIN = 347 MHz, AIN = –1 dBFS, fCLK = 5.2GHz, filtered, 1-VPP
sine-wave clock, JMODE = 7, dither enabled with default settings, VA11, VD11 and VS11 noise suppression ON
(EN_VA11_NOISE_SUPPR = EN_VD11_NOISE_SUPPR = EN_VS11_NOISE_SUPPR = 1), and background calibration
(unless otherwise noted); SNR results exclude DC, HD2 to HD9 and interleaving spurs; SINAD, ENOB, and SFDR results
exclude DC and fixed-frequency interleaving spurs
each tone at -7 dBFS, 100 MHz Tone Spacing
each tone at -7 dBFS, 100 MHz Tone Spacing
图6-25. Dual Channel Mode: Two Tone FFT at 897 MHz
图6-26. Dual Channel Mode: Two Tone FFT at 4197 MHz
each tone at -7 dBFS, 100 MHz Tone Spacing
each tone at -7 dBFS, 100 MHz Tone Spacing
图6-27. Dual Channel Mode: Two Tone FFT at 5597 MHz
图6-28. Dual Channel Mode: Two Tone FFT at 7997 MHz
AIN = -1 dBFS
AIN = -6 dBFS
图6-29. DES Mode: SNR vs Sample Rate
图6-30. DES Mode: SNR vs Sample Rate
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6.11 Typical Characteristics (continued)
typical values at TA = 25°C, VA19 = 1.9 V, VA11 = VD11 = 1.1 V, default full-scale voltage (FS_RANGE_A = FS_RANGE_B =
0xA000), input signal applied to INA± in single-channel modes, fIN = 347 MHz, AIN = –1 dBFS, fCLK = 5.2GHz, filtered, 1-VPP
sine-wave clock, JMODE = 7, dither enabled with default settings, VA11, VD11 and VS11 noise suppression ON
(EN_VA11_NOISE_SUPPR = EN_VD11_NOISE_SUPPR = EN_VS11_NOISE_SUPPR = 1), and background calibration
(unless otherwise noted); SNR results exclude DC, HD2 to HD9 and interleaving spurs; SINAD, ENOB, and SFDR results
exclude DC and fixed-frequency interleaving spurs
AIN = -12 dBFS
AIN = -1 dBFS
图6-31. DES Mode: SNR vs Sample Rate
图6-32. DES Mode: SFDR vs Sample Rate
AIN = -6 dBFS
AIN = -12 dBFS
图6-33. DES Mode: SFDR vs Sample Rate
图6-34. DES Mode: SFDR vs Sample Rate
AIN = -1 dBFS
AIN = -6 dBFS
图6-35. DES Mode: HD2 vs Sample Rate
图6-36. DES Mode: HD2 vs Sample Rate
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6.11 Typical Characteristics (continued)
typical values at TA = 25°C, VA19 = 1.9 V, VA11 = VD11 = 1.1 V, default full-scale voltage (FS_RANGE_A = FS_RANGE_B =
0xA000), input signal applied to INA± in single-channel modes, fIN = 347 MHz, AIN = –1 dBFS, fCLK = 5.2GHz, filtered, 1-VPP
sine-wave clock, JMODE = 7, dither enabled with default settings, VA11, VD11 and VS11 noise suppression ON
(EN_VA11_NOISE_SUPPR = EN_VD11_NOISE_SUPPR = EN_VS11_NOISE_SUPPR = 1), and background calibration
(unless otherwise noted); SNR results exclude DC, HD2 to HD9 and interleaving spurs; SINAD, ENOB, and SFDR results
exclude DC and fixed-frequency interleaving spurs
AIN = -12 dBFS
AIN = -1 dBFS
图6-37. DES Mode: HD2 vs Sample Rate
图6-38. DES Mode: HD3 vs Sample Rate
AIN = -6 dBFS
AIN = -12 dBFS
图6-39. DES Mode: HD3 vs Sample Rate
图6-40. DES Mode: HD3 vs Sample Rate
图6-41. DES Mode: FS/2 - FIN vs Sample Rate
图6-42. DES Mode: FS/4 + FIN vs Sample Rate
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6.11 Typical Characteristics (continued)
typical values at TA = 25°C, VA19 = 1.9 V, VA11 = VD11 = 1.1 V, default full-scale voltage (FS_RANGE_A = FS_RANGE_B =
0xA000), input signal applied to INA± in single-channel modes, fIN = 347 MHz, AIN = –1 dBFS, fCLK = 5.2GHz, filtered, 1-VPP
sine-wave clock, JMODE = 7, dither enabled with default settings, VA11, VD11 and VS11 noise suppression ON
(EN_VA11_NOISE_SUPPR = EN_VD11_NOISE_SUPPR = EN_VS11_NOISE_SUPPR = 1), and background calibration
(unless otherwise noted); SNR results exclude DC, HD2 to HD9 and interleaving spurs; SINAD, ENOB, and SFDR results
exclude DC and fixed-frequency interleaving spurs
图6-43. DES Mode: FS/4 - FIN vs Sample Rate
AIN = -1 dBFS
图6-44. Dual Channel Mode: SNR vs Sample Rate
AIN = -6 dBFS
AIN = -12 dBFS
图6-45. Dual Channel Mode: SNR vs Sample Rate
图6-46. Dual Channel Mode: SNR vs Sample Rate
AIN = -1 dBFS
AIN = -6 dBFS
图6-47. Dual Channel Mode: SFDR vs Sample Rate
图6-48. Dual Channel Mode: SFDR vs Sample Rate
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6.11 Typical Characteristics (continued)
typical values at TA = 25°C, VA19 = 1.9 V, VA11 = VD11 = 1.1 V, default full-scale voltage (FS_RANGE_A = FS_RANGE_B =
0xA000), input signal applied to INA± in single-channel modes, fIN = 347 MHz, AIN = –1 dBFS, fCLK = 5.2GHz, filtered, 1-VPP
sine-wave clock, JMODE = 7, dither enabled with default settings, VA11, VD11 and VS11 noise suppression ON
(EN_VA11_NOISE_SUPPR = EN_VD11_NOISE_SUPPR = EN_VS11_NOISE_SUPPR = 1), and background calibration
(unless otherwise noted); SNR results exclude DC, HD2 to HD9 and interleaving spurs; SINAD, ENOB, and SFDR results
exclude DC and fixed-frequency interleaving spurs
AIN = -12 dBFS
AIN = -1 dBFS
图6-49. Dual Channel Mode: SFDR vs Sample Rate
图6-50. Dual Channel Mode: HD2 vs Sample Rate
AIN = -6 dBFS
AIN = -12 dBFS
图6-51. Dual Channel Mode: HD2 vs Sample Rate
图6-52. Dual Channel Mode: HD2 vs Sample Rate
AIN = -1 dBFS
AIN = -6 dBFS
图6-53. Dual Channel Mode: HD3 vs Sample Rate
图6-54. Dual Channel Mode: HD3 vs Sample Rate
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6.11 Typical Characteristics (continued)
typical values at TA = 25°C, VA19 = 1.9 V, VA11 = VD11 = 1.1 V, default full-scale voltage (FS_RANGE_A = FS_RANGE_B =
0xA000), input signal applied to INA± in single-channel modes, fIN = 347 MHz, AIN = –1 dBFS, fCLK = 5.2GHz, filtered, 1-VPP
sine-wave clock, JMODE = 7, dither enabled with default settings, VA11, VD11 and VS11 noise suppression ON
(EN_VA11_NOISE_SUPPR = EN_VD11_NOISE_SUPPR = EN_VS11_NOISE_SUPPR = 1), and background calibration
(unless otherwise noted); SNR results exclude DC, HD2 to HD9 and interleaving spurs; SINAD, ENOB, and SFDR results
exclude DC and fixed-frequency interleaving spurs
图6-56. Dual Channel Mode: FS/2 - FIN vs Sample Rate
AIN = -12 dBFS
图6-55. Dual Channel Mode: HD3 vs Sample Rate
图6-57. DES Mode: SNR vs Input Amplitude
图6-58. DES Mode: SNR vs Input Amplitude and Dither
图6-59. DES Mode: SFDR vs Input Amplitude
图6-60. DES Mode: SFDR vs Input Amplitude and Dither
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6.11 Typical Characteristics (continued)
typical values at TA = 25°C, VA19 = 1.9 V, VA11 = VD11 = 1.1 V, default full-scale voltage (FS_RANGE_A = FS_RANGE_B =
0xA000), input signal applied to INA± in single-channel modes, fIN = 347 MHz, AIN = –1 dBFS, fCLK = 5.2GHz, filtered, 1-VPP
sine-wave clock, JMODE = 7, dither enabled with default settings, VA11, VD11 and VS11 noise suppression ON
(EN_VA11_NOISE_SUPPR = EN_VD11_NOISE_SUPPR = EN_VS11_NOISE_SUPPR = 1), and background calibration
(unless otherwise noted); SNR results exclude DC, HD2 to HD9 and interleaving spurs; SINAD, ENOB, and SFDR results
exclude DC and fixed-frequency interleaving spurs
图6-61. DES Mode: HD2 vs Input Amplitude
图6-62. DES Mode: HD2 vs Input Amplitude and Dither
图6-63. DES Mode: HD3 vs Input Amplitude
图6-64. DES Mode: HD3 vs Input Amplitude and Dither
图6-65. DES Mode: FS/2 - FIN vs Input Amplitude
图6-66. DES Mode: FS/2 - FIN vs Input Amplitude and Dither
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6.11 Typical Characteristics (continued)
typical values at TA = 25°C, VA19 = 1.9 V, VA11 = VD11 = 1.1 V, default full-scale voltage (FS_RANGE_A = FS_RANGE_B =
0xA000), input signal applied to INA± in single-channel modes, fIN = 347 MHz, AIN = –1 dBFS, fCLK = 5.2GHz, filtered, 1-VPP
sine-wave clock, JMODE = 7, dither enabled with default settings, VA11, VD11 and VS11 noise suppression ON
(EN_VA11_NOISE_SUPPR = EN_VD11_NOISE_SUPPR = EN_VS11_NOISE_SUPPR = 1), and background calibration
(unless otherwise noted); SNR results exclude DC, HD2 to HD9 and interleaving spurs; SINAD, ENOB, and SFDR results
exclude DC and fixed-frequency interleaving spurs
图6-67. DES Mode: FS/4 + FIN vs Input Amplitude
图6-68. DES Mode: FS/4 + FIN vs Input Amplitude and Dither
图6-69. DES Mode: FS/4 - FIN vs Input Amplitude
图6-70. DES Mode: FS/4 - FIN vs Input Amplitude and Dither
图6-71. Dual Channel Mode: SNR vs Input Amplitude
图6-72. Dual Channel Mode: SNR vs Input Amplitude and Dither
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6.11 Typical Characteristics (continued)
typical values at TA = 25°C, VA19 = 1.9 V, VA11 = VD11 = 1.1 V, default full-scale voltage (FS_RANGE_A = FS_RANGE_B =
0xA000), input signal applied to INA± in single-channel modes, fIN = 347 MHz, AIN = –1 dBFS, fCLK = 5.2GHz, filtered, 1-VPP
sine-wave clock, JMODE = 7, dither enabled with default settings, VA11, VD11 and VS11 noise suppression ON
(EN_VA11_NOISE_SUPPR = EN_VD11_NOISE_SUPPR = EN_VS11_NOISE_SUPPR = 1), and background calibration
(unless otherwise noted); SNR results exclude DC, HD2 to HD9 and interleaving spurs; SINAD, ENOB, and SFDR results
exclude DC and fixed-frequency interleaving spurs
图6-73. Dual Channel Mode: SFDR vs Input Amplitude
图6-74. Dual Channel Mode: SFDR vs Input Amplitude and
Dither
图6-75. Dual Channel Mode: HD2 vs Input Amplitude
图6-76. Dual Channel Mode: HD2 vs Input Amplitude and Dither
图6-77. Dual Channel Mode: HD3 vs Input Amplitude
图6-78. Dual Channel Mode: HD3 vs Input Amplitude and Dither
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6.11 Typical Characteristics (continued)
typical values at TA = 25°C, VA19 = 1.9 V, VA11 = VD11 = 1.1 V, default full-scale voltage (FS_RANGE_A = FS_RANGE_B =
0xA000), input signal applied to INA± in single-channel modes, fIN = 347 MHz, AIN = –1 dBFS, fCLK = 5.2GHz, filtered, 1-VPP
sine-wave clock, JMODE = 7, dither enabled with default settings, VA11, VD11 and VS11 noise suppression ON
(EN_VA11_NOISE_SUPPR = EN_VD11_NOISE_SUPPR = EN_VS11_NOISE_SUPPR = 1), and background calibration
(unless otherwise noted); SNR results exclude DC, HD2 to HD9 and interleaving spurs; SINAD, ENOB, and SFDR results
exclude DC and fixed-frequency interleaving spurs
图6-79. Dual Channel Mode: FS/2 - FIN vs Input Amplitude
图6-80. Dual Channel Mode: FS/2 - FIN vs Input Amplitude and
Dither
图6-81. DES Mode: SNR vs Clock Amplitude
图6-82. DES Mode: SFDR vs Clock Amplitude
图6-83. Dual Channel Mode: SNR vs Clock Amplitude
图6-84. Dual Channel Mode: SFDR vs Clock Amplitude
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6.11 Typical Characteristics (continued)
typical values at TA = 25°C, VA19 = 1.9 V, VA11 = VD11 = 1.1 V, default full-scale voltage (FS_RANGE_A = FS_RANGE_B =
0xA000), input signal applied to INA± in single-channel modes, fIN = 347 MHz, AIN = –1 dBFS, fCLK = 5.2GHz, filtered, 1-VPP
sine-wave clock, JMODE = 7, dither enabled with default settings, VA11, VD11 and VS11 noise suppression ON
(EN_VA11_NOISE_SUPPR = EN_VD11_NOISE_SUPPR = EN_VS11_NOISE_SUPPR = 1), and background calibration
(unless otherwise noted); SNR results exclude DC, HD2 to HD9 and interleaving spurs; SINAD, ENOB, and SFDR results
exclude DC and fixed-frequency interleaving spurs
FG calibration at each temperature
FG calibration at each temperature
图6-85. DES Mode: SNR, SINAD and SFDR vs Temperature
图6-86. DES Mode: HD2, HD3 and Worst Spur vs Temperature
FG25 is calibrated at 25°C and held at other temperatures,
other modes recalibrated at each temperature
FG25 is calibrated at 25°C and held at other temperatures,
other modes recalibrated at each temperature
图6-87. DES Mode: SNR vs Temperature and Calibration
图6-88. DES Mode: SFDR vs Temperature and Calibration
FG calibration at each temperature
FG calibration at each temperature
图6-89. Dual Channel Mode: SNR, SINAD and SFDR vs
图6-90. Dual Channel Mode: HD2, HD3 and Worst Spur vs
Temperature
Temperature
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6.11 Typical Characteristics (continued)
typical values at TA = 25°C, VA19 = 1.9 V, VA11 = VD11 = 1.1 V, default full-scale voltage (FS_RANGE_A = FS_RANGE_B =
0xA000), input signal applied to INA± in single-channel modes, fIN = 347 MHz, AIN = –1 dBFS, fCLK = 5.2GHz, filtered, 1-VPP
sine-wave clock, JMODE = 7, dither enabled with default settings, VA11, VD11 and VS11 noise suppression ON
(EN_VA11_NOISE_SUPPR = EN_VD11_NOISE_SUPPR = EN_VS11_NOISE_SUPPR = 1), and background calibration
(unless otherwise noted); SNR results exclude DC, HD2 to HD9 and interleaving spurs; SINAD, ENOB, and SFDR results
exclude DC and fixed-frequency interleaving spurs
FG25 is calibrated at 25°C and held at other temperatures,
other modes recalibrated at each temperature
FG25 is calibrated at 25°C and held at other temperatures,
other modes recalibrated at each temperature
图6-91. Dual Channel Mode: SNR vs Temperature and
图6-92. Dual Channel Mode: SFDR vs Temperature and
Calibration
Calibration
All supplies varied together
All supplies varied together
图6-93. DES Mode: SNR, SINAD and SFDR vs Supply Voltage
图6-94. DES Mode: HD2, HD3 and Worst Spur vs Supply
Voltage
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6.11 Typical Characteristics (continued)
typical values at TA = 25°C, VA19 = 1.9 V, VA11 = VD11 = 1.1 V, default full-scale voltage (FS_RANGE_A = FS_RANGE_B =
0xA000), input signal applied to INA± in single-channel modes, fIN = 347 MHz, AIN = –1 dBFS, fCLK = 5.2GHz, filtered, 1-VPP
sine-wave clock, JMODE = 7, dither enabled with default settings, VA11, VD11 and VS11 noise suppression ON
(EN_VA11_NOISE_SUPPR = EN_VD11_NOISE_SUPPR = EN_VS11_NOISE_SUPPR = 1), and background calibration
(unless otherwise noted); SNR results exclude DC, HD2 to HD9 and interleaving spurs; SINAD, ENOB, and SFDR results
exclude DC and fixed-frequency interleaving spurs
49
48.75
48.5
48.25
48
70
69
68
67
66
65
64
47.75
47.5
47.25
47
SNR
SINAD
-5
-2.5
0
2.5
5
-5
-2.5
0
2.5
5
Supply Voltage (% Variation from Nominal)
Supply Voltage (% Variation from Nominal)
All supplies varied together
All supplies varied together
图6-95. Dual Channel Mode: SNR and SINAD vs Supply Voltage
图6-96. Dual Channel Mode: SFDR vs Supply Voltage
-66
HD2
HD3
non-HD Spur
-67
-68
-69
-70
-71
-72
-73
-74
-75
-76
-5
-2.5
0
2.5
5
Supply Voltage (% Variation from Nominal)
图6-98. DES Mode: SNR, SFDR and SINAD vs Input Common
All supplies varied together
Mode Voltage
图6-97. Dual Channel Mode: HD2, HD3 and Worst Spur vs
Supply Voltage
图6-99. DES Mode: FS/2-FIN, FS/4 +/-FIN vs Input Common Mode
each tone -7dBFS, 100MHz tone spacing
Voltage
图6-100. DES Mode: IMD3 vs Input Frequency
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6.11 Typical Characteristics (continued)
typical values at TA = 25°C, VA19 = 1.9 V, VA11 = VD11 = 1.1 V, default full-scale voltage (FS_RANGE_A = FS_RANGE_B =
0xA000), input signal applied to INA± in single-channel modes, fIN = 347 MHz, AIN = –1 dBFS, fCLK = 5.2GHz, filtered, 1-VPP
sine-wave clock, JMODE = 7, dither enabled with default settings, VA11, VD11 and VS11 noise suppression ON
(EN_VA11_NOISE_SUPPR = EN_VD11_NOISE_SUPPR = EN_VS11_NOISE_SUPPR = 1), and background calibration
(unless otherwise noted); SNR results exclude DC, HD2 to HD9 and interleaving spurs; SINAD, ENOB, and SFDR results
exclude DC and fixed-frequency interleaving spurs
图6-102. DES Mode: IMD3 vs Tone Spacing
100MHz tone spacing
图6-101. DES Mode: IMD3 vs Input Amplitude
each tone -7 dBFS, 100MHz tone spacing, not including IMD3
spurs
not including IMD3 spurs, 100MHz tone spacing
图6-104. DES Mode: Two Tone SFDR vs Input Amplitude
图6-103. DES Mode: Two Tone SFDR vs Input Frequency
each tone -7 dBFS, 100MHz tone spacing
each tone -7 dBFS, 100MHz tone spacing
图6-105. Dual Channel Mode: IMD3 vs Input Frequency
图6-106. Dual Channel Mode: IMD3 vs Input Amplitude
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6.11 Typical Characteristics (continued)
typical values at TA = 25°C, VA19 = 1.9 V, VA11 = VD11 = 1.1 V, default full-scale voltage (FS_RANGE_A = FS_RANGE_B =
0xA000), input signal applied to INA± in single-channel modes, fIN = 347 MHz, AIN = –1 dBFS, fCLK = 5.2GHz, filtered, 1-VPP
sine-wave clock, JMODE = 7, dither enabled with default settings, VA11, VD11 and VS11 noise suppression ON
(EN_VA11_NOISE_SUPPR = EN_VD11_NOISE_SUPPR = EN_VS11_NOISE_SUPPR = 1), and background calibration
(unless otherwise noted); SNR results exclude DC, HD2 to HD9 and interleaving spurs; SINAD, ENOB, and SFDR results
exclude DC and fixed-frequency interleaving spurs
图6-107. Dual Channel Mode: IMD3 vs Tone Spacing
each tone -7 dBFS, 100MHz tone spacing, not including IMD3
spurs
图6-108. Dual Channel Mode: Two Tone SFDR vs Input
Frequency
1.44
BG
FG
LPBG
1.36
1.28
1.2
1.12
1.04
0.96
0.88
2000
4000
6000
8000
10000
Sample Rate (MSPS)
not including IMD3 spurs, 100MHz tone spacing
Independent of JMODE
图6-110. DES Mode: IVA19 vs Sample Rate
图6-109. Dual Channel Mode: Two Tone SFDR vs Input
Amplitude
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6.11 Typical Characteristics (continued)
typical values at TA = 25°C, VA19 = 1.9 V, VA11 = VD11 = 1.1 V, default full-scale voltage (FS_RANGE_A = FS_RANGE_B =
0xA000), input signal applied to INA± in single-channel modes, fIN = 347 MHz, AIN = –1 dBFS, fCLK = 5.2GHz, filtered, 1-VPP
sine-wave clock, JMODE = 7, dither enabled with default settings, VA11, VD11 and VS11 noise suppression ON
(EN_VA11_NOISE_SUPPR = EN_VD11_NOISE_SUPPR = EN_VS11_NOISE_SUPPR = 1), and background calibration
(unless otherwise noted); SNR results exclude DC, HD2 to HD9 and interleaving spurs; SINAD, ENOB, and SFDR results
exclude DC and fixed-frequency interleaving spurs
Independent of JMODE
JMODE 7
图6-111. DES Mode: IVA11 vs Sample Rate
图6-112. DES Mode: IVD11 vs Sample Rate
1.4
1.35
1.3
BG
FG
LPBG
1.25
1.2
1.15
1.1
1.05
1
1000 1500 2000 2500 3000 3500 4000 4500 5000 5500
Sample Rate (MSPS)
JMODE 7
Independent of JMODE
图6-113. DES Mode: Power Dissipation vs Sample Rate
图6-114. Dual Channel Mode: IVA19 vs Sample Rate
Independent of JMODE
JMODE 8
图6-115. Dual Channel Mode: IVA11 vs Sample Rate
图6-116. Dual Channel Mode: IVD11 vs Sample Rate
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6.11 Typical Characteristics (continued)
typical values at TA = 25°C, VA19 = 1.9 V, VA11 = VD11 = 1.1 V, default full-scale voltage (FS_RANGE_A = FS_RANGE_B =
0xA000), input signal applied to INA± in single-channel modes, fIN = 347 MHz, AIN = –1 dBFS, fCLK = 5.2GHz, filtered, 1-VPP
sine-wave clock, JMODE = 7, dither enabled with default settings, VA11, VD11 and VS11 noise suppression ON
(EN_VA11_NOISE_SUPPR = EN_VD11_NOISE_SUPPR = EN_VS11_NOISE_SUPPR = 1), and background calibration
(unless otherwise noted); SNR results exclude DC, HD2 to HD9 and interleaving spurs; SINAD, ENOB, and SFDR results
exclude DC and fixed-frequency interleaving spurs
JMODE 8
JMODES 7 (DES) and 8 (Dual Channel)
图6-117. Dual Chanel Mode: Power Dissipation vs Sample Rate
图6-118. Power Dissipation vs Temperature
图6-119. Background Calibration Core Transition (AC Signal)
图6-120. Background Calibration Core Transition (AC Signal
Zoomed)
图6-121. Background Calibration Core Transition (DC Signal)
图6-122. Background Calibration Core Transition (DC Signal
Zoomed)
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6.11 Typical Characteristics (continued)
typical values at TA = 25°C, VA19 = 1.9 V, VA11 = VD11 = 1.1 V, default full-scale voltage (FS_RANGE_A = FS_RANGE_B =
0xA000), input signal applied to INA± in single-channel modes, fIN = 347 MHz, AIN = –1 dBFS, fCLK = 5.2GHz, filtered, 1-VPP
sine-wave clock, JMODE = 7, dither enabled with default settings, VA11, VD11 and VS11 noise suppression ON
(EN_VA11_NOISE_SUPPR = EN_VD11_NOISE_SUPPR = EN_VS11_NOISE_SUPPR = 1), and background calibration
(unless otherwise noted); SNR results exclude DC, HD2 to HD9 and interleaving spurs; SINAD, ENOB, and SFDR results
exclude DC and fixed-frequency interleaving spurs
8000
7000
6000
5000
4000
3000
2000
1000
0
7000
6000
5000
4000
3000
2000
1000
ADC output code
Input pulse (8 GHz BW)
ADC output code
Input pulse (8 GHz BW)
Zoomed area
in next plot
-6000
-2000
2000
6000
Time (ps)
10000
14000
5600 5620 5640 5660 5680 5700 5720 5740 5760 5780 5800
Time (ps)
图6-123. Pulse Overdrive Recovery
图6-124. Pulse Overdrive Recovery Zoomed
11000
10000
9000
8000
7000
6000
5000
4000
3000
2000
1000
4500
ADC Output Code
Matched Sinewave
4000
3500
3000
2500
2000
1500
Zoomed area
in next plot
ADC Output Code
Matched Sinewave
0
25
50
75
100 125 150 175 200 225
Time (ps)
30
35
40
45
50
Time (ps)
55
60
65
70
图6-125. Sinewave Overdrive Recovery
图6-126. Sinewave Overdrive Recovery
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7 Detailed Description
7.1 Overview
ADC08DJ5200RF device is an RF-sampling, giga-sample, analog-to-digital converter (ADC) that can directly
sample input frequencies from DC to above 10 GHz. In dual-channel mode, the device can sample up to 5.2
GSPS and up to 10.4 GSPS in single-channel mode. Programmable tradeoffs in channel count (dual-channel
mode) and Nyquist bandwidth (single-channel mode) allow development of flexible hardware that meets the
needs of both high channel count or wide instantaneous signal bandwidth applications. Full-power input
bandwidth (–3 dB) of 8.0 GHz, with usable frequencies exceeding the –3-dB point in both dual- and single-
channel modes, allows direct RF sampling of L-band, S-band, C-band, and X-band for frequency agile systems.
The device uses a high-speed JESD204C output interface with up to 16 serialized lanes and subclass-1
compliance for deterministic latency and multi-device synchronization. The serial output lanes support up to
17.16 Gbps and can be configured to trade-off bit rate and number of lanes. Both 8B/10B and 64B/66B data
encoding schemes are supported. The 64B/66B encoding schemes support forward error correction (FEC) for
improved bit error rates. The JESD204C interface is backwards compatible with JESD204B receivers when
using 8B/10B encoding modes.
A number of synchronization features, including noiseless aperture delay (tAD) adjustment and SYSREF
windowing, simplify system design for multi-channel systems. Aperture delay adjustment can be used to simplify
SYSREF capture, to align the sampling instance between multiple ADCs or to sample an ideal location of a front-
end track and hold (T&H) amplifier output. SYSREF windowing offers a simplistic way to measure invalid timing
regions of SYSREF relative to the device clock and then choose an optimal sampling location. Dual-edge
sampling (DES) is implemented in single-channel mode to reduce the maximum clock rate applied to the ADC to
support a wide range of clock sources and relax setup and hold timing for SYSREF capture.
The device provides foreground and background calibration options for gain, offset and static linearity errors.
Foreground calibration is run at system startup or at specified times during which the ADC is offline and not
sending data to the logic device. Background calibration allows the ADC to run continually while the cores are
calibrated in the background so that the system does not experience downtime. The calibration routine is also
used to match the gain and offset between sub-ADC cores to minimize spurious artifacts from time interleaving.
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7.2 Functional Block Diagram
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7.3 Feature Description
7.3.1 Device Comparison
The devices listed in 表 7-1 are part of a pin-to-pin compatible, high-speed, wide-bandwidth ADC family. The
family is offered to provide a scalable family of devices for varying resolution, sampling rate and signal
bandwidth.
表7-1. Device Family Comparison
MAXIMUM
SAMPLING RATE
DUAL CHANNEL
DECIMATION
SINGLE CHANNEL
DECIMATION
INTERFACE
(MAX LINERATE)
PART NUMBER
RESOLUTION
JESD204B /
JESD204C
(17.16 Gbps)
Single 10.4 GSPS
Dual 5.2 GSPS
ADC12DJ5200RF
12-bit
Complex: 4x, 8x, 16x, 32x Complex: 4x, 8x, 16x, 32x
JESD204B /
JESD204C
(17.16 Gbps)
Single 10.4 GSPS
Dual 5.2 GSPS
ADC08DJ5200RF
ADC12DJ4000RF
8-bit
None
None
JESD204B /
JESD204C
(17.16 Gbps)
Single 8 GSPS
Dual 4 GSPS
12-bit
Complex: 4x, 8x
Complex: 4x, 8x
Single 6.4 GSPS
Dual 3.2 GSPS
Real: 2x
Complex: 4x, 8x, 16x
JESD204B
(12.8 Gbps)
ADC12DJ3200
ADC08DJ3200
ADC12DJ2700
12-bit
8-bit
None
None
None
Single 6.4 GSPS
Dual 3.2 GSPS
JESD204B
(12.8 Gbps)
None
Single 5.4 GSPS
Dual 2.7 GSPS
Real: 2x
Complex: 4x, 8x, 16x
JESD204B
(12.8 Gbps)
12-bit
7.3.2 Analog Inputs
The analog inputs of the device have internal buffers to enable high input bandwidth and to isolate sampling
capacitor glitch noise from the input circuit. Analog inputs must be driven differentially because operation with a
single-ended signal results in degraded performance. Both AC-coupling and DC-coupling of the analog inputs is
supported. The analog inputs are designed for an input common-mode voltage (VCMI) of 0 V, which is terminated
internally through single-ended, 50-Ω resistors to ground (GND) on each input pin. DC-coupled input signals
must have a common-mode voltage that meets the device input common-mode requirements specified as VCMI
in the Recommended Operating Conditions table. The 0-V input common-mode voltage simplifies the interface
to split-supply, fully-differential amplifiers and to a variety of transformers and baluns. The device includes
internal analog input protection to protect the ADC inputs during overranged input conditions; see the Analog
Input Protection section. 图7-1 provides a simplified analog input model.
AGND
Analog Input
Protection
Diodes
50 ꢀ
INA+, INB+
ADC
INAœ, INBœ
Input Buffer
50 ꢀ
图7-1. ADC08DJ5200RF Analog Input Internal Termination and Protection Diagram
There is minimal degradation in analog input bandwidth when using single-channel mode versus dual-channel
mode. Either analog input (INA+ and INA– or INB+ and INB–) can be used in single-channel mode. The
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desired input can be chosen using SINGLE_INPUT in the input mux control register. A calibration needs to be
performed after switching the input mux for the changes to take effect. Further, two inputs can be used in single-
channel mode to drive the interleaved ADCs separately using the SINGLE_INPUT register setting. This mode is
called dual-input single-channel mode. Dual-input single-channel mode is equivalent to dual channel mode,
except ADC B samples out-of-phase with ADC A (single-channel mode sample timing). This mode is available
when a single-channel mode JMODE setting is chosen.
7.3.2.1 Analog Input Protection
The analog inputs are protected against overdrive conditions by internal clamping diodes that are capable of
sourcing or sinking input currents during overrange conditions, see the voltage and current limits in the Absolute
Maximum Ratings table. The overrange protection is also defined for a peak RF input power in the Absolute
Maximum Ratings table, which is frequency independent. Operation above the maximum conditions listed in the
Recommended Operating Conditions table results in an increase in failure-in-time (FIT) rate, so the system must
correct the overdrive condition as quickly as possible. 图7-1 shows the analog input protection diodes.
7.3.2.2 Full-Scale Voltage (VFS) Adjustment
Input full-scale voltage (VFS) adjustment is available, in fine increments, for each analog input through the
FS_RANGE_A register setting (see the INA full-scale range adjust register) and FS_RANGE_B register setting
(see the INB full-scale range adjust register) for INA± and INB±, respectively. The available adjustment range is
specified in the Electrical Characterization: DC Specifications table. Larger full-scale voltages improve SNR and
noise floor (in dBFS/Hz) performance, but can degrade harmonic distortion. The full-scale voltage adjustment is
useful for matching the full-scale range of multiple ADCs when developing a multi-converter system or for
external interleaving of multiple ADC08DJ5200RF's to achieve higher sampling rates.
7.3.2.3 Analog Input Offset Adjust
In foreground calibration mode, the input offset voltage for each input and for each ADC core can be adjusted
through SPI registers. The OADJ_A_FG0_VINx and OADJ_A_FG90_VINx registers (registers 0x344 to 0x34A)
are used to adjust ADC core A's offset voltage when sampling analog input x (where x is A for INA± or B for
INB±) where the FG0 register is used for dual channel mode and FG90 is used for single channel mode.
OADJ_B_FG0_VINx is used to adjust ADC core B's offset voltage when sampling input x. OADJ_B_FG0_VINx
applies to both single channel mode and dual channel mode. To adjust the offset voltage in dual channel mode
simply adjust the offset for the ADC core sampling the desired input. In single channel mode, both ADC core A's
offset and ADC core B's offset must be adjusted together. The difference in the two core's offsets in single
channel mode will result in a spur at fS/2 that is independent of the input. These registers can be used to
compensate the fS/2 spur in single channel mode. See the Calibration Modes and Trimming section for more
information.
7.3.3 ADC Core
The ADC08DJ5200RF consists of a total of six ADC cores. The cores are interleaved for higher sampling rates
and swapped on-the-fly for calibration as required by the operating mode. This section highlights the theory and
key features of the ADC cores.
7.3.3.1 ADC Theory of Operation
The differential voltages at the analog inputs are captured by the rising edge of CLK± in dual-channel mode or
by the rising and falling edges of CLK± in single-channel mode. After capturing the input signal, the ADC
converts the analog voltage to a digital value by comparing the voltage to the internal reference voltage. If the
voltage on INA– or INB– is higher than the voltage on INA+ or INB+, respectively, then the digital output is a
negative 2's complement value. If the voltage on INA+ or INB+ is higher than the voltage on INA– or INB–,
respectively, then the digital output is a positive 2's complement value. 方程式 1 can calculate the differential
voltage at the input pins from the digital output.
Code
N
VIN
where
=
VFS
(1)
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• Code is the signed decimal output code (for example, –2048 to +2047)
• N is the ADC resolution
• and VFS is the full-scale input voltage of the ADC as specified in the Recommended Operating Conditions
table, including any adjustment performed by programming FS_RANGE_A or FS_RANGE_B
7.3.3.2 ADC Core Calibration
ADC core calibration is required to optimize the analog performance of the ADC cores. Calibration must be
repeated when operating conditions change significantly, namely temperature, in order to maintain optimal
performance. The device has a built-in calibration routine that can be run as a foreground operation or a
background operation. Foreground operation requires ADC downtime, where the ADC is no longer sampling the
input signal, to complete the process. Background calibration can be used to overcome this limitation and allow
constant operation of the ADC. See the Calibration Modes and Trimming section for detailed information on each
mode.
7.3.3.3 Analog Reference Voltage
The reference voltage for the ADC08DJ5200RF is derived from an internal band-gap reference. A buffered
version of the reference voltage is available at the BG pin for user convenience. This output has an output-
current capability of ±100 µA. The BG output must be buffered if more current is required. No provision exists for
the use of an external reference voltage, but the full-scale input voltage can be adjusted through the full-scale-
range register settings.
7.3.3.4 ADC Overrange Detection
To make sure that system gain management has the quickest possible response time, a low-latency configurable
overrange function is included. The overrange function works by monitoring the converted samples at the ADC
to quickly detect if the ADC is near saturation or already in an overrange condition. The absolute value of the
ADC data are checked against two programmable thresholds, OVR_T0 and OVR_T1. These thresholds apply to
both channel A and channel B in dual-channel mode. 表 7-2 lists how an ADC sample is converted to an
absolute value for a comparison of the thresholds.
表7-2. Conversion of ADC Sample for Overrange Comparison
ADC SAMPLE
(Offset Binary)
ADC SAMPLE
(2's Complement)
ABSOLUTE VALUE
111 1111 (127)
1111 1111 (255)
1111 0000 (240)
1000 0000 (128)
0001 0000 (16)
0000 0000 (0)
0111 1111(+127)
0111 0000 (+112)
111 0000 (112)
0000 0000(0)
111 0000 (112)
111 1111 (127)
0000 0000 (0)
1000 0001 0000 (–112)
1000 0000 0000 (–128)
If the absolute value equal or exceed the OVR_T0 or OVR_T1 thresholds during the monitoring period, then the
overrange bit associated with the threshold is set to 1, otherwise the overrange bit is 0. In dual-channel mode,
the overrange status can be monitored on the ORA0 and ORA1 pins for channel A and the ORB0 and ORB1
pins for channel B, where ORx0 corresponds to the OVR_T0 threshold and ORx1 corresponds to the OVR_T1
threshold. In single-channel mode, the overrange status for the OVR_T0 threshold is determined by monitoring
both the ORA0 and ORB0 outputs and the OVR_T1 threshold is determined by monitoring both ORA1 and
ORB1 outputs. In single-channel mode, the two outputs for each threshold must be OR'd together to determine
whether an overrange condition occurred. OVR_N can be used to set the output pulse duration from the last
overrange event. 表7-3 lists the overrange pulse lengths for the various OVR_N settings.
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表7-3. Overrange Monitoring Period for the ORA0, ORA1, ORB0, and ORB1 Outputs
OVERRANGE PULSE LENGTH SINCE LAST OVERRANGE
EVENT (DEVCLK Cycles)
OVR_N
0
1
2
3
4
5
6
7
8
16
32
64
128
256
512
1024
Typically, the OVR_T0 threshold can be set near the full-scale value (228 for example). When the threshold is
triggered, a typical system can turn down the system gain to avoid clipping. The OVR_T1 threshold can be set
much lower. For example, the OVR_T1 threshold can be set to 64 (peak input voltage of −12 dBFS). If the input
signal is strong, the OVR_T1 threshold is tripped occasionally. If the input is quite weak, the threshold is never
tripped. The downstream logic device monitors the OVR_T1 bit. If OVR_T1 stays low for an extended period of
time, then the system gain can be increased until the threshold is occasionally tripped (meaning the peak level of
the signal is above −12 dBFS).
7.3.3.5 Code Error Rate (CER)
ADC cores can generate bit errors within a sample, often called code errors (CER) or referred to as sparkle
codes, resulting from metastability caused by non-ideal comparator limitations. The device uses a unique ADC
architecture that inherently allows significant code error rate improvements from traditional pipelined flash or
successive approximation register (SAR) ADCs. The code error rate of the device is multiple orders of
magnitude better than what can be achieved in alternative architectures at equivalent sampling rates providing
significant signal reliability improvements.
7.3.4 Temperature Monitoring Diode
A built-in thermal monitoring diode is made available on the TDIODE+ and TDIODE–pins. This diode facilitates
temperature monitoring and characterization of the device in higher ambient temperature environments.
Although the on-chip diode is not highly characterized, the diode can be used effectively by performing a
baseline measurement (offset) at a known ambient or board temperature and creating a linear equation with the
diode voltage slope provided in the Electrical Characteristics: DC Specifications table. Perform offset
measurement with the device unpowered or with the PD pin asserted to minimize device self-heating.
Recommended monitoring devices include the LM95233 device and similar remote-diode temperature
monitoring products from Texas Instruments.
7.3.5 Timestamp
The TMSTP+ and TMSTP– differential input can be used as a time-stamp input to mark a specific sample
based on the timing of an external trigger event relative to the sampled signal. TIMESTAMP_EN (see the LSB
control bit output register) must be set in order to use the timestamp feature and output the timestamp data.
When enabled, the LSB of the 8-bit output sample is used to output the timestamp status. The trigger must be
applied to the differential TMSTP+ and TMSTP– inputs. The trigger can be asynchronous to the ADC sampling
clock and is sampled at approximately the same time as the analog input.
7.3.6 Clocking
The clocking subsystem of the device has two input signals, device clock (CLK+, CLK–) and SYSREF
(SYSREF+, SYSREF–). Within the clocking subsystem there is a noiseless aperture delay adjustment (tAD
adjust), a clock duty cycle corrector and a SYSREF capture block. 图7-2 describes the clocking subsystem.
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Duty Cycle
Correction
tAD Adjust
Clock Distribution
CLK+
CLK-
and Synchronization
(ADC cores, digital,
JESD204C, etc.)
E
E
RS
A
IN
V
F
_
O
IN
C
_
D
_
D
A
T
D
A
A
T
T
SYSREF Capture
Automatic
SYSREF
Calibration
SYSREF+
SYSREF-
SYSREF Windowing
SYSREF_POS SYSREF_SEL
SRC_EN
图7-2. Clocking Subsystem
The device clock is used as the sampling clock for the ADC core as well as the clocking for the digital processing
and serializer outputs. Use a low-noise (low jitter) device clock to maintain high signal-to-noise ratio (SNR) within
the ADC. In dual-channel mode, the analog input signal for each input is sampled on the rising edge of the
device clock. In single-channel mode, both the rising and falling edges of the device clock are used to capture
the analog signal to reduce the maximum clock rate required by the ADC. A noiseless aperture delay adjustment
(tAD adjust) allows the user to shift the sampling instance of the ADC in fine steps in order to synchronize
multiple ADC08DJ5200RFs or to fine-tune system latency. Duty cycle correction is implemented in the device to
ease the requirements on the external device clock while maintaining high performance. 表 7-4 summarizes the
device clock interface in dual-channel mode and single-channel mode.
表7-4. Device Clock vs Mode of Operation
MODE OF OPERATION
Dual-channel mode
SAMPLING RATE VS fCLK
SAMPLING INSTANT
Rising edge
1 × fCLK
Single-channel mode
2 × fCLK
Rising and falling edge
SYSREF is a system timing reference used for JESD204C subclass-1 implementations of deterministic latency.
SYSREF is used to achieve deterministic latency and for multi-device synchronization. SYSREF must be
captured by the correct device clock edge in order to achieve repeatable latency and synchronization. The
ADC08DJ5200RF includes SYSREF windowing and automatic SYSREF calibration to ease the requirements on
the external clocking circuits and to simplify the synchronization process. SYSREF can be implemented as a
single pulse or as a periodic clock. In periodic implementations, SYSREF must be equal to, or an integer division
of, the local multiframe clock frequency in 8B/10B encoding modes or the local extended multiblock clock
frequency in 64B/66B encoding modes. 方程式 2 is used to calculate valid SYSREF frequencies in 8B/10B
encoding modes and 方程式3 in 64B/66B encoding modes.
R ì fCLK
fSYSREF
=
ì ì ì
(2)
(3)
Rì fCLK
66ì32ìEìn
fSYSREF
=
where
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• R and F are set by the JMODE setting (see )
• fCLK is the device clock frequency (CLK±)
• K is the programmed multiframe length (see for valid K settings)
• E is the number of multiblocks in an extended multiblock.
• n is any positive integer
7.3.6.1 Noiseless Aperture Delay Adjustment (tAD Adjust)
The device contains a delay adjustment on the device clock (sampling clock) input path, called tAD adjust, that
can be used to shift the sampling instance within the device in order to align sampling instances among multiple
devices or for external interleaving of multiple devices. Further, tAD adjust can be used for automatic SYSREF
calibration to simplify synchronization; see the Automatic SYSREF Calibration section. Aperture delay
adjustment is implemented in a way that adds no additional noise to the clock path; however, a slight
degradation in aperture jitter (tAJ) is possible at large values of TAD_COARSE because of internal clock path
attenuation. The degradation in aperture jitter can result in minor SNR degradations at high input frequencies
(see tAJ in the Switching Characteristics table). This feature is programmed using TAD_INV, TAD_COARSE, and
TAD_FINE in the DEVCLK timing adjust ramp control register. Setting TAD_INV inverts the input clock resulting
in a delay equal to half the clock period. 表7-5 summarizes the step sizes and ranges of the TAD_COARSE and
TAD_FINE variable analog delays. All three delay options are independent and can be used in conjunction. All
clocks within the device are shifted by the programmed tAD adjust amount, which results in a shift of the timing of
the JESD204C serialized outputs and affects the capture of SYSREF.
表7-5. tAD Adjust Adjustment Ranges
ADJUSTMENT PARAMETER
ADJUSTMENT STEP
DELAY SETTINGS
MAXIMUM DELAY
TAD_INV
1 / (fCLK × 2)
1
1 / (fCLK × 2)
See tTAD(STEP) in the Switching
Characteristics table
See tTAD(MAX) in the Switching
Characteristics table
TAD_COARSE
TAD_FINE
256
256
See tTAD(STEP) in the Switching
Characteristics table
See tTAD(MAX) in the Switching
Characteristics table
In order to maintain timing alignment between converters, stable and matched power-supply voltages and device
temperatures must be provided.
Aperture delay adjustment can be changed on-the-fly during normal operation but may result in brief upsets to
the JESD204C data link. Use TAD_RAMP to reduce the probability of the JESD204C link losing synchronization;
see the Aperture Delay Ramp Control section.
7.3.6.2 Aperture Delay Ramp Control (TAD_RAMP)
The ADC08DJ5200RF contains a function to gradually adjust the tAD adjust setting towards the newly written
TAD_COARSE value. This functionality allows the tAD adjust setting to be adjusted with minimal internal clock
circuitry glitches. The TAD_RAMP_RATE parameter allows either a slower (one TAD_COARSE LSB per 384
tCLK cycles) or faster ramp (four TAD_COARSE LSBs per 384 tCLK cycles) to be selected. The TAD_RAMP_EN
parameter enables the ramp feature and any subsequent writes to TAD_COARSE initiate a new cramp.
7.3.6.3 SYSREF Capture for Multi-Device Synchronization and Deterministic Latency
The clocking subsystem is largely responsible for achieving multi-device synchronization and deterministic
latency. The ADC08DJ5200RF uses the JESD204C subclass-1 method to achieve deterministic latency and
synchronization. Subclass 1 requires that the SYSREF signal be captured by a deterministic device clock (CLK±)
edge at each system power-on and at each device in the system. This requirement imposes setup and hold
constraints on SYSREF relative to CLK±, which can be difficult to meet at giga-sample clock rates over all
system operating conditions. The device includes a number of features to simplify this synchronization process
and to relax system timing constraints:
• The device uses dual-edge sampling (DES) in single-channel mode to reduce the CLK± input frequency by
half and double the timing window for SYSREF (see 表7-4)
• A SYSREF position detector (relative to CLK±) and selectable SYSREF sampling position aid the user in
meeting setup and hold times over all conditions; see the SYSREF Position Detector section
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• Easy-to-use automatic SYSREF calibration uses the aperture timing adjust block (tAD adjust) to shift the ADC
sampling instance based on the phase of SYSREF (rather than adjusting SYSREF based on the phase of the
ADC sampling instance); see the Automatic SYSREF Calibration section
7.3.6.3.1 SYSREF Position Detector and Sampling Position Selection (SYSREF Windowing)
The SYSREF windowing block is used to first detect the position of SYSREF relative to the CLK± rising edge
and then to select a desired SYSREF sampling instance, which is a delay version of CLK±, to maximize setup
and hold timing margins. In many cases a single SYSREF sampling position (SYSREF_SEL) is sufficient to meet
timing for all systems (device-to-device variation) and conditions (temperature and voltage variations). However,
this feature can also be used by the system to expand the timing window by tracking the movement of SYSREF
as operating conditions change or to remove system-to-system variation at production test by finding a unique
optimal value at nominal conditions for each system.
This section describes proper usage of the SYSREF windowing block. First, apply the device clock and SYSREF
to the device. The location of SYSREF relative to the device clock cycle is determined and stored in the
SYSREF_POS bits of the SYSREF capture position register. ADC08DJ5200RF must see at least 3 rising edges
of SYSREF before the SYSREF_POS output is valid. Each bit of SYSREF_POS represents a potential SYSREF
sampling position. If a bit in SYSREF_POS is set to 1, then the corresponding SYSREF sampling position has a
potential setup or hold violation. Upon determining the valid SYSREF sampling positions (the positions of
SYSREF_POS that are set to 0) the desired sampling position can be chosen by setting SYSREF_SEL in the
clock control register 0 to the value corresponding to that SYSREF_POS position. In general, the middle
sampling position between two setup and hold instances is chosen. Ideally, SYSREF_POS and SYSREF_SEL
are performed at the nominal operating conditions of the system (temperature and supply voltage) to provide
maximum margin for operating condition variations. This process can be performed at final test and the optimal
SYSREF_SEL setting can be stored for use at every system power up. Further, SYSREF_POS can be used to
characterize the skew between CLK± and SYSREF± over operating conditions for a system by sweeping the
system temperature and supply voltages. For systems that have large variations in CLK± to SYSREF± skew, this
characterization can be used to track the optimal SYSREF sampling position as system operating conditions
change. In general, a single value can be found that meets timing over all conditions for well-matched systems,
such as those where CLK± and SYSREF± come from a single clocking device.
备注
SYSREF_SEL must be set to 0 when using automatic SYSREF calibration; see the Automatic
SYSREF Calibration section.
The step size between each SYSREF_POS sampling position can be adjusted using SYSREF_ZOOM. When
SYSREF_ZOOM is set to 0, the delay steps are coarser. When SYSREF_ZOOM is set to 1, the delay steps are
finer. See the Switching Characteristiccs table for delay step sizes when SYSREF_ZOOM is enabled and
disabled. In general, SYSREF_ZOOM = 1 is recommended to be used above fCLK = 3GHz and SYSREF_ZOOM
= 0 below fCLK = 3GHz. Bits 0 and 23 of SYSREF_POS are always be set to 1 because there is insufficient
information to determine if these settings are close to a timing violation, although the actual valid window can
extend beyond these sampling positions. The value programmed into SYSREF_SEL is the decimal number
representing the desired bit location in SYSREF_POS. 表 7-6 lists some example SYSREF_POS readings and
the optimal SYSREF_SEL settings. Although 24 sampling positions are provided by the SYSREF_POS status
register, SYSREF_SEL only allows selection of the first 16 sampling positions, corresponding to SYSREF_POS
bits 0 to 15. The additional SYSREF_POS status bits are intended only to provide additional knowledge of the
SYSREF valid window. In general, lower values of SYSREF_SEL are selected because of delay variation over
supply voltage, however in the fourth example a value of 15 provides additional margin and can be selected
instead.
表7-6. Examples of SYSREF_POS Readings and SYSREF_SEL Selections
SYSREF_POS[23:0]
OPTIMAL SYSREF_SEL
0x02E[7:0]
(Largest Delay)
0x02C[7:0](1)
(Smallest Delay)
0x02D[7:0](1)
SETTING
b10000000
b0110000 0
b00011001
8 or 9
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表7-6. Examples of SYSREF_POS Readings and SYSREF_SEL Selections (continued)
SYSREF_POS[23:0]
OPTIMAL SYSREF_SEL
SETTING
0x02E[7:0]
(Largest Delay)
0x02C[7:0](1)
(Smallest Delay)
0x02D[7:0](1)
b10011000
b10000000
b10000000
b10001100
b00000000
b01100000
b00000011
b01100011
b00110001
b0 0000001
b00000001
b00011001
12
6 or 7
4 or 15
6
(1) Red coloration indicates the bits that are selected, as given in the last column of this table.
7.3.6.3.2 Automatic SYSREF Calibration
The ADC08DJ5200RF has an automatic SYSREF calibration feature to alleviate the often challenging setup and
hold times associated with capturing SYSREF for giga-sample data converters. Automatic SYSREF calibration
uses the tAD adjust feature to shift the device clock to maximize the SYSREF setup and hold times or to align the
sampling instance based on the SYSREF rising edge.
The device must have a proper device clock applied and be programmed for normal operation before starting the
automatic SYSREF calibration. When ready to initiate automatic SYSREF calibration, a continuous SYSREF
signal must be applied. SYSREF must be a continuous (periodic) signal when using the automatic SYSREF
calibration. Start the calibration process by setting SRC_EN high in the SYSREF calibration enable register after
configuring the automatic SYSREF calibration using the SRC_CFG register. Upon setting SRC_EN high, the
device searches for the optimal tAD adjust setting until the device clock falling edge is internally aligned to the
SYSREF rising edge. TAD_DONE in the SYSREF calibration status register can be monitored tomake sure the
SYSREF calibration has finished. By aligning the device clock falling edge with the SYSREF rising edge,
automatic SYSREF calibration maximizes the internal SYSREF setup and hold times relative to the device clock
and also sets the sampling instant based on the SYSREF rising edge. After the automatic SYSREF calibration
finishes, the rest of the startup procedure can be performed to finish bringing up the system.
For multi-device synchronization, the SYSREF rising edge timing must be matched at all devices and therefore
trace lengths must be matched from a common SYSREF source to each device. Any skew between the
SYSREF rising edge at each device results in additional error in the sampling instance between devices,
however repeatable deterministic latency from system startup to startup through each device must still be
achieved. No other design requirements are needed in order to achieve multi-device synchronization as long as
a proper elastic buffer release point is chosen in the JESD204C receiver.
图 7-3 provides a timing diagram of the SYSREF calibration procedure. The optimized setup and hold times are
shown as tSU(OPT) and tH(OPT), respectively. Device clock and SYSREF are referred to as internal in this diagram
because the phase of the internal signals are aligned within the device and not to the external (applied) phase of
the device clock or SYSREF.
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Sampled Input Signal
Internal Unadjusted
Device Clock
Internal Calibrated
Device Clock
tTAD(SRC)
Internal SYSREF
tCAL(SRC)
tH(OPT)
tSU(OPT)
Before calibration, device clock falling edge does
not align with SYSREF rising edge
SRC_EN
(SPI register bit)
Calibration
enabled
After calibration, device clock falling edge
aligns with SYSREF rising edge
TAD_DONE
(SPI register bit)
Calibration
finished
图7-3. SYSREF Calibration Timing Diagram
When finished, the tAD adjust setting found by the automatic SYSREF calibration can be read from SRC_TAD in
the SYSREF calibration status register. After calibration, the system continues to use the calibrated tAD adjust
setting for operation until the system is powered down. However, if desired, the user can then disable the
SYSREF calibration and fine-tune the tAD adjust setting according to the systems needs. Alternatively, the use of
the automatic SYSREF calibration can be done at product test (or periodic recalibration) of the optimal tAD adjust
setting for each system. This value can be stored and written to the TAD register (TAD_INV, TAD_COARSE, and
TAD_FINE) upon system startup.
Do not run the SYSREF calibration when the ADC calibration (foreground or background) is running. If
background calibration is the desired use case, disable the background calibration when the SYSREF calibration
is used, then reenable the background calibration after TAD_DONE goes high. SYSREF_SEL in the clock
control register 0 must be set to 0 when using SYSREF calibration.
SYSREF calibration searches the TAD_COARSE delays using both noninverted (TAD_INV = 0) and inverted
clock polarity (TAD_INV = 1) to minimize the required TAD_COARSE setting in order to minimize loss on the
clock path to reduce aperture jitter (tAJ).
7.3.7 Programmable FIR Filter (PFIR)
The output of the ADCs can be sent through programmable finite-impulse-response (PFIR) digital filter for
equalization of the frequency response. The filter can be setup in a few modes of operation to allow independent
equalization of each channel in dual channel mode, equalization in single channel mode or as a time-varying
filter in dual channel mode (such as for I/Q correction). The various PFIR operating modes are given in 表7-7.
表7-7. PFIR Operating Modes
Center Tap
Resolution
Center Tap LSB
Weight
Non-Center Tap
Resolution
Non-Center Tap LSB
Weight
PFIR Mode
Filter Coefficients
Dual Channel
Equalization
18 bits
18 bits
2-16
2-16
12 bits
12 bits
2-10, 2-11...2-16
2-10, 2-11...2-16
9 per channel
9
Single Channel
Equalization
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表7-7. PFIR Operating Modes (continued)
Center Tap
Resolution
Center Tap LSB
Weight
Non-Center Tap
Resolution
Non-Center Tap LSB
Weight
PFIR Mode
Filter Coefficients
9 per coefficient set, 2
coefficient sets
Time Varying Filter
18 bits
2-16
12 bits
2-10, 2-11...2-16
Programming information for the various PFIR modes is given in 表 7-8. The coefficients are programmed into
the PFIR_Ax and PFIR_Bx registers.
表7-8. Programmable FIR Filter Mode Programming
PFIR Mode
PFIR Disabled
PFIR_MODE
PFIR_SHARE
PFIR_MERGE
0
2
2
2
X
0
1
0
X
0
1
1
Dual Channel Equalization
Single Channel Equalization
Time Varying Filter
7.3.7.1 Dual Channel Equalization
When the ADC is operating in dual channel mode (based on the JMODE setting) then the PFIR filter can be set
in dual channel equalization mode. This mode allows independent frequency equalization of the two ADC
channels. The filter for each channel consists of 9 coefficients that can be independently set. The center tap for
each filter has a resolution of 18 bits and the LSB has a weight of 2-16. The non-center taps have a resolution of
12-bits with programmable LSB weight of 2-10, 2-11, 2-12, 2-13, 2-14, 2-15 or 2-16. All non-center taps have the
same LSB weight. The block diagram for dual channel equalization is shown in 图7-4.
图7-4. Dual Channel Equalization PFIR Block Diagram
7.3.7.2 Single Channel Equalization
When the ADC is operating in single channel mode (based on the JMODE setting) then the PFIR filter can be set
in single channel equalization mode. This mode allows frequency equalization of the ADC. The filter consists of 9
coefficients that can be independently set. The center tap of the filter has a resolution of 18 bits and the LSB has
a weight of 2-16. The non-center taps have a resolution of 12-bits with programmable LSB weight of 2-10, 2-11
,
2-12, 2-13, 2-14, 2-15 or 2-16. All non-center taps have the same LSB weight. The block diagram for single channel
equalization is shown in 图7-5.
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图7-5. Single Channel Equalization PFIR Block Diagram
7.3.7.3 Time Varying Filter
When the ADC is operating in dual-input single channel mode (based on the JMODE setting and
SINGLE_INPUT setting) then the PFIR filter can be set in time varying filter mode. This mode enables a time
varying filter with two coefficient sets that are alternated between on a per sample basis. Each coefficient set
consists of 9 coefficients that can be independently set. The center tap of the filter has a resolution of 18 bits and
the LSB has a weight of 2-16. The non-center taps have a resolution of 12-bits with programmable LSB weight of
2-10, 2-11, 2-12, 2-13, 2-14, 2-15 or 2-16. All non-center taps have the same LSB weight. The block diagram for time
varying filter mode is shown in 图 7-6 and an alternate block diagram is given in 图 7-7 which shows the
equivalent filter in an I/Q correction-type topology.
图7-6. Time Varying Filter PFIR Block Diagram
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图7-7. Alternate I/Q Correction-Type Filter Block Diagram
7.3.8 JESD204C Interface
The ADC08DJ5200RF uses a JESD204C high-speed serial interface for data converters to transfer data from
the ADC to the receiving logic device. Many of the available JESD204C output formats are backwards
compatible with existing JESD204B receivers, including many of the JESD204B modes in the ADC12DJ2700
and ADC12DJ3200. The device serialized lanes are capable of operating with both 8B/10B encoding and
64B/66B encoding. A maximum of 16 lanes can be used to lower lane rates for interfacing with speed-limited
logic devices. There are a few differences between 8B/10B and 64B/66B encoded JESD204C, which will be
described throughout this section. 图 7-8 shows a simplified block diagram of the 8B/10B encoded JESD204C
interface and 图7-9 shows a simplified block diagram of the 64B/66B encoded JESD204C interface.
ADC
JESD204C Block
TRANSPORT
LAYER
SCRAMBLER
(Optional)
8B/10B
LINK LAYER
SERDES
TX PHY
ADC
ANALOG
CHANNEL
Logic Device
JESD204B or JESD204C Block
APPLICATION
LAYER
TRANSPORT
LAYER
DESCRAMBLE
(Optional)
8B/10B
LINK LAYER
SERDES
RX PHY
Copyright © 2018, Texas Instruments Incorporated
图7-8. Simplified 8B/10B Encoded JESD204C Interface Diagram
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ADC
JESD204C Block
TRANSPORT
LAYER
SCRAMBLER
(Required)
64B/66B
LINK LAYER
SERDES
TX PHY
ADC
ANALOG
CHANNEL
Logic Device
JESD204C Block
APPLICATION
LAYER
TRANSPORT
LAYER
DESCRAMBLE
(Required)
64B/66B
LINK LAYER
SERDES
RX PHY
Copyright © 2018, Texas Instruments Incorporated
图7-9. Simplified 64B/66B Encoded JESD204C Interface Diagram
The various signals used in the JESD204C interface and the associated the device pin names are summarized
briefly in 表 7-9 for reference. Most of the signals are common between 8B/10B and 64B/66B encoded
JESD204C, except for SYNC which is not needed to achieve block synchronization for 64B/66B encoding. The
sync header encoded into the data stream is used for block synchronization instead of the SYNC signal.
表7-9. Summary of JESD204C Signals
SIGNAL NAME
PIN NAMES
8B/10B
64B/66B
DESCRIPTION
High-speed serialized data
after 8B/10B or 64B/66B
encoding
Data
Yes
Yes
DA[7:0]+, DA[7:0]–, DB[7:0]+, DB[7:0]–)
Link initialization signal
(handshake), toggles low to
start code group
synchronization (CGS)
process. Not used for
64B/66B encoding modes,
unless it is used for NCO
synchronization purposes.
SYNC
Yes
No
SYNCSE, TMSTP+, TMSTP–
ADC sampling clock, also
used for clocking digital logic
and output serializers
Device clock
SYSREF
Yes
Yes
Yes
Yes
CLK+, CLK–
System timing reference used
to deterministically reset the
internal local multiframe clock
(LMFC) or local extended
multiblock clock (LEMC)
counters in each JESD204C
device
SYSREF+, SYSREF–
Not all optional features of JESD204C are supported by the device. The list of features that are supported and
the features that are not supported is provided in 表7-10.
表7-10. Declaration of Supported JESD204C Features
REFERENCE
LETTER IDENTIFIER
FEATURE
SUPPORT IN ADC08DJ5200RF
CLAUSE
clause 8
clause 7
clause 7
a
b
c
8B/10B link layer
64B/66B link layer
64B/80B link layer
Supported
Supported
Not supported
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表7-10. Declaration of Supported JESD204C Features (continued)
REFERENCE
CLAUSE
LETTER IDENTIFIER
FEATURE
SUPPORT IN ADC08DJ5200RF
The command channel when using the
64B/66B or 64B/80B link layer
d
e
f
clause 7
clause 7
Not supported
Forward error correction (FEC) when using
the 64B/66B or 64B/80B link layer
Supported
CRC3 when using the 64B/66B or 64B/80B
link layer
clause 7
Not supported
A physical SYNC pin when using the 8B/10B
link layer
g
h
clause 8
Supported
Not supported, but subclass 1 transmitter is
compatible with subclass 0 receiver
clause 7, clause 8
Subclass 0
i
j
clause 7, clause 8
clause 8
Subclass 1
Subclass 2
Supported
Not supported
Supported
k
clause 7, clause 8
Lane alignment within a single link
Subclass 1 with support for a lane alignment
on a multipoint link by means of the
MULTIREF signal
l
clause 7, clause 8
Not supported
SYNC interface timing is compatible with
JESD204A
m
n
clause 8
clause 8
Supported
Supported
SYNC interface timing is compatible with
JESD204B
7.3.8.1 Transport Layer
The transport layer takes samples from the ADC output and maps the samples into octets inside of frames. The
transport layer is common to both 8B/10B and 64B/66B encoding modes. These frames are then mapped onto
the available lanes. The mapping of octets into frames and frames onto lanes is defined by the transport layer
settings such as L, M, F, S, N and N'. An octet is 8 bits (before 8B/10B or 64B/66B encoding), a frame consists
of F octets and the frames are mapped onto L lanes. Samples are N bits, but sent as N' bits across the link. The
samples come from M converters and there are S samples per converter per frame cycle. M is sometimes
artificially increased in order to obtain a more desirable mapping, for instance lower latency may be achieved
with a larger M value for long frames.
There are a number of predefined transport layer modes in the device that are defined in . The high level
configuration parameters for the transport layer in the device are described in 表 7-14. The transport layer mode
is chosen by simply setting the JMODE register setting. For reference, the various configuration parameters for
JESD204C are defined in 表7-15.
The link layer further maps the frames into multiframes when using 8B/10B encoding or blocks, multiblocks and
extended multiblocks when using 64B/66B encoding.
7.3.8.2 Scrambler
A data scrambler is available to scramble the data before transmission across the channel. Scrambling is used
to remove the possibility of spectral peaks in the transmitted data due to repetitive data streams. The scrambler
is optional for 8B/10B encoded modes, however it is mandatory for 64B/66B encoded modes in order to have
sufficient spectral content for clock recovery and adaptive equalization and to maintain DC balance to allow AC
coupling of the transmitter to the receiver. The scrambler operates on the data before encoding, such that the
8B/10B scrambler scrambles the 8-bit octets before 10-bit encoding and the 64B/66B scrambler scrambles the
64-bit block before the sync header insertion (66-bit encoding). The JESD204C receiver automatically
synchronizes its descrambler to the incoming scrambled data stream. For 8B/10B encoding, the initial lane
alignment sequence (ILA) is never scrambled. Scrambling can be enabled by setting SCR (in the JESD204C
control register) for 8B/10B encoding modes, but it is automatically enabled in 64B/66B modes. The scrambling
polynomial is different for 8B/10B encoding and 64B/66B encoding schemes as defined by the JESD204C
standard.
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7.3.8.3 Link Layer
The link layer serves multiple purposes in JESD204C for both 8B/10B and 64B/66B encoding schemes, however
there are some differences in implementation for each encoding scheme. In general, the link layer's
responsibilities include scrambling of the data (see Scrambler), establishing the code (8B/10B) or block (64B/
66B) boundaries and the multiframe (8B/10B) or multiblock (64B/66B) boundaries, initializing the link, encoding
the data, and monitoring the health of the link. This section is split into an 8B/10B section (8B/10B Link Layer)
and a 64B/66B section (64B/66B Link Layer) in order to cover the specific implementation for each encoding
scheme.
7.3.8.4 8B/10B Link Layer
This section covers the link layer for the 8B/10B encoding operating modes including initialization of the
character, frame and multiframe boundaries, alignment of the lanes, 8B/10B encoding and monitoring of the
frame and multiframe alignment during operation.
7.3.8.4.1 Data Encoding (8B/10B)
The data link layer converts the 8-bit octets from the transport layer into 10-bit characters for transmission across
the link using 8B/10B encoding. 8B/10B encoding specifies DC balance to allow use of AC-coupling between the
SerDes transmitter and receiver, and maintains a sufficient number of edge transitions for the receiver to reliably
recover the data clock. 8B/10B encoding also provides some error detection since a single bit error in a
character likely results in either not being able to find the 10-bit character in the 8B/10B decoder lookup table or
an incorrect character disparity.
7.3.8.4.2 Multiframes and the Local Multiframe Clock (LMFC)
The frames from the transport layer are combined into multiframes which are used in the process of achieving
deterministic latency in subclass 1 implementations. The length of a multiframe is set by the K parameter which
defines the number of frames in a multiframe. JESD204C increases the maximum allowed number of frames per
multiframe (K) from 32 in JESD204B to 256 in JESD204C to allow a longer multi-frame to ease deterministic
latency requirements. The total allowed range of K is defined by the inequality ceil(17/F) ≤ K ≤ min(256,
floor(1024/F)) where ceil() and floor() are the ceiling and floor function, respectively. The local multiframe clock
(LMFC) keeps track of the start and end of a multiframe for deterministic latency and data synchronization
purposes. The LMFC is reset by the SYSREF signal to a deterministic phase in both the transmitter and receiver
in order to act as a timing reference for deterministic latency. The LMFC clock frequency is given in 方程式 4
where fBIT is the serialized bit rate (line rate) of the SerDes interface and F and K are as defined above. The
frequency of SYSREF must equal to or an integer division of fLMFC when using 8B/10B encoding modes if
SYSREF is a continuous signal.
fLMFC = fBIT / (10 × F × K)
(4)
7.3.8.4.3 Code Group Synchronization (CGS)
The first step in initializing the JESD204C link, after the LMFC is deterministically reset by SYSREF, is for the
receiver to find the boundaries of the encoded 10-bit characters sent across each SerDes lane. This process is
called code group synchronization (CGS). The receiver first asserts the SYNC signal (set to logic '0') when ready
to initialize the link. The transmitter responds to the request by sending a stream of K28.5 comma characters.
The receiver aligns its character clock to the K28.5 character sequence and CGS is achieved after successfully
receiving four consecutive K28.5 characters. The receiver deasserts SYNC (set to logic '1') on the next LMFC
edge after CGS is achieved and waits for the transmitter to start the initial lane alignment sequence (ILAS).
7.3.8.4.4 Initial Lane Alignment Sequence (ILAS)
After the transmitter detects the SYNC signal deassert (logic '0' to logic '1' transition), the transmitter waits until
its next LMFC edge to start sending the initial lane alignment sequence (ILAS). The ILAS consists of four
multiframes each containing a predetermined sequence. The receiver searches for the start of the ILAS to
determine the frame and multiframe boundaries. Each multiframe of the ILAS starts with a /R/ character (K28.0)
and ends with a /A/ character (K28.3) and either can be used to detect the boundary of a multiframe. Each lane
starts buffering its data in the elastic buffer once the ILAS reaches the receiver, starting with the /R/ character,
until all receivers have received the ILAS and subsequently release the ILAS from all lanes at the same time in
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order to align the lanes. The elastic buffer release point is chosen to avoid ambiguity in the release of the data
caused by variation in the data delay (arrival of the ILAS at the receiver for each lane). The second multiframe of
the ILAS contains configuration parameters for the JESD204C link configuration that can be used by the receiver
to verify that the transmitter and receiver configurations match.
7.3.8.4.5 Frame and Multiframe Monitoring
The ADC08DJ5200RF supports frame and multiframe monitoring for verifying the health of the JESD204C link
when using 8B/10B encoding. The scheme changes depending on the use of scrambling. The implementation
when scrambling is disabled is covered first. If the last octet of the current frame matches the last octet of the
previous frame, then the last octet of the current frame is encoded as an /F/ (K28.7) character. If the current
frame is also the last frame of a multiframe, then an /A/ (K28.3) character is used instead. Neither an /F/ or /A/
character should occur in a normal data stream, except when replaced by the transmitter for alignment
monitoring. When the receiver detects an /F/ or /A/ character in the normal data stream the receiver checks to
see if the character occurs at the location expected to be the end of a frame or multiframe. If the character
occurs at a location other than the end of a frame or multiframe then either the transmitter or receiver has
become misaligned. The receiver replaces the alignment character with the appropriate data character upon
reception of a properly aligned /F/ or /A/ character. The appropriate data character is the last octet of the
previously received frame. This scheme increases the probability of an alignment character for non-scrambled
data streams.
The implementation when scrambling is enabled is slightly different since the octets will be randomized. If the
last octet of a frame is 0xFC (before 8B/10B encoding) then the transmitter encodes the octet as an /F/ (/K28.7/)
character. If the last octet of a multiframe is 0x7C (before 8B/10B encoding) then the transmitter encodes the
octet as an /A/ (/K28.3/) character. The location of the /A/ and /F/ characters is monitored to verify proper frame
and multiframe alignment. The receiver replaces the alignment characters by simply replacing an /F/ character
with the 0xFC octet and an /A/ character with the 0x7C octet.
The receiver can report an error if multiple alignment characters occur in the incorrect location or do not occur
when expected. Upon detection of a frame or multiframe misalignment, the receiver should trigger a link
realignment by asserting SYNC. SYSREF should also be reissued to verify that the LMFC in the transmitter and
receiver have proper alignment before restarting the link.
7.3.8.5 64B/66B Link Layer
This section covers the link layer for the 64B/66B encoding operating modes which includes scrambling of the
data, addition of the sync headers (64B/66B encoding), the structure of the block and multiblock, the sync
header, cyclic redundancy checking (CRC), forward error correction (FEC) and link alignment.
7.3.8.5.1 64B/66B Encoding
The frames formed by the transport layer are packed into 8-octet long blocks (64 bits). This 64-bit block is
scrambled and then a 2-bit sync header (SH) is appended to form a 66-bit transmission block. The sync header
is used for block synchronization by marking the end of a block as well as allowing for cyclic redundancy
checking (CRC), forward error correction (FEC) or a command channel. The structure of a block is given in 表
7-11 where SH represents the appended 2-bit sync header.
表7-11. Structure of 64B/66B Block with Sync Header
SH
OCTET0
OCTET1
OCTET2
OCTET3
OCTET4
OCTET5
OCTET6
OCTET7
[0:1]
[2:9]
[10:17]
[18:25]
[26:33]
[34:41]
[42:49]
[50:57]
[58:65]
7.3.8.5.2 Multiblocks, Extended Multiblocks and the Local Extended Multiblock Clock (LEMC)
A multiblock is a 32 block container which consists of a concatenation of 32 blocks. An extended multiblock is a
concatenation of multiple multiblocks, where E defines the number of multiblocks in an extended multiblock. A
frame can be split between blocks and multiblocks, but there must be an integer number of frames in an
extended multiblock. An extended multiblock is only necessary when a multiblock does not have an integer
number of frames. If an extended multiblock is not used, because a multiblock contains an integer number of
frames, then the E parameter is equal to 1 to indicate that there is one multiblock in an extended multiblock.
Values of E greater than 1 are not supported in ADC08DJ5200RF.
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An extended multiblock is analogous to a multiframe in the 8B/10B transport layer. The local extended mutiblock
clock (LEMC) keeps track of the start and end of a multiblock for deterministic latency and data synchronization
purposes in the same way the LMFC tracks the start and end of a multiframe in 8B/10B encoding. The LEMC is
reset by the SYSREF signal to a deterministic phase in both the transmitter and receiver in order to act as a
timing reference for deterministic latency. The LEMC clock frequency is defined by 方程式 5 where fBIT is the
serialized bit rate (line rate) of the SerDes interface. The frequency of SYSREF must equal to or an integer
division of fLMFC when using 64B/66B encoding modes if SYSREF is a continuous signal.
fLEMC = fBIT / (66 × 32 × E)
(5)
7.3.8.5.3 Block, Multiblock and Extended Multiblock Alignment using Sync Header
The sync header contains two bits that are always opposite of each other (either 01 or 10). The JESD204C
receiver can find the block boundaries by looking for a 66-bit boundary that always contains a 0 to 1 or 1 to 0
transition. Although 0 to 1 and 1 to 0 transitions will occur at other locations in a block, it is impossible for the
sequence to appear at a fixed location, other than the proper sync header location, in successive blocks for a
long period of time. The sync header indicates the start of a block and can be used for block alignment
monitoring. If a 00 or a 11 bit sequence is seen at the assumed sync header location of a block, then block
alignment may have been lost. Multiple occurrences of incorrect sync header bits should trigger a search for the
sync header after sending SYSREF to all devices to reset LEMC alignment.
A sync header ([0:1]) of 01 corresponds to transmission of a 1 while a sync header of 10 corresponds to a
transmission of a 0. The transmitted bit from the sync header of each block of a multiblock are combined into a
32-bit word called the sync header stream. The sync header stream is used to transmit data in parallel with the
user data in order to synchronize the link by marking the borders of multiblocks and extended multiblocks. In
addition, the sync header stream provides one of either CRC, FEC or a command channel. The device supports
CRC-12 and FEC and does not support CRC-3 or the command channel.
The 32-bit sync header stream always ends with a 00001 bit sequence, called the end-of-multiblock (EoMB)
signal, that indicates the end of a multiblock. For CRC and command channel modes, a 00001 sequence will
never occur in any other location in the sync header stream. For FEC mode, it is possible for a 00001 sequence
to appear in another location within the sync header stream, however it is improbable to see the 00001
sequence in the same location within a sequence of multiple multiblocks. Therefore, in FEC mode it may take
more than one multiblock to find the end of a multiblock. The end of an extended multiblock is found for all
modes by monitoring bit 22 of the sync header stream, the EoEMB bit, which indicates the end of an extended
multiblock when set to a 1. The EoMB (00001) and EoEMB signals, as well as fixed 1s in the sync header
stream for CRC and command channel modes, form the pilot signal of the sync header stream.
The defined format for each form of the sync header stream are defined in the following sections.
7.3.8.5.3.1 Cyclic Redundancy Check (CRC) Mode
The cyclic redundancy check (CRC) mode is available to allow detection of potential bit errors during
transmission. Support for the 12-bit word CRC-12 mode is required by JESD204C, while a 3-bit word CRC-3
mode is optional. The device does not support the CRC-3 mode and therefore this section is specific to the
CRC-12 mode only. The transmitter computes the CRC-12 parity bits from the scrambled data bits of the 32
blocks of a multiblock. The 12-bit CRC parity word is then transmitted in the sync header stream of the next
multiblock. The receiver computes the 12-bit parity word of the received multiblock and compares it against the
received 12-bit parity word of the next multiblock. A difference indicates that there is at least one error in the
received data bits or in the received 12-bit parity word. The minimum latency to the detection of a bit error in the
first data bit of a multiblock is 46 blocks.
The mapping of the sync header stream when using the CRC-12 mode is shown in 表7-12. CRC[x] corresponds
to bit x of the 12-bit CRC word. Cmd[x] corresponds to bit x of the 7 bit command word, which are always set to
0's in the device. The 00001 bit sequence at the end of the sync header stream is the pilot signal that is used to
identify the end of a multiblock. The 1s that occur throughout the sync header makes suer the pilot signal is only
seen at the end of the sync header, allowing multiblock alignment after only a single multiblock has been
received. EoEMB is the end-of-extended-multiblock bit, which is set to 1 for the last multiblock of an extended
multiblock.
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表7-12. Sync Header Stream Bit Mapping for CRC-12 Mode
Bit
0
Function
CRC[11]
CRC[10]
CRC[9]
1
Bit
Function
CRC[5]
CRC[4]
CRC[3]
1
Bit
16
17
18
19
20
21
22
23
Function
Cmd[6]
Cmd[5]
Cmd[4]
1
Bit
24
25
26
27
28
29
30
31
Function
8
Cmd[2]
1
9
Cmd[1]
2
10
11
12
13
14
15
Cmd[0]
3
0
0
0
0
1
4
CRC[8]
CRC[7]
CRC[6]
1
CRC[2]
CRC[1]
CRC[0]
1
Cmd[3]
1
5
6
EoEMB
1
7
The CRC-12 encoder takes in a multiblock of 32 scrambled blocks (2048 bits) and computes the 12-bit parity
word using the generator polynomial given by 方程式 6. The polynomial is sufficient to detect all 2-bit errors in a
multiblock, spanning any distance, and burst error sequences of up to 12-bits in length. The probability of not
detecting a 3-bit error spanning any distance in a multiblock is approximately 0.004%.
0x987 == x12+x9+x8+x3+x2+x+1
(6)
The full parity bit generation for CRC-12 is shown in 图 7-10. The input is a 2048 bit sequence, built from the 32
scrambled blocks of a multiblock (sync header is not included). The 12-bit parity word, CRC[11:0], is taken from
the Sx blocks after the full 2048 bit sequence is processed. The Sx blocks are initialized with 0's before
processing each multiblock. For more information on the CRC-12 parity word generation, refer to the JESD204C
standard.
32-block input
(2048 bits)
1
x
x2
x3
x8
x9
x12
S11
S0
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
CRC[0]
CRC[1]
CRC[2]
CRC[3] CRC[4] CRC[5] CRC[6] CRC[7]
CRC[8]
CRC[9] CRC[10] CRC[11]
图7-10. CRC-12 Parity Bit Generator
7.3.8.5.3.2 Forward Error Correction (FEC) Mode
Forward error correction (FEC) is an optional feature in JESD204C and is supported by the device. Whereas
CRC-12 mode can only detect errors on the link, FEC is able to detect and correct errors in order to improve the
bit error rate (BER) for error-sensitive applications. Many applications can tolerate random bit errors, however
some applications, such as an oscilloscope, rely on long error-free measurements in order to detect a certain
response from the device under test (DUT). An error in these applications may result in a false-positive detection
of the response.
A scrambled multiblock of 32 blocks (2048 bits) is input into the FEC parity bit generator to generate the 26-bit
parity word. The parity word is sent in the sync header stream of the next multiblock. The receiver then
calculates its own 26-bit parity word and calculates the difference between the locally generated and received
parity word, called the syndrome of the received bits. If the syndrome is 0, then all bits are assumed to have
been received correctly, while any value other than 0 indicates at least one error in either the data bits or the
parity word. If the syndrome is non-zero, then it can be used to determine the most likely error and then correct
the error. The minimum latency from a bit error to detection and correct of a bit error in the first bit of a multiblock
is 58 blocks.
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The mapping of the sync header stream when using FEC mode is shown in 表 7-13. FEC[x] corresponds to bit x
of the 26-bit FEC word. The 00001 bit sequence at the end of the sync header stream is the pilot signal that is
used to identify the end of a multiblock. It is possible for a 00001 sequence to appear in another location within
the sync header stream in FEC mode, however it is improbable to see the 00001 sequence in the same location
within a sequence of multiple multiblocks. Therefore, in FEC mode it may take more than one multiblock to find
the end of a multiblock. EoEMB is the end-of-extended-multiblock bit, which is set to 1 for the last multiblock of
an extended multiblock.
表7-13. Sync Header Stream Bit Mapping for FEC Mode
Bit
0
Function
FEC[25]
FEC[24]
FEC[23]
FEC[22]
FEC[21]
FEC[20]
FEC[19]
FEC[18]
Bit
Function
FEC[17]
FEC[16]
FEC[15]
FEC[14]
FEC[13]
FEC[12]
FEC[11]
FEC[10]
Bit
16
17
18
19
20
21
22
23
Function
FEC[9]
FEC[8]
FEC[7]
FEC[6]
FEC[5]
FEC[4]
EoEMB
FEC[3]
Bit
24
25
26
27
28
29
30
31
Function
8
FEC[2]
1
9
FEC[1]
2
10
11
12
13
14
15
FEC[0]
3
0
0
0
0
1
4
5
6
7
The FEC encoder takes in a multiblock of 32 scrambled blocks (2048 bits) and computes the 26-bit parity word
using the generator polynomial given by 方程式 7. The 2048 scrambled input bits plus 26 parity bits forms a
shortened (2074, 2048) binary cyclic code. The (2074, 2048) binary cyclic code is shortened from the cyclic Fire
code (8687, 8661). This polynomial can correct up to a 9-bit burst error per multiblock.
g(x) = (x17+1)(x9+x4+1) == x26+x21+x17+x9+x4+1
(7)
The full 26-bit FEC parity word generation is shown in 图 7-11. The input is a 2048 bit sequence, built from the
32 scrambled blocks of a multiblock (sync header is not included). The 26-bit parity word, FEC[25:0], is taken
from the Sx blocks after the full 2048 bit sequence is processed. The Sx blocks are initialized with 0's before
processing each multiblock. For more information on the FEC parity word generation, refer to the JESD204C
standard.
32-block input
(2048 bits)
1
x4
x9
x17
x21
S0
S1
S2
S3
S4
S8
S9
S16
S17
S20
S21
S24
S25
...
...
...
...
...
FEC[21] FEC[24] FEC[25]
FEC[0] FEC[1] FEC[2] FEC[3]
FEC[4]
FEC[8]
FEC[9]
FEC[16]
FEC[17]
FEC[20]
图7-11. FEC Parity Bit Generator
FEC decoding and error correction are not covered here. For full details on FEC decoding and error correction,
refer to the JESD204C standard.
7.3.8.5.4 Initial Lane Alignment
The 64B/66B link layer does not use an initial lane alignment sequence (ILAS) like the 8B/10B link layer.
Therefore, the receiver must use a different scheme to align lanes using the elastic buffer. In 8B/10B mode, the
ILAS triggers the elastic buffer to start buffering the data for each lane. After all lanes have started buffering the
data, the elastic buffers for each lane are released at a release point determined by the release buffer delay
(RBD) parameter and the phase of the LMFC. In 64B/66B mode, the process starts by having all lanes achieve
block, multiblock and extended multiblock alignment. Once all lanes have achieved alignment, the receiver can
begin buffering data in the elastic buffers at the start of the next extended multiblock on each lane. The data is
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released at the next release point after all lanes have seen the start of an extended multiblock and have started
buffering the data. The release point is defined relative to the LEMC edge and the programmed RBD value, the
most intuitive of which is to release on the LEMC edge itself. The release point must be chosen to avoid the
region of the LEMC containing variation in the data delay on each lane from startup to startup.
7.3.8.5.5 Block, Multiblock and Extended Multiblock Alignment Monitoring
Synchronization of blocks, multiblocks and extended multiblocks by monitoring the sync header of each block
and EoMB and EoEMB bit of the sync header stream. A block will always begin with a 0 to 1 or 1 to 0 transition
(sync header). A single missed sync header can occur due to a bit error, however it there are a number of sync
header errors within a set number of blocks, then block synchronization has been lost and block synchronization
should be reinitialized. It is possible to still have block synchronization, but to lose multiblock or extended
multiblock synchronization. Multiblock synchronization is monitored by looking for the EoMB signal, 00001, at the
end of the sync header stream for each multiblock. If multiple EoMB signals are erroneous within a number of
blocks, multiblock synchronization has been lost and multiblock synchronization should be reinitialized. If an
erroneous EoEMB bit is received for multiple extended multiblocks within a number of extended multiblocks,
such as a 1 for a multiblock that is not the end of an extended multiblock or a 0 for a multiblock that is the end of
an extended multiblock, then multiblock synchronization is lost and extended multiblock synchronization should
be reinitialized. If multiblock or extended multiblock synchronizaton is lost, SYSREF should be applied to the
erroneous devices in order to reestablish the LEMC before the synchronization process begins.
7.3.8.6 Physical Layer
The JESD204C physical layer consists of a current mode logic (CML) output driver and receiver. The receiver
consists of a clock detection and recovery (CDR) unit to extract the data clock from the serialized data stream
and can contain a continuous time linear equalizer (CTLE) and/or discrete feedback equalizer (DFE) to correct
for the low-pass response of the physical transmission channel. Likewise, the transmitter can contain pre-
equalization to account for frequency dependent losses across the channel. The total reach of the SerDes links
depends on the data rate, board material, connectors, equalization, noise and jitter, and required bit-error
performance. The SerDes lanes do not have to be matched in length because the receiver aligns the lanes
during the initial lane alignment sequence.
7.3.8.6.1 SerDes Pre-Emphasis
The device high-speed output drivers can pre-equalize the transmitted data stream by using pre-emphasis in
order to compensate for the low-pass response of the transmission channel. Configurable pre-emphasis settings
allow the output drive waveform to be optimized for different PCB materials and signal transmission distances.
The pre-emphasis setting is adjusted through the serializer pre-emphasis setting SER_PE (in the serializer pre-
emphasis control register). Higher values increase the pre-emphasis to compensate for more lossy PCB
materials. This adjustment is best used in conjunction with an eye-diagram analysis capability in the receiver.
Adjust the pre-emphasis setting to optimize the eye-opening for the specific hardware configuration and line
rates needed.
7.3.8.7 JESD204C Enable
The JESD204C interface must be disabled through JESD_EN (in the JESD204C enable register) while any of
the other JESD204C parameters are being changed. When JESD_EN is set to 0 the block is held in reset and
the serializers are powered down. The clocks for this section are also gated off to further save power. When the
parameters are set as desired, the JESD204C block can be enabled (JESD_EN is set to 1).
7.3.8.8 Multi-Device Synchronization and Deterministic Latency
JESD204C subclass 1 outlines a method to achieve deterministic latency across the serial link. If two devices
achieve the same deterministic latency then they can be considered synchronized. This latency must be
achieved from system startup to startup to be deterministic. There are two key requirements to achieve
deterministic latency. The first is proper capture of SYSREF for which the device provides a number of features
to simplify this requirement at giga-sample clock rates (see the SYSREF Capture section for more information).
SYSREF resets either the LMFC in 8B/10B encoding mode or the LEMC is 64B/66B encoding mode. The LMFC
and LEMC are analogous between the two modes and are now referred to as LMFC/LEMC.
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The second requirement is to choose a proper elastic buffer release point in the receiver. Because the device is
an ADC, the device is the transmitter (TX) in the JESD204C link and the logic device is the receiver (RX). The
elastic buffer is the key block for achieving deterministic latency, and does so by absorbing variations in the
propagation delays of the serialized data as the data travels from the transmitter to the receiver. A proper release
point is one that provides sufficient margin against delay variations. An incorrect release point results in a latency
variation of one LMFC/LEMC period. Choosing a proper release point requires knowing the average arrival time
of data at the elastic buffer, referenced to an LMFC/LEMC edge, and the total expected delay variation for all
devices. With this information the region of invalid release points within the LMFC/LEMC period can be defined,
which stretches from the minimum to maximum delay for all lanes. Essentially, the designer must make sure the
data for all lanes arrives at all devices after the previous release point occurs, and before the next release point
occurs.
图 7-12 provides a timing diagram that demonstrates this requirement. In this figure, the data for two ADCs is
shown. The second ADC has a longer routing distance (tPCB) and results in a longer link delay. First, the invalid
region of the LMFC/LEMC period is marked off as determined by the data arrival times for all devices. Then, the
release point is set by using the release buffer delay (RBD) parameter to shift the release point an appropriate
number of frame clocks from the LMFC/LEMC edge so that the release point occurs within the valid region of the
LMFC/LEMC cycle. In the case of 图 7-12, the LMFC/LEMC edge (RBD = 0) is a good choice for the release
point because there is sufficient margin on each side of the valid region.
Nominal Link Delay
Link Delay
(Arrival at Elastic Buffer)
Variation
ADC 1 Data
tTX
tPCB
tRX-DESER
Propagation
Choose LMFC/LEMC
edge as release point
(RBD = 0)
ADC 2 Data
Propagation
tTX
tPCB
tRX-DESER
Release point
margin
TX LMFC/LEMC
RX LMFC/LEMC
Time
Invalid Region
of LMFC/LEMC
Valid Region of
LMFC/LEMC
图7-12. LMFC/LEMC Valid Region Definition for Elastic Buffer Release Point Selection
The TX and RX LMFC/LEMCs do not necessarily need to be phase aligned, but knowledge of their phase is
important for proper elastic buffer release point selection. Also, the elastic buffer release point occurs within
every LMFC/LEMC cycle, but the buffers only release when all lanes have arrived. Therefore, the total link delay
can exceed a single LMFC/LEMC period; see JESD204B multi-device synchronization: Breaking down the
requirements for more information.
7.3.8.9 Operation in Subclass 0 Systems
ADC08DJ5200RF can operate with subclass 0 compatibility provided that multi-ADC synchronization and
deterministic latency are not required. With these limitations, the device can operate without the application of
SYSREF. The internal LMFC/LEMC is automatically self-generated with unknown timing. SYNC is used as
normal to initiate the CGS and ILAS in 8B/10B mode.
7.3.9 Alarm Monitoring
A number of built-in alarms are available to monitor internal events. Several types of alarms and upsets are
detected by this feature:
1. Serializer FIFO alarm (FIFO overflow or underflow)
2. Serializer PLL is not locked
3. JESD204C link is enabled, but not transmitting data (not in the data transmission state)
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4. SYSREF causes internal clocks to be realigned
5. An upset that impacts the NCO phase
6. An upset that impacts the JESD204C clocks
When an alarm occurs, a bit for each specific alarm is set in ALM_STATUS. Each alarm bit remains set until the
host system writes a 1 to clear the alarm. If the alarm type is not masked (see the alarm mask register), then the
alarm is also indicated by the ALARM register. The CALSTAT output pin can be configured as an alarm output
that goes high when an alarm occurs; see the CAL_STATUS_SEL bit in the calibration pin configuration register.
7.3.9.1 Clock Upset Detection
The CLK_ALM register bit indicates if the internal clocks have been upset. The clocks in channel A are
continuously compared to channel B. If the clocks differ for even one DEVCLK / 2 cycle, the CLK_ALM register
bit is set and remains set until cleared by the host system by writing a 1. For the CLK_ALM register bit to
function properly, follow these steps:
1. Program JESD_EN = 0
2. The part must be configured to use both channels (PD_ACH = 0, PD_BCH = 0)
3. Program JESD_EN = 1
4. Write CLK_ALM = 1 to clear CLK_ALM
5. Monitor the CLK_ALM status bit or the CALSTAT output pin if CAL_STATUS_SEL is properly configured
6. When exiting global power-down (via MODE or the PD pin), the CLK_ALM status bit may be set and must be
cleared by writing a 1 to CLK_ALM
7.3.9.2 FIFO Upset Detection
The FIFO_ALM bit indicates if an underflow or overflow condition has occurred on any of the JESD204C
serializer lanes within the synchronizing FIFO between the digital logic block and serializer outputs. The
FIFO_LANE_ALM register bits can be used to determine which lane triggered the underflow or overflow
condition alarm. If the FIFO pointers are upset due to an undesired clock shift or other single event or incorrect
clocking frequencies the FIFO_LANE_ALM bit for the erroneous lane will be set to 1. If the INIT_ON_FIFO_ALM
bit is set then the serializers, FIFO and JESD204C block will automatically reinitialize.
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7.4 Device Functional Modes
The ADC08DJ5200RF can be configured to operate in a number of functional modes. These modes are
described in this section.
7.4.1 Dual-Channel Mode
ADC08DJ5200RF can be used as a dual-channel ADC where the sampling rate is equal to the clock frequency
(fS = fCLK) provided at the CLK+ and CLK– pins. The two inputs, AIN± and BIN±, serve as the respective inputs
for each channel in this mode. This mode is chosen simply by setting JMODE to the appropriate setting for the
desired configuration as described in . The analog inputs can be swapped by setting DUAL_INPUT (see the
input mux control register). One channel can be powered down to operate ADC08DJ5200RF as a single channel
at the maximum sampling rate of dual channel mode to save power compared to single channel mode operating
at half the rate.
7.4.2 Single-Channel Mode (DES Mode)
The ADC08DJ5200RF can also be used as a single-channel ADC where the sampling rate is equal to two times
the clock frequency (fS = 2 × fCLK) provided at the CLK+ and CLK– pins. This mode effectively interleaves the
two ADC channels together to form a single-channel ADC at twice the sampling rate. This mode is chosen
simply by setting JMODE to the appropriate setting for the desired configuration as described in . INA± or INB±,
can serve as the input to the ADC, however INA± is recommended for highest performance. The analog input
can be selected using SINGLE_INPUT (see the input mux control register). A calibration needs to be
performance after switching the input mux for the changes to take effect.
7.4.3 Dual-Input Single-Channel Mode (DUAL DES Mode)
The ADC08DJ5200RF can also be used as a single-channel ADC where the sampling rate is equal to two times
the clock frequency (fS = 2 × fCLK) provided at the CLK+ and CLK– pins. This mode interleaves the two
channels by sampling them out-of-phase and each channel samples separate analog inputs (INA± and INB±).
The effective sampling rate is twice the device clock input (CLK±). This mode is useful for sampling the output of
interleaved track-and-hold analog front-ends. This mode is chosen by setting JMODE to a single channel mode
as described in and setting SINGLE_INPUT to use both INA± and INB± (see the input mux control register). The
digital processing and JESD204C interface operate as if the device is in single-channel mode sampling only one
of the inputs.
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7.4.4 JESD204C Modes
The ADC08DJ5200RF can be programmed as a single-channel or dual-channel ADC and a number JESD204C
output formats. 表 7-14 summarizes the basic operating mode configuration parameters and whether they are
user configured or derived.
表7-14. ADC08DJ5200RF Operating Mode Configuration Parameters
USER CONFIGURED
PARAMETER
DESCRIPTION
VALUE
OR DERIVED
JESD204C operating mode, automatically
derives the rest of the JESD204C
parameters, single-channel or dual-channel
mode
Set by JMODE (see the JESD204C mode
register)
JMODE
User configured
1 = single-channel mode, 0 = dual-channel
mode
DES
R
Derived
Derived
See Operating Modes
Number of bits transmitted per lane per CLK±
cycle. The JESD204C line rate is the CLK±
frequency times R. This parameter sets the
SerDes PLL multiplication factor or controls
bypassing of the SerDes PLL.
See Operating Modes
See Operating Modes
Links
K
Number of JESD204C links used
Derived
Set by KM1 (see the JESD204C K parameter
register), see the allowed values in Operating
Modes. This parameter is ignored in 64B/66B
modes.
Number of frames per multiframe (8B/10B
mode)
User configured
Number of multiblocks per extended
multiblock (64B/66B mode)
Always set to '1' in ADC08DJ5200RF. This
parameter is ignored in 8B/10B modes.
E
Derived
There are a number of parameters required to define the JESD204C transport layer format, all of which are sent
across the link during the initial lane alignment sequence in 8B/10B mode. 64B/66B mode does not use the
ILAS, however the transport layer uses the same parameters. In the ADC08DJ5200RF, most parameters are
automatically derived based on the selected JMODE; however, a few are configured by the user. 表 7-15
describes these parameters.
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表7-15. JESD204C Initial Lane Alignment Sequence Parameters
USER CONFIGURED
OR DERIVED
PARAMETER
ADJCNT
DESCRIPTION
VALUE
LMFC adjustment amount (not applicable)
LMFC adjustment direction (not applicable)
Bank ID
Derived
Derived
Derived
Derived
Always 0
Always 0
Always 0
Always 0
ADJDIR
BID
CF
Number of control words per frame
Always set to 0 in ILAS, see Operating
Modes for actual usage
CS
Control bits per sample
Derived
Set by DID (see the JESD204C DID
parameter register), see Lane Assignments
DID
F
Device identifier, used to identify the link
User configured
Number of octets (bytes) per frame (per lane) Derived
See Operating Modes
Always 0
High-density format (samples split between
lanes)
HD
JESDV
K
Derived
JESD204 standard revision
Derived
Always 1
Set by the KM1 register, see the JESD204C
K parameter register
Number of frames per multiframe
User configured
L
Number of serial output lanes per link
Lane identifier for each lane
Derived
Derived
See Operating Modes
LID
See Lane Assignments
Number of converters used to determine lane
bit packing; may not match number of ADC
channels in the device
M
Derived
See Operating Modes
Sample resolution (before adding control and
tail bits)
N
N'
S
Derived
Derived
Derived
See Operating Modes
See Operating Modes
See Operating Modes
Bits per sample after adding control and tail
bits
Number of samples per converter (M) per
frame
SCR
Scrambler enabled
Device subclass version
Reserved field 1
User configured
Derived
Set by the JESD204C control register
SUBCLASSV
RES1
Always 1
Always 0
Always 0
Derived
RES2
Reserved field 2
Derived
Checksum for ILAS checking (sum of all
above parameters modulo 256)
CHKSUM
Derived
Computed based on parameters in this table
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7.4.4.1 JESD204C Operating Modes Table
表7-16. ADC08DJ5200RF Operating Modes
USER-SPECIFIED
PARAMETER
DERIVED PARAMETERS
INPUT
CLOCK
RANGE
(MHz)
ADC08DJ5200RF OPERATING MODE
L
M
R
(Fbit /
Fclk)
K
JMODE
Encoding DES LINKS
N
CS
(Per
(Per
F
S
HD
E
N’
[Min:Step:Max]
Link) Link)
RESERVED
0-4
5
—
—
—
1
—
2
—
8
—
0
—
8
—
4
—
1
—
1
—
4
—
0
—
—
—
—
—
—
1
—
—
8-bit, single channel, 8 lanes
8-bit, single channel, 16 lanes
8-bit, dual channel, 8 lanes
8-bit, dual channel, 16 lanes
RESERVED
32:16:256
32:16:256
32:16:256
32:16:256
8b/10b
8b/10b
8b/10b
8b/10b
2.5
800-5200
800-5200
800-5200
800-5200
6
1
2
8
0
8
8
1
1
8
0
1.25
2.5
7
0
2
8
0
8
4
1
1
4
0
8
0
2
8
0
8
8
1
1
8
0
1.25
9-33
34
—
—
—
1
—
2
—
8
—
0
—
8
—
2
—
1
—
1
—
2
—
0
—
—
8-bit, single channel, 4 lanes
8-bit, dual channel, 4 lanes
RESERVED
256(1)
256(1)
64b/66b
64b/66b
4.125
4.125
800-4160
800-4160
35
0
2
8
0
8
2
1
1
2
0
1
36-43
44
—
—
—
1
—
2
—
8
—
0
—
8
—
4
—
1
—
1
—
4
—
0
—
1
—
—
8-bit, single channel, 8 lanes
8-bit, dual channel, 8 lanes
RESERVED
256(1)
256(1)
64b/66b
64b/66b
2.0625
2.0625
800-5200
800-5200
45
0
2
8
0
8
4
1
1
4
0
1
46-49
50
—
—
—
1
—
2
—
8
—
0
—
8
—
8
—
1
—
1
—
8
—
0
—
1
—
—
8-bit, single channel, 16 lanes
8-bit, dual channel, 16 lanes
RESERVED
256(1)
256(1)
64b/66b
64b/66b
1.03125 800-5200
1.03125 800-5200
51
0
2
8
0
8
8
1
1
8
0
1
52-71
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
(1) In the 64B/66B modes, the K parameter is not directly programmable. K is related to E and F according to the equation K=8*32*E/F. K is not an actual parameter of the 64B/66B link
layer.
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7.4.4.2 JESD204C Modes continued
Configuring the ADC08DJ5200RF is made easy by using a single configuration parameter called JMODE (see
the JESD204C mode register). Using Operating Modes, the correct JMODE value can be found for the desired
operating mode. The modes listed in Operating Modes are the only available operating modes. This table also
gives a range and allowable step size for the K parameter (set by KM1, see the JESD204C K parameter
register), which sets the multiframe length in number of frames.
The ADC08DJ5200RF has a total of 16 high-speed output drivers that are grouped into two 8-lane JESD204C
links. All operating modes use two links with up to eight lanes per link. The lanes and their derived configuration
parameters are described in the Lane Assignement and Parameters table. For a specified JMODE, the lowest
indexed lanes for each link are used and the higher indexed lanes for each link are automatically powered down.
Always route the lowest indexed lanes to the logic device.
表7-17. ADC08DJ5200RF Lane Assignment and Parameters
DEVICE PIN
DESIGNATION
JESD204C LINK
DID (User Configured)
LID (Derived)
DA0±
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
DA1±
DA2±
Set by DID (see the JESD204C DID parameter
register), the effective DID is equal to the DID register
setting (DID)
DA3±
A
DA4±
DA5±
DA6±
DA7±
DB0±
DB1±
DB2±
Set by DID (see the JESD204C DID parameter
register), the effective DID is equal to the DID register
setting plus 1 (DID+1)
DB3±
B
DB4±
DB5±
DB6±
DB7±
7.4.4.3 JESD204C Transport Layer Data Formats
Output data are formatted in a specific optimized fashion for each JMODE setting based on the transport layer
settings for that JMODE. The 8-bit offset binary values are mapped into octets. The following tables show the
specific mapping formats for a single frame for each JMODE. The symbol definitions used in the JMODE tables
is provided in 表 7-18. In all mappings the tail bits (T) are 0 (zero). All samples are formatted as MSB first, LSB
last.
表7-18. JMODE Table Symbol Definitions
NOTATION
MODE
Single channel
Dual channel
Dual channel
—
DESCRIPTION
Sample n from ADC in single channel mode
Sample n from channel A in dual channel mode
Sample n from channel A in dual channel mode
Tail bits, always set to 0
S[n]
A[n]
B[n]
T
表7-19. JMODE 5 (8-bit, Single Channel, 8 Lanes)
OCTET
0
NIBBLE
0
1
DA0
S[0]
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表7-19. JMODE 5 (8-bit, Single Channel, 8 Lanes) (continued)
OCTET
NIBBLE
DA1
0
0
1
S[2]
S[4]
S[6]
S[1]
S[3]
S[5]
S[7]
DA2
DA3
DB0
DB1
DB2
DB3
表7-19 also applies to JMODE 44.
表7-20. JMODE 6 (8-bit, Single Channel, 16 Lanes)
OCTET
0
NIBBLE
DA0
DA1
DA2
DA3
DA4
DA5
DA6
DA7
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
0
1
S[0]
S[2]
S[4]
S[6]
S[8]
S[10]
S[12]
S[14]
S[1]
S[3]
S[5]
S[7]
S[9]
S[11]
S[13]
S[15]
表7-20 also applies to JMODE 50.
表7-21. JMODE 7 (8-bit, Dual Channel, 8 Lanes)
OCTET
0
NIBBLE
DA0
0
1
A[0]
A[1]
A[2]
A[3]
B[0]
B[1]
B[2]
B[3]
DA1
DA2
DA3
DB0
DB1
DB2
DB3
表7-21 also applies to JMODE 45.
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表7-22. JMODE 8 (8-bit, Dual Channel, 16 Lanes)
OCTET
NIBBLE
DA0
DA1
DA2
DA3
DA4
DA5
DA6
DA7
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
0
0
1
A[0]
A[1]
A[2]
A[3]
A[4]
A[5]
A[6]
A[7]
B[0]
B[1]
B[2]
B[3]
B[4]
B[5]
B[6]
B[7]
表7-22 also applies to JMODE 51.
表7-23. JMODE 34 (8-bit, Single Channel, 4 lanes)
OCTET
0
NIBBLE
DA0
0
1
S[0]
S[2]
S[1]
S[3]
DA1
DB0
DB1
表7-24. JMODE 35 (8-bit, Dual Channel, 4 lanes)
OCTET
0
NIBBLE
DA0
0
1
A[0]
A[1]
B[0]
B[1]
DA1
DB0
DB1
7.4.4.4 64B/66B Sync Header Stream Configuration
The sync header stream can be used to identify bit errors on the link or to correct bit errors. Two modes of
operation are available in the device. Cyclic redundancy checking (CRC) can be used to identify bit errors. The
device only supports 12-bit CRC (CRC-12) and does not support the optional 3-bit CRC-3 described by
JESD204C. Alternatively, forward error correction (FEC) can be used to identify bit errors and then correct bit
errors. For information on CRC-12, see Cyclic Redundancy Check (CRC) Mode. For information on FEC, see
Forward Error Correction (FEC) Mode. Set the sync header stream configuration by using the sync header mode
register.
7.4.5 Power-Down Modes
The PD input pin allows the devices to be entirely powered down. Power-down can also be controlled by MODE
(see the device configuration register). To power down only one channel in dual channel mode use the channel
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power down register. The serial data output drivers are disabled when PD is high. For proper operation in
foreground calibration mode, ADC_OFF in the CAL_CFG register should be programmed to 0x1. When the
device returns to normal operation, the JESD204 link must be re-established, and the ADC pipeline contain
meaningless information so the system must wait a sufficient time for the data to be flushed.
7.4.6 Test Modes
A number of device test modes are available. These modes insert known patterns of information into the device
data path for assistance with system debug, development, or characterization.
7.4.6.1 Serializer Test-Mode Details
Test modes are enabled by setting JTEST (see the JESD204C test pattern control register) to the desired test
mode. Each test mode is described in detail in the following sections. Regardless of the test mode, the serializer
outputs (number of lanes, rate) are powered up based on JMODE. Only enable the test modes when the
JESD204C link is disabled. 图7-13 provides a diagram showing the various test mode insertion points.
ADC
JESD204C Block
Active Lanes and
Serial Rates
Set by JMODE
8B/10B or
TRANSPORT
LAYER
SERDES
TX
SCRAMBLER
LINK LAYER
64B/66B
Encoder
ADC
Short Transport Test
Long Transport Test
Octet Ramp
Repeated ILA*
Modified RPAT*
K28.5*
PRBS
Clock Pattern
Serial Outputs High/Low
D21.5
* Applies only to JMODEs using 8B/10B encoding
图7-13. Test Mode Insertion Points
7.4.6.2 PRBS Test Modes
The PRBS test modes bypass the JESD204C transport layer and link layer and are therefore neither scrambled
nor encoded. These test modes produce pseudo-random bit streams that comply with the ITU-T O.150
specification. These bit streams are used with lab test equipment or logic devices that can self-synchronize to
the bit pattern. The initial phase of the pattern is not defined since the receiver self synchronizes.
The sequences are defined by a recursive equation. For example, 方程式8 defines the PRBS7 sequence.
y[n] = y[n –6]⊕y[n –7]
(8)
where
• bit n is the XOR of bit [n –6] and bit [n –7], which are previously transmitted bits
表 7-25 lists equations and sequence lengths for the available PRBS test modes where ⊕ is the XOR operation
and y[n] represents bit n in the PRBS sequence. The initial phase of the pattern is unique for each lane.
表7-25. PBRS Mode Equations
PRBS TEST MODE
PRBS7
SEQUENCE
SEQUENCE LENGTH (bits)
127
y[n] = y[n –6]⊕y[n –7]
y[n] = y[n –5]⊕y[n –9]
y[n] = y[n –14]⊕y[n –15]
y[n] = y[n –18]⊕y[n –23]
y[n] = y[n –28]⊕y[n –31]
PRBS9
511
PRBS15
PRBS23
PRBS31
32,767
8,388,607
2,147,483,647
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7.4.6.3 Clock Pattern Mode
In the clock pattern mode, the JESD204C transport layer and link layer are bypassed, so the test sequence is
neither scrambled nor encoded. The pattern consists of a 16-bit long sequence of 8 ones and 8 zeros (1111 1111
0000 0000) that repeats indefinitely.
7.4.6.4 Ramp Test Mode
In the ramp test mode, the JESD204C link layer operates normally, but the transport layer is disabled and the
input from the formatter is ignored. In 8B/10B modes, the pattern begins after the ILA sequence finishes. In
64B/66B mode, the pattern begins after the serializers are initialized. Each lane transmits an identical octet
stream that is encoded and scrambled by the link layer. The octet stream increments from 0x00 to 0xFF and
repeats. This mode is available for both 8B/10B and 64B/66B modes.
7.4.6.5 Short and Long Transport Test Mode
JESD204C defines both short and long transport test modes to verify that the transport layers in the transmitter
and receiver are operating correctly. The transport layer test modes are the same for 8B/10B mode and 64B/66B
modes, since the transport layer is independent of the link layer.
7.4.6.5.1 Short Transport Test Pattern
Short transport test patterns send a predefined octet format that repeats every frame. In the ADC08DJ5200RF,
all JMODE configurations use the short transport test pattern. The N' = 8 short transport test pattern is shown in
表 7-26. All applicable lanes are shown, however only the enabled lanes (lowest indexed) for the configured
JMODE are used.
表7-26. Short Transport Test Pattern for N' = 8 Modes (Length = 2 Frames)
FRAME
DA0
DA1
DA2
DA3
DB0
DB1
DB2
DB3
0
1
0x00
0x01
0x02
0x03
0x00
0x01
0x02
0x03
0xFF
0xFE
0xFD
0xFC
0xFF
0xFE
0xFD
0xFC
7.4.6.6 D21.5 Test Mode
In this test mode, the controller transmits a continuous stream of D21.5 characters (alternating 0s and 1s). This
mode applies to 8B/10B and 64B/66B modes.
7.4.6.7 K28.5 Test Mode
In this test mode, the controller transmits a continuous stream of K28.5 characters. This mode only applies to
8B/10B modes.
7.4.6.8 Repeated ILA Test Mode
In this test mode, the JESD204C link layer operates normally, except that the ILA sequence (ILAS) repeats
indefinitely instead of starting the data phase. Whenever the receiver issues a synchronization request, the
transmitter initiates code group synchronization. Upon completion of code group synchronization, the transmitter
repeatedly transmits the ILA sequence. This mode only applies to 8B/10B modes.
7.4.6.9 Modified RPAT Test Mode
A 12-octet repeating pattern is defined in INCITS TR-35-2004. The purpose of this pattern is to generate white
spectral content for JESD204C compliance and jitter testing. 表 7-27 lists the pattern before and after 8B/10B
encoding. This mode only applies to 8B/10B modes.
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OCTET NUMBER
表7-27. Modified RPAT Pattern Values
20b OUTPUT OF 8B/10B ENCODER
(Two Characters)
Dx.y NOTATION
8-BIT INPUT TO 8B/10B ENCODER
0
1
D30.5
D23.6
D3.1
0xBE
0xD7
0x23
0x47
0x6B
0x8F
0xB3
0x14
0x5E
0xFB
0x35
0x59
0x86BA6
0xC6475
0xD0E8D
0xCA8B4
0x7949E
0xAA665
2
3
D7.2
4
D11.3
D15.4
D19.5
D20.0
D30.2
D27.7
D21.1
D25.2
5
6
7
8
9
10
11
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7.4.7 Calibration Modes and Trimming
ADC08DJ5200RF has two calibration modes available: foreground calibration and background calibration. When
foreground calibration is initiated the ADCs are automatically taken offline and the output data becomes mid-
code (0x000 in 2's complement) while a calibration is occurring. Background calibration allows the ADC to
continue normal operation while the ADC cores are calibrated in the background by swapping in a different ADC
core to take its place. Additional offset calibration features are available in both foreground and background
calibration modes. Further, a number of ADC parameters can be trimmed to optimize performance in a user
system.
ADC08DJ5200RF consists of a total of six sub-ADCs, each referred to as a bank, with two banks forming an
ADC core. The banks sample out-of-phase so that each ADC core is two-way interleaved. The six banks form
three ADC cores, referred to as ADC A, ADC B, and ADC C. In foreground calibration mode, ADC A samples
INA± and ADC B samples INB± in dual-channel mode and both ADC A and ADC B sample INA± (or INB±) in
single-channel mode. In the background calibration modes, the third ADC core, ADC C, is swapped in
periodically for ADC A and ADC B so that they can be calibrated without disrupting operation. 图7-14 provides a
diagram of the calibration system including labeling of the banks that make up each ADC core. When calibration
is performed the linearity, gain and offset voltage for each bank are calibrated to an internally generated
calibration signal. The analog inputs can be driven during calibration, in both foreground and background
calibration, except that when offset calibration (OS_CAL or BGOS_CAL) is used there must be no signals (or
aliased signals) near DC for proper estimation of the offset (see the Offset Calibration section).
ADC A
Bank 0
MUX
Calibration
INA+
Bank 1
Signal
INAœ
ADC A
Output
MUX
Calibration
Engine
ADC C
Bank 2
Bank 3
Calibration
Engine
MUX
Calibration
Signal
Calibration
Engine
ADC B
Output
ADC B
MUX
INB+
Bank 4
Bank 5
INBœ
MUX
Calibration
Engine
Calibration
Signal
Calibration
Engine
图7-14. ADC08DJ5200RF Calibration System Block Diagram
In addition to calibration, a number of ADC parameters are user controllable to provide trimming for optimal
performance. These parameters include input offset voltage, ADC gain, interleaving timing, and input termination
resistance. The default trim values are programmed at the factory to unique values for each device that are
determined to be optimal at the test system operating conditions. The user can read the factory-programmed
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values from the trim registers and adjust as desired. The register fields that control the trimming are labeled
according to the input that is being sampled (INA± or INB±), the bank that is being trimmed, or the ADC core that
is being trimmed. The user is not expected to change the trim values as operating conditions change, however
optimal performance can be obtained by doing so. Any custom trimming must be done on a per device basis
because of process variations, meaning that there is no global optimal setting for all parts. See the Trimming
section for information about the available trim parameters and associated registers.
7.4.7.1 Foreground Calibration Mode
Foreground calibration requires the ADC to stop converting the analog input signals during the procedure.
Foreground calibration always runs on power-up and the user must wait a sufficient time before programming
the device to nake sure the calibration is finished. Foreground calibration can be initiated by triggering the
calibration engine. The trigger source can be either the CAL_TRIG pin or CAL_SOFT_TRIG (see the calibration
software trigger register) and is chosen by setting CAL_TRIG_EN (see the calibration pin configuration register).
7.4.7.2 Background Calibration Mode
Background calibration mode allows the ADC to continuously operate, with no interruption of data. This
continuous operation is accomplished by activating an extra ADC core that is calibrated and then takes over
operation for one of the other previously active ADC cores. When that ADC core is taken off-line, that ADC is
calibrated and can in turn take over to allow the next ADC to be calibrated. This process operates continuously,
ensuring the ADC cores always provide the optimum performance regardless of system operating condition
changes. Because of the additional active ADC core, background calibration mode has increased power
consumption in comparison to foreground calibration mode. The low-power background calibration (LPBG) mode
discussed in the Low-Power Background Calibration (LPBG) Mode section provides reduced average power
consumption in comparison with the standard background calibration mode. Background calibration can be
enabled by setting CAL_BG (see the calibration configuration 0 register). CAL_TRIG_EN must be set to 0 and
CAL_SOFT_TRIG must be set to 1.
Great care has been taken to minimize effects on converted data as the core switching process occurs, however,
small brief glitches may still occur on the converter data as the cores are swapped.
7.4.7.3 Low-Power Background Calibration (LPBG) Mode
Low-power background calibration (LPBG) mode reduces the power-overhead of enabling additional ADC cores.
Off-line cores are powered down until ready to be calibrated and put on-line. Set LP_EN = 1 to enable the low-
power background calibration feature. LP_SLEEP_DLY is used to adjust the amount of time an ADC sleeps
before waking up for calibration (if LP_EN = 1 and LP_TRIG = 0). LP_WAKE_DLY sets how long the core is
allowed to stabilize before calibration and being put on-line. LP_TRIG is used to select between an automatic
switching process or one that is controlled by the user via CAL_SOFT_TRIG or CAL_TRIG. In this mode there is
an increase in power consumption during the ADC core calibration. The power consumption roughly alternates
between the power consumption in foreground calibration when the spare ADC core is sleeping to the power
consumption in background calibration when the spare ADC is being calibrated. Design the power-supply
network to handle the transient power requirements for this mode. LPBG calibration mode is not recommended
to be used in single channel operating modes.
7.4.8 Offset Calibration
Foreground calibration and background calibration modes inherently calibrate the offsets of the ADC cores;
however, the input buffers sit outside of the calibration loop and therefore their offsets are not calibrated by the
standard calibration process. In both dual-channel mode and single-channel mode, uncalibrated input buffer
offsets result in a shift in the mid-code output (DC offset) with no input. Further, in single-channel mode
uncalibrated input buffer offsets can result in a fixed spur at fS / 2. A separate calibration is provided to correct
the input buffer offsets.
There must be no signals at or near DC or aliased signals that fall at or near DC in order to properly calibration
the offsets, requiring the system to specify this condition during normal operation or have the ability to mute the
input signal during calibration. Foreground offset calibration is enabled via CAL_OS and only performs the
calibration one time as part of the foreground calibration procedure. Background offset calibration is enabled via
CAL_BGOS and continues to correct the offset as part of the background calibration routine to account for
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operating condition changes. When CAL_BGOS is set, the system must make sure there are no DC or near DC
signals or aliased signals that fall at or near DC during normal operation. When background offset calibration is
used the analog to digital conversion is disturbed by a bandwidth difference. The calibration time is relatively
long becuase the offset calibration engine requires a lot of averaging. A preferred method for offset calibration is
to use foreground calibration as a one-time operation so the timing of the disturbing glitch can be controlled. A
one time foreground calibration can be performed by setting CAL_OS to 1 before setting CAL_EN. However, this
will not correct for variations as operating conditions change.
The offset calibration correction uses the input offset voltage trim registers (see 表7-28) to correct the offset and
therefore must not be written by the user when offset calibration is used. The user can read the calibrated values
by reading the OADJ_x_VINy registers, where x is the ADC core and y is the input (INA± or INB±), after
calibration is completed. Only read the values when FG_DONE is read as 1 when using foreground offset
calibration (CAL_OS = 1) and do not read the values when using background offset calibration (CAL_BGOS =
1).
7.4.9 Trimming
表 7-28 lists the parameters that can be trimmed and the associated registers. User trimming is limited to
foreground (FG) calibration mode only.
表7-28. Trim Register Descriptions
TRIM PARAMETER
TRIM REGISTER
NOTES
Band-gap reference
BG_TRIM
Measurement on BG output pin.
RTRIM_x,
where x = A for INA± or B for INB±)
Input termination resistance
The device must be powered on with a clock applied.
OADJ_A_FG0_VINx, OADJ_A_FG90_VINx and
OADJ_B_FG0_VINx,
Input offset adjustment in dual channel mode consists
where OADJ_A applies to ADC core A and OADJ_B of changing OADJ_A_FG0_VINA for channel A and
applies to ADC core B, FG0 applies to dual channel OADJ_B_FG0_VINB for channel B. In single channel
mode for ADC cores A and B and single channel mode, OADJ_A_FG90_VINx and OADJ_B_FG0_VINx
mode for ADC core B, FG90 applies to ADC core A must be adjusted together to trim the input offset or
in single channel mode and x = A for INA± or B for adjusted separate to compensate the fS/2 offset spur.
INB±)
Input offset voltage
Set FS_RANGE_A and FS_RANGE_B to default values
before trimming the input. Use FS_RANGE_A and
FS_RANGE_B to adjust the full-scale input voltage. The
GAIN_xy_FGDUAL registers apply to Dual Channel
Mode and the GAIN_xy_FGDES registers apply to the
GAIN_xy_FGDUAL or GAIN_xy_FGDES,
Single Channel Mode. To trim the gain of ADC core A or
where x = ADC channel (A or B) and y = bank
INA± and INB± gain
B, change GAIN_x0_FGDUAL and GAIN_x1_FGDUAL
number (0 or 1)
(or GAIN_x0_FGDES and GAIN_x1_FGDES) together
in the same direction. To trim the gain of the two banks
within ADC A or B, change GAIN_x0_FGDUAL and
GAIN_x1_FGDUAL (or GAIN_x0_FGDES and
GAIN_x1_FGDES) in opposite directions.
Full-scale input voltage adjustment for each input. The
default value is effected by GAIN_Bx (x = 0, 1, 4 or 5).
INA± and INB± full-scale
input voltage
FS_RANGE_x,
Trim GAIN_Bx with FS_RANGE_x set to the default
where x = A for INA± or B for INB±)
value. FS_RANGE_x can then be used to trim the full-
scale input voltage.
Trims the timing between the two banks of an ADC core
(ADC A or B). The 0° clock phase is used for dual
channel mode and for ADC B in single channel mode.
The –90° clock phase is used only for ADC A in single-
channel mode. A mismatch in the timing between the
two banks of an ADC core can result in an fS/2-fIN spur
Bx_TIME_y,
where x = bank number (0, 1, 4 or 5)
and y = 0° (0) or –90° (90) clock phase
Intra-ADC core timing (bank
timing)
in dual channel mode or fS/4±fIN spurs in single channel
mode.
The suffix letter (A or B) indicates the ADC core that is
Inter-ADC core timing (dual-
channel mode)
being trimmed. Changing either TADJ_A or TADJ_B
adjusts the sampling instance of ADC A relative to ADC
TADJ_A, TADJ_B
B in dual channel mode.
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表7-28. Trim Register Descriptions (continued)
TRIM PARAMETER
TRIM REGISTER
NOTES
These trim registers are used to adjust the timing of
ADC core A relative to ADC core B in single channel
mode. A mismatch in the timing will result in an fS/2-fIN
spur that is signal dependent. Changing either
TADJ_A_FG90_VINx or TADJ_B_FG0_VINx changes
the relative timing of ADC core A relative to ADC core B
in single channel mode.
Inter-ADC core timing
(single-channel mode)
TADJ_A_FG90_VINx, TADJ_B_FG0_VINx,
where x = analog input (INA± or INB±)
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7.5 Programming
7.5.1 Using the Serial Interface
The serial interface is accessed using the following four pins: serial clock (SCLK), serial data in (SDI), serial data
out (SDO), and serial interface chip-select ( SCS). Register access is enabled through the SCS pin.
7.5.1.1 SCS
This signal must be asserted low to access a register through the serial interface. Setup and hold times with
respect to the SCLK must be observed.
7.5.1.2 SCLK
Serial data input is accepted at the rising edge of this signal. SCLK has no minimum frequency requirement.
7.5.1.3 SDI
Each register access requires a specific 24-bit pattern at this input. This pattern consists of a read-and-write
(R/W) bit, register address, and register value. The data are shifted in MSB first and multi-byte registers are
always in little-endian format (least significant byte stored at the lowest address). Setup and hold times with
respect to the SCLK must be observed (see the Tining Requirements table).
7.5.1.4 SDO
The SDO signal provides the output data requested by a read command. This output is high impedance during
write bus cycles and during the read bit and register address portion of read bus cycles.
As shown in 图7-15, each register access consists of 24 bits. The first bit is high for a read and low for a write.
The next 15 bits are the address of the register that is to be written to. During write operations, the last eight bits
are the data written to the addressed register. During read operations, the last eight bits on SDI are ignored and,
during this time, the SDO outputs the data from the addressed register. 图7-15 shows the serial protocol details.
Single Register Access
SCS
1
8
16
17
24
SCLK
SDI
Command Field
Data Field
R/W A14 A13 A12 A11 A10 A9
A8
A7
A6
A5
A4
A3
A2
A1 A0
D7
D6
D5
D4
D3
D2
D1 D0
Data Field
High Z
High Z
SDO
(read mode)
D7
D6
D5
D4
D3 D2
D1
D0
图7-15. Serial Interface Protocol: Single Read/Write
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7.5.1.5 Streaming Mode
The serial interface supports streaming reads and writes. In this mode, the initial 24 bits of the transaction
specifics the access type, register address, and data value as normal. Additional clock cycles of write or read
data are immediately transferred, as long as the SCS input is maintained in the asserted (logic low) state. The
register address auto increments (default) or decrements for each subsequent 8-bit transfer of the streaming
transaction. The ADDR_ASC bit (register 000h, bits 5 and 2) controls whether the address value ascends
(increments) or descends (decrements). Streaming mode can be disabled by setting the ADDR_HOLD bit (see
the user SPI configuration register). 图7-16 shows the streaming mode transaction details.
Multiple Register Access
SCS
1
8
16
17
24
25
32
SCLK
SDI
Command Field
Data Field (write mode)
D4 D3 D2 D1
Data Field (write mode)
D5 D4 D3 D2
A1
1
R/W A14 A13 A12
A10 A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
D7
D6
D5
D0
D7
D6
D1
D0
Data Field
D4 D3 D2
Data Field
D3 D2
High Z
High Z
SDO
(read mode)
D7
D6
D5
D1
D0
D7
D6
D5
D4
D1
D0
图7-16. Serial Interface Protocol: Streaming Read/Write
See the SPI Register Map section for detailed information regarding the registers.
备注
The serial interface must not be accessed during ADC calibration. Accessing the serial interface
during this time impairs the performance of the device until the device is calibrated correctly. Writing or
reading the serial registers also reduces dynamic ADC performance for the duration of the register
access time.
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7.6 SPI Register Map
表 7-29 lists the SPI_Register_Map registers. All register offset addresses not listed in 表 7-29 should be
considered as reserved locations and the register contents should not be modified.
表7-29. SPI REGISTER MAP Registers
Address
0x0
Acronym
Register Name
Section
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
CONFIG_A
DEVICE_CONFIG
CHIP_TYPE
CHIP_ID
Configuration A (default: 0x30)
0x2
Device Configuration (default: 0x00)
Chip Type (Default: 0x03)
0x3
0x4
Chip Identification
0xC
VENDOR_ID
USR0
Vendor Identification (Default = 0x0451)
User SPI Configuration (Default: 0x00)
Clock Control 0 (default: 0x00)
0x10
0x29
0x2A
0x02B
0x2C
0x30
0x32
0x38
0x3B
0x48
0x60
0x61
0x62
0x64
0x68
0x6A
0x6B
0x6C
0x6E
0x70
0x71
0x7A
0x7B
0x7C
0x7E
0x7F
0x9D
0x160
0x200
0x201
0x202
0x203
0x204
0x205
0x206
0x207
CLK_CTRL0
CLK_CTRL1
CLK_CNTL2
SYSREF_POS
FS_RANGE_A
FS_RANGE_B
BG_BYPASS
TMSTP_CTRL
SER_PE
Clock Control 1 (default: 0x00)
Clock Control 2 (default: 0x11)
SYSREF Capture Position (Read-Only, Default: undefined)
FS_RANGE_A (default: 0xA000)
FS_RANGE_B (default: 0xA000)
Band-Gap Bypass (default: 0x00)
TMSTP Control (default: 0x00)
Serializer Pre-Emphasis Control (default: 0x00)
Input Mux Control (default: 0x01)
INPUT_MUX
CAL_EN
Calibration Enable (Default: 0x01)
CAL_CFG0
CAL_CFG2
CAL_AVG
Calibration Configuration 0 (Default: 0x01)
Calibration Configuration 0 (Default: 0x02)
Calibration Averaging (default: 0x61)
Calibration Status (default: undefined) (read-only)
Calibration Pin Configuration (default: 0x00)
Calibration Software Trigger (default: 0x01)
Low-Power Background Calibration (default: 0x88)
Calibration Data Enable (default: 0x00)
Calibration Data (default: undefined)
Gain DAC Trim A (default from Fuse ROM)
Gain DAC Trim B (default from Fuse ROM)
Band-Gap Trim (default from Fuse ROM)
Resistor Trim for VinA (default from Fuse ROM)
Resistor Trim for VinB (default from Fuse ROM)
ADC Dither Control (default from Fuse ROM)
LSB Control Bit Output (default: 0x00)
JESD204C Subsystem Enable (default: 0x01)
JESD204C Mode (default: 0x02)
CAL_STATUS
CAL_PIN_CFG
CAL_SOFT_TRIG
CAL_LP
CAL_DATA_EN
CAL_DATA
GAIN_TRIM_A
GAIN_TRIM_B
BG_TRIM
RTRIM_A
RTRIM_B
ADC_DITH
LSB_CTRL
JESD_EN
JMODE
KM1
JESD204C K Parameter (default: 0x1F)
JESD204C Manual Sync Request (default: 0x01)
JESD204C Control (default: 0x03)
JSYNC_N
JCTRL
JTEST
JESD204C Test Control (default: 0x00)
JESD204C DID Parameter (default: 0x00)
JESD204C Frame Character (default: 0x00)
DID
FCHAR
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表7-29. SPI REGISTER MAP Registers (continued)
Address
0x208
0x209
0x20A
0x20B
0x20F
0x211
0x212
0x213
0x270
0x297
0x2A2
0x2B0
0x2B1
0x2B2
0x2B5
0x2B8
0x2C0
0x2C1
0x2C2
0x2C4
0x310
0x313
0x314
Acronym
Register Name
Section
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
JESD_STATUS
PD_CH
JESD204C / System Status Register
JESD204C Channel Power Down (default: 0x00)
JESD204C Extra Lane Enable (Link A) (default: 0x00)
JESD204C Extra Lane Enable (Link B) (default: 0x00)
JESD204C Sync Word Mode (default: 0x00)
Over-range Threshold 0 (default: 0xF2)
JEXTRA_A
JEXTRA_B
SHMODE
OVR_T0
OVR_T1
Over-range Threshold 1 (default: 0xAB)
OVR_CFG
INIT_STATUS
SPIN_ID
Over-range Enable / Hold Off (default: 0x07)
Initialization Status (read-only)
Chip Spin Identifier (default: See description, read-only)
Analog Test Bus Control (default: 0x00)
TESTBUS
SRC_EN
SYSREF Calibration Enable (default: 0x00)
SYSREF Calibration Configuration (default: 0x05)
SYSREF Calibration Status (read-only, default: undefined)
DEVCLK Timing Adjust (default: 0x00)
SRC_CFG
SRC_STATUS
TAD
TAD_RAMP
ALARM
DEVCLK Timing Adjust Ramp Control (default: 0x00)
Alarm Interrupt (read-only)
ALM_STATUS
ALM_MASK
FIFO_LANE_ALM
TADJ_A
Alarm Status (default: 0x3F, write to clear)
Alarm Mask Register (default: 0x3F)
FIFO Overflow/Underflow Alarm (default: 0xFFFF)
Timing Adjust for A-ADC operating in Dual Channel Mode (default from Fuse ROM)
Timing Adjust for B-ADC operating in Dual Channel Mode (default from Fuse ROM)
TADJ_B
TADJ_A_FG90_VINA
Timing Adjust for A-ADC operating in Single Channel Mode and sampling INA±
(default from Fuse ROM)
0x315
0x31A
0x31B
0x344
0x346
0x348
0x34A
TADJ_B_FG0_VINA
TADJ_A_FG90_VINB
TADJ_B_FG0_VINB
OADJ_A_FG0_VINA
OADJ_A_FG0_VINB
OADJ_A_FG90_VINA
OADJ_A_FG90_VINB
Timing Adjust for B-ADC operating in Single Channel Mode and sampling INA±
(default from Fuse ROM)
Go
Go
Go
Go
Go
Go
Go
Timing Adjust for A-ADC operating in Single Channel Mode and sampling INB±
(default from Fuse ROM)
Timing Adjust for B-ADC operating in Single Channel Mode and sampling INB±
(default from Fuse ROM)
Offset Adjustment for A-ADC operating in Dual Channel Mode sampling INA±
(default from Fuse ROM)
Offset Adjustment for A-ADC operating in Dual Channel Mode sampling INB±
(default from Fuse ROM)
Offset Adjustment for A-ADC operating in Single Channel Mode sampling INA±
(default from Fuse ROM)
Offset Adjustment for A-ADC operating in Single Channel Mode sampling INB±
(default from Fuse ROM)
0x34C
0x34E
0x350
0x351
0x352
0x353
0x354
OADJ_B_FG0_VINA
OADJ_B_FG0_VINB
GAIN_A0_FGDUAL
GAIN_A1_FGDUAL
GAIN_B0_FGDUAL
GAIN_B1_FGDUAL
GAIN_A0_FGDES
Offset Adjustment for B-ADC sampling INA± (default from Fuse ROM)
Go
Go
Go
Go
Go
Go
Go
Offset Adjustment for B-ADC sampling INB± (default from Fuse ROM)
Fine Gain Adjust for ADC A Bank 0 in Dual Channel Mode (default from Fuse ROM)
Fine Gain Adjust for ADC A Bank 1 in Dual Channel Mode (default from Fuse ROM)
Fine Gain Adjust for ADC B Bank 0 in Dual Channel Mode (default from Fuse ROM)
Fine Gain Adjust for ADC B Bank 1 in Dual Channel Mode (default from Fuse ROM)
Fine Gain Adjust for ADC A Bank 0 in Single Channel Mode (default from Fuse
ROM)
0x355
GAIN_A1_FGDES
Fine Gain Adjust for ADC A Bank 1 in Single Channel Mode (default from Fuse
ROM)
Go
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表7-29. SPI REGISTER MAP Registers (continued)
Address
Acronym
Register Name
Section
0x356
GAIN_B0_FGDES
Fine Gain Adjust for ADC B Bank 0 in Single Channel Mode (default from Fuse
ROM)
Go
0x357
GAIN_B1_FGDES
Fine Gain Adjust for ADC B Bank 1 in Single Channel Mode (default from Fuse
ROM)
Go
0x400
0x418
0x41A
0x41C
0x41E
0x420
0x423
0x425
0x427
0x429
0x448
0x44A
0x44C
0x44E
0x450
0x453
0x455
0x457
0x459
PFIR_CFG
PFIR_A0
PFIR_A1
PFIR_A2
PFIR_A3
PFIR_A4
PFIR_A5
PFIR_A6
PFIR_A7
PFIR_A8
PFIR_B0
PFIR_B1
PFIR_B2
PFIR_B3
PFIR_B4
PFIR_B5
PFIR_B6
PFIR_B7
PFIR_B8
Programmable FIR Mode (default: 0x00)
PFIR Coefficient A0
PFIR Coefficient A1
PFIR Coefficient A2
PFIR Coefficient A3
PFIR Coefficient A4
PFIR Coefficient A5
PFIR Coefficient A6
PFIR Coefficient A7
PFIR Coefficient A8
PFIR Coefficient B0
PFIR Coefficient B1
PFIR Coefficient B2
PFIR Coefficient B3
PFIR Coefficient B4
PFIR Coefficient B5
PFIR Coefficient B6
PFIR Coefficient B7
PFIR Coefficient B8
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Complex bit access types are encoded to fit into small table cells. 表 7-30 shows the codes that are used for
access types in this section.
表7-30. SPI_Register_Map Access Type Codes
Access Type
Read Type
R
Code
Description
R
Read
Write Type
W
W
Write
Reset or Default Value
-n
Value after reset or the default
value
Register Array Variables
i,j,k,l,m,n
When these variables are used in
a register name, an offset, or an
address, they refer to the value of
a register array where the register
is part of a group of repeating
registers. The register groups
form a hierarchical structure and
the array is represented with a
formula.
y
When this variable is used in a
register name, an offset, or an
address it refers to the value of a
register array.
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7.6.1 CONFIG_A Register (Address = 0x0) [reset = 0x30]
CONFIG_A is shown in 图7-17 and described in 表7-31.
Return to the Summary Table.
Configuration A (default: 0x30)
图7-17. CONFIG_A Register
7
6
5
4
3
2
1
0
SOFT_RESET
R/W-0x0
RESERVED
R/W-0x0
ASCEND
R/W-0x1
SDO_ACTIVE
R-0x1
RESERVED
R/W-0x0
表7-31. CONFIG_A Register Field Descriptions
Bit
Field
Type
Reset
Description
7
SOFT_RESET
R/W
0x0
Setting this bit causes a full reset of the chip and all SPI registers
(including CONFIG_A). This bit is self-clearing. After writing this bit,
the part may take up to 750ns to reset. During this time, do not
perform any SPI transactions.
6
5
RESERVED
ASCEND
R/W
R/W
0x0
0x1
0 : Address is decremented during streaming reads/writes
1 : Address is incremented during streaming reads/writes (default)
4
SDO_ACTIVE
RESERVED
R
0x1
0x0
Always returns 1. Always use SDO for SPI reads.
No SDIO mode supported.
3:0
R/W
7.6.2 DEVICE_CONFIG Register (Address = 0x2) [reset = 0x00]
DEVICE_CONFIG is shown in 图7-18 and described in 表7-32.
Return to the Summary Table.
Device Configuration (default: 0x00)
图7-18. DEVICE_CONFIG Register
7
6
5
4
3
2
1
0
RESERVED
R/W-0x0
MODE
R/W-0x0
表7-32. DEVICE_CONFIG Register Field Descriptions
Bit
Field
Type
R/W
R/W
Reset
Description
7:2
1:0
RESERVED
MODE
0x0
0x0
0 : Normal operation (default)
1 : Reserved
2 : Reserved
3 : Power down (lowest power, slower resume)
7.6.3 CHIP_TYPE Register (Address = 0x3) [reset = 0x03]
CHIP_TYPE is shown in 图7-19 and described in 表7-33.
Return to the Summary Table.
Chip Type (Default: 0x03)
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图7-19. CHIP_TYPE Register
7
6
5
4
3
2
1
0
RESERVED
R/W-0x0
CHIP_TYPE
R-0x3
表7-33. CHIP_TYPE Register Field Descriptions
Bit
Field
Type
R/W
R
Reset
Description
7:4
3:0
RESERVED
CHIP_TYPE
0x0
0x3
Always returns 0x3, indicating that the part is a high speed ADC.
7.6.4 CHIP_ID Register (Address = 0x4) [reset = 0x0]
CHIP_ID is shown in 图7-20 and described in 表7-34.
Return to the Summary Table.
Chip Identification
图7-20. CHIP_ID Register
15
7
14
6
13
5
12
11
10
2
9
1
8
0
CHIP_ID
R-0x0
4
3
CHIP_ID
R-0x0
表7-34. CHIP_ID Register Field Descriptions
Bit
15:0
Field
Type
Reset
Description
CHIP_ID
R
0x0
Returns 0x0021 indicating the device is in the ADCrrDJssssRF
family.
7.6.5 VENDOR_ID Register (Address = 0xC) [reset = 0x0]
VENDOR_ID is shown in 图7-21 and described in 表7-35.
Return to the Summary Table.
Vendor Identification (Default = 0x0451)
图7-21. VENDOR_ID Register
15
7
14
6
13
5
12
11
10
2
9
1
8
0
VENDOR_ID
R-0x0
4
3
VENDOR_ID
R-0x0
表7-35. VENDOR_ID Register Field Descriptions
Bit
15:0
Field
VENDOR_ID
Type
Reset
Description
R
0x0
Always returns 0x0451 (Vendor ID for Texas Instruments)
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7.6.6 USR0 Register (Address = 0x10) [reset = 0x00]
USR0 is shown in 图7-22 and described in 表7-36.
Return to the Summary Table.
User SPI Configuration (Default: 0x00)
图7-22. USR0 Register
7
6
5
4
3
2
1
0
RESERVED
R/W-0x0
ADDR_HOLD
R/W-0x0
表7-36. USR0 Register Field Descriptions
Bit
Field
Type
R/W
R/W
Reset
Description
7:1
0
RESERVED
0x0
ADDR_HOLD
0x0
0 : Use ASCEND register to select address ascend/descend mode
(default)
1 : Address stays constant throughout streaming operation; useful for
reading and writing calibration vector information at the CAL_DATA
register
7.6.7 CLK_CTRL0 Register (Address = 0x29) [reset = 0x00]
CLK_CTRL0 is shown in 图7-23 and described in 表7-37.
Return to the Summary Table.
Clock Control 0 (default: 0x00)
图7-23. CLK_CTRL0 Register
7
6
5
4
3
2
1
0
RESERVED
SYSREF_PRO SYSREF_REC SYSREF_ZOO
SYSREF_SEL
R/W-0x0
C_EN
V_EN
M
R/W-0x0
R/W-0x0
R/W-0x0
R/W-0x0
表7-37. CLK_CTRL0 Register Field Descriptions
Bit
7
Field
RESERVED
Type
R/W
R/W
Reset
Description
0x0
6
SYSREF_PROC_EN
0x0
This bit enables the SYSREF processor, which allows the device to
process SYSREF events (default: disabled). SYSREF_RECV_EN
must be set before setting SYSREF_PROC_EN.
5
4
SYSREF_RECV_EN
SYSREF_ZOOM
R/W
R/W
0x0
0x0
Set this bit to enable the SYSREF receiver circuit (default: disabled)
Set this bit to zoom in the SYSREF windowing status and delays
(impacts SYSERF_POS and SYSREF_SEL). When set, the delays
used in the SYSREF windowing feature (reported in the
SYSREF_POS register) become smaller. Use SYSREF_ZOOM for
high clock rates, specifically when multiple SYSREF valid windows
are encountered in the SYSREF_POS register; see the SYSREF
Position Detector and Sampling Position Selection (SYSREF
Windowing) section.
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表7-37. CLK_CTRL0 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
3:0
SYSREF_SEL
R/W
0x0
Set this field to select which SYSREF delay to use. Set this field
based on the results returned by SYSREF_POS; see the SYSREF
Position Detector and Sampling Position Selection (SYSREF
Windowing) section. These bits must be set to 0 to use SYSREF
calibration; see the Automatic SYSREF Calibration section.
7.6.8 CLK_CTRL1 Register (Address = 0x2A) [reset = 0x00]
CLK_CTRL1 is shown in 图7-24 and described in 表7-38.
Return to the Summary Table.
Clock Control 1 (default: 0x00)
图7-24. CLK_CTRL1 Register
7
6
5
4
3
2
1
0
RESERVED
R/W-0x0
SYSREF_TIME DEVCLK_LVPE SYSREF_LVPE SYSREF_INVE
_STAMP_EN
CL_EN
CL_EN
RTED
R/W-0x0
R/W-0x0
R/W-0x0
R/W-0x0
表7-38. CLK_CTRL1 Register Field Descriptions
Bit
Field
RESERVED
Type
Reset
Description
7:4
3
R/W
0x0
SYSREF_TIME_STAMP_ R/W
EN
0x0
The SYSREF signal can be observed on the LSB of the JESD204C
output samples when SYSREF_TIMESTAMP_EN and
TIME_STAMP_EN are both set. This bit allows SYSREF± to be used
as the timestamp input.
2
1
0
DEVCLK_LVPECL_EN
SYSREF_LVPECL_EN
SYSREF_INVERTED
R/W
R/W
R/W
0x0
0x0
0x0
Activate DC-coupled, low-voltage PECL mode for CLK±; see the Pin
Functions table.
Activate DC-coupled, low-voltage PECL mode for SYSREF±; see the
Pin Functions table.
This bit inverts the SYSREF signal used for alignment.
7.6.9 CLK_CTRL2 Register (Address = 0x02B) [reset = 0x11]
CLK_CTRL2 is shown in and described in 图7-25 and described in 表7-39.
Return to the Summary Table.
Clock Control 2 (default: 0x11)
图7-25. CLK_CTRL2 Register
7
6
5
4
3
2
1
0
RESERVED
C_CLK_FEEDB
ACK_GAIN
Reserved
EN_VA11_NOIS
E_SUPPR
CLKSAMP_DEL
R/W-0x0
R/W-0x1
R/W-0x0
R/W-0x0
R/W-0x1
表7-39. CLK_CTRL2 Register Field Descriptions
Bit
7:5
Field
RESERVED
Type
Reset
Description
R/W
0x0
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表7-39. CLK_CTRL2 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
4
C_CLK_FEEDBACK_GAI R/W
N
0x1
Adjustable feedback gain for CMLtoCMOS converter (high gain:1)
3
2
Reserved
R/W
0x0
0x0
Reserved
EN_VA11_NOISE_SUPPR R/W
When set, noise on VA11 is suppressed. It is recommended to have
this set, as it reduces noise coupling from the digital circuits to
analog clock, at the expense of a small increase in power.
1:0
CLKSAMP_DEL
R/W
0x1
Adjustable delay for the sampling clock (one hot encoded)
7.6.10 SYSREF_POS Register (Address = 0x2C) [reset = 0x0]
SYSREF_POS is shown in 图7-26 and described in 表7-40.
Return to the Summary Table.
SYSREF Capture Position (Read-Only, Default: undefined)
图7-26. SYSREF_POS Register
23
15
7
22
14
6
21
13
5
20
19
18
10
2
17
9
16
8
SYSREF_POS
R/W-0x0
12
4
11
3
SYSREF_POS
R/W-0x0
1
0
SYSREF_POS
R/W-0x0
表7-40. SYSREF_POS Register Field Descriptions
Bit
23:0
Field
SYSREF_POS
Type
Reset
Description
R/W
0x0
Returns a 24-bit status value that indicates the position of the
SYSREF edge with respect to CLK±. Use this to program
SYSREF_SEL.
7.6.11 FS_RANGE_A Register (Address = 0x30) [reset = 0xA000]
FS_RANGE_A is shown in 图7-27 and described in 表7-41.
Return to the Summary Table.
FS_RANGE_A (default: 0xA000)
图7-27. FS_RANGE_A Register
15
7
14
6
13
5
12
11
10
2
9
1
8
0
FS_RANGE_A
R/W-0xA000
4
3
FS_RANGE_A
R/W-0xA000
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表7-41. FS_RANGE_A Register Field Descriptions
Bit
Field
Type
Reset
Description
15:0
FS_RANGE_A
R/W
0xA000
These bits enable adjustment of the analog full-scale range for INA±.
0x0000: Settings below 0x2000 result in degraded performance
0x2000: 500 mVPP - Recommended minimum setting
0xA000: 800 mVPP (default)
0xFFFF: 1000 mVPP - Maximum setting
7.6.12 FS_RANGE_B Register (Address = 0x32) [reset = 0xA000]
FS_RANGE_B is shown in 图7-28 and described in 表7-42.
Return to the Summary Table.
FS_RANGE_B (default: 0xA000)
图7-28. FS_RANGE_B Register
15
7
14
6
13
5
12
11
10
2
9
1
8
0
FS_RANGE_B
R/W-0xA000
4
3
FS_RANGE_B
R/W-0xA000
表7-42. FS_RANGE_B Register Field Descriptions
Bit
15:0
Field
FS_RANGE_B
Type
Reset
Description
R/W
0xA000
These bits enable adjustment of the analog full-scale range for INB±.
0x0000: Settings below 0x2000 result in degraded performance
0x2000: 500 mVPP - Recommended minimum setting
0xA000: 800 mVPP (default)
0xFFFF: 1000 mVPP - Maximum setting
7.6.13 BG_BYPASS Register (Address = 0x38) [reset = 0x00]
BG_BYPASS is shown in 图7-29 and described in 表7-43.
Return to the Summary Table.
Band-Gap Bypass (default: 0x00)
图7-29. BG_BYPASS Register
7
6
5
4
3
2
1
0
RESERVED
R/W-0x0
BG_BYPASS
R/W-0x0
表7-43. BG_BYPASS Register Field Descriptions
Bit
Field
Type
R/W
R/W
Reset
Description
7:1
0
RESERVED
BG_BYPASS
0x0
0x0
When set, VA11 is used as the voltage reference instead of the
band-gap voltage.
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7.6.14 TMSTP_CTRL Register (Address = 0x3B) [reset = 0x00]
TMSTP_CTRL is shown in 图7-30 and described in 表7-44.
Return to the Summary Table.
TMSTP Control (default: 0x00)
图7-30. TMSTP_CTRL Register
7
6
5
4
3
2
1
0
RESERVED
R/W-0x0
TMSTP_LVPEC TMSTP_RECV
L_EN
_EN
R/W-0x0
R/W-0x0
表7-44. TMSTP_CTRL Register Field Descriptions
Bit
Field
Type
R/W
R/W
Reset
Description
7:2
1
RESERVED
0x0
TMSTP_LVPECL_EN
0x0
When set, activates the low voltage PECL mode for the differential
TMSTP± input.
0
TMSTP_RECV_EN
R/W
0x0
Enables the differential differential TMSTP± input.
7.6.15 SER_PE Register (Address = 0x48) [reset = 0x00]
SER_PE is shown in 图7-31 and described in 表7-45.
Return to the Summary Table.
Serializer Pre-Emphasis Control (default: 0x00)
图7-31. SER_PE Register
7
6
5
4
3
2
1
0
RESERVED
R/W-0x0
SER_PE_BOO
ST
SER_PE
R/W-0x0
R/W-0x0
表7-45. SER_PE Register Field Descriptions
Bit
Field
Type
R/W
R/W
Reset
Description
7:4
3
RESERVED
0x0
SER_PE_BOOST
0x0
Additional pre-emphesis boost that increases the pre-emphesis
slightly and extends it in time.
2:0
SER_PE
R/W
0x0
Sets the pre-emphasis for the SerDes output lanes. Pre-emphasis
can be used to compensate for the high-frequency loss of the PCB
trace. This is a global setting that affects all 16 lanes (DA[7:0]±,
DB[7:0]±).
7.6.16 INPUT_MUX Register (Address = 0x60) [reset = 0x01]
INPUT_MUX is shown in 图7-32 and described in 表7-46.
Return to the Summary Table.
Input Mux Control (default: 0x01)
图7-32. INPUT_MUX Register
7
6
5
4
3
2
1
0
RESERVED
DUAL_INPUT
RESERVED
SINGLE_INPUT
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图7-32. INPUT_MUX Register (continued)
R/W-0x0
R/W-0x0
R/W-0x0
R/W-0x1
表7-46. INPUT_MUX Register Field Descriptions
Bit
7:5
4
Field
Type
R/W
R/W
Reset
Description
RESERVED
0x0
DUAL_INPUT
0x0
Select inputs for dual channel modes. If JMODE is selecting a single
channel mode, this register has no effect.
0: A channel samples INA±, B channel samples INB± (no swap)
(default)
1: A channel samples INB±, B channel samples INA± (swap)
3:2
1:0
RESERVED
R/W
R/W
0x0
0x1
SINGLE_INPUT
Defines which input is sampled in single channel mode. If JMODE is
not selecting a single channel mode, this register has no effect.
0: RESERVED
1: INA± is used (default)
2: INB± is used
3: ADC channel A samples INA± and ADC channel B samples INB±
(DUAL DES mode). A calibration needs to be performance after
switching the input mux for the changes to take effect.
7.6.17 CAL_EN Register (Address = 0x61) [reset = 0x01]
CAL_EN is shown in 图7-33 and described in 表7-47.
Return to the Summary Table.
Calibration Enable (Default: 0x01)
图7-33. CAL_EN Register
7
6
5
4
3
2
1
0
RESERVED
R/W-0x0
CAL_EN
R/W-0x1
表7-47. CAL_EN Register Field Descriptions
Bit
Field
Type
R/W
R/W
Reset
Description
7:1
0
RESERVED
CAL_EN
0x0
0x1
Calibration Enable. Set high to run calibration. Set low to hold
calibration in reset to program new calibration settings. Clearing
CAL_EN also resets the clock dividers that clock the digital block and
JESD204C interface.
Some calibration registers require clearing CAL_EN before making
any changes. All registers with this requirement contain a note in
their descriptions. After changing the registers, set CAL_EN to re-run
calibration with the new settings. Always set CAL_EN before setting
JESD_EN. Always clear JESD_EN before clearing CAL_EN.
7.6.18 CAL_CFG0 Register (Address = 0x62) [reset = 0x01]
CAL_CFG0 is shown in 图7-34 and described in 表7-48.
Return to the Summary Table.
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Calibration Configuration 0 (Default: 0x01)
图7-34. CAL_CFG0 Register
7
6
5
4
3
2
1
0
RESERVED
R/W-0x0
CAL_BGOS
R/W-0x0
CAL_OS
R/W-0x0
CAL_BG
R/W-0x0
CAL_FG
R/W-0x1
表7-48. CAL_CFG0 Register Field Descriptions
Bit
Field
Type
R/W
R/W
Reset
Description
7:4
3
RESERVED
CAL_BGOS
0x0
0x0
0 : Disable background offset calibration (default)
1 : Enable background offset calibration (requires CAL_BG to be
set).
2
1
0
CAL_OS
CAL_BG
CAL_FG
R/W
R/W
R/W
0x0
0x0
0x1
0 : Disable foreground offset calibration (default)
1 : Enable foreground offset calibration (requires CAL_FG to be set).
0 : Disable background calibration (default)
1 : Enable background calibration
0 : Reset calibration values, skip foreground calibration.
1 : Reset calibration values, then run foreground calibration (default).
7.6.19 CAL_CFG2 Register (Address = 0x64) [reset = 0x02]
CAL_CFG2 is shown in 图7-35and described in 表7-49.
Return to the Summary Table.
Calibration Configuration 2 (Default: 0x02)
图7-35. CAL_CFG2 Register
7
6
5
4
3
2
1
0
RESERVED
R/W-0x00
ADC_OFF
R/W-0x10
表7-49. CAL_CFG2 Register Field Descriptions
Bit
Field
Type
R/W
R/W
Reset
0x00
0x1
Description
7:2
1:0
RESERVED
ADC_OFF
Reserved
If background calibration is disabled, this selects which ADC will be
disabled and never calibrated. Only change ADC_OFF while
JESD_EN is 0.
0 : ADC0 (ADC1 will stand in for ADC0)
1 : ADC1
2 : ADC2 (ADC1 will stand in for ADC2)
3 : Reserved
7.6.20 CAL_AVG Register (Address = 0x68) [reset = 0x61]
CAL_AVG is shown in 图7-36 and described in 表7-50.
Return to the Summary Table.
Calibration Averaging (default: 0x61)
图7-36. CAL_AVG Register
7
6
5
4
3
2
1
0
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图7-36. CAL_AVG Register (continued)
RESERVED
R/W-0x0
OS_AVG
RESERVED
CAL_AVG
R/W-0x1
R/W-0x6
R/W-0x0
表7-50. CAL_AVG Register Field Descriptions
Bit
7
Field
Type
R/W
R/W
Reset
Description
RESERVED
OS_AVG
0x0
6:4
0x6
Select the amount of averaging used for the offset correction routine.
A larger number corresponds to more averaging.
3
RESERVED
CAL_AVG
R/W
R/W
0x0
0x1
2:0
Select the amount of averaging used for the linearity calibration
routine. A larger number corresponds to more averaging.
7.6.21 CAL_STATUS Register (Address = 0x6A) [reset = 0x0]
CAL_STATUS is shown in 图7-37 and described in 表7-51.
Return to the Summary Table.
Calibration Status (default: undefined) (read-only)
图7-37. CAL_STATUS Register
7
6
5
4
3
2
1
0
RESERVED
CAL_STAT
R-0x0
CAL_STOPPE
D
FG_DONE
R-0x0
R-0x0
R-0x0
表7-51. CAL_STATUS Register Field Descriptions
Bit
Field
Type
Reset
Description
7:5
4:2
RESERVED
CAL_STAT
R
0x0
R
0x0
Calibration status code
1
CAL_STOPPED
R
R
0x0
0x0
This bit returns a 1 when background calibration is successfully
stopped at the requested phase. This bit returns a 0 when calibration
starts operating again. If background calibration is disabled, this bit is
set when foreground calibration is completed or skipped.
0
FG_DONE
This bit is high to indicate that foreground calibration has completed
(or was skipped).
7.6.22 CAL_PIN_CFG Register (Address = 0x6B) [reset = 0x00]
CAL_PIN_CFG is shown in 图7-38 and described in 表7-52.
Return to the Summary Table.
Calibration Pin Configuration (default: 0x00)
图7-38. CAL_PIN_CFG Register
7
6
5
4
3
2
1
0
RESERVED
R/W-0x0
CAL_STATUS_SEL
R/W-0x0
CAL_TRIG_EN
R/W-0x0
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表7-52. CAL_PIN_CFG Register Field Descriptions
Bit
7:3
2:1
Field
Type
R/W
R/W
Reset
Description
RESERVED
0x0
CAL_STATUS_SEL
0x0
0 : CALSTAT output matches FG_DONE.
1 : CALSTAT output matches CAL_STOPPED.
2 : CALSTAT output matches ALARM.
3 : CALSTAT output is always low.
0
CAL_TRIG_EN
R/W
0x0
This bit selects the hardware or software trigger source.
0 : Use the CAL_SOFT_TRIG register for the calibration trigger. The
CALTRIG input is disabled (ignored).
1 : Use the CALTRIG input for the calibration trigger. The
CAL_SOFT_TRIG register is ignored.
7.6.23 CAL_SOFT_TRIG Register (Address = 0x6C) [reset = 0x01]
CAL_SOFT_TRIG is shown in 图7-39 and described in 表7-53.
Return to the Summary Table.
Calibration Software Trigger (default: 0x01)
图7-39. CAL_SOFT_TRIG Register
7
6
5
4
3
2
1
0
RESERVED
CAL_SOFT_TR
IG
R/W-0x0
R/W-0x1
表7-53. CAL_SOFT_TRIG Register Field Descriptions
Bit
Field
Type
R/W
R/W
Reset
Description
7:1
0
RESERVED
0x0
CAL_SOFT_TRIG
0x1
CAL_SOFT_TRIG is a software bit to provide the functionality of the
CALTRIG input pin when there are no hardware resources to drive
CALTRIG. Program CAL_TRIG_EN=0 to use CAL_SOFT_TRIG for
the calibration trigger.
Note: If no calibration trigger is needed, leave CAL_TRIG_EN=0 and
CAL_SOFT_TRIG=1 (trigger set high).
7.6.24 CAL_LP Register (Address = 0x6E) [reset = 0x88]
CAL_LP is shown in 图7-40 and described in 表7-54.
Return to the Summary Table.
Low-Power Background Calibration (default: 0x88)
图7-40. CAL_LP Register
7
6
5
4
3
2
1
0
LP_SLEEP_DLY
R/W-0x4
LP_WAKE_DLY
R/W-0x1
RESERVED
R/W-0x0
LP_TRIG
R/W-0x0
LP_EN
R/W-0x0
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表7-54. CAL_LP Register Field Descriptions
Bit
Field
Type
Reset
Description
7:5
LP_SLEEP_DLY
R/W
0x4
These bits adjust how long an ADC sleeps before waking for
calibration (only applies when LP_EN = 1 and LP_TRIG = 0). Values
below 4 are not recommended because of limited overall power
reduction benefits.
0: Sleep delay = (23 + 1) × 256 × tCLK
1: Sleep delay = (215 + 1) × 256 × tCLK
2: Sleep delay = (218 + 1) × 256 × tCLK
3: Sleep delay = (221 + 1) × 256 × tCLK
4: Sleep delay = (224 + 1) × 256 × tCLK (default, approximately
1.338 seconds with a 3.2-GHz clock)
5: Sleep delay = (227 + 1) × 256 × tCLK
6: Sleep delay = (230 + 1) × 256 × tCLK
7: Sleep delay = (233 + 1) × 256 × tCLK
4:3
LP_WAKE_DLY
R/W
0x1
These bits adjust how much time is provided for settling before
calibrating an ADC after the ADC wakes up (only applies when
LP_EN = 1). Values lower than 1 are not recommended because
there is insufficient time for the core to stabilize before calibration
begins.
0: Wake delay = (23 + 1) × 256 × tCLK
1: Wake delay = (218 + 1) × 256 × tCLK (default, approximately 21
ms with a 3.2-GHz clock)
2: Wake delay = (221 + 1) × 256 × tCLK
3: Wake delay = (224 + 1) × 256 × tCLK
2
1
RESERVED
LP_TRIG
R/W
R/W
0x0
0x0
0 : ADC sleep duration is set by LP_SLEEP_DLY (autonomous
mode).
1 : ADCs sleep until awoken by a trigger. An ADC is awoken when
the calibration trigger is low.
0
LP_EN
R/W
0x0
0 : Disable low-power background calibration (default)
1 : Enable low-power background calibration (only applies when
CAL_BG=1).
7.6.25 CAL_DATA_EN Register (Address = 0x70) [reset = 0x00]
CAL_DATA_EN is shown in 图7-41 and described in 表7-55.
Return to the Summary Table.
Calibration Data Enable (default: 0x00)
图7-41. CAL_DATA_EN Register
7
6
5
4
3
2
1
0
RESERVED
R/W-0x0
CAL_DATA_EN
R/W-0x0
表7-55. CAL_DATA_EN Register Field Descriptions
Bit
7:1
Field
RESERVED
Type
Reset
Description
R/W
0x0
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表7-55. CAL_DATA_EN Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
0
CAL_DATA_EN
R/W
0x0
Set this bit to enable the CAL_DATA register to enable reading and
writing of calibration data; see the CAL_DATA register for more
information.
7.6.26 CAL_DATA Register (Address = 0x71) [reset = 0x0]
CAL_DATA is shown in 图7-42 and described in 表7-56.
Return to the Summary Table.
Calibration Data (default: undefined)
图7-42. CAL_DATA Register
7
6
5
4
3
2
1
0
CAL_DATA
R/W-0x0
表7-56. CAL_DATA Register Field Descriptions
Bit
7:0
Field
CAL_DATA
Type
Reset
Description
R/W
0x0
After setting CAL_DATA_EN, repeated reads of this register return all
calibration values for the ADCs. Repeated writes of this register input
all calibration values for the ADCs. To read the calibration data, read
the register 673 times. To write the vector, write the register 673
times with previously stored calibration data. To speed up the read or
write operation, set ADDR_HOLD = 1 and use streaming read or
write process.
IMPORTANT: Accessing the CAL_DATA register when
CAL_STOPPED = 0 corrupts the calibration. Also, stopping the
process before reading or writing 673 times leaves the calibration
data in an invalid state.
7.6.27 GAIN_TRIM_A Register (Address = 0x7A) [reset = 0x0]
GAIN_TRIM_A is shown in 图7-43 and described in 表7-57.
Return to the Summary Table.
Gain DAC Trim A (default from Fuse ROM)
图7-43. GAIN_TRIM_A Register
7
6
5
4
3
2
1
0
GAIN_TRIM_A
R/W-0x0
表7-57. GAIN_TRIM_A Register Field Descriptions
Bit
7:0
Field
GAIN_TRIM_A
Type
Reset
Description
R/W
0x0
This register enables gain trim of INA±. After reset, the factory
trimmed value can be read and adjusted as required. Use
FS_RANGE_A to adjust the analog full-scale voltage (Vfs) of INA±.
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7.6.28 GAIN_TRIM_B Register (Address = 0x7B) [reset = 0x0]
GAIN_TRIM_B is shown in 图7-44 and described in 表7-58.
Return to the Summary Table.
Gain DAC Trim B (default from Fuse ROM)
图7-44. GAIN_TRIM_B Register
7
6
5
4
3
2
1
0
GAIN_TRIM_B
R/W-0x0
表7-58. GAIN_TRIM_B Register Field Descriptions
Bit
7:0
Field
GAIN_TRIM_B
Type
Reset
Description
R/W
0x0
This register enables gain trim of INB±. After reset, the factory
trimmed value can be read and adjusted as required. Use
FS_RANGE_B to adjust the analog full-scale voltage (Vfs) of INB±.
7.6.29 BG_TRIM Register (Address = 0x7C) [reset = 0x0]
BG_TRIM is shown in 图7-45 and described in 表7-59.
Return to the Summary Table.
Band-Gap Trim (default from Fuse ROM)
图7-45. BG_TRIM Register
7
6
5
4
3
2
1
0
RESERVED
R/W-0x0
BG_TRIM
R/W-0x0
表7-59. BG_TRIM Register Field Descriptions
Bit
Field
Type
R/W
R/W
Reset
Description
7:4
3:0
RESERVED
BG_TRIM
0x0
0x0
This register enables trimming of the internal band-gap reference.
After reset, the factory trimmed value can be read and adjusted as
required.
7.6.30 RTRIM_A Register (Address = 0x7E) [reset = 0x0]
RTRIM_A is shown in 图7-46 and described in 表7-60.
Return to the Summary Table.
Resistor Trim for VinA (default from Fuse ROM)
图7-46. RTRIM_A Register
7
6
5
4
3
2
1
0
RTRIM_A
R/W-0x0
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表7-60. RTRIM_A Register Field Descriptions
Bit
Field
RTRIM_A
Type
Reset
Description
7:0
R/W
0x0
This register controls the INA± ADC input termination trim. After
reset, the factory trimmed value can be read and adjusted as
required.
7.6.31 RTRIM_B Register (Address = 0x7F) [reset = 0x0]
RTRIM_B is shown in 图7-47 and described in 表7-61.
Return to the Summary Table.
Resistor Trim for VinB (default from Fuse ROM)
图7-47. RTRIM_B Register
7
6
5
4
3
2
1
0
RTRIM_B
R/W-0x0
表7-61. RTRIM_B Register Field Descriptions
Bit
7:0
Field
Type
Reset
Description
RTRIM_B
R/W
0x0
This register controls the INB± ADC input termination trim. After
reset, the factory trimmed value can be read and adjusted as
required.
7.6.32 ADC_DITH Register (Address = 0x9D) [reset = 0x01]
ADC_DITH is shown in 图7-48 and described in 表7-62.
Return to the Summary Table.
ADC Dither Control (default from Fuse ROM)
图7-48. ADC_DITH Register
7
6
5
4
3
2
1
0
RESERVED
ADC_DITH_ER ADC_DITH_AM ADC_DITH_EN
R
P
R/W-0x0
R/W-0x0
R/W-0x0
R/W-0x1
表7-62. ADC_DITH Register Field Descriptions
Bit
Field
Type
R/W
R/W
Reset
Description
7:3
2
RESERVED
0x0
ADC_DITH_ERR
0x0
Small rounding errors may occur when subtracting the dither signal.
The error can be chosen to either slightly degrade SNR or to slightly
increase the DC offset and FS/2 spur. In addition, the FS/4 spur will
also be increased slightly while in single channel mode.
0 : Rounding error degrades SNR
1 : Rounding error degrades DC offset, FS/2 spur and FS/4 spur
1
ADC_DITH_AMP
R/W
0x0
0 : Small dither for better SNR (default)
1 : Large dither for better spurious performance
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表7-62. ADC_DITH Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
0
ADC_DITH_EN
R/W
0x1
Set this bit to enable ADC dither. Dither can improve spurious
performance at the expense of slightly degraded SNR. The dither
amplitude (ADC_DITH_AMP) can be used to further tradeoff SNR
and spurious performance.
7.6.33 LSB_CTRL Register (Address = 0x160) [reset = 0x00]
LSB_CTRL is shown in 图7-49 and described in 表7-63.
Return to the Summary Table.
LSB Control Bit Output (default: 0x00)
图7-49. LSB_CTRL Register
7
6
5
4
3
2
1
0
RESERVED
TIME_STAMP_
EN
R/W-0x0
R/W-0x0
表7-63. LSB_CTRL Register Field Descriptions
Bit
Field
Type
R/W
R/W
Reset
Description
7:1
0
RESERVED
0x0
TIME_STAMP_EN
0x0
When set, the timestamp signal is transmitted on the LSB of the
output samples. The latency of the timestamp signal (through the
entire chip) matches the latency of the analog ADC inputs. Also set
SYNC_RECV_EN when using TIME_STAMP_EN.
Note 1: The control bit is placed on the LSB of the 8-bit samples
(leaving 7-bits of sample data).
Note 2: The control bit that is enabled by this register is never
advertised in the ILA (CS is 0 in the ILA).
7.6.34 JESD_EN Register (Address = 0x200) [reset = 0x01]
JESD_EN is shown in 图7-50 and described in 表7-64.
Return to the Summary Table.
JESD204C Subsystem Enable (default: 0x01)
图7-50. JESD_EN Register
7
6
5
4
3
2
1
0
RESERVED
R/W-0x0
JESD_EN
R/W-0x1
表7-64. JESD_EN Register Field Descriptions
Bit
7:1
Field
RESERVED
Type
Reset
Description
R/W
0x0
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表7-64. JESD_EN Register Field Descriptions (continued)
Bit
Field
JESD_EN
Type
Reset
Description
0
R/W
0x1
0 : Disable JESD204C interface
1 : Enable JESD204C interface
Note: Before altering other JESD204C registers, you must clear
JESD_EN. When JESD_EN is 0, the block is held in reset and the
serializers are powered down. The clocks are gated off to save
power. The LMFC/LEMC counter is also held in reset, so SYSREF
will not align the LMFC/LEMC.
Note 2: Always set CAL_EN before setting JESD_EN.
Note 3: Always clear JESD_EN before clearing CAL_EN.
7.6.35 JMODE Register (Address = 0x201) [reset = 0x02]
JMODE is shown in 图7-51 and described in 表7-65.
Return to the Summary Table.
JESD204C Mode (default: 0x02)
图7-51. JMODE Register
7
6
5
4
3
2
1
0
RW
表7-65. JMODE Register Field Descriptions
Bit
7:0
Field
Type
Reset
Description
JMODE
RW
0x02
Specify the JESD204C Modes (including DDC decimation factor)
Note 1: This register should only be changed when JESD_EN=0 and
CAL_EN=0.
Note 2: The MODE_LOCK register determines which modes are
allowed.
7.6.36 KM1 Register (Address = 0x202) [reset = 0x1F]
KM1 is shown in 图7-52 and described in 表7-66.
Return to the Summary Table.
JESD204C K Parameter (default: 0x1F)
图7-52. KM1 Register
7
6
5
4
3
2
1
0
KM1
R/W-0x1F
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表7-66. KM1 Register Field Descriptions
Bit
Field
Type
Reset
Description
7:0
KM1
R/W
0x1F
K is the number of frames per multiframe and this register must be
programmed as K-1. Depending on the JMODE setting, there are
constraints on the legal values of K (see KR).
The default values is KM1=31, which corresponds to K=32.
Note: For modes using the 64b/66b link layer, the KM1 register is
ignored and the value of K is determined from JMODE. The effective
value of K is 256*E/F.
Note: This register should only be changed when JESD_EN is 0.
7.6.37 JSYNC_N Register (Address = 0x203) [reset = 0x01]
JSYNC_N is shown in 图7-53 and described in 表7-67.
Return to the Summary Table.
JESD204C Manual Sync Request (default: 0x01)
图7-53. JSYNC_N Register
7
6
5
4
3
2
1
0
RESERVED
R/W-0x0
JSYNC_N
R/W-0x1
表7-67. JSYNC_N Register Field Descriptions
Bit
Field
Type
R/W
R/W
Reset
Description
7:1
0
RESERVED
JSYNC_N
0x0
0x1
Set this bit to 0 to request JESD204C synchronization (equivalent to
the SYNC~ signal being asserted). For normal operation, leave this
bit set to 1.
Note: The JSYNC_N register can always generate a synchronization
request, regardless of the SYNC_SEL register. However, if the
selected sync pin is stuck low, you cannot de-assert the
synchronization request unless you program SYNC_SEL=2.
7.6.38 JCTRL Register (Address = 0x204) [reset = 0x03]
JCTRL is shown in 图7-54 and described in 表7-68.
Return to the Summary Table.
JESD204C Control (default: 0x03)
图7-54. JCTRL Register
7
6
5
4
3
2
1
0
RESERVED
R/W-0x0
ALT_LANES
R/W-0x0
SYNC_SEL
R/W-0x0
SFORMAT
R/W-0x1
SCR
R/W-0x1
表7-68. JCTRL Register Field Descriptions
Bit
7:5
Field
RESERVED
Type
Reset
Description
R/W
0x0
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表7-68. JCTRL Register Field Descriptions (continued)
Bit
Field
ALT_LANES
Type
Reset
Description
4
R/W
0x0
0 : Normal lane mapping (default). Link A uses lanes DA0 to DA3
and link B uses lanes DB0 to DB3. Other lanes are powered down.
1 : Alternate lane mapping (use upper lanes). Link A uses lanes DA4
to DA7 and link B uses lanes DB4 to DB7. Lanes DA0 to DA3 and
DB0 to DB3 are powered down.
Note: This option is only supported when JMODE selects a mode
that uses 8 or less lanes. The behavior is undefined for modes that
do not meet this requirement.
3:2
SYNC_SEL
R/W
0x0
0 : Use the SYNCSE input for SYNC~ function (default)
1 : Use the TMSTP input for SYNC~ function. TMSTP_RECV_EN
must also be set.
2 : Do not use any sync input pin (use software SYNC~ through
JSYNC_N)
1
0
SFORMAT
SCR
R/W
R/W
0x1
0x1
Output sample format for JESD204C samples
0 : Offset binary
1 : Signed 2’s complement (default)
0 : 8B/10B Scrambler disabled (applies only to 8B/10B modes)
1 : 8b/10b Scrambler enabled (default)
Note 1: 64B/66B modes always use scrambling. This register does
not apply to 64B/66B modes.
Note 2: This register should only be changed when JESD_EN is 0.
7.6.39 JTEST Register (Address = 0x205) [reset = 0x00]
JTEST is shown in 图7-55 and described in 表7-69.
Return to the Summary Table.
JESD204C Test Control (default: 0x00)
图7-55. JTEST Register
7
6
5
4
3
2
1
0
RESERVED
R/W-0x0
JTEST
R/W-0x0
表7-69. JTEST Register Field Descriptions
Bit
7:5
Field
RESERVED
Type
Reset
Description
R/W
0x0
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表7-69. JTEST Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
4:0
JTEST
R/W
0x0
0 : Test mode disabled. Normal operation (default)
1 : PRBS7 test mode
2 : PRBS15 test mode
3 : PRBS23 test mode
4 : Ramp test mode
5 : Transport Layer test mode
6 : D21.5 test mode
7 : K28.5 test mode*
8 : Repeated ILA test mode*
9 : Modified RPAT test mode*
10: Serial outputs held low
11: Serial outputs held high
12: RESERVED
13: PRBS9 test mode
14: PRBS31 test mode
15: Clock test pattern (0x00FF)
16: K28.7 test mode*
17-31: RESERVED
* These test modes are only supported when JMODE is selecting a
mode that uses 8b/10b encoding.
Note: This register should only be changed when JESD_EN is 0.
7.6.40 DID Register (Address = 0x206) [reset = 0x00]
DID is shown in 图7-56 and described in 表7-70.
Return to the Summary Table.
JESD204C DID Parameter (default: 0x00)
图7-56. DID Register
7
6
5
4
3
2
1
0
DID
R/W-0x0
表7-70. DID Register Field Descriptions
Bit
7:0
Field
Type
Reset
Description
DID
R/W
0x0
Specifies the DID (Device ID) value that is transmitted during the
second multiframe of the JESD204B ILA. Link A will transmit DID,
and link B will transmit DID+1. Bit 0 is ignored and always returns 0
(if you program an odd number, it will be decremented to an even
number).
Note: This register should only be changed when JESD_EN is 0.
7.6.41 FCHAR Register (Address = 0x207) [reset = 0x00]
FCHAR is shown in 图7-57 and described in 表7-71.
Return to the Summary Table.
JESD204C Frame Character (default: 0x00)
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图7-57. FCHAR Register
7
6
5
4
3
2
1
0
RESERVED
R/W-0x0
FCHAR
R/W-0x0
表7-71. FCHAR Register Field Descriptions
Bit
7:2
1:0
Field
Type
R/W
R/W
Reset
Description
RESERVED
FCHAR
0x0
0x0
Specify which comma character is used to denote end-of-frame. This
character is transmitted opportunistically. This only applies to modes
that use 8B/10B encoding.
0 : Use K28.7 (default) (JESD204C compliant)
1 : Use K28.1 (not JESD204C compliant)
2 : Use K28.5 (not JESD204C compliant)
3 : Reserved
When using a JESD204C receiver, always use FCHAR=0.
When using a general purpose 8B/10B receiver, the K28.7 character
may cause issues. When K28.7 is combined with certain data
characters, a false, misaligned comma character can result, and
some receivers will re-align to the false comma. To avoid this,
program FCHAR to 1 or 2.
Note: This register should only be changed when JESD_EN is 0.
7.6.42 JESD_STATUS Register (Address = 0x208) [reset = 0x0]
JESD_STATUS is shown in 图7-58 and described in 表7-72.
Return to the Summary Table.
JESD204C / System Status Register
图7-58. JESD_STATUS Register
7
6
5
4
3
2
1
0
RESERVED
R/W-0x0
LINK_UP
R/W-0x0
SYNC_STATUS REALIGNED
R/W-0x0 R/W-0x0
ALIGNED
R/W-0x0
PLL_LOCKED
R/W-0x0
RESERVED
R/W-0x0
表7-72. JESD_STATUS Register Field Descriptions
Bit
7
Field
RESERVED
Type
R/W
R/W
Reset
Description
0x0
6
LINK_UP
0x0
When set, indicates that the JESD204C link is up.
5
4
3
SYNC_STATUS
R/W
R/W
R/W
0x0
0x0
0x0
Returns the state of the JESD204C SYNC~ signal.
0 : SYNC~ asserted
1 : SYNC~ de-asserted
REALIGNED
ALIGNED
When high, indicates that the digital block clock, frame clock, or
multiframe (LMFC) clock phase was realigned by SYSREF. Writing a
1 to this bit will clear it.
When high, indicates that the multiframe (LMFC) clock phase has
been established by SYSREF. The first SYSREF event after enabling
the JESD204B encoder will set this bit. Writing a 1 to this bit will clear
it.
2
PLL_LOCKED
R/W
0x0
When high, indicates that the serializer PLL is locked.
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表7-72. JESD_STATUS Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
1:0
RESERVED
R/W
0x0
7.6.43 PD_CH Register (Address = 0x209) [reset = 0x00]
PD_CH is shown in 图7-59 and described in 表7-73.
Return to the Summary Table.
JESD204C Channel Power Down (default: 0x00)
图7-59. PD_CH Register
7
6
5
4
3
2
1
0
RESERVED
R/W-0x0
PD_BCH
R/W-0x0
PD_ACH
R/W-0x0
表7-73. PD_CH Register Field Descriptions
Bit
Field
Type
R/W
R/W
Reset
Description
7:2
1
RESERVED
PD_BCH
0x0
0x0
When set, the “B”ADC channel is powered down. The digital
channels that are bound to the “B”ADC channel are also powered
down (see DIG_BIND).
Important notes:
1. You must set JESD_EN=0 before changing PD_CH.
2. To power down both ADC channels, use the MODE register.
3. If both channels are powered down, then the entire JESD204C
subsystem is powered down, including serializer PLL and LMFC.
4. If the selected JESD204C mode transmits A and B data on link A,
and the B digital channel is disabled, link A remains operational, but
the B-channel samples are undefined. For proper operation in
foreground calibration mode, ADC_OFF in the CAL_CFG register
should be programmed to 0x1.
0
PD_ACH
R/W
0x0
When set, the “A”ADC channel is powered down. The digital
channels that are bound to the “A”ADC channel are also powered
down (see DIG_BIND).
Important notes:
1. You must set JESD_EN=0 before changing PD_CH.
2. To power down both ADC channels, use the MODE register.
3. If both channels are powered down, then the entire JESD204C
subsystem is powered down, including serializer PLL and LMFC.
4. If the selected JESD204C mode transmits A and B data on link A,
and the B digital channel is disabled, link A remains operational, but
the B-channel samples are undefined. For proper operation in
foreground calibration mode, ADC_OFF in the CAL_CFG register
should be programmed to 0x1.
7.6.44 JEXTRA_A Register (Address = 0x20A) [reset = 0x00]
JEXTRA_A is shown in 图7-60 and described in 表7-74.
Return to the Summary Table.
JESD204C Extra Lane Enable (Link A) (default: 0x00)
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图7-60. JEXTRA_A Register
7
6
5
4
3
2
1
0
EXTRA_LANE_A
R/W-0x0
EXTRA_SER_A
R/W-0x0
表7-74. JEXTRA_A Register Field Descriptions
Bit
Field
Type
Reset
Description
7:1
EXTRA_LANE_A
R/W
0x0
Program these register bits to enable extra lanes (even if the
selected JMODE does not require the lanes to be enabled).
EXTRA_LANE_A(n) enables An (n=1 to 7). This register enables the
link layer clocks for the affected lanes. To also enable the extra
serializes set EXTRA_SER_A=1.
0
EXTRA_SER_A
R/W
0x0
0 : Only the link layer clocks for extra lanes are enabled.
1 : Serializers for extra lanes are enabled (as well as link layer
clocks). Use this mode to transmit data from the extra lanes.
Important Notes:
1. This register should only be changed when JESD_EN is 0.
2. The bit-rate and mode of the extra lanes are set by JMODE and
JTEST (see exception below).
3. If a lane is enabled by this register (and was not enabled by
JMODE), and JTEST is 0 or 5, the extra lanes will use an octet ramp
(same as JTEST=4).
4. This register does not override the PD_CH register, so make sure
the link is enabled to use this feature.
5. To enable serializer 'n', the lower number lanes 0 to n-1 must also
be enabled, otherwise serializer 'n' will not receive a clock.
7.6.45 JEXTRA_B Register (Address = 0x20B) [reset = 0x00]
JEXTRA_B is shown in 图7-61 and described in 表7-75.
Return to the Summary Table.
JESD204C Extra Lane Enable (Link B) (default: 0x00)
图7-61. JEXTRA_B Register
7
6
5
4
3
2
1
0
EXTRA_LANE_B
R/W-0x0
EXTRA_SER_B
R/W-0x0
表7-75. JEXTRA_B Register Field Descriptions
Bit
7:1
Field
EXTRA_LANE_B
Type
Reset
Description
R/W
0x0
Program these register bits to enable extra lanes (even if the
selected JMODE does not require the lanes to be enabled).
EXTRA_LANE_B(n) enables Bn (n=1 to 7). This register enables the
link layer clocks for the affected lanes. To also enable the extra
serializes set EXTRA_SER_B=1.
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表7-75. JEXTRA_B Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
0
EXTRA_SER_B
R/W
0x0
0 : Only the link layer clocks for extra lanes are enabled.
1 : Serializers for extra lanes are enabled (as well as link layer
clocks). Use this mode to transmit data from the extra lanes.
Important Notes:
1. This register should only be changed when JESD_EN is 0.
2. The bit-rate and mode of the extra lanes are set by JMODE and
JTEST (see exception below).
3. If a lane is enabled by this register (and was not enabled by
JMODE), and JTEST is 0 or 5, the extra lanes will use an octet ramp
(same as JTEST=4).
4. This register does not override the PD_CH register, so make sure
that the link is enabled to use this feature.
5. To enable serializer 'n', the lower number lanes 0 to n-1 must also
be enabled, otherwise serializer 'n' will not receive a clock.
7.6.46 SHMODE Register (Address = 0x20F) [reset = 0x00]
SHMODE is shown in 图7-62 and described in 表7-76.
Return to the Summary Table.
JESD204C Sync Word Mode (default: 0x00)
图7-62. SHMODE Register
7
6
5
4
3
2
1
0
RESERVED
R/W-0x0
SHMODE
R/W-0x0
表7-76. SHMODE Register Field Descriptions
Bit
Field
Type
R/W
R/W
Reset
Description
7:2
1:0
RESERVED
SHMODE
0x0
0x0
Select the mode for the 64b/66b sync word (32 bits of data per multi-
block). This only applies when JMODE is selecting a 64b/66b mode.
0 : Transmit CRC-12 signal (default setting)
1 : RESERVED
2 : Transmit FEC signal
3 : RESERVED
Note: This device does not support any JESD204C command
features. All command fields will be set to zero (idle headers).
Note: This register should only be changed when JESD_EN is 0.
7.6.47 OVR_T0 Register (Address = 0x211) [reset = 0xF2]
OVR_T0 is shown in 图7-63 and described in 表7-77.
Return to the Summary Table.
Over-range Threshold 0 (default: 0xF2)
图7-63. OVR_T0 Register
7
6
5
4
3
2
1
0
OVR_T0
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图7-63. OVR_T0 Register (continued)
R/W-0xF2
表7-77. OVR_T0 Register Field Descriptions
Bit
Field
OVR_T0
Type
Reset
Description
7:0
R/W
0xF2
This parameter defines the absolute sample level that causes control
bit 0 to be set. The detection level in dBFS (peak) is
20log10(OVR_T0/256) (Default: 0xF2 = 242-> -0.5dBFS)
7.6.48 OVR_T1 Register (Address = 0x212) [reset = 0xAB]
OVR_T1 is shown in 图7-64 and described in 表7-78.
Return to the Summary Table.
Over-range Threshold 1 (default: 0xAB)
图7-64. OVR_T1 Register
7
6
5
4
3
2
1
0
OVR_T1
R/W-0xAB
表7-78. OVR_T1 Register Field Descriptions
Bit
7:0
Field
Type
Reset
Description
OVR_T1
R/W
0xAB
This parameter defines the absolute sample level that causes control
bit 1 to be set. The detection level in dBFS (peak) is
20log10(OVR_T1/256) (Default: 0xAB = 171 -> -3.5dBFS)
7.6.49 OVR_CFG Register (Address = 0x213) [reset = 0x07]
OVR_CFG is shown in 图7-65 and described in 表7-79.
Return to the Summary Table.
Over-range Enable / Hold Off (default: 0x07)
图7-65. OVR_CFG Register
7
6
5
4
3
2
1
0
RESERVED
R/W-0x0
OVR_EN
R/W-0x0
OVR_N
R/W-0x7
表7-79. OVR_CFG Register Field Descriptions
Bit
Field
Type
R/W
R/W
Reset
Description
7:4
3
RESERVED
OVR_EN
0x0
0x0
Enables over-range status output pins when set high. The ORA0,
ORA1, ORB0 and ORB1 outputs are held low when OVR_EN is set
low. This register only affects the over-range output pins (ORxx).
JESD204C modes that transmit over-range bits are not affected by
this register.
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表7-79. OVR_CFG Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
2:0
OVR_N
R/W
0x7
Program this register to adjust the pulse extension for the ORA0/1
and ORB0/1 outputs. The minimum pulse duration of the over-range
outputs is 8 * 2OVR_N DEVCLK cycles. Incrementing this field doubles
the monitoring period.
7.6.50 INIT_STATUS Register (Address = 0x270) [reset = undefined]
INIT_STATUS is shown in 图7-66 and described in 表7-80.
Return to the Summary Table.
Chip Spin Identifier (default: See description, read-only)
图7-66. INIT_STATUS Register
7
6
5
4
3
2
1
0
RESERVED
R-undefined
INIT_STATUS
R-undefined
表7-80. INIT_STATUS Register Field Descriptions
Bit
Field
Type
Reset
Description
7:1
0
RESERVED
INIT_DONE
R
undefined
undefined
RESERVED
R
Returns 1 when the initialization logic has finished initializing the
device. This indicates that it is now safe to proceed with startup. No
SPI transactions should be performed before INIT_DONE returns
1(except SOFT_RESET).
7.6.51 SPIN_ID Register (Address = 0x297) [reset = 0x0A]
SPIN_ID is shown in 图7-67 and described in 表7-81.
Return to the Summary Table.
Chip Spin Identifier (default: See description, read-only)
图7-67. SPIN_ID Register
7
6
5
4
3
2
1
0
RESERVED
R/W-0x0
SPIN_ID
R/W-0x0A
表7-81. SPIN_ID Register Field Descriptions
Bit
Field
Type
R/W
R/W
Reset
Description
7:5
4:0
RESERVED
SPIN_ID
0x0
0xA
Spin identification value:
0: ADC12DJ5200RF
2 : ADC12DJ4000RF
10: ADC08DJ5200RF
7.6.52 TESTBUS Register (Address = 0x2A2) [reset = 0x0]
TESTBUS is shown in 图7-68 and described in 表7-82.
Return to the Summary Table.
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TESTBUS Register (default: 0x0)
图7-68. TESTBUS Register
7
6
5
4
3
2
1
0
RESERVED
R/W-0x0
EN_VD11_NOI EN_VS11_NOI
RESERVED
R/W-0x0
SE_SUPPR
SE_SUPPR
R/W-0x0
R/W-0x0
表7-82. TESTBUS Register Field Descriptions
Bit
Field
Type
Reset
Description
7:6
5
RESERVED
R/W
0x0
RESERVED
EN_VD11_NOISE_SUPP R/W
R
0x0
When set, noise on VD11 is suppressed. It is recommended to have
this set, as it reduces noise coupling from the digital circuits to
analog clock, at the expense of a small increase in power.
4
EN_VS11_NOISE_SUPP R/W
R
When set, noise on VS11 is suppressed. It is recommended to have
this set, as it reduces noise coupling from the digital circuits to
analog clock, at the expense of a small increase in power.
3:0
RESERVED
R/W
R/W
RESERVED
7.6.53 SRC_EN Register (Address = 0x2B0) [reset = 0x00]
SRC_EN is shown in 图7-69 and described in 表7-83.
Return to the Summary Table.
SYSREF Calibration Enable (default: 0x00)
图7-69. SRC_EN Register
7
6
5
4
3
2
1
0
RESERVED
R/W-0x0
SRC_EN
R/W-0x0
表7-83. SRC_EN Register Field Descriptions
Bit
Field
Type
R/W
R/W
Reset
Description
7:1
0
RESERVED
SRC_EN
0x0
0x0
0: SYSREF Calibration Disabled. Use the TAD register to manually
control the tad[16:0] output and adjust the DEVCLK delay. (default)
1: SYSREF Calibration Enabled. The DEVCLK delay is automatically
calibrated. The TAD register is ignored.
A 0-to-1 transition on SRC_EN starts the SYSREF calibration
sequence. Program SRC_CFG before setting SRC_EN. Make sure
that ADC calibration is not currently running before setting SRC_EN.
7.6.54 SRC_CFG Register (Address = 0x2B1) [reset = 0x05]
SRC_CFG is shown in 图7-70 and described in 表7-84.
Return to the Summary Table.
SYSREF Calibration Configuration (default: 0x05)
图7-70. SRC_CFG Register
7
6
5
4
3
2
1
0
RESERVED
SRC_AVG
SRC_HDUR
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图7-70. SRC_CFG Register (continued)
R/W-0x0
R/W-0x1
R/W-0x1
表7-84. SRC_CFG Register Field Descriptions
Bit
7:4
3:2
Field
Type
R/W
R/W
Reset
Description
RESERVED
SRC_AVG
0x0
0x1
Specifies the amount of averaging used for SYSREF Calibration.
Larger values will increase calibration time and reduce the variance
of the calibrated value.
0: 4 averages
1: 16 averages
2: 64 averages
3: 256 averages
1:0
SRC_HDUR
R/W
0x1
Specifies the duration of each high-speed accumulation for SYSREF
Calibration. If the SYSREF period exceeds the supported value,
calibration will fail. Larger values will increase calibration time and
support longer SYSREF periods. For a given SYSREF period, larger
values will also reduce the variance of the calibrated value.
0: 4 cycles per accumulation, max SYSREF period of 128 DEVCLK
cycles
1: 16 cycles per accumulation, max SYSREF period of 1664
DEVCLK cycles
2: 64 cycles per accumulation, max SYSREF period of 7808
DEVCLK cycles
3: 256 cycles per accumulation, max SYSREF period of 32384
DEVCLK cycles
Max duration of SYSREF calibration is bounded by: TSYSREFCAL
(in DEVCLK cycles) = 384 * 19 * 4^(SRC_AVG + SRC_HDUR + 2)
7.6.55 SRC_STATUS Register (Address = 0x2B2) [reset = 0x0]
SRC_STATUS is shown in 图7-71 and described in 表7-85.
Return to the Summary Table.
SYSREF Calibration Status (read-only, default: undefined)
图7-71. SRC_STATUS Register
23
15
7
22
14
6
21
13
5
20
12
4
19
11
3
18
10
2
17
16
RESERVED
R/W-0x0
SRC_DONE
R/W-0x0
SRC_TAD
R/W-0x0
9
8
SRC_TAD
R/W-0x0
1
0
SRC_TAD
R/W-0x0
表7-85. SRC_STATUS Register Field Descriptions
Bit
23:18
Field
RESERVED
Type
Reset
Description
R/W
0x0
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表7-85. SRC_STATUS Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
17
SRC_DONE
R/W
0x0
This bit returns ‘1’when SRC_EN=1 and SYSREF Calibration
has been completed.
16:0
SRC_TAD
R/W
0x0
This field returns the value for TAD[16:0] computed by SYSREF
Calibration. It is only valid if SRC_DONE=1.
SRC_TAD[16] indicates if DEVCLK has been inverted.
SRC_TAD[15:8] indicates the coarse delay adjustment.
SRC_TAD[7:0] indicates the fine delay adjustment.
7.6.56 TAD Register (Address = 0x2B5) [reset = 0x00]
TAD is shown in 图7-72 and described in 表7-86.
Return to the Summary Table.
DEVCLK Timing Adjust (default: 0x00)
图7-72. TAD Register
23
15
7
22
14
6
21
13
5
20
19
18
10
2
17
9
16
RESERVED
R/W-0x0
TAD_INV
R/W-0x0
12
11
3
8
TAD_COARSE
R/W-0x0
4
1
0
TAD_FINE
R-0x0
表7-86. TAD Register Field Descriptions
Bit
Field
Type
R/W
R/W
Reset
Description
23:17
16
RESERVED
TAD_INV
0x0
0x0
Inverts the sampling clock when set.
15:8
TAD_COARSE
R/W
0x0
This register controls the coarse resolution of the sampling aperture
delay adjustment when SRC_EN=0. Use this register to manually
control the DEVCLK aperture delay when SYSREF Calibration is
disabled. If ADC calibration or JESD204B is running, it is
recommended that you gradually increase or decrease this value (1
code at a time) to avoid clock glitches. Refer to Switching
Characteristics for TAD_COARSE resolution.
If ADC calibration is enabled (CAL_EN=1), or the JESD204C link is
enabled (JESD_EN=1), the following rules must be obeyed to avoid
clock glitches and unpredictable behavior:
1. Do not change TAD_INV. You must program CAL_EN=0 and
JESD_EN=0 before changing TAD_INV.
2. TAD_COARSE must be increased or decreased gradually (no
more than 4 codes at a time). This rule can be obeyed manually via
SPI writes, or by setting TAD_RAMP_EN.
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表7-86. TAD Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
7:0
TAD_FINE
R/W
0x0
This register controls the fine resolution of the sampling aperture
delay adjustment when SRC_EN=0. Use this register to manually
control the DEVCLK aperture delay when SYSREF Calibration is
disabled. Refer to Switching Characteristics for TAD_FINE
resolution. TAD_FINE may be changed to any value at any time (its
adjustment is too fine to cause clock glitches).
7.6.57 TAD_RAMP Register (Address = 0x2B8) [reset = 0x00]
TAD_RAMP is shown in 图7-73 and described in 表7-87.
Return to the Summary Table.
DEVCLK Timing Adjust Ramp Control (default: 0x00)
图7-73. TAD_RAMP Register
7
6
5
4
3
2
1
0
RESERVED
R/W-0x0
TAD_RAMP_R TAD_RAMP_E
ATE
N
R/W-0x0
R/W-0x0
表7-87. TAD_RAMP Register Field Descriptions
Bit
Field
Type
R/W
R/W
Reset
Description
7:2
1
RESERVED
0x0
TAD_RAMP_RATE
0x0
Specifies the ramp rate for TAD_COARSE when the TAD_COARSE
register is written while TAD_RAMP_EN=1.
0: TAD_COARSE ramps up or down one code per 384 sampling
clock cycles.
1: TAD_COARSE ramps up or down 4 codes per 384 sampling clock
cycles.
0
TAD_RAMP_EN
R/W
0x0
TAD ramp enable. Set this bit if you want the coarse TAD adjustment
(TAD_COARSE) to ramp up or down instead of changing abruptly.
0 : After writing the TAD_COARSE register, the applied
TAD_COARSE setting is updated within 1536 CLK cycles (ramp
feature disabled).
1 : After writing the TAD_COARSE register, the applied
TAD_COARSE setting ramps up or down gradually until it matches
the TAD_COARSE register.
7.6.58 ALARM Register (Address = 0x2C0) [reset = 0x0]
ALARM is shown in 图7-74 and described in 表7-88.
Return to the Summary Table.
Alarm Interrupt (read-only)
图7-74. ALARM Register
7
6
5
4
3
2
1
0
RESERVED
R-0x0
ALARM
R-0x0
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表7-88. ALARM Register Field Descriptions
Bit
7:1
0
Field
Type
Reset
Description
RESERVED
ALARM
R
0x0
R
0x0
This bit returns a ‘1’whenever any alarm occurs that is
unmasked in the ALM_STATUS register. Use ALM_MASK to mask
(disable) individual alarms. CAL_STATUS_SEL can be used to drive
the ALARM bit onto the CALSTAT output pin to provide a hardware
alarm interrupt signal.
7.6.59 ALM_STATUS Register (Address = 0x2C1) [reset = 0x3F]
ALM_STATUS is shown in 图7-75 and described in 表7-89.
Return to the Summary Table.
Alarm Status (default: 0x3F, write to clear)
图7-75. ALM_STATUS Register
7
6
5
4
3
2
1
0
RESERVED
R/W-0x0
FIFO_ALM
PLL_ALM
LINK_ALM
REALIGNED_A
LM
NCO_ALM
CLK_ALM
R/W-0x1
R/W-0x1
R/W-0x1
R/W-0x1
R/W-0x1
R/W-0x1
表7-89. ALM_STATUS Register Field Descriptions
Bit
Field
Type
R/W
R/W
Reset
Description
7:6
5
RESERVED
FIFO_ALM
0x0
0x1
FIFO overflow/underflow alarm: This bit is set whenever an active
JESD204C lane FIFO experiences an underflow or overflow
condition. Write a ‘1’to clear this bit. To inspect which lane
generated the alarm, read FIFO_LANE_ALM.
4
3
PLL_ALM
R/W
R/W
0x1
0x1
PLL Lock Lost Alarm: This bit is set whenever the PLL is not locked.
Write a ‘1’to clear this bit.
LINK_ALM
Link Alarm: This bit is set whenever the JESD204C link is enabled,
but is not in the data encoder state (for 8B/10B modes). In 64B/66B
modes, there is no data encoder state, so this alarm will be set when
the link first starts up, and will also be set if any event causes a
FIFO/serializer realignment. Write a ‘1’to clear this bit.
2
REALIGNED_ALM
R/W
0x1
Realigned Alarm: This bit is set whenever SYSREF causes the
internal clocks (including the LMFC/LEMC) to be realigned. Write a
‘1’to clear this bit.
1
0
NCO_ALM
CLK_ALM
R/W
R/W
0x1
0x1
Not used for ADC08DJ5200RF.
Clock Alarm: This bit can be used to detect an upset to the internal
JESD204C clocks. This bit is set whenever the internal clock dividers
for the A and B channels do not match. Write a ‘1’to clear this bit.
Refer to the alarm section for the proper usage of this register.
Note: After power-on reset or soft-reset, all alarm bits are set to
‘1.’
Note: When JESD_EN=0, all alarms (except CLK_ALM) are
undefined. It is recommended that the user clears the alarms after
setting JESD_EN=1.
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7.6.60 ALM_MASK Register (Address = 0x2C2) [reset = 0x3F]
ALM_MASK is shown in 图7-76 and described in 表7-90.
Return to the Summary Table.
Alarm Mask Register (default: 0x3F)
图7-76. ALM_MASK Register
7
6
5
4
3
2
1
0
RESERVED
R/W-0x0
MASK_FIFO_A MASK_PLL_AL MASK_LINK_A MASK_REALIG MASK_NCO_A MASK_CLK_AL
LM
M
LM
NED_ALM
LM
M
R/W-0x1
R/W-0x1
R/W-0x1
R/W-0x1
R/W-0x1
R/W-0x1
表7-90. ALM_MASK Register Field Descriptions
Bit
Field
Type
R/W
R/W
Reset
Description
7:6
5
RESERVED
0x0
MASK_FIFO_ALM
0x1
When set, FIFO_ALM is masked and will not impact the ALARM
register bit.
4
3
2
MASK_PLL_ALM
MASK_LINK_ALM
R/W
R/W
0x1
0x1
0x1
When set, PLL_ALM is masked and will not impact the ALARM
register bit.
When set, LINK_ALM is masked and will not impact the ALARM
register bit.
MASK_REALIGNED_ALM R/W
When set, REALIGNED_ALM is masked and will not impact the
ALARM register bit.
1
0
MASK_NCO_ALM
MASK_CLK_ALM
R/W
R/W
0x1
0x1
Not used for ADC08DJ5200RF.
When set, CLK_ALM is masked and will not impact the ALARM
register bit.
7.6.61 FIFO_LANE_ALM Register (Address = 0x2C4) [reset = 0xFFFF]
FIFO_LANE_ALM is shown in 图7-77 and described in 表7-91.
Return to the Summary Table.
FIFO Overflow/Underflow Alarm (default: 0xFFFF)
图7-77. FIFO_LANE_ALM Register
15
7
14
6
13
5
12
FIFO_LANE_ALM
R/W-0xFFFF
11
10
2
9
1
8
0
4
3
FIFO_LANE_ALM
R/W-0xFFFF
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表7-91. FIFO_LANE_ALM Register Field Descriptions
Bit
Field
FIFO_LANE_ALM
Type
Reset
Description
15:0
R/W
0xFFFF
FIFO_LANE_ALM[i] is set if the FIFO for lane i experiences overflow
or underflow. Use this register to determine which lane(s) generated
an alarm. Writing a ‘1’to any bit in this register will clear the alarm
(the alarm may immediately trip again if the overflow/underflow
condition persists). Writing a ‘1’to the FIFO_ALM bit in the
ALM_STATUS register will clear all bits of this register.
7.6.62 TADJ_A Register (Address = 0x310) [reset = 0x0]
TADJ_A is shown in 图7-78 and described in 表7-92.
Return to the Summary Table.
Timing Adjust for A-ADC operating in Dual Channel Mode (default from Fuse ROM)
图7-78. TADJ_A Register
7
6
5
4
3
2
1
0
TADJ_A
R/W-0x0
表7-92. TADJ_A Register Field Descriptions
Bit
7:0
Field
Type
Reset
Description
TADJ_A
R/W
0x0
This register (and other TADJ* registers that follow it) are used to
adjust the sampling instant of each ADC core. Different TADJ
registers apply to different ADCs under different modes. The default
values for all TADJ* registers are factory programmed values. The
factory trimmed values can be read out and adjusted as required.
7.6.63 TADJ_B Register (Address = 0x313) [reset = 0x0]
TADJ_B is shown in 图7-79 and described in 表7-93.
Return to the Summary Table.
Timing Adjust for B-ADC operating in Dual Channel Mode (default from Fuse ROM)
图7-79. TADJ_B Register
7
6
5
4
3
2
1
0
TADJ_B
R/W-0x0
表7-93. TADJ_B Register Field Descriptions
Bit
7:0
Field
Type
Reset
Description
TADJ_B
R/W
0x0
See TADJ_A register for description. Adjusts timing of B-ADC in dual
channel mode with foreground calibration enabled.
7.6.64 TADJ_A_FG90_VINA Register (Address = 0x314) [reset = 0x0]
TADJ_A_FG90_VINA is shown in 图7-80 and described in 表7-94.
Return to the Summary Table.
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Timing Adjust for A-ADC operating in Single Channel Mode and sampling INA± (default from Fuse ROM)
图7-80. TADJ_A_FG90_VINA Register
7
6
5
4
3
2
1
0
TADJ_A_FG90_VINA
R/W-0x0
表7-94. TADJ_A_FG90_VINA Register Field Descriptions
Bit
7:0
Field
Type
Reset
Description
TADJ_A_FG90_VINA
R/W
0x0
See TADJ_A register for description. Adjusts timing of A-ADC in
single channel mode with foreground calibration enabled and
sampling INA±.
7.6.65 TADJ_B_FG0_VINA Register (Address = 0x315) [reset = 0x0]
TADJ_B_FG0_VINA is shown in 图7-81 and described in 表7-95.
Return to the Summary Table.
Timing Adjust for B-ADC operating in Single Channel Mode and sampling INA± (default from Fuse ROM)
图7-81. TADJ_B_FG0_VINA Register
7
6
5
4
3
2
1
0
TADJ_B_FG0_VINA
R/W-0x0
表7-95. TADJ_B_FG0_VINA Register Field Descriptions
Bit
7:0
Field
Type
Reset
Description
TADJ_B_FG0_VINA
R/W
0x0
See TADJ_A register for description. Adjusts timing of B-ADC in
single channel mode with foreground calibration enabled and
sampling INA±.
7.6.66 TADJ_A_FG90_VINB Register (Address = 0x31A) [reset = 0x0]
TADJ_A_FG90_VINB is shown in 图7-82 and described in 表7-96.
Return to the Summary Table.
Timing Adjust for A-ADC operating in Single Channel Mode and sampling INB± (default from Fuse ROM)
图7-82. TADJ_A_FG90_VINB Register
7
6
5
4
3
2
1
0
TADJ_A_FG90_VINB
R/W-0x0
表7-96. TADJ_A_FG90_VINB Register Field Descriptions
Bit
7:0
Field
Type
Reset
Description
TADJ_A_FG90_VINB
R/W
0x0
See TADJ_A register for description. Adjusts timing of A-ADC in
single channel mode with foreground calibration enabled and
sampling INB±.
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7.6.67 TADJ_B_FG0_VINB Register (Address = 0x31B) [reset = 0x0]
TADJ_B_FG0_VINB is shown in 图7-83 and described in 表7-97.
Return to the Summary Table.
Timing Adjust for B-ADC operating in Single Channel Mode and sampling INB± (default from Fuse ROM)
图7-83. TADJ_B_FG0_VINB Register
7
6
5
4
3
2
1
0
TADJ_B_FG0_VINB
R/W-0x0
表7-97. TADJ_B_FG0_VINB Register Field Descriptions
Bit
7:0
Field
Type
Reset
Description
TADJ_B_FG0_VINB
R/W
0x0
See TADJ_A register for description. Adjusts timing of B-ADC in
single channel mode with foreground calibration enabled and
sampling INB±.
7.6.68 OADJ_A_FG0_VINA Register (Address = 0x344) [reset = 0x0]
OADJ_A_FG0_VINA is shown in 图7-84 and described in 表7-98.
Return to the Summary Table.
Offset Adjustment for A-ADC operating in Dual Channel Mode sampling INA± (default from Fuse ROM)
图7-84. OADJ_A_FG0_VINA Register
15
7
14
6
13
5
12
11
10
9
8
0
RESERVED
R/W-0x0
OADJ_A_FG0_VINA
R/W-0x0
4
3
2
1
OADJ_A_FG0_VINA
R/W-0x0
表7-98. OADJ_A_FG0_VINA Register Field Descriptions
Bit
Field
Type
R/W
R/W
Reset
Description
15:12
11:0
RESERVED
0x0
OADJ_A_FG0_VINA
0x0
Offset adjustment value applied to A-ADC when it samples INA± in
dual channel mode and foreground calibration is enabled.
7.6.69 OADJ_A_FG0_VINB Register (Address = 0x346) [reset = 0x0]
OADJ_A_FG0_VINB is shown in 图7-85 and described in 表7-99.
Return to the Summary Table.
Offset Adjustment for A-ADC operating in Dual Channel Mode sampling INB± (default from Fuse ROM)
图7-85. OADJ_A_FG0_VINB Register
15
7
14
6
13
5
12
4
11
3
10
9
8
0
RESERVED
R/W-0x0
OADJ_A_FG_VINB
R/W-0x0
2
1
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图7-85. OADJ_A_FG0_VINB Register (continued)
OADJ_A_FG_VINB
R/W-0x0
表7-99. OADJ_A_FG0_VINB Register Field Descriptions
Bit
15:12
11:0
Field
Type
R/W
R/W
Reset
Description
RESERVED
OADJ_A_FG_VINB
0x0
0x0
Offset adjustment value applied to A-ADC when it samples INB± in
dual channel mode and foreground calibration is enabled.
7.6.70 OADJ_A_FG90_VINA Register (Address = 0x348) [reset = 0x0]
OADJ_A_FG90_VINA is shown in 图7-86 and described in 表7-100.
Return to the Summary Table.
Offset Adjustment for A-ADC operating in Single Channel Mode sampling INA± (default from Fuse ROM)
图7-86. OADJ_A_FG90_VINA Register
15
7
14
6
13
5
12
11
10
9
8
0
RESERVED
R/W-0x0
OADJ_A_FG90_VINA
R/W-0x0
4
3
2
1
OADJ_A_FG90_VINA
R/W-0x0
表7-100. OADJ_A_FG90_VINA Register Field Descriptions
Bit
Field
Type
R/W
R/W
Reset
Description
15:12
11:0
RESERVED
0x0
OADJ_A_FG90_VINA
0x0
Offset adjustment value applied to A-ADC when it samples INA± in
single channel mode and foreground calibration is enabled.
7.6.71 OADJ_A_FG90_VINB Register (Address = 0x34A) [reset = 0x0]
OADJ_A_FG90_VINB is shown in 图7-87 and described in 表7-101.
Return to the Summary Table.
Offset Adjustment for A-ADC operating in Single Channel Mode sampling INB± (default from Fuse ROM)
图7-87. OADJ_A_FG90_VINB Register
15
7
14
6
13
5
12
11
10
9
8
0
RESERVED
R/W-0x0
OADJ_A_FG90_VINB
R/W-0x0
4
3
2
1
OADJ_A_FG90_VINB
R/W-0x0
表7-101. OADJ_A_FG90_VINB Register Field Descriptions
Bit
15:12
Field
RESERVED
Type
Reset
Description
R/W
0x0
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表7-101. OADJ_A_FG90_VINB Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
11:0
OADJ_A_FG90_VINB
R/W
0x0
Offset adjustment value applied to A-ADC when it samples INB±
using 90° clock phase and foreground calibration is enabled.
7.6.72 OADJ_B_FG0_VINA Register (Address = 0x34C) [reset = 0x0]
OADJ_B_FG0_VINA is shown in 图7-88 and described in 表7-102.
Return to the Summary Table.
Offset Adjustment for B-ADC sampling INA± (default from Fuse ROM)
图7-88. OADJ_B_FG0_VINA Register
15
7
14
6
13
5
12
11
10
9
8
0
RESERVED
R/W-0x0
OADJ_B_FG0_VINA
R/W-0x0
4
3
2
1
OADJ_B_FG0_VINA
R/W-0x0
表7-102. OADJ_B_FG0_VINA Register Field Descriptions
Bit
Field
Type
R/W
R/W
Reset
Description
15:12
11:0
RESERVED
0x0
OADJ_B_FG0_VINA
0x0
Offset adjustment value applied to B-ADC when it samples INA± and
foreground calibration is enabled. Applies to both dual channel mode
and single channel mode.
7.6.73 OADJ_B_FG0_VINB Register (Address = 0x34E) [reset = 0x0]
OADJ_B_FG0_VINB is shown in 图7-89 and described in 表7-103.
Return to the Summary Table.
Offset Adjustment for B-ADC sampling INB± (default from Fuse ROM)
图7-89. OADJ_B_FG0_VINB Register
15
7
14
6
13
5
12
11
10
9
8
0
RESERVED
R/W-0x0
OADJ_B_FG0_VINB
R/W-0x0
4
3
2
1
OADJ_B_FG0_VINB
R/W-0x0
表7-103. OADJ_B_FG0_VINB Register Field Descriptions
Bit
Field
Type
R/W
R/W
Reset
Description
15:12
11:0
RESERVED
0x0
OADJ_B_FG0_VINB
0x0
Offset adjustment value applied to B-ADC when it samples INB± and
foreground calibration is enabled. Applies to both dual channel mode
and single channel mode.
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7.6.74 GAIN_A0_FGDUAL Register (Address = 0x350) [reset = 0x0]
GAIN_A0_FGDUAL is shown in 图7-90 and described in 表7-104.
Return to the Summary Table.
Fine Gain Adjust for ADC A Bank 0 in Dual Channel Mode (default from Fuse ROM)
图7-90. GAIN_A0_FGDUAL Register
7
6
5
4
3
2
1
1
1
0
RESERVED
R/W-0x0
GAIN_A0_FGDUAL
R/W-0x0
表7-104. GAIN_A0_FGDUAL Register Field Descriptions
Bit
Field
Type
R/W
R/W
Reset
Description
7:5
4:0
RESERVED
0x0
GAIN_A0_FGDUAL
0x0
Fine gain adjustment for ADC A bank 0.
7.6.75 GAIN_A1_FGDUAL Register (Address = 0x351) [reset = 0x0]
GAIN_A1_FGDUAL is shown in 图7-91 and described in 表7-105.
Return to the Summary Table.
Fine Gain Adjust for ADC A Bank 1 in Dual Channel Mode (default from Fuse ROM)
图7-91. GAIN_A1_FGDUAL Register
7
6
5
4
3
2
0
RESERVED
R/W-0x0
GAIN_A1_FGDUAL
R/W-0x0
表7-105. GAIN_A1_FGDUAL Register Field Descriptions
Bit
Field
Type
R/W
R/W
Reset
Description
7:5
4:0
RESERVED
0x0
GAIN_A1_FGDUAL
0x0
Fine gain adjustment for ADC A bank 1.
7.6.76 GAIN_B0_FGDUAL Register (Address = 0x352) [reset = 0x0]
GAIN_B0_FGDUAL is shown in 图7-92 and described in 表7-106.
Return to the Summary Table.
Fine Gain Adjust for ADC B Bank 0 in Dual Channel Mode (default from Fuse ROM)
图7-92. GAIN_B0_FGDUAL Register
7
6
5
4
3
2
0
RESERVED
R/W-0x0
GAIN_A0_FGDUAL
R/W-0x0
表7-106. GAIN_B0_FGDUAL Register Field Descriptions
Bit
Field
Type
R/W
R/W
Reset
Description
7:5
4:0
RESERVED
0x0
GAIN_A0_FGDUAL
0x0
Fine gain adjustment for ADC B bank 0.
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7.6.77 GAIN_B1_FGDUAL Register (Address = 0x353) [reset = 0x0]
GAIN_B1_FGDUAL is shown in 图7-93 and described in 表7-107.
Return to the Summary Table.
Fine Gain Adjust for ADC B Bank 1 in Dual Channel Mode (default from Fuse ROM)
图7-93. GAIN_B1_FGDUAL Register
7
6
5
4
3
2
1
1
1
0
0
0
RESERVED
R/W-0x0
GAIN_B1_FGDUAL
R/W-0x0
表7-107. GAIN_B1_FGDUAL Register Field Descriptions
Bit
Field
Type
R/W
R/W
Reset
Description
7:5
4:0
RESERVED
0x0
GAIN_B1_FGDUAL
0x0
Fine gain adjustment for ADC B bank 1.
7.6.78 GAIN_A0_FGDES Register (Address = 0x354) [reset = 0x0]
GAIN_A0_FGDES is shown in 图7-94 and described in 表7-108.
Return to the Summary Table.
Fine Gain Adjust for ADC A Bank 0 in Single Channel Mode (default from Fuse ROM)
图7-94. GAIN_A0_FGDES Register
7
6
5
4
3
2
RESERVED
R/W-0x0
GAIN_A0_FGDUAL
R/W-0x0
表7-108. GAIN_A0_FGDES Register Field Descriptions
Bit
Field
Type
R/W
R/W
Reset
Description
7:5
4:0
RESERVED
0x0
GAIN_A0_FGDUAL
0x0
Fine gain adjustment for ADC A bank 0.
7.6.79 GAIN_A1_FGDES Register (Address = 0x355) [reset = 0x0]
GAIN_A1_FGDES is shown in 图7-95 and described in 表7-109.
Return to the Summary Table.
Fine Gain Adjust for ADC A Bank 1 in Single Channel Mode (default from Fuse ROM)
图7-95. GAIN_A1_FGDES Register
7
6
5
4
3
2
RESERVED
R/W-0x0
GAIN_A1_FGDUAL
R/W-0x0
表7-109. GAIN_A1_FGDES Register Field Descriptions
Bit
Field
Type
R/W
R/W
Reset
Description
7:5
4:0
RESERVED
0x0
GAIN_A1_FGDUAL
0x0
Fine gain adjustment for ADC A bank 1.
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7.6.80 GAIN_B0_FGDES Register (Address = 0x356) [reset = 0x0]
GAIN_B0_FGDES is shown in 图7-96 and described in 表7-110.
Return to the Summary Table.
Fine Gain Adjust for ADC B Bank 0 in Single Channel Mode (default from Fuse ROM)
图7-96. GAIN_B0_FGDES Register
7
6
5
4
3
2
1
1
1
0
RESERVED
R/W-0x0
GAIN_A0_FGDUAL
R/W-0x0
表7-110. GAIN_B0_FGDES Register Field Descriptions
Bit
Field
Type
R/W
R/W
Reset
Description
7:5
4:0
RESERVED
0x0
GAIN_A0_FGDUAL
0x0
Fine gain adjustment for ADC B bank 0.
7.6.81 GAIN_B1_FGDES Register (Address = 0x357) [reset = 0x0]
GAIN_B1_FGDES is shown in 图7-97 and described in 表7-111.
Return to the Summary Table.
Fine Gain Adjust for ADC B Bank 1 in Single Channel Mode (default from Fuse ROM)
图7-97. GAIN_B1_FGDES Register
7
6
5
4
3
2
0
RESERVED
R/W-0x0
GAIN_B1_FGDUAL
R/W-0x0
表7-111. GAIN_B1_FGDES Register Field Descriptions
Bit
Field
Type
R/W
R/W
Reset
Description
7:5
4:0
RESERVED
0x0
GAIN_B1_FGDUAL
0x0
Fine gain adjustment for ADC B bank 1.
7.6.82 PFIR_CFG Register (Address = 0x400) [reset = 0x00]
PFIR_CFG is shown in 图7-98 and described in 表7-112.
Return to the Summary Table.
Programmable FIR Mode (default: 0x00)
图7-98. PFIR_CFG Register
7
6
5
4
3
2
0
RESERVED
R/W-0x0
PFIR_SHARE PFIR_MERGE
R/W-0x0 R/W-0x0
PFIR_SCW
R/W-0x0
PFIR_MODE
R/W-0x0
表7-112. PFIR_CFG Register Field Descriptions
Bit
Field
RESERVED
Type
Reset
Description
7
R/W
0x0
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表7-112. PFIR_CFG Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
6
PFIR_SHARE
PFIR_MERGE
PFIR_SCW
R/W
0x0
When set, the PFIR on the B channel uses the same coefficients as
the PFIR on the A channel. When PFIR_SHARE=0, the B channel
filter uses its own set of coefficients (unique from channel A). See
Programmable FIR Filter (PFIR) section for usage details.
5
R/W
R/W
0x0
0x0
When set, the PFIR filters are merged into a single logical filter. This
mode processes ADC data samples as if they belong to a single
sample stream. Set PFIR_MERGE=1 whenever the ADC is setup in
Single Channel Mode.
4:2
Side coefficient weight for PFIR. This field determines the weight of
the coefficients (except for the center coefficient). Increasing the
coefficient weight increases the range of the coefficients at the
expense of reduced precision. The LSB weight is 2PFIR_SCW-16
where PFIR_SCW weight can be programmed from 0 to 6. The
,
default is 0 which provides an LSB weight of 2-16
.
1:0
PFIR_MODE
R/W
0x0
0 : PFIR block is disabled (default)
1 : RESERVED
2 : Enable PFIR block
3 : RESERVED
Note: When using the PFIR, you must also program the filter
coefficients.
Note: All PFIR_* register should only be changed when JESD_EN=0.
7.6.83 PFIR_A0 Register (Address = 0x418) [reset = 0x0]
PFIR_A0 is shown in 图7-99 and described in 表7-113.
Return to the Summary Table.
PFIR Coefficient A0
图7-99. PFIR_A0 Register
15
7
14
6
13
5
12
11
10
2
9
1
8
0
RESERVED
R/W-0x0
PFIR_A0
R/W-0x0
4
3
PFIR_A0
R/W-0x0
表7-113. PFIR_A0 Register Field Descriptions
Bit
Field
Type
R/W
R/W
Reset
Description
15:12
11:0
RESERVED
PFIR_A0
0x0
0x0
Signed, 2’s complement coefficient for the PFIR filter. This is the
first tap for the ADC A programmable FIR filter in Dual Channel
Mode or the first tap for the programmable FIR filter in Single
Channel Mode.
7.6.84 PFIR_A1 Register (Address = 0x41A) [reset = 0x0]
PFIR_A1 is shown in 图7-100 and described in 表7-114.
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Return to the Summary Table.
PFIR Coefficient A1
图7-100. PFIR_A1 Register
15
14
13
5
12
11
10
2
9
1
8
0
RESERVED
R/W-0x0
PFIR_A1
R/W-0x0
7
6
4
3
PFIR_A1
R/W-0x0
表7-114. PFIR_A1 Register Field Descriptions
Bit
Field
Type
R/W
R/W
Reset
Description
15:12
11:0
RESERVED
PFIR_A1
0x0
0x0
Signed, 2’s complement coefficient for the PFIR filter. This is the
second tap for the ADC A programmable FIR filter in Dual Channel
Mode or the second tap for the programmable FIR filter in Single
Channel Mode.
7.6.85 PFIR_A2 Register (Address = 0x41C) [reset = 0x0]
PFIR_A2 is shown in 图7-101 and described in 表7-115.
Return to the Summary Table.
PFIR Coefficient A2
图7-101. PFIR_A2 Register
15
7
14
6
13
5
12
11
10
2
9
1
8
0
RESERVED
R/W-0x0
PFIR_A2
R/W-0x0
4
3
PFIR_A2
R/W-0x0
表7-115. PFIR_A2 Register Field Descriptions
Bit
Field
Type
R/W
R/W
Reset
Description
15:12
11:0
RESERVED
PFIR_A2
0x0
0x0
Signed, 2’s complement coefficient for the PFIR filter. This is the
third tap for the ADC A programmable FIR filter in Dual Channel
Mode or the third tap for the programmable FIR filter in Single
Channel Mode.
7.6.86 PFIR_A3 Register (Address = 0x41E) [reset = 0x0]
PFIR_A3 is shown in 图7-102 and described in 表7-116.
Return to the Summary Table.
PFIR Coefficient A3
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图7-102. PFIR_A3 Register
15
14
6
13
5
12
11
10
2
9
1
8
0
RESERVED
R/W-0x0
PFIR_A3
R/W-0x0
7
4
3
PFIR_A3
R/W-0x0
表7-116. PFIR_A3 Register Field Descriptions
Bit
15:12
11:0
Field
Type
R/W
R/W
Reset
Description
RESERVED
PFIR_A3
0x0
0x0
Signed, 2’s complement coefficient for the PFIR filter. This is the
fourth tap for the ADC A programmable FIR filter in Dual Channel
Mode or the fourth tap for the programmable FIR filter in Single
Channel Mode.
7.6.87 PFIR_A4 Register (Address = 0x420) [reset = 0x0]
PFIR_A4 is shown in 图7-103 and described in 表7-117.
Return to the Summary Table.
PFIR Coefficient A4
图7-103. PFIR_A4 Register
23
15
7
22
14
6
21
13
5
20
12
4
19
11
3
18
10
2
17
9
16
8
RESERVED
R/W-0x0
PFIR_A4
R/W-0x0
PFIR_A4
R/W-0x0
1
0
PFIR_A4
R/W-0x0
表7-117. PFIR_A4 Register Field Descriptions
Bit
Field
Type
R/W
R/W
Reset
Description
23:18
17:0
RESERVED
PFIR_A4
0x0
0x0
Signed, 2’s complement coefficient for the PFIR filter. This is the
fifth tap for the ADC A programmable FIR filter in Dual Channel
Mode or the fifth tap for the programmable FIR filter in Single
Channel Mode. This is the center tap of the 9-tap filter and therefore
has a resolution of 18-bits.
7.6.88 PFIR_A5 Register (Address = 0x423) [reset = 0x0]
PFIR_A5 is shown in 图7-104 and described in 表7-118.
Return to the Summary Table.
PFIR Coefficient A5
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图7-104. PFIR_A5 Register
15
7
14
6
13
5
12
11
10
2
9
1
8
RESERVED
R/W-0x0
PFIR_A5
R/W-0x0
4
3
0
PFIR_A5
R/W-0x0
表7-118. PFIR_A5 Register Field Descriptions
Bit
Field
Type
R/W
R/W
Reset
Description
15:12
11:0
RESERVED
PFIR_A5
0x0
0x0
Signed, 2’s complement coefficient for the PFIR filter. This is the
sixth tap for the ADC A programmable FIR filter in Dual Channel
Mode or the sixth tap for the programmable FIR filter in Single
Channel Mode.
7.6.89 PFIR_A6 Register (Address = 0x425) [reset = 0x0]
PFIR_A6 is shown in 图7-105 and described in 表7-119.
Return to the Summary Table.
PFIR Coefficient A6
图7-105. PFIR_A6 Register
15
7
14
6
13
5
12
11
10
2
9
1
8
0
RESERVED
R/W-0x0
PFIR_A6
R/W-0x0
4
3
PFIR_A6
R/W-0x0
表7-119. PFIR_A6 Register Field Descriptions
Bit
Field
Type
R/W
R/W
Reset
Description
15:12
11:0
RESERVED
PFIR_A6
0x0
0x0
Signed, 2’s complement coefficient for the PFIR filter. This is the
seventh tap for the ADC A programmable FIR filter in Dual Channel
Mode or the seventh tap for the programmable FIR filter in Single
Channel Mode.
7.6.90 PFIR_A7 Register (Address = 0x427) [reset = 0x0]
PFIR_A7 is shown in 图7-106 and described in 表7-120.
Return to the Summary Table.
PFIR Coefficient A7
图7-106. PFIR_A7 Register
15
14
13
12
11
10
9
8
RESERVED
R/W-0x0
PFIR_A7
R/W-0x0
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图7-106. PFIR_A7 Register (continued)
7
6
5
4
3
2
1
0
PFIR_A7
R/W-0x0
表7-120. PFIR_A7 Register Field Descriptions
Bit
15:12
11:0
Field
Type
R/W
R/W
Reset
Description
RESERVED
PFIR_A7
0x0
0x0
Signed, 2’s complement coefficient for the PFIR filter. This is the
eighth tap for the ADC A programmable FIR filter in Dual Channel
Mode or the eighth tap for the programmable FIR filter in Single
Channel Mode.
7.6.91 PFIR_A8 Register (Address = 0x429) [reset = 0x0]
PFIR_A8 is shown in 图7-107 and described in 表7-121.
Return to the Summary Table.
PFIR Coefficient A8
图7-107. PFIR_A8 Register
15
7
14
6
13
5
12
11
10
2
9
1
8
0
RESERVED
R/W-0x0
PFIR_A8
R/W-0x0
4
3
PFIR_A8
R/W-0x0
表7-121. PFIR_A8 Register Field Descriptions
Bit
Field
Type
R/W
R/W
Reset
Description
15:12
11:0
RESERVED
PFIR_A8
0x0
0x0
Signed, 2’s complement coefficient for the PFIR filter. This is the
ninth tap for the ADC A programmable FIR filter in Dual Channel
Mode or the ninth tap for the programmable FIR filter in Single
Channel Mode.
7.6.92 PFIR_B0 Register (Address = 0x448) [reset = 0x0]
PFIR_B0 is shown in 图7-108 and described in 表7-122.
Return to the Summary Table.
PFIR Coefficient B0
图7-108. PFIR_B0 Register
15
7
14
6
13
5
12
11
10
2
9
1
8
0
RESERVED
R/W-0x0
PFIR_B0
R/W-0x0
4
3
PFIR_B0
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图7-108. PFIR_B0 Register (continued)
R/W-0x0
表7-122. PFIR_B0 Register Field Descriptions
Bit
15:12
11:0
Field
Type
R/W
R/W
Reset
Description
RESERVED
PFIR_B0
0x0
0x0
Signed, 2’s complement coefficient for the PFIR filter. This is the
first tap for the ADC B programmable FIR filter in Dual Channel
Mode.
7.6.93 PFIR_B1 Register (Address = 0x44A) [reset = 0x0]
PFIR_B1 is shown in 图7-109 and described in 表7-123.
Return to the Summary Table.
PFIR Coefficient B1
图7-109. PFIR_B1 Register
15
7
14
6
13
5
12
11
10
2
9
1
8
0
RESERVED
R/W-0x0
PFIR_B1
R/W-0x0
4
3
PFIR_B1
R/W-0x0
表7-123. PFIR_B1 Register Field Descriptions
Bit
Field
Type
R/W
R/W
Reset
Description
15:12
11:0
RESERVED
PFIR_B1
0x0
0x0
Signed, 2’s complement coefficient for the PFIR filter. This is the
second tap for the ADC B programmable FIR filter in Dual Channel
Mode.
7.6.94 PFIR_B2 Register (Address = 0x44C) [reset = 0x0]
PFIR_B2 is shown in 图7-110 and described in 表7-124.
Return to the Summary Table.
PFIR Coefficient B2
图7-110. PFIR_B2 Register
15
7
14
6
13
5
12
11
10
2
9
1
8
0
RESERVED
R/W-0x0
PFIR_B2
R/W-0x0
4
3
PFIR_B2
R/W-0x0
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表7-124. PFIR_B2 Register Field Descriptions
Bit
15:12
11:0
Field
Type
R/W
R/W
Reset
Description
RESERVED
PFIR_B2
0x0
0x0
Signed, 2’s complement coefficient for the PFIR filter. This is the
third tap for the ADC B programmable FIR filter in Dual Channel
Mode.
7.6.95 PFIR_B3 Register (Address = 0x44E) [reset = 0x0]
PFIR_B3 is shown in 图7-111 and described in 表7-125.
Return to the Summary Table.
PFIR Coefficient B3
图7-111. PFIR_B3 Register
15
7
14
6
13
5
12
11
10
2
9
1
8
0
RESERVED
R/W-0x0
PFIR_B3
R/W-0x0
4
3
PFIR_B3
R/W-0x0
表7-125. PFIR_B3 Register Field Descriptions
Bit
Field
Type
R/W
R/W
Reset
Description
15:12
11:0
RESERVED
PFIR_B3
0x0
0x0
Signed, 2’s complement coefficient for the PFIR filter. This is the
fourth tap for the ADC B programmable FIR filter in Dual Channel
Mode.
7.6.96 PFIR_B4 Register (Address = 0x450) [reset = 0x0]
PFIR_B4 is shown in 图7-112 and described in 表7-126.
Return to the Summary Table.
PFIR Coefficient B4
图7-112. PFIR_B4 Register
23
15
7
22
14
6
21
13
5
20
12
4
19
11
3
18
10
2
17
9
16
8
RESERVED
R/W-0x0
PFIR_B4
R/W-0x0
PFIR_B4
R/W-0x0
1
0
PFIR_B4
R/W-0x0
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表7-126. PFIR_B4 Register Field Descriptions
Bit
Field
Type
R/W
R/W
Reset
Description
23:18
17:0
RESERVED
PFIR_B4
0x0
0x0
Signed, 2’s complement coefficient for the PFIR filter. This is the
fifth tap for the ADC B programmable FIR filter in Dual Channel
Mode. This is the center tap of the 9-tap filter and therefore has a
resolution of 18-bits.
7.6.97 PFIR_B5 Register (Address = 0x453) [reset = 0x0]
PFIR_B5 is shown in 图7-113 and described in 表7-127.
Return to the Summary Table.
PFIR Coefficient B5
图7-113. PFIR_B5 Register
15
7
14
6
13
5
12
11
10
2
9
1
8
0
RESERVED
R/W-0x0
PFIR_B5
R/W-0x0
4
3
PFIR_B5
R/W-0x0
表7-127. PFIR_B5 Register Field Descriptions
Bit
Field
Type
R/W
R/W
Reset
Description
15:12
11:0
RESERVED
PFIR_B5
0x0
0x0
Signed, 2’s complement coefficient for the PFIR filter. This is the
sixth tap for the ADC B programmable FIR filter in Dual Channel
Mode.
7.6.98 PFIR_B6 Register (Address = 0x455) [reset = 0x0]
PFIR_B6 is shown in 图7-114 and described in 表7-128.
Return to the Summary Table.
PFIR Coefficient B6
图7-114. PFIR_B6 Register
15
7
14
6
13
5
12
11
10
2
9
1
8
0
RESERVED
R/W-0x0
PFIR_B6
R/W-0x0
4
3
PFIR_B6
R/W-0x0
表7-128. PFIR_B6 Register Field Descriptions
Bit
15:12
Field
RESERVED
Type
Reset
Description
R/W
0x0
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表7-128. PFIR_B6 Register Field Descriptions (continued)
Bit
Field
PFIR_B6
Type
Reset
Description
11:0
R/W
0x0
Signed, 2’s complement coefficient for the PFIR filter. This is the
seventh tap for the ADC B programmable FIR filter in Dual Channel
Mode.
7.6.99 PFIR_B7 Register (Address = 0x457) [reset = 0x0]
PFIR_B7 is shown in 图7-115 and described in 表7-129.
Return to the Summary Table.
PFIR Coefficient B7
图7-115. PFIR_B7 Register
15
7
14
6
13
5
12
11
10
2
9
1
8
0
RESERVED
R/W-0x0
PFIR_B7
R/W-0x0
4
3
PFIR_B7
R/W-0x0
表7-129. PFIR_B7 Register Field Descriptions
Bit
Field
Type
R/W
R/W
Reset
Description
15:12
11:0
RESERVED
PFIR_B7
0x0
0x0
Signed, 2’s complement coefficient for the PFIR filter. This is the
eighth tap for the ADC B programmable FIR filter in Dual Channel
Mode.
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7.6.100 PFIR_B8 Register (Address = 0x459) [reset = 0x0]
PFIR_B8 is shown in 图7-116 and described in 表7-130.
Return to the Summary Table.
PFIR Coefficient B8
图7-116. PFIR_B8 Register
15
7
14
6
13
5
12
11
10
2
9
1
8
0
RESERVED
R/W-0x0
PFIR_B8
R/W-0x0
4
3
PFIR_B8
R/W-0x0
表7-130. PFIR_B8 Register Field Descriptions
Bit
Field
Type
Reset
Description
15:12
11:0
RESERVED
PFIR_B8
R/W
0x0
R(1)/W
0x0
Signed, 2’s complement coefficient for the PFIR filter. This is the
ninth tap for the ADC B programmable FIR filter in Dual Channel
Mode.
(1) Read function does not properly return MSB value - the MSB value in readback is always 0.
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8 Application Information Disclaimer
备注
以下应用部分中的信息不属于TI 器件规格的范围,TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计,以确保系统功能。
8.1 Application Information
ADC08DJ5200RF can be used in a wide range of applications including radar, satellite communications, test
equipment (communications testers and oscilloscopes), and software-defined radios (SDRs). The wide input
bandwidth enables direct RF sampling to at least 10 GHz and the high sampling rate allows signal bandwidths of
greater than 5 GHz. ADC08DJ5200RF can also be DC-coupled to meet the needs of oscilloscopes or wideband
digitizers. The Typical Applications section describes two configurations that meet the needs of a number of
these applications.
8.2 Typical Applications
8.2.1 Reconfigurable Dual-Channel 5-GSPS or Single-Channel 10-Gsps Oscilloscope
This section demonstrates the use of the device in a reconfigurable oscilloscope. The device is ideally suited for
oscilloscope applications. The ability to tradeoff channel count and sampling speed allows designers to build
flexible hardware to meet multiple needs. This flexibility saves development time and cost, allows hardware
reuse for various projects and enables software upgrade paths for additional functionality. This section describes
an oscilloscope that can operate as a dual-channel oscilloscope running at 5 GSPS or can be reconfigured
through SPI programming as a single-channel, 10-GSPS oscilloscope. A reconfigurable setup allows users to
trade off the number of channels and the sampling rate of the oscilloscope as needed without changing the
hardware. Set the input bandwidth to the desired maximum signal bandwidth through the use of an antialiasing,
low-pass filter. Digital filtering can then be used to reconfigure the analog bandwidth as required. For instance,
the maximum bandwidth can be set to 2 GHz for use during pulsed transient detection and then reconfigured to
100 MHz through digital filtering for low-noise, power-supply ripple observation. 图 8-1 shows the application
block diagram.
图8-1. Typical Configuration for Reconfigurable Oscilloscope
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8.2.1.1 Design Requirements
8.2.1.1.1 Input Signal Path
Most oscilloscopes are required to be DC-coupled in order to monitor DC or low-frequency signals. This
requirement forces the design to use DC-coupled, fully differential amplifiers to convert from single-ended
signaling at the front panel to differential signaling at the ADC. This design uses two differential amplifiers. The
first amplifier shown in 图 8-1 is the LMH5401 that converts from single-ended to differential signaling. The
LMH5401 interfaces with the front panel through a programmable termination network and has an offset
adjustment input. The amplifier has an 8-GHz, gain-bandwidth product that is sufficient to support a 1-GHz
bandwidth oscilloscope. A second amplifier, the LMH6401, comes after the LMH5401 to provide a digitally
programmable gain control for the oscilloscope. The LMH6401 supports a gain range from –6 dB to 26 dB in 1-
dB steps. If gain control is not necessary or is performed in a different location in the signal chain, then this
amplifier can be replaced with a second LMH5401 for additional fixed gain or omitted altogether.
The input of the oscilloscope contains a programmable termination block that is not covered in detail here. This
block enables the front-panel input termination to be programmed. For instance, many oscilloscopes allow the
termination to be programmed as either 50-Ω or 1-MΩ to meet the needs of various applications. A 75-Ω
termination can also be desired to support cable infrastructure use cases. This block can also contain an option
for DC blocking to remove the DC component of the external signal and therefore pass only AC signals.
A precision DAC is used to configure the offset of the oscilloscope front-end to prevent saturation of the analog
signal chain for input signals containing large DC offsets. The DAC8560 is shown in 图 8-1 along with signal-
conditioning amplifiers OPA703 and LMH6559. The first differential amplifier, LMH5401, is driven by the front
panel input circuitry on one input, and the DC offset bias on the second input. The impedance of these driving
signals must be matched at DC and over frequency to ensure good even-order harmonic performance in the
single-ended to differential conversion operation. The high bandwidth of the LMH6559 allows the device to
maintain low impedance over a wide frequency range.
An antialiasing, low-pass filter is positioned at the input of the ADC to limit the bandwidth of the input signal into
the ADC. This amplifier also band-limits the front-end noise to prevent aliased noise from degrading the signal-
to-noise ratio of the overall system. Design this filter for the maximum input signal bandwidth specified by the
oscilloscope. The input bandwidth can then be reconfigured through the use of digital filters in the FPGA or ASIC
to limit the oscilloscope input bandwidth to a bandwidth less than the maximum.
8.2.1.1.2 Clocking
The ADC08DJ5200RF clock inputs must be AC-coupled to the device to ensure rated performance. The clock
source must have extremely low jitter (integrated phase noise) to enable rated performance. Recommended
clock synthesizers include LMX2594 and LMX2572.
The JESD204C data converter system (ADC plus logic device) requires additional SYSREF and device clocks.
LMK04832, LMK04828, LMK04826, and LMK04821 devices are suitable to generate these clocks. Depending
on the ADC clock frequency and jitter requirements, this device can also be used as the system clock
synthesizer or as a device clock and SYSREF distribution device when multiple ADC08DJ5200RF devices are
used in a system. For clock frequencies higher than 3.2 GHz, LMX2594 and LMX2572 can supply both the
device clock and SYSREF from a single device.
8.2.1.1.3 ADC08DJ5200RF
ADC08DJ5200RF has a number of features that make it a great fit for oscilloscope applications. The low code-
error rate (CER) eliminates concerns about undesired time domain glitches or sparkle codes. The low CER
makes the device a perfect fit for long-duration transient detection measurements and reduces the probability of
false triggers. The input common-mode voltage of 0 V allows the driving amplifiers to use equal split power
supplies that center the amplifier output common-mode voltage at 0 V and eliminates the need for common-
mode voltage shifting before the ADC inputs. The high input bandwidth of the device simplifies the design of the
driving amplifier circuit and antialiasing, low-pass filter. The use of dual-edge sampling (DES) in single-channel
mode eliminates the need to change the clock frequency when switching between dual- and single-channel
modes and simplifies synchronization by relaxing the setup and hold timing requirements of SYSREF. The tAD
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adjust circuit allows the user to time-align the sampling instances of multiple ADC08DJ5200RF devices or to set
the ideal sampling point of a front-end track and hold (T&H) amplifier.
8.3 Initialization Set Up
The device and JESD204C interface require a specific startup and alignment sequence. The order of that
sequence is listed in the following steps.
1. Power-up or reset the device.
2. Apply a stable device CLK signal at the desired frequency.
3. Perform a software reset by toggling SOFT_RESET to 1. Wait at least 1 µs before continuing.
4. Program JESD_EN = 0 to stop the JESD204C state machine and allow setting changes.
5. Program CAL_EN = 0 to stop the calibration state machine and allow setting changes.
6. Program the desired JMODE.
7. Program the desired KM1 value. KM1 = K–1.
8. Program SYNC_SEL as needed. Choose SYNCSE or timestamp differential inputs.
9. Configure device calibration settings as desired. Select foreground or background calibration modes and
offset calibration as needed.
10. Program CAL_EN = 1 to enable the calibration state machine.
11. Enable overrange via OVR_EN and adjust settings if desired.
12. Program JESD_EN = 1 to re-start the JESD204C state machine and allow the link to restart.
13. The JESD204C interface operates in response to the applied SYNC signal from the receiver.
14. Program CAL_SOFT_TRIG = 0.
15. Program CAL_SOFT_TRIG = 1 to initiate a calibration.
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9 Power Supply Recommendations
The device requires two different power-supply voltages. 1.9-V DC is required for the VA19 power bus and 1.1-V
DC is required for the VA11 and VD11 power buses.
The power-supply voltages must be low noise and provide the needed current to achieve rated device
performance.
There are two recommended power supply architectures:
1. Step down using high-efficiency switching converters, followed by a second stage of regulation to provide
switching noise reduction and improved voltage accuracy.
2. Directly step down the final ADC supply voltage using high-efficiency switching converters. This approach
provides the best efficiency, but care must be taken for switching noise to be minimized to prevent degraded
ADC performance.
TI WEBENCH® Power Designer can be used to select and design the individual power supply elements needed:
see the WEBENCH® Power Designer
Recommended switching regulators for the first stage include LMS3635-Q1, LMS3655-Q1, TPSM84424 and
similar devices.
Recommended low drop-out (LDO), low-noise linear regulators include the TPS7A84, TPS7A83A, TPS7A47 and
similar devices.
For the switcher only approach, the ripple filter must be designed to provide sufficient filtering at the switching
frequency of the DC-DC converter and harmonics of the switching frequency. Make a note of the switching
frequency reported from WEBENCH® and design the EMI filter and capacitor combination to have the notch
frequency centered as needed. Each application will have different tolerances for noise on the supply voltage so
strict ripple requirements are not provided. 图9-1 and 图9-2 illustrate the two approaches.
2.2 V
1.9 V
VA19
5 V - 12 V
Buck
LDO
FB
FB
47 ꢀF
47 ꢀF
10 ꢀF 0.1 ꢀF 0.1 ꢀF
+
œ
Power
Good
GND
GND
GND
GND
1.4 V
1.1 V
47 ꢀF
VA11
Buck
LDO
FB
FB
47 ꢀF
10 ꢀF 0.1 ꢀF 0.1 ꢀF
GND
GND
GND
VD11
FB
10 ꢀF 0.1 ꢀF 0.1 ꢀF
GND
Copyright © 2018, Texas Instruments Incorporated
FB = ferrite bead filter.
图9-1. LDO Linear Regulator Approach Example
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Ripple Filter
VA19
5 V - 12 V
1.9 V
Buck
FB
FB
10 ꢀF 10 ꢀF 10 ꢀF
10 ꢀF 0.1 ꢀF 0.1 ꢀF
+
œ
Power
Good
GND
GND
GND
Ripple Filter
VA11
1.1 V
Buck
FB
FB
10 ꢀF 10 ꢀF 10 ꢀF
10 ꢀF 0.1 ꢀF 0.1 ꢀF
GND
GND
VD11
FB
10 ꢀF 0.1 ꢀF 0.1 ꢀF
GND
Copyright © 2018, Texas Instruments Incorporated
Ripple filter notch frequency to match the fs of the buck converter.
FB = ferrite bead filter.
图9-2. Switcher-Only Approach Example
9.1 Power Sequencing
The voltage regulators must be sequenced using the power-good outputs and enable inputs to make sure the
Vx11 regulator is enabled after the VA19 supply is good. Similarly, as soon as the VA19 supply drops out of
regulation on power-down, the Vx11 regulator is disabled.
The general requirement for the ADC is that VA19 ≥Vx11 during power-up, operation, and power-down.
TI also recommends that VA11 and VD11 are derived from a common 1.1-V regulator. This recommendation
makes sure that all 1.1-V blocks are at the same voltage, and no sequencing problems exist between these
supplies. Also use ferrite bead filters to isolate any noise on the VA11 and VD11 buses from affecting each other.
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10 Layout
10.1 Layout Guidelines
There are many critical signals that require specific care during board design:
1. Analog input signals
2. CLK and SYSREF
3. JESD204C data outputs
4. Power connections
5. Ground connections
The analog input signals, clock signals and JESD204C data outputs must be routed for excellent signal quality at
high frequencies, but should also be routed for maximum isolation from each other. Use the following general
practices:
1. Route using loosely coupled 100-Ωdifferential traces when possible. This routing minimizes impact of
corners and length-matching serpentines on pair impedance.
2. Provide adequate pair-to-pair spacing to minimize crosstalk, especially with loosely coupled differential
traces. Tightly coupled differential traces may be used to reduce self-radiated noise or to improve
neighboring trace noise immunity when adequate spacing cannot be provided.
3. Provide adequate ground plane pour spacing to minimize coupling with the high-speed traces. Any ground
plane pour must have sufficient via connections to the main ground plane of the board. Do not use floating or
poorly connected ground pours.
4. Use smoothly radiused corners. Avoid 45- or 90-degree bends to reduce impedance mismatches.
5. Incorporate ground plane cutouts at component landing pads to avoid impedance discontinuities at these
locations. Cut-out below the landing pads on one or multiple ground planes to achieve a pad size or stackup
height that achieves the needed 50-Ω, single-ended impedance.
6. Avoid routing traces near irregularities in the reference ground planes. Irregularities include cuts in the
ground plane or ground plane clearances associated with power and signal vias and through-hole
component leads.
7. Provide symmetrically located ground tie vias adjacent to any high-speed signal vias at an appropriate
spacing as determined by the maximum frequency the trace will transport (<< λMIN/8).
8. When high-speed signals must transition to another layer using vias, transition as far through the board as
possible (top to bottom is best case) to minimize via stubs on top or bottom of the vias. If layer selection is
not flexible, use back-drilled or buried, blind vias to eliminate stubs. Always place ground vias close to the
signal vias when transitioning between layers to provide a nearby ground return path.
Pay particular attention to potential coupling between JESD204C data output routing and the analog input
routing. Switching noise from the JESD204C outputs can couple into the analog input traces and show up as
wideband noise due to the high input bandwidth fo the ADC. Ideally, route the JESD204C data outputs on a
separate layer from the ADC input traces to avoid noise coupling (not shown in the Layout Example section).
Tightly coupled traces can also be used to reduce noise coupling.
Impedance mismatch between the CLK± input pins and the clock source can result in reduced amplitude of the
clock signal at the ADC CLK± pins due to signal reflections or standing waves. A reduction in the clock amplitude
may degrade ADC noise performance, especially at high input frequencies. To avoid this, keep the clock source
close to the ADC (as shown in the Layout Example section) or implement impedance matching at the ADC CLK±
input pins.
In addition, TI recommends performing signal quality simulations of the critical signal traces before committing to
fabrication. Insertion loss, return loss, and time domain reflectometry (TDR) evaluations should be done.
The power and ground connections for the device are also very important. These rules must be followed:
1. Provide low-resistance connection paths to all power and ground pins.
2. Use multiple power layers if necessary to access all pins.
3. Avoid narrow isolated paths that increase connection resistance.
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4. Use a signal, ground, or power circuit board stackup to maximum coupling between the ground and power
planes.
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10.2 Layout Example
图10-1 to 图10-3 provide examples of the critical traces routed on the device evaluation module (EVM).
图10-1. Top Layer Routing: Analog Inputs, CLK and SYSREF, DA0-3, DB0-3
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图10-2. GND1 Cutouts to Optimize Impedance of Component Pads
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图10-3. Bottom Layer Routing: Additional CLK Routing, DA4-7, DB4-7
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
11.1.1.1
WEBENCH® Power Designer
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation see the following:
• ADC12DJ5200RF Evaluation Module User's Guide
• JESD204B multi-device synchronization: Breaking down the requirements
• Scalable 20.8 GSPS reference design for high speed 12 bit digitizers
• Synchronizing multi-channel data converter DDC and NCO features for RF systems reference design
• Multi-Channel JESD204B 15 GHz Clocking Reference Design for DSO, Radar and 5G Wireless Testers
• Flexible 3.2 GSPS Multi-Channel AFE Reference Design for DSOs, RADAR, and 5G Wireless Test Systems
• Low noise power-supply reference design maximizing performance in 12.8 GSPS data acquisition systems
• 12.8-GSPS analog front end reference design for high-speed oscilloscope and wide-band digitizer
• Direct RF-Sampling Radar Receiver for L-, S-, C-, and X-Band Using ADC12DJ3200 Reference Design
• LMX2594 Multiple PLL Reference Design
• LMX2594 15-GHz Wideband PLLatinum™ RF Synthesizer With Phase Synchronization and JESD204B
• LMX2572 6.4-GHz Low Power Wideband RF Synthesizer With Phase Synchronization and JESD204B
• LMK04832 Ultra Low-Noise JESD204B Compliant Clock Jitter Cleaner With Dual Loop PLLs
• LMK0482x Ultra Low-Noise JESD204B Compliant Clock Jitter Cleaner with Dual Loop PLLs
• LMK61E2 Ultra-Low Jitter Programmable Oscillator With Internal EEPROM
• LMH5401 8-GHz, Low-Noise, Low-Power, Fully-Differential Amplifier
• LMH6401 DC to 4.5 GHz, Fully-Differential, Digital Variable-Gain Amplifier
• TPSM84424 4.5-V to 17-V Input, 0.6-V to 10-V Output, 4-A Power Module
• TPS7A470x 36-V, 1-A, 4-µVRMS, RF LDO Voltage Regulator
• TPS7A83A 2-A, High-Accuracy (0.75%), Low-Noise (4.4 µVRMS) LDO Regulator
• TPS7A84 High-Current (3 A), High-Accuracy (1%), Low-Noise (4.4 µVRMS), LDO Voltage Regulator
• DAC8560 16-Bit, Ultra-Low Glitch, Voltage Output Digital-to-Analog Converter With 2.5-V, 2-ppm/°C
Reference
• LM95233 Dual Remote Diode and Local Temperature Sensor with SMBus Interface and TruTherm™
• TMP461 High-Accuracy Remote and Local Temperature Sensor with Pin-Programmable Bus Address
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11.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.4 Support Resources
11.5 Trademarks
WEBENCH® is a registered trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
11.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.7 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
19-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
168
250
(1)
(2)
(3)
(4/5)
(6)
ADC08DJ5200RFAAV
ADC08DJ5200RFAAVT
ACTIVE
FCCSP
FCCSP
AAV
144
144
RoHS & Green
RoHS & Green
SNAGCU
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 85
-40 to 85
ADC08DJ52
Samples
Samples
RF
ACTIVE
AAV
SNAGCU
ADC08DJ52
RF
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
19-Oct-2022
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Jun-2023
TRAY
L - Outer tray length without tabs
KO -
Outer
tray
height
W -
Outer
tray
width
Text
P1 - Tray unit pocket pitch
CW - Measurement for tray edge (Y direction) to corner pocket center
CL - Measurement for tray edge (X direction) to corner pocket center
Chamfer on Tray corner indicates Pin 1 orientation of packed units.
*All dimensions are nominal
Device
Package Package Pins SPQ Unit array
Max
matrix temperature
(°C)
L (mm)
W
K0
P1
CL
CW
Name
Type
(mm) (µm) (mm) (mm) (mm)
ADC08DJ5200RFAAV
AAV
FCCSP
144
168
8 X 21
150
315 135.9 7620 14.65
11
11.95
Pack Materials-Page 1
PACKAGE OUTLINE
AAV0144A
FCBGA - 1.91 mm max height
SCALE 1.400
BALL GRID ARRAY
10.15
9.85
A
B
BALL A1 CORNER
10.15
9.85
(
8)
(0.67)
1.91
1.70
(0.5)
C
SEATING PLANE
NOTE 4
BALL TYP
0.405
0.325
TYP
0.1 C
8.8 TYP
SYMM
(0.6) TYP
(0.6) TYP
0.8 TYP
M
L
K
J
H
G
F
SYMM
8.8
TYP
E
D
C
B
A
0.51
0.41
144X
0.15
0.08
C A B
NOTE 3
C
1
2
3
4
5
6
7
8
9
10
11
12
0.8 TYP
4219578/C 05/2022
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Dimension is measured at the maximum solder ball diameter, parallel to primary datum C.
4. Primary datum C and seating plane are defined by the spherical crowns of the solder balls.
www.ti.com
EXAMPLE BOARD LAYOUT
AAV0144A
FCBGA - 1.91 mm max height
BALL GRID ARRAY
(0.8) TYP
1
3
5
6
7
8
9
10 11
4
12
2
A
B
(0.8) TYP
C
D
E
F
144X ( 0.4)
SYMM
G
H
J
K
L
M
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
(
0.4)
0.05 MAX
METAL UNDER
SOLDER MASK
0.05 MIN
METAL
EXPOSED
METAL
EXPOSED
METAL
(
0.4)
SOLDER MASK
OPENING
SOLDER MASK
OPENING
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
NOT TO SCALE
4219578/C 05/2022
NOTES: (continued)
5. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
For more information, see Texas Instruments literature number SPRU811 (www.ti.com/lit/spru811).
www.ti.com
EXAMPLE STENCIL DESIGN
AAV0144A
FCBGA - 1.91 mm max height
BALL GRID ARRAY
(0.8) TYP
144X ( 0.4)
10 11
1
3
5
6
7
8
9
4
12
2
A
B
(0.8) TYP
C
D
E
F
SYMM
G
H
J
K
L
M
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.15 mm THICK STENCIL
SCALE:8X
4219578/C 05/2022
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
www.ti.com
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