ADC10321CIVT/NOPB [TI]

10 位、20MSPS 模数转换器 (ADC) | NEY | 32 | -40 to 85;


型号：	ADC10321CIVT/NOPB
厂家：	TEXAS INSTRUMENTS
描述：	10 位、20MSPS 模数转换器 (ADC) \| NEY \| 32 \| -40 to 85 转换器模数转换器
文件：	总28页 (文件大小：1162K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ADC10321

www.ti.com

SNAS028F –JUNE 2000–REVISED MAY 2013

ADC10321 10-Bit, 20MSPS, 98mW A/D Converter with Internal Sample and Hold

Check for Samples: ADC10321

FEATURES

DESCRIPTION

The ADC10321 is a low power, high performance

CMOS analog-to-digital converter that digitizes

signals to 10 bits resolution at sampling rates up to

25Msps while consuming a typical 98mW from a

single 5V supply. Reference force and sense pins

allow the user to connect an external reference buffer

amplifier to ensure optimal accuracy. No missing

codes is ensured over the full operating temperature

range. The unique two stage architecture achieves

9.2 Effective Bits with a 10MHz input signal and a

20MHz clock frequency. Output formatting is straight

binary coding.

•

Internal Sample-and-Hold

Single +5V Operation

•

Low Power Standby Mode

Ensured No Missing Codes

TTL/CMOS or 3V Logic Input/Output

Compatible

APPLICATIONS

•

Digital Video

Communications

Document Scanners

Medical Imaging

Electro-Optics

To ease interfacing to 3V systems, the digital I/O

power pins of the ADC10321 can be tied to a 3V

power source, making the outputs 3V compatible.

When not converting, power consumption can be

reduced by pulling the PD (Power Down) pin high,

placing the converter into a low power standby state,

where it typically consumes less than 4mW. The

ADC10321's speed, resolution and single supply

operation makes it well suited for a variety of

applications in video, imaging, communications,

multimedia and high speed data acquisition. Low

power, single supply operation ideally suit the

ADC10321 for high speed portable applications, and

its speed and resolution are ideal for charge coupled

device (CCD) input systems.

Plain Paper Copiers

CCD Imaging

KEY SPECIFICATIONS

•

Resolution 10 Bits

Conversion Rate 20 Msps

ENOB@ 10MHz Input 9.2 Bits (typ)

DNL 0.35 LSB (typ)

Conversion Latency 2 Clock Cycles

PSRR 56 dB

The ADC10321 comes in a space saving 32-pin

TQFP and operates over the industrial (−40°C ≤ T_A≤

+85°C) temperature range.

Power Consumption 98 mW (typ)

Low Power Standby Mode <4 mW (typ)

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

ADC10321

SNAS028F –JUNE 2000–REVISED MAY 2013

www.ti.com

Connection Diagrams

Block Diagram

Submit Documentation Feedback

Product Folder Links: ADC10321

ADC10321

www.ti.com

SNAS028F –JUNE 2000–REVISED MAY 2013

PIN DESCRIPTIONS AND EQUIVALENT CIRCUITS

No.

Description

Symbol

Equivalent Circuit

Analog I/O

Analog Input signal to be converted. Conversion range is

V_REFS to V_REFS.

V_IN

−

Analog input that goes to the high side of the reference

ladder of the ADC. This voltage should force V_REFS to be in

the range of 2.3V to 4.0V.

V_REF

Analog output used to sense the voltage near the top of the

ADC reference ladder.

V_REF

Analog input that goes to the low side of the reference ladder

of the ADC. This voltage should force V_REF−S to be in the

range of 1.3V to 3.0V.

−

V_REF

Analog output used to sense the voltage near the bottom of

the ADC reference ladder.

V_REF−

Converter digital clock input. V_INis sampled on the falling

edge of CLK input.

CLK

Submit Documentation Feedback

Product Folder Links: ADC10321

ADC10321

SNAS028F –JUNE 2000–REVISED MAY 2013

www.ti.com

PIN DESCRIPTIONS AND EQUIVALENT CIRCUITS (continued)

No.

Description

Symbol

Equivalent Circuit

Power Down input. When this pin is high, the converter is in

the Power Down mode and the data output pins are in a high

impedance state.

Output Enable pin. When this pin and the PD pin are low, the

output data pins are active. When this pin or the PD pin is

high, the output data pins are in a high impedance state.

14 thru

and

22 thru

Digital Output pins providing the 10 bit conversion results.

D0 is the LSB, D9 is the MSB. Valid data is present just after

the falling edge of the CLK input.

D0 -D9

Positive analog supply pins. These pins should be connected

to a clean, quiet voltage source of +5V. V_Aand V_Dshould

have a common supply and be separately bypassed with

10µF to 50µF capacitors in parallel with 0.1µF capacitors.

3, 7, 28

V_A

V_D

Positive digital supply pins. These pins should be connected

to a clean, quiet voltage source of +5V. V_Aand V_Dshould

have a common supply and be separately bypassed with

10µF to 50µF capacitors in parallel with 0.1µF capacitors.

5, 10

Positive supply pins for the digital output drivers. These pins

should be connected to a clean, quiet voltage source of +3V

to +5V and be separately bypassed with 10µF capacitors.

12, 21

V_DI/O

AGND

The ground return for the analog supply. AGND and DGND

should be connected together close to the ADC10321

package.

4, 27,

The ground return for the digital supply. AGND and DGND

should be connected together close to the ADC10321

pacjage.

6, 11

DGND

13, 20

DGND I/O

The ground return of the digital output drivers.

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

Submit Documentation Feedback

Product Folder Links: ADC10321

ADC10321

www.ti.com

SNAS028F –JUNE 2000–REVISED MAY 2013

ABSOLUTE MAXIMUM RATINGS^(1)(2)(3)

Positive Supply Voltage (V = V_A= V_D)

Voltage on Any I/O Pin

6.5V

−0.3V to (V_Aor V_D) +0.3V)

±25mA

Input Current at Any Pin⁽⁴⁾

Package Input Current⁽⁴⁾

±50mA

(5)

Package Dissipation at T_A= 25°C

ESD Susceptibility⁽⁶⁾Human Body Model

Machine Model

See

1500V

200V

Soldering Temp., Infrared, 10 sec.⁽⁷⁾

235°C

Storage Temperature

−65°C to +150°C

(1) All voltages are measured with respect to GND = AGND = DGND = 0V, unless otherwise specified.

(2) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for

which the device is functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see the

Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance characteristics may

degrade when the device is not operated under the listed test conditions.

(3) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and

specifications.

(4) When the input voltage at any pin exceeds the power supplies ( V_IN< AGND or V_IN> V_Aor V_D), the current at that pin should be limited

to 25mA. The 50mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an

input current of 25mA to two.

(5) The absolute maximum junction temperature (T_Jmax) for this device is 150°C. The maximum allowable power dissipation is dictated by

TJmax, the junction-to-ambient thermal resistance (θ_JA), and the ambient temperature (T_A), and can be calculated using the formula

P_DMAX = (T_Jmax - T_A)/θ_JA. In the 32-pin TQFP, θ_JAis 69°C/W, so P_DMAX = 1,811 mW at 25°C and 942mW at the maximum operating

ambient temperature of 85°C. Note that the power dissipation of this device under normal operation will typically be about 110mW

(98mW quiescent power + 2mW reference ladder power +10mW due to 10 TTL load on each digital output). The values for maximum

power dissipation listed above will be reached only when the ADC10321 is operated in a severe fault condition (e.g. when input or

output pins are driven beyond the power supply voltages, or the power supply polarity is reversed). Obviously, such conditions should

always be avoided.

(6) Human body model is 100 pF capacitor discharged through a 1.5kΩ resistor. Machine model is 220 pF discharged through ZERO Ω.

(7) The 235°C reflow temperature refers to infared reflow. For Vapor Phase Reflow (VPR), the following conditions apply: Maintain the

temperature at the top of the package body above 183°C for a minimum 60 seconds. The temperature measured on the package body

must not exceed 220°C. Only one excursion above 183°C is allowed per reflow cycle.

OPERATING RATINGS⁽¹⁾⁽²⁾

Operating Temperature

V_A,V_DSupply Voltage

V_DI/O Supply Voltage

V_INVoltage Range

−40°C ≤ T_A≤ +85°C

+4.5V to +5.5V

+2.7V to 5.5V

1.3V to (V_A-1.0V)

2.3V to (V_A-1.0V)

1.3V to 3.0V

V_REF+ Voltage Range

V_REF− Voltage Range

PD, CLK, OE Voltage

−0.3V to + 5.5V

(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for

which the device is functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see the

Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance characteristics may

degrade when the device is not operated under the listed test conditions.

(2) All voltages are measured with respect to GND = AGND = DGND = 0V, unless otherwise specified.

Submit Documentation Feedback

Product Folder Links: ADC10321

ADC10321

SNAS028F –JUNE 2000–REVISED MAY 2013

www.ti.com

CONVERTER ELECTRICAL CHARACTERISTICS

The following specifications apply for V_A= +5.0V_DC, V_D= 5.0V_DC, V_DI/O = 5.0V_DC, V_REF+ = +3.5V_DC, V_REF− = +1.5V_DC, C_L=

20pF, f_CLK= 20MHz, R_S= 25Ω. Boldface limits apply for T_A= T_MINto T_MAX: all other limits T_A= 25°C⁽¹⁾

Symbol

Parameter

Conditions

Typical⁽²⁾

Limits⁽³⁾

Units

Static Converter Characteristics

INL

Integral Non-Linearity

±0.45

±0.35

±1.0

±0.85

LSB(max)

Bits

DNL

Differential-Non Linearity

Resolution with No Missing

Codes

Zero Scale Offset Error

Full-Scale Error

−6

mV(max)

Dynamic Converter Characteristics

f_IN= 1.0MHz

f_IN= 4.43MHz

f_IN= 10MHz

9.5

9.2

Bits

Bits(min)

Bits

ENOB

S/(N+D)

SNR

Effective Number of Bits

9.0

f_IN= 1.0MHz

f_IN= 4.43MHz

f_IN= 10MHz

dB(min)

Signal-to-Noise Plus Distortion

Ratio

f_IN= 1.0MHz

f_IN= 4.43MHz

f_IN= 10MHz

dB(min)

Signal-to-Noise Ratio

f_IN= 1.0MHz

f_IN= 4.43MHz

f_IN= 10MHz

−71

−70

−66

dB(min)

THD

Total Harmonic Distortion

Spurious Free Dynamic Range

−59

f_IN= 1.0MHz

f_IN= 4.43MHz

f_IN= 10MHz

SFDR

Differential Gain Error

Differential Phase Error

Overrange Output Code

Underrange Output Code

Full Power Bandwidth

f_IN= 4.43MHz, f_CLK= 17.72MHz

0.5

%(max)

deg(max)

V_IN> V_REF

V_IN< V_REF

1023

−

150

MHz

Change in Full Scale with 4.5V to 5.5V

Supply Change

PSRR

Power Supply Rejection Ratio

Reference and Analog Input Characteristics⁽⁴⁾

1.3

4.0

V(min)

V(max)

V_IN

Analog Input Range

C_IN

I_IN

Analog V_INInput Capacitance

Input Leakage Current

µA

850

1150

Ω(min)

Ω(max)

R_REF

Reference Ladder Resistance

1000

V_REF

Positive Reference Voltage

Negative Reference Voltage

3.5

1.5

4.0

1.3

V(max)

V(min)

−

(V_REF+)

−(V_REF−)

1.0

2.7

V(min)

V(max)

Total Reference Voltage

2.0

(1) The inputs are protected as shown below. Input voltage magnitudes up to 500mV beyond the supply rails will not damage this device.

However, errors in the A/D conversion can occur if the input goes above V_Aor below AGND by more than 300 mV. See Figure 1,

Figure 2 and Figure 3.

(2) Typical figures are at T_A= T_J= 25°C, and represent most likely parametric norms.

(3) Tested limits are specified to TI's AOQL (Average Outgoing Quality Level).

(4) When the input signal is between V_REF+ and (V_A+ 300mV), the output code will be 3FFh, or all 1s. When the input signal is between

−300 mV and V_REF−, the output code will be 000h, or all 0s.

Submit Documentation Feedback

Product Folder Links: ADC10321

ADC10321

www.ti.com

SNAS028F –JUNE 2000–REVISED MAY 2013

DC AND LOGIC ELECTRICAL CHARACTERISTICS

The following specifications apply for V_A= +5.0V_DC, V_D= +5.0V_DC, V_DI/O = 5.0V_DC, V_REF+ = +3.5V_DC, V_REF− = +1.5V_DC, C_L=

20 pF, f_CLK= 20MHz, R_S= 25Ω. Boldface limits apply for T_A= T_MINto T_MAX: all other limits T_A= 25°C⁽¹⁾

Symbol

Parameter

Conditions

Typical⁽²⁾

Limits⁽³⁾

Units

CLK, OE, PD, Digital Input Characteristics

V_IH

V_IL

I_IH

Logical "1" Input Voltage

Logical "0" Input Voltage

Logical "1" Input Current

Logical "0" Input Current

V_D= 5.5V

V_D= 4.5V

V_IH= V_D

2.0

1.0

V(min)

V(max)

µA

I_IL

V_IL= DGND

−10

µA

D00 - D13 Digital Output Characteristics

V_DI/O = + 4.5V, I_OUT= −0.5mA

V_DI/O = + 2.7V, I_OUT= −0.5mA

4.0

2.4

V(min)

V_OH

V_OL

I_OZ

Logical "1" Output Voltage

Logical "0" Output Voltage

V_DI/O = + 4.5V, I_OUT= −1.6mA

V_DI/O = + 2.7V, I_OUT= −1.6mA

0.4

V(max)

V_OUT= DGND

V_OUT= V_D

−10

µA

TRI-STATE Output Current

Output Short Circuit Current

V_DI/O = 3V

V_DI/O = 5V

±12

±25

I_OS

Power Supply Characteristics

PD = LOW, Ref not included

PD = HIGH, Ref not included

14.5

0.5

I_A

Analog Supply Current

mA(max)

PD = LOW, Ref not included

PD = HIGH, Ref not included

0.2

I_D+ I_DI/O

P_D

Digital Supply Current

Power Consumption

mA(max)

110

mW (max)

(1) The inputs are protected as shown below. Input voltage magnitudes up to 500mV beyond the supply rails will not damage this device.

However, errors in the A/D conversion can occur if the input goes above V_Aor below AGND by more than 300 mV. See Figure 1,

Figure 2 and Figure 3.

(2) Typical figures are at T_A= T_J= 25°C, and represent most likely parametric norms.

(3) Tested limits are specified to TI's AOQL (Average Outgoing Quality Level).

AC ELECTRICAL CHARACTERISTICS

The following specifications apply for V_A= +5.0V_DC, V_DI/O = 5.0V_DC, V_REF+ = +3.5V_DC, V_REF− = +1.5V_DC, f_CLK= 20MHz, t_rc= t_fc

= 5ns, R_S= 25Ω. C_L(data bus loading) = 20 pF, Boldface limits apply for T_A= T_MINto T_MAX: all other limits T_A= 25°C⁽¹⁾

Units

Symbol

Parameter

Conditions

Typical⁽²⁾

Limits⁽³⁾

(Limits)

MHz(min)

MHz(max)

ns(min

f_CLK1

f_CLK2

t_CH

Maximum Clock Frequency

Minimum Clock Frequency

Clock High Time

t_CL

Clock Low Time

ns(min)

%(min)

%(max)

Duty Cycle

Pipeliine Delay (Latency)

Clock Input Rise and Fall Time

Output Rise and Fall Times

Fall of CLK to data valid

Output Data Hold Time

2.0

Clock Cycles

ns(max)

t_rc, t_fc

t_r, t_f

t_OD

ns(max)

t_OH

(1) The inputs are protected as shown below. Input voltage magnitudes up to 500mV beyond the supply rails will not damage this device.

However, errors in the A/D conversion can occur if the input goes above V_Aor below AGND by more than 300 mV. See Figure 1,

Figure 2 and Figure 3.

(2) Typical figures are at T_A= T_J= 25°C, and represent most likely parametric norms.

(3) Tested limits are specified to TI's AOQL (Average Outgoing Quality Level).

Submit Documentation Feedback

Product Folder Links: ADC10321

ADC10321

SNAS028F –JUNE 2000–REVISED MAY 2013

www.ti.com

AC ELECTRICAL CHARACTERISTICS (continued)

The following specifications apply for V_A= +5.0V_DC, V_DI/O = 5.0V_DC, V_REF+ = +3.5V_DC, V_REF− = +1.5V_DC, f_CLK= 20MHz, t_rc= t_fc

= 5ns, R_S= 25Ω. C_L(data bus loading) = 20 pF, Boldface limits apply for T_A= T_MINto T_MAX: all other limits T_A= 25°C⁽¹⁾

Units

(Limits)

Symbol

Parameter

Conditions

Typical⁽²⁾

Limits⁽³⁾

From output High, 2K to

Ground

t_DIS

Rising edge of OE to valid data

From output Low, 2K to

V_DI/O

t_EN

t_VALID

t_AD

Falling edge of OE to valid data

Data valid time

1K to V_CC

Apeture Delay

t_AJ

Aperture Jitter

<30

Full Scale Step Response

t_r= 10ns

V_INstep from (V_REF

+100mV) to (V_REF−)

conversion

Overrange Recovery Time

conversion

PD low to 1/2 LSB accurate conversion

(Wake-Up time)

t_WU

700

Figure 1.

Figure 2.

Figure 3.

Submit Documentation Feedback

Product Folder Links: ADC10321

ADC10321

www.ti.com

SNAS028F –JUNE 2000–REVISED MAY 2013

TYPICAL PERFORMANCE CHARACTERISTICS

V_A= V_D= V_DI/O = 5V, f_CLK= 20MHz, unless otherwise specified.

Typical INL

INL vs f_CLK

Figure 4.

INL vs V_A

Figure 5.

INL vs Clock Duty Cycle

Figure 6.

Figure 7.

Typical DNL

DNL vs f_CLK

Figure 8.

Figure 9.

Submit Documentation Feedback

Product Folder Links: ADC10321

ADC10321

SNAS028F –JUNE 2000–REVISED MAY 2013

www.ti.com

TYPICAL PERFORMANCE CHARACTERISTICS (continued)

V_A= V_D= V_DI/O = 5V, f_CLK= 20MHz, unless otherwise specified.

DNL vs V_A

DNL vs Clock Duty Cycle

Figure 10.

Figure 11.

SINAD & ENOB vs Temperature and f_IN

SINAD & ENOB vs V_A

Figure 12.

Figure 13.

SINAD & ENOB vs f_CLKand f_IN

I_A+ I_Dvs. Temperature

Figure 14.

Figure 15.

Submit Documentation Feedback

Product Folder Links: ADC10321

ADC10321

www.ti.com

SNAS028F –JUNE 2000–REVISED MAY 2013

TYPICAL PERFORMANCE CHARACTERISTICS (continued)

V_A= V_D= V_DI/O = 5V, f_CLK= 20MHz, unless otherwise specified.

Spectral Response at 20 MSPs

Figure 16.

Submit Documentation Feedback

Product Folder Links: ADC10321

ADC10321

SNAS028F –JUNE 2000–REVISED MAY 2013

www.ti.com

SPECIFICATION DEFINITIONS

APERTURE JITTER is the variation in aperture delay from sample to sample. Aperture jitter shows up as input

noise.

APERTURE DELAY See Sampling Delay.

DIFFERENTIAL GAIN ERROR is the percentage difference between the output amplitudes of a given amplitude

small signal, high frequency sine wave input at two different dc input levels.

DIFFERENTIAL PHASE ERROR is the difference in the output phase of a small signal sine wave input at two

different dc input levels.

DIFFERENTIAL NON-LINEARITY (DNL) is the measure of the maximum deviation from the ideal step size of 1

LSB.

EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE BITS) is another method of specifying Signal-to-Noise

and Distortion Ratio (S/N+D or SINAD). ENOB is defined as (SINAD −1.76) / 6.02.

FULL POWER BANDWIDTH is a measure of the frequency at which the reconstructed output fundamental

drops 3 dB below its 1MHz value for a full scale input. The test is performed with f_INequal to 100 kHz plus

integral multiples of f_CLK. The input frequency at which the output is −3 dB relative to the1MHz input signal is the

full power bandwidth.

FULL SCALE (FS) INPUT RANGE of the ADC is the input range of voltages over which the ADC will digitize that

input. For V_REF+ = 3.50V and V_REF− = 1.50V, FS = (V_REF+) − (V_REF−) = 2.00V.

FULL SCALE OFFSET ERROR is a measure of how far the last code transition is from the ideal 1½ LSB below

V_REF+ and is defined as V₁₀₂₃−1.5 LSB − V_REF+ , where V₁₀₂₃is the voltage at which the transitions from code

1022 to 1023 occurs.

FULL SCALE STEP RESPONSE is defined as the time required after V_INgoes from V_REF− to V_REF+, or V_REF+ to

V_REF−, and settles sufficiently for the converter to recover and make a conversion with its rated accuracy.

INTEGRAL NON-LINEARITY (INL) is a measure of the deviation of each individual code from a line drawn from

negative full scale (½ LSB below the first code transition) through positive full scale (1½ LSB above the last code

transition). The deviation of any given code from this straight line is measured from the center of that code value.

OUTPUT DELAY is the time delay after the fall of the input clock before the data update is present at the output

pins.

OUTPUT HOLD TIME is the length of time that the output data is valid after the fall of the input clock.

OVER RANGE RECOVERY TIME is the time required after V_INgoes from AGND to V_REF+ or V_INgoes from V_Ato

V_REF− for the converter to recover and make a conversion with its rated accuracy.

PIPELINE DELAY (LATENCY) is the number of clock cycles between initiation of conversion and when that data

is presented to the output driver stage. Data for any given sample is available by the Pipeline Delay plus the

Output Delay after that sample is taken. New data is available at every clock cycle, but the data lags the

conversion by the pipeline delay.

PSRR (POWER SUPPLY REJECTION RATIO) is the ratio of the change in dc power supply voltage to the

resulting change in Full Scale Error, expressed in dB.

SAMPLING (APERTURE) DELAY or APERTURE TIME is that time required after the fall of the clock input for

the sampling switch to open. The sample is effectively taken this amount of time after the fall of the clock input.

SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in dB, of the rms value of the input signal to the rms

value of the sum of all other spectral components below one-half the sampling frequency, not including

harmonics or dc.

SIGNAL TO NOISE PLUS DISTORTION (S/(N+D) or SINAD) is the ratio, expressed in dB, of the RMS value of

the input signal to the RMS value of all of the other spectral components below half the clock frequency,

including harmonics but excluding dc.

SPURIOUS FREE DYNAMIC RANGE (SFDR) is the difference, expressed in dB or dBc, between the RMS

values of the input signal and the peak spurious signal, where a spurious signal is any signal present in the

output spectrum that is not present at the input.

Submit Documentation Feedback

Product Folder Links: ADC10321

ADC10321

www.ti.com

SNAS028F –JUNE 2000–REVISED MAY 2013

TOTAL HARMONIC DISTORTION (THD) is the ratio, expressed in dB, of the rms total of the first six harmonic

components, to the rms value of the input signal.

ZERO SCALE OFFSET ERROR is the difference between the ideal input voltage (½ LSB) and the actual input

voltage that just causes a transition from an output code of zero to an output code of one.

Timing Diagram

Figure 17. ADC10321 Timing Diagram

Submit Documentation Feedback

Product Folder Links: ADC10321

ADC10321

SNAS028F –JUNE 2000–REVISED MAY 2013

www.ti.com

Figure 18. AC Test Circuit

Figure 19. t_EN, t_DISTest Circuit

FUNCTIONAL DESCRIPTION

The ADC10321 maintains excellent dynamic performance for input signals up to half the clock frequency. The

use of an internal sample-and-hold amplifier (SHA) enables sustained dynamic performance for signals of input

frequency beyond the clock rate, lowers the converter's input capacitance and reduces the number of external

components required.

The analog signal at V_INthat is within the voltage range set by V_REF+ S and V_REF− S are digitized to ten bits at up

to 25 MSPS. Input voltages below V_REF− S will cause the output word to consist of all zeroes. Input voltages

above V_REF+ S will cause the output word to consist of all ones. V_REF+ S has a range of 2.3 to 4.0 Volts, while

V_REF− S has a range of 1.3 to 3.0 Volts. V_REF+ S should always be at least 1.0 Volt more positive than V_REF− S.

Data is acquired at the falling edge of the clock and the digital equivalent of that data is available at the digital

outputs 2.0 clock cycles plus t_ODlater. The ADC10321 will convert as long as the clock signal is present at pin 9

and the PD pin is low. The Output Enable pin (OE), when low, enables the output pins. The digital outputs are in

the high impedance state when the OE pin is low or the PD pin is high.

Submit Documentation Feedback

Product Folder Links: ADC10321

ADC10321

www.ti.com

SNAS028F –JUNE 2000–REVISED MAY 2013

APPLICATIONS INFORMATION

THE ANALOG INPUT

The analog input of the ADC10321 is a switch (transmission gate) followed by a switched capacitor amplifier. The

capacitance seen at the input changes with the clock level, appearing as about 3pF when the clock is low, and

about 5pF when the clock is high. This small change in capacitance can be reasonably assumed to be a fixed

capacitance. Care should be taken to avoid driving the input beyond the supply rails, even momentarily, as

during power-up.

The LMH6702 has been found to be a good device to drive the ADC10321 because of its low voltage capability,

wide bandwidth, low distortion and minimal Differential Gain and Differential Phase. The LMH6702 performs best

with a feedback resistor of about 100 ohms.

Care should be taken to keep digital noise out of the analog input circuitry to maintain highest noise

performance.

REFERENCE INPUTS

NOTE

Throughout this data sheet reference is made to V_REF+ and to V_REF−. These refer to the

internal voltage across the reference ladder and are, nominally, V_REF+ S and V_REF− S,

respectively.

Figure 20 shows a simple reference biasing scheme with minimal components. While this circuit might suffice for

some applications, it does suffer from thermal drift because the external resistor at pin 2 will have a different

temperature coefficient than the on-chip resistors. Also, the on-chip resistors, while well matched to each other,

will have a large tolerance compared with any external resistors, causing the value of V_REF- to be quite variable.

No d.c. current should be allowed to flow through pin 1 or 32 or linearity errors will result near the zero scale and

full scale ends of the signal excursion. The sense pins were designed to be used with high impedance opamp

inputs for high accuracy biasing.

The circuit of Figure 21 is an improvement over the circuit of Figure 20 in that both ends of the reference ladder

are defined with reference voltages. This reduces problems of high reference variability and thermal drift, but

requires two reference sources.

In addition to the usual reference inputs, the ADC10321 has two sense outputs for precision control of the ladder

voltages. These sense outputs (V_REF+ S and V_REF− S) compensate for errors due to IR drops between the

source of the reference voltages and the ends of the reference ladder itself.

With the addition of two op-amps, the voltages at the top and bottom of the reference ladder can be forced to the

exact value desired, as shown in Figure 22.

Submit Documentation Feedback

Product Folder Links: ADC10321

ADC10321

SNAS028F –JUNE 2000–REVISED MAY 2013

www.ti.com

Figure 20. Simple, low component count reference biasing

Submit Documentation Feedback

Product Folder Links: ADC10321

ADC10321

www.ti.com

SNAS028F –JUNE 2000–REVISED MAY 2013

Figure 21. Better low component count reference biasing

The V_REF+ F and V_REF− F pins should each be bypassed to AGND with 10µF tantalum or electrolytic and 0.1µF

ceramic capacitors. The circuit of Figure 22 may be used if it is desired to obtain precise reference voltages. The

LMC6082 in this circuit was chosen for its low offset voltage, low voltage rail-to-rail capability and low cost.

Since the current flowing through the sense lines (those lines associated with V_REF+ S and V_REF− S) is

essentially zero, there is negligible voltage drop across any resistance in series with these sense pins and the

voltage at the inverting input of the op-amp accurately represents the voltage at the top (or bottom) of the ladder.

The op-amp drives the force input, forcing the voltage at the ends of the ladder to equal the voltage at the op-

amp's non-inverting input, plus any offset voltage. For this reason, op-amps with low V_OS, such as the LMC6081

and LMC6082, should be used for this application.

Voltages at the reference sense pins (V_REF+ S and V_REF− S) should be within the range specified in the

Operating Ratings table (2.3V to 4.0V for V_REF+ and 1.3V to 3.0V for V_REF−). Any device used to drive the

reference pins should be able to source sufficient current into the V_REF+ F pin and sink sufficient current from the

V_REF− F pin when the ladder is at its minimum value of 850 Ohms.

Submit Documentation Feedback

Product Folder Links: ADC10321

ADC10321

SNAS028F –JUNE 2000–REVISED MAY 2013

www.ti.com

The reference voltage at the top of the ladder (V_REF+) may take on values as low as 1.0V above the voltage at

the bottom of the ladder (V_REF−) and as high as (V_A- 1.0V) Volts. The voltage at the bottom of the ladder (V_REF−)

may take on values as low as 1.3 Volts and as high as 3.0V. However, to minimize noise effects and ensure

accurate conversions, the total reference voltage range (V_REF+ - V_REF−) should be a minimum of 2.0V and a

maximum of 2.7V.

Figure 22. Setting precision reference voltages

POWER SUPPLY CONSIDERATIONS

A/D converters draw sufficient transient current to corrupt their own power supplies if not adequately bypassed. A

10µF to 50µF tantalum or aluminum electrolytic capacitor should be placed within an inch (2.5 centimeters) of the

A/D power pins, with a 0.1µF ceramic chip capacitor placed as close as possible to each of the converter's power

supply pins. Leadless chip capacitors are preferred because they have low lead inductance.

While a single voltage source should be used for the analog and digital supplies of the ADC10321, this supply

should not be the supply that is used for other digital circuitry on the board.

As is the case with all high speed converters, the ADC10321 should be assumed to have little high frequency

power supply rejection. A clean analog power source should be used.

No pin should ever have a voltage on it that is in excess of the supply voltages or below ground, not even on a

transient basis. This can be a problem upon application of power to a circuit. Be sure that the supplies to circuits

driving the CLK, PD, OE, analog input and reference pins do not come up any faster than does the voltage at the

ADC10321 power pins.

Submit Documentation Feedback

Product Folder Links: ADC10321

ADC10321

www.ti.com

SNAS028F –JUNE 2000–REVISED MAY 2013

THE ADC10321 CLOCK

Although the ADC10321 is tested and its performance is specified with a 20MHz clock, it typically will function

with clock frequencies from 1MHz to 25MHz. Performance is best if the clock rise and fall times are 5ns or less.

If the CLK signal is interrupted, or its frequency is too low, the charge on internal capacitors can dissipate to the

point where the accuracy of the output data will degrade. This is what limits the minimum sample rate.

The duty cycle of the clock signal can affect the performance of the A/D Converter. Because achieving a precise

duty cycle is difficult, this device is designed to maintain performance over a range of duty cycles. While it is

specified and performance is specified with a 50% clock duty cycle, performance is typically maintained over a

clock duty cycle range of 45% to 55%.

The clock line should be series terminated at the source end in the characteristic impedance of that line. Use a

series resistor right after the source such that the source impedance plus that series resistor equals the

characteristic impedance of the clock line. This resistor should be as close to the source as possible, but in no

case should it be further away than

where

•

t_ris the rise time of the clock signal

t_PRis the propagation rate down the board.

(1)

For a Board of FR-4 material, t_PRis typically about 150 ps/inch.

To maintain a consistent impedance along the clock line, use stripline or microstrip techniques (see Application

Note AN-1113 [SNLA011]) and avoid the use of through-holes in the line.

It might also be necessary to terminate the ADC end of the clock line with a series RC to ground such that the

resistor value equals the characteristic impedance of the clock line and the capacitor value is

where

•

t_PRis again the propagation rate down the clock line

L is the length of the line in inches

Z_Ois the characteristic impedance of the clock line

(2)

LAYOUT AND GROUNDING

Proper routing of all signals and proper ground techniques are essential to ensure accurate conversion. Separate

analog and digital ground planes are required to meet data sheet limits. The analog ground plane should be low

impedance and free of noise form other parts of the system.

Each bypass capacitor should be located as close to the appropriate converter pin as possible and connected to

the pin and the appropriate ground plane with short traces. The analog input should be isolated from noisy signal

traces to avoid coupling of spurious signals into the input. Any external component (e.g., a filter capacitor)

connected between the converter's input and ground should be connected to a very clean point in the analog

ground return.

Figure 23 gives an example of a suitable layout, including power supply routing, ground plane separation, and

bypass capacitor placement. All analog circuitry (input amplifiers, filters, reference components, etc.) should be

placed on or over the analog ground plane. All digital circuitry and I/O lines should be over the digital ground

plane.

Digital and analog signal lines should never run parallel to each other in close proximity with each other. They

should only cross each other when absolutely necessary, and then only at 90° angles. Violating this rule can

result in digital noise getting into the input, which degrades accuracy and dynamic performance (THD, SNR,

SINAD).

Submit Documentation Feedback

Product Folder Links: ADC10321

ADC10321

SNAS028F –JUNE 2000–REVISED MAY 2013

www.ti.com

Figure 23. An acceptable layout pattern

DYNAMIC PERFORMANCE

The ADC10321 is ac tested and its dynamic performance is specified. To meet the published specifications, the

clock source driving the CLK input must be free of jitter. For best ac performance, isolating the ADC clock from

any digital circuitry should be done with adequate buffers, as with a clock tree. See Figure 24

Meeting dynamic specifications is also dependent upon keeping digital noise out of the input, as mentioned in

THE ANALOG INPUT and LAYOUT AND GROUNDING sections.

Figure 24. Isolating the ADC clock from digital circuitry

COMMON APPLICATION PITFALLS

Driving the inputs (analog or digital) beyond the power supply rails. For proper operation, all inputs should

not go more than 300mV beyond the supply pins. Exceeding these limits on even a transient basis can cause

faulty or erratic operation. It is not uncommon for high speed digital circuits (e.g., 74F and 74AC devices) to

exhibit undershoot that goes more than a volt below ground. A resistor of 50 to 100Ω in series with the offending

digital input will usually eliminate the problem.

Care should be taken not to overdrive the inputs of the ADC10321 (or any device) with a device that is powered

from supplies outside the range of the ADC10321 supply. Such practice may lead to conversion inaccuracies and

even to device damage.

Submit Documentation Feedback

Product Folder Links: ADC10321

ADC10321

www.ti.com

SNAS028F –JUNE 2000–REVISED MAY 2013

Attempting to drive a high capacitance digital data bus. The more capacitance the output drivers has to

charge for each conversion, the more instantaneous digital current is required from V_Dand DGND. These large

charging current spikes can couple into the analog section, degrading dynamic performance. Adequate

bypassing and maintaining separate analog and digital ground planes will reduce this problem on the board.

Buffering the digital data outputs (with an 74F541, for example) may be necessary if the data bus to be driven is

heavily loaded. Dynamic performance can also be improved by adding series resistors of 47Ω at each digital

output.

Driving the V_REF+ F pin or the V_REF− F pin with devices that can not source or sink the current required

by the ladder. As mentioned in REFERENCE INPUTS, be careful to see that any driving devices can source

sufficient current into the V_REF+ F pin and sink sufficient current from the V_REF− F pin. If these pins are not driven

with devices than can handle the required current, they will not be held stable and the converter output will

exhibit excessive noise.

Using a clock source with excessive jitter. This will cause the sampling interval to vary, causing excessive

output noise and a reduction in SNR performance. Simple gates with RC timing is generally inadequate.

Using the same voltage source for V_Dand other digital logic. As mentioned in POWER SUPPLY

CONSIDERATIONS, V_Dshould use the same power source used by V_A, but should be decoupled from V_A.

Submit Documentation Feedback

Product Folder Links: ADC10321

ADC10321

SNAS028F –JUNE 2000–REVISED MAY 2013

www.ti.com

REVISION HISTORY

Changes from Revision E (May 2013) to Revision F

Page

•

Changed layout of National Data Sheet to TI format .......................................................................................................... 21

Submit Documentation Feedback

Product Folder Links: ADC10321

PACKAGE OPTION ADDENDUM

www.ti.com

10-Dec-2020

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

ADC10321CIVT/NOPB

ACTIVE

LQFP

NEY

250

RoHS & Green

Level-3-260C-168 HR

-40 to 85

ADC10321

CIVT

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

23-Jun-2023

TRAY

L - Outer tray length without tabs

KO -

Outer

tray

height

W -

Outer

tray

width

Text

P1 - Tray unit pocket pitch

CW - Measurement for tray edge (Y direction) to corner pocket center

CL - Measurement for tray edge (X direction) to corner pocket center

Chamfer on Tray corner indicates Pin 1 orientation of packed units.

*All dimensions are nominal

Device

Package Package Pins SPQ Unit array

Max

matrix temperature

(°C)

L (mm)

Name

Type

(mm) (µm) (mm) (mm) (mm)

ADC10321CIVT/NOPB

NEY

LQFP

250

9 X 24

150

322.6 135.9 7620 12.2

11.1 11.25

Pack Materials-Page 1

PACKAGE OUTLINE

NEY0032A

LQFP - 1.6 mm max height

SCALE 1.800

PLASTIC QUAD FLATPACK

7.1

6.9

PIN 1 ID

7.1

6.9

9.4

TYP

8.6

0.27

0.17

OPTIONAL:

SHARP CORNERS EXCEPT

PIN 1 ID CORNER

28X 0.8

4X 5.6

32X

0.2

C A B

SEE DETAIL A

1.6 MAX

SEATING PLANE

0.09-0.20

TYP

0.25

GAGE PLANE

(1.4)

0.1

0.15

0.05

0.75

0.45

0 -7

DETAIL

DETAIL A

TYPICAL

4219901/A 10/2016

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. Reference JEDEC registration MS-026.

www.ti.com

EXAMPLE BOARD LAYOUT

NEY0032A

LQFP - 1.6 mm max height

PLASTIC QUAD FLATPACK

SYMM

32X (1.6)

32X (0.4)

SYMM

(8.5)

28X (0.8)

(R0.05) TYP

(8.5)

LAND PATTERN EXAMPLE

SCALE:8X

0.07 MAX

ALL AROUND

0.07 MIN

ALL AROUND

METAL

METAL UNDER

SOLDER MASK

OPENING

SOLDER MASK

DEFINED

NON SOLDER MASK

DEFINED

SOLDER MASK DETAILS

4219901/A 10/2016

NOTES: (continued)

4. Publication IPC-7351 may have alternate designs.

5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com

EXAMPLE STENCIL DESIGN

NEY0032A

LQFP - 1.6 mm max height

PLASTIC QUAD FLATPACK

SYMM

32X (1.6)

32X (0.4)

SYMM

(8.5)

28X (0.8)

(R0.05) TYP

(8.5)

SOLDER PASTE EXAMPLE

SCALE 8X

4219901/A 10/2016

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

7. Board assembly site may have different recommendations for stencil design.

www.ti.com

IMPORTANT NOTICE AND DISCLAIMER

TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE

DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”

AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY

IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD

PARTY INTELLECTUAL PROPERTY RIGHTS.

These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate

TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable

standards, and any other safety, security, regulatory or other requirements.

These resources are subject to change without notice. TI grants you permission to use these resources only for development of an

application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license

is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you

will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these

resources.

TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with

such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for

TI products.

TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

ADC10321CIVT/NOPB [TI]

相关型号：

ADC10321MDC

ADC10321MWC

ADC1034

ADC1034BIJ

ADC1034CIJ

ADC1034CIN

ADC1038

ADC1038BIJ

ADC1038BIWM

ADC1038CIJ

ADC1038CIWM

ADC1038CMJ