ADC10DV200CISQE/NOPB [TI]
双通道、10 位、200MSPS 模数转换器 (ADC) | NKA | 60 | -40 to 85;
| 型号： | ADC10DV200CISQE/NOPB |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 双通道、10 位、200MSPS 模数转换器 (ADC) | NKA | 60 | -40 to 85 转换器 模数转换器 |
| 文件： | 总26页 (文件大小：496K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ADC10DV200
www.ti.com
SNAS471A –FEBRUARY 2009–REVISED APRIL 2013
ADC10DV200 Dual 10-bit, 200 MSPS Low-Power A/D Converter with Parallel LVDS/CMOS
Outputs
Check for Samples: ADC10DV200
1
FEATURES
DESCRIPTION
The ADC10DV200 is a monolithic analog-to-digital
converter capable of converting two analog input
signals into 10-bit digital words at rates up to 200
Mega Samples Per Second (MSPS). The digital
output mode is selectable and can be either
differential LVDS or CMOS signals. This converter
uses a differential, pipelined architecture with digital
error correction and an on-chip sample-and-hold
circuit to minimize die size and power consumption
while providing excellent dynamic performance. A
unique sample-and-hold stage yields a full-power
bandwidth of 900MHz. Fabricated in core CMOS
process, the ADC10DV200 may be operated from a
single 1.8V power supply. The ADC10DV200
achieves approximately 9.6 effective bits at Nyquist
and consumes just 280mW at 170MSPS in CMOS
mode and 450mW at 200MSPS in LVDS mode. The
power consumption can be scaled down further by
reducing sampling rates.
2
•
Single 1.8V Power Supply Operation.
Power Scaling with Clock Frequency.
Internal Sample-and-Hold.
•
•
•
•
•
Internal or External Reference.
Power Down Mode.
Offset Binary or 2's Complement Output Data
Format.
•
•
LVDS or CMOS Output Signals.
60-pin WQFN Package, (9x9x0.8mm, 0.5mm
Pin-Pitch)
•
•
Clock Duty Cycle Stabilizer.
IF Sampling Bandwidth > 900MHz.
KEY SPECIFICATIONS
•
•
•
•
•
•
•
•
•
Resolution 10 Bits
Conversion Rate 200 MSPS
ENOB 9.6 bits (typ) @Fin=70 MHz
SNR 59.9 dBFS (typ) @Fin=70 MHz
SINAD 59.9 dBFS (typ) @Fin=70 MHz
SFDR 82 dBFS (typ) @Fin=70 MHz
LVDS Power 450mW (typ) @Fs=200 MSPS
CMOS Power 280mW (typ) @Fs=170 MSPS
Operating Temp. Range −40°C to +85°C.
APPLICATIONS
•
•
•
•
Communications
Medical Imaging
Portable Instrumentation
Digital Video
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2009–2013, Texas Instruments Incorporated
ADC10DV200
SNAS471A –FEBRUARY 2009–REVISED APRIL 2013
www.ti.com
Block Diagram
V
A+
A-
IN
S/H
10 Bit 200 MSPS
Pipeline Converter
V
IN
CLK+
CLK-
Timing
Control
10
DCS
Digital Error
Correction
V
RP
A
V
A
RM
V
RN
A
Data Out
Output
Clock
Output
Formatter
Output Buffer
(CMOS/LVDS)
Reference
V
DRDY
OR
REF
V
B
RP
V
RM
B
V
RN
B
Digital Error
Correction
10
10 Bit 200 MSPS
Pipeline Converter
V
B+
IN
S/H
V
B-
IN
Connection Diagram
1
45
V
AGND
DR
44
43
42
41
2
3
4
5
DB5/D7 -
DB4/D7 +
V
B-
IN
V
IN
B+
DB3/D6 -
DB2/D6 +
AGND
V
B
B
RM
6
7
8
9
40
ADC10DV200
60 LEAD WQFN
(TOP VIEW)
DB1/D5 -
DB0/D5 +
V
RP
39
38
37
36
35
34
33
32
31
V
B
RN
DRDYB/DRDY -
DRDYA/DRDY +
V
A
A
A
V
RN
10
11
PDA
V
RP
DA9/D4 -
V
RM
A
12
13
* Exposed pad must be soldered to ground
plane to ensure rated performance.
DA8/D4 +
AGND
A+
DA7/D3 -
DA6/D3 +
V
IN
14
15
V
A-
IN
V
DR
AGND
2
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Pin Descriptions and Equivalent Circuits
Pin No.
Symbol
Equivalent Circuit
Description
ANALOG I/O
13
3
VINA+
VINB+
V
A
Differential analog input pins. The differential full-scale input
signal level is 1.5VP-P with each input pin signal centered on a
14
2
VINA-
VINB-
common mode voltage, VCM
.
AGND
10
6
VRP
VRP
A
B
V
A
V
A
11
5
VRM
VRM
A
B
These pins should each be bypassed to AGND with a low ESL
(equivalent series inductance) 0.1 µF capacitor placed very
close to the pin to minimize stray inductance. An 0201 size 0.1
µF capacitor should be placed between VRP and VRN as close
to the pins as possible.
V
A
VRP and VRN should not be loaded. VRM may be loaded to 1mA
for use as a temperature stable 0.9V reference.
It is recommended to use VRM to provide the common mode
voltage, VCM for the differential analog inputs.
9
7
VRN
VRN
A
B
V
A
AGND
AGND
Reference Voltage select pin and external reference input. The
relationship between the voltage on the pin and the reference
voltage is as follows:
V
A
1.4V ≤ VREF ≤ VA
The internal 0.75V reference is
used.
0.2V ≤ VREF ≤ 1.4V
The external reference voltage is
used.
17
VREF
Note: When using an external
reference, be sure to bypass with
a 0.1µF capacitor to AGND as
close to the pin as possible.
AGND
AGND ≤ VREF ≤ 0.2V
The internal 0.5V reference is
used.
V
A
I
bias
Programming resistor for analog bias current. Nominally a
3.3kΩ to AGND for 200MSPS, or tie to VA to use the internal
frequency scaling current.
19
REXT
AGND
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Pin Descriptions and Equivalent Circuits (continued)
Pin No.
Symbol
Equivalent Circuit
Description
V
A
Data Format/Duty Cycle Correction selection pin.
(see Table 1)
20
DF/DCS
AGND
DIGITAL I/O
Clock input pins signal. The analog inputs are sampled on the
rising edge of this signal. The clock can be configured for
single-ended mode by shorting the CLK- pin to AGND. When in
differential mode, the common mode voltage for the clock is
internally set to 1.2V.
V
A
57
56
CLK +
CLK -
AGND
Two-state input controlling Power Down.
PD = VA, Power Down is enabled and power dissipation is
reduced.
36
53
PD_A
PD_B
V
A
PD = AGND, Normal operation.
Two-state input controlling Output Mode.
OUTSEL = VD, LVDS Output Mode.
OUTSEL = AGND, CMOS Output Mode.
23
OUTSEL
AGND
LVDS Output Mode
24, 25
26, 27
28, 29
32, 33
34, 35
39, 40
41, 42
43, 44
47, 48
49, 50
D0+,D0-
D1+, D1-
D2+, D2-
D3+, D3-
D4+, D4-
D5+, D5-
D6+, D6-
D7+, D7-
D8+, D8-
D9+, D9-
LVDS Output pairs for bits 0 through 9. A-channel and B-
channel digital LVDS outputs are interleaved. A channel is
ready at rising edge of DRDY and B channel is ready at the
falling edge of DRDY.
VDR
-
+
-
+
-
Data Ready Strobe. This signal is a LVDS DDR clock used to
capture the output data. A-channel data is valid on the rising
edge of this signal and B-channel data is valid on the falling
edge.
+
37
38
DRDY+
DRDY-
ADC over-range Signal. This signals timing is formatted
similarly to the data output signals. A channel is valid on DRDY
rising and B channel is valid on DRDY falling. This signal will go
high when the respective channel exceeds the allowable range
of the ADC. Nominally this signal will be low.
DRGND
51
52
OR+
OR-
4
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Pin Descriptions and Equivalent Circuits (continued)
Pin No.
Symbol
DA0-DA9
DB0-DB9
Equivalent Circuit
Description
CMOS Output Mode
Digital data output pins that make up the 10-bit conversion
result for Channel A. DA0 (pin 24) is the LSB, while DA9 (pin
35) is the MSB of the output word. Output levels are CMOS
compatible.
24-29,
32-35
V
V
A
DR
Digital data output pins that make up the 10-bit conversion
result for Channel B. DB0 (pin 39) is the LSB, while DB9 (pin
50) is the MSB of the output word. Output levels are CMOS
compatible.
39-44,
47-50
Data Ready Strobe for channel A. This signal is used to clock
the A-Channel output data. DRDYA is a SDR clock with same
frequency as CLK rate and data is valid on the rising edges.
37
DRDYA
DRDYB
Data Ready Strobe for channel B. This signal is used to clock
the B-Channel output data. DRDYB is a SDR clock with same
frequency as CLK rate and data is valid on the rising edges.
38
51
DRGND
DRGND
Overrange indicator for channel A. A high on this pin indicates
that the input exceeded the allowable range for the converter.
ORA
ORB
Overrange indicator for channel B. A high on this pin indicates
that the input exceeded the allowable range for the converter.
52
ANALOG POWER
Positive analog supply pins. These pins should be connected to
a quiet source and be bypassed to AGND with 0.1 µF
capacitors located close to the power pins.
8, 16, 18, 59,
60
VA
The ground return for the analog supply.
Exposed pad must be soldered to AGND to ensure rated
performance.
1, 4, 12, 15,
22, 55, 58, EP
AGND
DIGITAL POWER
Positive digital supply pins. These pins should be connected to
a quiet source and be bypassed to AGND with 0.1 µF
capacitors located close to the power pins.
21, 54
VD
Positive driver supply pin for the output drivers. This pin should
be connected to a quiet voltage source and be bypassed to
DRGND with a 0.1 µF capacitor located close to the power pin.
31, 45
30, 46
VDR
The ground return for the digital output driver supply. This pin
should be connected to the system digital ground.
DRGND
Table 1. Voltage on DF/DCS Pin and Corresponding Chip Response
Voltage on DF/DCS
Results
Suggestions
Min
Max
200mV
600 mV
1250 mV
VA
DF
1
DCS
0 mV
1
0
0
1
2's complement data, duty cycle correction on
Offset binary data, duty cycle correction off
2's complement data, duty cycle correction off
Offset binary data, duty cycle correction on
Tie to AGND
250 mV
750 mV
1400mV
0
Leave floating
1
0
Tie to VA
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
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(1) (2)(3)
Absolute Maximum Ratings
Supply Voltage (VA, VD VDR
)
−0.3V to 2.2V
Voltage on Any Pin
(Not to exceed 2.2V)
−0.3V to (VA +0.3V)
(4)
Input Current at Any Pin other than Supply Pins
±25 mA
±50 mA
(4)
Package Input Current
Max Junction Temp (TJ)
+150°C
Thermal Resistance (θJA
)
30°C/W
(5)
ESD Rating
Human Body Model
Machine Model
2500V
250V
Human Body Model
750V
Storage Temperature
−65°C to +150°C
Soldering process must comply with TI's Reflow Temperature Profile specifications. Refer to www.ti.com/packaging.(6)
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is specified to be functional, but do not ensure specific performance limits. For ensured specifications and test
conditions, see the Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance
characteristics may degrade when the device is not operated under the listed test conditions. Operation of the device beyond the
maximum Operating Ratings is not recommended.
(2) All voltages are measured with respect to GND = AGND = DRGND = 0V, unless otherwise specified.
(3) If Military/Aerospace specified devices are required, please contact the TI Sales Office/ Distributors for availability and specifications.
(4) When the input voltage at any pin exceeds the power supplies (that is, VIN < AGND, or VIN > VA), the current at that pin should be
limited to ±5 mA. The ±50 mA maximum package input current rating limits the number of pins that can safely exceed the power
supplies with an input current of ±5 mA to 10.
(5) Human Body Model is 100 pF discharged through a 1.5 kΩ resistor. Machine Model is 220 pF discharged through 0Ω resistor. Charged
device model simulates a pin slowly acquiring charge (such as from a device sliding down the feeder in an automated assembler) then
rapidly being discharged.
(6) Reflow temperature profiles are different for lead-free and non-lead-free packages.
(1) (2)
Operating Ratings
Operating Temperature
Supply Voltage (VA, VD, VDR
Clock Duty Cycle
−40°C ≤ TA ≤ +85°C
+1.7V to +1.9V
30/70 %
)
(DCS Enabled)
(DCS disabled)
48/52 %
VCM
0.8V to 1.0V
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is specified to be functional, but do not ensure specific performance limits. For ensured specifications and test
conditions, see the Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance
characteristics may degrade when the device is not operated under the listed test conditions. Operation of the device beyond the
maximum Operating Ratings is not recommended.
(2) All voltages are measured with respect to GND = AGND = DRGND = 0V, unless otherwise specified.
6
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Converter Electrical Characteristics
Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, VA = VD = VDR = +1.8V, fCLK = 200
MHz, CLK duty cycle = 50%, DCS = ON, Internal 0.75V Reference, LVDS Output. Typical values are for TA = 25°C. Boldface
(1) (2)
limits apply for TMIN ≤ TA ≤ TMAX. All other limits apply for TA = +25°C
Typical
Units
(Limits)
Symbol
Parameter
Conditions
Limits
(3)
STATIC CONVERTER CHARACTERISTICS
Resolution with No Missing Codes
10
Bits (min)
mLSB (max)
mLSB (max)
%FS (max)
%FS (max)
ppm/°C
INL
Integral Non Linearity
Differential Non Linearity
Positive Gain Error
±300
±170
0.57
0.60
13
±920
±430
3.11
2.72
DNL
PGE
NGE
Negative Gain Error
TC PGE Positive Gain Error Tempco
TC NGE Negative Gain Error Tempco
−40°C ≤ TA ≤ +85°C
−40°C ≤ TA ≤ +85°C
15
ppm/°C
Offset Error
VOFF
+0.75
-0.75
0.1
%FS (max)
ppm/°C
TC VOFF Offset Error Tempco
Under Range Output Code
Over Range Output Code
−40°C ≤ TA ≤ +85°C
4
0
0
1023
1023
REFERENCE AND ANALOG INPUT CHARACTERISTICS
1
0.85
V (min)
V (max)
VRM
VCM
Common Mode Output Voltage
0.9
Analog Input Common Mode Voltage
VIN Input Capacitance (each pin to
0.9
1
V
pF
pF
V
(CLK LOW)
(CLK HIGH)
VIN = 0.75 Vdc ± 0.5
V
CIN
(4)
AGND)
2.5
VRP
VRN
Internal Reference Top
1.33
0.55
0.78
Internal Reference Bottom
Internal Reference Accuracy
V
(VRP-VRN
)
V
EXT
VREF
0.5
1.0
V (Min)
V (max)
External Reference Voltage
(1) The inputs are protected as shown below. Input voltage magnitudes above VA or below GND will not damage this device, provided
current is limited per Note 3 under the Absolute Maximum Ratings. However, errors in the A/D conversion can occur if the input goes
above VA or below AGND.
V
A
I/O
To Internal Circuitry
AGND
(2) With a full scale differential input of 1.5VP-P , the 10-bit LSB is 1.465mV.
(3) Typical figures are at TA = 25°C and represent most likely parametric norms at the time of product characterization. The typical
specifications are not ensured.
(4) The input capacitance is the sum of the package/pin capacitance and the sample and hold circuit capacitance.
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Dynamic Converter Electrical Characteristics
Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, VA = VD = VDR = +1.8V, fCLK = 200
MHz, CLK duty cycle = 50%, DCS = ON, Internal 0.75V Reference, LVDS Output. Typical values are for TA = 25°C. Boldface
(1) (2)
limits apply for TMIN ≤ TA ≤ TMAX. All other limits apply for TA = +25°C
Units
Typical
Symbol
Parameter
Conditions
Limits
(Limits)
(3)
(4)
DYNAMIC CONVERTER CHARACTERISTICS, AIN= -1dBFS
(5)
FPBW
Full Power Bandwidth
-1 dBFS Input, −3 dB Corner
fIN = 10 MHz
900
59.9
59.9
82
MHz
dBFS
(6)
SNR
Signal-to-Noise Ratio
fIN = 70 MHz
59
70
dBFS (min)
dBFS
fIN = 10 MHz
(7)
SFDR
ENOB
H2
Spurious Free Dynamic Range
Effective Number of Bits
fIN = 70 MHz
82
dBFS (min)
Bits
fIN = 10 MHz
9.65
9.65
-94
fIN = 70 MHz
9.48
-70
-70
58.9
Bits (min)
dBFS
fIN = 10 MHz
Second Harmonic Distortion
Third Harmonic Distortion
fIN = 70 MHz
-94
dBFS (min)
dBFS
fIN = 10 MHz
-85
H3
fIN = 70 MHz
-84
dBFS (min)
dBFS
fIN = 10 MHz
59.8
59.8
(8)
SINAD
IMD
Signal-to-Noise and Distortion Ratio
fIN = 70 MHz
dBFS (min)
fIN1 = 69 MHz AIN1 = -7 dBFS
fIN2 = 70 MHz AIN2 = -7 dBFS
fIN1 = 69 MHz AIN1 = -1 dBFS
fIN2 = 70MHz AIN2 = -1 dBFS
(5)
Intermodulation Distortion
93
97
dBFS
dBFS
(5)
Cross Talk
(1) The inputs are protected as shown below. Input voltage magnitudes above VA or below GND will not damage this device, provided
current is limited per Note 4 under the Absolute Maximum Ratings. However, errors in the A/D conversion can occur if the input goes
above VA or below AGND.
V
A
I/O
To Internal Circuitry
AGND
(2) With a full scale differential input of 1.5VP-P , the 10-bit LSB is 1.465mV.
(3) Typical figures are at TA = 25°C and represent most likely parametric norms at the time of product characterization. The typical
specifications are not ensured.
(4) Units of dBFS indicates the value that would be attained with a full-scale input signal.
(5) This parameter is specified by design and/or characterization and is not tested in production.
(6) SNR minimum and typical values are for LVDS mode. Typical values for CMOS mode are typically 0.2dBFS lower.
(7) SFDR minimum and typical values are for LVDS mode. Typical values for CMOS mode are typically 2dBFS lower.
(8) SINAD minimum and typical values are for LVDS mode. Typical values for CMOS mode are typically 0.1dBFS lower.
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Power Supply Electrical Characteristics
Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, VA = VD = VDR = +1.8V, fCLK = 200
MHz, CLK duty cycle = 50%, DCS = ON, Internal 0.75V Reference, LVDS Output. Typical values are for TA = 25°C. Boldface
(1) (2)
limits apply for TMIN ≤ TA ≤ TMAX. All other limits apply for TA = 25°C
Typical
Units
(Limits)
Symbol
Parameter
Conditions
Limits
(3)
LVDS OUTPUT MODE
Full Operation, Internal Bias
Full Operation, External 3.3kΩ Bias
Full Operation
160
148
36
mA
IA
Analog Supply Current
184
43
mA (max)
mA (max)
mA (max)
mW
ID
Digital Supply Current
IDR
Output Driver Supply Current
64
80
Internal Bias
473
450
57
Power Consumption
External 3.3kΩ Bias
PDA=PDB=VA
524
mW (max)
mW
Power Down Power Consumption
(4)
CMOS OUTPUT MODE
Full Operation, Internal Bias
Full Operation, External 3.3kΩ Bias
Full Operation
138
124
31
IA
ID
Analog Supply Current
mA
mA
Digital Supply Current
Internal Bias
310
280
60
Power Consumption
mW
mW
External 3.3kΩ Bias
PDA=PDB=VA
Power Down Power Consumption
(1) The inputs are protected as shown below. Input voltage magnitudes above VA or below GND will not damage this device, provided
current is limited per Note 4 under the Absolute Maximum Ratings. However, errors in the A/D conversion can occur if the input goes
above VA or below AGND.
V
A
I/O
To Internal Circuitry
AGND
(2) With a full scale differential input of 1.5VP-P , the 10-bit LSB is 1.465mV.
(3) Typical figures are at TA = 25°C and represent most likely parametric norms at the time of product characterization. The typical
specifications are not ensured.
(4) CMOS Specifications are for FCLK = 170 MHz.
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Input/Output Logic Electrical Characteristics
Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, VA = VD = VDR = +1.8V, fCLK = 200
MHz, CLK duty cycle = 50%, DCS = ON, Internal 0.75V Reference. Typical values are for TA = 25°C. Boldface limits apply
(1) (2)
for TMIN ≤ TA ≤ TMAX. All other limits apply for TA = 25°C
Typical
Units
(Limits)
Symbol
Parameter
Conditions
Limits
(3)
DIGITAL INPUT CHARACTERISTICS (PD_A,PD_B,OUTSEL)
(4)
VIN(1)
VIN(0)
IIN(1)
IIN(0)
CIN
Logical “1” Input Voltage
Logical “0” Input Voltage
Logical “1” Input Current
Logical “0” Input Current
Digital Input Capacitance
VA = 1.9V
VA = 1.7V
VIN = 1.8V
VIN = 0V
0.89
0.67
V (min)
V (max)
µA
(4)
10.6
-7.6
2
µA
pF
LVDS OUTPUT CHARACTERISTICS (D0-D9,DRDY,OR)
(4)
VOD
LVDS differential output voltage
See
330
0
mVP-P
mV
Output Differential Voltage
Unbalance
±VOD
50
50
(4)
VOS
±VOS
RL
LVDS common-mode output voltage See
Offset Voltage Unbalance
1.25
V
mV
Ω
Intended Load Resistance
100
(5)
CMOS OUTPUT CHARACTERISTICS (DA0-DA9,DB0-DB9,DRDY,OR)
VOH
Logical "1" Output Voltage
Logical "0" Output Voltage
VDR = 1.8V (Unloaded)
VDR = 1.8V (Unloaded)
1.8
0
V
V
VOL
+IOSC
-IOSC
COUT
Output Short Circuit Source Current VOUT = 0V
-20
20
2
mA
mA
pF
Output Short Circuit Sink Current
Digital Output Capacitance
VOUT = VDR
(1) The inputs are protected as shown below. Input voltage magnitudes above VA or below GND will not damage this device, provided
current is limited per Note 4 under the Absolute Maximum Ratings. However, errors in the A/D conversion can occur if the input goes
above VA or below AGND.
V
A
I/O
To Internal Circuitry
AGND
(2) With a full scale differential input of 1.5VP-P , the 10-bit LSB is 1.465mV.
(3) Typical figures are at TA = 25°C and represent most likely parametric norms at the time of product characterization. The typical
specifications are not ensured.
(4) This parameter is specified by design and/or characterization and is not tested in production.
(5) CMOS Specifications are for FCLK = 170 MHz.
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Timing and AC Characteristics
Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, VA = VD = VDR = +1.8V, fCLK = 200
MHz, CLK duty cycle = 50%, DCS = ON, Internal 0.75V Reference. Typical values are for TA = 25°C. Timing measurements
(1)
are taken at 50% of the signal amplitude. Boldface limits apply for TMIN ≤ TA ≤ TMAX. All other limits apply for TA = 25°C
(2)
Typical
Units
(Limits)
Symbol
Parameter
Conditions
Limits
(3)
LVDS OUTPUT MODE
Maximum Clock Frequency
200
MHz (max)
MHz (min)
DCS On
DCS Off
65
45
Minimum Clock Frequency
DCS On
DCS Off
1.5
2.4
tCH
Clock High Time
Clock Low Time
Conversion Latency
ns (min)
ns (min)
DCS On
DCS Off
1.5
2.4
tCL
5/5.5
(A/B)
tCONV
Clock Cycles
tODA
tODB
tSU
Output Delay of CLK to A-Channel Data
Output Delay of CLK to B-Channel Data
Data Output Setup Time
Data Output Hold Time
Relative to rising edge of CLK
Relative to falling edge of CLK
Relative to DRDY
2.7
2.7
1.2
1.2
0.7
0.3
20
1.46
1.46
0.7
ns (min)
ns (min)
ns (min)
ns (min)
ns
tH
Relative to DRDY
0.7
tAD
Aperture Delay
tAJ
Aperture Jitter
ps rms
ps
tSKEW
Data-Data Skew
470
(4) (5)
CMOS OUTPUT MODE
Maximum Clock Frequency
170
MHz
MHz
DCS On
DCS Off
65
25
Minimum Clock Frequency
Clock High Time
DCS On
DCS Off
1.76
2.82
tCH
ns
DCS On
DCS Off
1.76
2.82
tCL
ns
tCONV
tOD
Conversion Latency
5.5
Clock Cycles
3.15
5.81
ns (min)
ns (max)
Output Delay of CLK to DATA
Relative to falling edge of CLK
4.5
tSU
tH
tAD
tAJ
Data Output Setup Time(5)
Data Output Hold Time(5)
Aperture Delay
Relative to DRDY
Relative to DRDY
2.5
3.4
0.7
0.3
1.79
2.69
ns (min)
ns (min)
ns
Aperture Jitter
ps rms
(1) The inputs are protected as shown below. Input voltage magnitudes above VA or below GND will not damage this device, provided
current is limited per Note 4 under the Absolute Maximum Ratings. However, errors in the A/D conversion can occur if the input goes
above VA or below AGND.
V
A
I/O
To Internal Circuitry
AGND
(2) With a full scale differential input of 1.5VP-P , the 10-bit LSB is 1.465mV.
(3) Typical figures are at TA = 25°C and represent most likely parametric norms at the time of product characterization. The typical
specifications are not ensured.
(4) CMOS Specifications are for FCLK = 170 MHz.
(5) This parameter is specified by design and/or characterization and is not tested in production.
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Specification Definitions
APERTURE DELAY is the time after the falling edge of the clock to when the input signal is acquired or held for
conversion.
APERTURE JITTER (APERTURE UNCERTAINTY) is the variation in aperture delay from sample to sample.
Aperture jitter manifests itself as noise in the output. The amount of SNR reduction can be calculated as
SNR Reduction = 20 x log10[½ x π x ƒA x tj]
(1)
CLOCK DUTY CYCLE is the ratio of the time during one cycle that a repetitive digital waveform is high to the
total time of one period. The specification here refers to the ADC clock input signal.
COMMON MODE VOLTAGE (VCM) is the common DC voltage applied to both input terminals of the ADC.
CONVERSION LATENCY is the number of clock cycles between initiation of conversion and when that data is
presented to the output driver stage. Data for any given sample is available at the output pins the Pipeline Delay
plus the Output Delay after the sample is taken. New data is available at every clock cycle, but the data lags the
conversion by the pipeline delay.
CROSSTALK is coupling of energy from one channel into the other channel.
DIFFERENTIAL NON-LINEARITY (DNL) is the measure of the maximum deviation from the ideal step size of 1
LSB.
EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE BITS) is another method of specifying Signal-to-Noise
and Distortion Ratio or SINAD. ENOB is defined as (SINAD - 1.76) / 6.02 and says that the converter is
equivalent to a perfect ADC of this (ENOB) number of bits.
FULL POWER BANDWIDTH is a measure of the frequency at which the reconstructed output fundamental
drops 3 dB below its low frequency value for a full scale input.
GAIN ERROR is the deviation from the ideal slope of the transfer function. It can be calculated as:
Gain Error = Positive Full Scale Error − Negative Full Scale Error
(2)
(3)
It can also be expressed as Positive Gain Error and Negative Gain Error, which are calculated as:
PGE = Positive Full Scale Error - Offset Error NGE = Offset Error - Negative Full Scale Error
INTEGRAL NON LINEARITY (INL) is a measure of the deviation of each individual code from a best fit straight
line. The deviation of any given code from this straight line is measured from the center of that code value.
INTERMODULATION DISTORTION (IMD) is the creation of additional spectral components as a result of two
sinusoidal frequencies being applied to the ADC input at the same time. It is defined as the ratio of the power in
the intermodulation products to the total power in the original frequencies. IMD is usually expressed in dBFS.
LSB (LEAST SIGNIFICANT BIT) is the bit that has the smallest value or weight of all bits. This value is VFS/2n,
where “VFS” is the full scale input voltage and “n” is the ADC resolution in bits.
MISSING CODES are those output codes that will never appear at the ADC outputs. The ADC is ensured not to
have any missing codes.
MSB (MOST SIGNIFICANT BIT) is the bit that has the largest value or weight. Its value is one half of full scale.
NEGATIVE FULL SCALE ERROR is the difference between the actual first code transition and its ideal value of
½ LSB above negative full scale.
OFFSET ERROR is the difference between the two input voltages [(VIN+) – (VIN-)] required to cause a transition
from code 511 to 512.
OUTPUT DELAY is the time delay after the falling edge of the clock before the data update is presented at the
output pins.
PIPELINE DELAY (LATENCY) See CONVERSION LATENCY.
POSITIVE FULL SCALE ERROR is the difference between the actual last code transition and its ideal value of
1½ LSB below positive full scale.
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POWER SUPPLY REJECTION RATIO (PSRR) is a measure of how well the ADC rejects a change in the power
supply voltage. PSRR is the ratio of the Full-Scale output of the ADC with the supply at the minimum DC supply
limit to the Full-Scale output of the ADC with the supply at the maximum DC supply limit, expressed in dB.
SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in dB, of the rms value of the input signal to the rms
value of the sum of all other spectral components below one-half the sampling frequency, not including
harmonics or DC.
SIGNAL TO NOISE PLUS DISTORTION (S/N+D or SINAD) Is the ratio, expressed in dB, of the rms value of the
input signal to the rms value of all of the other spectral components below half the clock frequency, including
harmonics but excluding d.c.
SPURIOUS FREE DYNAMIC RANGE (SFDR) is the difference, expressed in dB, between the rms values of the
input signal and the peak spurious signal, where a spurious signal is any signal present in the output spectrum
that is not present at the input.
TOTAL HARMONIC DISTORTION (THD) is the ratio, expressed in dB, of the rms total of the first six harmonic
levels at the output to the level of the fundamental at the output. THD is calculated as
(4)
where f1 is the RMS power of the fundamental (output) frequency and f2 through f7 are the RMS power of the first
six harmonic frequencies in the output spectrum.
SECOND HARMONIC DISTORTION (2ND HARM) is the difference expressed in dB, between the RMS power in
the input frequency at the output and the power in its 2nd harmonic level at the output.
THIRD HARMONIC DISTORTION (3RD HARM) is the difference, expressed in dB, between the RMS power in
the input frequency at the output and the power in its 3rd harmonic level at the output.
Timing Diagrams
V
V
A
B
IN
t
AD
IN
CLK N
CLK N+5
1/f
CLK
CLK
t
t
CL
CH
Latency = 5
CLK Cycles
DRDY
(DDR)
t
SU
t
ODB
t
ODA
t
H
D9-D0
AN-1
BN-1
AN
BN
AN+1
BN+1
AN+2
BN+2
AN+3
Figure 1. LVDS Output Timing
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V
V
A
B
IN
t
AD
IN
CLK N
CLK N+5
1/f
CLK
CLK
t
CH
Latency=5.5
CLK Cycles
t
CL
DRDYA
(DDR)
t
OD
t
t
H
SU
Data N+1
Data N+2
Data N
Data N-1
DA9-DA0
DRDYB
(DDR)
Data N+1
Data N
Data N-1
DB9-DB0
Figure 2. CMOS Output Timing
Transfer Characteristic
Output Code
1023
1022
MID-SCALE
POINT
POSITIVE
FULL-SCALE
TRANSITION
(V
)
FS+
512
NEGATIVE
FULL-SCALE
TRANSITION
OFFSET
ERROR
(VFS-)
(V +) < (V -)
IN IN
(V +) > (V -)
IN IN
2
1
0
0.0V
-1 * V
1 * V
REF
REF
Analog Input Voltage (V +) - (V -)
IN IN
Figure 3. Transfer Characteristic
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Typical Performance Characteristics DNL, INL
Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, VA = VD = VDR = +1.8V, fCLK = 200
MHz, 50% Duty Cycle, DCS Enabled, LVDS Output, VCM = VRM, TA = 25°C.
DNL
INL
Figure 4.
Figure 5.
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Typical Performance Characteristics
Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, VA = VD = VDR = +1.8V, fCLK = 200
MHz, 50% Duty Cycle, DCS disabled, LVDS Output, VCM = VRM, fIN = 70 MHz, TA = 25°C.
SNR, SINAD, SFDR
Distortion
vs.
VA
vs.
VA
Figure 6.
Figure 7.
SNR, SINAD, SFDR
vs.
Distortion
vs.
Temperature
Temperature
Figure 8.
Figure 9.
SNR, SINAD, SFDR
vs.
Clock Duty Cycle, fIN = 10MHz
Distortion
vs.
Clock Duty Cycle, fIN = 10MHz
Figure 10.
Figure 11.
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Typical Performance Characteristics (continued)
Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, VA = VD = VDR = +1.8V, fCLK = 200
MHz, 50% Duty Cycle, DCS disabled, LVDS Output, VCM = VRM, fIN = 70 MHz, TA = 25°C.
SNR, SINAD, SFDR
Distortion
vs.
vs.
Ext. Reference Voltage
Ext. Reference Voltage
Figure 12.
Figure 13.
SNR, SINAD, SFDR
vs.
Clock Frequency
Distortion
vs.
Clock Frequency
Figure 14.
Figure 15.
SNR, SINAD, SFDR
Distortion
vs.
Ext. VCM
vs.
Ext. VCM
Figure 16.
Figure 17.
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Typical Performance Characteristics (continued)
Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, VA = VD = VDR = +1.8V, fCLK = 200
MHz, 50% Duty Cycle, DCS disabled, LVDS Output, VCM = VRM, fIN = 70 MHz, TA = 25°C.
Spectral Response @ 10 MHz Input
Spectral Response @ 70 MHz Input
Figure 18.
Figure 19.
Spectral Response @ 170 MHz Input
IMD, fIN1 = 69 MHz, fIN2 = 70 MHz
Figure 20.
Figure 21.
Total Power
vs.
Clock Frequency, fIN = 10 MHz
Figure 22.
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FUNCTIONAL DESCRIPTION
Operating on a single +1.8V supply, the ADC10DV200 digitizes two differential analog input signals to 10 bits,
using a differential pipelined architecture with error correction circuitry and an on-chip sample-and-hold circuit to
ensure maximum performance. The user has the choice of using an internal 0.75V stable reference, or using an
external 0.75V reference. Any external reference is buffered on-chip to ease the task of driving that pin. Duty
cycle stabilization and output data format are selectable using the quad state function DF/DCS pin (pin 20). The
output data can be set for offset binary or two's complement.
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APPLICATIONS INFORMATION
OPERATING CONDITIONS
We recommend that the following conditions be observed for operation of the ADC10DV200:
1.7V ≤ VA ≤ 1.9V
1.7V ≤ VDR ≤ VA
45 MHz ≤ fCLK ≤ 200 MHz, with DCS off
65 MHz ≤ fCLK ≤ 200 MHz, with DCS on
0.75V internal reference
VREF = 0.75V (for an external reference)
VCM = 0.9V (from VRM
ANALOG INPUTS
Signal Inputs
)
Differential Analog Input Pins
The ADC10DV200 has a pair of analog signal input pins for each of two channels. VIN+ and VIN− form a
differential input pair. The input signal, VIN, is defined as
VIN = (VIN+) – (VIN−)
(5)
Figure 23shows the expected input signal range. Note that the common mode input voltage, VCM, should be
0.9V. Using VRM (pins 5,11) for VCM will ensure the proper input common mode level for the analog input signal.
The positive peaks of the individual input signals should each never exceed 2.2V. Each analog input pin of the
differential pair should have a maximum peak-to-peak voltage of 1.5V, be 180° out of phase with each other and
be centered around VCM.The peak-to-peak voltage swing at each analog input pin should not exceed the 1V or
the output data will be clipped.
Figure 23. Expected Input Signal Range
For single frequency sine waves the full scale error in LSB can be described as approximately
EFS = 1024 ( 1 - sin (90° + dev))
(6)
Where dev is the angular difference in degrees between the two signals having a 180° relative phase relationship
to each other (see Figure 24). For single frequency inputs, angular errors result in a reduction of the effective full
scale input. For complex waveforms, however, angular errors will result in distortion.
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Figure 24. Angular Errors Between the Two Input Signals Will Reduce the Output Level or Cause
Distortion
It is recommended to drive the analog inputs with a source impedance less than 100Ω. Matching the source
impedance for the differential inputs will improve even ordered harmonic performance (particularly second
harmonic).
Table 2 indicates the input to output relationship of the ADC10DV200.
Table 2. Input to Output Relationship
+
−
VIN
VIN
Binary Output
00 0000 0000
01 0000 0000
10 0000 0000
11 0000 0000
11 1111 1111
2’s Complement Output
10 0000 0000
V
CM − VREF/2
CM − VREF/4
VCM
VCM + VREF/2
VCM + VREF/4
VCM
Negative Full-Scale
Mid-Scale
V
11 0000 0000
00 0000 0000
VCM + VREF/4
VCM + VREF/2
V
CM − VREF/4
CM − VREF/2
01 0000 0000
V
01 1111 1111
Positive Full-Scale
Driving the Analog Inputs
The VIN+ and the VIN− inputs of the ADC10DV200 have an internal sample-and-hold circuit which consists of an
analog switch followed by a switched-capacitor amplifier.
Figure 25 and Figure 26 show examples of single-ended to differential conversion circuits. The circuit in
Figure 25 works well for input frequencies up to approximately 70MHz, while the circuit in Figure 26 works well
above 70MHz.
V
IN
0.1 mF
50W
20W
ADT1-1WT
ADC
Input
18 pF
0.1 mF
0.1 mF
20W
V
RM
Figure 25. Low Input Frequency Transformer Drive Circuit
V
IN
30W
27 pF
ETC1-1-13
25W
25W
ADC
Input
0.1 mF
0.1 mF
30W
ETC1-1-13
V
RM
0.1 mF
Figure 26. High Input Frequency Transformer Drive Circuit
One short-coming of using a transformer to achieve the single-ended to differential conversion is that most RF
transformers have poor low frequency performance. A differential amplifier can be used to drive the analog inputs
for low frequency applications. The amplifier must be fast enough to settle from the charging glitches on the
analog input resulting from the sample-and-hold operation before the clock goes high and the sample is passed
to the ADC core.
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Input Common Mode Voltage
The input common mode voltage, VCM, should be in the range of 0.8V to 1.0V and be a value such that the peak
excursions of the analog signal do not go more negative than ground or more positive than the VA supply. It is
recommended to use VRM (pins 5,11) as the input common mode voltage.
If the ADC10DV200 is operated with VA=1.8V, a resistor of approximately 1KΩ should be used from the VRM pin
to AGND. This will help maintain stability over the entire temperature range when using a high supply voltage.
Reference Pins
The ADC10DV200 is designed to operate with an internal or external voltage reference. The voltage on the VREF
pin selects the source and level of the reference voltage. An internal 0.75 Volt reference is used when a voltage
between 1.4 V to VA is applied to the VREF pin. An internal 0.5 Volt reference is used when a voltage between
0.2V and AGND is applied to the VREF pin. If a voltage between 0.2V and 1.4V is applied to the VREF pin, then
that voltage is used for the reference. SNR will improve without a significant degradation in SFDR for VREF=1.0V.
SNR will decrease if VREF=0.5V, yet linearity will be maintained. If using an external reference the VREF pin
should be bypassed to ground with a 0.1 µF capacitor close to the reference input pin.
It is important that all grounds associated with the reference voltage and the analog input signal make connection
to the ground plane at a single, quiet point to minimize the effects of noise currents in the ground path.
The Reference Bypass Pins (VRP, VRM, and VRN) for channels A and B are made available for bypass purposes.
These pins should each be bypassed to AGND with a low ESL (equivalent series inductance) 0.1 µF capacitor
placed very close to the pin to minimize stray inductance. A 0.1 µF capacitor should be placed between VRP and
VRN as close to the pins as possible. This configuration is shown in Figure 27. It is necessary to avoid reference
oscillation, which could result in reduced SFDR and/or SNR. VRM may be loaded to 1mA for use as a
temperature stable 0.9V reference. The remaining pins should not be loaded.
Smaller capacitor values than those specified will allow faster recovery from the power down mode, but may
result in degraded noise performance. Loading any of these pins, other than VRM may result in performance
degradation.
The nominal voltages for the reference bypass pins are as follows:
VRM = 0.9 V
VRP = 1.33 V
VRN = 0.55 V
DF/DCS Pin
Duty cycle stabilization and output data format are selectable using this quad state function pin. When enabled,
duty cycle stabilization can compensate for clock inputs with duty cycles ranging from 30% to 70% and generate
a stable internal clock, improving the performance of the part. See Table 1 for DF/DCS voltage vs output format
description. DCS mode of operation is limited to 65 MHz ≤ fCLK ≤ 200 MHz.
DIGITAL INPUTS
Digital CMOS compatible inputs consist of CLK, PD_A, PD_B, and OUTSEL.
Clock Input
The CLK controls the timing of the sampling process. To achieve the optimum noise performance, the clock input
should be driven with a stable, low jitter clock signal in the range indicated in the Electrical Table. The clock input
signal should also have a short transition region. This can be achieved by passing a low-jitter sinusoidal clock
source through a high speed buffer gate. The trace carrying the clock signal should be as short as possible and
should not cross any other signal line, analog or digital, not even at 90°.
If the clock is interrupted, or its frequency is too low, the charge on the internal capacitors can dissipate to the
point where the accuracy of the output data will degrade. This is what limits the minimum sample rate.
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The clock line should be terminated at its source in the characteristic impedance of that line. Take care to
maintain a constant clock line impedance throughout the length of the line. Refer to Application Note AN-905
(SNLA035) for information on setting characteristic impedance. It is highly desirable that the the source driving
the ADC clock pins only drive that pin.
The duty cycle of the clock signal can affect the performance of the A/D Converter. Because achieving a precise
duty cycle is difficult, the ADC10DV200 has a Duty Cycle Stabilizer.
DIGITAL OUTPUTS
Digital outputs consist of the LVDS signals D0-D9, OR, and DRDY.
The ADC10DV200 has 12 LVDS compatible data output pins: 10 data output pins corresponding to the
converted input value, a data ready (DRDY) signal that should be used to capture the output data and an over-
range indicator (OR) which is set high when the sample amplitude exceeds the 10-Bit conversion range. Valid
data is present at these outputs while the PD pin is low. A-Channel data should be captured and latched with the
rising edge of the DRDY signal and B-Channel data should be captured and latched with the falling edge of
DRDY.
To minimize noise due to output switching, the load currents at the digital outputs should be minimized. This can
be achieved by keeping the PCB traces less than 2 inches long; longer traces are more susceptible to noise. The
characteristic impedance of the LVDS traces should be 100Ω, and the effective capacitance < 10pF. Try to place
the 100Ω termination resistor as close to the receiving circuit as possible. (See Figure 27)
+1.8V
+1.8V
+1.8V
2x 0.1 mF
2x 0.1 mF
5x 0.1 mF
+
10 mF
0.1 mF
17
11
V
V
REF
A
RM
52
51
OR-
+
-
0.1 mF
10
9
100
100
V
A
RP
RN
OR+
0.1 mF
0.1 mF
0.1 mF
38
37
V
A
DRDY-
DRDY+
+
-
50
5
6
7
V
V
V
B
RM
0.1 mF
0.1 mF
50
49
48
47
44
43
42
41
40
39
35
34
33
32
29
28
27
26
25
24
B
RP
RN
D9-
+
-
0.1 mF
0.1 mF
100
100
100
100
100
100
100
100
100
100
D9+
B
V
20
IN_A
D8-
D8+
D7-
+
-
0.1 mF
0.1 mF
1
ADC10DV200
0.1 mF
18 pF
+
-
13
14
D7+
D6-
D6+
D5-
V
A+
A-
IN
20
+
-
V
IN
Receiver
ADT1-1WT
+
-
50
D5+
D4-
+
-
D4+
V
20
20
IN_B
0.1 mF
0.1 mF
D3-
D3+
D2-
+
-
1
0.1 mF
18 pF
+
-
3
2
V
V
B+
B-
IN
IN
D2+
D1-
D1+
D0-
D0+
+
-
ADT1-1WT
57
56
+
-
CLK+
CLK-
Crystal
Oscillator
20
36
53
23
DF/DCS
DF/DCS
PD_A
PD_A
PD_B
PD_B
OUTSEL
OUTSEL
Figure 27. Application Circuit
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POWER SUPPLY CONSIDERATIONS
The power supply pins should be bypassed with a 0.1 µF capacitor and with a 100 pF ceramic chip capacitor
close to each power pin. Leadless chip capacitors are preferred because they have low series inductance.
As is the case with all high-speed converters, the ADC10DV200 is sensitive to power supply noise. Accordingly,
the noise on the analog supply pin should be kept below 100 mVP-P
.
No pin should ever have a voltage on it that is in excess of the supply voltages, not even on a transient basis. Be
especially careful of this during power turn on and turn off.
24
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SNAS471A –FEBRUARY 2009–REVISED APRIL 2013
REVISION HISTORY
Changes from Original (April 2013) to Revision A
Page
•
Changed layout of National Data Sheet to TI format .......................................................................................................... 24
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相关型号：
ADC1109
IC 1-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, SMA25, MODULE-25, Analog to Digital Converter
ADI
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