ADC122S625 [TI]
双路 12 位、50 kSPS 至 200 kSPS、同步采样模数转换器;
| 型号： | ADC122S625 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 双路 12 位、50 kSPS 至 200 kSPS、同步采样模数转换器 转换器 模数转换器 |
| 文件： | 总30页 (文件大小：955K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ADC122S625
www.ti.com
SNAS451A –FEBRUARY 2008–REVISED MARCH 2013
ADC122S625 Dual 12-Bit, 50 kSPS to 200 kSPS, Simultaneous Sampling A/D Converter
Check for Samples: ADC122S625
1
FEATURES
DESCRIPTION
The ADC122S625 is a dual 12-bit, 50 kSPS to 200
kSPS simultaneous sampling Analog-to-Digital (A/D)
converter. The analog inputs on both channels are
sampled simultaneously to preserve their relative
phase information to each other. The converter is
23
•
True Simultaneous Sampling Differential
Inputs
•
Specified Performance from 50 kSPS to 200
kSPS
based on
a
successive-approximation register
•
•
•
•
External Reference
architecture where the differential nature of the
analog inputs is maintained from the internal track-
and-hold circuits throughout the A/D converter to
provide excellent common-mode signal rejection. The
ADC122S625 features an external reference that can
be varied from 1.0V to VA.
Wide Input Common-Mode Voltage Range
Single High-Speed Serial Data Output
Operating Temperature Range of −40°C to
+105°C
•
SPI™/ QSPI™/MICROWIRE/DSP Compatible
Serial Interface
The ADC122S625's serial data output is binary 2's
complement and is compatible with several
standards, such as SPI™, QSPI™, MICROWIRE™,
and many common DSP serial interfaces. The serial
clock (SCLK) and chip select bar (CS) are shared by
both channels.
APPLICATIONS
•
•
•
•
•
•
•
Motor Control
Power Meters/Monitors
Multi-Axis Positioning Systems
Instrumentation and Control Systems
Data Acquisition Systems
Medical Instruments
Operating from a single 5V analog supply and a
reference voltage of 2.5V, the total power
consumption while operating at 200 kSPS is typically
8.6 mW. With the ADC122S625 operating in power-
down mode, the power consumption reduces to 2.6
µW. The differential input, low power consumption,
and small size make the ADC122S625 ideal for direct
connection to sensors in motor control applications.
Direct Sensor Interface
KEY SPECIFICATIONS
•
•
•
•
•
•
•
Conversion Rate: 50 kSPS to 200 kSPS
INL: ±1 LSB (max)
Operation is specified over the industrial temperature
range of −40°C to +105°C and clock rates of 1.6 MHz
to 6.4 MHz. The ADC122S625 is available in a 10-
lead VSSOP package.
DNL: ±0.95 LSB (max)
SNR: 71 dBc (min)
Connection Diagram
THD: -72 dBc (min)
ENOB: 11.25 bits (min)
Power Consumption at 200 kSPS
V
10
9
CS
1
2
3
4
5
REF
–
Converting, VA = 5V, VREF = 2.5V: 8.6 mW
(typ)
CHA+
CHA-
CHB-
CHB+
SCLK
ADC122S625
8
D
OUT
–
Power-Down, VA = 5V, VREF = 2.5V: 2.6 µW
(typ)
7
V
A
6
GND
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
3
SPI, QSPI are trademarks of Motorola, Incorporated.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2008–2013, Texas Instruments Incorporated
ADC122S625
SNAS451A –FEBRUARY 2008–REVISED MARCH 2013
www.ti.com
Block Diagram
SAR
CHA+
CHARGE
REDISTRIBUTION
DAC
S/H
CHA-
COMPARATOR
SERIAL
INTERFACE
SAR
V
REF
CHB-
CHARGE
REDISTRIBUTION
DAC
S/H
CHB+
COMPARATOR
PIN DESCRIPTIONS AND EQUIVALENT CIRCUITS
Pin No.
Symbol
Description
Voltage Reference Input. A voltage reference between 1V and VA must be applied to this
input. VREF must be decoupled to GND with a minimum ceramic capacitor value of 0.1 µF.
A bulk capacitor value of 1.0 µF to 10 µF in parallel with the 0.1 µF is recommended for
enhanced performance.
1
VREF
Non-Inverting Input for Channel A. CHA+ is the positive analog input for the differential
signal applied to Channel A.
2
3
4
CHA+
CHA−
CHB−
Inverting Input for Channel A. CHA− is the negative analog input for the differential signal
applied to Channel A.
Inverting Input for Channel B. CHB− is the negative analog input for the differential signal
applied to Channel B.
Non-Inverting Input for Channel B. CHB+ is the positive analog input for the differential
signal applied to Channel B.
5
6
CHB+
GND
Ground. GND is the ground reference point for all signals applied to the ADC122S625.
Analog Power Supply input. A voltage source between 4.5V and 5.5V must be applied to
this input. VA must be decoupled to GND with a minimum ceramic capacitor value of 0.1
µF. A bulk capacitor value of 1.0 µF to 10 µF in parallel with the 0.1 µF is recommended for
enhanced performance.
7
8
VA
Serial Data Output for Channel A and Channel B. The serial data output word is comprised
of 4 null bits, 12 data bits (ChA conversion result), 4 null bits, and 12 data bits (ChB
conversion result). During a conversion, the data is output on the falling edges of SCLK and
is valid on the rising edges.
DOUT
9
SCLK
CS
Serial Clock. SCLK is used to control data transfer and serves as the conversion clock.
Chip Select Bar. CS is active low. The ADC122S625 is actively converting when CS is
LOW and Power-Down Mode when CS is HIGH. A conversion begins on the fall of CS.
10
2
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings(1)(2)(3)
Analog Supply Voltage VA
−0.3V to 6.5V
−0.3V to (VA +0.3V)
±10 mA
Voltage on Any Pin to GND
(4)
Input Current at Any Pin
(4)
Package Input Current
±50 mA
(5)
Power Consumption at TA = 25°C
See
(6)
ESD Susceptibility
Human Body Model
Machine Model
2500V
250V
Charge Device Model
1000V
Junction Temperature
Storage Temperature
+150°C
−65°C to +150°C
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see the
Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance characteristics may
degrade when the device is not operated under the listed test conditions. Operation of the device beyond the maximum Operating
Ratings is not recommended.
(2) All voltages are measured with respect to GND = 0V, unless otherwise specified.
(3) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
(4) When the input voltage at any pin exceeds the power supplies (that is, VIN < GND or VIN > VA), the current at that pin should be limited
to 10 mA. The 50 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an
input current of 10 mA to five.
(5) The absolute maximum junction temperature (TJmax) for this device is 150°C. The maximum allowable power dissipation is dictated by
TJmax, the junction-to-ambient thermal resistance (θJA), and the ambient temperature (TA), and can be calculated using the formula
PDMAX = (TJmax − TA)/θJA. The values for maximum power dissipation listed above will be reached only when the ADC122S625 is
operated in a severe fault condition (e.g. when input or output pins are driven beyond the power supply voltages, or the power supply
polarity is reversed). Such conditions should always be avoided.
(6) Human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor. Machine model is a 220 pF capacitor discharged
through 0 Ω. Charge device model simulates a pin slowly acquiring charge (such as from a device sliding down the feeder in an
automated assembler) then rapidly being discharged.
Operating Ratings(1)(2)
Operating Temperature Range
−40°C ≤ TA ≤ +105°C
+4.5V to +5.5V
1.0V to VA
Supply Voltage, VA
Reference Voltage, VREF
Input Common-Mode Voltage, VCM
Digital Input Pins Voltage Range
Clock Frequency
See Figure 36
0 to VA
1.6 MHz to 6.4 MHz
−VREF to +VREF
Differential Analog Input Voltage
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see the
Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance characteristics may
degrade when the device is not operated under the listed test conditions. Operation of the device beyond the maximum Operating
Ratings is not recommended.
(2) All voltages are measured with respect to GND = 0V, unless otherwise specified.
Package Thermal Resistance
Package
θJA
10-lead VSSOP
240°C / W
Soldering process must comply with TI's Reflow Temperature Profile
(1)
specifications. Refer to http://www.ti.com/packaging
(1) Reflow temperature profiles are different for lead-free packages.
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(1)
ADC122S625 Converter Electrical Characteristics
The following specifications apply for VA = +4.5V to 5.5V, VREF = 2.5V, fSCLK = 1.6 to 6.4 MHz, fIN = 20 kHz, CL = 25 pF,
unless otherwise noted. Boldface limits apply for TA = TMIN to TMAX; all other limits are at TA = 25°C.
Symbol
Parameter
Conditions
Typical
Limits
Units
STATIC CONVERTER CHARACTERISTICS
Resolution with No Missing Codes
12
±1
Bits
LSB (max)
LSB
Integral Non-Linearity
INL
±0.5
0.02
±0.4
0.02
0.2
0.1
−2
Integral Non-Linearity Matching
Differential Non-Linearity
DNL
±0.95
±3
LSB (max)
LSB
Differential Non-Linearity Matching
Offset Error
OE
LSB (max)
LSB
Offset Error Matching
Positive Gain Error
±5
LSB (max)
LSB
Positive Gain Error Matching
0.2
3
GE
Negative Gain Error
±8
LSB (max)
LSB
Negative Gain Error Matching
0.2
DYNAMIC CONVERTER CHARACTERISTICS
SINAD
SNR
Signal-to-Noise Plus Distortion Ratio fIN = 20 kHz, −0.1 dBFS
72.5
73.2
−83
84
69.5
71
dBc (min)
dBc (min)
dBc (max)
dBc (min)
bits (min)
MHz
Signal-to-Noise Ratio
fIN = 20 kHz, −0.1 dBFS
THD
Total Harmonic Distortion
Spurious-Free Dynamic Range
Effective Number of Bits
fIN = 20 kHz, −0.1 dBFS
fIN = 20 kHz, −0.1 dBFS
fIN = 20 kHz, −0.1 dBFS
−72
72
SFDR
ENOB
11.8
26
11.25
Differential Input
Output at 70.7%FS with
FS Input
FPBW
ISOL
−3 dB Full Power Bandwidth
Single-Ended Input
22
MHz
Channel-to-Channel Isolation
fIN < 1 MHz
−90
dBc
ANALOG INPUT CHARACTERISTICS
−VREF
+VREF
±1
V (min)
V (max)
µA (max)
pF
VIN
Differential Input Range
DC Leakage Current
Input Capacitance
IDCL
CINA
VIN = VREF or VIN = -VREF
In Track Mode
20
3
In Hold Mode
pF
See the Specification Definitions for the test
condition
CMRR
VREF
Common Mode Rejection Ratio
Reference Voltage Range
−90
dB
1.0
VA
V (min)
V (max)
DIGITAL INPUT CHARACTERISTICS
VIH
VIL
Input High Voltage
Input Low Voltage
Input Current
2.4
0.8
±1
4
V (min)
V (max)
µA (max)
pF (max)
IIN
VIN = 0V or VA
CIND
Input Capacitance
2
DIGITAL OUTPUT CHARACTERISTICS
ISOURCE = 200 µA
ISOURCE = 1 mA
ISINK = 200 µA
ISINK = 1 mA
V
A − 0.02
A − 0.09
0.01
V
A − 0.2
V (min)
V
VOH
Output High Voltage
Output Low Voltage
V
0.4
V (max)
V
VOL
0.08
IOZH, IOZL TRI-STATE Leakage Current
Force 0V or VA
Force 0V or VA
±1
4
µA (max)
pF (max)
COUT
TRI-STATE Output Capacitance
Output Coding
2
Binary 2'S Complement
(1) Tested limits are specified to TI's AOQL (Average Outgoing Quality Level).
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ADC122S625 Converter Electrical Characteristics (1) (continued)
The following specifications apply for VA = +4.5V to 5.5V, VREF = 2.5V, fSCLK = 1.6 to 6.4 MHz, fIN = 20 kHz, CL = 25 pF,
unless otherwise noted. Boldface limits apply for TA = TMIN to TMAX; all other limits are at TA = 25°C.
Symbol
Parameter
Conditions
Typical
Limits
Units
POWER SUPPLY CHARACTERISTICS
4.5
5.5
V (min)
V (max)
VA
Analog Supply Voltage
IVA
(Conv)
Analog Supply Current,
Continuously Converting
fSCLK = 6.4 MHz, fS = 200 kSPS, fIN = 20 kHz,
VA = 5V
1.7
20
2.45
40
mA (max)
µA (max)
IVREF
(Conv)
Reference Current, Continuously
Converting
fSCLK = 6.4 MHz, fS = 200 kSPS, VREF = 2.5V
fSCLK = 6.4 MHz, VA = 5.0V
10
µA
Analog Supply Current, Power Down
Mode (CS high)
IVA (PD)
(2)
fSCLK = 0, VA = 5.0V
0.5
1.1
µA (max)
µA
fSCLK = 6.4 MHz, VREF = 2.5V
0.05
0.05
IVREF
(PD)
Reference Current, Power Down
Mode (CS high)
(2)
fSCLK = 0, VREF = 2.5V
0.1
µA (max)
PWR
(Conv)
Power Consumption, Continuously
Converting
fSCLK = 6.4 MHz, fS = 200 kSPS, fIN = 20 kHz,
VA = 5.0V, VREF = 2.5V
8.6
12.4
mW (max)
fSCLK = 6.4 MHz, VA = 5.0V, VREF = 2.5V
fSCLK = 0, VA = 5.0V, VREF = 2.5V
50
µW
PWR
(PD)
Power Consumption, Power Down
Mode (CS high)
2.6
5.8
µW (max)
See the Specification Definitions for the test
condition
PSRR
Power Supply Rejection Ratio
−85
dB
AC ELECTRICAL CHARACTERISTICS
fSCLK
fSCLK
Maximum Clock Frequency
Minimum Clock Frequency
Maximum Sample Rate(3)
Minimum Sample Rate
Track/Hold Acquisition Time
Conversion Time
20
0.8
625
25
6.4
1.6
200
50
MHz (min)
MHz (max)
kSPS (min)
kSPS (min)
SCLK cycles
SCLK cycles
ns
fS
tACQ
tCONV
tAD
3
12
Aperture Delay
6
(2) Specified by design, characterization, or statistical analysis and is not tested at final test.
(3) While the maximum sample rate is fSCLK/32, the actual sample rate may be lower than this by having the CS rate slower than fSCLK/32.
(1)
ADC122S625 Timing Specifications
The following specifications apply for VA = +4.5V to 5.5V, VREF = 2.5V, fSCLK = 1.6 MHz to 6.4 MHz, CL = 25 pF, unless
otherwise noted. Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25°C.
Symbol
Parameter
Conditions
Typical
Limits
Units
ns (min)
ns (max)
ns (max)
ns (min)
ns (max)
ns (max)
ns (min)
ns (min)
ns
4
7
tCSSU
CS Setup Time prior to an SCLK rising edge
1/ fSCLK
1/ fSCLK - 3
tEN
tDH
tDA
tDIS
tCH
tCL
tr
DOUT Enable Time after the falling edge of CS
DOUT Hold time after an SCLK Falling edge
DOUT Access time after an SCLK Falling edge
DOUT Disable Time after the rising edge of CS(2)
SCLK High Time
9
9
20
6
20
10
26
20
25
25
SCLK Low Time
DOUT Rise Time
7
7
tf
DOUT Fall Time
ns
(1) Tested limits are specified to TI's AOQL (Average Outgoing Quality Level).
(2) tDIS is the time for DOUT to change 10%.
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Timing Diagrams
t
t
ACQ
CONV
10
CS
1
2
3
4
5
6
7
8
9
11
12
13
14
15
16
SCLK
DOUT
4 Leading Zeroes
DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Channel A Data
t
Power Down
CS
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
SCLK
DOUT
4 Leading Zeroes
DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Channel B Data
Figure 1. ADC122S625 Single Conversion Timing Diagram
t
t
t
PD
t
t
CONV
ACQ
CONV
ACQ
CS
1
2
3
4
5
6
15
16
17
18
19
20
21
22
31
32
33
34
35
36
37
38
47
48
SCLK
D
DB11 DB10
MSB
DB1 DB0
LSB
DB11 DB10
MSB
DB1 DB0
LSB
DB11 DB10
MSB
DB1 DB0
LSB
OUT
HI-Z
Channel A Data
Channel B Data
Channel A Data
Figure 2. ADC122S625 Continuous Conversion Timing Diagram
2.4V
D
OUT
0.8V
t
f
t
r
Figure 3. DOUT Rise and Fall Times
SCLK
V
IL
t
DA
2.4V
0.8V
D
OUT
t
DH
Figure 4. DOUT Hold and Access Times
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SCLK
CS
1
2
t
CSSU
Figure 5. Valid CS Assertion Times
V
IH
CS
90%
90%
D
D
OUT
10%
t
DIS
90%
OUT
10%
10%
Figure 6. Voltage Waveform for tDIS
Specification Definitions
APERTURE DELAY is the time between the fourth falling edge of SCLK and the time when the input signal is
acquired or held for conversion.
COMMON MODE REJECTION RATIO (CMRR) is a measure of how well in-phase signals common to both input
pins are rejected.
To calculate CMRR, the change in output offset is measured while the common mode input voltage is changed
from 2V to 3V.
CMRR = 20 LOG ( Δ Output Offset / Δ Common Input)
(1)
CONVERSION TIME is the time required, after the input voltage is acquired, for the ADC to convert the input
voltage to a digital word.
DIFFERENTIAL NON-LINEARITY (DNL) is the measure of the maximum deviation from the ideal step size of 1
LSB.
DUTY CYCLE is the ratio of the time that a repetitive digital waveform is high to the total time of one period. The
specification here refers to the SCLK.
EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE BITS) is another method of specifying Signal-to-Noise
and Distortion or SINAD. ENOB is defined as (SINAD − 1.76) / 6.02 and says that the converter is equivalent to
a perfect ADC of this (ENOB) number of bits.
FULL POWER BANDWIDTH is a measure of the frequency at which the reconstructed output fundamental
drops 3 dB below its low frequency value for a full scale input.
INTEGRAL NON-LINEARITY (INL) is a measure of the deviation of each individual code from a line drawn from
negative full scale (½ LSB below the first code transition) through positive full scale (½ LSB above the last code
transition). The deviation of any given code from this straight line is measured from the center of that code value.
MISSING CODES are those output codes that will never appear at the ADC outputs. The ADC122S625 is
specified not to have any missing codes.
NEGATIVE FULL-SCALE ERROR is the difference between the differential input voltage at which the output
code transitions from negative full scale to the next code and −VREF + 0.5 LSB.
NEGATIVE GAIN ERROR is the difference between the negative full-scale error and the offset error.
OFFSET ERROR is the difference between the differential input voltage at which the output code transitions from
code 000h to 001h and 1/2 LSB.
POSITIVE FULL-SCALE ERROR is the difference between the differential input voltage at which the output
code transitions to positive full scale and VREF minus 1.5 LSB.
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POSITIVE GAIN ERROR is the difference between the positive full-scale error and the offset error.
POWER SUPPLY REJECTION RATIO (PSRR) is a measure of how well a change in supply voltage is rejected.
PSRR is calculated from the ratio of the change in offset error for a given change in supply voltage, expressed in
dB. For the ADC122S625, VA is changed from 4.5V to 5.5V.
PSRR = 20 LOG (ΔOffset / ΔVA)
(2)
SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in dB, of the rms value of the input signal to the rms
value of the sum of all other spectral components below one-half the sampling frequency, not including
harmonics or d.c.
SIGNAL TO NOISE PLUS DISTORTION (S/N+D or SINAD) Is the ratio, expressed in dB, of the rms value of the
input signal to the rms value of all of the other spectral components below half the clock frequency, including
harmonics but excluding d.c.
SPURIOUS FREE DYNAMIC RANGE (SFDR) is the difference, expressed in dB, between the desired signal
amplitude to the amplitude of the peak spurious spectral component, where a spurious spectral component is
any signal present in the output spectrum that is not present at the input and may or may not be a harmonic.
TOTAL HARMONIC DISTORTION (THD) is the ratio of the rms total of the first five harmonic components at the
output to the rms level of the input signal frequency as seen at the output, expressed in dB. THD is calculated as
2
Af22 +3+ Af6
THD = 20 • log10
2
Af1
(3)
where Af1 is the RMS power of the input frequency at the output and Af2 through Af6 are the RMS power in the
first 5 harmonic frequencies.
THROUGHPUT TIME is the minimum time required between the start of two successive conversion.
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Typical Performance Characteristics
VA = 5.0V, VREF = 2.5V, TA = +25°C, fSAMPLE = 200 kSPS, fSCLK = 6.4 MHz, fIN = 20 kHz unless otherwise stated.
DNL - 200 kSPS
INL - 200 kSPS
Figure 7.
Figure 8.
DNL vs. VA
INL vs. VA
Figure 9.
Figure 10.
DNL vs. VREF
INL vs. VREF
Figure 11.
Figure 12.
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Typical Performance Characteristics (continued)
VA = 5.0V, VREF = 2.5V, TA = +25°C, fSAMPLE = 200 kSPS, fSCLK = 6.4 MHz, fIN = 20 kHz unless otherwise stated.
DNL vs. SCLK FREQUENCY
INL vs. SCLK FREQUENCY
Figure 13.
Figure 14.
DNL vs. TEMPERATURE
INL vs. TEMPERATURE
Figure 15.
Figure 16.
SINAD vs. VA
THD vs. VA
Figure 17.
Figure 18.
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Typical Performance Characteristics (continued)
VA = 5.0V, VREF = 2.5V, TA = +25°C, fSAMPLE = 200 kSPS, fSCLK = 6.4 MHz, fIN = 20 kHz unless otherwise stated.
SINAD vs. VREF
THD vs. VREF
Figure 19.
Figure 20.
SINAD vs. SCLK FREQUENCY
THD vs. SCLK FREQUENCY
Figure 21.
Figure 22.
SINAD vs. INPUT FREQUENCY
THD vs. INPUT FREQUENCY
Figure 23.
Figure 24.
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Typical Performance Characteristics (continued)
VA = 5.0V, VREF = 2.5V, TA = +25°C, fSAMPLE = 200 kSPS, fSCLK = 6.4 MHz, fIN = 20 kHz unless otherwise stated.
SINAD vs. TEMPERATURE
THD vs. TEMPERATURE
Figure 25.
Figure 26.
VA CURRENT vs. VA
VA CURRENT vs. SCLK FREQ
Figure 27.
Figure 28.
VA CURRENT vs. TEMPERATURE
VREF CURRENT vs. SCLK FREQ
Figure 29.
Figure 30.
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Typical Performance Characteristics (continued)
VA = 5.0V, VREF = 2.5V, TA = +25°C, fSAMPLE = 200 kSPS, fSCLK = 6.4 MHz, fIN = 20 kHz unless otherwise stated.
VREF CURRENT vs. TEMP
CMRR vs. CM RIPPLE FREQ
Figure 31.
Figure 32.
SPECTRAL RESPONSE - 200 kSPS
Figure 33.
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FUNCTIONAL DESCRIPTION
The ADC122S625 is a dual 12-bit, simultaneous sampling Analog-to-Digital (A/D) converter. The converter is
based on a successive-approximation register (SAR) architecture where the differential nature of the analog
inputs is maintained from the internal track-and-hold circuits throughout the A/D converter. The analog inputs on
both channels are sampled simultaneously to preserve their relative phase information to each other. The
architecture and process allow the ADC122S625 to acquire and convert dual analog signals at sample rates up
to 200 kSPS while consuming very little power.
The ADC122S625 requires an external reference, external clock, and an analog power supply. The analog
supply (VA) can range from 4.5V to 5.5V and the external reference can be any voltage between 1V and VA. The
value of the reference voltage determines the range of the analog input, while the reference input current
depends upon the conversion rate.
Analog inputs are presented at the inputs of Channel A and Channel B. Upon initiation of a conversion, the
differential input at these pins is sampled on the internal capacitor array. The analog input signals are
disconnected from the external circuitry while a conversion is in progress.
The external clock can take on values as indicated in the Electrical Characteristics Table. The duty cycle of the
clock is essentially unimportant, provided the minimum clock high and low times are met. The minimum clock
frequency is set by internal capacitor leakage. Each conversion requires thirty-two clock cycles to complete.
The ADC122S625 offers a high-speed serial data output that is binary 2's complement and compatible with
several standards, such as SPI™, QSPI™, MICROWIRE™, and many common DSP serial interfaces. The digital
conversion result of Channel A and Channel B is clocked out on the falling edges of the SCLK input and is
provided serially at DOUT, most significant bit first. The result of Channel A is output before the result of Channel
B, with four zeros in between the two results. The digital data provided on DOUT is that of the conversion currently
in progress. With CS held low after the result of Channel B is output, the ADC122S625 will continuously convert
the analog inputs until CS is de-asserted (brought high). Having a single, serial DOUT makes the ADC122S625 an
excellent replacement for two independent ADCs that are part of a daisy chain configuration and allows a system
designer to save valuable board space and power.
REFERENCE INPUT
The externally supplied reference voltage sets the analog input range. The ADC122S625 will operate with a
reference voltage in the range of 1V to VA.
Operation with a reference voltage below 1V is also possible with slightly diminished performance. As the
reference voltage (VREF) is reduced, the range of acceptable analog input voltages is reduced. Assuming a
proper common-mode input voltage, the differential peak-to-peak input range is limited to twice VREF. See Input
Common Mode Voltage for more details. Reducing the value of VREF also reduces the size of the least significant
bit (LSB). The size of one LSB is equal to twice the reference voltage divided by 4096. When the LSB size goes
below the noise floor of the ADC122S625, the noise will span an increasing number of codes and overall
performance will suffer. For example, dynamic signals will have their SNR degrade, while D.C. measurements
will have their code uncertainty increase. Since the noise is Gaussian in nature, the effects of this noise can be
reduced by averaging the results of a number of consecutive conversions.
Additionally, since offset and gain errors are specified in LSB, any offset and/or gain errors inherent in the A/D
converter will increase in terms of LSB size as the reference voltage is reduced.
The reference input and the analog inputs are connected to the capacitor array through a switch matrix when the
input is sampled. Hence, the current requirements at the reference and at the analog inputs are a series of
transient spikes that occur at a frequency dependent on the operating sample rate of the ADC122S625.
The reference current changes only slightly with temperature. See the curves, Reference Current vs. SCLK
Frequency and Reference Current vs. Temperature in the Typical Performance Characteristics section for
additional details.
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ANALOG SIGNAL INPUTS
The ADC122S625 has dual differential inputs where the effective input voltage that is digitized is CHA+ minus
CHA− (DIFFINA) and CHB+ minus CHB− (DIFFINB). As is the case with all differential input A/D converters,
operation with a fully differential input signal or voltage will provide better performance than with a single-ended
input. However, the ADC122S625 can be presented with a single-ended input as shown in Single-Ended Input
Operation and the Application Circuits.
The current required to recharge the input sampling capacitor will cause voltage spikes at the + and − inputs. Do
not try to filter out these noise spikes. Rather, ensure that the noise spikes settle out during the acquisition period
(three SCLK cycles after the fall of CS). This is true for both Channel A and Channel B since both channels are
converted simultaneously on the fourth falling edge of SCLK after CS is asserted.
Differential Input Operation
With a fully differential input voltage or signal, a positive full scale output code (0111 1111 1111b or 7FFh) will be
obtained when DIFFINA or DIFFINB is greater than or equal to VREF − 1.5 LSB. A negative full scale code (1000
0000 0000b or 800h) will be obtained when DIFFINA or DIFFINB is greater than or equal to −VREF + 0.5 LSB.
This ignores gain, offset and linearity errors, which will affect the exact differential input voltage that will
determine any given output code. Figure 34 shows the ADC122S625 being driven by a full-scale differential
source.
VREF
2
VCM
VREF
2
VCM
+
-
VCM
RS
+
SRC
CS
ADC122S625
-
RS
VREF
2
VCM
VREF
VCM
+
-
VCM
2
Figure 34. Differential Input
Single-Ended Input Operation
For single-ended operation, the non-inverting inputs of the ADC122S625 can be driven with a signal that has a
maximum to minimum value range that is equal to or less than twice the reference voltage. The inverting inputs
should be biased at a stable voltage that is halfway between these maximum and minimum values. In order to
utilize the entire dynamic range of the ADC122S625, the reference voltage is limited at VA / 2. This allows the
non-inverting inputs the maximum swing range of ground to VA. Figure 35 shows the ADC122S625 being driven
by a full-scale single-ended source. Even though the design of the ADC122S625 is optimized for a differential
input, there is very little performance degradation while operating the ADC122S625 in single-ended fashion.
VCM + VREF
VCM
VCM - VREF
RS
+
CS
ADC122S625
-
SRC
VCM
Figure 35. Single-Ended Input
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Input Common Mode Voltage
The allowable input common mode voltage (VCM) range depends upon the supply and reference voltages used
for the ADC122S625. The ranges of VCM for differential and single-ended operation are depicted in Figure 36 and
Figure 37. Equations for calculating the minimum and maximum common mode voltages for differential and
single-ended operation are shown in Table 1.
6
Differential Input
5
V
= 5.0V
A
3.75
2.5
1.25
0
-1
0.0
1.0
2.0 2.5 3.0
(V)
4.0
5.0
V
REF
Figure 36. VCM range for Differential Input operation
6
Single-Ended Input
5
V
= 5.0V
A
3.75
2.5
1.25
0
-1
0.0
0.75
1.25
(V)
1.75
2.5
V
REF
Figure 37. VCM range for single-ended operation
Table 1. Allowable VCM Range
Input Signal
Minimum VCM
VREF / 2
Maximum VCM
A − VREF / 2
A − VREF
Differential
V
Single-Ended
VREF
V
SERIAL DIGITAL INTERFACE
The ADC122S625 communicates via a synchronous serial interface as shown in the Timing Diagrams section.
CS, chip select, initiates conversions and frames the serial data transfers. SCLK (serial clock) controls both the
conversion process and the timing of the serial data. DOUT is the serial data output pin, where the conversion
results of Channel A and Channel B are sent as a serial data stream, with the result of Channel A output before
the result of Channel B.
A serial frame is initiated on the falling edge of CS and ends on the rising edge of CS. The ADC122S625's DOUT
is in a high impedance state when CS is high (asserted) and is active when CS is low (de-asserted); thus CS
acts as an output enable. A timing diagram for a single conversion is shown in Figure 1.
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During the first three cycles of SCLK, the ADC122S625 is in acquisition mode (tACQ), tracking the input voltage
on both Channel A and Channel B. For the next twelve SCLK cycles (tCONV), the conversion of Channel A and
Channel B is accomplished simultaneously and data is presented on DOUT, one bit at a time. SCLK falling edges
one through four clock out leading zeros while falling edges five through sixteen clock out the conversion result
of Channel A, MSB first. The process is repeated in order to clock out the result of Channel B, with SCLK falling
edges seventeen through twenty clocking out four zeros followed by falling edges twenty-one through thirty-two
clokcing out the conversion result of Channel B. If there is more than one conversion in a frame (continuous
conversion mode), the ADC122S625 will re-enter acquisition mode on the falling edge of SCLK after the N*32
rising edge of SCLK and re-enter conversion mode on the N*32+4 falling edge of SCLK as shown in Figure 2.
"N" is an integer value.
The ADC122S625 can enter acquisition mode under three different conditions. The first condition involves CS
going low (asserted) with SCLK high. In this case, the ADC122S625 enters acquisition mode on the first falling
edge of SCLK after CS is asserted. In the second condition, CS goes low with SCLK low. Under this condition,
the ADC122S625 automatically enters acquisition mode and the falling edge of CS is seen as the first falling
edge of SCLK. In the third condition, CS and SCLK go low simultaneously and the ADC122S625 immediately
enters acquisition mode. While there is no timing restriction with respect to the falling edges of CS and the falling
edge of SCLK, see Figure 5 for setup and hold time requirements for the falling edge of CS with respect to the
rising edge of SCLK.
CS Input
The CS (chip select bar) is an active low input that is TTL and CMOS compatible. The ADC122S625 transitions
from acquisition mode, to conversion mode, to power-down mode when CS is low and is always in power-down
mode when CS is high. The falling edge of CS marks the beginning of a conversion where the input to Channel
A and Channel B are tracked by the input sampling capacitor. The rising edge of CS marks the end of a
conversion window. As a result, CS frames the conversion window and can be used to control the sample rate of
the ADC122S625. While the SCLK frequency is limited to a range of 1.6 MHz to 6.4 MHz, the frequency of CS
has no limitation. This allows a system designer to operate the ADC122S625 at sample rates approaching zero
samples per second if conserving power is very important. See Burst Mode Operation for more details. Multiple
conversions can occur within a given conversion frame with each conversion requiring thirty-two SCLK cycles.
This is referred to as continuous conversion mode and is shown in Figure 2 of the Timing Diagrams section.
Proper operation requires that the fall of CS not occur simultaneously with a rising edge of SCLK. If the fall of CS
occurs during the rising edge of SCLK, the data might be clocked out one bit early. Whether or not the data is
clocked out early depends upon how close the CS transition is to the SCLK transition, the device temperature,
and characteristics of the individual device. To ensure that the MSB is always clocked out at a given time (the
5th falling edge of SCLK), it is essential that the fall of CS always meet the timing requirement specified in the
Timing Specification table.
SCLK Input
The SCLK (serial clock) serves two purposes in the ADC122S625. It is used by the ADC122S625 as the
conversion clock and it is used as the serial clock to output the conversion results. The SCLK input is TTL and
CMOS compatible. Internal settling time requirements limit the maximum clock frequency while internal capacitor
leakage limits the minimum clock frequency. The ADC122S625 offers specified performance with the clock rates
indicated in the Electrical Characteristics Table.
Data Output(s)
The conversion result of Channel A and Channel B is output on DOUT, with the result of Channel A being output
before the result of Channel B. The data output format of the ADC122S625 is binary, two’s complement, as
shown in Table 2. This table indicates the ideal output code for a given input voltage and does not include the
effects of offset, gain error, linearity errors, or noise. Each data output bit is output on the falling edges of SCLK.
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Table 2. Ideal Output Code vs. Input Voltage
Analog Input
(+IN) − (−IN)
2's Complement Binary Output
2's Comp. Hex Code
2's Comp. Dec Code
VREF − 1.5 LSB
+ 0.5 LSB
0111 1111 1111
0000 0000 0001
0000 0000 0000
1111 1111 1111
1000 0000 0000
7FF
001
000
FFF
800
2047
1
− 0.5 LSB
0
0V − 1.5 LSB
−VREF + 0.5 LSB
−1
−2048
While data is output on the falling edges of SCLK, receiving systems have the option of capturing the data from
the ADC122S625 on the subsequent rising or falling edge of SCLK. If a receiving system is going to capture data
on the subsequent falling edges of SCLK, it is important to make sure that the minimum hold time after an SCLK
falling edge (tDH) is acceptable. See Figure 4 for DOUT hold and access times.
DOUT is enabled on the falling edge of CS and disabled on the rising edge of CS. If CS is raised prior to the 16th
falling edge of SCLK, the current conversion is aborted and DOUT will go into its high impedance state. A new
conversion will begin when CS is taken LOW.
Applications Information
OPERATING CONDITIONS
We recommend that the following conditions be observed for operation of the ADC122S625:
−40°C ≤ TA ≤ +105°C
+4.5V ≤ VA ≤ +5.5V
1V ≤ VREF ≤ VA
1.6 MHz ≤ fSCLK ≤ 6.4 MHz
VCM: See Input Common Mode Voltage
POWER CONSUMPTION
The architecture, design, and fabrication process allow the ADC122S625 to operate at conversion rates up to
200 kSPS while consuming very little power. The ADC122S625 consumes the least amount of power while
operating in power down mode. For applications where power consumption is critical, the ADC122S625 should
be operated in power down mode as often as the application will tolerate. To further reduce power consumption,
stop the SCLK while CS is high.
Burst Mode Operation
Normal operation of the ADC122S625 requires the SCLK frequency to be thirty-two times the sample rate and
the CS rate to be the same as the sample rate. However, in order to minimize power consumption in applications
requiring sample rates below 50 kSPS, the ADC122S625 should be run with an SCLK frequency of 6.4 MHz and
a CS rate as slow as the system requires. When this is accomplished, the ADC122S625 is operating in burst
mode. The ADC122S625 enters into power down mode at the end of each conversion, minimizing power
consumption. This causes the converter to spend the longest possible time in power down mode. Since power
consumption scales directly with conversion rate, minimizing power consumption requires determining the lowest
conversion rate that will satisfy the requirements of the system.
POWER SUPPLY CONSIDERATIONS AND PCB LAYOUT
For best performance, care should be taken with the physical layout of the printed circuit board. This is especially
true with a low reference voltage or when the conversion rate is high. At high clock rates there is less time for
settling, so it is important that any noise settles out before the conversion begins.
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Analog Power Supply
Any ADC architecture is sensitive to spikes on the power supply, reference, and ground pins. These spikes may
originate from switching power supplies, digital logic, high power devices, and other sources. Power to the
ADC122S625 should be clean and well bypassed. A 0.1 µF ceramic bypass capacitor and a 1 µF to 10 µF
capacitor should be used to bypass the ADC122S625 supply, with the 0.1 µF capacitor placed as close to the
ADC122S625 package as possible.
Since the ADC122S625 has a separate analog and reference pin, the user has two options. The first option is to
tie the analog and reference supply pins together and power them with the same power supply. This is the most
cost effective way of powering the ADC122S625 but it is also the least ideal. As stated previously, noise from the
analog supply pin can couple into the reference supply pin and adversely affect performance. The other option
involves the user powering the analog and reference supply pins with separate supply voltages. These supply
voltages can have the same amplitude or they can be different. The only design constraint is that the reference
supply voltage be less than the analog supply voltage.
Voltage Reference
The reference source must have a low output impedance and needs to be bypassed with a minimum capacitor
value of 0.1 µF. A larger capacitor value of 1 µF to 10 µF placed in parallel with the 0.1 µF is preferred. While the
ADC122S625 draws very little current from the reference on average, there are higher instantaneous current
spikes at the reference input.
The reference input of the ADC122S625, like all A/D converters, does not reject noise or voltage variations. Keep
this in mind if the reference voltage is derived from the power supply. Any noise and/or ripple from the supply
that is not rejected by the external reference circuitry will appear in the digital results. The use of an active
reference source is recommended. The LM4040 and LM4050 shunt reference families and the LM4132 and
LM4140 series reference families are excellent choices for a reference source.
PCB Layout
Capacitive coupling between the noisy digital circuitry and the sensitive analog circuitry can lead to poor
performance. The solution is to keep the analog circuitry separated from the digital circuitry and the clock line as
short as possible. Digital circuits create substantial supply and ground current transients. The logic noise
generated could have significant impact upon system noise performance. To avoid performance degradation of
the ADC122S625 due to supply noise, avoid sharing the power supplies for VA and VREF with other digital
circuitry on the board.
Generally, analog and digital lines should cross each other at 90° to avoid crosstalk. However, to maximize
accuracy in high resolution systems, avoid crossing analog and digital lines altogether. It is important to keep
clock lines as short as possible and isolated from other lines, including other digital lines. In addition, the clock
line should also be treated as a transmission line and be properly terminated. The analog input should be
isolated from noisy signal traces to avoid coupling of spurious signals into the input. Any external component
(e.g., a filter capacitor) connected between the converter's input pins and ground or to the reference input pin
and ground should be connected to a very clean point in the ground plane.
A single, uniform ground plane and the use of split power planes are recommended. The power planes should be
located within the same board layer. All analog circuitry (input amplifiers, filters, reference components, etc.)
should be placed over the analog power plane. All digital circuitry and I/O lines should be placed over the digital
power plane. Furthermore, the GND pin on the ADC122S625 and all the components in the reference circuitry
and input signal chain that are connected to ground should be connected to the ground plane at a quiet point.
Avoid connecting these points too close to the ground point of a microprocessor, microcontroller, digital signal
processor, or other high power digital device.
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APPLICATION CIRCUITS
The following figures are examples of the ADC122S625 in typical application circuits. These circuits are basic
and will generally require modification for specific circumstances.
Data Acquisition
Figure 38 shows a basic low cost, low power data acquisition circuit. The analog supply pin is powered by the
system +5V supply and the 2.5V reference voltage is generated by the LM4040-2.5 shunt reference.
+5V
+
10 mF
2 kW
ADC122S625
V
REF
V
A
+
0.1 mF
0.1 mF
10 mF
LM4040-2.5
Microcontroller
CHA+ SCLK
DIFFINA
DIFFINB
CHA-
GND
D
OUT
CSB
CHB-
CHB+
Figure 38. Low cost, low power Data Acquisition System
Current Sensing Application
Figure 39 shows an example of interfacing a pair of current transducers to the ADC122S625. The current
transducers convert an input current into a voltage that is converted by the ADC122S625. Since the output
voltage of the current transducers are single-ended and centered around a common-mode voltage of 2.5V, the
ADC122S625 is configured with the output of the transducer driving the non-inverting inputs and the common-
mode output voltage of the transducer driving the inverting input. The output of the transducer has an output
range of ±2V around the common-mode voltage of 2.5V. As a result, a series reference voltage of 2.0V is
connected to the ADC122S625. This will allow all of the codes of the ADC122S625 to be available for the
application. This configuration of the ADC122S625 is referred to as a single-ended application of a differential
ADC. All of the elements in the application are conveniently powered by the same +5V power supply, keeping
circuit complexity and cost to a minimum.
+5V
+
10 mF
LM4132-2.0
V
REF
V
A
ADC122S625
+
0.1 mF
0.1 mF
10 mF
2.5V + 2.0V
2.5V
CHA+
OUT
+5V
I
IN
I
I
IN
ADC
ADC
SCLK
V
OUT
CM
CHA-
GND
GND
I
I
OUT
D
OUT
Serial
Interface
CSB
CHB-
2.5V
V
CM
I
IN
I
IN
+5V
OUT
GND
2.5V + 2.0V
I
OUT
CHB+
OUT
LTSR-15NPs
Figure 39. Interfacing the ADC122S625 to a Current Transducer
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Bridge Sensor Application
Figure 40 shows an example of interfacing the ADC122S625 to a pair of bridge sensors. The application
assumes that the bridge sensors require buffering and amplification to fully utilize the dynamic range of the ADC
and thus optimize the performance of the entire signal path. The amplification stage for each ADC input consists
of a pair of opamps from the LMP7704. The amplification stage offers the benefit of high input impedance and
potentially high amplification. On the other hand, it offers no common-mode rejection of noise coming from the
bridge sensors. The application circuit assumes the bridge sensors are powered from the same +5V power
supply voltage as the analog supply pin on the ADC122S625. This has the benefit of providing the ideal
common-mode input voltage for the ADC122S625 while keeping design complexity and cost to a minimum. The
LM4132-4.1, a 4.1V series reference, is used as the reference voltage in the application.
+5V
+5V = V
A
+
-
470 pF
180W
ADC122S625
ADC_A
100 kW
100 kW
2 kW
180W
-
+
A
= 100 V/V
V
Bridge
Sensor
SCLK
DOUT
LMP7704
Serial Interface
+5V
CSB
+
-
470 pF
180W
100 kW
ADC_B
2 kW
180W
100 kW
V
REF
-
+
A
V
= 100 V/V
Bridge
Sensor
LM4132-4.1
4.7 mF
+5V
+
+
0.1 mF
4.7 mF
Figure 40. Interfacing the ADC122S625 to Bridge Sensors
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REVISION HISTORY
Changes from Original (March 2013) to Revision A
Page
•
Changed layout of National Data Sheet to TI format .......................................................................................................... 21
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
ADC122S625CIMM/NOPB
ADC122S625CIMMX/NOPB
ACTIVE
ACTIVE
VSSOP
VSSOP
DGS
DGS
10
10
1000 RoHS & Green
3500 RoHS & Green
SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 105
-40 to 105
X35C
X35C
SN
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
ADC122S625CIMM/NOPB VSSOP
DGS
DGS
10
10
1000
3500
178.0
330.0
12.4
12.4
5.3
5.3
3.4
3.4
1.4
1.4
8.0
8.0
12.0
12.0
Q1
Q1
ADC122S625CIMMX/
NOPB
VSSOP
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
ADC122S625CIMM/NOPB
VSSOP
VSSOP
DGS
DGS
10
10
1000
3500
210.0
367.0
185.0
367.0
35.0
35.0
ADC122S625CIMMX/
NOPB
Pack Materials-Page 2
PACKAGE OUTLINE
DGS0010A
VSSOP - 1.1 mm max height
S
C
A
L
E
3
.
2
0
0
SMALL OUTLINE PACKAGE
C
SEATING PLANE
0.1 C
5.05
4.75
TYP
PIN 1 ID
AREA
A
8X 0.5
10
1
3.1
2.9
NOTE 3
2X
2
5
6
0.27
0.17
10X
3.1
2.9
1.1 MAX
0.1
C A
B
B
NOTE 4
0.23
0.13
TYP
SEE DETAIL A
0.25
GAGE PLANE
0.15
0.05
0.7
0.4
0 - 8
DETAIL A
TYPICAL
4221984/A 05/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-187, variation BA.
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EXAMPLE BOARD LAYOUT
DGS0010A
VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
10X (1.45)
(R0.05)
TYP
SYMM
10X (0.3)
1
5
10
SYMM
6
8X (0.5)
(4.4)
LAND PATTERN EXAMPLE
SCALE:10X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4221984/A 05/2015
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
DGS0010A
VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
10X (1.45)
SYMM
(R0.05) TYP
10X (0.3)
8X (0.5)
1
5
10
SYMM
6
(4.4)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:10X
4221984/A 05/2015
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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