ADC1251CMJ-QML
更新时间：2024-09-18 18:15:53
品牌：TI
描述：1-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, CDIP24, CERDIP-24
概述
规格参数
数据手册ADC1251CMJ-QML 概述
1-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, CDIP24, CERDIP-24 模数转换器
ADC1251CMJ-QML 规格参数
| 生命周期： | Obsolete | 包装说明： | DIP, |
| Reach Compliance Code： | unknown | ECCN代码： | 3A001.A.2.C |
| HTS代码： | 8542.39.00.01 | 风险等级： | 5.82 |
| 最大模拟输入电压： | 5.55 V | 最小模拟输入电压： | -4.55 V |
| 最长转换时间： | 15.65 µs | 转换器类型： | ADC, SUCCESSIVE APPROXIMATION |
| JESD-30 代码： | R-GDIP-T24 | 最大线性误差 (EL)： | 0.0244% |
| 标称负供电电压： | -5 V | 模拟输入通道数量： | 1 |
| 位数： | 12 | 功能数量： | 1 |
| 端子数量： | 24 | 最高工作温度： | 125 °C |
| 最低工作温度： | -55 °C | 输出位码： | BINARY |
| 输出格式： | PARALLEL, WORD | 封装主体材料： | CERAMIC, GLASS-SEALED |
| 封装代码： | DIP | 封装形状： | RECTANGULAR |
| 封装形式： | IN-LINE | 认证状态： | Not Qualified |
| 采样并保持/跟踪并保持： | SAMPLE | 筛选级别： | MIL-STD-883 |
| 座面最大高度： | 4.572 mm | 标称供电电压： | 5 V |
| 表面贴装： | NO | 技术： | CMOS |
| 温度等级： | MILITARY | 端子形式： | THROUGH-HOLE |
| 端子节距： | 2.54 mm | 端子位置： | DUAL |
| 宽度： | 15.24 mm | Base Number Matches： | 1 |
ADC1251CMJ-QML 数据手册
通过下载ADC1251CMJ-QML数据手册来全面了解它。这个PDF文档包含了所有必要的细节，如产品概述、功能特性、引脚定义、引脚排列图等信息。
PDF下载MILITARY DATA SHEET
Original Creation Date: 09/26/95
Last Update Date: 12/10/96
MNADC1251CM-X REV 2A0
Last Major Revision Date: 12/10/96
SELF-CALIBRATING 12-BIT PLUS SIGN A/D CONVERTER WITH
SAMPLE-AND-HOLD
General Description
The ADC1251 is a CMOS 12-bit plus sign successive approximation analog-to-digital
converter. On request, the ADC1251 goes through a self-calibration cycle that adjusts for
any zero, full scale, or linearity errors. The ADC1251 also has the ability to go through
an Auto-Zero cycle that corrects the zero error during every conversion.
The analog input to the ADC1251 is tracked and held by the internal circuitry, so an
external sample-and-hold is not required. The ADC1251 has an S/H control input which
directly controls the track-and-hold state of the A/D. A unipolar analog input voltage
range (0 to +5V) or a bipolar range (-5V to +5V) can be accommodated with +5V supplies.
The 13-bit data result is available on the eight outputs of the ADC1251 in two bytes,
high-byte first and sign extended. The digital inputs and outputs are compatible with TTL
or CMOS logic levels.
Industry Part Number
NS Part Numbers
ADC1251CM
ADC1251CMJ-QML
Prime Die
ADC1251CM
Controlling Document
5962-9157803QJA
Processing
Subgrp Description
Temp (oC)
MIL-STD-883, Method 5004
1
Static tests at
+25
2
Static tests at
+125
-55
3
Static tests at
4
Dynamic tests at
Dynamic tests at
Dynamic tests at
Functional tests at
Functional tests at
Functional tests at
Switching tests at
Switching tests at
Switching tests at
+25
Quality Conformance Inspection
5
+125
-55
6
MIL-STD-883, Method 5005
7
+25
8A
8B
9
+125
-55
+25
10
11
+125
-55
1
MILITARY DATA SHEET
MNADC1251CM-X REV 2A0
Features
- Self-calibration provides excellent temperature stability
- Internal sample-and-hold
- 8-bit uP/DSP interface
- Bipolar input range with a single +5V reference
- No missing codes over temperature
- TTL/MOS input/output compatible
Applications
- Digital signal processing
- High resolution process control
- Instrumentation
2
MILITARY DATA SHEET
MNADC1251CM-X REV 2A0
(Absolute Maximum Ratings)
Supply Voltage (Vcc = DVcc = AVcc)
6.5V
-6.5
Negative Supply Voltage (V-)
Voltage at Logic Control Inputs
-0.3V to (Vcc+0.3V)
Voltage at Analog Inputs
(Vref, Vin)
(V- -0.3V) to (Vcc + 0.3V)
AVcc - DVcc
0.3V
Input Current at Any Pin
Package Input Current
Power Dissipation at 25 C
Storage Temperature Range
+5mA
+20mA
875mW
-65 C to +150 C
Thermal Resistance
ThetaJA
(Still Air)
80 C/W
TBD
(500LF/Min Air flow)
ThetaJC
TBD
ESD Susceptability
2000V
300 C
Soldering Information
(10 sec.)
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur.
Operating Ratings indicate conditions for which the device is functional, but do not
guarantee specific performance limits. For guaranteed specifications and test
conditions, see the Electrical Characteristics. The guaranteed specifications apply
only for the test conditions listed. Some performance characteristics may degrade
when the device is not operated under the listed test conditions.
Note 2: All voltages are measured with respect to Agnd and Dgnd, unless otherwise specified.
Note 3: When the input voltage (Vin) at any pin exceeds the power supply rails (Vin < V- or
Vin >(AVcc or DVcc), the current at that pin should be limited to 5mA. The 20mA
maximum package input current rating allows the voltage at any four pins, with an
input current limit of 5mA, to simultaneously exceed the power supply voltages.
Note 4: The power dissipation of this device under normal operation should never exceed 191mW
(Quiescent Power Dissipation + 1 TTL Load on each digital output). Caution should be
taken not to exceed absolute maximum power rating when the device is operating in
severe fault condition (ex. when any inputs or outputs exceed the power supply). The
maximum power dissipation must be derated at elevated temperatures and is dictated by
Tjmax (maximum junction temperature), ThetaJA (package junction to ambient thermal
resistance), and TA (ambient temperature). The maximum allowable power dissipation at
any temperature is Pdmax = (Tjmax - TA)/ThetaJA or the number given in the Absolute
Maximum Ratings, whichever is lower. For this device, Tjmax = 150 C.
Note 5: Human body model, 100pF discharged through a 1.5K Ohm resistor.
Note 6: A diode exists between AVcc and DVcc. To guarantee accuracy, it is required that the
AVcc and DVcc be connected together to a power supply with separate bypass filters at
each Vcc pin.
3
MILITARY DATA SHEET
MNADC1251CM-X REV 2A0
Recommended Operating Conditions
Temperature Range
-55 C < TA < 125 C
DVcc and AVcc Voltage
Negative Supply Voltage (V-)
Reference Voltage
4.5V to 5.5V
-4.5V to -5.5V
3.5V to AVcc+50mV
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur.
Operating Ratings indicate conditions for which the device is functional, but do not
guarantee specific performance limits. For guaranteed specifications and test
conditions, see the Electrical Characteristics. The guaranteed specifications apply
only for the test conditions listed. Some performance characteristics may degrade
when the device is not operated under the listed test conditions.
Note 2: All voltages are measured with respect to Agnd and Dgnd, unless otherwise specified.
Note 3: When the input voltage (Vin) at any pin exceeds the power supply rails (Vin < V- or
Vin> (AVcc or DVcc), the current at that pin should be limited to 5mA. The 20mA
maximum package input current rating allows the voltage at any four pins, with an
input current limit of 5mA, to simultaneously exceed the power supply voltages.
Note 4: A diode exists between AVcc and Dvcc. To guarantee accuracy, it is required that the
AVcc and DVcc be connected together to a power supply with separate bypass filters at
each Vcc pin.
4
MILITARY DATA SHEET
MNADC1251CM-X REV 2A0
Electrical Characteristics
DC PARAMETERS: STATIC PARAMETERS
(The following conditions apply to all the following parameters, unless otherwise specified.)
DC: Vcc = DVcc = AVcc= +5V, V- = -5V, AZ = "1" and fCLK = 3.5MHz, Vref = +5V.
PIN-
NAME
SUB-
GROUPS
SYMBOL
PARAMETER
CONDITIONS
NOTES
MIN
MAX UNIT
Positive Integral After Auto-Cal
Linearity Error
-1.0
1.0
1.0
LSB 1, 2,
3
Negative Integral After Auto-Cal
Linearity Error
-1.0
12
LSB 1, 2,
3
Positive or
Negative
Differential
Linearity
After Auto-Cal
Bits 1, 2,
3
Zero Error
AZ = "0" and fCLK = 1.75MHz
After Auto-Cal Only
-2.0
+2.0
LSB 1, 2,
3
-2.0
+3.0
-1.5
2.0
LSB 1
+3.0
1.5
LSB 2, 3
Positive
Full-Scale Error
AZ = "0" and fCLK = 1.75MHz
After Auto-Cal only
LSB 1, 2,
3
-1.5
-2.0
-1.5
1.5
2.0
1.5
LSB 1
LSB 2, 3
Negative
Full-Scale Error
AZ = "0" and fCLK = 1.75MHz
After Auto-Cal only
LSB 1, 2,
3
-1.5
-2.0
1.5
2.0
LSB 1
LSB 2, 3
Vin
Analog Input
Voltage
V-
-.05
Vcc+
.05
V
1, 2,
3
5
MILITARY DATA SHEET
MNADC1251CM-X REV 2A0
Electrical Characteristics
DC PARAMETERS: DIGITAL AND DC PARAMETERS
(The following conditions apply to all the following parameters, unless otherwise specified.)
DC: Vcc = DVcc = AVcc= +5V, V- = -5V, Vref = +5V, fCLK = 3.5MHz.
PIN-
NAME
SUB-
SYMBOL
Vin
PARAMETER
CONDITIONS
NOTES
MIN
2.0
MAX UNIT
GROUPS
Input Voltage for Logical "1", Vcc = 5.25V
All Input Except
CLK IN
V
1, 2,
3
Logical "0", Vcc = 4.75V
0.8
V
1, 2,
3
Iin
Input Current
Logical "1", Vin = 5V
Logical "0", Vin = 0V
1.0
2.3
uA
uA
V
1, 2,
3
-1.0
2.7
1, 2,
3
Vt+
Vt-
Vh
CLK IN Positive
Going Threshold
Voltage
1, 2,
3
CLK IN Negative
Going Threshold
Voltage
V
V
1, 2,
3
CLK IN Hysteresis
"Vt+(min) -
Vt-(max)"
0.4
1, 2,
3
Vout
Output Voltage
Logical "1", Vcc=4.75V, Iout = -360uA
Logical "1", Vcc = 4.75V, Iout = -10uA
Logical "0", Vcc = 4.75V, Iout = 1.6mA
2.4
4.5
V
1, 2,
3
V
1, 2,
3
0.4
V
1, 2,
3
Iout
TRI-STATE Output Vout = 0V
Leakage Current
-3.0
uA
uA
mA
mA
mA
mA
mA
1, 2,
3
Vout = 5V
3.0
1, 2,
3
Isource
Isink
DIcc
AIcc
I-
Output Source
Current
Vout = 0V
Vout = 5V
Cs = "1"
Cs = "1"
-6.0
1, 2,
3
Output Sink
Current
8.0
1, 2,
3
DVcc Supply
Current
2.5
1, 2,
3
AVcc Supply
Current
10.0
10.0
1, 2,
3
V- Supply Current Cs = "1"
1, 2,
3
6
MILITARY DATA SHEET
MNADC1251CM-X REV 2A0
Electrical Characteristics
AC PARAMETERS:
(The following conditions apply to all the following parameters, unless otherwise specified.)
AC: DVcc = AVcc = +5V, V- = -5V, tr = tf = 20nS.
PIN-
NAME
SUB-
SYMBOL
fCLK
PARAMETER
CONDITIONS
NOTES
MIN
MAX UNIT
GROUPS
Clock Frequency
3.5
60
MHz 4, 5,
6
Clock Duty Cycle
40
%
4, 5,
6
tC
tC
tC
tC
Conversion Time
Using WR to Start
a Conversion
fCLK = 2.0MHz
27x"1/
fCLK"+
250nS
4, 5,
6
Conversion Time
Using WR to Start
a Conversion
fCLK = 3.5MHz, AZ= "1"
fCLK = 1.75MHz, AZ = "0"
AZ = "1"
7.95
uS
4, 5,
6
Conversion Time
Using WR to Start
a Conversion
15.65 uS
4, 5,
6
Conversion Time
Using S/H to
Start a
34x"1/
fCLK"+
250nS
4, 5,
6
Conversion
tC
Conversion Time
Using S/H to
Start a
fCLK = 3.5MHz, AZ = "1"
9.95
uS
uS
4, 5,
6
Conversion
tA
Acquisition Time Resource = 50 Ohm
3.5
4, 5,
6
tIA
Internal
7x"1/
fCLK"
4, 5,
6
Acquisition Time
(When Using
WR Control Only)
tZA
Auto Zero Time +
Acquisition Time
33x"1/
fCLK"+
250nS
4, 5,
6
fCLK = 1.75MHz
19.05 uS
4, 5,
6
tD(EOC)L
tCAL
Delay from Hold
Command to
Falling Edge of
EOC
Using WR Control
Using S/H Control
350
150
nS
nS
4, 5,
6
4, 5,
6
Calibration Time
1399x"
1/
fCLK"
4, 5,
6
tCAL
Calibration Time fCLK = 3.5MHz
400
uS
nS
4, 5,
6
tW(CAL)L
Calibration Pulse
Width
200
4, 5,
6
7
MILITARY DATA SHEET
MNADC1251CM-X REV 2A0
Electrical Characteristics
AC PARAMETERS:(Continued)
(The following conditions apply to all the following parameters, unless otherwise specified.)
AC: DVcc = AVcc = +5V, V- = -5V, tr = tf = 20nS.
PIN-
NAME
SUB-
SYMBOL
PARAMETER
CONDITIONS
NOTES
MIN
200
MAX UNIT
GROUPS
tW(WR)L
Minimum WR Pulse
Width
nS
4, 5,
6
tACC
Maximum Access
Time (Delay from
Falling Edge of
RD to Output Data
Valid)
Cl = 100pF
95
nS
4, 5,
6
t0H, t1H
tPD(INT)
tRR
TRI-STATE Control Rl = 1K Ohm, Cl = 100pF
(Delay from
70
nS
nS
nS
4, 5,
6
Rising Edge of
RD to Hi-Z State)
Maximum Delay
from Falling Edge
of RD or WR to
Reset of INT
175
4, 5,
6
Delay between
Sucessive
RD Pulses
60
4, 5,
6
Note 1: Positive linearity error is defined as the deviation of the analog value, expressed
in LSB's, from the straight line that passes through positive full scale and zero.
For negative linearity error the straight line passes through negative full scale and
zero.
Note 2: The ADC1251's self-calibration technique ensures linearity, full scale, and offset
errors as specified, but noise inherent in the self-calibration process will result
in a repeatability uncertainty of +0.20 LSB.
Note 3: If TA changes then an Auto-Zero or Auto-Cal cycle will have to be re-started.
Note 4: When using the WR control to start a conversion if the clock is asynchronous to the
rising edge of WR an uncertainty of one clock period will exist in the end of the
interval TA, therefore making TA end a minimum 6 clock periods or a maximum 7 clock
periods after the rising edge of WR. If the falling edge of the clock is synchronous
to the rising edge of WR then TA will end exactly 6.5 clock period after the rising
edge of WR. This does not occur when S/H control is used.
Note 5: The CAL line must be high before a conversion is started.
8
MILITARY DATA SHEET
MNADC1251CM-X REV 2A0
Graphics and Diagrams
GRAPHICS#
DESCRIPTION
6170HRA1
J24ARK
24 LEAD CERDIP (J) (B/I CKT)
24 LEAD CERDIP (J) (P/P DWG)
See attached graphics following this page.
9
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