ADC12D1620QML-SP_V01 [TI]
ADC12D1620QML-SP 12-Bit, Single Or Dual, 3200- or 1600-MSPS RF Sampling Analog-to-Digital Converter (ADC);
| 型号： | ADC12D1620QML-SP_V01 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | ADC12D1620QML-SP 12-Bit, Single Or Dual, 3200- or 1600-MSPS RF Sampling Analog-to-Digital Converter (ADC) |
| 文件： | 总83页 (文件大小：3455K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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ADC12D1620QML-SP
SNAS717 –APRIL 2017
ADC12D1620QML-SP 12-Bit, Single Or Dual, 3200- or 1600-MSPS RF Sampling
Analog-to-Digital Converter (ADC)
1 Features
3 Description
The ADC12D1620QML device uses
a package
1
•
Total Ionizing Dose (TID) to 300 krad(Si)
Single Event Functional Interrupt (SEFI) Tested
Single Event Latch-up (SEL) > 120 MeV-cm2/mg
Cold Sparing Capable
redesign to achieve better ENOB, SNR, and X-talk
compared to the ADC12D1600QML. As is its
predecessor, the ADC12D1620QML is a low-power,
high-performance CMOS analog-to-digital converter
(ADC) that digitizes signals at a 12-bit resolution at
sampling rates up to 3.2 GSPS in an interleaved
mode. It can also be used as a dual-channel ADC for
sampling rates up to 1.6 GSPS. For sampling rates
below 800 MHz, there is a low-sampling power-
saving mode (LSPSM) that reduces power
consumption to less than 1.4 W per channel (typical).
The ADC can support conversion rates as low as 200
MSPS.
•
•
•
•
•
Wide Temperature Range –55°C to +125°C
Power Consumption = 3.8 W or 2.7 W (1600- or
800-MHz Clock)
•
•
3-dB Input Bandwidth = 3 GHz
Low-Sampling Power-Saving Mode (LSPSM)
Reduces Power Consumption and Improves
Performance for fCLK ≤ 800 MHz
•
•
•
•
Auto-Sync Function for Multi-Chip Systems
Time Stamp Feature to Capture External Trigger
Test Patterns at Output for System Debug
Device Information(1)
PART NUMBER
GRADE
PACKAGE
ADC12D1620CCMLS Flight 300 krad
CCGA (376)
1:1 Non-Demuxed or 1:2 or 1:4 Parallel Demuxed
LVDS Outputs
Pre-flight engineering
prototype
ADC12D1620CCMPR
ADC10D1000DAISY
CCGA (376)
•
Single 1.9-V Power Supply
Daisy chain, mechanical
sample, no die
CCGA (376)
CLGA (256)
CLGA (256)
2 Applications
ADC12D1620LGMLS Flight 300 krad
•
•
•
Direct RF Down Conversion
Pre-flight engineering
prototype
ADC12D1620LGMPR
ADC10D1000LDAZ
Satellite Wideband Communications
Synthetic Aperture RADAR and LIDAR
Daisy chain, mechanical
sample, no die
CLGA (256)
(1) For all available packages, see the package orderable
addendum (POA) at the end of the data sheet.
space
Functional Block Diagram
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
ADC12D1620QML-SP
SNAS717 –APRIL 2017
www.ti.com
Table of Contents
6.18 Timing Diagrams................................................... 27
6.19 Typical Characteristics.......................................... 32
Detailed Description ............................................ 37
7.1 Overview ................................................................. 37
7.2 Functional Block Diagram ....................................... 37
7.3 Feature Description................................................. 38
7.4 Device Functional Modes........................................ 46
7.5 Programming .......................................................... 47
7.6 Register Maps......................................................... 52
Application and Implementation ........................ 59
8.1 Application Information............................................ 59
8.2 Radiation Environments.......................................... 66
8.3 Cold Sparing ........................................................... 66
Power Supply Recommendations...................... 68
9.1 System Power-On Considerations.......................... 68
1
2
3
4
5
6
Features.................................................................. 1
Applications ........................................................... 1
Description ............................................................. 1
Revision History..................................................... 2
Pin Configuration and Functions......................... 3
Specifications....................................................... 12
6.1 Absolute Maximum Ratings .................................... 12
6.2 ESD Ratings............................................................ 12
6.3 Recommended Operating Conditions..................... 12
6.4 Thermal Information................................................ 13
7
8
9
6.5 Converter Electrical Characteristics: Static Converter
Characteristics ......................................................... 13
6.6 Converter Electrical Characteristics: Dynamic
Converter Characteristics......................................... 15
6.7 Converter Electrical Characteristics: Analog
Input/Output and Reference Characteristics............ 17
10 Layout................................................................... 69
10.1 Layout Guidelines ................................................. 69
10.2 Layout Example .................................................... 71
10.3 Thermal Considerations........................................ 73
10.4 Board Mounting Recommendation ....................... 73
11 Device and Documentation Support ................. 75
11.1 Device Support .................................................... 75
11.2 Receiving Notification of Documentation Updates 77
11.3 Community Resources.......................................... 77
11.4 Trademarks........................................................... 77
11.5 Electrostatic Discharge Caution............................ 77
11.6 Glossary................................................................ 77
6.8 Converter Electrical Characteristic: Channel-to-
Channel Characteristics........................................... 18
6.9 Converter Electrical Characteristics: LVDS CLK Input
Characteristics ........................................................ 18
6.10 Electrical Characteristics: AutoSync Feature........ 19
6.11 Converter Electrical Characteristics: Digital Control
and Output Pin Characteristics ................................ 19
6.12 Converter Electrical Characteristics: Power Supply
Characteristics ........................................................ 21
6.13 Converter Electrical Characteristics: AC Electrical
Characteristics ......................................................... 23
6.14 Electrical Characteristics: Delta Parameters......... 24
6.15 Timing Requirements: Serial Port Interface.......... 25
6.16 Timing Requirements: Calibration......................... 26
6.17 Quality Conformance Inspection........................... 26
12 Mechanical, Packaging, and Orderable
Information ........................................................... 77
12.1 Engineering Samples............................................ 78
4 Revision History
DATE
REVISION
NOTES
April 2017
*
Initial release
2
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SNAS717 –APRIL 2017
5 Pin Configuration and Functions
The center ground pins are for thermal dissipation and must be soldered to a ground plane to ensure
rated performance. See Layout Guidelines for more information.
NAA Package
376-Pin CCGA and CLGA
Top View
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
GND
V_A
SDO
T PM
NDM
V_A
GND
V_E
GND_E
DId0+
V_DR
DId3+
GND_DR
DId6+
V_DR
DId9+
GND_DR
DId11+
DId11-
GND_DR
A
B
C
D
E
F
A
B
C
D
E
F
Vbg
Rtrim+
V_A
GND
Vcmo
ECEb
Rext+
Rext-
RSV1
SDI
SCSb
GND
CalRun
SCLK
GND
V_A
GND
CAL
GND
V_A
GND_E
V_E
V_E
GND_E
V_A
DId0-
DId1+
DId1-
DId2+
DId2-
V_DR
DId3-
DId4+
DId4-
DId5+
DId5-
DId6-
DId7+
DId7-
DId8+
DId8-
V_DR
DId9-
DId10-
DId10+
DI0-
DI0+
V_DR
DI3+
DI1+
DI2+
DI1-
DI2-
Rtrim-
T diode+
VbiasI
V_A
GND_DR
GND_DR
V_DR
DI4+
DI4-
V_A
GND
GND_DR
GND_DR
DI7+
DI3-
DI5+
DI5-
1
2
3
4
5
6
7
8
9
10
11
V_A
GND_T C T diode-
RSV2
V_T C
V_A
DI6+
DI6-
GND_DR
DI8-
AA
AB
AC
AD
AE
AF
AG
AH
AJ
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
V_T C
VinI+
VinI-
GND
GND_T C
V_T C
V_T C
GND_T C
V_T C
DI7-
DI8+
G
H
J
G
H
J
GND
GND
GND
GND
GND
GND
GND
GND
GND
DI9+
DI9-
DI10+
DI11-
DI10-
GND_T C
VbiasI
VbiasI
GND_T C
GND_T C
VbiasQ
V_A
V_DR
DI11+
ORI-
V_DR
DCLKI-
V_T C
ORI+
DCLKI+
K
L
K
L
GND
VbiasQ
GND_T C
V_T C
V_T C
ORQ+
GND_DR
DQ9+
ORQ-
DQ11+
DQ9-
DQ7-
DQ6+
DQ3-
DQ3+
GND_DR
DQ0+
DCLKQ+ DCLKQ-
VinQ-
VinQ+
V_T C
V_A
V_T C
DQ11-
DQ10+
DQ8+
DQ6-
GND_DR
DQ10-
DQ8-
M
N
P
R
T
M
N
P
R
T
GND_T C
V_T C
GND_T C
GND_T C
V_T C
V_T C
GND
DQ7+
AK
AL
V_T C
V_DR
V_DR
DQ5-
V_A
GND_T C GND_T C
V_DR
DQ5+
DQ4+
DQ2+
DQ1+
GND_T C
CLK-
CLK+
PDI
PDQ
RSV
FSR
GND
GND
DES
RCOut1- VbiasQ
RCOut2+ RCOut2-
V_A
V_A
DQd1-
V_DR
DQd4-
GND_DR
DQd7-
V_DR
V_DR
DQd10-
DQd9-
GND_DR
DQ0-
DQ4-
U
V
W
Y
U
V
W
Y
DCLK_R
ST +
LSPSM
DDRPh
V_E
GND_E
V_E
GND_E
V_E
DQd1+
DQd0-
DQd0+
DQd2-
DQd2+
V_DR
DQd4+
DQd3-
DQd5-
DQd5+
DQd7+
DQd6-
DQd8-
DQd8+
V_DR
DQ2-
DCLK_R
ST -
GND
V_A
RCLK-
V_A
V_A
GND
GND
DQd10+
DQ1-
GND
RCLK+ RCOut1+
GND_E
DQd3+ GND_DR DQd6+
DQd9+ GND_DR DQd11+
DQd11- GND_DR
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
The center ground pins are for thermal dissipation and must be soldered to a ground plane to ensure rated
performance. See Layout Guidelines for more information.
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Pin Functions: Analog Front-End and Clock Pins
PIN
TYPE
DESCRIPTION
EQUIVALENT CIRCUIT
NAME
NO.
ANALOG FRONT-END AND CLOCK PINS
V
A
Differential converter sampling clock. In the non-
DES mode, the analog inputs are sampled on the
positive transitions of this clock signal. In the DES
mode, the selected input is sampled on both
transitions of this clock. This clock must be AC-
coupled.
CLK+
CLK–
50k
50k
AGND
U2/V1
V2/W1
Y4/W5
I
100
V
BIAS
V
A
AGND
V
A
Differential DCLK reset. A positive pulse on this
input is used to reset the DCLKI and DCLKQ
outputs of two or more ADC12D1620 devices in
order to synchronize them with other ADC12D1620
devices in the system. DCLKI and DCLKQ are
always in phase with each other, unless one
channel is powered down, and do not require a
pulse from DCLK_RST to become synchronized.
The pulse applied here must meet timing
relationships with respect to the CLK input. Although
supported, this feature has been superseded by
AutoSync.
AGND
DCLK_RST+
DCLK_RST–
I
100
V
A
AGND
V
A
Reference clock input. When the AutoSync feature
is active, and the ADC12D1620 is in slave mode,
the internal divided clocks are synchronized with
respect to this input clock. The delay on this clock
may be adjusted when synchronizing multiple ADCs.
This feature is available in ECM with the DRC bits of
the AutoSync Control Register (Addr: Eh, Bits:
15:7).
RCLK+
RCLK–
50k
50k
AGND
I
100
V
BIAS
V
A
AGND
V
A
Reference clock output 1 and 2. These signals,
when enabled, provide a reference clock. The
RCOut rates for all of the available modes can be
found in Table 8; the rates displayed in the table are
independent of whether the ADC is in master or
slave mode. RCOut1 and RCOut2 are used to drive
the RCLK of ADC12D1620 to enable automatic
synchronization for multiple ADCs (AutoSync
feature). The impedance of each trace from RCOut1
and RCOut2 to the RCLK of ADC12D1620 should
be 100-Ω differential. Having two clock outputs
allows the auto-synchronization to propagate as a
binary tree. Use the DOC bit of the AutoSync
Control Register (Addr: Eh; Bit: 1) to enable or
disable this feature; default is disabled.
100W
100W
RCOut1+,
RCOut1–
RCOut2+,
RCOut2–
Y5/U6
V6/V7
O
-
+
A GND
4
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Pin Functions: Analog Front-End and Clock Pins (continued)
PIN
TYPE
DESCRIPTION
EQUIVALENT CIRCUIT
NAME
NO.
V
A
External reference resistor terminals. Connect a 3.3-
kΩ, ±0.1% resistor between Rext+, Rext–. The Rext
resistor is used as a reference to trim internal
circuits that affect the linearity of the converter; the
value and precision of this resistor must not be
compromised.
Rext+
Rext–
C3/D3
I/O
V
GND
V
A
Input termination trim resistor terminals. Connect a
3.3-kΩ, ±0.1%resistor between Rtrim+/ Rtrim–. The
Rtrim resistor is used to establish the calibrated
100-Ω input impedance of Vinl, VinQ, and CLK.
These impedances may be fine-tuned by varying the
value of the resistor by a corresponding percentage;
however, the tuning range and performance is not
tested for such an alternative values.
Rtrim+
Rtrim–
C1/D2
I/O
V
GND
V
A
Tdiode_P
Temperature sensor diode positive (anode) and
negative (cathode) terminals. This set of pins is
used for die temperature measurements. It has not
been fully characterized.
GND
A
Tdiode+
Tdiode–
E2/F3
O
V
Tdiode_N
GND
V
A
Bandgap voltage output or LVDS common-mode
voltage select. This pin provides a buffered version
of the bandgap output voltage; it is capable of
sourcing/sinking 100 μA and driving a load of up to
80 pF. Alternately, this pin may be used to select
the LVDS digital output common-mode voltage. If
tied to logic-high, the 1.2-V LVDS common-mode
voltage is selected; 0.8 V is the default.
VBG
B1
I/O
GND
V
A
Common-mode voltage. This pin is the common-
mode output in DC-coupling mode and also serves
as the AC-coupling mode select pin. When DC-
coupling is used at the analog inputs, the voltage
output at this pin is required to be the common-
mode input voltage at VIN+ and VIN−. When AC-
coupling is used, this pin must be grounded. This
pin is capable of sourcing or sinking 100 μA.
V
CMO
200k
VCMO
C2
I/O
Enable AC
Coupling
8 pF
GND
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Pin Functions: Analog Front-End and Clock Pins (continued)
PIN
TYPE
DESCRIPTION
EQUIVALENT CIRCUIT
NAME
NO.
Differential signal I and Q inputs. In the non-dual
edge sampling (non-DES) mode, each I and Q input
is sampled and converted by its respective channel
with each positive transition of the CLK input. In
non-ECM (non-extended control mode) and DES
mode, both channels sample the
I input. In
Extended Control mode (ECM), the Q input may
optionally be selected for conversion in DES mode
by the DEQ Bit of the Configuration Register (Addr:
0h; Bit: 6).
V
A
Each I- and Q-channel input has an internal
common mode bias that is disabled when DC-
coupled mode is selected. Both inputs must be
either AC- or DC-coupled. The coupling mode is
selected by the VCMO pin.
50k
AGND
100
V
CMO
VinI+, VinI–
VinQ+, VinQ–
H1/J1
N1/M1
I
Control from V
CMO
V
A
In non-ECM, the full-scale range of these inputs is
determined by the FSR pin; both I and Q channels
have the same full-scale input range. In ECM, the
full-scale input range of the I- and Q-channel inputs
may be independently set with the I- and Q-channel
Full-Scale Range Adjust Registers (Addr: 3h and
Addr: Bh, respectively). The high and low full-scale
input range setting in non-ECM corresponds to the
mid and minimum full-scale input range in ECM.
50k
AGND
The input offset may also be adjusted in ECM with
the I- and Q-channel Offset Adjust Registers (Addr:
2h and Addr: Ah, respectively).
CONTROL AND STATUS PINS
Calibration cycle initiate. The user can command the
device to execute a self-calibration cycle by holding
this input high for a minimum of tCAL_H after having
held it low for a minimum of tCAL_L. This pin is active
in both ECM and non-ECM. In ECM, this pin is
logically OR'd with the CAL Bit of the Configuration
Register (Addr: 0h, Bit 15). Therefore, both the pin
and bit must be set low and then either can be set
high to execute an on-command calibration. TI
recommends holding the CAL pin high during
normal usage to reduce the chance that an SEU
causes a calibration cycle.
V
A
CAL
D6
I
GND
V
A
Calibration running indication. This output is logic-
high while the calibration sequence is executing;
otherwise, this output is logic-low.
CalRun
B5
O
GND
6
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Pin Functions: Analog Front-End and Clock Pins (continued)
PIN
TYPE
DESCRIPTION
EQUIVALENT CIRCUIT
NAME
NO.
DDR phase select. In DDR, when this input is logic-
low, it selects the 0° data-to-DCLK phase
relationship. When this input is logic-high, it selects
the 90° data-to-DCLK phase relationship; that is, the
DCLK transition indicates the middle of the valid
data outputs.
V
A
In SDR, when this input is logic-low, the output
transitions on the rising edge of DCLK. When this
input is logic-high, output transition is on the falling
edge of DCLK.
DDRPh
W4
I
This pin only has an effect when the chip is in 1:2
demuxed mode; that is, the NDM pin is set to logic-
low. In ECM, this input is ignored and the DDR
phase is selected through the Control Register by
the DPS bit (Addr: 0h, Bit 14); the default is 0°
mode.
GND
Dual edge sampling (DES) mode select. In the non-
extended control mode (Non-ECM), when this input
is set to logic-high, the DES mode of operation is
selected; this means that the VinI input is sampled
by both channels in a time-interleaved manner and
the VinQ input is ignored.
V
A
DES
V5
I
When this input is set to logic-low, the device is in
non-DES mode; that is, I and Q channels operate
independently. In the extended control mode (ECM),
this input is ignored and DES mode selection is
controlled through the DES bit of the Configuration
Register (Addr: 0h; Bit: 7); default is non-DES mode
operation.
GND
Extended control enable. Extended feature control
through the SPI interface is enabled and the device
is in ECM when this signal is asserted (logic-low).
Please reference Table 1 for information on the
behavior of the control pins when the extended
feature control is enabled.
V
V
V
A
50 kW
ECE
B3
Y3
V4
I
I
I
When this signal is de-asserted (logic-high), the SPI
interface is disabled, all SPI registers are reset to
their default values, and all available settings are
controlled with the control pins.
GND
Full-scale input range select. In non-ECM, when this
input is set to logic-low or logic-high, the full-scale
differential input range for both I- and Q-channel
inputs is set to the lower or higher FSR value,
respectively. In the ECM, this input is ignored and
the full-scale range of the I- and Q-channelinputs is
independently determined by the setting of the I-
and Q-channel Full-Scale Range Adjust Registers
(Addr: 3h and Addr: Bh, respectively). Note that the
high (lower) FSR value in non-ECM corresponds to
the mid (min) available selection in ECM; the FSR
range in ECM is greater.
A
FSR
GND
Low-sampling power-saving mode (LSPSM) select.
In LSPSM, the power consumption is reduced by
approximately 20%, and some improvement in
performance may be seen. The output is in SDR in
1:2 demux mode and DDR in 1:1 non-demux mode.
DDR is not available in 1:2 demux mode in LSPSM.
The maximum sampling rate in LSPSM in non-DES
mode is 800 MSPS. When this input is logic-high,
the device is in LSPSM and when this input is logic-
low, the device is in normal mode or non-LSPSM.
A
LSPSM
GND
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Pin Functions: Analog Front-End and Clock Pins (continued)
PIN
TYPE
DESCRIPTION
EQUIVALENT CIRCUIT
NAME
NO.
V
A
Non-demuxed mode select. Setting this input to
logic-high causes the digital output bus to be in the
1:1 non-demuxed mode. Setting this input to logic-
low causes the digital output bus to be in the 1:2
demuxed mode. This feature is pin-controlled only
and remains active during both ECM and non-ECM.
NDM
A5
I
GND
V
Power down I and Q channels. Setting either input
to logic-high powers down the respective I or Q
channel. Setting either input to logic-low brings the
respective I or Q channel to a operational state after
a finite time delay. This pin is active in both ECM
and non-ECM. In ECM, each pin is logically OR'd
with its respective bit. Therefore, either this pin or
the PDI and PDQ bits in the Configuration Register
(Addr: 0h; Bit: 11 and Bit: 10, respectively) can be
used to power down the I and Q channels.
A
50 kW
PDI
PDQ
U3
V3
I
GND
Reserved. This pin is used for internal purposes and
must be connected to GND through a 100-kΩ
resistor.
RSV
W3
—
NONE
Decouple this pin with a 100-nF capacitor with a low
resistance, low inductance path to GND.
RSV1
RSV2
E3
F4
—
—
NONE
NONE
Decouple this pin with a 100-nF capacitor with a low
resistance, low inductance path to GND.
V
A
Serial clock. In ECM, serial data is shifted into and
out of the device synchronously to this clock signal.
This clock may be disabled and held logic-low, as
long as timing specifications are not violated when
the clock is enabled or disabled.
100 kW
100 kW
100 kW
SCLK
SCS
SDI
C5
C4
B4
I
I
I
GND
V
A
Serial chip select. In ECM, when this signal is
asserted (logic-low), SCLK is used to clock in serial
data that is present on SDI and to source serial data
on SDO. When this signal is de-asserted (logic-
high), SDI is ignored and SDO is tri-state.
GND
V
A
Serial data-in. In ECM, serial data is shifted into the
device on this pin while SCS signal is asserted
(logic-low).
GND
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Pin Functions: Analog Front-End and Clock Pins (continued)
PIN
TYPE
DESCRIPTION
EQUIVALENT CIRCUIT
NAME
NO.
V
A
Serial data-out. In ECM, serial data is shifted out of
the device on this pin while SCS signal is asserted
(logic-low). This output is tri-state when SCS is de-
asserted (logic-high).
SDO
A3
O
GND
V
A
Test pattern mode select. With this input at logic-
high, the device continuously outputs a fixed,
repetitive test pattern at the digital outputs. In ECM,
this input is ignored, and the test pattern mode can
only be activated through the Control Register by
the TPM bit (Addr: 0h, Bit: 12).
TPM
A4
I
GND
POWER AND GROUND PINS
A1, A7, B2,
B7, C6, D4,
D5, E4, K1, L1,
T4, U4, U5,
W2, W7, Y1,
Y7, AA2:AL11
GND
P
P
Analog ground return
NONE
NONE
A13, A17, A20,
D13, D16, E17,
F17, F20, M17,
M20, U13,
U17, V18, Y13,
Y17, Y20
GNDDR
Ground return for the output drivers
Ground return for the digital encoder
A9, B8, C9,
V9, W8, Y9
GNDE
P
P
NONE
NONE
F2, G2, H3, J2,
K4, L4, M2,
N3, P2, R2,
Ground return for the track-and-hold and clock
circuitry
GNDTC
T2, T3, U1
A2, A6, B6,
C7, D1, D8,
D9, E1, F1,
H4, N4, R1,
T1, U8, U9,
W6, Y2, Y6
Analog power supply. This supply is tied to the ESD
ring; therefore, it must be powered up before or with
any other supply.
VA
P
NONE
Bias voltage I channel. This is an externally
decoupled bias voltage for the I channel. Each pin
must individually be decoupled with a 100-nF
capacitor through a low resistance, low inductance
path to GND.
VbiasI
D7, J4, K2
L2, M4, U7
P
P
NONE
NONE
Bias voltage Q channel. This is an externally
decoupled bias voltage for the Q channel. Each pin
must individually be decoupled with a 100-nF
capacitor through a low resistance, low inductance
path to GND.
VbiasQ
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Pin Functions: Analog Front-End and Clock Pins (continued)
PIN
TYPE
DESCRIPTION
EQUIVALENT CIRCUIT
NAME
NO.
A11, A15, C18,
D11, D15,
D17, J17, J20,
R17, R20, T17,
U11, U15,
VDR
P
Power supply for the output drivers
Power supply for the digital encoder
NONE
U16, Y11, Y15
A8, B9, C8,
V8, W9, Y8
VE
P
P
NONE
NONE
G1, G3, G4,
H2, J3, K3, L3,
M3, N2, P1,
Power supply for the track-and-hold and clock
circuitry
VTC
P3, P4, R3, R4
HIGH-SPEED DIGITAL OUTPUT PINS
VDR
Data clock output for the I- and Q-channel data bus.
These differential clock outputs are used to latch the
output data and, if used, terminate with a 100-Ω
differential resistor placed as closely as possible to
the differential receiver. Delayed and non-delayed
data outputs are supplied synchronously to this
signal. The DCLK rates for all of the available
modes can be found in Table 8. DCLKI and DCLKQ
are always in phase with each other, unless one
channel is powered down, and do not require a
pulse from DCLK_RST to become synchronized.
DCLKI+,
DCLKI–
DCLKQ+,
DCLKQ–
-
+
-
K19/K20
L19/L20
O
+
DR GND
DI11+, DI11–
DI10+, DI10–
DI9+, DI9–
DI8+, DI8–
DI7+, DI7–
DI6+, DI6–
DI5+, DI5–
DI4+, DI4–
DI3+, DI3–
DI2+, DI2–
DI1+,DI1 –
DI0+, DI0–
·
DQ11+, DQ11–
DQ10+, DQ10–
DQ9+, DQ9–
DQ8+, DQ8–
DQ7+, DQ7–
DQ6+, DQ6–
DQ5+, DQ5–
DQ4+, DQ4–
DQ3+, DQ3–
DQ2+, DQ2–
DQ1+, DQ1–
DQ0+, DQ0–
J18/J19
H19/H20
H17/H18
G19/G20
G17/G18
F18/F19
E19/E20
D19/D20
D18/E18
C19/C20
B19/B20
B18/C17
·
M18/M19
N19/N20
N17/N18
P19/P20
P17/P18
R18/R19
T19/T20
U19/U20
U18/T18
V19/V20
W19/W20
W18/V17
VDR
I- and Q-channel digital data outputs. In non-demux
mode, this LVDS data is transmitted at the sampling
clock rate. In demux mode, these outputs provide ½
the data at ½ the sampling clock rate, synchronized
with the delayed data; that is, the other ½ of the
data which was sampled one clock cycle earlier.
Compared with the DId and DQd outputs, these
outputs represent the later time samples. If used,
terminate each of these outputs with a 100-Ω
differential resistor placed as closely as possible to
the differential receiver.
-
+
-
O
+
DR GND
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Pin Functions: Analog Front-End and Clock Pins (continued)
PIN
TYPE
DESCRIPTION
EQUIVALENT CIRCUIT
NAME
NO.
DId11+, DId11–
DId10+, DId10–
DId9+, DId9–
DId8+, DId8–
DId7+, DId7–
DId6+, DId6–
DId5+, DId5–
DId4+, DId4–
DId3+, DId3–
DId2+, DId2–
DId1+,DId1 –
DId0+, DId0–
·
DQd11+, DQd11–
DQd10+, DQd10–
DQd9+, DQd9–
DQd8+, DQd8–
DQd7+, DQd7–
DQd6+, DQd6–
DQd5+, DQd5–
DQd4+, DQd4–
DQd3+, DQd3–
DQd2+, DQd2–
DQd1+, DQd1–
DQd0+, DQd0–
A18/A19
B17/C16
A16/B16
B15/C15
C14/D14
A14/B14
B13/C13
C12/D12
A12/B12
B11/C11
C10/D10
A10/B10
·
Y18/Y19
W17/V16
Y16/W16
W15/V15
V14/U14
Y14/W14
W13/V13
V12/U12
Y12/W12
W11/V11
V10/U10
Y10/W10
VDR
Delayed I- and Q-channel digital data outputs. In
non-demux mode, these outputs are tri-state. In
demux mode, these outputs provide ½ the data at ½
the sampling clock rate, synchronized with the non-
delayed data; that is, the other ½ of the data which
was sampled one clock cycle later. Compared with
the DI and DQ outputs, these outputs represent the
earlier time samples. If used, terminate each of
these outputs with a 100-Ω differential resistor
placed as closely as possible to the differential
receiver.
-
+
-
O
+
DR GND
VDR
Out-of-range output for the I and Q channel. This
differential output is asserted logic-high while the
over- or under-range condition exists; that is, the
differential signal at each respective analog input
exceeds the full-scale value. Each OR result refers
to the current data, with which it is clocked out. If
used, terminate each of these outputs with a 100-Ω
differential resistor placed as closely as possible to
the differential receiver.
ORI+,
ORI–
ORQ+,
ORQ–
-
+
-
K17/K18
L17/L18
O
+
DR GND
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)(1)(2)
MIN
MAX
2.2
UNIT
V
Supply voltage (VA, VTC, VDR, VE)
Supply difference – max(VA/TC/DR/E) – min(VA/TC/DR/E
)
0
100
2.35
2.5
mV
V
Voltage on any input pin (except VinI+, VinI–, VinQ+, VinQ–)
VinI+, VinI–, VinQ+, VinQ– voltage (maintaining common mode)(3)
Input current at VinI+, VinI–, VinQ+, VinQ–(3)
−0.15
−0.15
V
±50
100
±50
4.4
mA
mV
mA
W
Ground difference – max(GNDTC/DR/E) – min(GNDTC/DR/E
Input current at any pin(4)
Power dissipation at TA ≤ 125°C(4)
Storage temperature, Tstg
)
0
−65
150
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are measured with respect to GND = GNDDR = GNDE = GNDTC = 0 V, unless otherwise specified.
(3) Verified during product qualification high-temperature lifetime testing (HTOL) at TJ = 150°C for 1000 hours continuous operation with VA
= VD = 2.2 V.
(4) When the input voltage at any pin exceeds the power supply limits, the current at that pin must be limited to 50 mA. In addition,
overvoltage at a pin must adhere to maximum voltage limits. Simultaneous overvoltage at multiple pins requires adherence to the
maximum package power dissipation limits, which are calculated using the JEDEC JESD51-7 thermal model. Higher dissipation may be
possible based on customer-specific thermal situations and specified thermal package resistances from junction to case.
6.2 ESD Ratings
VALUE
UNIT
V(ESD)
Electrostatic discharge
Human-body Model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±2500
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 500-V HBM is possible with the necessary precautions.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)(1)
MIN
−55
MAX UNIT
Case temperature
125
2
°C
V
Supply voltage (VA, VTC, VE)
1.8
Voltage on any input pin (except VinI+, VinI–, VinQ+, VinQ–)
−0.15
1.8
2.15
VA
2.4
1
V
Driver supply voltage (VDR
)
V
VinI+, VinI–, VinQ+, VinQ– voltage(2)
VinI+, VinI–, VinQ+, VinQ– differential voltage(3)
VinI+, VinI–, VinQ+, VinQ– current(2)
DC-coupled
–0.4
V
DC-coupled at 100% duty cycle
DC-coupled at 20% duty cycle
DC-coupled at 10% duty cycle
AC-coupled
2
V
2.8
50
–50
mA
Maintaining common-mode voltage,
AC-coupled
15.3
VinI+, VinI–, VinQ+, VinQ– power
dBm
V
Not maintaining common-mode
voltage, AC-coupled
17.1
0
Ground difference – max(GNDTC/DR/E) – min(GNDTC/DR/E
)
(1) All voltages are measured with respect to GND = GNDDR = GNDE = GNDTC = 0 V, unless otherwise specified.
(2) Proper common mode voltage must be maintained to ensure proper output code, especially during input overdrive.
(3) This rating is intended for DC-coupled applications; the voltages and duty cycles listed may be safely applied to VIN± for the lifetime of
the part.
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Recommended Operating Conditions (continued)
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX UNIT
Input current at any pin except VinI+, VinI–, VinQ+, or VinQ–(4)
CLK+, CLK– voltage
±50
mA
V
0
0.4
VA
2
Differential CLK amplitude
VP-P
mV
VCMI common-mode input voltage
VCMO – 150
VCMO + 150
(4) When the input voltage at any pin exceeds the power supply limits, the current at that pin must be limited to 50 mA. In addition,
overvoltage at a pin must adhere to maximum voltage limits. Simultaneous overvoltage at multiple pins requires adherence to the
maximum package power dissipation limits, which are calculated using the JEDEC JESD51-7 thermal model. Higher dissipation may be
possible based on customer-specific thermal situations and specified thermal package resistances from junction to case.
6.4 Thermal Information
ADC12D1620QML-SP
THERMAL METRIC(1)(2)
NAA (CCGA)
UNIT
376 PINS
13.1
5.0
RθJA
RθJC(top)
RθJB
ψJT
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
5.1
Junction-to-top characterization parameter
Junction-to-board characterization parameter
2.6
ψJB
4.7
(1) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics
(2) Solder process specifications in Board Mounting Recommendation.
6.5 Converter Electrical Characteristics: Static Converter Characteristics
The following specifications apply after calibration for VA = VDR = VTC = VE = 1.9 V; I and Q channels AC-coupled, FSR pin =
high; CL = 10-pF; differential AC-coupled sine wave input clock, fCLK = 1.6 GHz at 0.5 VP-P with 50% duty cycle; VBG = floating;
non-extended control mode; Rext = Rtrim = 3300 Ω ±0.1%; analog signal source impedance = 100-Ω differential; 1:2
demultiplex non-DES mode; I and Q channels; duty-cycle stabilizer on.(1)(2)
PARAMETER
TEST CONDITIONS
SUB-GROUPS
MIN
TYP(3)
MAX UNIT
DC-coupled, 1 MHz sine wave over-
ranged
INL
Integral non-linearity
[1, 2, 3]
–7.5
±2.5
7.5
1.35
12
LSB
LSB
DC-coupled, 1 MHz sine wave over-
ranged
DNL
Differential non-linearity
[1, 2, 3]
[1, 2, 3]
–1.35
±0.5
Resolution with no
missing codes
bits
LSB
mV
VOFF
Offset error
8
Input offset adjustment
range
VOFF_ADJ
Extended control mode
±45
(1) The analog inputs are protected as shown below. Input voltage magnitudes beyond the Absolute Maximum Ratings may damage this
device.
V
A
TO INTERNAL
CIRCUITRY
I / O
GND
(2) To ensure accuracy, it is required that VA, VTC, VE and VDR be well bypassed. Each supply pin must be decoupled with separate bypass
capacitors.
(3) Typical figures are at TA = 25°C, and represent most likely parametric norms. Test limits are ensured to Texas Instrument's average
outgoing quality level (AOQL).
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Converter Electrical Characteristics: Static Converter Characteristics (continued)
The following specifications apply after calibration for VA = VDR = VTC = VE = 1.9 V; I and Q channels AC-coupled, FSR pin =
high; CL = 10-pF; differential AC-coupled sine wave input clock, fCLK = 1.6 GHz at 0.5 VP-P with 50% duty cycle; VBG = floating;
non-extended control mode; Rext = Rtrim = 3300 Ω ±0.1%; analog signal source impedance = 100-Ω differential; 1:2
demultiplex non-DES mode; I and Q channels; duty-cycle stabilizer on.(1)(2)
PARAMETER
TEST CONDITIONS
SUB-GROUPS
MIN
TYP(3)
MAX UNIT
PFSE
NFSE
Positive full-scale error See(4)
[1, 2, 3]
–30
30
mV
Negative full-scale
See(4)
[1, 2, 3]
–30
30
mV
error
(VIN+) − (VIN−) > positive full scale
(VIN+) − (VIN−) < negative full scale
[1, 2, 3]
[1, 2, 3]
4095
Out-of-range output
code
0
(4) Calculation of full-scale error for this device assumes that the actual reference voltage is exactly its nominal value. Full-scale error for
this device, therefore, is a combination of full-scale error and reference voltage error. For relationship between gain error and full-scale
error, see gain error in Device Nomenclature .
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6.6 Converter Electrical Characteristics: Dynamic Converter Characteristics
The following specifications apply after calibration for VA = VDR = VTC = VE = 1.9 V; I and Q channels AC-coupled, FSR pin =
high; CL = 10 pF; differential AC-coupled sine wave input clock, fCLK = 1.6 GHz at 0.5 VP-P with 50% duty cycle; VBG = floating;
non-extended control mode; Rext = Rtrim = 3300 Ω ±0.1%; analog signal source impedance = 100-Ω differential; 1:2
demultiplex non-DES mode; I and Q channels; duty-cycle stabilizer on.(1)(2)
PARAMETER
TEST CONDITIONS
SUB-GROUPS
MIN
TYP(3)
MAX
UNIT
Error/
Sample
CER
Code error rate
10–18
–76
–63
–80
–64
–72
–59
–77
–61
dBFS
dBc
fIN = 2070 MHz ± 2.5 MHz at –13
dBFS
dBFS
dBc
fIN = 2070 MHz ± 2.5 MHz at –16
dBFS
3rd order
intermodulation
distortion
IMD3
dBFS
dBc
fIN = 2670 MHz ± 2.5 MHz at –13
dBFS
dBFS
dBc
fIN = 2670 MHz ± 2.5 MHz at –16
dBFS
1:2 DEMUX, NON-DES MODE, NON-ECM, NON-LSPSM, fCLK = 1.6 GHz, fIN = 248 MHz, VIN = –0.5 dBFS
[4]
[5]
8.8
8.7
9.1
56.5
58.4
Effective number of
bits
ENOB
SINAD
bits
[6]
8.4
[4]
54.7
54.1
52.3
56
Signal-to-noise plus
distortion ratio
[5]
dBFS
dBFS
[6]
[4]
SNR
THD
Signal-to-noise ratio
[5]
54.6
53.5
[6]
dBFS
dBFS
dBFS
[4, 5]
[6]
–62
–59.2
–55.5
Total harmonic
distortion
2nd
Harm
Second harmonic
distortion
–72.2
dBFS
dBFS
3rd
Harm
Third harmonic
distortion
–62.1
62.1
[4]
[5]
[6]
58.9
58.1
56
dBFS
dBFS
Spurious-free dynamic
range
SFDR
(1) The analog inputs are protected as shown below. Input voltage magnitudes beyond the Absolute Maximum Ratings may damage this
device.
V
A
TO INTERNAL
CIRCUITRY
I / O
GND
(2) To ensure accuracy, it is required that VA, VTC, VE and VDR be well bypassed. Each supply pin must be decoupled with separate bypass
capacitors.
(3) Typical figures are at TA = 25°C, and represent most likely parametric norms. Test limits are ensured to Texas Instrument's average
outgoing quality level (AOQL).
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Converter Electrical Characteristics: Dynamic Converter Characteristics (continued)
The following specifications apply after calibration for VA = VDR = VTC = VE = 1.9 V; I and Q channels AC-coupled, FSR pin =
high; CL = 10 pF; differential AC-coupled sine wave input clock, fCLK = 1.6 GHz at 0.5 VP-P with 50% duty cycle; VBG = floating;
non-extended control mode; Rext = Rtrim = 3300 Ω ±0.1%; analog signal source impedance = 100-Ω differential; 1:2
demultiplex non-DES mode; I and Q channels; duty-cycle stabilizer on.(1)(2)
PARAMETER
TEST CONDITIONS
SUB-GROUPS
MIN
TYP(3)
MAX
UNIT
1:2 DEMUX, NON-DES MODE, NON-ECM, LSPSM, fCLK = 800 MHz, fIN = 248 MHz, VIN = –0.5 dBFS
[4, 5]
[6]
9.1
8.6
9.5
bits
Effective number of
bits
ENOB
SINAD
SNR
bits
[4, 5]
[6]
56.5
53.5
57.6
56.8
58.6
59.8
–67
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
Signal-to-noise plus
distortion ratio
[4, 5]
[6]
Signal-to-noise ratio
[4, 5]
[6]
–62.3
–57
Total harmonic
distortion
THD
2nd
Harm
Second harmonic
distortion
–77.7
dBFS
dBFS
3rd
Harm
Third harmonic
distortion
–67.5
67.4
[4, 5]
[6]
62.5
57.5
dBFS
dBFS
Spurious-free dynamic
range
SFDR
NON-DEMUX, NON-DES MODE, ECM, NON-LSPSM, fCLK = 1.6 GHz, fIN = 248 MHz, VIN = –0.5 dBFS
ENOB
Effective number of
bits
9.1
bits
SINAD Signal-to-noise plus
distortion ratio
56.6
58.6
dBFS
dBFS
dBFS
SNR
THD
Signal-to-noise ratio
Total harmonic
distortion
–63.2
2nd
Harm
Second harmonic
distortion
–72
–63.3
63.3
dBFS
dBFS
dBFS
3rd
Harm
Third harmonic
distortion
SFDR
Spurious-free dynamic
range
1:4 DEMUX, DES MODE, NON-LSPSM, fCLK = 1.6 GHz, fIN = 248 MHz, VIN = –0.5 dBFS
ENOB
Effective number of
bits
8.9
bits
SINAD Signal-to-noise plus
distortion ratio
55.5
56.9
dB
SNR
THD
Signal-to-noise ratio
dBFS
dBFS
Total harmonic
distortion
–62.3
2nd
Harm
Second harmonic
distortion
–79.1
–62.3
61.7
dBFS
dBFS
dBFS
3rd
Harm
Third harmonic
distortion
SFDR
Spurious-free dynamic
range
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6.7 Converter Electrical Characteristics: Analog Input/Output and Reference Characteristics
The following specifications apply after calibration for VA = VDR = VTC = VE = 1.9 V; I and Q channels AC-coupled, FSR pin =
high; CL = 10-pF; differential AC-coupled sine wave input clock, fCLK = 1.6 GHz at 0.5 VP-P with 50% duty cycle; VBG = floating;
non-extended control mode; Rext = Rtrim = 3300 Ω ±0.1%; analog signal source impedance = 100-Ω differential; 1:2
demultiplex non-DES mode; I and Q channels; duty-cycle stabilizer on.(1)(2)
SUB-
PARAMETER
TEST CONDITIONS
MIN
TYP(3)
MAX
UNIT
GROUPS
[4, 5, 6]
[4, 5, 6]
FSR pin Y3 Low
630
820
mVP-P
mVP-P
FSR pin Y3 High
750
890
EXTENDED CONTROL MODE
FM(14:0) = 0000h
Analog differential input
full-scale range
VIN_FSR
600
800
mVP-P
mVP-P
mVP-P
pF
FM(14:0) = 4000h (default)
FM(14:0) = 7FFFh
1000
0.02
Analog input
capacitance,
Non-DES mode
Differential
Each input pin to ground
(4)(5)
1.6
0.02
2.2
pF
pF
pF
CIN
Analog input
capacitance,
DES mode
Differential
Each input pin to ground
(4)(5)
Differential input
resistance
RIN
[1, 2, 3]
[1, 2, 3]
99
103
107
Ω
COMMON-MODE OUTPUT
Common-mode output
voltage
ICMO = ±100 μA
ICMO = ±100 μA
VCMO
1.15
1.25
38
1.35
V
Common-mode output
TC_VCMO voltage temperature
coefficient
ppm/°C
VCMO input threshold to
VCMO_LVL
0.63
V
set DC-coupling mode
Maximum VCMO load
CL_VCMO
See(5)
80
pF
capacitance
BANDGAP REFERENCE
Bandgap reference
output voltage
IBG = ±100 µA
IBG = ±100 µA
VBG
[1, 2, 3]
1.15
1.27
50
1.35
V
Bandgap reference
TC_VBG voltage temperature
coefficient
ppm/°C
Maximum bandgap
CLOAD
reference load
VBG
80
pF
capacitance
(1) The analog inputs are protected as shown below. Input voltage magnitudes beyond the Absolute Maximum Ratings may damage this
device.
V
A
TO INTERNAL
CIRCUITRY
I / O
GND
(2) To ensure accuracy, it is required that VA, VTC, VE and VDR be well bypassed. Each supply pin must be decoupled with separate bypass
capacitors.
(3) Typical figures are at TA = 25°C, and represent most likely parametric norms. Test limits are ensured to Texas Instrument's average
outgoing quality level (AOQL).
(4) The analog and clock input capacitances are die capacitances only. Additional package capacitances of 0.22-pF differential and 1.06-pF
each pin to ground are isolated from the die capacitances by lead and bond wire inductances.
(5) This parameter is specified by design and/or characterization and is not tested in production.
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6.8 Converter Electrical Characteristic: Channel-to-Channel Characteristics
The following specifications apply after calibration for VA = VDR = VTC = VE = 1.9 V; I and Q channels AC-coupled, FSR pin =
high; CL = 10 pF; differential AC-coupled sine wave input clock, fCLK = 1.6 GHz at 0.5 VP-P with 50% duty cycle; VBG = floating;
non-extended control mode; Rext = Rtrim = 3300 Ω ±0.1%; analog signal source impedance = 100-Ω differential; 1:2
demultiplex non-DES mode; I and Q channels; duty-cycle stabilizer on.(1)(2)
SUB-
GROUPS
PARAMETER
CONDITIONS
MIN
TYP(3)
MAX
UNIT
Phase matching (I, Q)
fIN = 1 GHz
< 1
Degree
dBFS
Crosstalk from I channel
(aggressor) to Q channel
(victim)
Aggressor = 248 MHz
Aggressor = 498 MHz
–72
X-TALK
Q-channel
–75
–71
–79
dBFS
dBFS
dBFS
Crosstalk from Q channel
(aggressor) to I channel
(victim)
Aggressor = 248 MHz
Aggressor = 498 MHz
X-TALK
I-channel
(1) The analog inputs are protected as shown below. Input voltage magnitudes beyond the Absolute Maximum Ratings may damage this
device.
V
A
TO INTERNAL
CIRCUITRY
I / O
GND
(2) To ensure accuracy, it is required that VA, VTC, VE and VDR be well bypassed. Each supply pin must be decoupled with separate bypass
capacitors.
(3) Typical figures are at TA = 25°C, and represent most likely parametric norms. Test limits are ensured to Texas Instrument's average
outgoing quality level (AOQL).
6.9 Converter Electrical Characteristics: LVDS CLK Input Characteristics
The following specifications apply after calibration for VA = VDR = VTC = VE = 1.9 V; I and Q channels AC-coupled, FSR pin =
high; CL = 10 pF; differential AC-coupled sine wave input clock, fCLK = 1.6 GHz at 0.5 VP-P with 50% duty cycle; VBG = floating;
non-extended control mode; Rext = Rtrim = 3300 Ω ±0.1%; analog signal source impedance = 100-Ω differential; 1:2
demultiplex non-DES mode; I and Q channels; duty-cycle stabilizer on.(1)(2)
SUB-
PARAMETER
CONDITIONS
MIN
TYP(3)
MAX
UNIT
GROUPS
[1, 2, 3]
[1, 2, 3]
Sine-wave clock
0.4
0.4
2
2
Differential clock input
level(4)
VIN_CLK
VP-P
Square-wave clock
Differential
0.1
1
Sampling clock input
capacitance(4)(5)
CIN_CLK
RIN_CLK
pF
Each input to ground
Sampling clock input
resistance
100
Ω
(1) The analog inputs are protected as shown below. Input voltage magnitudes beyond the Absolute Maximum Ratings may damage this
device.
V
A
TO INTERNAL
CIRCUITRY
I / O
GND
(2) To ensure accuracy, it is required that VA, VTC, VE and VDR be well bypassed. Each supply pin must be decoupled with separate bypass
capacitors.
(3) Typical figures are at TA = 25°C, and represent most likely parametric norms. Test limits are ensured to Texas Instrument's average
outgoing quality level (AOQL).
(4) This parameter is specified by design and/or characterization and is not tested in production.
(5) The analog and clock input capacitances are die capacitances only. Additional package capacitances of 0.22-pF differential and 1.06-pF
each pin to ground are isolated from the die capacitances by lead and bond wire inductances.
18
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6.10 Electrical Characteristics: AutoSync Feature
The following specifications apply after calibration for for VA = VDR = VTC = VE = 1.9 V; I and Q channels AC-coupled, FSR pin
= High; CL = 10 pF; differential AC-coupled sine wave input clock, fCLK = 1.6 GHz at 0.5 VP-P with 50% duty cycle; VBG
=
floating; non-extended control mode; Rext = Rtrim = 3300 Ω ±0.1%; analog signal source impedance = 100-Ω differential; 1:2
demultiplex non-DES mode; I and Q channels; duty-cycle stabilizer on(1)(2)
SUB-
GROUPS
PARAMETER
TEST CONDITIONS
MIN
TYP(3)
MAX
UNIT
Differential RCLK input
level
mVp-p
VIN_RCLK
CIN_RCLK
RIN_CLK
Differential peak-to-peak
360
Differential
0.1
1
RCLK input capacitance
pF
Each input to ground
RCLK differential input
resistance
Ω
100
IIH_RCLK
IIL_RCLK
Input leakage current
Input leakage current
VIN = VA
[1, 2, 3]
[1, 2, 3]
20
μA
μA
VIN = GND
–32
Differential RCOut output
voltage
VO_RCOUT
360
mVp-p
(1) The analog inputs are protected as shown below. Input voltage magnitudes beyond the Absolute Maximum Ratings may damage this
device.
V
A
TO INTERNAL
CIRCUITRY
I / O
GND
(2) To ensure accuracy, it is required that VA, VTC, VE and VDR be well bypassed. Each supply pin must be decoupled with separate bypass
capacitors.
(3) Typical figures are at TA = 25°C, and represent most likely parametric norms. Test limits are ensured to Texas Instrument's average
outgoing quality level (AOQL).
6.11 Converter Electrical Characteristics: Digital Control and Output Pin Characteristics
The following specifications apply after calibration for for VA = VDR = VTC = VE = 1.9 V; I and Q channels AC-coupled, FSR pin
= High; CL = 10 pF; differential AC-coupled sine wave input clock, fCLK = 1.6 GHz at 0.5 VP-P with 50% duty cycle; VBG
=
floating; non-extended control mode; Rext = Rtrim = 3300 Ω ±0.1%; analog signal source impedance = 100-Ω differential; 1:2
demultiplex non-DES mode; I and Q channels; duty-cycle stabilizer on.(1)(2)
SUB-
GROUPS
PARAMETER
CONDITIONS
MIN
TYP(3)
MAX UNIT
DIGITAL CONTROL PINS, (DES, LSPSM, CAL, PDI, PDQ, TPM, NDM, FSR, DDRPh, ECE, SCLK, SDI, SCS— unless otherwise
specified)
VIH
VIL
IIH
Logic high input voltage
Logic low input voltage
Input leakage current
[1, 2, 3]
[1, 2, 3]
[1, 2, 3]
0.7 x VA
V
V
0.3 x VA
1
VIN = VA
–1
µA
(1) The analog inputs are protected as shown below. Input voltage magnitudes beyond the Absolute Maximum Ratings may damage this
device.
V
A
TO INTERNAL
CIRCUITRY
I / O
GND
(2) To ensure accuracy, it is required that VA, VTC, VE and VDR be well bypassed. Each supply pin must be decoupled with separate bypass
capacitors.
(3) Typical figures are at TA = 25°C, and represent most likely parametric norms. Test limits are ensured to Texas Instrument's average
outgoing quality level (AOQL).
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Converter Electrical Characteristics: Digital Control and Output Pin Characteristics (continued)
The following specifications apply after calibration for for VA = VDR = VTC = VE = 1.9 V; I and Q channels AC-coupled, FSR pin
= High; CL = 10 pF; differential AC-coupled sine wave input clock, fCLK = 1.6 GHz at 0.5 VP-P with 50% duty cycle; VBG
=
floating; non-extended control mode; Rext = Rtrim = 3300 Ω ±0.1%; analog signal source impedance = 100-Ω differential; 1:2
demultiplex non-DES mode; I and Q channels; duty-cycle stabilizer on.(1)(2)
SUB-
GROUPS
PARAMETER
CONDITIONS
MIN
TYP(3)
MAX UNIT
Input leakage current (DES,
LSPSM, CAL, TPM, NDM,
FSR, DDRPh)
[1, 2, 3]
–1
1
µA
µA
IIL
Input leakage current
(SCLK, SDI, SCS)
VIN = GND
[1, 2, 3]
[1, 2, 3]
–30
–55
Input leakage current (PDI,
PDQ, ECE)
Input capacitance(4)
µA
pF
CIN_DIG
Each input to ground
1.5
DIGITAL OUTPUT PINS (Data, DCLKI, DCLKQ, ORI, ORQ) - see Device Nomenclature
VBG = floating, OVS = High
VBG = floating, OVS = Low
VBG = VA, OVS = high
VBG = VA, OVS = low
[1, 2, 3]
[1, 2, 3]
[1, 2, 3]
[1, 2, 3]
380
240
600
440
670
500
840 mVP-P
650 mVP-P
mVP-P
LVDS differential output
voltage
VOD
mVP-P
Change in LVDS output
swing between logic levels
ΔVO DIFF
-20
1
20
mV
VBG = floating
VBG = VA
0.8
1.2
V
V
VOS
Output offset voltage
Change in output offset
voltage between logic
levels
ΔVOS
±1
mV
VBG = floating; D+ and D−
connected to 0.8 V
IOS
ZO
Output short-circuit current
±3.8
100
mA
Differential output
impedance
Ω
DIFFERENTIAL DCLK RESET PINS (DCLK_RST)
DCLK_RST Common mode
VCMI_DRST
1.25
0.6
V
VP-P
Ω
Input Voltage
Differential DCLK_RST
VID_DRST
Input Voltage
Differential DCLK_RST
RIN_DRST
100
Input Resistance(5)
DIGITAL OUTPUT PINS (CalRun, SDO)
VOH
VOL
Logic high output level
Logic low output level
CalRun, SDO IOH = −400 µA
[1, 2, 3]
[1, 2, 3]
1.5
1.7
V
V
CalRun, SDO IOH = 400 µA
0.14
0.3
(4) The digital control pin capacitances are die capacitances only. Additional package capacitance of 1.6-pF each pin to ground are isolated
from the die capacitances by lead and bond wire inductances.
(5) This parameter is specified by design and/or characterization and is not tested in production.
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6.12 Converter Electrical Characteristics: Power Supply Characteristics
The following specifications apply after calibration for VA = VDR = VTC = VE = 1.9 V; I and Q channels AC-coupled, FSR pin =
high; CL = 10 pF; differential AC-coupled sine wave input clock, fCLK = 1.6 GHz at 0.5 VP-P with 50% duty cycle; VBG = floating;
non-extended control mode; Rext = Rtrim = 3300 Ω ±0.1%; analog signal source impedance = 100-Ω differential; 1:2
demultiplex non-DES mode; I and Q channels; duty-cycle stabilizer on.(1)(2)
SUB-
GROUPS
PARAMETER
CONDITIONS
MIN
TYP(3)
MAX
UNIT
fCLK = 1.6 GHz, 1:2 DEMUX MODE, NON-LSPSM
PDI = PDQ = Low
[1, 2, 3]
1160
637
635
2
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
µA
PDI = Low; PDQ = High
PDI = High; PDQ = Low
PDI = PDQ = High
IA
Analog supply current
PDI = PDQ = Low
[1, 2, 3]
[1, 2, 3]
[1, 2, 3]
471
284
284
1
PDI = Low; PDQ = High
PDI = High; PDQ = Low
PDI = PDQ = High
Track-and-hold and clock
supply current
ITC
IDR
IE
PDI = PDQ = Low
281
149
143
8
PDI = Low; PDQ = High
PDI = High; PDQ = Low
PDI = PDQ = High
Output driver supply
current
PDI = PDQ = Low
90
mA
mA
mA
µA
PDI = Low; PDQ = High
PDI = High; PDQ = Low
PDI = PDQ = High
54
Digital encoder supply
current
42
0.04
2020
1120
1110
2.7
3.8
2.1
2.1
5.2
PDI = PDQ = Low
[1, 2, 3]
[1, 2, 3]
[1, 2, 3]
2280
1300
1300
mA
mA
mA
mA
W
PDI = Low; PDQ = High
PDI = High; PDQ = Low
PDI = PDQ = High
IT
Total current
PDI = PDQ = Low
[1, 2, 3]
4.4
PDI = Low; PDQ = High
PDI = High; PDQ = Low
PDI = PDQ = High
W
PC
Power consumption
W
mW
(1) The analog inputs are protected as shown below. Input voltage magnitudes beyond the Absolute Maximum Ratings may damage this
device.
V
A
TO INTERNAL
CIRCUITRY
I / O
GND
(2) To ensure accuracy, it is required that VA, VTC, VE and VDR be well bypassed. Each supply pin must be decoupled with separate bypass
capacitors.
(3) Typical figures are at TA = 25°C, and represent most likely parametric norms. Test limits are ensured to Texas Instrument's average
outgoing quality level (AOQL).
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Converter Electrical Characteristics: Power Supply Characteristics (continued)
The following specifications apply after calibration for VA = VDR = VTC = VE = 1.9 V; I and Q channels AC-coupled, FSR pin =
high; CL = 10 pF; differential AC-coupled sine wave input clock, fCLK = 1.6 GHz at 0.5 VP-P with 50% duty cycle; VBG = floating;
non-extended control mode; Rext = Rtrim = 3300 Ω ±0.1%; analog signal source impedance = 100-Ω differential; 1:2
demultiplex non-DES mode; I and Q channels; duty-cycle stabilizer on.(1)(2)
SUB-
GROUPS
PARAMETER
CONDITIONS
MIN
TYP(3)
MAX
UNIT
fCLK = 800 MHz, 1:2 DEMUX MODE, LSPSM
PDI = PDQ = Low
[1, 2, 3]
754
423
423
2
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
µA
PDI = Low; PDQ = High
PDI = High; PDQ = Low
PDI = PDQ = High
IA
Analog supply current
PDI = PDQ = Low
[1, 2, 3]
[1, 2, 3]
[1, 2, 3]
344
212
212
1
PDI = Low; PDQ = High
PDI = High; PDQ = Low
PDI = PDQ = High
Track-and-hold and clock
supply current
ITC
IDR
IE
PDI = PDQ = Low
273
141
141
8
PDI = Low; PDQ = High
PDI = High; PDQ = Low
PDI = PDQ = High
Output driver supply
current
PDI = PDQ = Low
46
mA
mA
mA
µA
PDI = Low; PDQ = High
PDI = High; PDQ = Low
PDI = PDQ = High
24
Digital encoder supply
current
22
0.03
1417
801
799
2.7
2.7
1.5
1.5
5.2
PDI = PDQ = Low
[1, 2, 3]
[1, 2, 3]
[1, 2, 3]
1620
940
mA
mA
mA
mA
W
PDI = Low; PDQ = High
PDI = High; PDQ = Low
PDI = PDQ = High
IT
Total current
940
PDI = PDQ = Low
[1, 2, 3]
3.1
PDI = Low; PDQ = High
PDI = High; PDQ = Low
PDI = PDQ = High
W
PC
Power consumption
W
mW
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6.13 Converter Electrical Characteristics: AC Electrical Characteristics
The following specifications apply after calibration for VA = VDR = VTC = VE = 1.9 V; I and Q channels AC-coupled, FSR pin =
high; CL = 10 pF; differential AC-coupled sine wave input clock, fCLK = 1.6 GHz at 0.5 VP-P with 50% duty cycle; VBG = floating;
non-extended control mode; Rext = Rtrim = 3300 Ω ±0.1%; analog signal source impedance = 100-Ω differential; 1:2
demultiplex non-DES mode; I and Q channels; duty-cycle stabilizer on.(1)(2)
SUB-
GROUPS
PARAMETER
CONDITIONS
MIN
TYP(3)
MAX UNIT
INPUT CLOCK (CLK)
Non-LSPSM
LSPSM
[9, 10, 11]
[9, 10, 11]
1.6
GHz
MHz
Maximum input clock
frequency
fCLK (max)
800
Non-DES mode;
LFS = 1b
200
Non-LSPSM
LSPSM
[9, 10, 11]
[9, 10, 11]
MHz
Minimum input clock
frequency
fCLK (min)
DES mode
250
Non-DES mode
200
MHz
Input clock duty
cycle(4)
fCLK(min) ≤ fCLK ≤ fCLK (max)
20%
50%
80%
tCL
Input clock low time(4)
Input clock high time(4)
200
200
500
500
ps
ps
tCH
DCLK_RST
Setup time
DCLK_RST±
tSR
tHR
45
45
ps
ps
Hold time DCLK_RST±
Input
Clock
Cycles
Pulse width
DCLK_RST±
tPWR
5
DATA CLOCK (DCLKI, DCLKQ)
DCLK duty cycle
50%
4
90° mode
0° mode
Input
Clock
Cycles
DCLK synchronization
tSYNC_DLY
delay
5
Differential low-to-high
transition time
tLHT
10% to 90%, CL = 2.5-pF
10% to 90%, CL = 2.5-pF
DDR mode, 90° DCLK
DDR mode, 90° DCLK
200
ps
ps
ps
ps
ps
Differential high-to-low
transition time
tHLT
200
500
500
±50
Data-to-DCLK set-up
time
tSU
DCLK-to-data hold
time
tH
DCLK-to-data output
skew
tOSK
50% of DCLK transition to 50% of data transition
(1) The analog inputs are protected as shown below. Input voltage magnitudes beyond the Absolute Maximum Ratings may damage this
device.
V
A
TO INTERNAL
CIRCUITRY
I / O
GND
(2) The maximum clock frequency for non-demux mode is 1 GHz.
(3) Typical figures are at TA = 25°C, and represent most likely parametric norms. Test limits are ensured to Texas Instrument's average
outgoing quality level (AOQL).
(4) This parameter is specified by design and/or characterization and is not tested in production.
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Converter Electrical Characteristics: AC Electrical Characteristics (continued)
The following specifications apply after calibration for VA = VDR = VTC = VE = 1.9 V; I and Q channels AC-coupled, FSR pin =
high; CL = 10 pF; differential AC-coupled sine wave input clock, fCLK = 1.6 GHz at 0.5 VP-P with 50% duty cycle; VBG = floating;
non-extended control mode; Rext = Rtrim = 3300 Ω ±0.1%; analog signal source impedance = 100-Ω differential; 1:2
demultiplex non-DES mode; I and Q channels; duty-cycle stabilizer on.(1)(2)
SUB-
GROUPS
PARAMETER
CONDITIONS
MIN
TYP(3)
MAX UNIT
DATA INPUT-TO-OUTPUT
Sampling (aperture)
delay
tAD
Input CLK+ rise to acquisition of data
1.3
0.2
ns
ps
(rms)
tAJ
Aperture jitter
Input clock-to data
output delay (in
50% of input clock transition to 50% of data
transition
tOD
3.2
ns
addition to tLAT
)
Latency in
1:2 demux non-DES
mode(4)
DI, DQ outputs
[4, 5, 6]
[4, 5, 6]
34 Input
Clock
DId, DQd outputs
35
Cycles
DI outputs
DQ outputs
DId outputs
DQd outputs
DI outputs
[4, 5, 6]
[4, 5, 6]
[4, 5, 6]
[4, 5, 6]
[4, 5, 6]
34
Latency in
Input
34.5
1:4 demux DES
Clock
Cycles
mode(4)
35
tLAT
35.5
Latency in
34 Input
Clock
non-demux non-DES
mode(4)
Cycles
DQ outputs
DI outputs
DQ outputs
[4, 5, 6]
[4, 5, 6]
[4, 5, 6]
34
Latency in
34 Input
Clock
non-demux DES
mode(4)
Cycles
34.5
Input
Clock
Cycle
Over range recovery
time
Differential VIN step from ±1.2 V to 0 V to get
accurate conversion
tORR
1
PD low-to-rated
accuracy conversion
(wake-up time)
Non-DES mode
DES mode
500
1
ns
µs
tWU
6.14 Electrical Characteristics: Delta Parameters
over operating free-air temperature range (unless otherwise noted)(1)(2)(3)(4)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
mA
IA
Analog supply current
–6
–4
6
4
ITC
IDR
IE
Track and hold supply current
Output driver supply current
Digital encoder supply current
mA
–15
–30
15
30
mA
mA
(1) Delta parameters are measured on the automated test equipment (ATE) as part of the ATE program at both pre and post burn-in.
(2) The four delta parameter currents are measured at the beginning of the ATE program. The voltage supply is then pulsed to the absolute
max and the remainder of the ATE program is executed. After the ATE program is executed, the four delta parameter currents are
measured again. The differences in the measured supply currents at the beginning and end of the ATE program are the delta
parameters.
(3) Delta parameters are measured at TA = 25°C prior to burn-in and at TA= –55°C, 25°C, and 125°C after burn-in. The differences between
supply currents measured before and after burn-in are not included in the delta parameter analysis.
(4) For delta parameters outside of the distribution, the corresponding parts are rejected.
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6.15 Timing Requirements: Serial Port Interface
over operating free-air temperature range (unless otherwise noted)
The following specifications apply after calibration for VA = VDR = VTC = VE = 1.9 V; I and Q channels AC-coupled, FSR pin =
High; CL = 10 pF; differential AC-coupled sine wave input clock, fCLK = 1.6 GHz at 0.5 VP-P with 50% duty cycle; VBG = floating;
non-extended control mode; Rext = Rtrim = 3300 Ω ±0.1%; analog signal source impedance = 100-Ω differential; 1:2
demultiplex non-DES mode; I and Q channels; duty-cycle stabilizer on.(1)(2)
TEST
CONDITIONS
SUB-
GROUPS
PARAMETER
MIN
NOM(3)
MAX
UNIT
fSCLK
(max)
Maximum serial clock frequency See(4)
15
MHz
fSCLK (min) Minimum serial clock frequency See(4)
0
MHz
ns
Serial clock low time
[9, 10, 11]
[9, 10, 11]
30
30
Serial clock high time
ns
Serial data to serial clock rising
setup time
tSSU
tSH
See(4)
See(4)
2.5
1
ns
ns
ns
Serial data to serial clock rising
hold time
SCS to serial clock rising setup
time
tSCS
2.5
SCS to serial clock falling hold
time
tHCS
tBSU
1.5
10
ns
ns
Bus turnaround time
(1) The analog inputs are protected as shown below. Input voltage magnitudes beyond the Absolute Maximum Ratings may damage this
device.
V
A
TO INTERNAL
CIRCUITRY
I / O
GND
(2) The maximum clock frequency for non-demux mode is 1 GHz.
(3) Typical figures are at TA = 25°C, and represent most likely parametric norms. Test limits are ensured to Texas Instrument's average
outgoing quality level (AOQL).
(4) This parameter is specified by design and/or characterization and is not tested in production.
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6.16 Timing Requirements: Calibration
over operating free-air temperature range (unless otherwise noted)
The following specifications apply after calibration for VA = VDR = VTC = VE = 1.9 V; I and Q channels AC-coupled, FSR pin =
high; CL = 10 pF; differential AC-coupled sine wave input clock, fCLK = 1.6 GHz at 0.5 VP-P with 50% duty cycle; VBG = floating;
non-extended control mode; Rext = Rtrim = 3300 Ω ±0.1%; analog signal source impedance = 100-Ω differential; 1:2
demultiplex non-DES mode; I and Q channels; duty-cycle stabilizer on.(1)(2)
PARAMETER
TEST
SUB-
MIN
NOM(3)
MAX
UNIT
CONDITIONS
GROUPS
Non-ECM
tCAL
Calibration cycle time
ECM; CSS = 0b
ECM; CSS = 1b
4.1 × 107
Clock Cycles
See Figure 8, note
tCAL_L CAL pin low time
tCAL_H CAL pin high time
[9, 10, 11]
[9, 10, 11]
1280
1280
Clock Cycles
Clock Cycles
(4)
See Figure 8, note
(4)
(1) The analog inputs are protected as shown below. Input voltage magnitudes beyond the Absolute Maximum Ratings may damage this
device.
V
A
TO INTERNAL
CIRCUITRY
I / O
GND
(2) The maximum clock frequency for non-demux mode is 1 GHz.
(3) Typical figures are at TA = 25°C, and represent most likely parametric norms. Test limits are ensured to Texas Instrument's average
outgoing quality level (AOQL).
(4) This parameter is specified by design and/or characterization and is not tested in production.
6.17 Quality Conformance Inspection
MIL-STD-883, Method 5005 - Group A
SUBGROUP
DESCRIPTION
Static tests at
TEMPERATURE (°C)
1
2
+25
+125
-55
Static tests at
3
Static tests at
4
Dynamic tests at
Dynamic tests at
Dynamic tests at
Functional tests at
Functional tests at
Functional tests at
Switching tests at
Switching tests at
Switching tests at
Setting time at
+25
+125
-55
5
6
7
+25
+125
-55
8A
8B
9
+25
+125
-55
10
11
12
13
14
+25
+125
-55
Setting time at
Setting time at
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6.18 Timing Diagrams
Sample N
DI
Sample N-1
DId
V
I+/-
IN
Sample N+1
t
AD
CLK+
t
OD
Sample N-39 and
Sample N-38
DId, DI
Sample N-37 and Sample N-36
Sample N-35 and Sample N-34
t
OSK
DCLKI+/-
(0°Phase)
t
t
H
SU
DCLKI+/-
(90°Phase)
Figure 1. Clocking in Non-LSPSM, 1:2 Demux, Non-DES Mode*
Sample N
Sample N-1
DQ
DQ
V
Q+/-
IN
Sample N+1
t
AD
CLK+
DQ
t
OD
Sample N-34
OSK
Sample N-33
Sample N-37
Sample N-35
Sample N-36
t
DCLKQ+/-
(0°Phase)
Figure 2. Clocking in Non-LSPSM, Non-Demux, Non-DES Mode*
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Timing Diagrams (continued)
DQ
c
DI
c
DId
Sample N
Sample N-0.5
Sample N-1
DQd
c
c
V
Q+/-
IN
Sample
N-1.5
Sample N+1
t
AD
c
c
CLK+/-
t
OD
DQd, DId,
DQ, DI
Sample N-37.5, N-37,
N-36.5, N-36
Sample N-35.5, N-35,
N-34.5, N-34
Sample N-39.5, N-39,
N-38.5, N-38
t
OSK
DCLKQ+/-
(0°Phase)
t
t
H
SU
DCLKQ+/-
(90°Phase)
Figure 3. Clocking in Non-LSPSM, 1:4 Demux DES Mode*
Sample N - 0.5
Sample N
Sample N-1
DI
DQ
DI
V
Q+/-
IN
Sample N + 0.5
DQ
Sample N+1
t
AD
CLK+
t
OD
Sample N-34.5, N-34
Sample N-33.5, N-33
Sample N-37.5, N-37
Sample N-36.5, N-36
DQ, DI
Sample N-35.5, N-35
t
OSK
DCLKQ+/-
(0°Phase)
Figure 4. Clocking in Non-LSPSM, Non-Demux Mode DES Mode*
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Timing Diagrams (continued)
Sample N
DI
Sample N-1
DId
V I+/-
IN
Sample N+1
t
AD
CLK+
t
OD
Sample N-22.5 and
Sample N-21.5
DId, DI
Sample N-20.5 and Sample N-19.5
Sample N-18.5 and Sample N-17.5
t
OSK
DCLKI+/-
(SDR Rising)
Figure 5. Clocking in LSPSM, 1:2 Demux Mode, Non-DES Mode*
Sample N
Sample N-1
DQ
DQ
V
Q+/-
IN
Sample N+1
t
AD
CLK+
DQ
t
OD
Sample N-17
OSK
Sample N-16
Sample N-20
Sample N-18
Sample N-19
t
DCLKQ+/-
(DDR 0°Phase)
t
H
t
SU
DCLKQ+/-
(DDR 90°Phase)
t
OSK
DCLKI+/-
(SDR Rising)
Figure 6. Clocking in LSPSM, Non-Demux Mode, Non-DES Mode*
* The timing for Figure 1 through Figure 6 is shown for the one input only (I or Q). However, both I and Q inputs
may be used. For this case, the I channel functions precisely the same as the Q channel, with VinI, DCLKI, DId,
and DI instead of VinQ, DCLKQ, DQd, and DQ. Both I and Q channel use the same CLK.
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Timing Diagrams (continued)
Synchronizing Edge
t
SYNC_DLY
CLK
t
HR
t
SR
DCLK_RST-
DCLK_RST+
t
OD
t
PWR
DCLKI+
DCLKQ+
Figure 7. Data Clock Reset Timing (Demux Mode)
t
CAL
CalRun
t
CAL_H
CAL
t
CAL_L
POWER
SUPPLY
Figure 8. On-Command Calibration Timing
Single Register Access
SCS
t
t
SCS
t
HCS
1
24
HCS
8
9
SCLK
SDI
Command Field
Data Field
Data Field
LSB
MSB
MSB
t
SH
t
SSU
t
BSU
SDO
ad mode)
High Z
High Z
LSB
Figure 9. Serial Interface Timing
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Timing Diagrams (continued)
IDEAL
POSITIVE
FULL-SCALE
TRANSITION
Output
Code
ACTUAL
POSITIVE
FULL-SCALE
TRANSITION
1111 1111 1111 (4095)
1111 1111 1110 (4094)
1111 1111 1101 (4093)
POSITIVE
FULL-SCALE
ERROR
MID-SCALE
TRANSITION
1000 0000 0000 (2048)
0111 1111 1111 (2047)
OFFSET
ERROR
IDEAL NEGATIVE
FULL-SCALE TRANSITION
ACTUAL NEGATIVE
FULL-SCALE TRANSITION
NEGATIVE
FULL-SCALE
ERROR
0000 0000 0010 (2)
0000 0000 0001 (1)
0000 0000 0000 (0)
(V +) < (V -)
IN IN
(V +) > (V -)
IN
IN
0.0V
Differential Analog Input Voltage (+V /2) - (-V /2)
-V /2
+V /2
IN
IN
IN
IN
Figure 10. Input / Output Transfer Characteristic
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6.19 Typical Characteristics
VA = VDR = VTC = VE = 1.9 V, fCLK = 1600 MHz in non-LSPSM and 800 MHz in LSPSM, fIN = 248 MHz, TA= 25°C, 1:2 demux
non-DES mode, and calibration performed after temperature, supply voltage or sample rate change, unless otherwise stated.
4
4
2
2
0
+INL
-INL
0
œ2
œ4
-2
-4
-65
0
4095
-15
35
85
135
Output Code
Temperature (oC)
C001
Figure 12. Minimum and Maximum INL vs Temperature
Figure 11. INL vs Code
4
0.8
0.4
2
0
0.0
œ0.4
œ0.8
-2
+DNL
-DNL
-4
-65
4095
0
-15
35
85
135
Temperature (oC)
Output Code
C004
Figure 14. Minimum and Maximum DNL vs Temperature
Figure 13. DNL vs Code
10
9
10
9
8
8
Non-LSPSM 1600 MSPS
DES 3200 MSPS
LSPSM 800 MSPS
Non-LSPSM 1600 MSPS
DES 3200 MSPS
LSPSM 800 MSPS
7
7
6
0
6
1.8
400 800 1200 1600 2000 2400 2800 3200 3600
Sample Rate (MSPS)
1.9
2
VA (V)
Figure 15. ENOB vs Sample Rate
Figure 16. ENOB vs Supply Voltage
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Typical Characteristics (continued)
VA = VDR = VTC = VE = 1.9 V, fCLK = 1600 MHz in non-LSPSM and 800 MHz in LSPSM, fIN = 248 MHz, TA= 25°C, 1:2 demux
non-DES mode, and calibration performed after temperature, supply voltage or sample rate change, unless otherwise stated.
10
10
9
9
8
8
Non-LSPSM 1600 MSPS
DES 3200 MSPS
LSPSM 800 MSPS
7
Non-LSPSM 1600 MSPS
DES 3200 MSPS
LSPSM 800 MSPS
7
6
6
-55
-25
5
35
65
95
125
0
400
800 1200 1600 2000 2400 2800 3200
Input Frequency (MHz)
Temperature (oC)
Figure 17. ENOB vs Temperature
Figure 18. ENOB vs Input Frequency
70
65
60
55
50
45
40
35
70
65
60
55
50
45
40
35
Non-LSPSM 1600 MSPS
DES 3200 MSPS
LSPSM 800 MSPS
Non-LSPSM 1600 MSPS
DES 3200 MSPS
LSPSM 800 MSPS
0
400 800 1200 1600 2000 2400 2800 3200 3600
Sample Rate (MSPS)
1.8
1.9
VA (V)
2
Figure 19. SNR vs Sample Rate
Figure 20. SNR vs Supply Voltage
70
65
60
55
50
45
40
35
70
65
60
55
50
45
40
35
Non-LSPSM 1600 MSPS
DES 3200 MSPS
LSPSM 800 MSPS
Non-LSPSM 1600 MSPS
DES 3200 MSPS
LSPSM 800 MSPS
-55
-25
5
35
65
95
125
0
400
800 1200 1600 2000 2400 2800 3200
Input Frequency (MHz)
Temperature (oC)
Figure 21. SNR vs Temperature
Figure 22. SNR vs Input Frequency
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Typical Characteristics (continued)
VA = VDR = VTC = VE = 1.9 V, fCLK = 1600 MHz in non-LSPSM and 800 MHz in LSPSM, fIN = 248 MHz, TA= 25°C, 1:2 demux
non-DES mode, and calibration performed after temperature, supply voltage or sample rate change, unless otherwise stated.
-40
-50
-60
-70
-80
-40
-50
-60
-70
-80
Non-LSPSM 1600 MSPS
DES 3200 MSPS
LSPSM 800 MSPS
Non-LSPSM 1600 MSPS
DES 3200 MSPS
LSPSM 800 MSPS
0
400 800 1200 1600 2000 2400 2800 3200 3600
Sample Rate (MSPS)
1.8
1.9
VA (V)
2
Figure 23. THD vs Sample Rate
Figure 24. THD vs Supply Voltage
-40
-50
-60
-70
-80
-40
Non-LSPSM 1600 MSPS
DES 3200 MSPS
LSPSM 800 MSPS
Non-LSPSM 1600 MSPS
DES 3200 MSPS
LSPSM 800 MSPS
-50
-60
-70
-80
-55
-25
5
35
65
95
125
0
400
800 1200 1600 2000 2400 2800 3200
Input Frequency (MHz)
Temperature (oC)
Figure 25. THD vs Temperature
Figure 26. THD vs Input Frequency
80
70
60
50
40
80
70
60
50
40
Non-LSPSM 1600 MSPS
DES 3200 MSPS
LSPSM 800 MSPS
Non-LSPSM 1600 MSPS
DES 3200 MSPS
LSPSM 800 MSPS
0
400 800 1200 1600 2000 2400 2800 3200 3600
Sample Rate (MSPS)
1.8
1.9
VA (V)
2
Figure 27. SFDR vs Sample Rate
Figure 28. SFDR vs Supply Voltage
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Typical Characteristics (continued)
VA = VDR = VTC = VE = 1.9 V, fCLK = 1600 MHz in non-LSPSM and 800 MHz in LSPSM, fIN = 248 MHz, TA= 25°C, 1:2 demux
non-DES mode, and calibration performed after temperature, supply voltage or sample rate change, unless otherwise stated.
80
70
60
50
40
80
70
60
50
40
Non-LSPSM 1600 MSPS
DES 3200 MSPS
LSPSM 800 MSPS
Non-LSPSM 1600 MSPS
DES 3200 MSPS
LSPSM 800 MSPS
-55
-25
5
35
65
95
125
0
400
800 1200 1600 2000 2400 2800 3200
Input Frequency (MHz)
Temperature (oC)
Figure 29. SFDR vs Temperature
Figure 30. SFDR vs Input Frequency
10
9
70
65
60
55
50
45
40
35
8
Calibrated at 87.5oC
No recalibration at
other temps
Calibrated at 87.5oC
No recalibration at
other temps
7
6
-55
-25
5
35
65
95
125
-55
-25
5
35
65
95
125
Temperature (oC)
Temperature (oC)
fCLK = 1.6 GHz
fIN = 248 MHz
fCLK = 1.6 GHz
fIN = 248 MHz
Figure 31. ENOB vs Temperature Calibration at 87.5°C Only
Figure 32. SNR vs Temperature Calibration at 87.5°C Only
80
-40
70
-50
-60
60
Calibrated at 87.5oC
No recalibration at
-70
50
Calibrated at 87.5oC
No recalibration at
other temps
other temps
-80
-55
40
-55
-25
5
35
65
95
125
-25
5
35
65
95
125
Temperature (oC)
Temperature (oC)
fCLK = 1.6 GHz
fIN = 248 MHz
fCLK = 1.6 GHz
fIN = 248 MHz
Figure 33. THD vs Temperature Calibration at 87.5°C Only
Figure 34. SFDR vs Temperature Calibration at 87.5°C Only
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Typical Characteristics (continued)
VA = VDR = VTC = VE = 1.9 V, fCLK = 1600 MHz in non-LSPSM and 800 MHz in LSPSM, fIN = 248 MHz, TA= 25°C, 1:2 demux
non-DES mode, and calibration performed after temperature, supply voltage or sample rate change, unless otherwise stated.
-50
-60
-70
-80
-90
-50
-60
-70
-80
-90
-7 dBFS
-13 dBFS
-16 dBFS
Non-LSPSM 1600 MSPS
DES 3200 MSPS
0
1000
2000
3000
0
1000
2000
3000
Input Frequency (MHz)
Input Frequency (MHz)
Figure 35. 3rd Order Intermodulation Distortion vs Input
Frequency
Figure 36. 3rd Order Intermodulation Distortion vs Input
Frequency (DES Mode 3200 MSPS)
-30
-40
-50
-60
-70
0
-3
-6
-9
-12
Non-LSPSM 1600 MSPS
DES 3200 MSPS
DESIQ 3200 MSPS
-80
-90
I Channel
Q Channel
-15
-18
0
400
800 1200 1600 2000 2400 2800 3200
Input Frequency (MHz)
0
400 800 1200 1600 2000 2400 2800 3200 3600 4000
Input Frequnecy (MHz)
Figure 37. Cross Talk vs Input Frequency
Figure 38. Insertion Loss vs Input Frequency
4
3.5
3
2.5
LSPSM
Non-LSPSM
2
0
400
800
Sample Rate (MSPS)
1200
1600
C024
Figure 39. Power Consumption vs Sample Rate
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7 Detailed Description
7.1 Overview
The ADC12D1620 device is a versatile analog-to-digital converter (ADC) with an innovative architecture, which
permits very high-speed operation. The controls available ease the application of the device to circuit solutions.
Optimum performance requires adherence to the provisions discussed here and in the Application Information.
This section covers an overview, a description of control modes (extended control mode and non-extended
control mode), and features.
The ADC12D1620 device uses a calibrated folding and interpolating architecture that achieves a high effective
number of bits (ENOB). The use of folding amplifiers greatly reduces the number of comparators and power
consumption. Interpolation reduces the number of front-end amplifiers required, minimizing the load on the input
signal and further reducing power requirements. In addition to correcting other non-idealities, on-chip calibration
reduces the INL bow often seen with folding architectures. The result is an extremely fast, high-performance,
low-power converter.
7.1.1 Operation Summary
A differential analog input is digitized into 12 bits. Differential input signals below the negative full-scale range
cause the output word to be all zeroes. Differential inputs above the positive full-scale range results in the output
word being all ones. If either case happens, the out-of-range output for the respective channel has a logic-high
signal.
There are 4 major sampling modes:
1. Dual-channel ADC with a sampling range of 200 to 1600 MSPS.
2. Single channel, interleaved ADC in dual-edge sampling with a sampling range of 500 to 3200 MSPS.
3. Dual-channel ADC in LSPSM with a sampling range of 200 to 800 MSPS.
4. Single channel, interleaved ADC in LSPSM and dual-edge sampling with a sampling range of 500 to 1600
MSPS.
The device has many operating options. Some of these options can be controlled through pin configurations in
non-extended control mode (non-ECM or sometimes known as pin-control mode). An expanded feature set is
available in extended control mode (ECM) through the serial interface.
Each channel has a selectable output demultiplexer that feeds two LVDS buses. Depending upon the sampling
mode and the demux option chosen, the output data rate can be the same, one half, or one quarter the sample
rate.
7.2 Functional Block Diagram
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7.3 Feature Description
The ADC12D1620 offers many features to make the device convenient to use in a wide variety of applications.
Table 1 is a summary of the features available, as well as details for the control mode chosen. N/A means Not
Applicable.
Table 1. Features and Modes
CONTROL PIN
FEATURE
NON-ECM
ACTIVE IN
ECM
ECM
DEFAULT ECM STATE
INPUT CONTROL AND ADJUST
AC- and DC-coupled mode
selection
Selected through VCMO
(Pin C2)
Yes
No
Not available
N/A
Selected through the
Configuration Register
(Addr: 3h and Bh)
Selected through FSR
(Pin Y3)
Input full-scale range adjust
Input offset adjust setting
Mid FSR value
Selected through the
Configuration Register
(Addr: 2h and Ah)
Not available
N/A
Offset = 0 mV
Selected through
LSPSM
Low-sampling power-saving
mode
Yes
No
Not available
N/A
Non-DES mode
N/A
(Pin V4)
Selected through DES
(Pin V5)
Selected through the DES bit
DES / Non-DES mode selection
DES mode input selection
DESCLKIQ mode
(Addr: 0h; Bit: 7)
Selected through the DEQ, DIQ
bits
Not available
Not available
Not available
N/A
N/A
N/A
(Addr: 0h; Bits: 6:5)
Selected through the DCK bit
N/A
(Addr: Eh; Bit: 6)
Selected through the DES
Timing Adjust Reg
(Addr: 7h)
DES timing adjust
Mid skew offset
Selected through the
Configuration Register
(Addr: Ch and Dh)
Sampling clock phase adjust
Not available
N/A
tAD adjust disabled
OUTPUT CONTROL AND ADJUST
Selected through
DDRPh (Pin W4)
Selected through the DPS bit
DDR clock phase selection
No
N/A
N/A
N/A
Yes
N/A
No
0° mode
DDR mode
N/A
(Addr: 0h; Bit: 14)
Selected through the SDR bit
DDR / SDR DCLK selection
Not available
Not available
(Addr: 0h; Bit: 2)
SDR rising / falling DCLK
Selection
Selected through the DPS bit
(Addr: 0h; Bit: 14)
LVDS differential voltage
amplitude selection
Selected through the OVS bit
Higher amplitude only
Higher amplitude
N/A
(Addr: 0h; Bit: 13)
LVDS common-mode voltage
amplitude selection
Selected through VBG
(Pin B1)
Not available
Selected through the 2SC bit
Output formatting selection
Test pattern mode at output
Offset binary only
Offset binary
TPM disabled
N/A
(Addr: 0h; Bit: 4)
Selected through TPM
(Pin A4)
Selected through the TPM bit
(Addr: 0h; Bit: 12)
Demux/Non-demux mode
selection
Selected through NDM
(Pin A5)
Yes
Not available
Selected through the
Configuration Register
(Addr: Eh)
Master mode,
RCOut1, RCOut2 disabled
AutoSync
Not available
N/A
Selected through the
Configuration Register
(Addr: Eh; Bit: 0)
DCLK reset
Time stamp
Not available
Not available
N/A
N/A
DCLK reset disabled
Time stamp disabled
Selected through the TSE bit
(Addr: 0h; Bit: 3)
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Feature Description (continued)
Table 1. Features and Modes (continued)
CONTROL PIN
ACTIVE IN
ECM
FEATURE
CALIBRATION
NON-ECM
ECM
DEFAULT ECM STATE
Selected through CAL
(Pin D6)
Selected through the CAL bit
N/A
(CAL = 0)
On-command calibration
Yes
N/A
N/A
(Addr: 0h; Bit: 15)
Selected through the
Configuration Register
(Addr: 4h)
Calibration Adjust
Not available
Not available
tCAL
Selected through the SSC bit
R/W calibration values
disabled
Read/Write calibration settings
POWER-DOWN
(Addr: 4h; Bit: 7)
Selected through PDI
(Pin U3)
Selected through the PDI bit
Power down I channel
Yes
Yes
I-channel operational
Q-channel operational
(Addr: 0h; Bit: 11)
Selected through PDQ
(Pin V3)
Selected through the PDQ bit
Power down Q channel
(Addr: 0h; Bit: 10)
7.3.1 Input Control and Adjust
There are several features and configurations for the input of the ADC12D1620 device that enable it to be used
in many different applications. AC- and DC-coupled modes, input full-scale range adjust, input offset adjust,
LSPSM, DES/non-DES modes, and sampling clock phase adjust are discussed in the following sections.
7.3.1.1 AC- and DC-Coupled Modes
The analog inputs may be AC- or DC-coupled. See AC- or DC-Coupled Mode Pin (VCMO) for information on how
to select the desired mode. For applications information, see DC-Coupled Input Signals and AC-Coupled Input
Signals.
7.3.1.2 Input Full-Scale Range Adjust
The input full-scale range for the ADC12D1620 may be adjusted through non-ECM or ECM. In non-ECM, a
control pin selects a higher or lower value; see Full-Scale Input-Range Pin (FSR). In ECM, the full-scale input
range of the I- and Q-channel inputs may be independently set with 15 bits precision through the I- and Q-
channel Full-Scale Range Adjust Registers (Addr: 3h and Addr: Bh, respectively). See VIN_FSR in Converter
Electrical Characteristics: Analog Input/Output and Reference Characteristics for electrical specification details.
Note that the higher and lower full-scale input range settings in non-ECM correspond to the middle and minimum
full-scale input range settings in ECM. An on-command calibration must be executed following a change of the
input full-scale range. See Table 16 and Table 24 for information about the registers.
7.3.1.3 Input Offset Adjust
The input offset adjust for the ADC12D1620 may be adjusted in ECM with 12 bits precision plus sign through the
I- and Q-channel Offset Adjust Registers (Addr: 2h and Addr: Ah, respectively). See Table 15 and Table 23 for
information about the registers.
7.3.1.4 Low-Sampling Power-Saving Mode (LSPSM)
For applications with input clock speeds 200 to 800 MHz, the ADC12D1620 device can be switched to the
LSPSM for a reduction in power consumption of approximately 20%. See Low-Sampling Power-Saving Mode Pin
(LSPSM) for information on how to select the desired mode and details on operation in this mode.
7.3.1.5 DES Timing Adjust
The performance of the ADC12D1620 in DES mode depends on how well the two channels are interleaved (that
is, that the clock samples either channel with precisely a 50% duty-cycle); each channel has the same offset
(nominally code 2047/2048), and each channel has the same full-scale range. The ADC12D1620 device includes
an automatic clock phase background adjustment in DES mode to automatically and continuously adjust the
clock phase of the I and Q channels. In addition to this, the residual fixed timing skew offset may be further
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manually adjusted, and further reduce timing spurs for specific applications. See DES Timing Adjust (Addr: 7h).
As the DES timing adjust is programmed from 0d to 127d, the magnitude of the Fs/2-Fin timing interleaving spur
decreases to a local minimum and then increases again. The default, nominal setting of 64d may or may not
coincide with this local minimum. The user may manually skew the global timing to achieve the lowest possible
timing interleaving spur.
7.3.1.6 Sampling Clock Phase Adjust
The sampling clock (CLK) phase may be delayed internally to the ADC up to 825 ps in ECM. This feature helps
the system designer remove small imbalances in clock distribution traces at the board level when multiple ADCs
are used, or to simplify complex system functions such as beam steering for phase-array antennas.
Additional delay in the clock path also creates additional jitter when using the sampling clock phase adjust.
Because the sampling clock phase adjust delays all clocks, including the DCLKs and output data, the user is
strongly advised to use the minimal amount of adjustment and verify the net benefit of this feature in their system
before relying on it.
7.3.2 Output Control and Adjust
There are several features and configurations for the ADC12D1620 output that make the device ideal for many
different applications. This section covers DDR clock phase, LVDS output differential and common-mode voltage,
output formatting, test pattern mode, and time stamp.
7.3.2.1 SDR / DDR Clock
The ADC12D1620 output data can be delivered in double data rate (DDR) or single data rate (SDR). For DDR,
the DCLK frequency is half the data rate, and data is sent to the outputs on both edges of DCLK; see Figure 40.
The DCLK-to-data phase relationship may be either 0° or 90°. For 0° mode, the data transitions on each edge of
the DCLK. Any offset from this timing is tOSK; (see Converter Electrical Characteristics: AC Electrical
Characteristics for details). For 90° mode, the DCLK transitions in the middle of each data cell. Setup and hold
times for this transition, tSU and tH, may also be found in Converter Electrical Characteristics: AC Electrical
Characteristics. The DCLK-to-data phase relationship may be selected through the DDRPh pin in non-ECM (see
Dual Data-Rate Phase Pin (DDRPh)) or the DPS bit in the Configuration Register (Addr: 0h; Bit: 14) in ECM.
Note that for DDR mode, the 1:2 demux mode is not available in LSPSM.
Data
DCLK
0°Mode
DCLK
90°Mode
Figure 40. DDR DCLK-to-Data Phase Relationship
For SDR, the DCLK frequency is the same as the data rate, and data is sent to the outputs on a single edge of
DCLK; see Figure 41. The data may transition on either the rising or falling edge of DCLK. Any offset from this
timing is tOSK; see Converter Electrical Characteristics: AC Electrical Characteristics for details. The DCLK
rising or falling edge may be selected through the SDR bit in the Configuration Register (Addr: 0h; Bit: 2) in ECM
only.
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Data
DCLK
SDR Rising
DCLK
SDR Falling
Figure 41. SDR DCLK-to-Data Phase Relationship
7.3.2.2 LVDS Output Differential Voltage
The ADC12D1620 device is available with a selectable higher or lower LVDS output differential voltage. This
parameter is VOD, found in Converter Electrical Characteristics: Digital Control and Output Pin Characteristics.
The desired voltage may be selected through the OVS bit in the Configuration Register (Addr: 0h, Bit: 13). For
many applications, such as when the LVDS outputs are very close to an FPGA on the same board, the lower
setting is sufficient for good performance; this also reduces the possibility for EMI from the LVDS outputs to other
signals on the board. See Configuration Register 1 for more information.
7.3.2.3 LVDS Output Common-Mode Voltage
The ADC12D1620 is available with a selectable higher or lower LVDS output common-mode voltage. This
parameter is VOS, found in Converter Electrical Characteristics: Digital Control and Output Pin Characteristics.
See LVDS Output Common-Mode Pin (VBG) for information on how to select the desired voltage.
7.3.2.4 Output Formatting
The formatting at the digital data outputs may be either offset binary or two's complement. The default formatting
is offset binary, but two's complement may be selected through the 2SC bit of the Configuration Register (Addr:
0h; Bit: 4); see Configuration Register 1 for more information.
7.3.2.5 Test-Pattern Mode
The ADC12D1620 can provide a test pattern at the four output buses, independent of the input signal, that aids
in system debug. In test-pattern mode, the ADC is disengaged, and a test pattern generator is connected to the
outputs, including ORI and ORQ. The test pattern output is the same in DES mode or non-DES mode. Each port
is given a unique 12-bit word, alternating between 1's and 0's. When the device is programmed into the demux
mode, the order of the test pattern is described in Table 2. If the I or Q channel is powered down, the test pattern
is not output for that channel.
Table 2. Test Pattern by Output Port in Non-LSPSM Demux Mode
TIME
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
Qd
Id
Q
I
ORQ
0b
1b
0b
1b
0b
0b
1b
0b
1b
0b
ORI
0b
1b
0b
1b
0b
0b
1b
0b
1b
0b
COMMENTS
000h
FFFh
000h
FFFh
000h
000h
FFFh
000h
FFFh
000h
004h
FFBh
004h
FFBh
004h
004h
FFBh
004h
FFBh
004h
008h
FF7h
008h
FF7h
008h
008h
FF7h
008h
FF7h
008h
010h
FEFh
010h
FEFh
010h
010h
FEFh
010h
FEFh
010h
Pattern Sequence
n
Pattern Sequence
n+1
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Table 2. Test Pattern by Output Port in Non-LSPSM Demux Mode (continued)
TIME
T10
T11
T12
T13
Qd
000h
FFFh
000h
...
Id
Q
I
ORQ
0b
ORI
0b
1b
0b
...
COMMENTS
004h
FFBh
004h
...
008h
FF7h
008h
...
010h
FEFh
010h
...
1b
Pattern Sequence
n+2
0b
...
When the device is programmed into the non-demux mode, the test pattern’s order is described in Table 3.
Table 3. Test Pattern by Output Port in Non-LSPSM Non-Demux Mode
TIME
T0
Q
I
ORQ
0b
0b
1b
1b
0b
1b
0b
1b
1b
1b
0b
0b
1b
1b
...
ORI
0b
0b
1b
1b
0b
1b
0b
1b
1b
1b
0b
0b
1b
1b
...
COMMENTS
000h
000h
FFFh
FFFh
000h
FFFh
000h
FFFh
FFFh
FFFh
000h
000h
FFFh
FFFh
...
004h
004h
FFBh
FFBh
004h
FFBh
004h
FFBh
FFBh
FFBh
004h
004h
FFBh
FFBh
...
T1
T2
T3
T4
Pattern Sequence
n
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
Pattern Sequence
n+1
Table 4. Test Pattern by Output Port in LSPSM Demux Mode
TIME
Qd
Id
Q
I
ORQ
1b
1b
1b
1b
0b
1b
1b
1b
1b
0b
1b
1b
1b
...
ORI
1b
1b
1b
1b
0b
1b
1b
1b
1b
0b
1b
1b
1b
...
COMMENTS
T0
T1
FF7h
FF7h
008h
008h
008h
FF7h
FF7h
008h
008h
008h
FF7h
FF7h
008h
...
FEFh
FEFh
010h
010h
010h
FEFh
FEFh
010h
010h
010h
FEFh
FEFh
010h
...
008h
008h
FF7h
FF7h
008h
008h
008h
FF7h
FF7h
008h
008h
008h
FF7h
...
010h
010h
FEFh
FEFh
010h
010h
010h
FEFh
FEFh
010h
010h
010h
FEFh
...
Pattern sequence
T2
n
T3
T4
T5
T6
Pattern sequence
T7
n+1
T8
T9
T10
T11
T12
T13
Pattern sequence
n+2
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Table 5. Test Pattern by Output Port in LSPSM Non-Demux Mode
TIME
Q
I
ORQ
0b
1b
0b
1b
0b
0b
1b
0b
1b
0b
0b
1b
0b
1b
...
ORI
0b
1b
0b
1b
0b
0b
1b
0b
1b
0b
0b
1b
0b
1b
...
COMMENTS
T0
T1
008h
FF7h
008h
FF7h
008h
008h
FF7h
008h
FF7h
008h
008h
FF7h
008h
FF7h
...
010h
FEFh
010h
FEFh
010h
010h
FEFh
010h
FEFh
010h
010h
FEFh
010h
FEFh
...
Pattern sequence
T2
n
T3
T4
T5
T6
Pattern sequence
T7
n+1
T8
T9
T10
T11
T12
T13
T14
Pattern sequence
n+2
7.3.2.6 Time Stamp
The time-stamp feature enables the user to capture the timing of an external trigger event, relative to the
sampled signal. When enabled through the TSE bit of the Configuration Register (Addr: 0h; Bit: 3), the LSB of
the digital outputs (DQd, DQ, DId, DI) captures the trigger information. In effect, the 12-bit converter becomes an
11-bit converter, and the LSB acts as a 1-bit converter with the same latency as the 11-bit converter. Apply the
trigger to the DCLK_RST input. It may be asynchronous to the ADC sampling clock.
7.3.3 Calibration Feature
The ADC12D1620 calibration must be run to achieve specified performance. The calibration procedure is exactly
the same regardless of how it was initiated or when it is run. Calibration trims the analog input differential
termination resistors, the CLK input resistor, and sets internal bias currents that affect the linearity of the
converter. This minimizes full-scale error, offset error, DNL and INL, which results in the maximum dynamic
performance, as measured by the SNR, THD, SINAD (SNDR), and ENOB pins.
7.3.3.1 Calibration Control Pins and Bits
Table 6 is a summary of the pins and bits used for calibration. See Pin Configuration and Functions for complete
pin information and Figure 8 for the timing diagram.
Table 6. Calibration Pins
PIN (Bit)
NAME
FUNCTION
D6
CAL
(Calibration)
Initiate calibration; see Calibration Pin (CAL)
Adjust calibration sequence
(Addr: 0h; Bit: 15)
(Addr: 4h)
Calibration Adjust
CalRun
(Calibration Running)
B5
Indicates while calibration is running
Rtrim+, Rtrim–
(Input termination trim resistor)
C1/D2
C3/D3
External resistor used to calibrate analog and CLK inputs
External resistor used to calibrate internal linearity
Rext+, Rext–
(External Reference resistor)
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7.3.3.2 How to Execute a Calibration
Calibration may be initiated by holding the CAL pin low for at least tCAL_L clock cycles, then holding it high for at
least tCAL_H clock cycles, as defined in Timing Requirements: Calibration. The minimum tCAL_L and tCAL_H input
clock cycle sequences are required to ensure that random noise does not cause a calibration to begin when it is
not desired. The time taken by the calibration procedure is specified as tCAL. The CAL pin is active in both ECM
and non-ECM. However, in ECM, the CAL pin is logically OR'd with the CAL bit, so both the pin and bit must be
set low before executing another calibration with either pin or bit.
TI recommends holding the CAL pin high during normal usage of the ADC12D1620 device to reduce the chance
that an SEU causes a calibration cycle.
7.3.3.3 On-Command Calibration
In addition to executing a calibration after power-on and device stabilization, in order to obtain optimal parametric
performance TI recommends execution of an on-command calibration whenever the settings or conditions to the
device are significantly altered. Some examples include: changing the FSR through either ECM or Non-ECM,
power-cycling either channel, and switching into or out of DES mode. For best performance, it is also
recommended that an on-command calibration be run 20 seconds or more after application of power and
whenever the operating temperature changes significantly relative to the specific system performance
requirements. See Figure 31 for the impact temperature change can have on the performance of the device
without re-calibration.
Due to the nature of the calibration feature, TI recommends avoiding unnecessary activities on the device while
the calibration is taking place. For example, do not read or write to the serial interface or use the DCLK reset
feature while calibrating the ADC; doing so impairs the performance of the device until it is re-calibrated correctly.
Also, TI recommends not to apply a strong narrow-band signal to the analog inputs during calibration because
this may impair the accuracy of the calibration; broad spectrum noise is acceptable.
7.3.3.4 Calibration Adjust
The sequence of the calibration event itself may be adjusted. This feature can be used if a shorter calibration
time than the default is required; see tCAL in Converter Electrical Characteristics: AC Electrical Characteristics.
However, the performance of the device may be compromised when using this feature.
The calibration sequence may be adjusted through the CSS bit of the Calibration Adjust register (Addr: 4h; Bit:
14). The default setting of CSS = 1b executes both RIN and RIN_CLK calibration (using Rtrim) and internal linearity
calibration (using Rext). Executing a calibration with CSS = 0b executes only the internal linearity calibration. The
first time that calibration is executed, it must be with CSS = 1b to trim RIN and RIN_CLK. However, once the device
is at its operating temperature, and RIN has been trimmed at least one time, it does not drift significantly.
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7.3.3.4.1 Read/Write Calibration Settings
When the ADC performs a calibration, the calibration constants are stored in an array which is accessible
through the Calibration Values register (Addr: 5h). To save the time it takes to execute a calibration, tCAL, or to
allow re-use of a previous calibration result, these values can be read from and written to the register at a later
time. For example, if an application requires the same input impedance, RIN, this feature can be used to load a
previously determined set of values. For the calibration values to be valid, the ADC must be operating under the
same conditions, including temperature, at which the calibration values were originally determined by the ADC.
To read calibration values from the SPI, do the following:
1. Set ADC to desired operating conditions.
2. Set the SSC bit (Addr: 4h; Bit: 7) to 1.
3. Read exactly 240 times the Calibration Values register (Addr: 5h). The register values are R0, R1, R2...
R239 where R0 is a dummy value. The contents of R<239:1> should be stored.
4. Set the SSC bit (Addr: 4h; Bit: 7) to 0.
5. Continue with normal operation.
To write calibration values to the SPI, do the following:
1. Set ADC to operating conditions at which Calibration Values were previously read.
2. Set the SSC bit (Addr: 4h; Bit: 7) to 1.
3. Write exactly 239 times the Calibration Values register (Addr: 5h). The registers should be written with stored
register values R1, R2... R239.
4. Make two additional dummy writes of 0000h.
5. Set the SSC bit (Addr: 4h; Bit: 7) to 0.
6. Continue with normal operation.
7.3.3.5 Calibration and Power-Down
If PDI and PDQ are simultaneously asserted during a calibration cycle, the ADC12D1620 device immediately
powers down. The calibration cycle continues when either or both channels are powered back up, but the
calibration is compromised due to the incomplete settling of bias currents directly after power up. Therefore, a
new calibration must be executed upon powering the ADC12D1620 back up. In general, the ADC12D1620 must
be re-calibrated when either or both channels are powered back up, or after one channel is powered down. For
best results, this must be done after the device has stabilized to its operating temperature.
7.3.3.6 Calibration and the Digital Outputs
During calibration, the digital outputs (including DI, DId, DQ, DQd and OR) are set logic-low, to reduce noise.
The DCLK runs continuously during calibration. After the calibration is completed and the CalRun signal is logic-
low, it takes an additional 60 sampling clock cycles before the output of the ADC12D1620 is valid converted data
from the analog inputs. This is the time it takes for the pipeline to flush, as well as for other internal processes.
7.3.4 Power Down
On the ADC12D1620, the I and Q channels may be powered down individually. This may be accomplished
through the control pins, PDI and PDQ, or through ECM. In ECM, the PDI and PDQ pins are logically OR'd with
the PDI and PDQ bits of the Control Register (Addr: 0h; Bits: 11:10). See Power-Down I-Channel Pin (PDI) and
Power-Down Q-Channel Pin (PDQ) for more information.
7.3.5 Low-Sampling Power-Saving Mode (LSPSM)
For applications with input clock speeds of 200 to 800 MHz (sample rates of 200 to 800 MSPS in non-DES
mode), the ADC may be put in LSPSM using the LSPSM (V4) pin (see Low-Sampling Power-Saving Mode Pin
(LSPSM)). LSPSM powers down certain areas of the device, reduces the power consumption by approximately
20%, and may improve the spectral purity of the output. In 1:2 demux mode, the output is in SDR, and the DLCK
frequency will be Fs/2 . In non-demux mode, the output is switchable between DDR and SDR; see Table 8 for
the DCLK frequencies for each mode and output combination.
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7.4 Device Functional Modes
7.4.1 DES/Non-DES Mode
The ADC12D1620 device can operate in dual-edge sampling (DES) or non-DES mode. In non-DES mode, inputs
are sampled at the sampling clock frequency. Depending on whether channels are powered down, one or two
inputs may be sampled. The DES mode enables a single analog input to be sampled by both I and Q channels.
One channel samples the input on the rising edge of the sampling clock and the other samples the input signal
on the falling edge of the sampling clock. A single input is thus sampled twice per clock cycle, resulting in an
overall sample rate of twice the sampling clock frequency. Because DES mode uses both I and Q channels to
process the input signal, both channels must be powered up for the DES mode to function properly.
See Dual-Edge Sampling Pin (DES) for information on how to select the DES mode. In non-ECM only the I input
may be used for the DES mode input. In ECM, either the I or Q input may be selected by first using the DES bit
(Addr: 0h; Bit: 7) to select the DES mode. Setting the DEQ bit (Addr: 0h; Bit: 6) selects the Q input, while leaving
the default value of DEQ=0 selects the I input.
Two other DES modes are available. These provide improved input bandwidth compared to DESI and DESQ
modes, but require driving the I and Q inputs with identical in-phase signals.
The DESIQ mode is selected by setting the DIQ bit (Addr: 0h; Bit: 5). In this mode the I and Q input signals are
connected to the I and Q converter channels and also connected to each other internally to enable better I to Q
signal matching compared with the DESCLKIQ mode discussed next.
DESCLKIQ mode is similar to the DESIQ mode, except that the I and Q channels remain electrically separate
internal to the ADC12D1620. For this reason, the I to Q signal matching is slightly worse, and spurious
performance is degraded compared to DESIQ mode. DESCLKIQ input bandwidth is slightly better than the
DESIQ bandwidth. The DCK bit (Addr: Eh; Bit: 6) is used to select the 180° sampling-clock mode.
Table 7 summarizes the relative bandwidth and SFDR performance of the DES sampling modes:
Table 7. DES Mode Comparison
DES MODE
DESI, DESQ
DESIQ
INPUTS DRIVEN
I or Q
INPUT BANDWIDTH
SFDR PERFORMANCE
Lowest
Mid
Highest
Mid
I and Q
DESCLKIQ
I and Q
Highest
Lowest
In the DES mode, the output data must be carefully interleaved in order to reconstruct the sampled signal. If the
device is programmed into the 1:4 demux DES mode, the data is effectively demultiplexed by 1:4. If the sampling
clock is 1600 MHz, the effective sampling rate is doubled to 3.2 GSPS, and each of the 4 output buses has an
output rate of 800 MSPS. All data is available in parallel. To properly reconstruct the sampled waveform, the four
words of parallel data that are output with each DCLK must be correctly interleaved. The sampling order is as
follows, from the earliest to the latest: DQd, DId, DQ, DI (see Figure 3). If the device is programmed into the
nondemux DES mode, two words of parallel data are output with each edge of the DCLK in the following
sampling order, from the earliest to the latest: DQ, DI (see Figure 4).
7.4.2 Demux/Non-Demux Mode
The ADC12D1620 device may be in one of two demultiplex modes: demux mode or non-demux mode (also
sometimes referred to as 1:1 demux mode). In non-demux mode, the data from the input is simply output at the
sampling rate on one 12-bit bus. In demux mode, the data from the input is output at half the sampling rate, on
twice the number of buses. Demux/non-demux mode may only be selected by the NDM pin. In non-DES mode,
the output data from each channel may be demultiplexed by a factor of 1:2 (1:2 demux Non-DES mode) or not
demultiplexed (non-demux non-DES mode). In DES mode, the output data from both channels interleaved may
be demultiplexed (1:4 demux DES mode) or not demultiplexed (non-demux DES mode).
See Table 8 for a selection of available modes.
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Table 8. Supported Demux, Data Rate Modes
OUTPUT
MODE
DCLK
RCOUT
NON-LSPSM, NON-DES MODE
DDR
SDR
DDR
SDR
0° mode / 90° mode
Rising / Falling mode
0° mode only
FCLK/4
FCLK/2
FCLK/2
N/A
FCLK/4
1:2 demux
1:1 demux
LSPSM, NON-DES MODE
1:2 demux
Not available
N/A
DDR
SDR
DDR
SDR
Not available
Rising / Falling mode
0° mode only
N/A
N/A
FCLK/2
FCLK/2
FCLK
FCLK/2
1:1 demux
NON-LSPSM, DES MODE
1:4 demux
Rising mode only
DDR
SDR
DDR
SDR
0° mode / 90° mode
Rising / Falling mode
0° mode only
FCLK/4
FCLK/2
FCLK/2
N/A
FCLK/4
1:1 demux
LSPSM, DES MODE
1:4 demux
Not Available
N/A
DDR
SDR
DDR
SDR
Not Available
Rising mode only
0° mode / 90° mode
Rising mode only
N/A
N/A
FCLK/2
FCLK/2
FCLK
FCLK/2
1:1 demux
7.5 Programming
7.5.1 Control Modes
The ADC12D1620 may be operated in one of two control modes: non-extended-control mode (non-ECM) or
extended-control mode (ECM). In the simpler non-ECM (also sometimes referred to as pin-control mode), the
user affects available configuration and control of the device through the control pins. The ECM provides
additional configuration and control options through a serial interface and a set of 16 registers, most of which are
available to the user.
7.5.1.1 Non-ECM
In non-ECM, the serial interface is not active, and all available functions are controlled through various pin
settings. Non-ECM is selected by setting the ECE pin to logic-high. Note that for the control pins, logic-high and
logic-low refer to VA and GND, respectively. Nine dedicated control pins provide a wide range of control for the
ADC12D1620 and facilitate its operation. These control pins provide DES mode selection, demux-mode
selection, DDR-phase selection, execute calibration, power down I channel, power down Q channel, test-pattern-
mode selection, and full-scale input-range selection. In addition to this, two dual-purpose control pins provide for
AC- or DC-coupled mode selection and LVDS output common-mode voltage selection. See Table 9 for a
summary.
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Programming (continued)
Table 9. Non-ECM Pin Summary
PIN NAME
LOGIC LOW
LOGIC HIGH
FLOATING
DEDICATED CONTROL PINS
DES
Non-DES mode
Demux mode
0° mode
DES mode
Non-demux mode
90° mode
Not valid
Not valid
NDM
DDR
DDRPh
SDR
Not valid
Rising edge
Falling edge
CAL
See Calibration Pin (CAL)
Not valid
Not valid
LPSSM
Non-LSPSM
I-channel active
LSPSM
PDI
Power down I-channel
Power down Q-channel
Test pattern mode
Power down I-channel
Power down Q-channel
Not valid
PDQ
Q-channel active
TPM
Non-test pattern mode
Lower FS input range
FSR
DUAL-PURPOSE CONTROL PINS
VCMO
Higher FS input range
Not valid
AC-coupled operation
Not allowed
Not allowed
DC-coupled operation
Higher LVDS common-mode
voltage
Lower LVDS common-mode
voltage
VBG
7.5.1.1.1 Dual-Edge Sampling Pin (DES)
The dual-edge sampling (DES) pin selects whether the ADC12D1620 is in DES mode (logic-high) or non-DES
mode (logic-low). DES mode means that a single analog input is sampled by both I and Q channels in a time-
interleaved manner. One of the ADCs samples the input signal on the rising sampling clock edge (duty cycle
corrected); the other ADC samples the input signal on the falling sampling clock edge (duty cycle corrected). In
non-ECM, only the I input may be used for DES mode, also known as DESI mode. In ECM, the Q input may be
selected through the DEQ bit of the Configuration Register (Addr: 0h; Bit: 6), also known as DESQ mode. In
ECM, both the I and Q inputs may be selected, also known as DESIQ or DESCLKIQ mode.
To use this feature in ECM, use the DES bit in the Configuration Register (Addr: 0h; Bit: 7). See DES/Non-DES
Mode for more information.
7.5.1.1.2 Non-Demultiplexed Mode Pin (NDM)
The non-demultiplexed mode (NDM) pin selects whether the ADC12D1620 is in demux mode (logic-low) or non-
demux mode (logic-high). In non-demux mode, the data from the input is produced at the sampled rate at a
single 12-bit output bus. In demux mode, the data from the input is produced at half the sampled rate and at
twice the number of output buses. For non-DES mode, each I or Q channel produces its data on one or two
buses for non-demux or demux mode, respectively. For DES mode, the selected channel produces its data on
two or four buses for non-demux or demux mode, respectively.
This feature is pin-controlled only and remains active during both non-ECM and ECM. See Demux/Non-Demux
Mode for more information.
7.5.1.1.3 Dual Data-Rate Phase Pin (DDRPh)
The dual data-rate phase (DDRPh) pin selects whether the ADC12D1620 is in 0° mode (logic-low) or 90° mode
(logic-high) for DDR mode. For DDR mode, the data may transition either with the DCLK transition (0° mode) or
halfway between DCLK transitions (90° mode). If the device is in SDR mode, the DDRPh pin selects whether the
data transitions on the rising edge of DCLK (logic-low) or the falling edge of DCLK (logic-high). The DDRPh pin
selects the mode for both the I channel: DI- and DId-to-DCLKI phase relationship and for the Q channel: DQ- and
DQd-to-DCLKQ phase relationship.
To use this feature in ECM, use the DPS bit in the Configuration Register (Addr: 0h; Bit: 14). See SDR / DDR
Clock for more information.
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7.5.1.1.4 Calibration Pin (CAL)
The calibration (CAL) pin may be used to execute an on-command calibration. The effect of calibration is to
maximize the dynamic performance. To initiate an on-command calibration through the CAL pin, bring the CAL
pin high for a minimum of tCAL_H input clock cycles after it has been low for a minimum of tCAL_L input clock cycles
(seeConverter Electrical Characteristics: AC Electrical Characteristics clock cycle specification). TI recommends
holding the CAL pin high during normal usage of the ADC12D1620 device to reduce the chance that an SEU
causes a calibration cycle. In ECM, this pin remains active and is logically OR'd with the CAL bit.
To use this feature in ECM, use the CAL bit in the Configuration Register (Addr: 0h; Bit: 15). See Calibration
Feature for more information.
7.5.1.1.5 Low-Sampling Power-Saving Mode Pin (LSPSM)
The LSPSM pin selects whether the device is in non-LSPSM (logic-low) or LSPSM (logic-high). In LSPSM, the
input clock is limited to 800 MHz, and the sample rate in non-DES mode is limited to 800 MSPS.
The LSPSM pin remains active in ECM. See Low-Sampling Power-Saving Mode (LSPSM) for more details.
7.5.1.1.6 Power-Down I-Channel Pin (PDI)
The power-down I-channel (PDI) pin selects whether the I channel is powered down (logic-high) or active (logic-
low). The digital data output pins, DI and DId, (both positive and negative) are put into a high impedance state
when the I channel is powered down. Upon return to the active state, the pipeline contains meaningless
information and must be flushed. The supply currents (typicals and limits) are available for the I channel powered
down or active and may be found in Converter Electrical Characteristics: Power Supply Characteristics .
Recalibrate the device following a power-cycle of PDI (or PDQ).
The PDI pin remains active in ECM, and either the PDI pin or the PDI bit of the Configuration Register (Addr: 0h;
Bit: 11) may be used to power-down the I channel. See Power Down for more information.
7.5.1.1.7 Power-Down Q-Channel Pin (PDQ)
The power-down Q-channel (PDQ) pin selects whether the Q channel is powered down (logic-high) or active
(logic-low). This pin functions similarly to the PDI pin, except that it applies to the Q channel; review the
information in Power-Down I-Channel Pin (PDI) and apply to the PDQ pin as well. The PDI and PDQ pins
function independently of each other to control whether each I or Q channel is powered down or active.
The PDQ pin remains active in ECM, and either the PDQ pin or the PDQ bit of the Configuration Register (Addr:
0h; Bit: 10) may be used to power-down the Q channel. See Power Down for more information.
7.5.1.1.8 Test-Pattern Mode Pin (TPM)
The test-pattern-mode (TPM) pin selects whether the output of the ADC12D1620 is a test pattern (logic-high) or
the converted analog input (logic-low). The ADC12D1620 can provide a test pattern at the four output buses,
independentl of the input signal, to aid in system debug. In TPM, the ADC is disengaged, and a test pattern
generator is connected to the outputs, including ORI and ORQ. See Test-Pattern Mode for more information.
7.5.1.1.9 Full-Scale Input-Range Pin (FSR)
The full-scale input-range (FSR) pin selects whether the full-scale input range for both the I channel and Q
channel is higher (logic-high) or lower (logic-low). The input full-scale range is specified as VIN_FSR in Converter
Electrical Characteristics: Digital Control and Output Pin Characteristics. In non-ECM, the full-scale input range
for each I and Q channel may not be set independently, but it is possible to do so in ECM. The device must be
calibrated following a change in FSR to obtain optimal performance.
To use this feature in ECM, use the I- and Q-channel Full Scale Range Adjust registers (Addr: 3h and Bh,
respectively). See Input Control and Adjust for more information.
7.5.1.1.10 AC- or DC-Coupled Mode Pin (VCMO
)
The VCMO pin serves a dual purpose. When functioning as an output, it provides the optimal common-mode
voltage for the DC-coupled analog inputs. When functioning as an input, it selects whether the device is AC-
coupled (logic-low) or DC-coupled (floating). The VCMO pin is always active, in both ECM and non-ECM.
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7.5.1.1.11 LVDS Output Common-Mode Pin (VBG
)
The VBG pin serves a dual purpose. When functioning as an output, it provides a buffered copy of the bandgap
reference voltage. When functioning as an input, it selects whether the LVDS output common-mode voltage is
higher (logic-high) or lower (floating). The LVDS output common-mode voltage is specified as VOS and may be
found in Converter Electrical Characteristics: Digital Control and Output Pin Characteristics. The VBG pin is
always active, in both ECM and non-ECM.
7.5.1.2 Extended Control Mode
In extended control mode (ECM), most functions are controlled through the serial interface. In addition to this,
several of the control pins remain active. See Table 1 for details. ECM is selected by setting the ECE pin to logic-
low. Each time the ADC is powered up the configuration register values are in an unknown state. Therefore all
registers must be user configured to the default and/or desired values before device use. If the ECE pin is set to
logic-high (non-ECM), then the registers are reset to their default values. Therefore, a simple way to reset the
registers is by toggling the ECE pin. Four pins on the ADC12D1620 device control the serial interface: SCS,
SCLK, SDI, and SDO. This section covers the serial interface. (See also Register Definitions.)
7.5.1.2.1 Serial Interface
The ADC12D1620 offers a serial interface that allows access to the sixteen control registers within the device.
The serial interface is a generic 4-wire (optionally 3-wire) synchronous interface that is compatible with SPI type
interfaces that are used on many micro-controllers and DSP controllers. Each serial interface access cycle is
exactly 24 bits long. A register-read or register-write can be accomplished in one cycle. The signals are defined
in such a way that the user can opt to simply join SDI and SDO signals in their system to accomplish a single,
bidirectional SDI/O signal. A summary of the pins for this interface may be found in Table 10. See Figure 9 for
the timing diagram and Timing Requirements: Serial Port Interface for timing specification details. Control register
contents are retained when the device is put into power-down mode. If this feature is unused, the SCLK, SDI,
and, SCS pins may be left floating because they each have an internal pullup.
Table 10. Serial Interface Pins
PIN
C4
C5
B4
A3
NAME
SCS (serial chip select bar)
SCLK (serial clock)
SDI (serial data in)
SDO (serial data out)
SCS: Each assertion (logic-low) of this signal starts a new register access, that is, the SDI command field must
be ready on the following SCLK rising edge. The user is required to de-assert this signal after the 24th clock. If
the SCS is de-asserted before the 24th clock, no data read/write occurs. For a read operation, if the SCS is
asserted longer than 24 clocks, the SDO output holds the D0 bit until SCS is de-asserted. For a write operation,
if the SCS is asserted longer than 24 clocks, data write occurs normally through the SDI input upon the 24th
clock. Setup and hold times, tSCS and tHCS, with respect to the SCLK must be observed. SCS must be toggled in
between register access cycles.
SCLK: This signal is used to register the input data (SDI) on the rising edge and to source the output data (SDO)
on the falling edge. The user may disable the clock and hold it at logic-low. There is no minimum frequency
requirement for SCLK; see fSCLK in Timing Requirements: Serial Port Interface for more details.
SDI: Each register access requires a specific 24-bit pattern at this input, consisting of a command field and a
data field. If the SDI and SDO wires are shared (3-wire mode), during read operations it is necessary to tri-state
the master must be tristate while the data field is output by the ADC on SDO. The master must be tri-state before
the falling edge of the 8th clock. If SDI and SDO are not shared (4-wire mode), then this is not necessary. Setup
and hold times, tSH and tSSU, with respect to the SCLK must be observed.
SDO: This output is normally tri-state and is driven only when SCS is asserted, the first 8 bits of command data
have been received and it is a READ operation. The data is shifted out, MSB first, starting with the falling edge of
the 8th clock. At the end of the access, when SCS is de-asserted, this output is tri-state once again. If an invalid
address is accessed, the data sourced will consist of all zeroes. If it is a read operation, there is a bus turnaround
time, tBSU, from when the last bit of the command field was read in until the first bit of the data field is written out.
Table 11 shows the serial interface bit definitions.
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Table 11. Command and Data Field Definitions
BIT NO.
NAME
COMMENTS
1b indicates a read operation.
0b indicates a write operation.
Bits must be set to 10b.
1
Read/Write (R/W)
2-3
4-7
8
Reserved
A<3:0>
X
16 registers may be addressed. The order is MSB first.
This is a "don't care" bit.
9-24
D<15:0>
Data written to or read from addressed register.
The serial data protocol is shown for a read and write operation in Figure 42 and Figure 43, respectively.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
SCSb
SCLK
*Only required to be tri-stated in 3-wire mode.
1
0
A3
A2
A1
A0
X
SDI
R/W
SDO
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Figure 42. Serial Data Protocol - Read Operation
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
SCSb
SCLK
R/W
1
0
A3
A2
A1
A0
X
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
SDI
SDO
Figure 43. Serial Data Protocol - Write Operation
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7.6 Register Maps
7.6.1 Register Definitions
Eleven read/write registers provide several control and configuration options in the extended control mode. When
the device is in non-extended control mode (non-ECM), the registers have the settings shown in the "DV" rows
and cannot be changed. See Table 12 for a summary.
Table 12. Register Addresses
A3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
A2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
A1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
A0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
HEX
0h
1h
2h
3h
4h
5h
6h
7h
8h
9h
Ah
Bh
Ch
Dh
Eh
Fh
REGISTER ADDRESSED
Configuration Register 1
Reserved
I-channel Offset Adjust
I-channel Full-Scale Range Adjust
Calibration Adjust
Calibration Values
Reserved
DES Timing Adjust
Reserved
Reserved
Q-channel Offset Adjust
Q-channel Full-Scale Range Adjust
Aperture Delay Coarse Adjust
Aperture Delay Fine Adjust
AutoSync
Reserved
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Table 13. Configuration Register 1
Addr: 0h (0000b)
Default Values: 2000h
Bit
Name CAL
DV(1)
15
14
DPS
0
13
OVS
1
12
TPM
0
11
PDI
0
10
PDQ
0
9
Res
0
8
7
DES
0
6
DEQ
0
5
DIQ
0
4
2SC
0
3
TSE
0
2
SDR
0
1
0
LFS
0/1
Reserved
0
0
0
(1) DV means Default Value. Refer to Extended Control Mode for more information on setting ECM default values.
Bit 15
CAL: Calibration enable. When this bit is set to 1b, an on-command calibration is initiated. This bit is not reset automatically
upon completion of the calibration. Therefore, the user must reset this bit to 0b and then set it to 1b again to execute
calibration. This bit is logically OR'd with the CAL Pin; both bit and pin must be set to 0b before either is used to execute a
calibration. TI recommends holding the CAL pin high during normal usage of the ADC12D1620 device to reduce the chance
that an SEU causes a calibration cycle.
Bit 14
Bit 13
Bit 12
DPS: DCLK phase select. In DDR, set this bit to 0b to select the 0° mode DDR data-to-DCLK phase relationship and to 1b to
select the 90° mode. In SDR, set this bit to 0b to transition the data on the rising edge of DCLK; set this bit to 1b to transition
the data on the falling edge of DCLK.
OVS: Output voltage select. This bit sets the differential voltage level for the LVDS outputs including Data, OR, and DCLK. 0b
selects the lower level and 1b selects the higher level. See VOD in Converter Electrical Characteristics: Digital Control and
Output Pin Characteristics for details.
TPM: Test pattern mode. When this bit is set to 1b, the device continually outputs a fixed digital pattern at the digital data and
OR outputs. When set to 0b, the device continually outputs the converted signal, which was present at the analog inputs. See
Test-Pattern Mode for details about the TPM pattern.
Bit 11
Bit 10
PDI: Power-down I channel. When this bit is set to 0b, the I channel is fully operational; when it is set to 1b, the I channel is
powered-down. The I channel may be powered-down through this bit or the PDI pin, which is active, even in ECM.
PDQ: Power-down Q channel. When this bit is set to 0b, the Q channel is fully operational; when it is set to 1b, the Q channel
is powered-down. The Q channel may be powered-down through this bit or the PDQ pin, which is active, even in ECM.
Bit 9
Bit 8
Reserved. Must be set as shown.
LFS: Low-frequency select. If the sampling clock (CLK) is at or below 300 MHz in non-LSPSM, set this bit to 1b for improved
performance. In LSPSM, the device is automatically in LFS, and this bit is inactive.
Bit 7
Bit 6
Bit 5
DES: Dual-edge sampling mode select. When this bit is set to 0b, the device operates in the non-DES mode; when it is set to
1b, the device operates in the DES mode. See DES/Non-DES Mode for more information.
DEQ: DES Q input select, also known as DESQ mode. When the device is in DES mode, this bit selects the input that the
device operates on. The default setting of 0b selects the I input and 1b selects the Q input.
DIQ: DES I and Q input, also known as DESIQ mode. When in DES mode, setting this bit to 1b shorts the I and Q inputs
internally to the device. In this mode, both the I and Q inputs must be externally driven; see DES/Non-DES Mode for more
information. If the bit is left at its default 0b, the I and Q inputs remain electrically separate.
The allowed DES modes settings are shown below. For DESCLKIQ mode, see the Table 27 register (Addr Eh).
MODE
ADDR 0h, BIT<7:5>
ADDR Eh, BIT<6>
Non-DES mode
DESI mode
000b
100b
110b
101b
000b
0b
0b
0b
0b
1b
DESQ mode
DESIQ mode
DESCLKIQ mode
Bit 4
Bit 3
Bit 2
2SC: Two's complement output. For the default setting of 0b, the data is output in offset binary format; when set to 1b, the
data is output in two's complement format.
TSE: Time stamp enable. For the default setting of 0b, the time stamp feature is not enabled; when set to 1b, the feature is
enabled. See Output Control and Adjust for more information about this feature.
SDR: Single data rate. For the default setting of 0b, the data is clocked in dual data rate; when set to 1b, the data is clocked in
single data rate. See Output Control and Adjust for more information about this feature. Note that for DDR mode, the 1:2
demux mode is not available in LSPSM. See Table 8 for a selection of available modes.
Bits 1:0
Reserved. Must be set as shown.
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Table 14. Reserved
Addr: 1h (0001b)
Default Values: 2907h
Bit
15
14
0
13
1
12
0
11
1
10
0
9
8
7
6
0
5
0
4
0
3
0
2
1
0
Name
DV(1)
Reserved
0
0
1
0
1
1
1
(1) DV means Default Value. Refer to Extended Control Mode for more information on setting ECM default values.
Bits 15:0 Reserved. Must be set as shown.
Table 15. I-Channel Offset Adjust
Addr: 2h (0010b)
Default Values: 0000h
Bit
15
14
Reserved
0
13
0
12
OS
0
11
0
10
9
8
7
6
5
4
0
3
0
2
1
0
Name
DV(1)
OM(11:0)
0
0
0
0
0
0
0
0
0
0
(1) DV means Default Value. Refer to Extended Control Mode for more information on setting ECM default values.
Bits 15:13 Reserved. Must be set to 0b.
Bit 12
OS: Offset sign. The default setting of 0b incurs a positive offset of a magnitude set by Bits 11:0 to the ADC output. Setting this
bit to 1b incurs a negative offset of the set magnitude.
Bits 11:0
OM(11:0): Offset magnitude. These bits determine the magnitude of the offset set at the ADC output (straight binary coding).
The range is from 0 mV for OM(11:0) = 0d to 45 mV for OM(11:0) = 4095d in steps of ~11 µV. Monotonicity is specified by
design only for the 9 MSBs.
CODE
OFFSET [mV]
0000 0000 0000 (default)
1000 0000 0000
1111 1111 1111
0
22.5
45
Table 16. I-Channel Full Scale Range Adjust
Addr: 3h (0011b)
Bit 15
Name Res
DV(1)
Default Values: 4000h
14
1
13
0
12
0
11
10
9
8
7
FM(14:0)
0
6
5
4
0
3
0
2
1
0
0
0
0
0
0
0
0
0
0
0
(1) DV means Default Value. Refer to Extended Control Mode for more information on setting ECM default values.
Bit 15
Reserved. Must be set to 0b.
Bits 14:0
FM(14:0): FSR magnitude. These bits increase the ADC full-scale range magnitude (straight binary coding.) The range is from
600 mV (0d) to 1000 mV (32767d) with the default setting at 800 mV (16384d). Monotonicity is specified by design only for the
9 MSBs. The mid-range (low) setting in ECM corresponds to the nominal (low) setting in non-ECM. A greater range of FSR
values is available in ECM, that is, FSR values above 800 mV. See VIN_FSR in Converter Electrical Characteristics: Analog
Input/Output and Reference Characteristics for characterization details.
CODE
FSR [mV]
600
000 0000 0000 0000
100 0000 0000 0000 (default)
111 1111 1111 1111
800
1000
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Table 17. Calibration Adjust
Addr: 4h (0100b)
Default Values: DB4Bh
Bit
Name Res
DV(1)
15
14
CSS
1
13
0
12
1
11
10
9
8
7
SSC
0
6
5
0
4
0
3
Reserved
1
2
1
0
Reserved
1
1
0
1
1
1
0
1
1
(1) DV means Default Value. Refer to Extended Control Mode for more information on setting ECM default values.
Bit 15
Bit 14
Reserved. Must be set as shown.
CSS: Calibration sequence select. The default 1b selects the following calibration sequence: reset all previously calibrated
elements to nominal values, do RIN calibration, do internal linearity calibration. Setting CSS = 0b selects the following
calibration sequence: do not reset RIN to its nominal value, skip RIN calibration, do internal linearity calibration. The calibration
must be completed at least one time with CSS = 1b to calibrate RIN. Subsequent calibrations may be run with CSS = 0b (skip
RIN calibration) or 1b (full RIN and internal linearity calibration).
Bits 13:8
Bit 7
Reserved. Must be set as shown.
SSC: SPI scan control. Setting this control bit to 1b allows the calibration values, stored in Addr: 5h, to be read/written. When
not reading/writing the calibration values, this control bit should left at its default 0b setting. See Calibration Feature for more
information.
Bits 6:0
Reserved. Must be set as shown.
Table 18. Calibration Values
Addr: 5h (0101b)
Default Values: XXXXh
Bit
15
14
X
13
X
12
X
11
X
10
9
8
7
6
5
4
3
2
1
0
Name
DV(1)
SS(15:0)
X
X
X
X
X
X
X
X
X
X
X
X
(1) DV means Default Value. Refer to Extended Control Mode for more information on setting ECM default values.
Bits 15:0
SS(15:0): SPI scan. When the ADC performs a self-calibration, the values for the calibration are stored in this register and may
be read from/written to it. Set the SSC of the Calibration Adjust register (Addr: 4h, Bit: 7) to read/write. See Calibration Feature
for more information.
Table 19. Reserved
Addr: 6h (0110b)
Default Values: 1C2Eh
Bit
15
14
0
13
0
12
1
11
1
10
1
9
8
7
6
0
5
1
4
0
3
1
2
1
0
Name
DV(1)
Reserved
0
0
0
0
1
1
0
(1) DV means Default Value. Refer to Extended Control Mode for more information on setting ECM default values.
Bits 15:0 Reserved. Must be set as shown.
Table 20. DES Timing Adjust
Addr: 7h (0111b)
Default Values: 8142h
Bit
15
14
0
13
0
12
DTA(6:0)
0
11
0
10
9
8
7
6
5
0
4
Reserved
0
3
0
2
1
0
Name
DV(1)
1
0
0
1
0
1
0
1
0
(1) DV means Default Value. Refer to Extended Control Mode for more information on setting ECM default values.
Bits 15:9
Bits 8:0
DTA(6:0): DES mode timing adjust. In the DES mode, the time at which the falling edge sampling clock samples relative to the
rising edge of the sampling clock may be adjusted; the automatic duty cycle correction continues to function. See Input Control
and Adjust for more information. The nominal step size is 30 fs.
Reserved. Must be set as shown.
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Table 21. Reserved
Addr: 8h (1000b)
Default Values: 0F0Fh
Bit
15
14
0
13
0
12
0
11
1
10
1
9
8
7
6
0
5
0
4
0
3
1
2
1
0
Name
DV(1)
Reserved
0
1
1
0
1
1
1
(1) DV means Default Value. Refer to Extended Control Mode for more information on setting ECM default values.
Bits 15:0 Reserved. Must be set as shown.
Table 22. Reserved
Addr: 9h (1001b)
Default Values: 0000h
Bit
15
14
0
13
0
12
0
11
0
10
0
9
8
7
6
0
5
0
4
0
3
0
2
1
0
Name
DV(1)
Reserved
0
0
0
0
0
0
0
(1) DV means Default Value. Refer to Extended Control Mode for more information on setting ECM default values.
Bits 15:0 Reserved. Must be set as shown.
Table 23. Q-Channel Offset Adjust
Addr: Ah (1010b)
Default Values: 0000h
Bit
15
14
Reserved
0
13
0
12
OS
0
11
0
10
9
8
7
6
5
4
0
3
0
2
1
0
Name
DV(1)
OM(11:0)
0
0
0
0
0
0
0
0
0
0
(1) DV means Default Value. Refer to Extended Control Mode for more information on setting ECM default values.
Bits 15:13 Reserved. Must be set to 0b.
Bit 12
OS: Offset sign. The default setting of 0b incurs a positive offset of a magnitude set by Bits 11:0 to the ADC output. Setting this
bit to 1b incurs a negative offset of the set magnitude.
Bits 11:0
OM(11:0): Offset magnitude. These bits determine the magnitude of the offset set at the ADC output (straight binary coding).
The range is from 0 mV for OM(11:0) = 0d to 45 mV for OM(11:0) = 4095d in steps of ~11 µV. Monotonicity is specified by
design only for the 9 MSBs.
CODE
OFFSET [mV]
0000 0000 0000 (default)
1000 0000 0000
1111 1111 1111
0
22.5
45
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Table 24. Q-Channel Full-Scale Range Adjust
Addr: Bh (1011b)
Default Values: 4000h
Bit
Name Res
DV(1)
15
14
1
13
0
12
0
11
10
9
8
7
FM(14:0)
0
6
5
4
0
3
0
2
1
0
0
0
0
0
0
0
0
0
0
0
(1) DV means Default Value. Refer to Extended Control Mode for more information on setting ECM default values.
Bit 15
Reserved. Must be set to 0b.
Bits 14:0
FM(14:0): FSR magnitude. These bits increase the ADC full-scale range magnitude (straight binary coding.) The range is from
600 mV (0d) to 1000 mV (32767d) with the default setting at 800 mV (16384d). Monotonicity is specified by design only for the
9 MSBs. The mid-range (low) setting in ECM corresponds to the nominal (low) setting in Non-ECM. A greater range of FSR
values is available in ECM, that is, FSR values above 800 mV. See VIN_FSR in Converter Electrical Characteristics: Analog
Input/Output and Reference Characteristics for characterization details.
CODE
FSR [mV]
600
000 0000 0000 0000
100 0000 0000 0000 (default)
111 1111 1111 1111
800
1000
Table 25. Aperture Delay Coarse Adjust
Addr: Ch (1100b)
Default Values: 0004h
Bit
15
14
0
13
0
12
0
11
10
9
8
7
6
5
4
0
3
STA
0
2
DCC
1
1
0
Name
DV(1)
CAM(11:0)
Res
0
0
0
0
0
0
0
0
0
0
(1) DV means Default Value. Refer to Extended Control Mode for more information on setting ECM default values.
Bits 15:4
CAM(11:0): Coarse adjust magnitude. This 12-bit value determines the amount of delay that is applied to the input CLK signal.
The range is 0-ps delay for CAM(11:0) = 0d to a maximum delay of 825 ps for CAM(11:0) = 2431d (±95 ps due to PVT
variation) in steps of ~340 fs. For code CAM(11:0) = 2432d and above, the delay saturates and the maximum delay applies.
Additional, finer delay steps are available in register Dh. The STA (Bit 3) must be selected to enable this function.
Bit 3
STA: Select tAD Adjust. Set this bit to 1b to enable the tAD adjust feature, which makes both coarse and fine adjustment
settings, that is, CAM(11:0) and FAM(5:0), available.
Bit 2
DCC: Duty cycle correct. This bit can be set to 0b to disable the automatic duty-cycle stabilizer feature of the chip. This feature
is enabled by default.
Bits 1:0
Reserved. Must be set to 0b.
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Table 26. Aperture Delay Fine Adjust
Addr: Dh (1101b)
Default Values: 0000h
Bit
15
14
0
13
12
0
11
0
10
9
8
7
6
5
4
3
0
2
1
0
Name
DV(1)
FAM(5:0)
Reserved
0
0
0
0
0
0
0
0
0
0
0
0
(1) DV means Default Value. Refer to Extended Control Mode for more information on setting ECM default values.
Bits 15:10 FAM(5:0): Fine aperture adjust magnitude. This 6-bit value determines the amount of additional delay that is applied to the
input CLK when the clock phase adjust feature is enabled through STA (Addr: Ch; Bit: 3). The range is straight binary from 0
ps delay for FAM(5:0) = 0d to 2.3 ps delay for FAM(5:0) = 63d (±300 fs due to PVT variation) in steps of ~36 fs.
Bits 9:0
Reserved. Must be set as shown.
Table 27. AutoSync
Addr: Eh (1110b)
Default Values: 0003h
Bit
15
14
0
13
0
12
0
11
DRC(8:0)
0
10
0
9
8
7
6
DCK
0
5
Res
0
4
3
0
2
ES
0
1
DOC
1
0
DR
1
Name
DV(1)
SP(1:0)
0
0
0
0
0
(1) DV means Default Value. Refer to Extended Control Mode for more information on setting ECM default values.
Bits 15:7
Bit 6
DRC(8:0): Delay reference clock. These bits may be used to increase the delay on the input reference clock when
synchronizing multiple ADCs. The delay may be set from a minimum of 0s (0d) to a maximum of 1200 ps (319d). The delay
remains the maximum of 1200 ps for any codes above or equal to 319d. See Synchronizing Multiple ADC12D1620 Devices in
a System for more information.
DCK: DESCLKIQ mode. Set this bit to 1b to enable Dual-Edge Sampling, in which the Sampling Clock samples the I and Q
inputs 180º out of phase with respect to one , that is, the DESCLKIQ mode. To select the DESCLKIQ mode, Addr: 0h, Bits
<7:5> must also be set to 000b. See Input Control and Adjust for more information.
Bit 5
Reserved. Must be set as shown.
Bits 4:3
SP(1:0): Select phase. These bits select the phase of the reference clock that is latched. The codes correspond to the
following phase shift:
00 = 0°
01 = 90°
10 = 180°
11 = 270°
Bit 2
Bit 1
ES: Enable slave. Set this bit to 1b to enable the slave mode of operation. In this mode, the internal divided clocks are
synchronized with the reference clock coming from the master ADC. The master clock is applied on the input pins RCLK. If this
bit is set to 0b, then the device is in master mode.
DOC: Disable output reference clocks. In non-LSPSM, setting this bit to 0b sends a CLK/4 signal on RCOut1 and RCOut2; in
LSPSM, setting this bit to 0b sends a CLK/2 signal on RCOut1 and RCOut2. The default setting of 1b disables these output
drivers. This bit functions as described, regardless of whether the device is operating in Master or Slave mode, as determined
by ES (Bit 2).
Bit 0
DR: Disable reset. The default setting of 1b leaves the DCLK_RST functionality disabled. Set this bit to 0b to enable
DCLK_RST functionality.
Table 28. Reserved
Addr: Fh (1111b)
Default Values: 001Dh
Bit
15
14
0
13
0
12
0
11
0
10
0
9
8
7
6
0
5
0
4
1
3
1
2
1
0
Name
DV(1)
Reserved
0
0
0
0
1
0
1
(1) DV means Default Value. Refer to Extended Control Mode for more information on setting ECM default values.
Bits 15:0 Reserved. This address is read only.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
8.1.1 Analog Inputs
The ADC12D1620 device continuously converts any signal that is present at the analog inputs, as long as a CLK
signal is also provided to the device. This section covers important aspects related to the analog inputs including:
acquiring the input, driving the ADC in DES mode, the reference voltage and FSR, out-of-range indication, AC-
DC-coupled signals, and single-ended input signals.
8.1.1.1 Acquiring the Input
The aperture delay, tAD, is the amount of delay, measured from the sampling edge of the clock input, after which
signal present at the input pin is sampled inside the device. Data is acquired at the rising edge of CLK+ in non-
DES mode and both the falling and rising edges of CLK+ in DES mode. In Non-DES mode, the I and Q channels
always sample data on the rising edge of CLK+. In DES mode, that is, DESI, DESQ, DESIQ, and DESCLKIQ,
the I-channel samples data on the rising edge of CLK+, and the Q-channel samples data on the falling edge of
CLK+. The digital equivalent of that data is available at the digital outputs a constant number of sampling clock
cycles later for the DI, DQ, DId and DQd output buses, also known as latency, depending on the demultiplex
mode which is selected. In addition to the latency, there is a constant output delay, tOD, before the data is
available at the outputs. See tOD in the Converter Electrical Characteristics: AC Electrical Characteristics, and
also see tLAT, tAD, and tOD in Converter Electrical Characteristics: AC Electrical Characteristics.
8.1.1.2 Driving the ADC in DES Mode
The ADC12D1620 can be configured as either a 2-channel, 1.6 GSPS device (Non-DES mode) or a 1-channel
3.2-GSPS device (DES mode). When the device is configured in DES mode, there is a choice for with which
input to drive the single-channel ADC. These are the 3 options:
DES – externally driving the I-channel input only. This is the default selection when the ADC is configured in DES
mode. It may also be referred to as DESI for added clarity.
DESQ – externally driving the Q-channel input only.
DESIQ, DESCLKIQ – externally driving both the I- and Q-channel inputs. VinI+ and VinQ+ must be driven with
the exact same signal. VinI- and VinQ- must be driven with the exact same signal, which is the differential
complement to the one driving VinI+ and VinQ+.
The input impedance for each I and Q input is 100-Ω differential (or 50-Ω single-ended), so the trace to each
VinI+, VinI-, VinQ+, and VinQ- must always be 50-Ω single-ended. If a single I or Q input is being driven, then
that input presents a 100-Ω differential load. For example, if a 50-Ω single-ended source is driving the ADC, a
1:2 balun transforms the impedance to 100-Ω differential. However, if the ADC is being driven in DESIQ mode,
then the 100-Ω differential impedance from the I input appears in parallel with the Q input for a composite load of
50-Ω differential, and a 1:1 balun would be appropriate. See Figure 44 for an example circuit driving the ADC in
DESIQ mode. A recommended part selection uses the mini-circuits TC1-1-13MA+ balun with Ccouple = 0.22 µF.
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Application Information (continued)
Ccouple
VINI+
VINI-
50 Ω
Source
100 Ω
1:1 Balun
Ccouple
Ccouple
VINQ+
100 Ω
VINQ-
Ccouple
ADC12D1600/1000RF
Copyright © 2017, Texas Instruments Incorporated
Figure 44. Driving DESIQ Mode
when only one channel is used in non-DES mode or the ADC is driven in DESI or DESQ mode, terminate the
unused analog input to reduce any noise coupling into the ADC. See Table 29 for details.
Table 29. Unused Analog Input Recommended Termination
MODE
POWER DOWN
COUPLING
AC-DC
DC
RECOMMENDED TERMINATION
Tie Unused+ and Unused– to VBG
Tie Unused+ and Unused– to VBG
Tie Unused+ to Unused–
Non-DES
Yes
No
DES/Non-DES
DES/Non-DES
No
AC
8.1.1.3 FSR and the Reference Voltage
The full-scale analog-differential input range (VIN_FSR) of the ADC12D1620 is derived from an internal bandgap
reference. In Non-ECM, this full-scale range has two settings controlled by the FSR pin; see Full-Scale Input-
Range Pin (FSR). The FSR Pin operates on both I and Q channels. In ECM, the full-scale range may be
independently set with 15 bits of precision for each channel through the I- and Q-channel Full-Scale Range
Adjust Registers (Addr: 3h and Addr: Bh, respectively); see Table 16 and Table 24 for information about the
registers. The best SNR is obtained with a higher full-scale input range, but better distortion and SFDR are
obtained with a lower full-scale input range. It is not possible to use an external analog reference voltage to
modify the full-scale range, and this adjustment should only be done digitally, as described.
A buffered version of the internal bandgap reference voltage is made available at the VBG pin for the user. The
VBG pin can drive a load of up to 80-pF and source or sink up to 100 μA. It must be buffered if current higher
than 100 μA is required. This pin remains as a constant reference voltage regardless of what full-scale range is
selected and may be used for a system reference. VBG is a dual-purpose pin and it may also be used to select a
higher LVDS output common-mode voltage; see LVDS Output Common-Mode Pin (VBG).
8.1.1.4 Out-Of-Range Indication
Differential input signals are digitized to 12 bits, based on the full-scale range. Signal excursions beyond the full-
scale range, that is, greater than +VIN_FSR/2 or less than – VIN_FSR/2, are clipped at the output. An input signal
above the FSR results in all 1's at the output; an an input signal that is below the FSR results in all 0's at the
output. When the conversion result is clipped for the I-channel input, the out-of-range I-channel (ORI) output is
activated so that ORI+ goes high and ORI– goes low while the signal is out of range. This output is active as
long as accurate data on either or both of the buses is outside the range of 000h to FFFh. The Q channel has a
separate ORQ, which functions similarly.
8.1.1.5 AC-Coupled Input Signals
The ADC12D1620 analog inputs require a precise common-mode voltage. This voltage is generated on-chip
when AC-coupling mode is selected. See AC- and DC-Coupled Modes for more information about how to select
AC-coupled mode.
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In AC-coupled mode, the analog inputs must of course be AC-coupled. For an ADC12D1620 used in a typical
application, this may be accomplished by on-board capacitors, as shown in Figure 45.
When the AC-coupled mode is selected, terminate unused channels as shown in Table 29. Do not connect an
unused analog input directly to ground.
C
C
couple
V
+
IN
couple
V
V
-
IN
CMO
ADC12D1600/1000RF
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Figure 45. AC-Coupled Differential Input
The analog inputs for the ADC12D1620 are internally buffered; this simplifies the task of driving these inputs and
the RC pole, which is generally used at sampling ADC inputs, is not required. If the user desires to place an
amplifier circuit before the ADC, take care to choose an amplifier with adequate noise and distortion
performance, and adequate gain at the frequencies used for the application.
8.1.1.6 DC-Coupled Input Signals
In DC-coupled mode, the ADC12D1620 differential inputs must have the correct common-mode voltage. This
voltage is provided by the device itself at the VCMO output pin. TI recommends using this voltage because the
VCMO output potential changes with temperature, and the common-mode voltage of the driving device should
track this change. Full-scale distortion performance falls off as the input common-mode voltage deviates from
VCMO. Therefore, TI recommends keeping the input common-mode voltage within 100 mV of VCMO (typical),
although this range may be extended to ±150 mV (maximum). See VCMI in Converter Electrical Characteristics:
Analog Input/Output and Reference Characteristics and ENOB vs VCMI in Typical Characteristics. Performance in
AC- and DC-coupled modes are similar, provided that the input common mode voltage at both analog inputs
remains within 100 mV of VCMO
.
8.1.1.7 Single-Ended Input Signals
The analog inputs of the ADC12D1620 are not designed to accept single-ended signals. The best way to handle
single-ended signals is to first convert them to differential signals before presenting them to the ADC. The easiest
way to accomplish single-ended to differential signal conversion is with an appropriate balun transformer, as
shown in Figure 46.
Ccouple
VIN+
50 Ω
Source
100 Ω
1:2 Balun
VIN-
Ccouple
ADC12D1600/1000RF
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Figure 46. Single-Ended to Differential Conversion Using a Balun
When selecting a balun, it is important to understand the input architecture of the ADC. Match the impedance of
the analog source to the on-chip 100-Ω differential input termination resistor of the device. The range of this
termination resistor is specified as RIN in Converter Electrical Characteristics: Analog Input/Output and Reference
Characteristics.
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8.1.2 Clock Inputs
The ADC12D1620 has a differential clock input, CLK+ and CLK–, which must be driven with an AC-coupled,
differential clock signal. This provides the level shifting necessary so that the clock can be driven with LVDS,
PECL, LVPECL, or CML levels. The clock inputs are internally terminated to 100-Ω differential and self-biased.
This section covers coupling, frequency range, level, duty-cycle, jitter, and layout considerations.
8.1.2.1 CLK Coupling
The clock inputs of the ADC12D1620 must be capacitively coupled to the clock pins as indicated in Figure 47.
Ccouple
CLK+
Ccouple
CLK-
ADC12D1600/1000RF
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Figure 47. Differential Input Clock Connection
Selection of capacitor value depends on the clock frequency, capacitor component characteristics, and other
system economic factors.
8.1.2.2 CLK Frequency
Although the ADC12D1620 device is tested and its performance is specified with a differential 1.6-GHz sampling
clock, it typically functions well over the input clock-frequency range; see fCLK
and fCLK
is possible if the maximum
in Converter
(min)
(max)
Electrical Characteristics: AC Electrical Characteristics. Operation up to fCLK
(max)
ambient temperatures indicated are not exceeded. Operating at sample rates above fCLK (max) for the maximum
ambient temperature may result in reduced device reliability and product lifetime. This is due to the fact that
higher sample rates results in higher power consumption and die temperatures. If in non-LSPSM and fCLK < 300
MHz, enable LFS in the Control Register (Addr: 0h; Bit: 8). In LSPSM, the LFS bit is already enabled.
8.1.2.3 CLK Level
The input clock amplitude is specified as VIN_CLK in Converter Electrical Characteristics: AC Electrical
Characteristics. Input clock amplitudes above the maximum VIN_CLK may result in increased input offset voltage.
This causes the converter to produce an output code other than the expected 2047/2048 when both input pins
are at the same potential. Insufficient input clock levels result in poor dynamic performance. Both of these results
may be avoided by keeping the clock input amplitude within the specified limits of VIN_CLK
.
8.1.2.4 CLK Duty Cycle
The duty cycle of the input clock signal can affect the performance of any ADC. The ADC12D1620 device
features a duty-cycle-clock correction circuit, which can maintain performance over the 20%-to-80% specified
clock duty-cycle range. This feature is enabled by default and provides improved ADC clocking, especially in the
dual-edge sampling (DES) mode.
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8.1.2.5 CLK Jitter
High-speed, high-performance ADCs such as the ADC12D1620 require a very stable input clock signal with
minimum phase noise or jitter. ADC jitter requirements are defined by the ADC resolution (number of bits),
maximum ADC input frequency, and the input signal amplitude relative to the ADC input full-scale range. The
maximum jitter (the sum of the jitter from all sources) allowed to prevent a jitter-induced reduction in SNR is
found to be:
tJ(MAX) = (VIN(P-P)/ VFSR) x (1/(2(N+1) x π x fIN))
where
•
•
•
•
•
tJ(MAX) is the rms total of all jitter sources in seconds
VIN(P-P) is the peak-to-peak analog input signal
VFSR is the full-scale range of the ADC
N is the ADC resolution in bits
fIN is the maximum input frequency, in Hertz, at the ADC analog input
(1)
tJ(MAX) is the square root of the sum of the squares (RSS) of the jitter from all sources, including: ADC input clock,
system, input signals, and the ADC itself. Because the effective jitter added by the ADC is beyond user control,
TI recommends keeping the sum of all other externally added jitter to a minimum.
8.1.2.6 CLK Layout
The ADC12D1620 clock input is internally terminated with a trimmed 100-Ω resistor. The differential input clock
line pair must have a characteristic impedance of 100 Ω and (when using a balun), be terminated at the clock
source in that (100-Ω) characteristic impedance.
It is good practice to keep the ADC input clock line as short as possible, tightly coupled, keep it well away from
any other signals, and treat it as a transmission line. Otherwise, other signals can introduce jitter into the input
clock signal. Also, the clock signal can introduce noise into the analog path if it is not properly isolated.
8.1.3 LVDS Outputs
The data, ORI, ORQ, DCLKI and DCLKQ outputs are LVDS. The electrical specifications of the LVDS outputs
are compatible with typical LVDS receivers available on ASIC and FPGA chips; however, they are not IEEE or
ANSI communications standards compliant due to the low 1.9-V supply used on this device. Terminate these
outputs with a 100-Ω differential resistor placed as closely as possible to the receiver. If the 100-Ω differential
resistance is built into the receiver, an externally placed resistor is not necessary. This section covers common-
mode and differential voltage, and data rate.
8.1.3.1 Common-Mode and Differential Voltage
The LVDS outputs have selectable common-mode and differential voltage, VOS and VOD; see Converter Electrical
Characteristics: Digital Control and Output Pin Characteristics and also see Output Control and Adjust for more
information.
Selecting the higher VOS also increases VOD slightly. The differential voltage, VOD, may be selected for the higher
or lower value. For short LVDS lines and low noise systems, satisfactory performance may be achieved with the
lower VOD. This also results in lower power consumption. If the LVDS lines are long and/or the system in which
the ADC12D1620 is used is noisy, it may be necessary to select the higher VOD
.
8.1.3.2 Output Data Rate
The data is produced at the output at the same rate it is sampled at the input. The minimum recommended input
clock rate for this device is fCLK(MIN); see Converter Electrical Characteristics: AC Electrical Characteristics.
However, it is possible to operate the device in 1:2 demux mode and capture data from just one 12-bit bus; for
example, just DI (or DId) although both DI and DId are fully operational. This decimates the data by two and
effectively halves the data rate.
8.1.3.3 Terminating Unused LVDS Output Pins
If the ADC is used in non-demux mode, only the DI and DQ data outputs will have valid data present on them.
The DId and DQd data outputs may be left not connected; if unused, they are internally tri-state.
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Similarly, if the Q channel is powered-down (that is, PDQ is logic-high), the DQ data output pins, DCLKQ and
ORQ, may be left not connected.
8.1.4 Synchronizing Multiple ADC12D1620 Devices in a System
The ADC12D1620 has two features to assist the user with synchronizing multiple ADCs in a system: AutoSync
and DCLK reset. The AutoSync feature is new and designates one ADC12D1620 as the master ADC and other
ADC12D1620 devices in the system as slave ADCs. The DCLK reset feature performs the same function as the
AutoSync feature, but is the first-generation solution to synchronizing multiple ADCs in a system; it is disabled by
default. For applications in which there are multiple master and slave ADC12D1620 devices in a system,
AutoSync may be used to synchronize the slave ADC12D1620 devices to each respective master ADC12D1620,
and the DCLK reset may be used to synchronize the master ADC12D1620 devices to each other.
If the AutoSync or DCLK reset feature is not used, see Table 30 for recommendations about terminating unused
pins.
Table 30. Unused AutoSync and DCLK Reset Pin Recommendation
PIN(s)
UNUSED TERMINATION
Do not connect.
RCLK+, RCLK–
RCOUT1+, RCOUT1–
RCOUT2+, RCOUT2–
DCLK_RST+
Do not connect.
Do not connect.
Connect to GND with a 1-kΩ resistor.
Connect to VA with a 1-kΩ resistor.
DCLK_RST-
8.1.4.1 AutoSync Feature
AutoSync is a new feature which continuously synchronizes the outputs of multiple ADC12D1620 devices in a
system. It may be used to synchronize the DCLK and data outputs of one or more slave ADC12D1620 devices to
one master ADC12D1620. Several advantages of this feature include: no special synchronization pulse required,
any upset in synchronization is recovered upon the next DCLK cycle, and the master/slave ADC12D1620
devices may be arranged as a binary tree so that any upset quickly propagates out of the system.
An example system is shown in Figure 48, which consists of one master ADC and two slave ADCs. For
simplicity, only one DCLK is shown; in reality, there is DCLKI and DCLKQ, but they are always in phase with one
another.
Slave 1
ADC12D1600/1000RF
Slave 2
ADC12D1600/1000RF
RCOut1
RCOut2
DCLK
RCOut1
RCOut2
DCLK
Master
ADC12D1600/1000RF
RCOut1
RCOut2
DCLK
CLK
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Figure 48. AutoSync Example
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In order to synchronize the DCLK (and data) outputs of multiple ADCs, the DCLKs must transition at the same
time, as well as be in phase with one another. The DCLK at each ADC is generated from the CLK after some
latency, plus tOD minus tAD. Therefore, in order for the DCLKs to transition at the same time, the CLK signal must
reach each ADC at the same time. To tune out any differences in the CLK path to each ADC, the tAD adjust
feature may be used. However, using the tAD adjust feature also affects when the DCLK is produced at the
output. If the device is in demux mode, there are four possible phases that each DCLK may be generated on
because the typical CLK = 1GHz and DCLK = 250 MHz for this case. The RCLK signal controls the phase of the
DCLK, so that each slave DCLK is on the same phase as the master DCLK.
The AutoSync feature may only be used through the Control Registers. For more information, see AN-2132
Synchronizing Multiple GSPS ADCs in a System: The AutoSync Feature.
8.1.4.2 DCLK Reset Feature
The DCLK reset feature is available through ECM, but it is disabled by default. DCLKI and DCLKQ are always
synchronized, by design, and do not require a pulse from DCLK_RST to become synchronized.
The DCLK_RST signal must observe certain timing requirements, which are shown in Figure 7 of Timing
Requirements: Calibration. The DCLK_RST pulse must be of a minimum width, and its deassertion edge must
observe setup and hold times with respect to the CLK input rising edge. These timing specifications are listed as
tPWR, tSR and tHR and may be found in Converter Electrical Characteristics: AC Electrical Characteristics.
The DCLK_RST signal can be asserted asynchronously to the input clock. If DCLK_RST is asserted, the DCLK
output is held in a designated state (logic-high) in demux mode; in non-demux mode, the DCLK continues to
function normally. Depending upon when the DCLK_RST signal is asserted, there may be a narrow pulse on the
DCLK line during this reset event. When the DCLK_RST signal is de-asserted, there are tSYNC_DLY CLK cycles of
systematic delay and the next CLK rising edge synchronizes the DCLK output with those of other ADC12D1620
devices in the system. For 90° mode (DDRPh = logic-high), the synchronizing edge occurs on the rising edge of
CLK, 4 cycles after the first rising edge of CLK after DCLK_RST is released. For 0° mode (DDRPh = logic-low),
this is 5 cycles instead. The DCLK output is enabled again after a constant delay of tOD
.
For both demux and non-demux modes, there is some uncertainty about how DCLK comes out of the reset state
for the first DCLK_RST pulse. For the second (and subsequent) DCLK_RST pulses, the DCLK comes out of the
reset state in a known way. Therefore, if using the DCLK reset feature, TI recommends applying one dummy
DCLK_RST pulse before using the second DCLK_RST pulse to synchronize the outputs. This recommendation
applies each time the device or channel is powered-on.
When using DCLK_RST to synchronize multiple ADC12D1620 devices, the select-phase bits in the Control
Register (Addr: Eh, Bits: 4:3) must be the same for each master ADC12D1620.
8.1.5 Temperature Sensor
The ADC12D1620 has an on-die temperature diode connected to the Tdiode+ and Tdiode– pins that may be
used to monitor the die temperature. In Figure 49, the LM95213 is used to monitor the temperature of an
ADC12D1620 as well as an FPGA, see Figure 49. Typical temperature diode voltage to temperature
characteristic is:
(Vdiode - 0.84161)
TJ =
-0.0015
for
•
1-mA diode forward current
(2)
If this feature is unused, the Tdiode+ and Tdiode– pins may be left floating.
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7
5
D1+
D-
IE = IF
100 pF
ADC12D1600/1000RF
IR
IE = IF
100 pF
FPGA
6
D2+
IR
LM95213
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Figure 49. Typical Temperature Sensor Application
8.2 Radiation Environments
Careful consideration must be given to environmental conditions when using a product in a radiation
environment.
8.2.1 Total Ionizing Dose
Radiation hardness assured (RHA) products are those part numbers with a total ionizing dose (TID) level
specified in the POA. Testing and qualification of these products is done on a wafer level according to MIL-STD-
883, Test Method 1019. Wafer level TID data are available with lot shipments.
8.2.2 Single Event Latch-Up and Functional Interrupt
One time single event latch-up (SEL) and single event functional interrupt (SEFI) testing was performed
according to EIA/JEDEC Standard, EIA/JEDEC57. The linear energy transfer threshold (LETth) shown in the
Features section is the maximum LET tested. A test report is available upon request.
8.2.3 Single Event Upset
A report on single event upset (SEU) is available upon request.
8.3 Cold Sparing
The ADC12D1620QML-SP has been designed for cold sparing with no reduction in operational lifetime or
increase in FIT rate as long as certain conditions are met. Cold sparing is defined as a device in which all power
supplies are either floating (high-impedance) or grounded. When cold sparing, all output pins must be either
floating or clamped to ground through ESD diodes of the receiving device and not pulled up to an active power
supply voltage. Input pins may be driven low (or grounded) or driven to other voltages as long as they are within
the Recommended Operating Conditions. Input pins (digital and analog) must maintain a maximum input level of
2.15 V and maximum input current of 50 mA per pin when cold sparing. The input current at each pin is a
function of the voltage applied to the pin, the ESD diode IV curve, the power down pin settings, and conditions of
the V_A supply. See Figure 50 to Figure 52 for typical IV curves.
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Cold Sparing (continued)
100
80
60
40
20
0
100
80
60
40
20
0
TJ = 30èC
TJ = 100èC
TJ = 30èC
TJ = 100èC
-20
-20
0
0.5
1
1.5
0
0.5
1
1.5
2
2.5
3
Applied Input Voltage (V)
Applied Input Voltage (V)
D090
D091
VA = GND
VA = HiZ
PDI = PDQ = Low
Figure 50. ESD Diode Current
Figure 51. ESD Diode Current
100
80
60
40
20
0
TJ = 30èC
TJ = 100èC
-20
0
0.5
1
1.5
2
2.5
3
Applied Input Voltage (V)
D092
VA = HiZ
PDI = PDQ = High
Figure 52. ESD Diode Current
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9 Power Supply Recommendations
9.1 System Power-On Considerations
9.1.1 Control Pins
Upon power-on, the control pins must be set to the proper configuration per Table 9, ensuring the absolute
maximum values in Absolute Maximum Ratings are not violated. This can be done through either pullup and
pulldown resistors to VA and VGND or through an FPGA or ASIC. If using an FPGA or ASIC, TI does not
recommended writing to the control pins or SPI before power is applied to the ADC12D1620 device.
9.1.2 Power On in Non-ECM
If the device is in non-ECM at power on, the control registers are configured in the default mode shown in
Table 1 and Register Definitions. The device may be run in non-ECM or switched to ECM and have the registers
changed through the SPI per Extended Control Mode. After the device has been configured and has stabilized,
run a calibration per Calibration Feature.
9.1.3 Power On in ECM
If the device is in ECM at power on, the control registers come up in an unknown, random state. The registers
must be configured through the SPI per Extended Control Mode, or the registers can be set to the default
settings in Table 1 by toggling the ECE pin logic-high and then logic-low. After the device has been configured
and has stabilized, run a calibration per Calibration Feature.
9.1.4 Power-on and Data Clock (DCLK)
Many applications use the DCLK output for a system clock. For the ADC12D1620 device, each I channel and Q
channel has its own DCLKI and DCLKQ, respectively. The DCLK output is always active, unless that channel is
powered down or the DCLK reset feature is used while the device is in demux mode. As the supply to the device
ramps, the DCLK also comes up. While the supply is too low, there is no output at DCLK. As the supply
continues to ramp, DCLK functions intermittently with irregular frequency, but the amplitude continues to track
with the supply. Much below the low end of operating supply range of the ADC12D1620, the DCLK is already
fully operational.
Slope = 1.22V/ms
1900
1710
1490
VA
1210
660
635
520
DCLK
300
time
Figure 53. Supply and DCLK Ramping
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10 Layout
10.1 Layout Guidelines
10.1.1 Power Planes
Source all supply buses for the ADC from a common linear voltage regulator. This ensures that all power buses
to the ADC are turned on and off simultaneously. This single source is split into individual sections of the power
plane, with individual decoupling and connections to the different power supply buses of the ADC. Due to the low
voltage but relatively high supply-current requirement, the optimal solution may be to use a switching regulator to
provide an intermediate low voltage, which is then regulated down to the final ADC supply voltage by a linear
regulator.
Power for the ADC must be provided through a broad plane, which is located on one layer adjacent to the
ground plane(s). Placing the power and ground planes on adjacent layers provides low-impedance decoupling of
the ADC supplies, especially at higher frequencies. The output of a linear regulator must feed into the power
plane through a low-impedance, multi-via connection. The power plane must be split into individual power
peninsulas near the ADC. Each peninsula must feed a particular power bus on the ADC, with decoupling for that
power bus connecting the peninsula to the ground plane near each power/ground pin pair. Using this technique
can be difficult on many printed circuit CAD tools. To work around this, 0-Ω resistors can be used to connect the
power source net to the individual nets for the different ADC power buses. As a final step, the 0-Ω resistors can
be removed, and the plane and peninsulas can be connected manually after all other error checking is
completed.
10.1.2 Bypass Capacitors
TI's general recommendation is to have one 100-nF capacitor for each power/ground pin pair. The capacitors
must be surface-mount multi-layer ceramic-chip capacitors similar to Panasonic part number ECJ-0EB1A104K.
10.1.3 Ground Planes
Grounding must done using continuous full ground planes to minimize the impedance for all ground return paths
and provide the shortest possible image/return path for all signal traces.
10.1.4 Power System Example
See Figure 54 for an example with continuous ground planes (except where clear areas are needed to provide
appropriate impedance management for specific signals). Power is provided on one plane, with the 1.9-V ADC
supply being split into multiple zones or peninsulas for the specific power buses of the ADC. Decoupling
capacitors are connected between these power bus peninsulas and the adjacent ground planes using vias. The
capacitors are located as close as possible to the individual power/ground pin pairs of the ADC. In most cases,
this means the capacitors are located on the opposite side of the PCB to the ADC.
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Layout Guidelines (continued)
HV or Unreg
Voltage
Linear
Regulator
Switching
Regulator
Cross Section
Line
Intermediate
Voltage
1.9V ADC Main
VTC VA VE
VDR
ADC
Top Layer œ Signal 1
Ground 1
Dielectric 1
Dielectric 2
Dielectric 3
Dielectric 4
Dielectric 5
Dielectric 6
Dielectric 7
Signal 2
Ground 2
Signal 3
Power 1
Ground 3
Bottom Layer œ Signal X
Figure 54. Power and Grounding Example
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10.2 Layout Example
Balun transformer to convert the
SE CLK signal to differential signal
CLK path with minimal
adjacent circuit
To provide best grounding and thermal
Analog input path with
minimal adjacent circuit
performance all the ground pins on
internal pad should be connected to all the
ground layers with vias.
High speed data paths and DCLK
signals should be of same length
Figure 55. ADC12D1620 Layout Example: Top Side and Inner Layers
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Layout Example (continued)
All high speed signal routing should use impedance
controlled traces, either 50-Ω single ended or 100-Ω
differential
Decoupling
capacitors near
the device
Decoupling
Capacitors near
VIN
The four holes highlighted with black squares were for the
socket version of the board and are not required for end
application.
Figure 56. ADC12D1620 Layout Example: Bottom Side and Inner Layers
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10.3 Thermal Considerations
The CCGA package is a modified ceramic-land-grid array with an added heat sink. The signal pins on the outer
edge are 1.27-mm pitch, while the pins in the center attached to the heat sink are 1 mm. The smaller pitch for the
center pins is to improve the thermal resistance. The center pins of the package are attached to the back of the
die through a heat sink. Connecting these pins to the PCB ground planes with a low thermal resistance path is
the best way to remove heat from the ADC. These pins must also be connected to the ground planes through
low impedance path for electrical purposes.
IC Die
Cross Section
Line
Heat Sink
Not to Scale
Figure 57. CPGA Conceptual Drawing
10.4 Board Mounting Recommendation
Proper thermal profile is required to establish re-flow under the package and ensure all joints meet profile
specifications.
Table 31. Solder Profile Specification
MAXIMUM PEAK
TEMPERATURE
RANGE UP
PEAK TEMPERATURE (TPK
)
RAMP DOWN
≤ 4°C/sec
210°C ≤ tPK ≤ 215°C
≤ 220°C
≤ 5°C/sec
The 220°C peak temperature is driven by the requirement to limit the dissolution of lead from the high-melt pin to
the eutectic solder. Too much lead increases the effective melting point of the board-side joint and makes it
much more difficult to remove the device if module rework is required.
Cool-down rates and methods affect CCGA assemble yield and reliability. Picking up boards or opening the oven
while solder joints are in molten state can disturb the solder joint. Do not pick up boards until the solder joints
have fully solidified. Board warping may potentially cause CCGA lifting off pads during cooling and this condition
can also cause pin cracking when severe. This warping is a result of a high differential cooling rate between the
top and bottom of the board. Both conditions can be prevented by using even top and bottom cooling.
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Figure 58. Landing Pattern Recommendation
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
11.1.2 Device Nomenclature
APERTURE (SAMPLING) DELAY is the amount of delay, measured from the sampling edge of the CLK input,
after which the signal present at the input pin is sampled inside the device.
APERTURE JITTER (tAJ) is the variation in aperture delay from sample-to-sample. Aperture jitter can be
effectively considered as noise at the input.
CODE ERROR RATE (CER) is the probability of error and is defined as the probable number of word errors on
the ADC output per unit of time divided by the number of words seen in that amount of time. A CER of 10–18
corresponds to a statistical error in one word about every 31.7 years for the adc12d1620QML-SP .
CLOCK DUTY CYCLE is the ratio of the time that the clock waveform is at a logic high to the total time of one
clock period.
DIFFERENTIAL NON-LINEARITY (DNL) is the measure of the maximum deviation from the ideal step size of 1
LSB. It is measured at the relevant sample rate, fCLK, with fIN = 1 MHz sine wave.
EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE BITS) is method of specifying signal-to-noise and
distortion ratio, or SINAD. ENOB is defined as (SINAD − 1.76) / 6.02 and states that the converter is equivalent
to a perfect ADC of this many (ENOB) number of bits.
GAIN ERROR is the deviation from the ideal slope of the transfer function. It can be calculated from offset and
full-scale errors. the positive gain error is the offset error minus the positive full-scale error. The negative gain
error is the negative full-scale error minus the offset error. The gain error is the negative full-scale error minus the
positive full-scale error; it is also equal to the positive gain error plus the negative gain error.
GAIN FLATNESS is the measure of the variation in gain over the specified bandwidth. For example, for the
adc12d1620QML-SP, from D.C. to Fs/2 is to 800 MHz for the non-DES mode and from D.C. to Fs/2 is 1600 MHz
for the DES mode.
INTEGRAL NON-LINEARITY (INL) is a measure of worst-case deviation of the ADC transfer function from an
ideal straight line drawn through the ADC transfer function. The deviation of any given code from this straight line
is measured from the center of that code value step. The best fit method is used.
INSERTION LOSS is the loss in power of a signal due to the insertion of a device, for example the adc12d1620,
expressed in dB.
INTERMODULATION DISTORTION (IMD) is a measure of the near-in 3rd order distortion products (2f2 – f1,
2f1 – f2), which occur when two tones that are close in frequency (f1, f2) are applied to the ADC input. It is
measured from the input tone's level to the higher of the two distortion products (dBc) or simply the level of the
higher of the two distortion products (dBFS).
LSB (LEAST SIGNIFICANT BIT) is the bit that has the smallest value or weight of all bits. This value is
VFS / 2N
where
•
•
VFS is the differential full-scale amplitude VIN_FSR as set by the FSR input
N is the ADC resolution in bits, which is 12 for the adc12d1620
(3)
LOW VOLTAGE DIFFERENTIAL SIGNALING (LVDS) DIFFERENTIAL OUTPUT VOLTAGE (VID and VOD) is
two times the absolute value of the difference between the VD+ and VD- signals; each signal measured with
respect to ground. VOD peak is VOD,P= (VD+ – VD–) and VOD peak-to-peak is VOD,P-P= 2 × (VD+ – VD–); for this
product, the VOD is measured peak-to-peak.
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Device Support (continued)
V
D
+
V
-
D
½×V
OD
V +
D
V
OS
V
-
D
GND
½×V = | V + - V - |
OD
D
D
Figure 59. LVDS Output Signal Levels
LVDS OUTPUT OFFSET VOLTAGE (VOS) is the midpoint between the D+ and D– pins output voltage with
respect to ground; that is , [(VD+) +( VD-)]/2. See Figure 59.
MISSING CODES are those output codes that are skipped and will never appear at the ADC outputs. These
codes cannot be reached with any input value.
MSB (MOST SIGNIFICANT BIT) is the bit that has the largest value or weight. Its value is one half of full scale.
NEGATIVE FULL-SCALE ERROR (NFSE) is a measure of how far the first code transition is from the ideal 1/2
LSB above a differential −VIN / 2 with the FSR pin low. For the adc12d1620 the reference voltage is assumed to
be ideal, so this error is a combination of full-scale error and reference voltage error.
NOISE FLOOR DENSITY is a measure of the power density of the noise floor, expressed in dBFS/Hz and
dBm/Hz. '0 dBFS' is defined as the power of a sinusoid that precisely uses the full-scale range of the ADC.
NOISE POWER RATIO (NPR) is the ratio of the sum of the power inside the notched bins to the sum of the
power in an equal number of bins outside the notch, expressed in dB.
OFFSET ERROR (VOFF) is a measure of how far the mid-scale point is from the ideal zero voltage differential
input.
Offset Error = Actual Input causing average of 8 k samples to result in an average code of 2047.5.
OUTPUT DELAY (tOD) is the time delay (in addition to latency) after the rising edge of CLK+ before the data
update is present at the output pins.
OVER-RANGE RECOVERY TIME is the time required after the differential input voltages goes from ±1.2 V to 0
V for the converter to recover and make a conversion with its rated accuracy.
PIPELINE DELAY (LATENCY) is the number of input clock cycles between initiation of conversion and when
that data is presented to the output driver stage. The data lags the conversion by the latency plus the tOD
.
POSITIVE FULL-SCALE ERROR (PFSE) is a measure of how far the last code transition is from the ideal 1-1/2
LSB below a differential +VIN / 2. For the ADC12D1620 the reference voltage is assumed to be ideal, so this
error is a combination of full-scale error and reference voltage error.
SIGNAL-TO-NOISE RATIO (SNR) is the ratio, expressed in dB, of the rms value of the fundamental for a single-
tone to the rms value of the sum of all other spectral components below one-half the sampling frequency, not
including harmonics or DC.
SIGNAL-TO-NOISE PLUS DISTORTION (S/(N+D) or SINAD) is the ratio, expressed in dB, of the rms value of
the fundamental for a single tone to the rms value of all of the other spectral components below half the input
clock frequency, including harmonics but excluding DC.
SPURIOUS-FREE DYNAMIC RANGE (SFDR) is the difference, expressed in dB, between the rms values of the
input signal at the output and the peak spurious signal, where a spurious signal is any signal present in the
output spectrum that is not present at the input, excluding DC.
R
R
R
θJA is the thermal resistance between the junction to ambient.
θJB is the thermal resistance between the junction and the circuit board close to the outer pins.
θJT is the thermal resistance between the junction and the case, measured at the lid of the package.
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Device Support (continued)
TOTAL HARMONIC DISTORTION (THD) is the ratio expressed in dB, of the rms total of the first nine harmonic
levels at the output to the level of the fundamental at the output. THD is calculated as
2
2
f10
A
+ . . . + A
f2
THD = 20 x log
2
A
f1
where
•
•
Af1 is the RMS power of the fundamental (output) frequency
Af2 through Af10 are the RMS power of the first 9 harmonic frequencies in the output spectrum
(4)
– Second Harmonic Distortion (2nd Harm) is the difference, expressed in dB, between the RMS power in the
input frequency seen at the output and the power in its 2nd harmonic level at the output.
– Third Harmonic Distortion (3rd Harm) is the difference expressed in dB between the RMS power in the input
frequency seen at the output and the power in its 3rd harmonic level at the output.
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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12.1 Engineering Samples
Engineering samples are available for order and are identified by the "MPR" in the orderable device name (see
Packaging Information in the Addendum). Engineering (MPR) samples meet the performance specifications of
the datasheet at room temperature only and have not received the full space production flow or testing.
Engineering samples may be QCI rejects that failed tests that would not impact the performance at room
temperature, such as radiation or reliability testing.
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PACKAGE OPTION ADDENDUM
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17-Oct-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
5962F1220502VXF
ADC12D1620CCMLS
ADC12D1620CCMPR
ADC12D1620LGMLS
ADC12D1620LGMPR
PREVIEW
CCGA
CCGA
CCGA
CLGA
CLGA
NAA
376
376
376
256
256
1
TBD
TBD
TBD
TBD
TBD
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
-55 to 125
-55 to 125
25 to 25
F1220502VXF
ADC12D1620
ACTIVE
ACTIVE
ACTIVE
ACTIVE
NAA
1
Call TI
Call TI
Call TI
Call TI
ADC12D1620CC
MLS
NAA
1
ADC12D1620CC
MPR E.S.
FVA
1
-55 to 125
25 to 25
ADC12D1620LG
MLS
FVA
1
ADC12D1620LG
MPR E.S.
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
17-Oct-2020
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE OUTLINE
FVA0256A
CLGA - 4.13 mm max height
SCALE 0.500
Ceramic Land Grid Array
28.16
27.72
L
(45 X 1.02)
PIN 1 INDEX MARK
28.16
27.72
(
21.81)
SEAL RING
19.81 0.08
M
(3X 45 X 0.51)
4.13 MAX
N
0.1
0.63
0.37
(2.79)
24.13 TYP
1.27 TYP
1.27 TYP
Y
W
0.05
V
U
T
R
P
N
M
L
K
J
24.13
TYP
11 0.13
HEAT SINK
H
G
F
E
D
C
B
0.94
0.84
256X
0.3
0.15
N L
N
M
A
2
3
4
6
7
11 12 13 14
16 17
1
5
8
9 10
15
18
19 20
INDEX MARK
4221354/A 04/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
MECHANICAL DATA
NAA0376A
CCC376A (Rev D)
www.ti.com
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