ADC12DJ5200SE_技术文档

ADC12DJ5200SE

ZHCSOJ3A –MARCH 2023 –REVISED MAY 2023

ADC12DJ5200SE 具有集成平衡-非平衡变压器的10.4GSPS 单通道或5.2GSPS 双

通道12 位射频采样模数转换器(ADC)

1 特性

3 说明

• ADC 内核：

ADC12DJ5200SE 是一款具有集成输入平衡-非平衡变

压器的射频采样千兆采样模数转换器 (ADC) 。

ADC12DJ5200SE 可配置为双通道 5.2GSPS ADC 或

单通道 10.4GSPS ADC。-3dB 输入频率范围为 2GHz

至 6.3GHz，可对频率捷变系统的 S 和 C 频带进行直

接射频采样。

– 12 位分辨率

– 单通道模式下的采样率高达10.4 GSPS

– 双通道模式下的采样率高达5.2 GSPS

• 单端50Ω输入：

– 模拟输入范围(-3dB)：2 至6.3 GHz

– 满量程输入功率(4.5GHz)：- 1.25dBm

– 灵活的V_CM：没有直流路径连接到GND 或电源

的交流耦合

ADC12DJ5200SE 使用具有多达 16 个串行通道的高速

JESD204C 输出接口，支持高达 17.16Gbps 的线路速

率。通过 JESD204C 子类 1 支持确定性延迟和多器件

同步。JESD204C 接口可进行配置，对线路速率和通

道数进行权衡。支持 8b/10b 和 64b/66b 数据编码方

案。64b/66b 编码支持前向纠错 (FEC)，可改进误码

率。此接口向后兼容JESD204B 接收器。

• 性能规格：

– 本底噪声（2.3GHz、–20dBFS、

INPUT_FS= 1.5dBm）：

• 双通道模式：-149dBFS/Hz

• 单通道模式：-151.5dBFS/Hz

– ENOB（双通道，F_IN= 2.3 GHz）：8.5 位

• 无噪声孔径延迟(t_AD) 调节：

– 精确采样控制：19 fs 步长

– 简化同步和交错

– 温度和电压不变延迟

• 简便易用的同步特性：

无噪声孔径延迟调节和 SYSREF 窗口等创新的同步特

性可简化多通道应用的系统设计。提供可选的数字下变

频器 (DDC)，以便将数字信号频谱下变频到基带信号

并降低接口速率。可编程 FIR 滤波器可实现片上均

衡。

封装信息

封装⁽¹⁾

封装尺寸（标称值）

器件型号

– 自动SYSREF 计时校准

– 样片标记时间戳

ADC12DJ5200SE

FCBGA (144) 10.00mm × 10.00mm

• JESD204C 串行数据接口：

(1) 如需了解所有可用封装，请参阅产品说明书末尾的封装选项附

录。

– 最大通道速率：17.16 Gbps

– 支持64b/66b 和8b/10b 编码

– 8b/10b 模式兼容JESD204B

• 可选数字下变频器(DDC)：

– 4 倍、8 倍、16 倍和32 倍复杂抽取

– 每个DDC 均具有四个独立的32 位NCO

• 峰值射频输入功率：+26.25 dBm（+ 27.5 dBFS，

560x 满量程功率）

NCOA0 NCOA1 NCOB0 NCOB1 CALTRG PD

SCLK

SDI

SDO

SCS\

SPI Registers and

Device Control

DDC Bypass / Single Channel Mode

DDC

A

TMSTP+

TMSTP-

DA0+

DA0-

NCO Bank

A

Input

MUX

JESD204B

Link

ADC

A

N

A

INA

DA7+

DA7-

Mixer

Filter

JMODE

DDC Bypass / Single Channel Mode

Over-

range

SYNCSE\

DDC

B

DB0+

DB0-

NCO Bank

B

INB

Input

MUX

JESD204B

Link

ADC

B

N

B

DB7+

DB7-

Mixer

Filter

• 可实现均衡的可编程FIR 滤波器

DIGBIND

Aperture

Delay Adjust

JMODE

• 功耗：4W

CLK+

CLK-

Clock Distribu on

and Synchroniza on

• 电源：1.1V/1.9V

Status

Indicators

SYSREF+

SYSREF-

SYSREF

Windowing

2 应用

TDIODE+

TDIODE-

• 通信测试仪（802.11ad，5G）

• 电子战（信号情报、电子情报）

• 卫星通信(SATCOM)

ADC12DJ5200SE 方框图

• 射频采样软件定义无线电(SDR)

本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SLVSGH5

ADC12DJ5200SE

ZHCSOJ3A –MARCH 2023 –REVISED MAY 2023

www.ti.com.cn

Table of Contents

7.1 Overview...................................................................36

7.2 Functional Block Diagram.........................................37

7.3 Feature Description...................................................38

7.4 Device Functional Modes..........................................71

7.5 Programming............................................................ 97

7.6 SPI Register Map......................................................99

8 Application Information Disclaimer...........................165

8.1 Application Information........................................... 165

8.2 Typical Applications................................................ 165

8.3 Initialization Set Up................................................. 168

8.4 Power Supply Recommendations...........................169

8.5 Layout..................................................................... 171

9 Device and Documentation Support..........................175

9.1 Device Support....................................................... 175

9.2 Documentation Support.......................................... 175

9.3 Receiving Notification of Documentation Updates..176

9.4 Support Resources................................................. 176

9.5 Trademarks.............................................................176

10 Mechanical, Packaging, and Orderable

1 特性................................................................................... 1

2 应用................................................................................... 1

3 说明................................................................................... 1

4 Revision History.............................................................. 2

5 Pin Configuration and Functions...................................3

6 Specifications.................................................................. 9

6.1 Absolute Maximum Ratings........................................ 9

6.2 ESD Ratings............................................................... 9

6.3 Recommended Operating Conditions.......................10

6.4 Thermal Information..................................................10

6.5 Electrical Characteristics: DC Specifications............ 11

6.6 Electrical Characteristics: Power Consumption........ 13

6.7 Electrical Characteristics: AC Specifications

(Dual-Channel Mode)..................................................14

6.8 Electrical Characteristics: AC Specifications

(Single-Channel Mode)............................................... 17

6.9 Timing Requirements................................................21

6.10 Switching Characteristics........................................23

6.11 Typical Characteristics............................................ 26

7 Detailed Description......................................................36

Information.................................................................. 176

4 Revision History

注：以前版本的页码可能与当前版本的页码不同

Changes from Revision * (March 2023) to Revision A (May 2023)

Page

• 将文档状态从预告信息更改为生产数据 ............................................................................................................ 1

English Data Sheet: SLVSGH5

2

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5 Pin Configuration and Functions

图5-1. AAV Package, 144-Ball Flip Chip BGA (Top View)

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表5-1. Pin Functions

I/O

DESCRIPTION

NAME

NO.

A1, A2, A3,

A5, A6, A7,

B2, B3, B4,

B5, B6, B7,

C6, D1, D6,

E1, E6, F2, F3,

F6, G2, G3,

G6, H1, H6,

J1, J6, L2, L3,

L4, L5, L6, L7,

M1, M2, M3,

M5, M6, M7

Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit

board.

AGND

—

Band-gap voltage output. This pin is capable of sourcing only small currents and driving limited

capacitive loads, as specified in the Recommended Operating Conditions table. This pin can be

left disconnected if not used.

BG

C3

F7

E7

O

I

Foreground calibration status output or device alarm output. Functionality is programmed through

CAL_STATUS_SEL. This pin can be left disconnected if not used.

CALSTAT

CALTRIG

Foreground calibration trigger input. This pin is only used if hardware calibration triggering is

selected in CAL_TRIG_EN, otherwise software triggering is performed using CAL_SOFT_TRIG.

Tie this pin to GND if not used.

Device (sampling) clock positive input. The clock signal is strongly recommended to be AC-

coupled to this input for best performance. In single-channel mode, the analog input signal is

sampled on both the rising and falling edges. In dual-channel mode, the analog signal is sampled

on the rising edge. This differential input has an internal untrimmed 100-Ωdifferential termination

and is self-biased to the optimal input common-mode voltage as long as DEVCLK_LVPECL_EN is

set to 0.

CLK+

F1

I

Device (sampling) clock negative input. TI strongly recommends using AC-coupling for best

performance.

G1

I

CLK–

High-speed serialized data output for channel A, lane 0, positive connection. This differential

output must be AC-coupled and must always be terminated with a 100-Ωdifferential termination

at the receiver. This pin can be left disconnected if not used, or connected to any voltage level

between GND (0V) and VD11 (1.1V) using 0 OHM to 1MOHM resistors.

DA0+

E12

O

High-speed serialized data output for channel A, lane 0, negative connection. This pin can be left

disconnected if not used, or connected to any voltage level between GND (0V) and VD11 (1.1V)

using 0 OHM to 1MOHM resistors.

F12

C12

D12

A10

A11

A8

O

DA0–

DA1+

DA1–

DA2+

DA2–

DA3+

DA3–

High-speed serialized data output for channel A, lane 1, positive connection. This differential

output must be AC-coupled and must always be terminated with a 100-Ωdifferential termination

at the receiver. This pin can be left disconnected if not used, or connected to any voltage level

between GND (0V) and VD11 (1.1V) using 0 OHM to 1MOHM resistors.

High-speed serialized data output for channel A, lane 1, negative connection. This pin can be left

disconnected if not used, or connected to any voltage level between GND (0V) and VD11 (1.1V)

using 0 OHM to 1MOHM resistors.

High-speed serialized-data output for channel A, lane 2, positive connection. This differential

output must be AC-coupled and must always be terminated with a 100-Ωdifferential termination

at the receiver. This pin can be left disconnected if not used, or connected to any voltage level

between GND (0V) and VD11 (1.1V) using 0 OHM to 1MOHM resistors.

High-speed serialized-data output for channel A, lane 2, negative connection. This pin can be left

disconnected if not used, or connected to any voltage level between GND (0V) and VD11 (1.1V)

using 0 OHM to 1MOHM resistors.

High-speed serialized-data output for channel A, lane 3, positive connection. This differential

output must be AC-coupled and must always be terminated with a 100-Ωdifferential termination

at the receiver. This pin can be left disconnected if not used, or connected to any voltage level

between GND (0V) and VD11 (1.1V) using 0 OHM to 1MOHM resistors.

High-speed serialized-data output for channel A, lane 3, negative connection. This pin can be left

disconnected if not used, or connected to any voltage level between GND (0V) and VD11 (1.1V)

using 0 OHM to 1MOHM resistors.

A9

4

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表5-1. Pin Functions (continued)

I/O

DESCRIPTION

NAME

NO.

High-speed serialized data output for channel A, lane 4, positive connection. This differential

output must be AC-coupled and must always be terminated with a 100-Ωdifferential termination

at the receiver. This pin can be left disconnected if not used, or connected to any voltage level

between GND (0V) and VD11 (1.1V) using 0 OHM to 1MOHM resistors.

DA4+

E11

O

High-speed serialized data output for channel A, lane 4, negative connection. This pin can be left

disconnected if not used, or connected to any voltage level between GND (0V) and VD11 (1.1V)

using 0 OHM to 1MOHM resistors.

F11

C11

D11

B10

B11

B8

O

DA4–

DA5+

DA5–

DA6+

DA6–

DA7+

High-speed serialized data output for channel A, lane 5, positive connection. This differential

output must be AC-coupled and must always be terminated with a 100-Ωdifferential termination

at the receiver. This pin can be left disconnected if not used, or connected to any voltage level

between GND (0V) and VD11 (1.1V) using 0 OHM to 1MOHM resistors.

High-speed serialized data output for channel A, lane 5, negative connection. This pin can be left

disconnected if not used, or connected to any voltage level between GND (0V) and VD11 (1.1V)

using 0 OHM to 1MOHM resistors.

High-speed serialized data output for channel A, lane 6, positive connection. This differential

output must be AC-coupled and must always be terminated with a 100-Ωdifferential termination

at the receiver. This pin can be left disconnected if not used, or connected to any voltage level

between GND (0V) and VD11 (1.1V) using 0 OHM to 1MOHM resistors.

High-speed serialized data output for channel A, lane 6, negative connection. This pin can be left

disconnected if not used, or connected to any voltage level between GND (0V) and VD11 (1.1V)

using 0 OHM to 1MOHM resistors.

High-speed serialized data output for channel A, lane 7, positive connection. This differential

output must be AC-coupled and must always be terminated with a 100-Ωdifferential termination

at the receiver. This pin can be left disconnected if not used, or connected to any voltage level

between GND (0V) and VD11 (1.1V) using 0 OHM to 1MOHM resistors.

High-speed serialized data output for channel A, lane 7, negative connection. This pin can be left

disconnected if not used, or connected to any voltage level between GND (0V) and VD11 (1.1V)

using 0 OHM to 1MOHM resistors.

B9

H12

G12

K12

J12

M10

M11

M8

O

DA7–

DB0+

DB0–

DB1+

DB1–

DB2+

DB2–

DB3+

DB3–

High-speed serialized data output for channel B, lane 0, positive connection. This differential

output must be AC-coupled and must always be terminated with a 100-Ωdifferential termination

at the receiver. This pin can be left disconnected if not used.

High-speed serialized data output for channel B, lane 0, negative connection. This pin can be left

disconnected if not used, or connected to any voltage level between GND (0V) and VD11 (1.1V)

using 0 OHM to 1MOHM resistors.

High-speed serialized data output for channel B, lane 1, positive connection. This differential

output must be AC-coupled and must always be terminated with a 100-Ωdifferential termination

at the receiver. This pin can be left disconnected if not used.

High-speed serialized data output for channel B, lane 1, negative connection. This pin can be left

disconnected if not used, or connected to any voltage level between GND (0V) and VD11 (1.1V)

using 0 OHM to 1MOHM resistors.

High-speed serialized data output for channel B, lane 2, positive connection. This differential

output must be AC-coupled and must always be terminated with a 100-Ωdifferential termination

at the receiver. This pin can be left disconnected if not used.

High-speed serialized data output for channel B, lane 2, negative connection. This pin can be left

disconnected if not used, or connected to any voltage level between GND (0V) and VD11 (1.1V)

using 0 OHM to 1MOHM resistors.

High-speed serialized data output for channel B, lane 3, positive connection. This differential

output must be AC-coupled and must always be terminated with a 100-Ωdifferential termination

at the receiver. This pin can be left disconnected if not used.

High-speed serialized data output for channel B, lane 3, negative connection. This pin can be left

disconnected if not used, or connected to any voltage level between GND (0V) and VD11 (1.1V)

using 0 OHM to 1MOHM resistors.

M9

High-speed serialized data output for channel B, lane 4, positive connection. This differential

output must be AC-coupled and must always be terminated with a 100-Ωdifferential termination

at the receiver. This pin can be left disconnected if not used, or connected to any voltage level

between GND (0V) and VD11 (1.1V) using 0 OHM to 1MOHM resistors.

DB4+

H11

O

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ADC12DJ5200SE

ZHCSOJ3A –MARCH 2023 –REVISED MAY 2023

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表5-1. Pin Functions (continued)

I/O

DESCRIPTION

NAME

NO.

High-speed serialized data output for channel B, lane 4, negative connection. This pin can be left

disconnected if not used, or connected to any voltage level between GND (0V) and VD11 (1.1V)

using 0 OHM to 1MOHM resistors.

G11

O

—

DB4–

High-speed serialized data output for channel B, lane 5, positive connection. This differential

output must be AC-coupled and must always be terminated with a 100-Ωdifferential termination

at the receiver. This pin can be left disconnected if not used, or connected to any voltage level

between GND (0V) and VD11 (1.1V) using 0 OHM to 1MOHM resistors.

DB5+

DB5–

DB6+

DB6–

DB7+

K11

J11

L10

L11

L8

High-speed serialized data output for channel B, lane 5, negative connection. This pin can be left

disconnected if not used, or connected to any voltage level between GND (0V) and VD11 (1.1V)

using 0 OHM to 1MOHM resistors.

High-speed serialized data output for channel B, lane 6, positive connection. This differential

output must be AC-coupled and must always be terminated with a 100-Ωdifferential termination

at the receiver. This pin can be left disconnected if not used, or connected to any voltage level

between GND (0V) and VD11 (1.1V) using 0 OHM to 1MOHM resistors.

High-speed serialized data output for channel B, lane 6, negative connection. This pin can be left

disconnected if not used, or connected to any voltage level between GND (0V) and VD11 (1.1V)

using 0 OHM to 1MOHM resistors.

High-speed serialized data output for channel B, lane 7, positive connection. This differential

output must be AC-coupled and must always be terminated with a 100-Ωdifferential termination

at the receiver. This pin can be left disconnected if not used, or connected to any voltage level

between GND (0V) and VD11 (1.1V) using 0 OHM to 1MOHM resistors.

High-speed serialized data output for channel B, lane 7, negative connection. This pin can be left

disconnected if not used, or connected to any voltage level between GND (0V) and VD11 (1.1V)

using 0 OHM to 1MOHM resistors.

L9

DB7–

A12, B12, D9,

D10, F9, F10,

G9, G10, J9,

J10, L12, M12

Digital supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit

board.

DGND

Channel A single ended analog input. INA is recommended for use in single channel mode for

optimal performance. The full-scale input voltage swing is determined by the FS_RANGE_A

register (see the Full-Scale Voltage (V_FS) Adjustment section). This input is AC coupled with a

nominal impedance of 50Ω. There is no DC connection to supply or ground. This pin can be left

disconnected if not used.

INA

INB

A4

I

Channel B single ended analog input. INA is recommended for use in single channel mode for

optimal performance. The full-scale input voltage swing is determined by the FS_RANGE_B

register (see the Full-Scale Voltage (V_FS) Adjustment section). This input is AC coupled with a

nominal impedance of 50Ω. There is no DC connection to supply or ground. This pin can be left

disconnected if not used.

M4

LSB of NCO selection control for DDC A. NCOA0 and NCOA1 select which NCO, of a possible

four NCOs, is used for digital mixing when using a complex output JMODE. The remaining

unselected NCOs continue to run to maintain phase coherency and can be swapped in by

changing the values of NCOA0 and NCOA1 (when CMODE = 1). This pin is an asynchronous

input. See the NCO Fast Frequency Hopping (FFH) and NCO Selection sections for more

information. Tie this pin to GND if not used.

NCOA0

NCOA1

NCOB0

C7

D7

K7

I

MSB of NCO selection control for DDC A. Tie this pin to GND if not used.

LSB of NCO selection control for DDC B. NCOB0 and NCOB1 select which NCO, of a possible

four NCOs, is used for digital mixing when using a complex output JMODE. The remaining

unselected NCOs continue to run to maintain phase coherency and can be swapped in by

changing the values of NCOB0 and NCOB1 (when CMODE = 1). This pin is an asynchronous

input. See the NCO Fast Frequency Hopping (FFH) and NCO Selection sections for more

information. Tie this pin to GND if not used.

NCOB1

ORA0

J7

I

MSB of NCO selection control for DDC B. Tie this pin to GND if not used.

Fast overrange detection status for channel A for the OVR_T0 threshold. When the analog input

exceeds the threshold programmed into OVR_T0, this status indicator goes high. The minimum

pulse duration is set by OVR_N. See the ADC Overrange Detection section for more information.

This pin can be left disconnected if not used.

C8

O

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表5-1. Pin Functions (continued)

I/O

DESCRIPTION

NAME

NO.

Fast overrange detection status for channel A for the OVR_T1 threshold. When the analog input

exceeds the threshold programmed into OVR_T1, this status indicator goes high. The minimum

pulse duration is set by OVR_N. See the ADC Overrange Detection section for more information.

This pin can be left disconnected if not used.

ORA1

D8

O

Fast overrange detection status for channel B for the OVR_T0 threshold. When the analog input

exceeds the threshold programmed into OVR_T0, this status indicator goes high. The minimum

pulse duration is set by OVR_N. See the ADC Overrange Detection section for more information.

This pin can be left disconnected if not used.

ORB0

ORB1

K8

J8

O

Fast overrange detection status for channel B for the OVR_T1 threshold. When the analog input

exceeds the threshold programmed into OVR_T1, this status indicator goes high. The minimum

pulse duration is set by OVR_N. See the ADC Overrange Detection section for more information.

This pin can be left disconnected if not used.

This pin disables all analog circuits and serializer outputs when set high for temperature diode

calibration or to reduce power consumption when the device is not being used. Tie this pin to GND

if not used.

PD

K6

F8

I

Serial interface clock. This pin functions as the serial-interface clock input that clocks the serial

programming data in and out. The Using the Serial Interface section describes the serial interface

in more detail. Supports 1.1-V and 1.8-V CMOS levels.

SCLK

Serial interface chip select active low input. The Using the Serial Interface section describes the

serial interface in more detail. Supports 1.1-V and 1.8-V CMOS levels. This pin has a 82-kΩ

pullup resistor to VD11.

SCS

SDI

E8

G8

H8

I

Serial interface data input. The Using the Serial Interface section describes the serial interface in

more detail. Supports 1.1-V and 1.8-V CMOS levels.

Serial interface data output. The Using the Serial Interface section describes the serial interface in

more detail. This pin is high impedance during normal device operation. This pin outputs 1.9-V

CMOS levels during serial interface read operations. This pin can be left disconnected if not used.

SDO

O

Single-ended JESD204C SYNC signal. This input is an active low input that is used to initialize

the JESD204C serial link in 8B/10B modes when SYNC_SEL is set to 0. The 64B/66B modes do

not use the SYNC signal for initialization, however it may be used for NCO synchronization. When

toggled low in 8B/10B modes this input initiates code group synchronization (see the Code Group

Synchronization (CGS) section). After code group synchronization, this input must be toggled high

to start the initial lane alignment sequence (see the Initial Lane Alignment Sequence (ILAS)

section). A differential SYNC signal can be used instead by setting SYNC_SEL to 1 and using

TMSTP± as a differential SYNC input. Tie this pin to GND if differential SYNC (TMSTP±) is used

as the JESD204C SYNC signal.

SYNCSE

C2

I

The SYSREF positive input is used to achieve synchronization and deterministic latency across

the JESD204C interface. This differential input (SYSREF+ to SYSREF–) has an internal

untrimmed 100-Ωdifferential termination and can be AC-coupled when SYSREF_LVPECL_EN is

set to 0. This input is self-biased when SYSREF_LVPECL_EN is set to 0. The termination

changes to 50 Ωto ground on each input pin (SYSREF+ and SYSREF–) and can be DC-

coupled when SYSREF_LVPECL_EN is set to 1. This input is not self-biased when

SYSREF_LVPECL_EN is set to 1 and must be biased externally to the input common-mode

voltage range provided in the Recommended Operating Conditions table.

SYSREF+

K1

I

L1

K2

K3

I

SYSREF negative input

SYSREF–

TDIODE+

TDIODE–

Temperature diode positive (anode) connection. An external temperature sensor can be

connected to TDIODE+ and TDIODE–to monitor the junction temperature of the device. This pin

can be left disconnected if not used.

Temperature diode negative (cathode) connection. This pin can be left disconnected if not used.

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表5-1. Pin Functions (continued)

I/O

DESCRIPTION

NAME

NO.

Timestamp input positive connection or differential JESD204C SYNC positive connection. This

input is a timestamp input, used to mark a specific sample, when TIMESTAMP_EN is set to 1.

This differential input is used as the JESD204C SYNC signal input when SYNC_SEL is set 1. This

input can be used as both a timestamp and differential SYNC input at the same time, allowing

feedback of the SYNC signal using the timestamp mechanism. TMSTP± uses active low signaling

when used as a JESD204C SYNC. For additional usage information, see the Timestamp section.

TMSTP_RECV_EN must be set to 1 to use this input. This differential input (TMSTP+ to

TMSTP–) has an internal untrimmed 100-Ωdifferential termination and can be AC-coupled when

TMSTP_LVPECL_EN is set to 0. The termination changes to 50 Ωto ground on each input pin

(TMSTP+ and TMSTP–) and can be DC coupled when TMSTP_LVPECL_EN is set to 1. This pin

is not self-biased and therefore must be externally biased for both AC- and DC-coupled

configurations. The common-mode voltage must be within the range provided in the

Recommended Operating Conditions table when both AC and DC coupled. This pin can be left

disconnected and disabled (TMSTP_RECV_EN = 0) if SYNCSE is used for JESD204C SYNC and

timestamp is not required.

TMSTP+

B1

I

Timestamp input positive connection or differential JESD204C SYNC negative connection. This

pin can be left disconnected and disabled (TMSTP_RECV_EN = 0) if SYNCSE is used for

JESD204C SYNC and timestamp is not required.

C1

I

TMSTP–

C5, D2, D3,

D5, E5, F5,

G5, H5, J2, J3,

J5, K5

1.1-V analog supply. Decouple with at least one 0.1 μF capacitor per ball as close to the ball as

possible (this may be on the backside of the board connecting to the vias if the board is not too

thick).

VA11

C4, D4, E2,

E3, E4, F4,

G4, H2, H3,

H4, J4, K4

1.9-V analog supply. Decouple with at least one 0.1 μF capacitor per ball as close to the ball as

possible (this may be on the backside of the board connecting to the vias if the board is not too

thick).

VA19

VD11

I

C9, C10, E9,

E10, G7, H7,

H9, H10, K9,

K10

1.1-V digital supply. Decouple with at least one 0.1 μF capacitor per ball as close to the ball as

possible (this may be on the backside of the board connecting to the vias if the board is not too

thick).

8

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6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

–0.3

–1.32

–0.1

MAX

2.35

1.32

0.1

UNIT

V

VA19⁽²⁾

VA11⁽²⁾

V_DD

Supply voltage range

VD11⁽³⁾

Voltage between VD11 and VA11

V_GND

Voltage between AGND and DGND

V

DA[7:0]+, DA[7:0]–, DB[7:0]+, DB[7:0]–,

TMSTP+, TMSTP–⁽³⁾

VD11 +

0.5⁽⁵⁾

–0.5

–3

VA11 + 0.5⁽⁴⁾

CLK+, CLK–, SYSREF+, SYSREF–⁽²⁾

BG, TDIODE+, TDIODE–⁽²⁾

INA, INB⁽²⁾

VA19 +

0.5⁽⁶⁾

V_PIN

Pin voltage range

V

3

CALSTAT, CALTRIG, NCOA0, NCOA1,

NCOB0, NCOB1, ORA0, ORA1, ORB0, ORB1,

PD, SCLK, SCS, SDI, SDO, SYNCSE ⁽²⁾

VA19 +

0.5⁽⁶⁾

–0.5

–25

I_MAX(ANY)

P_MAX(INx)

Peak input current (any input except INA, INB)

Peak RF input power (INA, INB)

25

mA

26.25

dBm

Z_S= 50 Ω, up to 21 days

Peak total input current (sum of absolute value of all currents forced in or out, not including power-

supply current)

I_MAX(ALL)

100

mA

T_j

Junction temperature

Storage temperature

150

°C

T_stg

–65

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated

under Recommended Operating Conditions . Exposure to absolute-maximum-rated conditions for extended periods may affect device

reliability.

(2) Measured to AGND.

(3) Measured to DGND.

(4) Maximum voltage not to exceed VA11 absolute maximum rating.

(5) Maximum voltage not to exceed VD11 absolute maximum rating.

(6) Maximum voltage not to exceed VA19 absolute maximum rating.

6.2 ESD Ratings

VALUE

±2000

±500

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

Charged device model (CDM), per ANSI/ESDA/JEDEC JS-002⁽²⁾

V_(ESD)

Electrostatic discharge

V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

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6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

1.8

NOM

MAX

UNIT

VA19, analog 1.9-V supply⁽²⁾

1.9

1.1

2.0

1.15

V_DD

Supply voltage range

VA11, analog 1.1-V supply⁽²⁾

VD11, digital 1.1-V supply⁽³⁾

INA, INB

1.05

V

1.1

ac coupled

0.3

0

0.55

V_CMI

Input common-mode voltage

CLK+, CLK–, SYSREF+, SYSREF–^{(2) (4)}

TMSTP+, TMSTP–^{(3) (5)}

V

0.3

CLK+ to CLK–, SYSREF+ to SYSREF–,

TMSTP+ to TMSTP–

V_ID

P_IN

Input voltage, peak-to-peak differential

0.4

1.0

2.0 V_PP-DIFF

Input power for fullscale at minimum

balun loss

f_IN= 4.5GHz, FS_RANGE_A =

FS_RANGE_B = 0xA000

-1.5

100

dBm

µA

I_{C_TD}

C_L

Temperature diode input current

BG maximum load capacitance

BG maximum output current

Input clock duty cycle

TDIODE+ to TDIODE–

50

100

70

pF

µA

%

I_O

DC

T_A

30

50

Operating free-air temperature

Operating junction temperature

85

°C

–40

T_J

125⁽¹⁾

(1) Prolonged use above junction temperature of 105°C may increase the device failure-in-time (FIT) rate.

(2) Measured to AGND.

(3) Measured to DGND.

(4) TI strongly recommends that CLK± be AC-coupled with DEVCLK_LVPECL_EN set to 0 to allow CLK± to self-bias to the optimal input

common-mode voltage for best performance. TI recommends AC-coupling for SYSREF± unless DC-coupling is required, in which

case, the LVPECL input mode must be used (SYSREF_LVPECL_EN = 1).

(5) TMSTP± does not have internal biasing that requires TMSTP± to be biased externally whether AC-coupled with TMSTP_LVPECL_EN

= 0 or DC-coupled with TMSTP_LVPECL_EN= 1.

6.4 Thermal Information

ADC12DJ5200SE

THERMAL METRIC⁽¹⁾

AAV or ZEG (FCBGA)

UNIT

144 PINS

23.9

0.8

R_θJA

Junction-to-ambient thermal resistance

°C/W

R_θJC(top)

R_θJB

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

8.4

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

0.23

8.4

ψ_JT

ψ_JB

R_θJC(bot)

n/a

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

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6.5 Electrical Characteristics: DC Specifications

typical values at T_A= 25°C, VA19 = 1.9 V, VA11 = 1.1 V, VD11 = 1.1 V, default full-scale voltage, f_IN= 2347 MHz, A_IN= –1

dBFS, f_CLK= 5.12 GHz, filtered 1-V_PPsine-wave clock, JMODE = 1, Dither enabled with default settings, VA11, VD11 and

VS11 noise suppression ON (EN_VA11_NOISE_SUPPR = EN_VD11_NOISE_SUPPR = EN_VS11_NOISE_SUPPR = 1),

and background calibration (unless otherwise noted); minimum and maximum values are at nominal supply voltages and

over the operating free-air temperature range provided in the Recommended Operating Conditions table

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

DC ACCURACY

Resolution

Resolution with no missing codes

12

Bits

ANALOG INPUTS (INA, INB)

CAL_OS = 0

CAL_OS = 1

±0.06

±0.02

%FSR

V_OFF

Offset error

Input offset voltage adjustment

range

Available offset correction range (see OS_CAL or

OADJ_x_INx)

V_{OFF_ADJ}

±6.75

%FSR

Foreground calibration at nominal temperature only

Foreground calibration at each temperature

2.18

-0.67

m%FSR/°

C

V_{OFF_DRIFT}

Offset drift

Foreground and FGOS calibration at each

temperature

0

TEMPERATURE DIODE CHARACTERISTICS (TDIODE+, TDIODE–)

Forced forward current of 100 µA. Offset voltage

(approximately 0.792 V at 0°C) varies with process

and must be measured for each part. Offset

measurement must be done with the device

unpowered or with the PD pin asserted to minimize

device self-heating.

Temperature diode voltage slope

mV/°C

ΔV_BE

–1.65

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6.5 Electrical Characteristics: DC Specifications (continued)

typical values at T_A= 25°C, VA19 = 1.9 V, VA11 = 1.1 V, VD11 = 1.1 V, default full-scale voltage, f_IN= 2347 MHz, A_IN= –1

dBFS, f_CLK= 5.12 GHz, filtered 1-V_PPsine-wave clock, JMODE = 1, Dither enabled with default settings, VA11, VD11 and

VS11 noise suppression ON (EN_VA11_NOISE_SUPPR = EN_VD11_NOISE_SUPPR = EN_VS11_NOISE_SUPPR = 1),

and background calibration (unless otherwise noted); minimum and maximum values are at nominal supply voltages and

over the operating free-air temperature range provided in the Recommended Operating Conditions table

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

BAND-GAP VOLTAGE OUTPUT (BG)

V_BG

Reference output voltage

Reference output temperature drift

1.1

V

I_L≤100 µA

V_{BG_DRIFT}

µV/°C

–64

CLOCK INPUTS (CLK+, CLK–, SYSREF+, SYSREF–, TMSTP+, TMSTP–)

Differential termination with DEVCLK_LVPECL_EN

= 0, SYSREF_LVPECL_EN = 0, and

TMSTP_LVPECL_EN = 0

100

50

Z_T

Internal termination

Ω

Single-ended termination to GND (per pin) with

DEVCLK_LVPECL_EN = 0, SYSREF_LVPECL_EN

= 0, and TMSTP_LVPECL_EN = 0

Self-biasing common-mode voltage for CLK± when

AC-coupled (DEVCLK_LVPECL_EN must be set to

0)

0.3

Self-biasing common-mode voltage for SYSREF±

when AC-coupled (SYSREF_LVPECL_EN must be

set to 0) and with receiver enabled

Input common-mode voltage, self-

biased

0.28

V_CM

V

(SYSREF_RECV_EN = 1)

Self-biasing common-mode voltage for SYSREF±

when AC-coupled (SYSREF_LVPECL_EN must be

set to 0) and with receiver disabled

(SYSREF_RECV_EN = 0)

C_{L_DIFF}

C_{L_SE}

Differential input capacitance

Single-ended input capacitance

Between positive and negative differential input pins

Each input to ground

0.04

0.5

pF

SERDES OUTPUTS (DA[7:0]+, DA[7:0]–, DB[7:0]+, DB[7:0]–)

Differential output voltage, peak-to-

peak

V_OD

550

600

650 mV_PP-DIFF

100-Ωload

V_CM

Output common-mode voltage

Differential output impedance

AC coupled

VD11 / 2

100

V

Z_DIFF

Ω

CMOS INTERFACE: SCLK, SDI, SDO, SCS, PD, NCOA0, NCOA1, NCOB0, NCOB1, CALSTAT, CALTRIG, ORA0, ORA1, ORB0, ORB1, SYNCSE

V_IH

V_IL

I_IH

High-level input voltage

Low-level input voltage

High-level input current

Low-level input current

Input capacitance

required input voltage

0.7

V

0.45

40

µA

pF

V

I_IL

–40

C_I

3.4

V_OH

V_OL

High-level output voltage

Low-level output voltage

1.65

I_LOAD= –400 µA

I_LOAD= 400 µA

150

mV

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6.6 Electrical Characteristics: Power Consumption

typical values at T_A= 25°C, VA19 = 1.9 V, VA11 = 1.1 V, VD11 = 1.1 V, default full-scale voltage, f_IN= 2347 MHz, A_IN= –1

dBFS, f_CLK= 5.12 GHz, filtered 1-V_PPsine-wave clock, JMODE = 1, Dither enabled with default settings, VA11, VD11 and

VS11 noise suppression ON (EN_VA11_NOISE_SUPPR = EN_VD11_NOISE_SUPPR = EN_VS11_NOISE_SUPPR = 1),

and background calibration (unless otherwise noted); minimum and maximum values are at nominal supply voltages and

over the operating free-air temperature range provided in the Recommended Operating Conditions table

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

mA

W

I_VA19

I_VA11

I_VD11

P_DIS

I_VA19

I_VA11

I_VD11

P_DIS

I_VA19

I_VA11

I_VD11

P_DIS

I_VA19

I_VA11

I_VD11

P_DIS

I_VA19

I_VA11

I_VD11

P_DIS

I_VA19

I_VA11

I_VD11

P_DIS

I_VA19

I_VA11

I_VD11

P_DIS

1.9-V analog supply current

1.1-V analog supply current

1.1-V digital supply current

Power dissipation

934

Power mode 1: JMODE 1 (single-channel

mode, 16 lanes, 8B/10B encoding, DDC

bypassed), foreground calibration

845

1170

4.01

935

1.9-V analog supply current

1.1-V analog supply current

1.1-V digital supply current

Power dissipation

1050

950

mA

W

Power mode 2: JMODE 30 (single-

channel mode, 8 lanes, 64B/66B

encoding, DDC bypassed), foreground

calibration

850

1195

4.0

1450

4.6

1.9-V analog supply current

1.1-V analog supply current

1.1-V digital supply current

Power dissipation

1242

1030

1265

4.90

1320

1030

1250

5.03

936

mA

W

Power mode 3: JMODE 1 (single-channel

mode, 16 lanes, 8B/10B encoding, DDC

bypassed), background calibration

1.9-V analog supply current

1.1-V analog supply current

1.1-V digital supply current

Power dissipation

mA

W

Power mode 4: JMODE 3 (dual-channel

mode, 16 lanes, 8B/10B encoding, DDC

bypassed), background calibration

1.9-V analog supply current

1.1-V analog supply current

1.1-V digital supply current

Power dissipation

mA

W

Power mode 5: JMODE 22 (single-

channel mode, 8 lanes, 8B/10B encoding,

4x decimation), foreground calibration

845

2350

5.3

1.9-V analog supply current

1.1-V analog supply current

1.1-V digital supply current

Power dissipation

1014

845

mA

W

Power mode 6: JMODE 11 (dual-channel

mode, 8 lanes, 8B/10B encoding, 4x

decimation), foreground calibration

2260

5.34

44

1.9-V analog supply current

1.1-V analog supply current

1.1-V digital supply current

Power dissipation

mA

W

27

Power mode 7: PD pin held high, clock

disabled

33

0.15

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6.7 Electrical Characteristics: AC Specifications (Dual-Channel Mode)

typical values at T_A= 25°C, VA19 = 1.9 V, VA11 = 1.1 V, VD11 = 1.1 V, default full-scale voltage, f_IN= 2347 MHz, A_IN= –1

dBFS, f_CLK= 5.12 GHz, filtered 1-V_PPsine-wave clock, JMODE = 3, Dither enabled with default settings, VA11, VD11 and

VS11 noise suppression ON (EN_VA11_NOISE_SUPPR = EN_VD11_NOISE_SUPPR = EN_VS11_NOISE_SUPPR = 1),

and background calibration (unless otherwise noted); minimum and maximum values are at nominal supply voltages and

over the operating free-air temperature range provided in the Recommended Operating Conditions table

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Low frequency

High frequency

Low frequency

High frequency

3.4

BW_-1dB

Input bandwidth -1dB range

5.9

GHz

2.0

BW_-3dB

P_FS

Input bandwidth -3dB range

Fullscale Input Power

6.5

f_IN= 4.5GHz, FS_RANGE_A = FS_RANGE_B = 0xA000

Aggressor = 3 GHz, –1 dBFS

-1.25

–73

–62

dBm

dB

Channel-to-channel

crosstalk

XTALK

dB

Aggressor = 6 GHz, –1 dBFS

Errors/

sample

CER

Code error rate

Maximum CER, does not include JESD204C interface BER

10^–18

2.8

DC input noise standard

deviation

No input, foreground calibration, excludes DC offset, includes fixed

interleaving spur (f_S/ 2 spur)

NOISE_DC

LSB

Maximum full-scale voltage (FS_RANGE_A = FS_RANGE_B =

0xFFFF), A_IN= –20 dBFS

–150.6

–149.0

23.4

Noise spectral density,

excludes fixed interleaving

spur (f_S/ 2 spur)

dBFS/

Hz

NSD

NF

Default full-scale voltage (FS_RANGE_A = FS_RANGE_B =

0xA000), A_IN= –20 dBFS

Maximum full-scale voltage (FS_RANGE_A = FS_RANGE_B =

0xFFFF), A_IN= –20 dBFS

dB

Noise figure, Z_S= 50 Ω

Default full-scale voltage (FS_RANGE_A = FS_RANGE_B =

0xA000), A_IN= –20 dBFS

25

50

53.5

53.9

54.8

A_IN= –1 dBFS

A_IN= –3 dBFS

f_IN= 2397 MHz

A_IN= –12 dBFS

A_IN= –3 dBFS, FS_RANGE_A

= FS_RANGE_B = 0xFFFF

55.1

Signal-to-noise ratio,

excluding DC, HD2 to

HD9, f_S/ 2, f_S/ 2 –f_IN

52.0

53.0

54.7

50.5

51.7

54.4

52.8

53.6

54.6

A_IN= –1 dBFS

SNR

dBFS

,

f_IN= 4197 MHz

f_IN= 5997 MHz

A_IN= –3 dBFS

A_IN= –12 dBFS

A_IN= –1 dBFS

A_IN= –3 dBFS

A_IN= –12 dBFS

A_IN= –1 dBFS

A_IN= –3 dBFS

A_IN= –12 dBFS

50

f_IN= 2397 MHz

A_IN= –3 dBFS, VFS_RANGE_A

= FS_RANGE_B = 0xFFFF

54.6

Signal-to-noise and

distortion ratio, excluding DC

and f_S/ 2 fixed spurs

51.0

52.4

54.4

47.9

50.7

54.2

A_IN= –1 dBFS

A_IN= –3 dBFS

A_IN= –12 dBFS

A_IN= –1 dBFS

A_IN= –3 dBFS

A_IN= –12 dBFS

SINAD

dBFS

f_IN= 4197 MHz

f_IN= 5997 MHz

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6.7 Electrical Characteristics: AC Specifications (Dual-Channel Mode) (continued)

typical values at T_A= 25°C, VA19 = 1.9 V, VA11 = 1.1 V, VD11 = 1.1 V, default full-scale voltage, f_IN= 2347 MHz, A_IN= –1

dBFS, f_CLK= 5.12 GHz, filtered 1-V_PPsine-wave clock, JMODE = 3, Dither enabled with default settings, VA11, VD11 and

VS11 noise suppression ON (EN_VA11_NOISE_SUPPR = EN_VD11_NOISE_SUPPR = EN_VS11_NOISE_SUPPR = 1),

and background calibration (unless otherwise noted); minimum and maximum values are at nominal supply voltages and

over the operating free-air temperature range provided in the Recommended Operating Conditions table

PARAMETER

TEST CONDITIONS

MIN

TYP

8.5

8.6

8.8

MAX

UNIT

7.88

A_IN= –1 dBFS

A_IN= –3 dBFS

f_IN= 2397 MHz

A_IN= –12 dBFS

A_IN= –3 dBFS, FS_RANGE_A

= FS_RANGE_B = 0xFFFF

8.8

Effective number of bits,

excluding DC and f_S/ 2 fixed

spurs

8.2

8.4

7.7

8.1

8.7

65

A_IN= –1 dBFS

A_IN= –3 dBFS

A_IN= –12 dBFS

A_IN= –1 dBFS

A_IN= –3 dBFS

A_IN= –12 dBFS

A_IN= –1 dBFS

A_IN= –3 dBFS

A_IN= –12 dBFS

ENOB

SFDR

HD2

bits

f_IN= 4197 MHz

f_IN= 5997 MHz

53

67

f_IN= 2397 MHz

73

A_IN= –3 dBFS, FS_RANGE_A

= FS_RANGE_B = 0xFFFF

67

Spurious-free dynamic

60

64

A_IN= –1 dBFS

A_IN= –3 dBFS

A_IN= –12 dBFS

A_IN= –1 dBFS

A_IN= –3 dBFS

A_IN= –12 dBFS

A_IN= –1 dBFS

A_IN= –3 dBFS

A_IN= –12 dBFS

range, excluding DC and f_S

2 fixed spurs

/

dBFS

f_IN= 4197 MHz

f_IN= 5997 MHz

71

53

61

70

-56

–66

–73

–82

f_IN= 2397 MHz

A_IN= –3 dBFS, FS_RANGE_A

= FS_RANGE_B = 0xFFFF

–70

2nd-order harmonic

distortion

A_IN= –1 dBFS

A_IN= –3 dBFS

A_IN= –12 dBFS

A_IN= –1 dBFS

A_IN= –3 dBFS

A_IN= –12 dBFS

A_IN= –1 dBFS

A_IN= –3 dBFS

A_IN= –12 dBFS

–70

–72

–85

–62

–65

–80

–74

–87

f_IN= 4197 MHz

f_IN= 5997 MHz

-60

f_IN= 2397 MHz

A_IN= –3 dBFS, FS_RANGE_A

= FS_RANGE_B = 0xFFFF

–75

A_IN= –1 dBFS

A_IN= –3 dBFS

A_IN= –12 dBFS

A_IN= –1 dBFS

A_IN= –3 dBFS

A_IN= –12 dBFS

–64

–67

–77

–53

–62

–80

HD3

3rd-order harmonic distortion

f_IN= 4197 MHz

f_IN= 5997 MHz

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6.7 Electrical Characteristics: AC Specifications (Dual-Channel Mode) (continued)

typical values at T_A= 25°C, VA19 = 1.9 V, VA11 = 1.1 V, VD11 = 1.1 V, default full-scale voltage, f_IN= 2347 MHz, A_IN= –1

dBFS, f_CLK= 5.12 GHz, filtered 1-V_PPsine-wave clock, JMODE = 3, Dither enabled with default settings, VA11, VD11 and

VS11 noise suppression ON (EN_VA11_NOISE_SUPPR = EN_VD11_NOISE_SUPPR = EN_VS11_NOISE_SUPPR = 1),

and background calibration (unless otherwise noted); minimum and maximum values are at nominal supply voltages and

over the operating free-air temperature range provided in the Recommended Operating Conditions table

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

f_S/ 2 fixed interleaving spur,

independent of input signal

f_S/ 2

-55

dBFS

A_IN= –20 dBFS

–72

-53

A_IN= –1 dBFS

A_IN= –3 dBFS

A_IN= –12 dBFS

–67

–68

–75

f_IN= 2397 MHz

A_IN= –3 dBFS, FS_RANGE_A

= FS_RANGE_B = 0xFFFF

–69

f_S/ 2 –f_INinput signal

dependent interleaving spur

A_IN= –1 dBFS

A_IN= –3 dBFS

A_IN= –12 dBFS

A_IN= –1 dBFS

A_IN= –3 dBFS

A_IN= –12 dBFS

A_IN= –1 dBFS

A_IN= –3 dBFS

A_IN= –12 dBFS

–62

–65

–73

–62

–64

–71

–75

–80

dBFS

f_S/ 2 –f_IN

f_IN= 4197 MHz

f_IN= 5997 MHz

-62

f_IN= 2397 MHz

A_IN= –3 dBFS, FS_RANGE_A

= FS_RANGE_B = 0xFFFF

–75

Worst spur, excluding DC,

HD2, HD3, f_S/ 2 and f_S/ 2 -

f_INspurs

A_IN= –1 dBFS

–67

–74

–75

–64

–72

–74

–72

–77

–89

SPUR

f_IN= 4197 MHz

f_IN= 5997 MHz

A_IN= –3 dBFS

A_IN= –12 dBFS

A_IN= –1 dBFS

A_IN= –3 dBFS

A_IN= –12 dBFS

A_IN= –7 dBFS per tone

A_IN= –9 dBFS per tone

A_IN= –18 dBFS per tone

f₁= 2393 MHz,

f₂= 2403 MHz

A_IN= –9 dBFS per tone, FS_RANGE_A

= FS_RANGE_B = 0xFFFF

–74

3rd-order intermodulation

distortion

A_IN= –7 dBFS per tone

A_IN= –9 dBFS per tone

A_IN= –18 dBFS per tone

A_IN= –7 dBFS per tone

A_IN= –9 dBFS per tone

A_IN= –18 dBFS per tone

–70

–76

–81

–55

–61

–84

IMD3

f₁= 4193 MHz,

f₂= 4203 MHz

f₁= 5993 MHz,

f₂= 6003 MHz

English Data Sheet: SLVSGH5

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6.8 Electrical Characteristics: AC Specifications (Single-Channel Mode)

typical values at T_A= 25°C, VA19 = 1.9 V, VA11 = 1.1 V, VD11 = 1.1 V, default full-scale voltage, input signal applied to INA,

f_IN= 2347 MHz, A_IN= –1 dBFS, f_CLK= 5.12 GHz, filtered 1-V_PPsine-wave clock, JMODE = 1, Dither enabled with default

settings, VA11, VD11 and VS11 noise suppression ON (EN_VA11_NOISE_SUPPR = EN_VD11_NOISE_SUPPR =

EN_VS11_NOISE_SUPPR = 1), and background calibration (unless otherwise noted); minimum and maximum values are at

nominal supply voltages and over the operating free-air temperature range provided in the Recommended Operating

Conditions table

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

GHz

dBm

Low frequency

High frequency

Low frequency

High frequency

3.0

BW_-1dB

BW_-3dB

Input bandwidth -1dB range

5.8

2.0

Input bandwidth -3dB range

6.3

P_FS

Fullscale Input Power

Code error rate

f_IN= 4.5GHz, FS_RANGE_A = 0xA000

-1.25

Errors/

sample

CER

Maximum CER, does not include JESD204C interface BER

10^–18

2.8

DC input noise standard

deviation

No input, foreground calibration, excludes DC offset, includes fixed

interleaving spurs (f_S/ 2 and f_S/ 4 spurs), OS_CAL enabled

NOISE_DC

NSD

LSB

Maximum full-scale voltage (FS_RANGE_A = 0xFFFF), A_IN= –20

dBFS

–153.1

–151.5

20.9

Noise spectral density,

excludes fixed interleaving

spurs (f_S/ 2 and f_S/ 4 spur)

dBFS/

Hz

Default full-scale voltage (FS_RANGE_A = 0xA000), A_IN= –20

dBFS

Maximum full-scale voltage (FS_RANGE_A = 0xFFFF), A_IN= –20

dBFS

NF

dB

Noise figure, Z_S= 50 Ω

Default full-scale voltage (FS_RANGE_A = 0xA000), A_IN= –20

dBFS

22.5

50

53.5

54

A_IN= –1 dBFS

A_IN= –3 dBFS

f_IN= 2397 MHz

54.7

55.1

52.1

53.0

54.6

50.6

51.8

54.4

50.7

52.0

54.1

52.6

49.0

50.8

54.7

47.2

49.6

53.6

A_IN= –12 dBFS

A_IN= –3 dBFS, FS_RANGE_A = 0xFFFF

A_IN= –1 dBFS

Signal-to-noise ratio,

excluding DC, HD2 to

HD9, f_S/ 2, f_S/ 4_,f_S/ 2 –

f_IN,f_S/ 4 ± f_IN

SNR

dBFS

f_IN= 4197 MHz

f_IN= 5997 MHz

A_IN= –3 dBFS

A_IN= –12 dBFS

A_IN= –1 dBFS

A_IN= –3 dBFS

A_IN= –12 dBFS

A_IN= –1 dBFS

A_IN= –3 dBFS

f_IN= 2397 MHz

A_IN= –12 dBFS

A_IN= –3 dBFS, FS_RANGE_A = 0xFFFF

A_IN= –1 dBFS

Signal-to-noise and

distortion ratio, excluding DC

and f_S/ 2 fixed spurs

SINAD

dBFS

f_IN= 4197 MHz

f_IN= 5997 MHz

A_IN= –3 dBFS

A_IN= –12 dBFS

A_IN= –1 dBFS

A_IN= –3 dBFS

A_IN= –12 dBFS

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typical values at T_A= 25°C, VA19 = 1.9 V, VA11 = 1.1 V, VD11 = 1.1 V, default full-scale voltage, input signal applied to INA,

f_IN= 2347 MHz, A_IN= –1 dBFS, f_CLK= 5.12 GHz, filtered 1-V_PPsine-wave clock, JMODE = 1, Dither enabled with default

settings, VA11, VD11 and VS11 noise suppression ON (EN_VA11_NOISE_SUPPR = EN_VD11_NOISE_SUPPR =

EN_VS11_NOISE_SUPPR = 1), and background calibration (unless otherwise noted); minimum and maximum values are at

nominal supply voltages and over the operating free-air temperature range provided in the Recommended Operating

Conditions table

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

8.2

A_IN= –1 dBFS

8.3

A_IN= –3 dBFS

f_IN= 2397 MHz

8.7

A_IN= –12 dBFS

8.5

A_IN= –3 dBFS, FS_RANGE_A = 0xFFFF

A_IN= –1 dBFS

Effective number of bits,

excluding DC and f_S/ 2 fixed

spurs

7.9

ENOB

SFDR

HD2

bits

f_IN= 4197 MHz

f_IN= 5997 MHz

8.2

A_IN= –3 dBFS

8.6

A_IN= –12 dBFS

7.6

A_IN= –1 dBFS

8.0

A_IN= –3 dBFS

8.6

A_IN= –12 dBFS

56

A_IN= –1 dBFS

59

A_IN= –3 dBFS

f_IN= 2397 MHz

68

A_IN= –12 dBFS

59

A_IN= –3 dBFS, FS_RANGE_A = 0xFFFF

A_IN= –1 dBFS

Spurious free dynamic

range, excluding DC, f_S/ 4

and f_S/ 2 fixed spurs

54

dBFS

f_IN= 4197 MHz

f_IN= 5997 MHz

57

A_IN= –3 dBFS

66

A_IN= –12 dBFS

53

A_IN= –1 dBFS

57

A_IN= –3 dBFS

66

A_IN= –12 dBFS

-59

A_IN= –1 dBFS

–66

–73

–84

–69

–71

–75

–84

–66

–70

–83

–72

–77

–88

–75

–62

–68

–78

–54

–63

–80

A_IN= –3 dBFS

f_IN= 2397 MHz

A_IN= –12 dBFS

A_IN= –3 dBFS, FS_RANGE_A = 0xFFFF

A_IN= –1 dBFS

2nd-order harmonic

distortion

f_IN= 4197 MHz

f_IN= 5997 MHz

A_IN= –3 dBFS

A_IN= –12 dBFS

A_IN= –1 dBFS

A_IN= –3 dBFS

A_IN= –12 dBFS

-58

A_IN= –1 dBFS

A_IN= –3 dBFS

f_IN= 2397 MHz

A_IN= –12 dBFS

A_IN= –3 dBFS, FS_RANGE_A = 0xFFFF

A_IN= –1 dBFS

HD3

3rd-order harmonic distortion

f_IN= 4197 MHz

f_IN= 5997 MHz

A_IN= –3 dBFS

A_IN= –12 dBFS

A_IN= –1 dBFS

A_IN= –3 dBFS

A_IN= –12 dBFS

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typical values at T_A= 25°C, VA19 = 1.9 V, VA11 = 1.1 V, VD11 = 1.1 V, default full-scale voltage, input signal applied to INA,

f_IN= 2347 MHz, A_IN= –1 dBFS, f_CLK= 5.12 GHz, filtered 1-V_PPsine-wave clock, JMODE = 1, Dither enabled with default

settings, VA11, VD11 and VS11 noise suppression ON (EN_VA11_NOISE_SUPPR = EN_VD11_NOISE_SUPPR =

EN_VS11_NOISE_SUPPR = 1), and background calibration (unless otherwise noted); minimum and maximum values are at

nominal supply voltages and over the operating free-air temperature range provided in the Recommended Operating

Conditions table

PARAMETER

TEST CONDITIONS

MIN

TYP

–58

–59

–69

–59

–55

–58

–66

–55

–57

–68

–66

–67

–77

–68

–64

–65

–77

–62

–64

–72

–55

–73

MAX

UNIT

A_IN= –1 dBFS

A_IN= –3 dBFS

f_IN= 2397 MHz

A_IN= –12 dBFS

A_IN= –3 dBFS, FS_RANGE_A = 0xFFFF

A_IN= –1 dBFS

f_S/ 2 –f_INinput signal

dependent interleaving spur

dBFS

f_S/ 2 –f_IN

f_IN= 4197 MHz

f_IN= 5997 MHz

A_IN= –3 dBFS

A_IN= –12 dBFS

A_IN= –1 dBFS

A_IN= –3 dBFS

A_IN= –12 dBFS

-54

A_IN= –1 dBFS

A_IN= –3 dBFS

f_IN= 2397 MHz

A_IN= –12 dBFS

A_IN= –3 dBFS, FS_RANGE_A = 0xFFFF

A_IN= –1 dBFS

f_S/ 4 ± f_INinput signal

dependent interleaving spur

f_S/ 4 ± f_IN

dBFS

f_IN= 4197 MHz

f_IN= 5997 MHz

A_IN= –3 dBFS

A_IN= –12 dBFS

A_IN= –1 dBFS

A_IN= –3 dBFS

A_IN= –12 dBFS

A_IN= –20 dBFS, OS_CAL disabled

A_IN= –20 dBFS, OS_CAL enabled

f_S/ 2 fixed interleaving spur,

independent of input signal

f_S/ 2

f_S/ 4

dBFS

f_S/ 4 fixed interleaving spur,

independent of input signal

-55

-62

A_IN= –20 dBFS

–69

A_IN= –1 dBFS

–74

–75

–77

–75

–68

–71

–73

–67

–74

–76

A_IN= –3 dBFS

f_IN= 2397 MHz

A_IN= –12 dBFS

A_IN= –3 dBFS, FS_RANGE_A = 0xFFFF

Worst spur, excluding DC,

HD2, HD3, f_S/ 2, f_S/ 4, f_S/ 2

- f_IN, and f_S/ 4 ± f_IN

A_IN= –1 dBFS

A_IN= –3 dBFS

A_IN= –12 dBFS

A_IN= –1 dBFS

A_IN= –3 dBFS

A_IN= –12 dBFS

SPUR

dBFS

f_IN= 4197 MHz

f_IN= 5997 MHz

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typical values at T_A= 25°C, VA19 = 1.9 V, VA11 = 1.1 V, VD11 = 1.1 V, default full-scale voltage, input signal applied to INA,

f_IN= 2347 MHz, A_IN= –1 dBFS, f_CLK= 5.12 GHz, filtered 1-V_PPsine-wave clock, JMODE = 1, Dither enabled with default

settings, VA11, VD11 and VS11 noise suppression ON (EN_VA11_NOISE_SUPPR = EN_VD11_NOISE_SUPPR =

EN_VS11_NOISE_SUPPR = 1), and background calibration (unless otherwise noted); minimum and maximum values are at

nominal supply voltages and over the operating free-air temperature range provided in the Recommended Operating

Conditions table

PARAMETER

TEST CONDITIONS

MIN

TYP

–73

–78

–92

MAX

UNIT

dBFS

A_IN= –7 dBFS per tone

A_IN= –9 dBFS per tone

A_IN= –18 dBFS per tone

f₁= 2393 MHz,

f₂= 2403 MHz

A_IN= –9 dBFS per tone, FS_RANGE_A =

0xFFFF

dBFS

–75

3rd-order intermodulation

distortion

A_IN= –7 dBFS per tone

A_IN= –9 dBFS per tone

A_IN= –18 dBFS per tone

A_IN= –7 dBFS per tone

A_IN= –9 dBFS per tone

A_IN= –18 dBFS per tone

–70

–77

–81

–57

–64

–84

IMD3

f₁= 4193 MHz,

f₂= 4203 MHz

dBFS

f₁= 5993 MHz,

f₂= 6003 MHz

English Data Sheet: SLVSGH5

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6.9 Timing Requirements

typical values at T_A= 25°C, VA19 = 1.9 V, VA11 = 1.1 V, VD11 = 1.1 V, default full-scale voltage, f_IN= 2347 MHz, A_IN= –1

dBFS, f_CLK= 5.12 GHz, filtered 1-V_PPsine-wave clock, JMODE = 1, Dither enabled with default settings, VA11, VD11 and

VS11 noise suppression ON (EN_VA11_NOISE_SUPPR = EN_VD11_NOISE_SUPPR = EN_VS11_NOISE_SUPPR = 1),

and background calibration (unless otherwise noted); minimum and maximum values are at nominal supply voltages and

over the operating free-air temperature range provided in the Recommended Operating Conditions table

MIN

NOM

MAX

UNIT

DEVICE (SAMPLING) CLOCK (CLK+, CLK–)

f_CLK

Input clock frequency (CLK±), both single-channel and dual-channel modes⁽¹⁾

t_CLK

Input clock period (CLK±), both single-channel and dual-channel modes⁽¹⁾

SYSREF (SYSREF+, SYSREF–)

800

5200

1250

MHz

ps

192.3

Width of invalid SYSREF capture region of CLK± period, indicating setup or hold time

t_INV(SYSREF)

t_INV(TEMP)

t_INV(VA11)

48

0.02

ps

violation, as measured by SYSREF_POS status register, SYSREF_ZOOM = 1⁽³⁾

Drift of invalid SYSREF capture region over temperature, positive number indicates a

shift toward MSB of SYSREF_POS register, SYSREF_ZOOM = 1

ps/°C

ps/mV

Drift of invalid SYSREF capture region over VA11 supply voltage, positive number

indicates a shift toward MSB of SYSREF_POS register, SYSREF_ZOOM = 1

-0.03

SYSREF_ZOOM = 0

Delay of SYSREF_POS LSB⁽⁴⁾

39

24

t_STEP(SP)

ps

SYSREF_ZOOM = 1

Minimum SYSREF± assertion duration with SYSREF Windowing after SYSREF± rising

edge event

t_{(PH_SYS)}

t_{(PL_SYS)}

5*T_CLK+4.5

ns

Minimum SYSREF± de-assertion duration with SYSREF Windowing after SYSREF±

falling edge event

JESD204B SYNC TIMING (SYNCSE OR TMSTP±)

JMODE = 10, 21, 23

19

JMODE = 11, 14, 22, 24,

61

10

JMODE = 12, 15, 16, 25,

26, 27, 56, 57, 58, 62, 63,

66, 67, 69, 70

18

23

17

Minimum hold time from multiframe or extended

multiblock boundary (SYSREF rising edge captured high)

to de-assertion of JESD204C SYNC signal (SYNCSE if

SYNC_SEL = 0 or TMSTP± if SYNC_SEL = 1) for NCO

synchronization (NCO_SYNC_ILA = 1)⁽²⁾

t_CLK

cycles

t_H(SYNCSE)

JMODE = 13

JMODE = 36, 37, 38, 52,

53, 54, 55, 59, 60, 65, 68,

71

JMODE = 39

21

9

JMODE = 46, 47, 48, 49,

64

JMODE = 10, 21, 23

–2

7

JMODE = 11, 14, 22, 24,

61

JMODE = 12, 15, 16, 25,

26, 27, 56, 57, 58, 62, 63,

66, 67, 69, 70

–1

–6

0

Minimum setup time from de-assertion of JESD204C

SYNC signal (SYNCSE if SYNC_SEL = 0 or TMSTP± if

SYNC_SEL = 1) to multiframe or extended multiblock

boundary (SYSREF rising edge captured high) for NCO

synchronization (NCO_SYNC_ILA = 1)⁽²⁾

t_CLK

cycles

t_SU(SYNCSE)

JMODE = 13

JMODE = 36, 37, 38, 52,

53, 54, 55, 59, 60, 65, 68,

71

JMODE = 39

–4

8

JMODE = 46, 47, 48, 49,

64

t_(SYNCSE)

SYNCSE minimum assertion time to trigger link resynchronization

4

Frames

SERIAL PROGRAMMING INTERFACE (SCLK, SDI, SCS)

f_CLK(SCLK)

t_(PH)

Serial clock frequency

15.625

MHz

ns

Serial clock high value pulse duration

Serial clock low value pulse duration

Setup time from SCS to rising edge of SCLK

Hold time from rising edge of SCLK to SCS

32

30

t_(PL)

ns

t_SU(SCS)

t_H(SCS)

ns

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6.9 Timing Requirements (continued)

typical values at T_A= 25°C, VA19 = 1.9 V, VA11 = 1.1 V, VD11 = 1.1 V, default full-scale voltage, f_IN= 2347 MHz, A_IN= –1

dBFS, f_CLK= 5.12 GHz, filtered 1-V_PPsine-wave clock, JMODE = 1, Dither enabled with default settings, VA11, VD11 and

VS11 noise suppression ON (EN_VA11_NOISE_SUPPR = EN_VD11_NOISE_SUPPR = EN_VS11_NOISE_SUPPR = 1),

and background calibration (unless otherwise noted); minimum and maximum values are at nominal supply voltages and

over the operating free-air temperature range provided in the Recommended Operating Conditions table

MIN

25

3

NOM

MAX

UNIT

t_SU(SDI)

t_H(SDI)

Setup time from SDI to rising edge of SCLK

Hold time from rising edge of SCLK to SDI

ns

(1) Unless functionally limited to a smaller range in the ADC12DJ5200SE Operating Modes table based on programmed JMODE.

(2) This parameter only applies to JMODE settings that use 8B/10B encoding or settings that use 64B/66B encoding and 4x or 8x

decimation. SYNC is not used for 64B/66B encoding modes unless the DDC block and NCOs are used and require synchronization.

(3) Use SYSREF_POS to select an optimal SYSREF_SEL value for the SYSREF capture, see the SYSREF Position Detector and

Sampling Position Selection (SYSREF Windowing) section for more information on SYSREF windowing. The invalid region, specified

by t_INV(SYSREF), indicates the portion of the CLK± period(t_CLK), as measured by SYSREF_SEL, that may result in a setup and hold

violation. Verify that the timing skew between SYSREF± and CLK± over system operating conditions from the nominal conditions (that

used to find optimal SYSREF_SEL) does not result in the invalid region occurring at the selected SYSREF_SEL position in

SYSREF_POS, otherwise a temperature dependent SYSREF_SEL selection may be needed to track the skew between CLK± and

SYSREF±.

(4) It is recommended to use SYSREF_ZOOM = 0 below f_CLK= 3GHz and SYSREF_ZOOM = 1 above f_CLK= 3GHz

English Data Sheet: SLVSGH5

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6.10 Switching Characteristics

typical values at T_A= 25°C, VA19 = 1.9 V, VA11 = 1.1 V, VD11 = 1.1 V, default full-scale voltage, f_IN= 2347 MHz, A_IN= –1

dBFS, f_CLK= 5.12 GHz, filtered 1-V_PPsine-wave clock, JMODE = 1, Dither enabled with default settings, VA11, VD11 and

VS11 noise suppression ON (EN_VA11_NOISE_SUPPR = EN_VD11_NOISE_SUPPR = EN_VS11_NOISE_SUPPR = 1),

and background calibration (unless otherwise noted); minimum and maximum values are at nominal supply voltages and

over the operating free-air temperature range provided in the Recommended Operating Conditions table

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

DEVICE (SAMPLING) CLOCK (CLK+, CLK–)

Sampling (aperture) delay from the CLK±

rising edge (dual-channel mode) or rising

and falling edge (single-channel mode) to

sampling instant

TAD_COARSE = 0x00, TAD_FINE =

0x00, and TAD_INV = 0

t_AD

360

289

ps

Coarse adjustment (TAD_COARSE =

0xFF)

Maximum t_ADadjust programmable delay,

t_TAD(MAX)

not including clock inversion (TAD_INV = 0)

Fine adjustment (TAD_FINE = 0xFF)

Coarse adjustment (TAD_COARSE)

Fine adjustment (TAD_FINE)

4.9

1.13

19

ps

fs

t_TAD(STEP)

t_ADadjust programmable delay step size

Minimum t_ADadjust coarse setting

(TAD_COARSE = 0x00, TAD_INV = 0),

dither disabled (ADC_DITH_EN = 0)

50

60

fs

Minimum t_ADadjust coarse setting

(TAD_COARSE = 0x00, TAD_INV = 0),

dither enabled (ADC_DITH_EN = 1)

Maximum t_ADadjust coarse setting

(TAD_COARSE = 0xFF) excluding

TAD_INV (TAD_INV = 0), dither disabled

(ADC_DITH_EN = 0)

t_AJ

Aperture jitter, rms

65⁽³⁾

Maximum t_ADadjust coarse setting

(TAD_COARSE = 0xFF) excluding

TAD_INV (TAD_INV = 0), dither enabled

(ADC_DITH_EN = 1)

74⁽³⁾

SERIAL DATA OUTPUTS (DA[7:0]+, DA[7:0]–, DB[7:0]+, DB[7:0]–)

f_SERDES

UI

Serialized output bit rate

1

17.16

1000

Gbps

ps

Serialized output unit interval

58.2

20% to 80%, 8H8L test pattern, 17.16

Gbps

t_TLH

t_THL

Low-to-high transition time (differential)

High-to-low transition time (differential)

18.9

18.8

9.0

ps

20% to 80%, 8H8L test pattern, 17.16

Gbps

PRBS-7 test pattern, JMODE = 19, 12.8

Gbps

DDJ

DCD

EBUJ

RJ

Data dependent jitter, peak-to-peak

Even-odd jitter, peak-to-peak

ps

PRBS-9 test pattern, JMODE = 30,

17.16 Gbps

10.0

.33

PRBS-7 test pattern, JMODE = 19, 12.8

Gbps

PRBS-9 test pattern, JMODE = 30,

17.16 Gbps

.6

PRBS-7 test pattern, JMODE = 19, 12.8

Gbps

1.7

Effective bounded uncorrelated jitter, peak-

to-peak

PRBS-9 test pattern, JMODE = 30,

17.16 Gbps

1.93

0.85

0.88

23.3

22.6

8H8L test pattern, JMODE = 19, 12.8

Gbps

Unbounded random jitter, RMS

PRBS-9 test pattern, JMODE = 30,

17.16 Gbps

PRBS-7 test pattern, JMODE = 19, 12.8

Gbps

Total jitter, peak-to-peak, with unbounded

random jitter portion defined with respect to

a BER = 1e-15 (Q = 7.94)

TJ

PRBS-9 test pattern, JMODE = 30,

17.16 Gbps

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6.10 Switching Characteristics (continued)

typical values at T_A= 25°C, VA19 = 1.9 V, VA11 = 1.1 V, VD11 = 1.1 V, default full-scale voltage, f_IN= 2347 MHz, A_IN= –1

dBFS, f_CLK= 5.12 GHz, filtered 1-V_PPsine-wave clock, JMODE = 1, Dither enabled with default settings, VA11, VD11 and

VS11 noise suppression ON (EN_VA11_NOISE_SUPPR = EN_VD11_NOISE_SUPPR = EN_VS11_NOISE_SUPPR = 1),

and background calibration (unless otherwise noted); minimum and maximum values are at nominal supply voltages and

over the operating free-air temperature range provided in the Recommended Operating Conditions table

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

ADC CORE LATENCY

JMODE = 0, 30, 32

2.5

-9.5

2

JMODE = 1, 5, 19, 40, 42, 44

JMODE = 2, 31, 33

JMODE = 3, 7, 20

JMODE = 6, 50

-10

-13.5

-14

JMODE = 8, 51

JMODE = 10, 37

JMODE = 11, 47

JMODE = 12, 53

JMODE = 13, 39

JMODE = 14, 15, 49, 55

JMODE = 16

183

171

167

372

364

356

Deterministic delay from the CLK± edge

that samples the reference sample to the

CLK± edge that samples SYSREF going

high⁽¹⁾

JMODE = 21, 36

JMODE = 22, 46

JMODE = 23, 38

JMODE = 24, 48

JMODE = 25, 52

JMODE = 26, 54

JMODE = 27

148

t_ADC

142

t_CLKcycles

223.5

219.5

138

211.5

207.5

6.5

JMODE = 34

JMODE = 35

6

JMODE = 41, 43, 45

JMODE = 56, 59

JMODE = 57, 58, 60

JMODE = 61, 62, 63, 64, 65

JMODE = 66, 67, 68

JMODE = 69, 70, 71

-10.0

750

742

403.5

1514

777.5

English Data Sheet: SLVSGH5

24

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6.10 Switching Characteristics (continued)

typical values at T_A= 25°C, VA19 = 1.9 V, VA11 = 1.1 V, VD11 = 1.1 V, default full-scale voltage, f_IN= 2347 MHz, A_IN= –1

dBFS, f_CLK= 5.12 GHz, filtered 1-V_PPsine-wave clock, JMODE = 1, Dither enabled with default settings, VA11, VD11 and

VS11 noise suppression ON (EN_VA11_NOISE_SUPPR = EN_VD11_NOISE_SUPPR = EN_VS11_NOISE_SUPPR = 1),

and background calibration (unless otherwise noted); minimum and maximum values are at nominal supply voltages and

over the operating free-air temperature range provided in the Recommended Operating Conditions table

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

JESD204C AND SERIALIZER LATENCY

JMODE = 0

92

159

93

111

182

111

188

168

215

168

103

102

166

305

165

134

119

118

JMODE = 1

JMODE = 2

JMODE = 3

159

143

191

143

85

JMODE = 5

JMODE = 6, 8, 12, 15, 25, 26

JMODE = 7, 11, 22

JMODE = 10

JMODE = 13, 21, 23

JMODE = 14, 24

JMODE = 16, 27

JMODE = 19, 20

JMODE = 30, 31

JMODE = 32, 34, 36

JMODE = 33, 35, 37

JMODE = 38

85

143

280

143

114

102

103

102

103

205

206

179

267

268

143

191

280

179

268

267

191

280

268

267

Delay from the CLK± rising edge that

samples SYSREF high to the first bit of the

multiframe (8B/10B encoding) or extended

multiblock (64B/66B encoding) on the

JESD204C serial output lane

t_TX

JMODE = 39

118 t_CLKcycles

JMODE = 40

229

200

202

291

165

213

305

199

289

212

304

288

corresponding to the reference sample of

(2)

t_ADC

JMODE = 41

JMODE = 42, 43, 48, 49

JMODE = 44, 45, 46, 47

JMODE = 50, 52, 54

JMODE = 51, 53, 55

JMODE = 56, 61

JMODE = 57, 62

JMODE = 58, 63

JMODE = 59, 64

JMODE = 60

JMODE = 65

JMODE = 66, 69

JMODE = 67, 70

JMODE = 68

JMODE = 71

SERIAL PROGRAMMING INTERFACE (SDO)

Delay from the falling edge of the 16th SCLK cycle during read operation for SDO

transition from tri-state to valid data

t_(OZD)

1

ns

t_(ODZ)

t_(OD)

Delay from the SCS rising edge for SDO transition from valid data to tri-state

Delay from the falling edge of SCLK during read operation to SDO valid

10

12

ns

1

(1) t_ADCis an exact, unrounded, deterministic delay. The delay can be negative if the reference sample is sampled after the SYSREF high

capture point, in which case the total latency is smaller than the delay given by t_TX

.

(2) The values given for t_TXinclude deterministic and non-deterministic delays. Over process, temperature, and voltage, the delay will

vary. JESD204B accounts for these variations when operating in subclass-1 mode in order to achieve deterministic latency. Proper

receiver RBD values must be chosen such that the elastic buffer release point does not occur within the invalid region of the local

multiframe clock (LMFC) cycle.

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(3) t_AJincreases because of additional attenuation on the internal clock path.

6.11 Typical Characteristics

typical values at T_A= 25°C, VA19 = 1.9 V, VA11 = VD11 = 1.1 V, default full-scale voltage (FS_RANGE_A = FS_RANGE_B =

0xA000), input signal applied to INA in single-channel modes, f_IN= 4197 MHz, A_IN= –1 dBFS, f_CLK= maximum-rated clock

frequency, filtered, 1-V_PPsine-wave clock, JMODE = 1, dither enabled with default settings, VA11, VD11 and VS11 noise

suppression ON (EN_VA11_NOISE_SUPPR = EN_VD11_NOISE_SUPPR = EN_VS11_NOISE_SUPPR = 1), and

background calibration (unless otherwise noted); SNR results exclude DC, HD2 to HD9 and interleaving spurs; SINAD,

ENOB, and SFDR results exclude DC and fixed-frequency interleaving spurs

20

15

10

5

0

-2

-55 C

25 C

125 C

-4

-6

-8

-10

-12

-14

-16

-18

-20

0

-55 C

25 C

125 C

-5

0

1

2

3

4

5

6

7

8

9

10

0

1

2

3

4

5

6

7

8

9

10

Input Frequency (GHz)

JMODE 1

JMODE 1, relative to minimum fullscale amplitude

图6-1. DES Mode: Input Fullscale vs Input Frequency

图6-2. DES Mode: Input Amplitude vs Input Frequency

0

-5

20

-55 C

25 C

125 C

15

-10

-15

-20

-25

-30

-35

-40

10

5

0

-5

0

2000

4000

6000

8000

10000

0

1

2

3

4

5

6

7

8

9

10

Input Frequency (MHz)

Input Frequency (GHz)

JMODE 1

JMODE 3

图6-3. DES Mode: Input Return Loss vs Input Frequency

图6-4. Dual Channel Mode: Input Fullscale vs Input Frequency

26

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6.11 Typical Characteristics (continued)

typical values at T_A= 25°C, VA19 = 1.9 V, VA11 = VD11 = 1.1 V, default full-scale voltage (FS_RANGE_A = FS_RANGE_B =

0xA000), input signal applied to INA in single-channel modes, f_IN= 4197 MHz, A_IN= –1 dBFS, f_CLK= maximum-rated clock

frequency, filtered, 1-V_PPsine-wave clock, JMODE = 1, dither enabled with default settings, VA11, VD11 and VS11 noise

suppression ON (EN_VA11_NOISE_SUPPR = EN_VD11_NOISE_SUPPR = EN_VS11_NOISE_SUPPR = 1), and

background calibration (unless otherwise noted); SNR results exclude DC, HD2 to HD9 and interleaving spurs; SINAD,

ENOB, and SFDR results exclude DC and fixed-frequency interleaving spurs

0

-2

0

-5

-4

-10

-15

-20

-25

-30

-35

-40

-6

-8

-10

-12

-14

-16

-18

-20

-55 C

25 C

125 C

INA

INB

0

1

2

3

4

5

6

7

8

9

10

0

2000

4000

6000

8000

10000

Input Frequency (GHz)

Input Frequency (MHz)

JMODE 3, relative to minimum fullscale amplitude

JMODE 3

图6-5. Dual Channel Mode: Input Amplitude vs Input Frequency

图6-6. Dual Channel Mode: Input Return Loss vs Input

Frequency

56

54

52

50

48

A_IN= -12 dBFS

A_IN= -6 dBFS

A_IN= -1 dBFS

46

44

1000

2000

3000

4000

5000

6000

7000

8000

Input Frequency (MHz)

JMODE 3

JMODE 1

图6-7. Dual Channel Mode: Crosstalk vs Input Frequency

图6-8. DES Mode: SNR vs Input Frequency

75

56

54

52

50

48

46

44

70

65

60

55

50

A_IN= -12 dBFS

A_IN= -6 dBFS

A_IN= -1 dBFS

A_IN= -12 dBFS

A_IN= -6 dBFS

A_IN= -1 dBFS

45

40

1000

2000

3000

4000

5000

6000 7000 8000

1000

2000

3000

4000

5000

6000

7000

8000

Input Frequency (MHz)

JMODE 1

图6-9. DES Mode: SFDR vs Input Frequency

图6-10. DES Mode: SINAD vs Input Frequency

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6.11 Typical Characteristics (continued)

typical values at T_A= 25°C, VA19 = 1.9 V, VA11 = VD11 = 1.1 V, default full-scale voltage (FS_RANGE_A = FS_RANGE_B =

0xA000), input signal applied to INA in single-channel modes, f_IN= 4197 MHz, A_IN= –1 dBFS, f_CLK= maximum-rated clock

frequency, filtered, 1-V_PPsine-wave clock, JMODE = 1, dither enabled with default settings, VA11, VD11 and VS11 noise

suppression ON (EN_VA11_NOISE_SUPPR = EN_VD11_NOISE_SUPPR = EN_VS11_NOISE_SUPPR = 1), and

background calibration (unless otherwise noted); SNR results exclude DC, HD2 to HD9 and interleaving spurs; SINAD,

ENOB, and SFDR results exclude DC and fixed-frequency interleaving spurs

-40

-50

-40

-50

A_IN= -12 dBFS

A_IN= -6 dBFS

A_IN= -1 dBFS

A_IN= -12 dBFS

A_IN= -6 dBFS

A_IN= -1 dBFS

-60

-70

-80

-90

-100

1000

2000

3000

4000

5000

6000

7000

8000

1000

2000

3000

4000

5000

6000

7000

8000

Input Frequency (MHz)

JMODE 1

图6-11. DES Mode: HD2 vs Input Frequency

图6-12. DES Mode: HD3 vs Input Frequency

-40

-50

-60

-70

-80

58

57

56

55

54

53

52

51

50

F_IN= 2397 MHz, Dither off

F_IN= 4197 MHz, Dither off

F_IN= 5597 MHz, Dither off

F_IN= 2397 MHz, Dither on

F_IN= 4197 MHz, Dither on

F_IN= 5597 MHz, Dither on

F_S/2 - F_IN

F_S/4 - F_IN

F_S/4 + F_IN

1000

2000

3000

4000

5000

6000

7000

8000

-80

-70

-60

-50

-40

-30

-20

-10

0

Input Frequency (MHz)

Input Amplitude (dBFS)

JMODE 1

图6-13. DES Mode: Interleaving Spurs vs Input Frequency

图6-14. DES Mode: SNR vs Input Amplitude

90

85

80

75

70

56

54

52

50

48

46

44

65

F_IN= 2397 MHz, Dither off

F_IN= 4197 MHz, Dither off

F_IN= 5597 MHz, Dither off

F_IN= 2397 MHz, Dither on

F_IN= 4197 MHz, Dither on

F_IN= 5597 MHz, Dither on

60

55

50

A_IN= -12 dBFS

A_IN= -6 dBFS

A_IN= -1 dBFS

-80

-70

-60

-50

-40

-30

-20

-10

0

1000

2000

3000

4000

5000

6000

7000

8000

Input Amplitude (dBFS)

Input Frequency (MHz)

JMODE 1

图6-15. DES Mode: SFDR vs Input Amplitude

图6-16. DES Mode: SINAD vs Input Amplitude

English Data Sheet: SLVSGH5

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6.11 Typical Characteristics (continued)

typical values at T_A= 25°C, VA19 = 1.9 V, VA11 = VD11 = 1.1 V, default full-scale voltage (FS_RANGE_A = FS_RANGE_B =

0xA000), input signal applied to INA in single-channel modes, f_IN= 4197 MHz, A_IN= –1 dBFS, f_CLK= maximum-rated clock

frequency, filtered, 1-V_PPsine-wave clock, JMODE = 1, dither enabled with default settings, VA11, VD11 and VS11 noise

suppression ON (EN_VA11_NOISE_SUPPR = EN_VD11_NOISE_SUPPR = EN_VS11_NOISE_SUPPR = 1), and

background calibration (unless otherwise noted); SNR results exclude DC, HD2 to HD9 and interleaving spurs; SINAD,

ENOB, and SFDR results exclude DC and fixed-frequency interleaving spurs

-40

-50

-40

-50

F_IN= 2397 MHz, Dither off

F_IN= 4197 MHz, Dither off

F_IN= 5597 MHz, Dither off

F_IN= 2397 MHz, Dither on

F_IN= 4197 MHz, Dither on

F_IN= 5597 MHz, Dither on

F_IN= 2397 MHz, Dither off

F_IN= 4197 MHz, Dither off

F_IN= 5597 MHz, Dither off

F_IN= 2397 MHz, Dither on

F_IN= 4197 MHz, Dither on

F_IN= 5597 MHz, Dither on

-60

-70

-80

-90

-100

-110

-100

-80

-70

-60

-50

-40

-30

-20

-10

0

-80

-70

-60

-50

-40

-30

-20

-10

0

Input Amplitude (dBFS)

JMODE 1

图6-17. DES Mode: HD2 vs Input Amplitude

图6-18. DES Mode: HD3 vs Input Amplitude

-30

-40

F_IN= 2397 MHz, Dither off

F_IN= 4197 MHz, Dither off

F_IN= 5597 MHz, Dither off

F_IN= 2397 MHz, Dither on

F_IN= 4197 MHz, Dither on

F_IN= 5597 MHz, Dither on

F_IN= 2397 MHz, Dither off

F_IN= 4197 MHz, Dither off

F_IN= 5597 MHz, Dither off

F_IN= 2397 MHz, Dither on

F_IN= 4197 MHz, Dither on

F_IN= 5597 MHz, Dither on

-40

-50

-60

-70

-80

-90

-100

-110

-100

-110

-80

-70

-60

-50

-40

-30

-20

-10

-80

-70

-60

-50

-40

-30

-20

-10

0

Input Amplitude (dBFS)

JMODE 1

图6-19. DES Mode: F_S/2 - F_INvs Input Amplitude

图6-20. DES Mode: F_S/4 - F_INvs Input Amplitude

-40

-45

-50

-55

-60

-65

-70

-75

-80

-85

-90

F_IN= 2397 MHz, Dither off

F_IN= 4197 MHz, Dither off

F_IN= 5597 MHz, Dither off

F_IN= 2397 MHz, Dither on

F_IN= 4197 MHz, Dither on

F_IN= 5597 MHz, Dither on

-50

-60

-70

-80

-90

-100

-110

-80

-70

-60

-50

-40

-30

-20

-10

1000

2000

3000

4000

5000

6000

7000

8000

Input Amplitude (dBFS)

Input Frequency (MHz)

JMODE 1

JMODE 1, 100 MHz Tone Spacing, -7 dBFS per Tone

图6-21. DES Mode: F_S/4 + F_INvs Input Amplitude

图6-22. DES Mode: IMD3 vs Input Frequency

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6.11 Typical Characteristics (continued)

typical values at T_A= 25°C, VA19 = 1.9 V, VA11 = VD11 = 1.1 V, default full-scale voltage (FS_RANGE_A = FS_RANGE_B =

0xA000), input signal applied to INA in single-channel modes, f_IN= 4197 MHz, A_IN= –1 dBFS, f_CLK= maximum-rated clock

frequency, filtered, 1-V_PPsine-wave clock, JMODE = 1, dither enabled with default settings, VA11, VD11 and VS11 noise

suppression ON (EN_VA11_NOISE_SUPPR = EN_VD11_NOISE_SUPPR = EN_VS11_NOISE_SUPPR = 1), and

background calibration (unless otherwise noted); SNR results exclude DC, HD2 to HD9 and interleaving spurs; SINAD,

ENOB, and SFDR results exclude DC and fixed-frequency interleaving spurs

65

60

55

50

45

40

-50

-60

F_IN= 2397 MHz, Dither off

F_IN= 4197 MHz, Dither off

F_IN= 5597 MHz, Dither off

F_IN= 2397 MHz, Dither on

F_IN= 4197 MHz, Dither on

F_IN= 5597 MHz, Dither on

-70

-80

-90

-100

-110

1000

2000

3000

4000

5000

6000

7000

8000

-80

-70

-60

-50

-40

-30

-20

-10

0

Input Frequency (MHz)

Input Amplitude (dBFS)

JMODE 1, 100 MHz Tone Spacing, -7 dBFS per Tone

JMODE 1, 100 MHz Tone Spacing

图6-24. DES Mode: IMD3 vs Input Amplitude

图6-23. DES Mode: Two Tone SFDR vs Input Frequency

90

85

80

75

70

-50

A_IN= -7 dBFS

A_IN= -12 dBFS

-55

-60

-65

-70

-75

-80

65

F_IN= 2397 MHz, Dither off

F_IN= 4197 MHz, Dither off

F_IN= 5597 MHz, Dither off

F_IN= 2397 MHz, Dither on

F_IN= 4197 MHz, Dither on

F_IN= 5597 MHz, Dither on

60

55

50

-80

-70

-60

-50

-40

-30

-20

-10

0

200 400 600 800 1000 1200 1400 1600 1800 2000

Tone Spacing (MHz)

Input Amplitude (dBFS)

JMODE 1, 100 MHz Tone Spacing

JMODE 1, 4197 MHz

图6-25. DES Mode: Two Tone SFDR vs Input Amplitude

图6-26. DES Mode: IMD3 vs Tone Spacing

0

-10

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-100

-110

-120

0

1000

2000

3000

4000

5000

0

1000

2000

3000

4000

5000

Output Frequency (MHz)

JMODE 1

图6-27. DES Mode: Single Tone Output Spectrum at 2397 MHz

图6-28. DES Mode: Single Tone Output Spectrum at 4197 MHz

30

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6.11 Typical Characteristics (continued)

typical values at T_A= 25°C, VA19 = 1.9 V, VA11 = VD11 = 1.1 V, default full-scale voltage (FS_RANGE_A = FS_RANGE_B =

0xA000), input signal applied to INA in single-channel modes, f_IN= 4197 MHz, A_IN= –1 dBFS, f_CLK= maximum-rated clock

frequency, filtered, 1-V_PPsine-wave clock, JMODE = 1, dither enabled with default settings, VA11, VD11 and VS11 noise

suppression ON (EN_VA11_NOISE_SUPPR = EN_VD11_NOISE_SUPPR = EN_VS11_NOISE_SUPPR = 1), and

background calibration (unless otherwise noted); SNR results exclude DC, HD2 to HD9 and interleaving spurs; SINAD,

ENOB, and SFDR results exclude DC and fixed-frequency interleaving spurs

0

-10

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-100

-110

-120

0

1000

2000

3000

4000

5000

0

1000

2000

3000

4000

5000

Output Frequency (MHz)

JMODE 1

JMODE 1, 100 MHz Tone Spacing, -7 dBFS per Tone

图6-29. DES Mode: Single Tone Output Spectrum at 5597 MHz

图6-30. DES Mode: Two Tone Output Spectrum at 2397 MHz

0

-10

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-100

-110

-120

0

1000

2000

3000

4000

5000

0

1000

2000

3000

4000

5000

Output Frequency (MHz)

JMODE 1, 100 MHz Tone Spacing, -7 dBFS per Tone

图6-31. DES Mode: Two Tone Output Spectrum at 4197 MHz

图6-32. DES Mode: Two Tone Output Spectrum at 5597 MHz

56

80

75

70

65

60

54

52

50

48

55

A_IN= -12 dBFS

A_IN= -6 dBFS

A_IN= -1 dBFS

A_IN= -12 dBFS

A_IN= -6 dBFS

A_IN= -1 dBFS

45

46

44

50

1000

2000

3000

4000

5000

6000

7000

8000

1000

2000

3000

4000

5000

6000

7000

8000

Input Frequency (MHz)

JMODE 3

图6-33. Dual Channel Mode: SNR vs Input Frequency

图6-34. Dual Channel Mode: SFDR vs Input Frequency

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6.11 Typical Characteristics (continued)

typical values at T_A= 25°C, VA19 = 1.9 V, VA11 = VD11 = 1.1 V, default full-scale voltage (FS_RANGE_A = FS_RANGE_B =

0xA000), input signal applied to INA in single-channel modes, f_IN= 4197 MHz, A_IN= –1 dBFS, f_CLK= maximum-rated clock

frequency, filtered, 1-V_PPsine-wave clock, JMODE = 1, dither enabled with default settings, VA11, VD11 and VS11 noise

suppression ON (EN_VA11_NOISE_SUPPR = EN_VD11_NOISE_SUPPR = EN_VS11_NOISE_SUPPR = 1), and

background calibration (unless otherwise noted); SNR results exclude DC, HD2 to HD9 and interleaving spurs; SINAD,

ENOB, and SFDR results exclude DC and fixed-frequency interleaving spurs

56

54

52

50

48

46

44

-40

-50

A_IN= -12 dBFS

A_IN= -6 dBFS

A_IN= -1 dBFS

-60

-70

-80

A_IN= -12 dBFS

A_IN= -6 dBFS

A_IN= -1 dBFS

-90

-100

1000

2000

3000

4000

5000

6000

7000

8000

1000

2000

3000

4000

5000

6000

7000

8000

Input Frequency (MHz)

JMODE 3

图6-35. Dual Channel Mode: SINAD vs Input Frequency

图6-36. Dual Channel Mode: HD2 vs Input Frequency

-40

-50

-52

-54

-56

-58

-60

-62

-64

-66

-68

-70

A_IN= -12 dBFS

A_IN= -6 dBFS

A_IN= -1 dBFS

-50

-60

-70

-80

-90

-100

1000

2000

3000

4000

5000

6000

7000

8000

1000

2000

3000

4000

5000

6000

7000

8000

Input Frequency (MHz)

JMODE 3

图6-37. Dual Channel Mode: HD3 vs Input Frequency

图6-38. Dual Channel Mode: F_S/2 - F_INvs Input Frequency

58

57

56

55

54

90

85

80

75

70

53

65

F_IN= 2397 MHz, Dither off

F_IN= 4197 MHz, Dither off

52

51

50

60

55

50

F_IN= 5597 MHz, Dither off

F_IN= 2397 MHz, Dither on

F_IN= 4197 MHz, Dither on

F_IN= 5597 MHz, Dither on

F_IN= 5597 MHz, Dither off

F_IN= 2397 MHz, Dither on

F_IN= 4197 MHz, Dither on

F_IN= 5597 MHz, Dither on

-80

-70

-60

-50

-40

-30

-20

-10

0

-80

-70

-60

-50

-40

-30

-20

-10

0

Input Amplitude (dBFS)

JMODE 3

图6-39. Dual Channel Mode: SNR vs Input Amplitude

图6-40. Dual Channel Mode: SFDR vs Input Amplitude

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6.11 Typical Characteristics (continued)

typical values at T_A= 25°C, VA19 = 1.9 V, VA11 = VD11 = 1.1 V, default full-scale voltage (FS_RANGE_A = FS_RANGE_B =

0xA000), input signal applied to INA in single-channel modes, f_IN= 4197 MHz, A_IN= –1 dBFS, f_CLK= maximum-rated clock

frequency, filtered, 1-V_PPsine-wave clock, JMODE = 1, dither enabled with default settings, VA11, VD11 and VS11 noise

suppression ON (EN_VA11_NOISE_SUPPR = EN_VD11_NOISE_SUPPR = EN_VS11_NOISE_SUPPR = 1), and

background calibration (unless otherwise noted); SNR results exclude DC, HD2 to HD9 and interleaving spurs; SINAD,

ENOB, and SFDR results exclude DC and fixed-frequency interleaving spurs

-40

F_IN= 2397 MHz, Dither off

F_IN= 4197 MHz, Dither off

F_IN= 5597 MHz, Dither off

F_IN= 2397 MHz, Dither on

F_IN= 4197 MHz, Dither on

F_IN= 5597 MHz, Dither on

-50

-60

-70

-80

-90

-100

-110

-80

-70

-60

-50

-40

-30

-20

-10

0

Input Amplitude (dBFS)

JMODE 3

图6-41. Dual Channel Mode: HD2 vs Input Amplitude

图6-42. Dual Channel Mode: HD3 vs Input Amplitude

-30

-40

-45

-50

-55

-60

-65

-70

-75

-80

-85

-90

F_IN= 2397 MHz, Dither off

F_IN= 4197 MHz, Dither off

F_IN= 5597 MHz, Dither off

F_IN= 2397 MHz, Dither on

F_IN= 4197 MHz, Dither on

F_IN= 5597 MHz, Dither on

-40

-50

-60

-70

-80

-90

-100

-110

-80

-70

-60

-50

-40

-30

-20

-10

0

1000

2000

3000

4000

5000

6000

7000

8000

Input Amplitude (dBFS)

Input Frequency (MHz)

JMODE 3

JMODE 3, 100 MHz Tone Spacing, -7 dBFS per Tone

图6-43. Dual Channel Mode: F_S/2 - F_INvs Input Amplitude

图6-44. Dual Channel Mode: IMD3 vs Input Frequency

70

65

60

55

50

45

40

35

30

-50

F_IN= 2397 MHz, Dither off

F_IN= 4197 MHz, Dither off

F_IN= 5597 MHz, Dither off

F_IN= 2397 MHz, Dither on

F_IN= 4197 MHz, Dither on

F_IN= 5597 MHz, Dither on

-60

-70

-80

-90

-100

-110

1000

2000

3000

4000

5000

6000

7000

8000

-80

-70

-60

-50

-40

-30

-20

-10

0

Input Frequency (MHz)

Input Amplitude (dBFS)

JMODE 3, 100 MHz Tone Spacing, -7 dBFS per Tone

JMODE 3, 100 MHz Tone Spacing

图6-45. Dual Channel Mode: Two Tone SFDR vs Input

图6-46. Dual Channel Mode: IMD3 vs Input Amplitude

Frequency

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6.11 Typical Characteristics (continued)

typical values at T_A= 25°C, VA19 = 1.9 V, VA11 = VD11 = 1.1 V, default full-scale voltage (FS_RANGE_A = FS_RANGE_B =

0xA000), input signal applied to INA in single-channel modes, f_IN= 4197 MHz, A_IN= –1 dBFS, f_CLK= maximum-rated clock

frequency, filtered, 1-V_PPsine-wave clock, JMODE = 1, dither enabled with default settings, VA11, VD11 and VS11 noise

suppression ON (EN_VA11_NOISE_SUPPR = EN_VD11_NOISE_SUPPR = EN_VS11_NOISE_SUPPR = 1), and

background calibration (unless otherwise noted); SNR results exclude DC, HD2 to HD9 and interleaving spurs; SINAD,

ENOB, and SFDR results exclude DC and fixed-frequency interleaving spurs

90

85

80

75

70

65

F_IN= 2397 MHz, Dither off

F_IN= 4197 MHz, Dither off

60

55

50

F_IN= 5597 MHz, Dither off

F_IN= 2397 MHz, Dither on

F_IN= 4197 MHz, Dither on

F_IN= 5597 MHz, Dither on

-80

-70

-60

-50

-40

-30

-20

-10

0

Input Amplitude (dBFS)

JMODE 3, 100 MHz Tone Spacing

JMODE 3, 4197 MHz

图6-47. Dual Channel Mode: Two Tone SFDR vs Input

图6-48. Dual Channel Mode: IMD3 vs Tone Spacing

Amplitude

0

-10

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-100

-110

-120

0

500

1000

1500

2000

2500

0

500

1000

1500

2000

2500

Output Frequency (MHz)

JMODE 3

图6-49. Dual Channel Mode: Single Tone Spectrum at 2397 MHz 图6-50. Dual Channel Mode: Single Tone Spectrum at 4197 MHz

0

-10

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-100

-110

-120

0

500

1000

1500

2000

2500

0

500

1000

1500

2000

2500

Output Frequency (MHz)

JMODE 3

JMODE 3, 100 MHz Tone Spacing, -7 dBFS per Tone

图6-51. Dual Channel Mode: Single Tone Spectrum at 5597 MHz 图6-52. Dual Channel Mode: Dual Tone Spectrum at 2397 MHz

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6.11 Typical Characteristics (continued)

typical values at T_A= 25°C, VA19 = 1.9 V, VA11 = VD11 = 1.1 V, default full-scale voltage (FS_RANGE_A = FS_RANGE_B =

0xA000), input signal applied to INA in single-channel modes, f_IN= 4197 MHz, A_IN= –1 dBFS, f_CLK= maximum-rated clock

frequency, filtered, 1-V_PPsine-wave clock, JMODE = 1, dither enabled with default settings, VA11, VD11 and VS11 noise

suppression ON (EN_VA11_NOISE_SUPPR = EN_VD11_NOISE_SUPPR = EN_VS11_NOISE_SUPPR = 1), and

background calibration (unless otherwise noted); SNR results exclude DC, HD2 to HD9 and interleaving spurs; SINAD,

ENOB, and SFDR results exclude DC and fixed-frequency interleaving spurs

0

-10

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-100

-110

-120

0

500

1000

1500

2000

2500

0

500

1000

1500

2000

2500

Output Frequency (MHz)

JMODE 3, 100 MHz Tone Spacing, -7 dBFS per Tone

图6-53. Dual Channel Mode: Dual Tone Spectrum at 4197 MHz

图6-54. Dual Channel Mode: Dual Tone Spectrum at 5597 MHz

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7 Detailed Description

7.1 Overview

The ADC12DJ5200SE is an RF-sampling, gigasample, analog-to-digital converter (ADC) with integrated input

baluns. The ADC12DJ5200SE can be configured as a dual-channel, 5.2 GSPS ADC or single-channel, 10.4

GSPS ADC. The -3 dB input frequency range of 2.1 to 6.3 GHz enables direct RF sampling of S-band and C-

band for frequency agile systems.

The device uses a high-speed JESD204C output interface with up to 16 serialized lanes and subclass-1

compliance for deterministic latency and multi-device synchronization. The serial output lanes support up to

17.16 Gbps and can be configured to trade-off bit rate and number of lanes. Both 8B/10B and 64B/66B data

encoding schemes are supported. The 64B/66B encoding schemes support forward error correction (FEC) for

improved bit error rates. The JESD204C interface is backwards compatible with JESD204B receivers when

using 8B/10B encoding modes.

A number of synchronization features, including noiseless aperture delay (t_AD) adjustment and SYSREF

windowing, simplify system design for multi-channel systems. Aperture delay adjustment can be used to simplify

SYSREF capture, to align the sampling instance between multiple ADCs or to sample an ideal location of a front-

end track and hold (T&H) amplifier output. SYSREF windowing offers a simplistic way to measure invalid timing

regions of SYSREF relative to the device clock and then choose an optimal sampling location. Dual-edge

sampling (DES) is implemented in single-channel mode to reduce the maximum clock rate applied to the ADC to

support a wide range of clock sources and relax setup and hold timing for SYSREF capture.

Optional digital down converters (DDCs) are available in both single-channel mode and dual-channel mode to

allow a reduction in interface rate (decimation) and digital mixing of the signal to baseband. Single-channel

mode supports a single DDC while dual-channel mode supports one DDC per channel. The DDC block supports

data decimation of 4x, 8x, 16x or 32x and alias-free complex output bandwidths of 80% of the effective output

data rate.

The device provides foreground and background calibration options for gain, offset and static linearity errors.

Foreground calibration is run at system startup or at specified times during which the ADC is offline and not

sending data to the logic device. Background calibration allows the ADC to run continually while the cores are

calibrated in the background so that the system does not experience downtime. The calibration routine is also

used to match the gain and offset between sub-ADC cores to minimize spurious artifacts from time interleaving.

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7.2 Functional Block Diagram

NCOA0 NCOA1 NCOB0 NCOB1 CALTRG PD

SCLK

SDI

SDO

SCS\

SPI Registers and

Device Control

DDC Bypass / Single Channel Mode

DDC A

NCO Bank A

TMSTP+

TMSTP-

DA0+

DA0-

Input

MUX

JESD204B

Link A

ADC A

N

INA

DA7+

DA7-

Mixer

Filter

JMODE

DDC Bypass / Single Channel Mode

Over-

range

SYNCSE\

DDC B

DB0+

DB0-

NCO Bank B

INB

Input

MUX

JESD204B

Link B

ADC B

N

DB7+

DB7-

Mixer

Filter

DIGBIND

Aperture

Delay Adjust

JMODE

CLK+

CLK-

Clock Distribu on

and Synchroniza on

Status

Indicators

SYSREF+

SYSREF-

SYSREF

Windowing

TDIODE+

TDIODE-

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7.3 Feature Description

7.3.1 Device Comparison

The devices listed in 表 7-1 are part of a high-speed, wide-bandwidth ADC family. The differential input devices

are pin compatible, and the single ended device is pin compatible except for the ADC input and surrounding

balls. The family is offered to provide a scalable family of devices for varying resolution, sampling rate and signal

bandwidth.

表7-1. Device Family Comparison

MAXIMUM

SAMPLING

RATE

INTERFACE

(MAX

LINERATE)

PART

NUMBER

DUAL CHANNEL

DECIMATION

SINGLE CHANNEL

DECIMATION

RESOLUTION

Input

Single 10.4

GSPS

Dual 5.2 GSPS

JESD204B /

JESD204C

(17.16 Gbps)

Single ended,

AC only

ADC12DJ5200

SE

Complex: 4x, 8x, 16x, Complex: 4x, 8x, 16x,

32x 32x

12-bit

Single 10.4

GSPS

Dual 5.2 GSPS

JESD204B /

JESD204C

(17.16 Gbps)

Differential,

DC or AC

ADC12DJ5200

RF

Complex: 4x, 8x, 16x, Complex: 4x, 8x, 16x,

12-bit

32x

Single 10.4

GSPS

Dual 5.2 GSPS

JESD204B /

JESD204C

(17.16 Gbps)

Differential,

DC or AC

ADC08DJ5200

RF

8-bit

None

JESD204B /

JESD204C

(17.16 Gbps)

Differential,

DC or AC

ADC12DJ4000 Single 8 GSPS

Complex: 4x, 8x, 16x, Complex: 4x, 8x, 16x,

12-bit

RF

Dual 4 GSPS

32x

Single 6.4

ADC12DJ3200 GSPS

Dual 3.2 GSPS

Differential,

DC or AC

Real: 2x

Complex: 4x, 8x, 16x

JESD204B

(12.8 Gbps)

12-bit

None

Single 6.4

ADC08DJ3200 GSPS

Differential,

DC or AC

JESD204B

(12.8 Gbps)

8-bit

None

Dual 3.2 GSPS

Single 5.4

ADC12DJ2700 GSPS

Dual 2.7 GSPS

Differential,

DC or AC

Real: 2x

Complex: 4x, 8x, 16x

JESD204B

(12.8 Gbps)

12-bit

7.3.2 Analog Inputs

The analog inputs of the device contain an AC coupled balun to convert the single ended input to a differential

signal for the ADCs. The input impedance is nominally 50 Ω. The ADCs have internal buffers to enable high

input bandwidth and to isolate sampling capacitor glitch noise from the input circuit. The single ended input has

no DC path. The device includes internal analog input protection to protect the ADC inputs during overranged

input conditions; see the Analog Input Protection section. 图7-1 provides a simplified analog input model.

AGND

Analog Input

50

Protection

Diodes

INA, INB

ADC

Input Buffer

50

图7-1. ADC12DJ5200SE Analog Input Internal Termination and Protection Diagram

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There is minimal degradation in analog input bandwidth when using single-channel mode versus dual-channel

mode. Either analog input (INA or INB) can be used in single-channel mode, but INA is preferred for better

performance. The desired input can be chosen using SINGLE_INPUT in the input mux control register. A

calibration needs to be performed after switching the input mux for the changes to take effect. Further, two inputs

can be used in single-channel mode to drive the interleaved ADCs separately using the SINGLE_INPUT register

setting. This mode is called dual-input single-channel mode. Dual-input single-channel mode is equivalent to

dual channel mode, except ADC B samples out-of-phase with ADC A (single-channel mode sample timing). This

mode is available when a single-channel mode JMODE setting is chosen.

7.3.2.1 Analog Input Protection

The analog inputs are protected against overdrive conditions by internal clamping diodes. The overrange

protection is defined for a peak RF input power in the Absolute Maximum Ratings table. Operation above the

maximum conditions listed in the Recommended Operating Conditions table results in an increase in failure-in-

time (FIT) rate, so the system must correct the overdrive condition as quickly as possible. 图 7-1 shows the

analog input protection diodes.

7.3.2.2 Full-Scale Voltage (V_FS) Adjustment

Input full-scale power (P_FS) adjustment is available, in fine increments, for each analog input through the

FS_RANGE_A register setting (see the INA full-scale range adjust register) and FS_RANGE_B register setting

(see the INB full-scale range adjust register) for INA and INB, respectively. The available adjustment range is

specified in the Electrical Characteristics: DC Specifications table. Larger full-scale power improve SNR and

noise floor (in dBFS/Hz) performance, but can degrade harmonic distortion. The full-scale power adjustment is

useful for matching the full-scale range of multiple ADCs when developing a multi-converter system or for

external interleaving of multiple ADC12DJ5200SE's to achieve higher sampling rates.

7.3.2.3 Analog Input Offset Adjust

In foreground calibration mode, the input offset voltage for each input and for each ADC core can be adjusted

through SPI registers. The OADJ_A_FG0_VINx and OADJ_A_FG90_VINx registers (registers 0x344 to 0x34A)

are used to adjust ADC core A's offset voltage when sampling analog input x (where x is A for INA or B for INB)

where the FG0 register is used for dual channel mode and FG90 is used for single channel mode.

OADJ_B_FG0_VINx is used to adjust ADC core B's offset voltage when sampling input x. OADJ_B_FG0_VINx

applies to both single channel mode and dual channel mode. To adjust the offset voltage in dual channel mode

simply adjust the offset for the ADC core sampling the desired input. In single channel mode, both ADC core A's

offset and ADC core B's offset must be adjusted together. The difference in the two core's offsets in single

channel mode will result in a spur at f_S/2 that is independent of the input. These registers can be used to

compensate the f_S/2 spur in single channel mode. See the Calibration Modes and Trimming section for more

information.

7.3.3 ADC Core

The ADC12DJ5200SE has 3 ADC channels, each consisting of 2 ADC cores. Two of the ADC channels are

active while one channel is offline for calibration. The cores are interleaved for higher sampling rates and the

channels are swapped on-the-fly for calibration as required by the operating mode. The two active channels can

be interleaved to double the sample rate. This section highlights the theory and key features of the ADC cores.

7.3.3.1 ADC Theory of Operation

The differential voltages at the ADC inputs (after the balun) are captured by the rising edge of CLK± in dual-

channel mode or by the rising and falling edges of CLK± in single-channel mode. After capturing the input signal,

the ADC converts the analog voltage to a digital value by comparing the voltage to the internal reference

voltage. If the voltage on negative differential input is higher than the voltage on the positive differential input,

then the digital output is a negative 2's complement value. If the voltage on positive differential input is higher

than the voltage on the negative differential input, then the digital output is a positive 2's complement value.

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7.3.3.2 ADC Core Calibration

ADC core calibration is required to optimize the analog performance of the ADC cores. Calibration must be

repeated when operating conditions change significantly, namely temperature, to maintain optimal performance.

The device has a built-in calibration routine that can be run as a foreground operation or a background

operation. Foreground operation requires ADC downtime, where the ADC is no longer sampling the input signal,

to complete the process. Background calibration can be used to overcome this limitation and allow constant

operation of the ADC. See the Calibration Modes and Trimming section for detailed information on each mode.

7.3.3.3 Analog Reference Voltage

The reference voltage for the ADC12DJ5200SE is derived from an internal band-gap reference. A buffered

version of the reference voltage is available at the BG pin for user convenience. This output has an output-

current capability of ±100 µA. The BG output must be buffered if more current is required. No provision exists for

the use of an external reference voltage, but the full-scale input voltage can be adjusted through the full-scale-

range register settings.

7.3.3.4 ADC Overrange Detection

To make sure the system gain management has the quickest possible response time, a low-latency configurable

overrange function is included. The overrange function works by monitoring the converted 12-bit samples at the

ADC to quickly detect if the ADC is near saturation or already in an overrange condition. The absolute value of

the upper 8 bits of the ADC data are checked against two programmable thresholds, OVR_T0 and OVR_T1.

These thresholds apply to both channel A and channel B in dual-channel mode. 表7-2 lists how an ADC sample

is converted to an absolute value for a comparison of the thresholds.

表7-2. Conversion of ADC Sample for Overrange Comparison

ADC SAMPLE

(Offset Binary)

ADC SAMPLE

(2's Complement)

UPPER 8 BITS USED FOR

COMPARISON

ABSOLUTE VALUE

1111 1111 1111 (4095)

1111 1111 0000 (4080)

1000 0000 0000 (2048)

0000 0001 0000 (16)

0000 0000 0000 (0)

0111 1111 1111 (+2047)

0111 1111 0000 (+2032)

0000 0000 0000 (0)

111 1111 1111 (2047)

111 1111 0000 (2032)

000 0000 0000 (0)

1111 1111 (255)

1111 1110 (254)

0000 0000 (0)

1111 1110 (254)

1111 1111 (255)

111 1111 0000 (2032)

111 1111 1111 (2047)

1000 0001 0000 (–2032)

1000 0000 0000 (–2048)

If the upper 8 bits of the absolute value equal or exceed the OVR_T0 or OVR_T1 thresholds during the

monitoring period, then the overrange bit associated with the threshold is set to 1, otherwise the overrange bit is

0. In dual-channel mode, the overrange status can be monitored on the ORA0 and ORA1 pins for channel A and

the ORB0 and ORB1 pins for channel B, where ORx0 corresponds to the OVR_T0 threshold and ORx1

corresponds to the OVR_T1 threshold. In single-channel mode, the overrange status for the OVR_T0 threshold

is determined by monitoring both the ORA0 and ORB0 outputs and the OVR_T1 threshold is determined by

monitoring both ORA1 and ORB1 outputs. In single-channel mode, the two outputs for each threshold must be

OR'd together to determine whether an overrange condition occurred. OVR_N can be used to set the output

pulse duration from the last overrange event. 表 7-3 lists the overrange pulse lengths for the various OVR_N

settings (see the overrange configuration register). In decimation modes (only in the JMODEs where CS = 1 in

表 7-24), the overrange status is also embedded into the output data samples where the OVR_T0 threshold

status is embedded as the LSB along with the upper 15 bits of every complex I sample and the OVR_T1

threshold status is embedded as the LSB along with the upper 15 bits of every complex Q sample. 表 7-4 lists

the outputs, related data samples, threshold settings, and the monitoring period equation. The embedded

overrange bit goes high if the associated channel exceeds the associated overrange threshold within the

monitoring period set by OVR_N. Use 表7-4 to calculate the monitoring period.

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表7-3. Overrange Monitoring Period for the ORA0, ORA1, ORB0, and ORB1 Outputs

OVERRANGE PULSE LENGTH SINCE LAST OVERRANGE

EVENT (DEVCLK Cycles)

OVR_N

0

1

2

3

4

5

6

7

8

16

32

64

128

256

512

1024

表7-4. Threshold and Monitoring Period for Embedded Overrange Indicators in Dual-Channel

Decimation Modes

OVERRANGE

INDICATOR

ASSOCIATED

THRESHOLD

OVERRANGE STATUS MONITORING PERIOD

DECIMATION TYPE

EMBEDDED IN

(ADC Samples)

Channel A in-phase (I)

samples

ORA0

ORA1

ORB0

ORB1

OVR_T0

OVR_T1

OVR_T0

OVR_T1

Complex down-conversion

2^{OVR_N (1)}

Channel A quadrature

(Q) samples

2^{OVR_N (1)}

Channel B in-phase (I)

samples

Channel B quadrature

(Q) samples

(1) OVR_N is the monitoring period register setting.

Typically, the OVR_T0 threshold can be set near the full-scale value (228 for example). When the threshold is

triggered, a typical system can turn down the system gain to avoid clipping. The OVR_T1 threshold can be set

much lower. For example, the OVR_T1 threshold can be set to 64 (peak input voltage of −12 dBFS). If the input

signal is strong, the OVR_T1 threshold is tripped occasionally. If the input is quite weak, the threshold is never

tripped. The downstream logic device monitors the OVR_T1 bit. If OVR_T1 stays low for an extended period of

time, then the system gain can be increased until the threshold is occasionally tripped (meaning the peak level of

the signal is above −12 dBFS).

7.3.3.5 Code Error Rate (CER)

ADC cores can generate bit errors within a sample, often called code errors (CER) or referred to as sparkle

codes, resulting from metastability caused by non-ideal comparator limitations. The device uses a unique ADC

architecture that inherently allows significant code error rate improvements from traditional pipelined flash or

successive approximation register (SAR) ADCs. The code error rate of the device is multiple orders of

magnitude better than what can be achieved in alternative architectures at equivalent sampling rates providing

significant signal reliability improvements.

7.3.4 Temperature Monitoring Diode

A built-in thermal monitoring diode is made available on the TDIODE+ and TDIODE–pins. This diode facilitates

temperature monitoring and characterization of the device in higher ambient temperature environments.

Although the on-chip diode is not highly characterized, the diode can be used effectively by performing a

baseline measurement (offset) at a known ambient or board temperature and creating a linear equation with the

diode voltage slope provided in the Electrical Characteristics: DC Specifications table. Perform offset

measurement with the device unpowered or with the PD pin asserted to minimize device self-heating.

Recommended monitoring devices include the LM95233 device and similar remote-diode temperature

monitoring products from Texas Instruments.

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7.3.5 Timestamp

The TMSTP+ and TMSTP– differential input can be used as a time-stamp input to mark a specific sample

based on the timing of an external trigger event relative to the sampled signal. TIMESTAMP_EN (see the LSB

control bit output register) must be set to use the timestamp feature and output the timestamp data. When

enabled, the LSB of the 12-bit ADC digital output reports the status of the TMSTP± input. In effect, the 12-bit

output sample consists of the upper 11-bits of the 12-bit converter and the LSB of the 12-bit output sample is the

output of a parallel 1-bit converter (TMSTP±) with the same latency as the ADC core. In the 8-bit operating

modes, the LSB of the 8-bit output sample is used to output the timestamp status. The trigger must be applied to

the differential TMSTP+ and TMSTP– inputs. The trigger can be asynchronous to the ADC sampling clock and

is sampled at approximately the same time as the analog input. Timestamp cannot be used when a JMODE with

decimation is selected and instead SYSREF must be used to achieve synchronization through the JESD204C

subclass-1 method for achieving deterministic latency.

7.3.6 Clocking

The clocking subsystem of the device has two input signals, device clock (CLK+, CLK–) and SYSREF

(SYSREF+, SYSREF–). Within the clocking subsystem there is a noiseless aperture delay adjustment (t_AD

adjust), a clock duty cycle corrector and a SYSREF capture block. 图7-2 describes the clocking subsystem.

Duty Cycle

Correction

t_ADAdjust

Clock Distribution

and Synchronization

CLK+

(ADC cores, digital,

JESD204C, etc.)

CLK-

E

RS

A

IN

V

F

_

O

IN

C

_

D

_

D

A

T

D

A

T

SYSREF Capture

Automatic

SYSREF

Calibration

SYSREF+

SYSREF-

SYSREF Windowing

SYSREF_POS SYSREF_SEL

SRC_EN

图7-2. Clocking Subsystem

The device clock is used as the sampling clock for the ADC core as well as the clocking for the digital processing

and serializer outputs. Use a low-noise (low jitter) device clock to maintain high signal-to-noise ratio (SNR) within

the ADC. In dual-channel mode, the analog input signal for each input is sampled on the rising edge of the

device clock. In single-channel mode, both the rising and falling edges of the device clock are used to capture

the analog signal to reduce the maximum clock rate required by the ADC. A noiseless aperture delay adjustment

(t_ADadjust) allows the user to shift the sampling instance of the ADC in fine steps to synchronize multiple

ADC12DJ5200SEs or to fine-tune system latency. Duty cycle correction is implemented in the device to ease the

requirements on the external device clock while maintaining high performance. 表 7-5 summarizes the device

clock interface in dual-channel mode and single-channel mode.

表7-5. Device Clock vs Mode of Operation

MODE OF OPERATION

Dual-channel mode

SAMPLING RATE VS f_CLK

SAMPLING INSTANT

Rising edge

1 × f_CLK

Single-channel mode

2 × f_CLK

Rising and falling edge

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SYSREF is a system timing reference used for JESD204C subclass-1 implementations of deterministic latency.

SYSREF is used to achieve deterministic latency and for multi-device synchronization. SYSREF must be

captured by the correct device clock edge to achieve repeatable latency and synchronization. The

ADC12DJ5200SE includes SYSREF windowing and automatic SYSREF calibration to ease the requirements on

the external clocking circuits and to simplify the synchronization process. SYSREF can be implemented as a

single pulse or as a periodic clock. In periodic implementations, SYSREF must be equal to, or an integer division

of, the local multiframe clock frequency in 8B/10B encoding modes or the local extended multiblock clock

frequency in 64B/66B encoding modes. 方程式 1 is used to calculate valid SYSREF frequencies in 8B/10B

encoding modes and 方程式2 in 64B/66B encoding modes.

R ì f_CLK

f_SYSREF

=

10

ì

F

ì

K

ì

n

(1)

(2)

Rì f_CLK

66ì32ìEìn

f_SYSREF

=

where

• R and F are set by the JMODE setting (see 表7-24)

• f_CLKis the device clock frequency (CLK±)

• K is the programmed multiframe length (see 表7-24 for valid K settings)

• E is the number of multiblocks in an extended multiblock.

• n is any positive integer

7.3.6.1 Noiseless Aperture Delay Adjustment (t_ADAdjust)

The device contains a delay adjustment on the device clock (sampling clock) input path, called t_ADadjust, that

can be used to shift the sampling instance within the device to align sampling instances among multiple devices

or for external interleaving of multiple devices. Further, t_ADadjust can be used for automatic SYSREF calibration

to simplify synchronization; see the Automatic SYSREF Calibration section. Aperture delay adjustment is

implemented in a way that adds no additional noise to the clock path, however a slight degradation in aperture

jitter (t_AJ) is possible at large values of TAD_COARSE because of internal clock path attenuation. The

degradation in aperture jitter can result in minor SNR degradations at high input frequencies (see t_AJin the

Switching Characteristics table). This feature is programmed using TAD_INV, TAD_COARSE, and TAD_FINE in

the DEVCLK timing adjust ramp control register. Setting TAD_INV inverts the input clock resulting in a delay

equal to half the clock period. 表 7-6 summarizes the step sizes and ranges of the TAD_COARSE and

TAD_FINE variable analog delays. All three delay options are independent and can be used in conjunction. All

clocks within the device are shifted by the programmed t_ADadjust amount, which results in a shift of the timing of

the JESD204C serialized outputs and affects the capture of SYSREF.

表7-6. t_ADAdjust Adjustment Ranges

ADJUSTMENT PARAMETER

ADJUSTMENT STEP

DELAY SETTINGS

MAXIMUM DELAY

TAD_INV

1 / (f_CLK× 2)

1

1 / (f_CLK× 2)

See t_TAD(STEP)in the Switching

Characteristics table

See t_TAD(MAX)in the Switching

Characteristics table

TAD_COARSE

TAD_FINE

256

See t_TAD(STEP)in the Switching

Characteristics table

See t_TAD(MAX)in the Switching

Characteristics table

To maintain timing alignment between converters, stable and matched power-supply voltages and device

temperatures must be provided.

Aperture delay adjustment can be changed on-the-fly during normal operation but may result in brief upsets to

the JESD204C data link. Use TAD_RAMP to reduce the probability of the JESD204C link losing synchronization;

see the Aperture Delay Ramp Control section.

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7.3.6.2 Aperture Delay Ramp Control (TAD_RAMP)

The ADC12DJ5200SE contains a function to gradually adjust the t_ADadjust setting towards the newly written

TAD_COARSE value. This functionality allows the t_ADadjust setting to be adjusted with minimal internal clock

circuitry glitches. The TAD_RAMP_RATE parameter allows either a slower (one TAD_COARSE LSB per 256

t_CLKcycles) or faster ramp (four TAD_COARSE LSBs per 256 t_CLKcycles) to be selected. The TAD_RAMP_EN

parameter enables the ramp feature and any subsequent writes to TAD_COARSE initiate a new cramp.

7.3.6.3 SYSREF Capture for Multi-Device Synchronization and Deterministic Latency

The clocking subsystem is largely responsible for achieving multi-device synchronization and deterministic

latency. The ADC12DJ5200SE uses the JESD204C subclass-1 method to achieve deterministic latency and

synchronization. Subclass 1 requires that the SYSREF signal be captured by a deterministic device clock (CLK±)

edge at each system power-on and at each device in the system. This requirement imposes setup and hold

constraints on SYSREF relative to CLK±, which can be difficult to meet at giga-sample clock rates over all

system operating conditions. The device includes a number of features to simplify this synchronization process

and to relax system timing constraints:

• The device uses dual-edge sampling (DES) in single-channel mode to reduce the CLK± input frequency by

half and double the timing window for SYSREF (see 表7-5)

• A SYSREF position detector (relative to CLK±) and selectable SYSREF sampling position aid the user in

meeting setup and hold times over all conditions; see the SYSREF Position Detector section

• Easy-to-use automatic SYSREF calibration uses the aperture timing adjust block (t_ADadjust) to shift the ADC

sampling instance based on the phase of SYSREF (rather than adjusting SYSREF based on the phase of the

ADC sampling instance); see the Automatic SYSREF Calibration section

7.3.6.3.1 SYSREF Position Detector and Sampling Position Selection (SYSREF Windowing)

The SYSREF windowing block is used to first detect the position of SYSREF relative to the CLK± rising edge

and then to select a desired SYSREF sampling instance, which is a delay version of CLK±, to maximize setup

and hold timing margins. In many cases a single SYSREF sampling position (SYSREF_SEL) is sufficient to meet

timing for all systems (device-to-device variation) and conditions (temperature and voltage variations). However,

this feature can also be used by the system to expand the timing window by tracking the movement of SYSREF

as operating conditions change or to remove system-to-system variation at production test by finding a unique

optimal value at nominal conditions for each system.

This section describes proper usage of the SYSREF windowing block. First, apply the device clock and SYSREF

to the device. The location of SYSREF relative to the device clock cycle is determined and stored in the

SYSREF_POS bits of the SYSREF capture position register. ADC12DJ5200SE must see at least 3 rising edges

of SYSREF before the SYSREF_POS output is valid. Each bit of SYSREF_POS represents a potential SYSREF

sampling position. If a bit in SYSREF_POS is set to 1, then the corresponding SYSREF sampling position has a

potential setup or hold violation. Upon determining the valid SYSREF sampling positions (the positions of

SYSREF_POS that are set to 0) the desired sampling position can be chosen by setting SYSREF_SEL in the

clock control register 0 to the value corresponding to that SYSREF_POS position. In general, the middle

sampling position between two setup and hold instances is chosen. Ideally, SYSREF_POS and SYSREF_SEL

are performed at the nominal operating conditions of the system (temperature and supply voltage) to provide

maximum margin for operating condition variations. This process can be performed at final test and the optimal

SYSREF_SEL setting can be stored for use at every system power up. Further, SYSREF_POS can be used to

characterize the skew between CLK± and SYSREF± over operating conditions for a system by sweeping the

system temperature and supply voltages. For systems that have large variations in CLK± to SYSREF± skew, this

characterization can be used to track the optimal SYSREF sampling position as system operating conditions

change. In general, a single value can be found that meets timing over all conditions for well-matched systems,

such as those where CLK± and SYSREF± come from a single clocking device.

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备注

SYSREF_SEL must be set to 0 when using automatic SYSREF calibration; see the Automatic

SYSREF Calibration section.

The step size between each SYSREF_POS sampling position can be adjusted using SYSREF_ZOOM. When

SYSREF_ZOOM is set to 0, the delay steps are coarser. When SYSREF_ZOOM is set to 1, the delay steps are

finer. See the Switching Characteristics table for delay step sizes when SYSREF_ZOOM is enabled and

disabled. In general, SYSREF_ZOOM = 1 is recommended to be used above f_CLK= 3GHz and SYSREF_ZOOM

= 0 below f_CLK= 3GHz. Bits 0 and 23 of SYSREF_POS are always be set to 1 because there is insufficient

information to determine if these settings are close to a timing violation, although the actual valid window can

extend beyond these sampling positions. The value programmed into SYSREF_SEL is the decimal number

representing the desired bit location in SYSREF_POS. 表 7-7 lists some example SYSREF_POS readings and

the optimal SYSREF_SEL settings. Although 24 sampling positions are provided by the SYSREF_POS status

register, SYSREF_SEL only allows selection of the first 16 sampling positions, corresponding to SYSREF_POS

bits 0 to 15. The additional SYSREF_POS status bits are intended only to provide additional knowledge of the

SYSREF valid window. In general, lower values of SYSREF_SEL are selected because of delay variation over

supply voltage, however in the fourth example a value of 15 provides additional margin and can be selected

instead.

表7-7. Examples of SYSREF_POS Readings and SYSREF_SEL Selections

SYSREF_POS[23:0]

OPTIMAL SYSREF_SEL

0x02E[7:0]

(Largest Delay)

0x02C[7:0]⁽¹⁾

(Smallest Delay)

0x02D[7:0]⁽¹⁾

SETTING

b10000000

b10011000

b10000000

b10001100

b0110000 0

b00000000

b01100000

b00000011

b01100011

b00011001

b00110001

b0 0000001

b00000001

b00011001

8 or 9

12

6 or 7

4 or 15

6

(1) Red coloration indicates the bits that are selected, as given in the last column of this table.

7.3.6.3.2 Automatic SYSREF Calibration

The ADC12DJ5200SE has an automatic SYSREF calibration feature to alleviate the often challenging setup and

hold times associated with capturing SYSREF for giga-sample data converters. Automatic SYSREF calibration

uses the t_ADadjust feature to shift the device clock to maximize the SYSREF setup and hold times or to align the

sampling instance based on the SYSREF rising edge.

The device must have a proper device clock applied and be programmed for normal operation before starting the

automatic SYSREF calibration. When ready to initiate automatic SYSREF calibration, a continuous SYSREF

signal must be applied. SYSREF must be a continuous (periodic) signal when using the automatic SYSREF

calibration. Start the calibration process by setting SRC_EN high in the SYSREF calibration enable register after

configuring the automatic SYSREF calibration using the SRC_CFG register. Upon setting SRC_EN high, the

device searches for the optimal t_ADadjust setting until the device clock falling edge is internally aligned to the

SYSREF rising edge. TAD_DONE in the SYSREF calibration status register can be monitored to make sure the

SYSREF calibration has finished. By aligning the device clock falling edge with the SYSREF rising edge,

automatic SYSREF calibration maximizes the internal SYSREF setup and hold times relative to the device clock

and also sets the sampling instant based on the SYSREF rising edge. After the automatic SYSREF calibration

finishes, the rest of the startup procedure can be performed to finish bringing up the system.

For multi-device synchronization, the SYSREF rising edge timing must be matched at all devices and therefore

trace lengths must be matched from a common SYSREF source to each device. Any skew between the

SYSREF rising edge at each device results in additional error in the sampling instance between devices;

however, repeatable deterministic latency from system startup to startup through each device must still be

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achieved. No other design requirements are needed to achieve multi-device synchronization as long as a proper

elastic buffer release point is chosen in the JESD204C receiver.

图 7-3 provides a timing diagram of the SYSREF calibration procedure. The optimized setup and hold times are

shown as t_SU(OPT)and t_H(OPT), respectively. Device clock and SYSREF are referred to as internal in this diagram

because the phase of the internal signals are aligned within the device and not to the external (applied) phase of

the device clock or SYSREF.

Sampled Input Signal

Internal Unadjusted

Device Clock

Internal Calibrated

Device Clock

t_TAD(SRC)

Internal SYSREF

t_CAL(SRC)

t_H(OPT)

t_SU(OPT)

Before calibration, device clock falling edge does

not align with SYSREF rising edge

SRC_EN

(SPI register bit)

Calibration

enabled

After calibration, device clock falling edge

aligns with SYSREF rising edge

TAD_DONE

(SPI register bit)

Calibration

finished

图7-3. SYSREF Calibration Timing Diagram

When finished, the t_ADadjust setting found by the automatic SYSREF calibration can be read from SRC_TAD in

the SYSREF calibration status register. After calibration, the system continues to use the calibrated t_ADadjust

setting for operation until the system is powered down. However, if desired, the user can then disable the

SYSREF calibration and fine-tune the t_ADadjust setting according to the systems needs. Alternatively, the use of

the automatic SYSREF calibration can be done at product test (or periodic recalibration) of the optimal t_ADadjust

setting for each system. This value can be stored and written to the TAD register (TAD_INV, TAD_COARSE, and

TAD_FINE) upon system startup.

Do not run the SYSREF calibration when the ADC calibration (foreground or background) is running. If

background calibration is the desired use case, disable the background calibration when the SYSREF calibration

is used, then reenable the background calibration after TAD_DONE goes high. SYSREF_SEL in the clock

control register 0 must be set to 0 when using SYSREF calibration.

SYSREF calibration searches the TAD_COARSE delays using both noninverted (TAD_INV = 0) and inverted

clock polarity (TAD_INV = 1) to minimize the required TAD_COARSE setting to minimize loss on the clock path

to reduce aperture jitter (t_AJ).

7.3.7 Programmable FIR Filter (PFIR)

The output of the ADCs can be sent through programmable finite-impulse-response (PFIR) digital filter for

equalization of the frequency response. The filter can be setup in a few modes of operation to allow independent

equalization of each channel in dual channel mode, equalization in single channel mode or as a time-varying

filter in dual channel mode (such as for I/Q correction). The various PFIR operating modes are given in 表7-8.

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PFIR Mode

表7-8. PFIR Operating Modes

Center Tap

Resolution

Center Tap LSB

Weight

Non-Center Tap

Resolution

Non-Center Tap LSB

Filter Coefficients

Weight

Dual Channel

Equalization

18 bits

2^-16

12 bits

2^-10, 2^-11...2^-16

9 per channel

9

Single Channel

Equalization

9 per coefficient set, 2

coefficient sets

Time Varying Filter

Programming information for the various PFIR modes is given in 表 7-9. The coefficients are programmed into

the PFIR_Ax and PFIR_Bx registers.

表7-9. Programmable FIR Filter Mode Programming

PFIR Mode

PFIR Disabled

PFIR_MODE

PFIR_SHARE

PFIR_MERGE

0

2

X

0

1

0

X

0

1

Dual Channel Equalization

Single Channel Equalization

Time Varying Filter

7.3.7.1 Dual Channel Equalization

When the ADC is operating in dual channel mode (based on the JMODE setting) then the PFIR filter can be set

in dual channel equalization mode. This mode allows independent frequency equalization of the two ADC

channels. The filter for each channel consists of 9 coefficients that can be independently set. The center tap for

each filter has a resolution of 18 bits and the LSB has a weight of 2^-16. The non-center taps have a resolution of

12-bits with programmable LSB weight of 2^-10, 2^-11, 2^-12, 2^-13, 2^-14, 2^-15or 2^-16. All non-center taps have the

same LSB weight. The block diagram for dual channel equalization is shown in 图7-4.

FIR A

(9 taps)

ADC A

DDC A

DDC Block

DDC B

JESD204C

Interface

PFIR Block

FIR B

(9 taps)

ADC B

图7-4. Dual Channel Equalization PFIR Block Diagram

7.3.7.2 Single Channel Equalization

When the ADC is operating in single channel mode (based on the JMODE setting) then the PFIR filter can be set

in single channel equalization mode. This mode allows frequency equalization of the ADC. The filter consists of 9

coefficients that can be independently set. The center tap of the filter has a resolution of 18 bits and the LSB has

a weight of 2^-16. The non-center taps have a resolution of 12-bits with programmable LSB weight of 2^-10, 2^-11

,

2^-12, 2^-13, 2^-14, 2^-15or 2^-16. All non-center taps have the same LSB weight. The block diagram for single channel

equalization is shown in 图7-4.

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FIR

(9 taps)

ADC A

DDC

JESD204C

Interface

PFIR Block

DDC Block

ADC B

SINGLE_INPUT

图7-5. Single Channel Equalization PFIR Block Diagram

7.3.7.3 Time Varying Filter

When the ADC is operating in dual-input single channel mode (based on the JMODE setting and

SINGLE_INPUT setting) then the PFIR filter can be set in time varying filter mode. This mode enables a time

varying filter with two coefficient sets that are alternated between on a per sample basis. Each coefficient set

consists of 9 coefficients that can be independently set. The center tap of the filter has a resolution of 18 bits and

the LSB has a weight of 2^-16. The non-center taps have a resolution of 12-bits with programmable LSB weight of

2^-10, 2^-11, 2^-12, 2^-13, 2^-14, 2^-15or 2^-16. All non-center taps have the same LSB weight. The block diagram for time

varying filter mode is shown in 图 7-6 and an alternate block diagram is given in 图 7-7 which shows the

equivalent filter in an I/Q correction-type topology.

From coefficient set A

Uses coefficient set A

Uses coefficient set B

From coefficient set B

Filter input = A_I0,B_I0,A_I1,B_I1,A_I2,B_I2,A_I3,B_I3,A_I4,B_I4

Filter output = A_O0,B_O0,A_O1,B_O1,A_O2,B_O2,A_O3,B_O3,A_O4,B_O4

Time Varying FIR

(9 taps, 2 sets)

ADC A

DDC

Sample

Interleave

Sample

Deinterleave

JESD204C

Interface

PFIR Block

DDC Block

ADC B

图7-6. Time Varying Filter PFIR Block Diagram

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FIR A

(5 even taps)

FIR A

(4 odd taps)

ADC A

DDC

Sample

Interleave

JESD204C

DDC Block

PFIR Block

Interface

FIR B

(4 odd taps)

ADC B

z^-1

FIR B

(5 even taps)

图7-7. Alternate I/Q Correction-Type Filter Block Diagram

7.3.8 Digital Down Converters (DDC)

After converting the analog voltage to a digital value, the digitized sample can either be sent directly to the

JESD204C interface block (DDC bypass) or sent to the digital down converter (DDC) block for frequency

conversion and decimation. The DDC block can be used in both dual channel mode and single channel mode.

Frequency conversion and decimation allows a specific frequency band to be selected and reduces the amount

of data sent over the data interface. The DDC first mixes the desired band to complex baseband (0 Hz) by

performing a complex mixing operating using the numerically-controlled oscillator (NCO) as the local oscillator

(LO). The DDC then low-pass filters the baseband signal to remove unwanted frequency images and any signals

that may potentially alias into the desired band. It finally decimates (down samples) the data to reduce the data

rate. Note that the filtering and decimation operations are actually performed as a single operation in the device.

The DDC is designed with sufficient precision such that the digital processing does not degrade the noise

spectral density (NSD) performance of the ADC. 图 7-8 illustrates the DDC block in the device in dual channel

mode while 图 7-9 shows the DDC block of the device in single channel mode. In dual channel mode, the input

data for each DDC can be selected to come from either ADC channel A or ADC channel B by using the

DIG_BIND_x SPI registers. Channel B has the same structure with the input data selected by DIG_BIND_B and

the NCO selection mux controlled by pins NCOB[1:0] or through CSELB[1:0]. Only one DDC is available for use

in single channel mode.

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DDC

NCO Bank A

MUX

NCOA[1:0]

or CSELA[1:0]

Real

12-bit @ Fs

Complex

15-bit @ Fs

Complex

15-bit @ Fs/D

ADC

Channel A

D

JESD204C

Link A

Complex

Mixer

DIG_BIND_A

Real

12-bit @ Fs

DDC Bypass

JMODE

DDC

NCO Bank B

MUX

JMODE

NCOA[1:0]

or CSELA[1:0]

Real

12-bit @ Fs

Complex

15-bit @ Fs

Complex

15-bit @ Fs/D

D

ADC

Channel B

JESD204C

Link B

Complex

Mixer

DIG_BIND_B

Real

12-bit @ Fs

DDC Bypass

JMODE

图7-8. Digital Down Conversion Block in Dual Channel Mode

DDC

NCO Bank A

ADC

Channel A

NCOA[1:0]

or CSELA[1:0]

JESD204C

Link A

MUX

Real

Complex

12-bit @ Fs

15-bit @ Fs

15-bit @ Fs/D

D

Complex

Mixer

JMODE

Real

12-bit @ Fs

DDC Bypass

JMODE

CLK

ADC

Channel B

JESD204C

Link B

图7-9. Digital Down Conversion Block in Single Channel Mode

7.3.8.1 Numerically-Controlled Oscillator and Complex Mixer

The DDC contains a complex numerically-controlled oscillator (NCO) and a complex mixer. 方程式 3 shows the

complex exponential sequence generated by the oscillator.

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x[n] = e^jωn

(3)

The frequency (ω) is specified by a 32-bit register setting (see the Basic NCO Frequency Setting Mode section

and the Rational NCO Frequency Setting Mode section). The complex exponential sequence is multiplied by the

real input from the ADC to mix the desired carrier to a frequency equal to f_IN+ f_NCO, where f_INis the analog input

frequency after aliasing (in undersampling systems) and f_NCOis the programmed NCO frequency.

7.3.8.1.1 NCO Fast Frequency Hopping (FFH)

Fast frequency hopping (FFH) is made possible by each DDC having four independent NCOs that can be

controlled by the NCOA0 and NCOA1 pins for DDC A and the NCOB0 and NCOB1 pins for DDC B. Each NCO

has independent frequency settings (see the Basic NCO Frequency Setting Mode section) and initial phase

settings (see the NCO Phase Offset Setting section) that can be set independently. Further, all NCOs have

independent phase accumulators that continue to run when the specific NCO is not selected, allowing the NCOs

to maintain their phase between selection so that downstream processing does not need to perform carrier

recovery after each hop, for instance.

NCO hopping occurs when the NCO GPIO pins change state. The pins are controlled asynchronously and

therefore synchronous switching is not possible. Associated latencies are demonstrated in 图 7-10, where t_TX

and t_ADCare provided in the Switching Characteristics table. All latencies in 表7-10 are approximations only.

DDC Block

NCO Bank

t_GPIO-MIXER

t_MIXER-TX

MUX

NCOx[1:0]

Dx0+/-

Dx1+/-

Dx2+/-

INx+

INx-

ADC

N

JESD204C

Complex

Mixer

Decimate-by-N

(based on JMODE)

Dx7+/-

t_ADC-MIXER

图7-10. NCO Fast Frequency Hopping Latency Diagram

表7-10. NCO Fast Frequency Hopping Latency Definitions

LATENCY PARAMETER

VALUE OR CALCULATION

UNITS

t_GPIO-MIXER

~45 to ~68

t_CLKcycles

t_ADC-MIXER

~37

t_MIXER-TX

(t_TX+ t_ADC) –t_ADC-MIXER

7.3.8.1.2 NCO Selection

Within each channel DDC, four different frequency and phase settings are available for use. Each of the four

settings use a different phase accumulator within the NCO. Because all four phase accumulators are

independent and continuously running, rapid switching between different NCO frequencies is possible allowing

for phase coherent frequency hopping.

The specific frequency-phase pair used for each channel is selected through the NCOA[1:0] or NCOB[1:0] input

pins when CMODE is set to 1. Alternatively, the selected NCO can be chosen through SPI by CSELA for DDC A

and CSELB for DDC B by setting CMODE to 0 (default). The logic table for NCO selection is provided in 表 7-11

for both the GPIO and SPI selection options.

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表7-11. Logic Table for NCO Selection Using GPIO or SPI

NCO SELECTION

NCO 0 using GPIO

NCO 1 using GPIO

NCO 2 using GPIO

NCO 3 using GPIO

NCO 0 using SPI

NCO 1 using SPI

NCO 2 using SPI

NCO 3 using SPI

CMODE

NCOx1

NCOx0

CSELx[1]

CSELx[0]

1

0

1

X

0

1

X

0

1

0

1

0

1

X

The frequency for each phase accumulator is programmed independently through the FREQAx, FREQBx (x = 0

to 3) and, optionally, NCO_RDIV register settings. The phase offset for each accumulator is programmed

independently through the PHASEAx and PHASEBx (x = 0 to 3) register settings.

7.3.8.1.3 Basic NCO Frequency Setting Mode

In basic NCO frequency-setting mode (NCO_RDIV = 0x0000), the NCO frequency setting is set by the 32-bit

register value, FREQAx and FREQBx (x = 0 to 3). The NCO frequency for DDC A can be calculated using 方程

式 4, where FREQAx can be replaced by FREQBx to calculate the NCO frequency for DDC B. FREQAx and

FREQBx can be considered either a 2's complement number (–2147483648 to 2147483647) or as an offset

binary number (0 to 4294967295).

ƒ_(NCO)= FREQAx × 2^–32× ƒ_(DEVCLK)(x = 0 –3)

(4)

备注

Changing the FREQAx and FREQBx register settings during operation results in a non-deterministic

NCO phase. If deterministic phase is required, the NCOs must be resynchronized; see the NCO

Phase Synchronization section.

7.3.8.1.4 Rational NCO Frequency Setting Mode

In basic NCO frequency mode, the frequency step size is very small and many frequencies can be synthesized,

but sometimes an application requires very specific frequencies that fall between two frequency steps. For

example with ƒ_Sequal to 2457.6 MHz and a desired ƒ_(NCO)equal to 5.02 MHz, the value for FREQAx is

8773085.867. Truncating the fractional portion results in an ƒ_(NCO)equal to 5.0199995 MHz, which is not the

desired frequency.

To produce the desired frequency, the NCO_RDIV parameter is used to force the phase accumulator to arrive at

specific frequencies without error. First, select a frequency step size (ƒ_(STEP)) that is appropriate for the NCO

frequency steps required. The typical value of ƒ_(STEP)is 10 kHz. Next, use 方程式 5 to program the NCO_RDIV

value.

¦

(

/ ¦_STEP

)

DEVCLK

NCO_RDIV =

64

(5)

The result of 方程式 5 must be an integer value. If the value is not an integer, adjust either of the parameters

until the result is an integer value.

For example, select a value of 1920 for NCO_RDIV.

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备注

NCO_RDIV values larger than 8192 can degrade the NCO SFDR performance and are not

recommended.

Now use 方程式6 to calculate the FREQAx register value.

FREQAx = round 2³²´ ¦_NCO/ ¦_DEVCLK

(

)

(6)

Alternatively, the following equations can be used:

ƒ_(NCO)

N =

ƒ_(STEP)

(7)

(8)

FREQAx = round 2²⁶´ N / NCO_RDIV

(

)

表7-12 lists common values for NCO_RDIV in 10-kHz frequency steps.

表7-12. Common NCO_RDIV Values (For 10-kHz Frequency Steps)

f_CLK(MHz)

2457.6

NCO_RDIV

3840

1966.08

1600

3072

2500

1474.56

1228.8

2304

1920

7.3.8.1.5 NCO Phase Offset Setting

The NCO phase-offset setting for each NCO is set by the 16-bit register value PHASEAx and PHASEBx (where

x = 0 to 3). The value is left-justified into a 32-bit field and then added to the phase accumulator.

Use 方程式9 to calculate the phase offset in radians.

7.3.8.1.6

Φ(rad) = PHASEA/Bx × 2^–16× 2 × π(x = 0 to 3)

(9)

7.3.8.1.7 NCO Phase Synchronization

The NCOs must be synchronized after setting or changing the value of FREQAx or FREQBx. NCO

synchronization is performed when the JESD204C link is initialized or by SYSREF, based on the settings of

NCO_SYNC_ILA and NCO_SYNC_NEXT. The procedures are as follows for the JESD204C initialization

procedure and the SYSREF procedure for both DC-coupled and AC-coupled SYSREF signals.

NCO synchronization using the JESD204C SYNC signal ( SYNCSE or TMSTP±). Although the 64B/66B

encoding modes do not use the SYNC signal to initialize the JESD204C link, it can still be used for NCO

synchronization with this method:

1. The device must be programmed for normal operation

2. Set NCO_SYNC_ILA to 1 to enable NCO synchronization using the SYNC signal

3. Set JESD_EN to 0

4. Program FREQAx, FREQBx, PHASEAx, and PHASEBx to the desired settings

5. In the JESD204C receiver (logic device), deassert the SYNC signal by setting SYNC high

6. Set JESD_EN to 1

7. Assert the SYNC signal by setting SYNC low in the JESD204C receiver. This start the code group

synchronization (CGS) process in 8B/10B encoding modes or arms the trigger in 64B/66B encoding modes.

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8. After achieving CGS (or when ready to synchronize), deassert the SYNC signal by setting SYNC high at the

same time for all ADCs to synchronize the NCOs in each ADC. The SYNC signal must meet the required

setup and hold times (as specified in the Timing Requirements table)

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NCO synchronization using SYSREF (DC-coupled):

1. The device must be programmed for normal operation

2. Set JESD_EN to 1 to start the JESD204C link (the SYNC signal can respond as normal during the CGS

process)

3. Program FREQAx, FREQBx, PHASEAx, and PHASEBx to the desired settings

4. Verify that SYSREF is disabled (held low)

5. Arm NCO synchronization by setting NCO_SYNC_NEXT to 1

6. Issue a single SYSREF pulse to all ADCs to synchronize NCOs within all devices

NCO synchronization using SYSREF (AC-coupled):

1. The device must be programmed for normal operation

2. Set JESD_EN to 1 to start the JESD204C link (the SYNC signal can respond as normal during the CGS

process)

3. Program FREQAx, FREQBx, PHASEAx, and PHASEBx to the desired settings

4. Run SYSREF continuously

5. Arm NCO synchronization by setting NCO_SYNC_NEXT to 1 at the same time at all ADCs by timing the

rising edge of SCLK for the last data bit (LSB) at the end of the SPI write so that the SCLK rising edge

occurs after a SYSREF rising edge and early enough before the next SYSREF rising edge so that the trigger

is armed before the next SYSREF rising edge (a long SYSREF period is recommended)

6. NCOs in all ADCs are synchronized by the next SYSREF rising edge

7.3.8.2 Decimation Filters

The decimation filters are arranged to provide a programmable overall decimation of 4 or 8. All decimation filters

operate on complex data (from the complex digital mixer) and the outputs have a resolution of 15 bits. The

decimation filters are implemented as linear phase finite impulse response (FIR) filters. 表 7-13 lists the effective

output sample rates, available signal bandwidths, output formats, and stop-band attenuation for each decimation

mode.

表7-13. Output Sample Rates and Signal Bandwidths

ƒ_(DEVCLK)

DECIMATION

SETTING

OUTPUT FORMAT

OUTPUT RATE MAX ALIAS PROTECTED SIGNAL

STOP-BAND

ATTENUATION

PASS-BAND

RIPPLE

(MSPS)

BANDWIDTH (MHz)

No decimation (DDC

bypass)

Real signal,

12-bit data

< ±0.001 dB

ƒ_(DEVCLK)

ƒ_(DEVCLK)/ 2

—

Complex signal,

15-bit data

Decimate-by-4

Decimate-by-8

Decimate-by-16

Decimate-by-32

> 90 dB

ƒ_(DEVCLK)/ 4

ƒ_(DEVCLK)/ 8

ƒ_(DEVCLK)/ 16

ƒ_(DEVCLK)/ 32

0.8 × ƒ_(DEVCLK)/ 4

0.8 × ƒ_(DEVCLK)/ 8

0.8 × ƒ_(DEVCLK)/ 16

0.8 × ƒ_(DEVCLK)/ 32

Complex signal,

15-bit data

Complex signal,

15-bit data

Complex signal,

15-bit data

图 7-11 to 图 7-18 provide the composite decimation filter responses. The black portion of the trace shows the

pass-band region, or alias-protected region, of the response. The red portion of the trace shows the transition

region of the response as well as any frequency regions that will alias into the transition region. The transition

region is not alias protected and therefore desired signals should only be placed in the pass-band region of the

filter response. The blue portion of the trace shows the frequency regions that will alias into the pass-band after

decimation and therefore define the stop-band region of the frequency response. The stop-band attenuation is

defined to sufficient filter any undesired images or signals to prevent them from aliasing into the desired pass-

band. Use analog filtering before the analog inputs (INA or INB) for additional attenuation of signals that fall

within this band or to sufficiently reduce signals at the ADC inputs that may produce harmonics, interleaving

spurs or other undesired spurious signals that will alias into the desired signal band (before the complex mixing

and decimation operations).

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0.001

0.0005

0

-20

Passband

Transition Band

Passband

Transition Band

Aliasing Band

-40

-60

-80

-0.0005

-0.001

-100

-120

0

0.02

0.04

0.06

0.08

Normalized Frequency (Fs)

0.1

0.12

0

0.1

0.2 0.3

Normalized Frequency (Fs)

0.4

0.5

h4co

图7-12. Decimate-by-4 Composite Zoomed Pass-

图7-11. Decimate-by-4 Composite Response

Band Response

0.001

0

Passband

Transition Band

Passband

Transition Band

Aliasing Band

-20

-40

0.0005

0

-60

-80

-0.0005

-0.001

-100

-120

0

0.01

0.02

0.03

0.04

Normalized Frequency (Fs)

0.05

0.06

0

0.1

0.2 0.3

Normalized Frequency (Fs)

0.4

0.5

h8co

图7-14. Decimate-by-8 Composite Zoomed Pass-

图7-13. Decimate-by-8 Composite Response

Band Response

0.001

10

Passband

Transition Band

Passband

Transition Band

Aliasing Band

-10

-30

0.0005

-50

-70

0

-90

-0.0005

-0.001

-110

-130

0

0.005

0.01

0.015

0.02

Normalized Frequency (Fs)

0.025

0.03

0

0.1

0.2 0.3

Normalized Frequency (Fs)

0.4

0.5

h16c

图7-16. Decimate-by-16 Composite Zoomed Pass-

图7-15. Decimate-by-16 Composite Response

Band Response

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0.001

0.0005

0

Passband

Transition Band

Aliasing Band

-20

-40

-60

-80

-0.0005

-0.001

-100

-120

0

0.0025

0.005

0.0075

0.01

Normalized Frequency (Fs)

0.0125

0.015

0.1

0.2 0.3

Normalized Frequency (Fs)

0.4

0.5

h32c

图7-18. Decimate-by-32 Composite Zoomed Pass-

图7-17. Decimate-by-32 Composite Response

Band Response

For maximum efficiency, a group of high-speed filter blocks are implemented with specific blocks used for each

decimation setting to achieve the composite responses illustrated in 图 7-11 to 图 7-18. 表 7-14 describes the

combination of filter blocks used for each decimation setting and 表 7-15 lists the coefficient details and

decimation factor of each filter block. The coefficients are symmetric with the center tap indicated by bold text.

表7-14. Decimation Mode Filter Usage

DECIMATION SETTING

FILTER BLOCKS USED (Listed in Order of Operation)

4

8

CS40, CS80

CS20, CS40, CS80

16

32

CS10, CS20, CS40, CS80

CS5, CS10, CS20, CS40, CS80

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表7-15. Filter Coefficient Details

FILTER COEFFICIENT SET (Decimation Factor of Filter, Scale factor)

CS10 (2, 2^-11CS20 (2, 2^-14CS40 (2, 2^-17

–327

CS5 (2, 2^-5

)

CS80 (2, 2^-19

)

109

0

109

0

–1

0

–1

0

–65

0

–65

0

–327

0

–37

0

2231

0

9

577

1024

577

2231

0

118

0

–837

0

–837

0

16

0

4824

8192

4824

–8881

0

–8881

0

–291

0

39742

65536

39742

612

0

–1159

0

2031

0

2031

0

–3356

0

–3356

0

5308

0

5308

0

–8140

0

–8140

0

12284

0

12284

0

–18628

0

–18628

0

29455

0

29455

0

–53191

0

–53191

0

166059

262144

166059

7.3.8.3 Output Data Format

The DDC output data consists of 15-bit complex data plus the two overrange threshold-detection control bits.表

7-16 shows the data output format for the DDC modes.

表7-16. Complex Decimation Output Sample Format

16-BIT OUTPUT WORD

I/Q

SAMPLE

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

I

DDC in-phase (I) 15-bit output data

DDC quadrature (Q) 15-bit output data

OVR_T0

OVR_T1

Q

7.3.8.4 Decimation Settings

7.3.8.4.1 Decimation Factor

The decimation setting is adjustable over the following settings and is set by the JMODE parameter. See 表7-24

for the available JMODE values and the corresponding decimation settings.

• DDC Bypass: No decimation, real output

• Decimate-by-4: Complex output

• Decimate-by-8: Complex output

• Decimate-by-16: Complex output

• Decimate-by-32: Complex output

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7.3.8.4.2 DDC Gain Boost

The DDC gain boost (see the DDC configuration register) provides additional gain through the DDC block.

Setting BOOST to 1 sets the total decimation filter chain gain to 6.02 dB. With a setting of 0, the total decimation

filter chain has a 0-dB gain. Only use this setting when the negative image of the input signal is filtered out by

the decimation filters, otherwise clipping may occur. There is no reduction in analog performance when gain

boost is enabled or disabled, but care must be taken to understand the reference output power for proper

performance calculations.

7.3.9 JESD204C Interface

The ADC12DJ5200SE uses a JESD204C high-speed serial interface for data converters to transfer data from

the ADC to the receiving logic device. Many of the available JESD204C output formats are backwards

compatible with existing JESD204B receivers, including many of the JESD204B modes in the ADC12DJ2700

and ADC12DJ3200. The device serialized lanes are capable of operating with both 8B/10B encoding and

64B/66B encoding. A maximum of 16 lanes can be used to lower lane rates for interfacing with speed-limited

logic devices. There are a few differences between 8B/10B and 64B/66B encoded JESD204C, which will be

described throughout this section. 图 7-19 shows a simplified block diagram of the 8B/10B encoded JESD204C

interface and 图7-20 shows a simplified block diagram of the 64B/66B encoded JESD204C interface.

ADC

JESD204C Block

TRANSPORT

LAYER

SCRAMBLER

(Optional)

8B/10B

LINK LAYER

SERDES

TX PHY

ADC

ANALOG

CHANNEL

Logic Device

JESD204B or JESD204C Block

APPLICATION

LAYER

TRANSPORT

LAYER

DESCRAMBLE

(Optional)

8B/10B

LINK LAYER

SERDES

RX PHY

图7-19. Simplified 8B/10B Encoded JESD204C Interface Diagram

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ADC

JESD204C Block

TRANSPORT

LAYER

SCRAMBLER

(Required)

64B/66B

LINK LAYER

SERDES

TX PHY

ADC

ANALOG

CHANNEL

Logic Device

JESD204C Block

APPLICATION

LAYER

TRANSPORT

LAYER

DESCRAMBLE

(Required)

64B/66B

LINK LAYER

SERDES

RX PHY

图7-20. Simplified 64B/66B Encoded JESD204C Interface Diagram

The signals used in the JESD204C interface and the associated device pin names are summarized in 表 7-17.

Most of the signals are common between 8B/10B and 64B/66B encoded JESD204C, except for SYNC which is

not needed to achieve block synchronization for 64B/66B encoding. The sync header encoded into the data

stream is used for block synchronization instead of the SYNC signal.

表7-17. Summary of JESD204C Signals

SIGNAL NAME

PIN NAMES

8B/10B

64B/66B

DESCRIPTION

High-speed serialized data

after 8B/10B or 64B/66B

encoding

Data

Yes

DA[7:0]+, DA[7:0]–, DB[7:0]+, DB[7:0]–)

Link initialization signal

(handshake), toggles low to

start code group

synchronization (CGS)

process. Not used for

64B/66B encoding modes,

unless it is used for NCO

synchronization purposes.

SYNC

Yes

No

SYNCSE, TMSTP+, TMSTP–

ADC sampling clock, also

used for clocking digital logic

and output serializers

Device clock

SYSREF

Yes

CLK+, CLK–

System timing reference used

to deterministically reset the

internal local multiframe clock

(LMFC) or local extended

multiblock clock (LEMC)

counters in each JESD204C

device

SYSREF+, SYSREF–

Not all optional features of JESD204C are supported by the device. The list of features that are supported and

the features that are not supported is provided in 表7-18.

表7-18. Declaration of Supported JESD204C Features

REFERENCE

LETTER IDENTIFIER

FEATURE

SUPPORT IN ADC12DJ5200SE

CLAUSE

clause 8

clause 7

a

b

c

8B/10B link layer

64B/66B link layer

64B/80B link layer

Supported

Not supported

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表7-18. Declaration of Supported JESD204C Features (continued)

REFERENCE

CLAUSE

LETTER IDENTIFIER

FEATURE

SUPPORT IN ADC12DJ5200SE

The command channel when using the

64B/66B or 64B/80B link layer

d

e

f

clause 7

Not supported

Forward error correction (FEC) when using

the 64B/66B or 64B/80B link layer

Supported

CRC3 when using the 64B/66B or 64B/80B

link layer

clause 7

Not supported

A physical SYNC pin when using the 8B/10B

link layer

g

h

clause 8

Supported

Not supported, but subclass 1 transmitter is

compatible with subclass 0 receiver

clause 7, clause 8

Subclass 0

i

j

clause 7, clause 8

clause 8

Subclass 1

Subclass 2

Supported

Not supported

Supported

k

clause 7, clause 8

Lane alignment within a single link

Subclass 1 with support for a lane alignment

on a multipoint link by means of the

MULTIREF signal

l

clause 7, clause 8

Not supported

SYNC interface timing is compatible with

JESD204A

m

n

clause 8

Supported

SYNC interface timing is compatible with

JESD204B

7.3.9.1 Transport Layer

The transport layer takes samples from the ADC output (when decimation is bypassed) or from the DDC output

and maps the samples into octets inside of frames. The transport layer is common to both 8B/10B and 64B/66B

encoding modes. These frames are then mapped onto the available lanes. The mapping of octets into frames

and frames onto lanes is defined by the transport layer settings such as L, M, F, S, N and N'. An octet is 8 bits

(before 8B/10B or 64B/66B encoding), a frame consists of F octets and the frames are mapped onto L lanes.

Samples are N bits, but sent as N' bits across the link. The samples come from M converters and there are S

samples per converter per frame cycle. M is sometimes artificially increased to obtain a more desirable mapping,

for instance lower latency may be achieved with a larger M value for long frames.

There are a number of predefined transport layer modes in the device that are defined in 表 7-24. The high level

configuration parameters for the transport layer in the device are described in 表 7-22. The transport layer mode

is chosen by simply setting the JMODE register setting. For reference, the various configuration parameters for

JESD204C are defined in 表7-23.

The link layer further maps the frames into multiframes when using 8B/10B encoding or blocks, multiblocks and

extended multiblocks when using 64B/66B encoding.

7.3.9.2 Scrambler

A data scrambler is available to scramble the data before transmission across the channel. Scrambling is used

to remove the possibility of spectral peaks in the transmitted data due to repetitive data streams. The scrambler

is optional for 8B/10B encoded modes, however it is mandatory for 64B/66B encoded modes to have sufficient

spectral content for clock recovery and adaptive equalization and to maintain DC balance to allow AC coupling

of the transmitter to the receiver. The scrambler operates on the data before encoding, such that the 8B/10B

scrambler scrambles the 8-bit octets before 10-bit encoding and the 64B/66B scrambler scrambles the 64-bit

block before the sync header insertion (66-bit encoding). The JESD204C receiver automatically synchronizes its

descrambler to the incoming scrambled data stream. For 8B/10B encoding, the initial lane alignment sequence

(ILA) is never scrambled. Scrambling can be enabled by setting SCR (in the JESD204C control register) for

8B/10B encoding modes, but it is automatically enabled in 64B/66B modes. The scrambling polynomial is

different for 8B/10B encoding and 64B/66B encoding schemes as defined by the JESD204C standard.

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7.3.9.3 Link Layer

The link layer serves multiple purposes in JESD204C for both 8B/10B and 64B/66B encoding schemes, however

there are some differences in implementation for each encoding scheme. In general, the link layer's

responsibilities include scrambling of the data (see Scrambler), establishing the code (8B/10B) or block (64B/

66B) boundaries and the multiframe (8B/10B) or multiblock (64B/66B) boundaries, initializing the link, encoding

the data, and monitoring the health of the link. This section is split into an 8B/10B section (8B/10B Link Layer)

and a 64B/66B section (64B/66B Link Layer) to cover the specific implementation for each encoding scheme.

7.3.9.4 8B/10B Link Layer

This section covers the link layer for the 8B/10B encoding operating modes including initialization of the

character, frame and multiframe boundaries, alignment of the lanes, 8B/10B encoding and monitoring of the

frame and multiframe alignment during operation.

7.3.9.4.1 Data Encoding (8B/10B)

The data link layer converts the 8-bit octets from the transport layer into 10-bit characters for transmission across

the link using 8B/10B encoding. 8B/10B encoding for DC balance to allow use of AC-coupling between the

SerDes transmitter and receiver, and makes sure a sufficient number of edge transitions for the receiver to

reliably recover the data clock. 8B/10B encoding also provides some error detection since a single bit error in a

character can result in either not being able to find the 10-bit character in the 8B/10B decoder look up table or an

incorrect character disparity.

7.3.9.4.2 Multiframes and the Local Multiframe Clock (LMFC)

The frames from the transport layer are combined into multiframes which are used in the process of achieving

deterministic latency in subclass 1 implementations. The length of a multiframe is set by the K parameter which

defines the number of frames in a multiframe. JESD204C increases the maximum allowed number of frames per

multiframe (K) from 32 in JESD204B to 256 in JESD204C to allow a longer multi-frame to ease deterministic

latency requirements. The total allowed range of K is defined by the inequality ceil(17/F) ≤ K ≤ min(256,

floor(1024/F)) where ceil() and floor() are the ceiling and floor function, respectively. The local multiframe clock

(LMFC) keeps track of the start and end of a multiframe for deterministic latency and data synchronization

purposes. The LMFC is reset by the SYSREF signal to a deterministic phase in both the transmitter and receiver

to act as a timing reference for deterministic latency. The LMFC clock frequency is given in 方程式 10 where f_BIT

is the serialized bit rate (line rate) of the SerDes interface and F and K are as defined above. The frequency of

SYSREF must equal to or an integer division of f_LMFCwhen using 8B/10B encoding modes if SYSREF is a

continuous signal.

f_LMFC= f_BIT/ (10 × F × K)

(10)

7.3.9.4.3 Code Group Synchronization (CGS)

The first step in initializing the JESD204C link, after the LMFC is deterministically reset by SYSREF, is for the

receiver to find the boundaries of the encoded 10-bit characters sent across each SerDes lane. This process is

called code group synchronization (CGS). The receiver first asserts the SYNC signal (set to logic '0') when ready

to initialize the link. The transmitter responds to the request by sending a stream of K28.5 comma characters.

The receiver aligns its character clock to the K28.5 character sequence and CGS is achieved after successfully

receiving four consecutive K28.5 characters. The receiver deasserts SYNC (set to logic '1') on the next LMFC

edge after CGS is achieved and waits for the transmitter to start the initial lane alignment sequence (ILAS).

7.3.9.4.4 Initial Lane Alignment Sequence (ILAS)

After the transmitter detects the SYNC signal deassert (logic '0' to logic '1' transition), the transmitter waits until

its next LMFC edge to start sending the initial lane alignment sequence (ILAS). The ILAS consists of four

multiframes each containing a predetermined sequence. The receiver searches for the start of the ILAS to

determine the frame and multiframe boundaries. Each multiframe of the ILAS starts with a /R/ character (K28.0)

and ends with a /A/ character (K28.3) and either can be used to detect the boundary of a multiframe. Each lane

starts buffering its data in the elastic buffer once the ILAS reaches the receiver, starting with the /R/ character,

until all receivers have received the ILAS and subsequently release the ILAS from all lanes at the same time to

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align the lanes. The elastic buffer release point is chosen to avoid ambiguity in the release of the data caused by

variation in the data delay (arrival of the ILAS at the receiver for each lane). The second multiframe of the ILAS

contains configuration parameters for the JESD204C link configuration that can be used by the receiver to verify

that the transmitter and receiver configurations match.

7.3.9.4.5 Frame and Multiframe Monitoring

The ADC12DJ5200SE supports frame and multiframe monitoring for verifying the health of the JESD204C link

when using 8B/10B encoding. The scheme changes depending on the use of scrambling. The implementation

when scrambling is disabled is covered first. If the last octet of the current frame matches the last octet of the

previous frame, then the last octet of the current frame is encoded as an /F/ (K28.7) character. If the current

frame is also the last frame of a multiframe, then an /A/ (K28.3) character is used instead. Neither an /F/ or /A/

character should occur in a normal data stream, except when replaced by the transmitter for alignment

monitoring. When the receiver detects an /F/ or /A/ character in the normal data stream the receiver checks to

see if the character occurs at the location expected to be the end of a frame or multiframe. If the character

occurs at a location other than the end of a frame or multiframe then either the transmitter or receiver has

become misaligned. The receiver replaces the alignment character with the appropriate data character upon

reception of a properly aligned /F/ or /A/ character. The appropriate data character is the last octet of the

previously received frame. This scheme increases the probability of an alignment character for non-scrambled

data streams.

The implementation when scrambling is enabled is slightly different since the octets will be randomized. If the

last octet of a frame is 0xFC (before 8B/10B encoding) then the transmitter encodes the octet as an /F/ (/K28.7/)

character. If the last octet of a multiframe is 0x7C (before 8B/10B encoding) then the transmitter encodes the

octet as an /A/ (/K28.3/) character. The location of the /A/ and /F/ characters is monitored to verify proper frame

and multiframe alignment. The receiver replaces the alignment characters by simply replacing an /F/ character

with the 0xFC octet and an /A/ character with the 0x7C octet.

The receiver can report an error if multiple alignment characters occur in the incorrect location or do not occur

when expected. Upon detection of a frame or multiframe misalignment, the receiver should trigger a link

realignment by asserting SYNC. SYSREF should also be reissued to verify that the LMFC in the transmitter and

receiver have proper alignment before restarting the link.

7.3.9.5 64B/66B Link Layer

This section covers the link layer for the 64B/66B encoding operating modes which includes scrambling of the

data, addition of the sync headers (64B/66B encoding), the structure of the block and multiblock, the sync

header, cyclic redundancy checking (CRC), forward error correction (FEC) and link alignment.

7.3.9.5.1 64B/66B Encoding

The frames formed by the transport layer are packed into 8-octet long blocks (64 bits). This 64-bit block is

scrambled and then a 2-bit sync header (SH) is appended to form a 66-bit transmission block. The sync header

is used for block synchronization by marking the end of a block as well as allowing for cyclic redundancy

checking (CRC), forward error correction (FEC) or a command channel. The structure of a block is given in 表

7-19 where SH represents the appended 2-bit sync header.

表7-19. Structure of 64B/66B Block with Sync Header

SH

OCTET0

OCTET1

OCTET2

OCTET3

OCTET4

OCTET5

OCTET6

OCTET7

[0:1]

[2:9]

[10:17]

[18:25]

[26:33]

[34:41]

[42:49]

[50:57]

[58:65]

7.3.9.5.2 Multiblocks, Extended Multiblocks and the Local Extended Multiblock Clock (LEMC)

A multiblock is a 32 block container which consists of a concatenation of 32 blocks. An extended multiblock is a

concatenation of multiple multiblocks, where E defines the number of multiblocks in an extended multiblock. A

frame can be split between blocks and multiblocks, but there must be an integer number of frames in an

extended multiblock. An extended multiblock is only necessary when a multiblock does not have an integer

number of frames. If an extended multiblock is not used, because a multiblock contains an integer number of

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frames, then the E parameter is equal to 1 to indicate that there is one multiblock in an extended multiblock.

Values of E greater than 1 are not supported in ADC12DJ5200SE.

An extended multiblock is analogous to a multiframe in the 8B/10B transport layer. The local extended mutiblock

clock (LEMC) keeps track of the start and end of a multiblock for deterministic latency and data synchronization

purposes in the same way the LMFC tracks the start and end of a multiframe in 8B/10B encoding. The LEMC is

reset by the SYSREF signal to a deterministic phase in both the transmitter and receiver to act as a timing

reference for deterministic latency. The LEMC clock frequency is defined by 方程式 11 where f_BITis the

serialized bit rate (line rate) of the SerDes interface. The frequency of SYSREF must equal to or an integer

division of f_LMFCwhen using 64B/66B encoding modes if SYSREF is a continuous signal.

f_LEMC= f_BIT/ (66 × 32 × E)

(11)

7.3.9.5.3 Block, Multiblock and Extended Multiblock Alignment using Sync Header

The sync header contains two bits that are always opposite of each other (either 01 or 10). The JESD204C

receiver can find the block boundaries by looking for a 66-bit boundary that always contains a 0 to 1 or 1 to 0

transition. Although 0 to 1 and 1 to 0 transitions will occur at other locations in a block, it is impossible for the

sequence to appear at a fixed location, other than the proper sync header location, in successive blocks for a

long period of time. The sync header indicates the start of a block and can be used for block alignment

monitoring. If a 00 or a 11 bit sequence is seen at the assumed sync header location of a block, then block

alignment may have been lost. Multiple occurrences of incorrect sync header bits should trigger a search for the

sync header after sending SYSREF to all devices to reset LEMC alignment.

A sync header ([0:1]) of 01 corresponds to transmission of a 1 while a sync header of 10 corresponds to a

transmission of a 0. The transmitted bit from the sync header of each block of a multiblock are combined into a

32-bit word called the sync header stream. The sync header stream is used to transmit data in parallel with the

user data to synchronize the link by marking the borders of multiblocks and extended multiblocks. In addition, the

sync header stream provides one of either CRC, FEC or a command channel. The device supports CRC-12 and

FEC and does not support CRC-3 or the command channel.

The 32-bit sync header stream always ends with a 00001 bit sequence, called the end-of-multiblock (EoMB)

signal, that indicates the end of a multiblock. For CRC and command channel modes, a 00001 sequence will

never occur in any other location in the sync header stream. For FEC mode, it is possible for a 00001 sequence

to appear in another location within the sync header stream, however it is improbable to see the 00001

sequence in the same location within a sequence of multiple multiblocks. Therefore, in FEC mode it may take

more than one multiblock to find the end of a multiblock. The end of an extended multiblock is found for all

modes by monitoring bit 22 of the sync header stream, the EoEMB bit, which indicates the end of an extended

multiblock when set to a 1. The EoMB (00001) and EoEMB signals, as well as fixed 1s in the sync header

stream for CRC and command channel modes, form the pilot signal of the sync header stream.

The defined format for each form of the sync header stream are defined in the following sections.

7.3.9.5.3.1 Cyclic Redundancy Check (CRC) Mode

The cyclic redundancy check (CRC) mode is available to allow detection of potential bit errors during

transmission. Support for the 12-bit word CRC-12 mode is required by JESD204C, while a 3-bit word CRC-3

mode is optional. The device does not support the CRC-3 mode and therefore this section is specific to the

CRC-12 mode only. The transmitter computes the CRC-12 parity bits from the scrambled data bits of the 32

blocks of a multiblock. The 12-bit CRC parity word is then transmitted in the sync header stream of the next

multiblock. The receiver computes the 12-bit parity word of the received multiblock and compares it against the

received 12-bit parity word of the next multiblock. A difference indicates that there is at least one error in the

received data bits or in the received 12-bit parity word. The minimum latency to the detection of a bit error in the

first data bit of a multiblock is 46 blocks.

The mapping of the sync header stream when using the CRC-12 mode is shown in 表7-20. CRC[x] corresponds

to bit x of the 12-bit CRC word. Cmd[x] corresponds to bit x of the 7 bit command word, which are always set to

0's in the device. The 00001 bit sequence at the end of the sync header stream is the pilot signal that is used to

identify the end of a multiblock. The 1s that occur throughout the sync header make ensure the pilot signal is

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only seen at the end of the sync header, allowing multiblock alignment after only a single multiblock has been

received. EoEMB is the end-of-extended-multiblock bit, which is set to 1 for the last multiblock of an extended

multiblock.

表7-20. Sync Header Stream Bit Mapping for CRC-12 Mode

Bit

0

Function

CRC[11]

CRC[10]

CRC[9]

1

Bit

Function

CRC[5]

CRC[4]

CRC[3]

1

Bit

16

17

18

19

20

21

22

23

Function

Cmd[6]

Cmd[5]

Cmd[4]

1

Bit

24

25

26

27

28

29

30

31

Function

8

Cmd[2]

1

9

Cmd[1]

2

10

11

12

13

14

15

Cmd[0]

3

0

1

4

CRC[8]

CRC[7]

CRC[6]

1

CRC[2]

CRC[1]

CRC[0]

1

Cmd[3]

1

5

6

EoEMB

1

7

The CRC-12 encoder takes in a multiblock of 32 scrambled blocks (2048 bits) and computes the 12-bit parity

word using the generator polynomial given by 方程式12. The polynomial is sufficient to detect all 2-bit errors in a

multiblock, spanning any distance, and burst error sequences of up to 12-bits in length. The probability of not

detecting a 3-bit error spanning any distance in a multiblock is approximately 0.004%.

0x987 == x¹²+x⁹+x⁸+x³+x²+x+1

(12)

The full parity bit generation for CRC-12 is shown in 图 7-21. The input is a 2048 bit sequence, built from the 32

scrambled blocks of a multiblock (sync header is not included). The 12-bit parity word, CRC[11:0], is taken from

the S_xblocks after the full 2048 bit sequence is processed. The S_xblocks are initialized with 0s before

processing each multiblock. For more information on the CRC-12 parity word generation, refer to the JESD204C

standard.

32-block input

(2048 bits)

1

x

x²

x³

x⁸

x⁹

x¹²

S₁₁

S₀

S₁

S₂

S₃

S₄

S₅

S₆

S₇

S₈

S₉

S₁₀

CRC[0]

CRC[1]

CRC[2]

CRC[3] CRC[4] CRC[5] CRC[6] CRC[7]

CRC[8]

CRC[9] CRC[10] CRC[11]

图7-21. CRC-12 Parity Bit Generator

7.3.9.5.3.2 Forward Error Correction (FEC) Mode

Forward error correction (FEC) is an optional feature in JESD204C and is supported by the device. Whereas

CRC-12 mode can only detect errors on the link, FEC is able to detect and correct errors to improve the bit error

rate (BER) for error-sensitive applications. Many applications can tolerate random bit errors, however some

applications, such as an oscilloscope, rely on long error-free measurements to detect a certain response from

the device under test (DUT). An error in these applications may result in a false-positive detection of the

response.

A scrambled multiblock of 32 blocks (2048 bits) is input into the FEC parity bit generator to generate the 26-bit

parity word. The parity word is sent in the sync header stream of the next multiblock. The receiver then

calculates its own 26-bit parity word and calculates the difference between the locally generated and received

parity word, called the syndrome of the received bits. If the syndrome is 0, then all bits are assumed to have

been received correctly, while any value other than 0 indicates at least one error in either the data bits or the

parity word. If the syndrome is non-zero, then it can be used to determine the most likely error and then correct

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the error. The minimum latency from a bit error to detection and correct of a bit error in the first bit of a multiblock

is 58 blocks.

The mapping of the sync header stream when using FEC mode is shown in 表 7-21. FEC[x] corresponds to bit x

of the 26-bit FEC word. The 00001 bit sequence at the end of the sync header stream is the pilot signal that is

used to identify the end of a multiblock. It is possible for a 00001 sequence to appear in another location within

the sync header stream in FEC mode, however it is improbable to see the 00001 sequence in the same location

within a sequence of multiple multiblocks. Therefore, in FEC mode it may take more than one multiblock to find

the end of a multiblock. EoEMB is the end-of-extended-multiblock bit, which is set to 1 for the last multiblock of

an extended multiblock.

表7-21. Sync Header Stream Bit Mapping for FEC Mode

Bit

0

Function

FEC[25]

FEC[24]

FEC[23]

FEC[22]

FEC[21]

FEC[20]

FEC[19]

FEC[18]

Bit

Function

FEC[17]

FEC[16]

FEC[15]

FEC[14]

FEC[13]

FEC[12]

FEC[11]

FEC[10]

Bit

16

17

18

19

20

21

22

23

Function

FEC[9]

FEC[8]

FEC[7]

FEC[6]

FEC[5]

FEC[4]

EoEMB

FEC[3]

Bit

24

25

26

27

28

29

30

31

Function

8

FEC[2]

1

9

FEC[1]

2

10

11

12

13

14

15

FEC[0]

3

0

1

4

5

6

7

The FEC encoder takes in a multiblock of 32 scrambled blocks (2048 bits) and computes the 26-bit parity word

using the generator polynomial given by 方程式 13. The 2048 scrambled input bits plus 26 parity bits forms a

shortened (2074, 2048) binary cyclic code. The (2074, 2048) binary cyclic code is shortened from the cyclic Fire

code (8687, 8661). This polynomial can correct up to a 9-bit burst error per multiblock.

g(x) = (x¹⁷+1)(x⁹+x⁴+1) == x²⁶+x²¹+x¹⁷+x⁹+x⁴+1

(13)

The full 26-bit FEC parity word generation is shown in 图 7-22. The input is a 2048 bit sequence, built from the

32 scrambled blocks of a multiblock (sync header is not included). The 26-bit parity word, FEC[25:0], is taken

from the S_xblocks after the full 2048 bit sequence is processed. The S_xblocks are initialized with 0's before

processing each multiblock. For more information on the FEC parity word generation, refer to the JESD204C

standard.

32-block input

(2048 bits)

1

x⁴

x⁹

x¹⁷

x²¹

S₀

S₁

S₂

S₃

S₄

S₈

S₉

S₁₆

S₁₇

S₂₀

S₂₁

S₂₄

S₂₅

...

FEC[21] FEC[24] FEC[25]

FEC[0] FEC[1] FEC[2] FEC[3]

FEC[4]

FEC[8]

FEC[9]

FEC[16]

FEC[17]

FEC[20]

图7-22. FEC Parity Bit Generator

FEC decoding and error correction are not covered here. For full details on FEC decoding and error correction,

refer to the JESD204C standard.

7.3.9.5.4 Initial Lane Alignment

The 64B/66B link layer does not use an initial lane alignment sequence (ILAS) like the 8B/10B link layer.

Therefore, the receiver must use a different scheme to align lanes using the elastic buffer. In 8B/10B mode, the

ILAS triggers the elastic buffer to start buffering the data for each lane. After all lanes have started buffering the

data, the elastic buffers for each lane are released at a release point determined by the release buffer delay

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(RBD) parameter and the phase of the LMFC. In 64B/66B mode, the process starts by having all lanes achieve

block, multiblock and extended multiblock alignment. Once all lanes have achieved alignment, the receiver can

begin buffering data in the elastic buffers at the start of the next extended multiblock on each lane. The data is

released at the next release point after all lanes have seen the start of an extended multiblock and have started

buffering the data. The release point is defined relative to the LEMC edge and the programmed RBD value, the

most intuitive of which is to release on the LEMC edge itself. The release point must be chosen to avoid the

region of the LEMC containing variation in the data delay on each lane from startup to startup.

7.3.9.5.5 Block, Multiblock and Extended Multiblock Alignment Monitoring

Synchronization of blocks, multiblocks and extended multiblocks by monitoring the sync header of each block

and EoMB and EoEMB bit of the sync header stream. A block will always begin with a 0 to 1 or 1 to 0 transition

(sync header). A single missed sync header can occur due to a bit error, however it there are a number of sync

header errors within a set number of blocks, then block synchronization has been lost and block synchronization

should be reinitialized. It is possible to still have block synchronization, but to lose multiblock or extended

multiblock synchronization. Multiblock synchronization is monitored by looking for the EoMB signal, 00001, at the

end of the sync header stream for each multiblock. If multiple EoMB signals are erroneous within a number of

blocks, multiblock synchronization has been lost and multiblock synchronization should be reinitialized. If an

erroneous EoEMB bit is received for multiple extended multiblocks within a number of extended multiblocks,

such as a 1 for a multiblock that is not the end of an extended multiblock or a 0 for a multiblock that is the end of

an extended multiblock, then multiblock synchronization is lost and extended multiblock synchronization should

be reinitialized. If multiblock or extended multiblock synchronizaton is lost, SYSREF should be applied to the

erroneous devices to reestablish the LEMC before the synchronization process begins.

7.3.9.6 Physical Layer

The JESD204C physical layer consists of a current mode logic (CML) output driver and receiver. The receiver

consists of a clock detection and recovery (CDR) unit to extract the data clock from the serialized data stream

and can contain a continuous time linear equalizer (CTLE) and/or discrete feedback equalizer (DFE) to correct

for the low-pass response of the physical transmission channel. Likewise, the transmitter can contain pre-

equalization to account for frequency dependent losses across the channel. The total reach of the SerDes links

depends on the data rate, board material, connectors, equalization, noise and jitter, and required bit-error

performance. The SerDes lanes do not have to be matched in length because the receiver aligns the lanes

during the initial lane alignment sequence.

7.3.9.6.1 SerDes Pre-Emphasis

The device high-speed output drivers can pre-equalize the transmitted data stream by using pre-emphasis to

compensate for the low-pass response of the transmission channel. Configurable pre-emphasis settings allow

the output drive waveform to be optimized for different PCB materials and signal transmission distances. The

pre-emphasis setting is adjusted through the serializer pre-emphasis setting SER_PE (in the serializer pre-

emphasis control register). Higher values increase the pre-emphasis to compensate for more lossy PCB

materials. This adjustment is best used in conjunction with an eye-diagram analysis capability in the receiver.

Adjust the pre-emphasis setting to optimize the eye-opening for the specific hardware configuration and line

rates needed.

7.3.9.7 JESD204C Enable

The JESD204C interface must be disabled through JESD_EN (in the JESD204C enable register) while any of

the other JESD204C parameters are being changed. When JESD_EN is set to 0 the block is held in reset and

the serializers are powered down. The clocks for this section are also gated off to further save power. When the

parameters are set as desired, the JESD204C block can be enabled (JESD_EN is set to 1).

7.3.9.8 Multi-Device Synchronization and Deterministic Latency

JESD204C subclass 1 outlines a method to achieve deterministic latency across the serial link. If two devices

achieve the same deterministic latency then they can be considered synchronized. This latency must be

achieved from system startup to startup to be deterministic. There are two key requirements to achieve

deterministic latency. The first is proper capture of SYSREF for which the device provides a number of features

to simplify this requirement at giga-sample clock rates (see the SYSREF Capture section for more information).

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SYSREF resets either the LMFC in 8B/10B encoding mode or the LEMC is 64B/66B encoding mode. The LMFC

and LEMC are analogous between the two modes and will now be referred to as LMFC/LEMC.

The second requirement is to choose a proper elastic buffer release point in the receiver. Because the device is

an ADC, the device is the transmitter (TX) in the JESD204C link and the logic device is the receiver (RX). The

elastic buffer is the key block for achieving deterministic latency, and does so by absorbing variations in the

propagation delays of the serialized data as the data travels from the transmitter to the receiver. A proper release

point is one that provides sufficient margin against delay variations. An incorrect release point results in a latency

variation of one LMFC/LEMC period. Choosing a proper release point requires knowing the average arrival time

of data at the elastic buffer, referenced to an LMFC/LEMC edge, and the total expected delay variation for all

devices. With this information the region of invalid release points within the LMFC/LEMC period can be defined,

which stretches from the minimum to maximum delay for all lanes. Essentially, the designer must be sure the

data for all lanes arrives at all devices after the previous release point occurs and before the next release point

occurs.

图 7-23 provides a timing diagram that demonstrates this requirement. In this figure, the data for two ADCs is

shown. The second ADC has a longer routing distance (t_PCB) and results in a longer link delay. First, the invalid

region of the LMFC/LEMC period is marked off as determined by the data arrival times for all devices. Then, the

release point is set by using the release buffer delay (RBD) parameter to shift the release point an appropriate

number of frame clocks from the LMFC/LEMC edge so that the release point occurs within the valid region of the

LMFC/LEMC cycle. In the case of 图 7-23, the LMFC/LEMC edge (RBD = 0) is a good choice for the release

point because there is sufficient margin on each side of the valid region.

Nominal Link Delay

Link Delay

(Arrival at Elastic Buffer)

Variation

ADC 1 Data

t_TX

t_PCB

t_RX-DESER

Propagation

Choose LMFC/LEMC

edge as release point

(RBD = 0)

ADC 2 Data

Propagation

t_TX

t_PCB

t_RX-DESER

Release point

margin

TX LMFC/LEMC

RX LMFC/LEMC

Time

Invalid Region

of LMFC/LEMC

Valid Region of

LMFC/LEMC

图7-23. LMFC/LEMC Valid Region Definition for Elastic Buffer Release Point Selection

The TX and RX LMFC/LEMCs do not necessarily need to be phase aligned, but knowledge of their phase is

important for proper elastic buffer release point selection. Also, the elastic buffer release point occurs within

every LMFC/LEMC cycle, but the buffers only release when all lanes have arrived. Therefore, the total link delay

can exceed a single LMFC/LEMC period; see JESD204B multi-device synchronization: Breaking down the

requirements for more information.

7.3.9.9 Operation in Subclass 0 Systems

ADC12DJ5200SE can operate with subclass 0 compatibility provided that multi-ADC synchronization and

deterministic latency are not required. With these limitations, the device can operate without the application of

SYSREF. The internal LMFC/LEMC is automatically self-generated with unknown timing. SYNC is used as

normal to initiate the CGS and ILAS in 8B/10B mode.

7.3.10 Alarm Monitoring

A number of built-in alarms are available to monitor internal events. Several types of alarms and upsets are

detected by this feature:

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1. Serializer FIFO alarm (FIFO overflow or underflow)

2. Serializer PLL is not locked

3. JESD204C link is enabled, but not transmitting data (not in the data transmission state)

4. SYSREF causes internal clocks to be realigned

5. An upset that impacts the NCO phase

6. An upset that impacts the internal DDC or JESD204C clocks

When an alarm occurs, a bit for each specific alarm is set in ALM_STATUS. Each alarm bit remains set until the

host system writes a 1 to clear the alarm. If the alarm type is not masked (see the alarm mask register), then the

alarm is also indicated by the ALARM register. The CALSTAT output pin can be configured as an alarm output

that goes high when an alarm occurs; see the CAL_STATUS_SEL bit in the calibration pin configuration register.

7.3.10.1 NCO Upset Detection

The NCO_ALM register bit indicates if the NCO in channel A or B has been upset. The NCO phase

accumulators in channel A are continuously compared to channel B. If the accumulators differ for even one clock

cycle, the NCO_ALM register bit is set and remains set until cleared by the host system by writing a 1. This

feature requires the phase and frequency words for each NCO accumulator in DDC A (PHASEAx, FREQAx) to

be set to the same values as the NCO accumulators in DDC B (PHASEBx, FREQBx). For example, PHASEA0

must be the same as PHASEB0 and FREQA0 must be the same as FREQB0, however, PHASEA1 can be set to

a different value than PHASEA0. This requirement ultimately reduces the number of NCO frequencies available

for phase coherent frequency hopping from four to two for each DDC. DDC B can use a different NCO frequency

than DDC A by setting the NCOB[1:0] pins to a different value than NCOA[1:0]. This detection is only valid after

the NCOs are synchronized by either SYSREF or the start of the ILA sequence (as determined by the NCO

synchronization register). For the NCO upset detection to work properly, follow these steps:

1. Program JESD_EN = 0

2. Make sure the device is configured to use both channels (PD_ACH = 0, PD_BCH = 0)

3. Select a JMODE that uses the NCO

4. Program all NCO frequencies and phases to be the same for channel A and B (for example, FREQA0 =

FREQB0, FREQA1 = FREQB1, FREQA2 = FREQB2, and FREQA3 = FREQB3)

5. If desired, use the CMODE and CSEL registers or the NCOA[1:0] and NCOB[1:0] pins to choose a unique

frequency for channel A and channel B

6. Program JESD_EN = 1

7. Synchronize the NCOs (using SYNC or using SYSREF); see the NCO synchronization register

8. Write a 1 to the NCO_ALM register bit to clear it

9. Monitor the NCO_ALM status bit or the CALSTAT output pin if CAL_STATUS_SEL is properly configured

10. If the frequency or phase registers are changed while the NCO is enabled, the NCOs can get out of

synchronization

11. Repeat steps 7-9

12. If the device enters and exits global power down, repeat steps 7-9

7.3.10.2 Clock Upset Detection

The CLK_ALM register bit indicates if the internal clocks have been upset. The clocks in channel A are

continuously compared to channel B. If the clocks differ for even one DEVCLK / 2 cycle, the CLK_ALM register

bit is set and remains set until cleared by the host system by writing a 1. For the CLK_ALM register bit to

function properly, follow these steps:

1. Program JESD_EN = 0

2. Make sure the part is configured to use both channels (PD_ACH = 0, PD_BCH = 0)

3. Program JESD_EN = 1

4. Write CLK_ALM = 1 to clear CLK_ALM

5. Monitor the CLK_ALM status bit or the CALSTAT output pin if CAL_STATUS_SEL is properly configured

6. When exiting global power-down (via MODE or the PD pin), the CLK_ALM status bit may be set and must be

cleared by writing a 1 to CLK_ALM

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7.3.10.3 FIFO Upset Detection

The FIFO_ALM bit indicates if an underflow or overflow condition has occurred on any of the JESD204C

serializer lanes within the synchronizing FIFO between the digital logic block and serializer outputs. The

FIFO_LANE_ALM register bits can be used to determine which lane triggered the underflow or overflow

condition alarm. If the FIFO pointers are upset due to an undesired clock shift or other single event or incorrect

clocking frequencies the FIFO_LANE_ALM bit for the erroneous lane will be set to 1. If the INIT_ON_FIFO_ALM

bit is set then the serializers, FIFO and JESD204C block will automatically reinitialize.

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7.4 Device Functional Modes

The ADC12DJ5200SE can be configured to operate in a number of functional modes. These modes are

described in this section.

7.4.1 Dual-Channel Mode

ADC12DJ5200SE can be used as a dual-channel ADC where the sampling rate is equal to the clock frequency

(f_S= f_CLK) provided at the CLK+ and CLK–pins. The two inputs, INA and INB, serve as the respective inputs for

each channel in this mode. This mode is chosen simply by setting JMODE to the appropriate setting for the

desired configuration as described in 表 7-24. The analog inputs can be swapped by setting DUAL_INPUT (see

the input mux control register). One channel can be powered down to operate ADC12DJ5200SE as a single

channel at the maximum sampling rate of dual channel mode to save power compared to single channel mode

operating at half the rate.

7.4.2 Single-Channel Mode (DES Mode)

The ADC12DJ5200SE can also be used as a single-channel ADC where the sampling rate is equal to two times

the clock frequency (f_S= 2 × f_CLK) provided at the CLK+ and CLK– pins. This mode effectively interleaves the

two ADC channels together to form a single-channel ADC at twice the sampling rate. This mode is chosen

simply by setting JMODE to the appropriate setting for the desired configuration as described in 表 7-24. INA or

INB, can serve as the input to the ADC, however INA is recommended for highest performance. The analog

input can be selected using SINGLE_INPUT (see the input mux control register). A calibration needs to be

performance after switching the input mux for the changes to take effect.

7.4.3 Dual-Input Single-Channel Mode (DUAL DES Mode)

The ADC12DJ5200SE can also be used as a single-channel ADC where the sampling rate is equal to two times

the clock frequency (f_S= 2 × f_CLK) provided at the CLK+ and CLK– pins. This mode interleaves the two

channels by sampling them out-of-phase and each channel samples separate analog inputs (INA and INB). The

effective sampling rate is twice the device clock input (CLK±). This mode is useful for sampling the output of

interleaved track-and-hold analog front-ends. This mode is chosen by setting JMODE to a single channel mode

as described in 表 7-24 and setting SINGLE_INPUT to use both INA and INB (see the input mux control

register). The digital processing and JESD204C interface operate as if the device is in single-channel mode

sampling only one of the inputs.

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7.4.4 JESD204C Modes

The ADC12DJ5200SE can be programmed as a single-channel or dual-channel ADC, with or without

decimation, and a number JESD204C output formats. 表 7-22 summarizes the basic operating mode

configuration parameters and whether they are user configured or derived.

表7-22. ADC12DJ5200SE Operating Mode Configuration Parameters

USER CONFIGURED

PARAMETER

DESCRIPTION

VALUE

OR DERIVED

JESD204C operating mode, automatically

derives the rest of the JESD204C

parameters, single-channel or dual-channel

mode and the decimation factor

Set by JMODE (see the JESD204C mode

register)

JMODE

User configured

D

Decimation factor

Derived

See Operating Modes

1 = single-channel mode, 0 = dual-channel

mode

DES

Number of bits transmitted per lane per

CLK+/–cycle. The JESD204C line rate is

the CLK+/–frequency times R. This

parameter sets the SerDes PLL multiplication

factor or controls bypassing of the SerDes

PLL.

R

Derived

See Operating Modes

Links

K

Number of JESD204C links used

Derived

Set by KM1 (see the JESD204C K parameter

register), see the allowed values in Operating

Modes. This parameter is ignored in 64B/66B

modes.

Number of frames per multiframe (8B/10B

mode)

User configured

Number of multiblocks per extended

multiblock (64B/66B mode)

Always set to '1' in ADC12DJ5200SE. This

parameter is ignored in 8B/10B modes.

E

Derived

There are a number of parameters required to define the JESD204C transport layer format, all of which are sent

across the link during the initial lane alignment sequence in 8B/10B mode. 64B/66B mode does not use the

ILAS, however the transport layer uses the same parameters. In the ADC12DJ5200SE, most parameters are

automatically derived based on the selected JMODE; however, a few are configured by the user. 表 7-23

describes these parameters.

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表7-23. JESD204C Initial Lane Alignment Sequence Parameters

USER CONFIGURED

OR DERIVED

PARAMETER

DESCRIPTION

VALUE

ADJCNT

ADJDIR

BID

LMFC adjustment amount (not applicable)

LMFC adjustment direction (not applicable)

Bank ID

Derived

Always 0

CF

Number of control words per frame

Always set to 0 in ILAS, see Operating

Modes for actual usage

CS

Control bits per sample

Derived

Set by DID (see the JESD204C DID

parameter register), see Lane Assignments

DID

F

Device identifier, used to identify the link

User configured

Number of octets (bytes) per frame (per lane) Derived

See Operating Modes

Always 0

High-density format (samples split between

lanes)

HD

JESDV

K

Derived

JESD204 standard revision

Derived

Always 1

Set by the KM1 register, see the JESD204C

K parameter register

Number of frames per multiframe

User configured

L

Number of serial output lanes per link

Lane identifier for each lane

Derived

See Operating Modes

See Lane Assignments

LID

Number of converters used to determine lane

bit packing; may not match number of ADC

channels in the device

M

Derived

See Operating Modes

Sample resolution (before adding control and

tail bits)

N

N'

S

Derived

See Operating Modes

Bits per sample after adding control and tail

bits

Number of samples per converter (M) per

frame

SCR

Scrambler enabled

Device subclass version

Reserved field 1

User configured

Derived

Set by the JESD204C control register

SUBCLASSV

RES1

Always 1

Always 0

Derived

RES2

Reserved field 2

Derived

Checksum for ILAS checking (sum of all

above parameters modulo 256)

CHKSUM

Derived

Computed based on parameters in this table

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7.4.4.2 JESD204C Modes cont.

Configuring the ADC12DJ5200SE is made easy by using a single configuration parameter called JMODE (see

the JESD204C mode register). Using Operating Modes, the correct JMODE value can be found for the desired

operating mode. The modes listed in Operating Modes are the only available operating modes. This table also

gives a range and allowable step size for the K parameter (set by KM1, see the JESD204C K parameter

register), which sets the multiframe length in number of frames.

The ADC12DJ5200SE has a total of 16 high-speed output drivers that are grouped into two 8-lane JESD204C

links. All operating modes use two links with up to eight lanes per link. The lanes and their derived configuration

parameters are described in the Lane Assignement and Parameters table. For a specified JMODE, the lowest

indexed lanes for each link are used and the higher indexed lanes for each link are automatically powered down.

Always route the lowest indexed lanes to the logic device.

表7-25. ADC12DJ5200SE Lane Assignment and Parameters

DEVICE PIN

DESIGNATION

JESD204C LINK

DID (User Configured)

LID (Derived)

DA0±

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

DA1±

DA2±

Set by DID (see the JESD204C DID parameter

register), the effective DID is equal to the DID register

setting (DID)

DA3±

A

DA4±

DA5±

DA6±

DA7±

DB0±

DB1±

DB2±

Set by DID (see the JESD204C DID parameter

register), the effective DID is equal to the DID register

setting plus 1 (DID+1)

DB3±

B

DB4±

DB5±

DB6±

DB7±

7.4.4.3 JESD204C Transport Layer Data Formats

Output data are formatted in a specific optimized fashion for each JMODE setting based on the transport layer

settings for that JMODE. When the DDC is not used (decimation = 1) the 12-bit offset binary values are mapped

into octets. For the DDC mode, the 16-bit values (15-bit complex data plus 1 overrange bit) are mapped into

octets. The following tables show the specific mapping formats for a single frame for each JMODE. The symbol

definitions used in the JMODE tables is provided in 表 7-26. In all mappings the tail bits (T) are 0 (zero). All

samples are formatted as MSB first, LSB last.

表7-26. JMODE Table Symbol Definitions

NOTATION

S[n]

MODE

DESCRIPTION

Single channel, DDC bypassed

Dual channel, DDC bypassed

Sample n from ADC in single channel mode when DDC is bypassed

Sample n from channel A in dual channel mode when DDC is bypassed

Tail bits, always set to 0

A[n]

B[n]

T

—

AI[n], AQ[n]

BI[n], BQ[n]

Dual channel, DDC enabled

Complex I/Q sample n from DDC A in dual channel mode

Complex I/Q sample n from DDC B in dual channel mode

Overrange flag for channel A, set high if channel A sample n exceeds

overrange threshold 0 (OVR_T0)

ORA0[n]

Dual channel, DDC enabled

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表7-26. JMODE Table Symbol Definitions (continued)

NOTATION

MODE

DESCRIPTION

Overrange flag for channel A, set high if channel A sample n exceeds

overrange threshold 1 (OVR_T1)

ORA1[n]

Dual channel, DDC enabled

Overrange flag for channel B, set high if channel B sample n exceeds

overrange threshold 0 (OVR_T0)

ORB0[n]

ORB1[n]

Dual channel, DDC enabled

Overrange flag for channel B, set high if channel B sample n exceeds

overrange threshold 1 (OVR_T1)

I[n], Q[n]

OR0[n]

OR1[n]

Single channel, DDC enabled

Complex I/Q sample n from the DDC in single channel mode

Overrange flag, set high if sample n exceeds overrange threshold 0 (OVR_T0)

Overrange flag, set high if sample n exceeds overrange threshold 1 (OVR_T1)

表7-27. JMODE 0 (12-bit, Single Channel, DDC Bypass, 8 lanes)

OCTET

NIBBLE

DA0

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

T

S[0]

S[2]

S[4]

S[6]

S[1]

S[3]

S[5]

S[7]

S[8]

S[16]

S[18]

S[20]

S[22]

S[17]

S[19]

S[21]

S[23]

S[24]

S[26]

S[28]

S[30]

S[25]

S[27]

S[29]

S[31]

S[32]

S[34]

S[36]

S[38]

S[33]

S[35]

S[37]

S[39]

DA1

S[10]

S[12]

S[14]

S[9]

DA2

DA3

DB0

DB1

S[11]

S[13]

S[15]

DB2

DB3

表7-27 also applies to JMODE 30.

表7-28. JMODE 1 (12-bit, Single Channel, DDC Bypass, 16 lanes)

OCTET

NIBBLE

DA0

DA1

DA2

DA3

DA4

DA5

DA6

DA7

DB0

DB1

DB2

DB3

DB4

DB5

DB6

DB7

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

T

S[0]

S[2]

S[4]

S[6]

S[8]

S[10]

S[12]

S[14]

S[1]

S[3]

S[5]

S[7]

S[9]

S[11]

S[13]

S[15]

S[16]

S[18]

S[20]

S[22]

S[24]

S[26]

S[28]

S[30]

S[17]

S[19]

S[21]

S[23]

S[25]

S[27]

S[29]

S[31]

S[32]

S[34]

S[36]

S[38]

S[40]

S[42]

S[44]

S[46]

S[33]

S[35]

S[37]

S[39]

S[41]

S[43]

S[45]

S[47]

S[48]

S[50]

S[52]

S[54]

S[56]

S[58]

S[60]

S[62]

S[49]

S[51]

S[53]

S[55]

S[57]

S[59]

S[61]

S[63]

S[64]

S[66]

S[68]

S[70]

S[72]

S[74]

S[76]

S[78]

S[65]

S[67]

S[69]

S[71]

S[73]

S[75]

S[77]

S[79]

表7-28 also applies to JMODE 40.

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表7-29. JMODE 2 (12-Bit, Dual Channel, DDC Bypass, 8 Lanes)

OCTET

NIBBLE

DA0

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

T

A[0]

A[1]

A[2]

A[3]

B[0]

B[1]

B[2]

B[3]

A[4]

A[5]

A[6]

A[7]

B[4]

B[5]

B[6]

B[7]

A[8]

A[12]

A[13]

A[14]

A[15]

B[12]

B[13]

B[14]

B[15]

A[16]

A[17]

A[18]

A[19]

B[16]

B[17]

B[18]

B[19]

DA1

A[9]

DA2

A[10]

A[11]

B[8]

DA3

DB0

DB1

B[9]

DB2

B[10]

B[11]

DB3

表7-29 also applies to JMODE 31.

表7-30. JMODE 3 (12-Bit, Dual Channel, DDC Bypass, 16 Lanes)

OCTET

NIBBLE

DA0

DA1

DA2

DA3

DA4

DA5

DA6

DA7

DB0

DB1

DB2

DB3

DB4

DB5

DB6

DB7

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

T

A[0]

A[1]

A[2]

A[3]

A[4]

A[5]

A[6]

A[7]

B[0]

B[1]

B[2]

B[3]

B[4]

B[5]

B[6]

B[7]

A[8]

A[16]

A[17]

A[18]

A[19]

A[20]

A[21]

A[22]

A[23]

B[16]

B[17]

B[18]

B[19]

B[20]

B[21]

B[22]

B[23]

A[24]

A[25]

A[26]

A[27]

A[28]

A[29]

A[30]

A[31]

B[24]

B[25]

B[26]

B[27]

B[28]

B[29]

B[30]

B[31]

A[32]

A[33]

A[34]

A[35]

A[36]

A[37]

A[38]

A[39]

B[32]

B[33]

B[34]

B[35]

B[36]

B[37]

B[38]

B[39]

A[9]

A[10]

A[11]

A[12]

A[13]

A[14]

A[15]

B[8]

B[9]

B[10]

B[11]

B[12]

B[13]

B[14]

B[15]

表7-30 also applies to JMODE 41.

表7-31. JMODE 5 (8-bit, Single Channel, 8 Lanes)

OCTET

0

NIBBLE

DA0

0

1

S[0]

S[2]

S[4]

S[6]

S[1]

S[3]

S[5]

S[7]

DA1

DA2

DA3

DB0

DB1

DB2

DB3

表7-31 also applies to JMODE 44.

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表7-32. JMODE 6 (8-bit, Single Channel, 16 Lanes)

OCTET

NIBBLE

DA0

DA1

DA2

DA3

DA4

DA5

DA6

DA7

DB0

DB1

DB2

DB3

DB4

DB5

DB6

DB7

0

1

S[0]

S[2]

S[4]

S[6]

S[8]

S[10]

S[12]

S[14]

S[1]

S[3]

S[5]

S[7]

S[9]

S[11]

S[13]

S[15]

表7-32 also applies to JMODE 50.

表7-33. JMODE 7 (8-bit, Dual Channel, 8 Lanes)

OCTET

0

NIBBLE

DA0

0

1

A[0]

A[1]

A[2]

A[3]

B[0]

B[1]

B[2]

B[3]

DA1

DA2

DA3

DB0

DB1

DB2

DB3

表7-33 also applies to JMODE 45.

表7-34. JMODE 8 (8-bit, Dual Channel, 16 Lanes)

OCTET

0

NIBBLE

DA0

DA1

DA2

DA3

DA4

DA5

DA6

DA7

DB0

0

1

A[0]

A[1]

A[2]

A[3]

A[4]

A[5]

A[6]

A[7]

B[0]

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表7-34. JMODE 8 (8-bit, Dual Channel, 16 Lanes) (continued)

OCTET

NIBBLE

DB1

0

1

B[1]

B[2]

B[3]

B[4]

B[5]

B[6]

B[7]

DB2

DB3

DB4

DB5

DB6

DB7

表7-34 also applies to JMODE 51.

表7-35. JMODE 10 (15-bit, Dual Channel, Decimate-by-4, 4 lanes)

OCTET

0

1

NIBBLE

DA0

0

1

2

3

AI[0], ORA0[0]

AQ[0], ORA1[0]

BI[0], ORB0[0]

BQ[0], ORB1[0]

DA1

DB0

DB1

表7-35 also applies to JMODE 37.

表7-36. JMODE 11 (15-bit, Dual Channel, Decimate-by-4, 8 lanes)

OCTET

0

1

NIBBLE

DA0

0

1

2

3

AI[0], ORA0[0]

AI[1], ORA0[1]

AQ[0], ORA1[0]

AQ[1], ORA1[1]

BI[0], ORB0[0]

BI[1], ORB0[1]

BQ[0], ORB1[0]

BQ[1], ORB1[1]

DA1

DA2

DA3

DB0

DB1

DB2

DB3

表7-36 also applies to JMODE 47.

表7-37. JMODE 12 (15-bit, Dual Channel, Decimate-by-4, 16 lanes)

OCTET

0

1

NIBBLE

DA0

DA1

DA2

DA3

DA4

DA5

DA6

DA7

DB0

0

1

2

3

AI[0], ORA0[0]

AI[1], ORA0[1]

AI[2], ORA0[2]

AI[3], ORA0[3]

AQ[0], ORA1[0]

AQ[1], ORA1[1]

AQ[2], ORA1[2]

AQ[3], ORA1[3]

BI[0], ORB0[0]

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表7-37. JMODE 12 (15-bit, Dual Channel, Decimate-by-4, 16 lanes) (continued)

OCTET

NIBBLE

DB1

0

1

0

1

2

3

BI[1], ORB0[1]

BI[2], ORB0[2]

BI[3], ORB0[3]

BQ[0], ORB1[0]

BQ[1], ORB1[1]

BQ[2], ORB1[2]

BQ[3], ORB1[3]

DB2

DB3

DB4

DB5

DB6

DB7

表7-37 also applies to JMODE 53.

表7-38. JMODE 13 (15-bit, Dual Channel, Decimate-by-8, 2 lanes)

OCTET

NIBBLE

DA0

0

1

2

3

0

1

2

3

4

5

6

7

AI[0], ORA0[0]

BI[0], ORB0[0]

AQ[0], ORA1[0]

BQ[0], ORB1[0]

DB0

表7-38 also applies to JMODE 39,JMODE 56, JMODE 59, JMODE 66 and JMODE 68.

表7-39. JMODE 14 (15-bit, Dual Channel, Decimate-by-8, 4 lanes)

OCTET

NIBBLE

DA0

0

1

0

1

2

3

AI[0], ORA0[0]

AQ[0], ORA1[0]

BI[0], ORB0[0]

BQ[0], ORB1[0]

DA1

DB0

DB1

表7-39 also applies to JMODE 49, JMODE 57, JMODE 60 and JMODE 67.

表7-40. JMODE 15 (15-bit, Dual Channel, Decimate-by-8, 8 lanes)

OCTET

NIBBLE

DA0

0

1

0

1

2

3

AI[0], ORA0[0]

AI[1], ORA0[1]

AQ[0], ORA1[0]

AQ[1], ORA1[1]

BI[0], ORB0[0]

BI[1], ORB0[1]

BQ[0], ORB1[0]

BQ[1], ORB1[1]

DA1

DA2

DA3

DB0

DB1

DB2

DB3

表7-40 also applies to JMODE 55 and JMODE 58.

表7-41. JMODE 16 (15-bit, Dual Channel, Decimate-by-8, 16 lanes)

OCTET

0

1

NIBBLE

DA0

0

1

2

3

AI[0], ORA0[0]

AI[1], ORA0[1]

AI[2], ORA0[2]

AI[3], ORA0[3]

AQ[0], ORA1[0]

AQ[1], ORA1[1]

DA1

DA2

DA3

DA4

DA5

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表7-41. JMODE 16 (15-bit, Dual Channel, Decimate-by-8, 16 lanes) (continued)

OCTET

NIBBLE

DA6

0

1

0

1

2

3

AQ[2], ORA1[2]

AQ[3], ORA1[3]

BI[0], ORB0[0]

BI[1], ORB0[1]

BI[2], ORB0[2]

BI[3], ORB0[3]

BQ[0], ORB1[0]

BQ[1], ORB1[1]

BQ[2], ORB1[2]

BQ[3], ORB1[3]

DA7

DB0

DB1

DB2

DB3

DB4

DB5

DB6

DB7

表7-42. JMODE 19 (12-bit, Single Channel, DDC Bypass, 12 lanes)

OCTET

0

1

NIBBLE

DA0

DA1

DA2

DA3

DA4

DA5

DB0

DB1

DB2

DB3

DB4

DB5

0

1

2

3

S[0][11:0]

S[2][11:8]

S[2][7:0]

S[10][7:0]

S[3][7:0]

S[11][7:0]

S[4][11:4]

S[12][11:4]

S[5][11:4]

S[13][11:4]

S[4][3:0]

S[12][3:0]

S[5][3:0]

S[13][3:0]

S[6][11:0]

S[14][11:0]

S[7][11:0]

S[15][11:0]

S[8][11:0]

S[1][11:0]

S[9][11:0]

S[10][11:8]

S[3][11:8]

S[11][11:8]

表7-42 also applies to JMODE 42.

表7-43. JMODE 20 (12-bit, Dual Channel, DDC Bypass, 12 lanes)

OCTET

NIBBLE

DA0

0

1

0

1

2

3

A[0][11:0]

A[1][11:8]

DA1

A[1][7:0]

A[5][7:0]

B[1][7:0]

B[5][7:0]

A[2][11:4]

A[6][11:4]

B[2][11:4]

B[6][11:4]

DA2

A[2][3:0]

A[6][3:0]

B[2][3:0]

B[6][3:0]

A[3][11:0]

A[7][11:0]

B[3][11:0]

B[7][11:0]

DA3

A[4][11:0]

B[0][11:0]

B[4][11:0]

A[5][11:8]

B[1][11:8]

B[5][11:8]

DA4

DA5

DB0

DB1

DB2

DB3

DB4

DB5

表7-43 also applies to JMODE 43.

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表7-44. JMODE 21 (15-bit, Single Channel, Decimate-by-4, 4 lanes)

OCTET

NIBBLE

DA0

0

1

I[0], OR0[0]

I[1], OR0[1]

Q[0], OR1[0]

Q[1], OR1[1]

DA1

DB0

DB1

表7-44 also applies to JMODE 36.

表7-45. JMODE 22 (15-bit, Single Channel, Decimate-by-4, 8 lanes)

OCTET

NIBBLE

DA0

0

1

I[0], OR0[0]

I[1], OR0[1]

I[2], OR0[2]

I[3], OR0[3]

Q[0], OR1[0]

Q[1], OR1[1]

Q[2], OR1[2]

Q[3], OR1[3]

DA1

DA2

DA3

DB0

DB1

DB2

DB3

表7-45 also applies to JMODE 46.

表7-46. JMODE 23 (15-bit, Single Channel, Decimate-by-8, 2 lanes)

OCTET

NIBBLE

DA0

0

1

I[0], OR0[0]

Q[0], OR1[0]

DB0

表7-46 also applies to JMODE 38, JMODE 61, JMODE 64, JMODE 69 and JMODE 71.

表7-47. JMODE 24 (15-bit, Single Channel, Decimate-by-8, 4 lanes)

OCTET

NIBBLE

DA0

0

1

I[0], OR0[0]

I[1], OR0[1]

Q[0], OR1[0]

Q[1], OR1[1]

DA1

DB0

DB1

表7-47 also applies to JMODE 48, JMODE 62, JMODE 65 and JMODE 70.

表7-48. JMODE 25 (15-bit, Single Channel, Decimate-by-4, 16 lanes)

OCTET

0

1

NIBBLE

DA0

0

1

2

3

I[0], OR0[0]

I[1], OR0[0]

I[2], OR0[1]

I[3], OR0[1]

I[4], OR0[2]

I[5], OR0[2]

DA1

DA2

DA3

DA4

DA5

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表7-48. JMODE 25 (15-bit, Single Channel, Decimate-by-4, 16 lanes) (continued)

OCTET

NIBBLE

DA6

0

1

0

1

2

3

I[6], OR0[3]

I[7], OR0[3]

Q[0], OR1[0]

Q[1], OR1[0]

Q[2], OR1[1]

Q[3], OR1[1]

Q[4], OR1[2]

Q[5], OR1[2]

Q[6], OR1[3]

Q[7], OR1[3]

DA7

DB0

DB1

DB2

DB3

DB4

DB5

DB6

DB7

表7-48 also applies to JMODE 52.

表7-49. JMODE 26 (15-bit, Single Channel, Decimate-by-8, 8 lanes)

OCTET

0

1

NIBBLE

DA0

0

1

2

3

I[0], OR0[0]

I[1], OR0[1]

I[2], OR0[2]

I[3], OR0[3]

Q[0], OR1[0]

Q[1], OR1[1]

Q[2], OR1[2]

Q[3], OR1[3]

DA1

DA2

DA3

DB0

DB1

DB2

DB3

表7-49 also applies to JMODE 54 and JMODE 63.

表7-50. JMODE 27 (15-bit, Single Channel, Decimate-by-8, 16 lanes)

OCTET

0

1

NIBBLE

DA0

DA1

DA2

DA3

DA4

DA5

DA6

DA7

DB0

DB1

DB2

DB3

DB4

DB5

DB6

DB7

0

1

2

3

I[0], OR0[0]

I[1], OR0[1]

I[2], OR0[2]

I[3], OR0[3]

I[4], OR0[4]

I[5], OR0[5]

I[6], OR0[6]

I[7], OR0[7]

Q[0], OR1[0]

Q[1], OR1[1]

Q[2], OR1[2]

Q[3], OR1[3]

Q[4], OR1[4]

Q[5], OR1[5]

Q[6], OR1[6]

Q[7], OR1[7]

表7-51. JMODE 32 (12-bit, Single Channel, DDC Bypass, 6 lanes)

OCTET

NIBBLE

DA0

0

1

0

1

2

3

S[0][11:0]

S[2][11:8]

DA1

S[2][7:0]

S[4][11:4]

DA2

S[4][3:0]

S[6][11:0]

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表7-51. JMODE 32 (12-bit, Single Channel, DDC Bypass, 6 lanes) (continued)

OCTET

NIBBLE

DB0

0

1

0

1

2

3

S[1][11:0]

S[3][11:8]

DB1

S[3][7:0]

S[5][11:4]

DB2

S[5][3:0]

S[7][11:0]

表7-52. JMODE 33 (12-bit, Dual Channel, DDC Bypass, 6 lanes)

OCTET

NIBBLE

DA0

0

1

0

1

2

3

A[0][11:0]

A[1][11:8]

DA1

A[1][7:0]

B[1][7:0]

A[2][11:4]

B[2][11:4]

DA2

A[2][3:0]

B[2][3:0]

A[3][11:0]

B[3][11:0]

DB0

B[0][11:0]

B[1][11:8]

DB1

DB2

表7-53. JMODE 34 (8-bit, Single Channel, 4 lanes)

OCTET

0

NIBBLE

DA0

0

1

S[0]

S[2]

S[1]

S[3]

DA1

DB0

DB1

表7-54. JMODE 35 (8-bit, Dual Channel, 4 lanes)

OCTET

0

NIBBLE

DA0

0

1

A[0]

A[1]

B[0]

B[1]

DA1

DB0

DB1

表7-55. JMODE 37 (15-bit, Dual Channel, Decimate-by-4, 4 lanes)

OCTET

0

1

NIBBLE

DA0

0

1

2

3

AI[0], ORA0[0]

AQ[0], ORA1[0]

BI[0], ORB0[0]

BQ[0], ORB1[0]

DA1

DB0

DB1

表7-56. JMODE 38 (15-bit, Single Channel, Decimate-by-8, 2 lanes)

OCTET

NIBBLE

DA0

0

1

I[0], OR0[0]

Q[0], OR1[0]

DB0

表7-57. JMODE 39 (15-bit, Dual Channel, Decimate-by-8, 2 lanes)

OCTET

NIBBLE

DA0

0

1

2

3

0

1

2

3

4

5

6

7

AI[0], ORA0[0]

BI[0], ORB0[0]

AQ[0], ORA1[0]

BQ[0], ORB1[0]

DB0

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表7-58. JMODE 56 (15-bit, Dual Channel, Decimate-by-16, 2 lanes)

OCTET

0

1

2

3

NIBBLE

DA0

0

1

2

3

4

5

6

7

AI[0], ORA0[0]

BI[0], ORB0[0]

AQ[0], ORA1[0]

BQ[0], ORB1[0]

DB0

7.4.4.4 64B/66B Sync Header Stream Configuration

The sync header stream can be used to identify bit errors on the link or to correct bit errors. Two modes of

operation are available in the device. Cyclic redundancy checking (CRC) can be used to identify bit errors. The

device only supports 12-bit CRC (CRC-12) and does not support the optional 3-bit CRC-3 described by

JESD204C. Alternatively, forward error correction (FEC) can be used to identify bit errors and then correct bit

errors. For information on CRC-12, see Cyclic Redundancy Check (CRC) Mode. For information on FEC, see

Forward Error Correction (FEC) Mode. Set the sync header stream configuration by using the sync header mode

register.

7.4.4.5 Dual DDC and Redundant Data Mode

When operating in dual-channel mode, the data from one channel can be routed to both digital down-converter

blocks by using DIG_BIND_A or DIG_BIND_B (see the digital channel binding register). This feature enables

down-conversion of two separate captured bands from a single ADC channel. The second ADC can be powered

down in this mode by setting PD_ACH or PD_BCH (see the channel power down register).

Additionally, DIG_BIND_A or DIG_BIND_B can be used to provide redundant data to separate digital processors

by routing data from one ADC channel to both JESD204C links. Redundant data mode is available for all

JMODE modes except for the single-channel modes. Both dual DDC mode and redundant data mode are

demonstrated in 图 7-24 where the data for ADC channel A is routed to both DDCs and then transmitted to a

single processor or two processors (for redundancy).

DDC Bypass

JESD204C

LINK A

(DA0-DA7)

ADC

Channel A

DDC A

JMODE

DIG_BIND_A = 0

DDC Bypass

JESD204C

LINK B

(DB0-DB7)

DDC B

ADC

Channel B

JMODE

DIG_BIND_B = 0

图7-24. Dual DDC Mode or Redundant Data Mode for Channel A

7.4.5 Power-Down Modes

The PD input pin allows the devices to be entirely powered down. Power-down can also be controlled by MODE

(see the device configuration register). To power down only one channel in dual channel mode use the channel

power down register. The serial data output drivers are disabled when PD is high. For proper operation in

foreground calibration mode, ADC_OFF in the CAL_CFG register should be programmed to 0x1. When the

device returns to normal operation, the JESD204 link must be re-established, and the ADC pipeline and

decimation filters contain meaningless information so the system must wait a sufficient time for the data to be

flushed.

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7.4.6 Test Modes

A number of device test modes are available. These modes insert known patterns of information into the device

data path for assistance with system debug, development, or characterization.

7.4.6.1 Serializer Test-Mode Details

Test modes are enabled by setting JTEST (see the JESD204C test pattern control register) to the desired test

mode. Each test mode is described in detail in the following sections. Regardless of the test mode, the serializer

outputs (number of lanes, rate) are powered up based on JMODE. Only enable the test modes when the

JESD204C link is disabled. 图7-25 provides a diagram showing the various test mode insertion points.

ADC

JESD204C Block

Active Lanes and

Serial Rates

Set by JMODE

8B/10B or

TRANSPORT

LAYER

SERDES

TX

SCRAMBLER

LINK LAYER

64B/66B

Encoder

ADC

Short Transport Test

Long Transport Test

Octet Ramp

Repeated ILA*

Modified RPAT*

K28.5*

PRBS

Clock Pattern

Serial Outputs High/Low

D21.5

* Applies only to JMODEs using 8B/10B encoding

图7-25. Test Mode Insertion Points

7.4.6.2 PRBS Test Modes

The PRBS test modes bypass the JESD204C transport layer and link layer and are therefore neither scrambled

nor encoded. These test modes produce pseudo-random bit streams that comply with the ITU-T O.150

specification. These bit streams are used with lab test equipment or logic devices that can self-synchronize to

the bit pattern. The initial phase of the pattern is not defined since the receiver self synchronizes.

The sequences are defined by a recursive equation. For example, 方程式14 defines the PRBS7 sequence.

y[n] = y[n –6]⊕y[n –7]

(14)

where

• bit n is the XOR of bit [n –6] and bit [n –7], which are previously transmitted bits

表 7-59 lists equations and sequence lengths for the available PRBS test modes where ⊕ is the XOR operation

and y[n] represents bit n in the PRBS sequence. The initial phase of the pattern is unique for each lane.

表7-59. PBRS Mode Equations

PRBS TEST MODE

PRBS7

SEQUENCE

SEQUENCE LENGTH (bits)

127

y[n] = y[n –6]⊕y[n –7]

y[n] = y[n –5]⊕y[n –9]

y[n] = y[n –14]⊕y[n –15]

y[n] = y[n –18]⊕y[n –23]

y[n] = y[n –28]⊕y[n –31]

PRBS9

511

PRBS15

PRBS23

PRBS31

32,767

8,388,607

2,147,483,647

7.4.6.3 Clock Pattern Mode

In the clock pattern mode, the JESD204C transport layer and link layer are bypassed, so the test sequence is

neither scrambled nor encoded. The pattern consists of a 16-bit long sequence of 8 ones and 8 zeros (1111 1111

0000 0000) that repeats indefinitely.

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7.4.6.4 Ramp Test Mode

In the ramp test mode, the JESD204C link layer operates normally, but the transport layer is disabled and the

input from the formatter is ignored. In 8B/10B modes, the pattern begins after the ILA sequence finishes. In

64B/66B mode, the pattern begins after the serializers are initialized. Each lane transmits an identical octet

stream that is encoded and scrambled by the link layer. The octet stream increments from 0x00 to 0xFF and

repeats. This mode is available for both 8B/10B and 64B/66B modes.

7.4.6.5 Short and Long Transport Test Mode

JESD204C defines both short and long transport test modes to verify that the transport layers in the transmitter

and receiver are operating correctly. The ADC12DJ5200SE has three different short transport layer test patterns

depending on the N' value of the specified JMODE (see Operating Modes). The short transport layer is only

used when control bits are not used. Otherwise, the long transport test mode must be used. ADC12DJ5200SE

supports the long transport test mode for all N' = 16 modes, since these modes use control bits. The transport

layer test modes are the same for 8B/10B mode and 64B/66B modes with identical N' values, since the transport

layer is independent of the link layer.

7.4.6.5.1 Short Transport Test Pattern

Short transport test patterns send a predefined octet format that repeats every frame. In the ADC12DJ5200SE,

all JMODE configurations that have an N' value of 8 or 12 use the short transport test pattern. The N' = 8 short

transport test pattern is shown in 表 7-60. The N' = 12 test patterns are shown in 表 7-61, 表 7-62 and 表 7-63

which cover different values of F and S. All applicable lanes are shown, however only the enabled lanes (lowest

indexed) for the configured JMODE are used.

表7-60. Short Transport Test Pattern for N' = 8 Modes (Length = 2 Frames)

FRAME

DA0

DA1

DA2

DA3

DB0

DB1

DB2

DB3

0

1

0x00

0x01

0x02

0x03

0x00

0x01

0x02

0x03

0xFF

0xFE

0xFD

0xFC

0xFF

0xFE

0xFD

0xFC

表7-61. Short Transport Test Pattern for N' = 12, F = 8 Modes (Length = 1 Frame)

OCTET

NIBBLE

DA0

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

T

0xF01

0xE11

0xD21

0xC31

0xB41

0xA51

0x961

0x871

0xF01

0xE11

0xD21

0xC31

0xB41

0xF02

0xE12

0xD22

0xC32

0xB42

0xA52

0x962

0x872

0xF02

0xE12

0xD22

0xC32

0xB42

0xF03

0xE13

0xD23

0xC33

0xB43

0xA53

0x963

0x873

0xF03

0xE13

0xD23

0xC33

0xB43

0xF04

0xE14

0xD24

0xC34

0xB44

0xA54

0x964

0x874

0xF04

0xE14

0xD24

0xC34

0xB44

0xF05

0xE15

0xD25

0xC35

0xB45

0xA55

0x965

0x875

0xF05

0xE15

0xD25

0xC35

0xB45

DA1

DA2

DA3

DA4

DA5

DA6

DA7

DB0

DB1

DB2

DB3

DB4

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表7-61. Short Transport Test Pattern for N' = 12, F = 8 Modes (Length = 1 Frame) (continued)

OCTET

NIBBLE

DB5

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

T

0xA51

0x961

0x871

0xA52

0x962

0x872

0xA53

0x963

0x873

0xA54

0x964

0x874

0xA55

0x965

0x875

DB6

T

DB7

T

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表7-62. Short Transport Test Pattern for N' = 12, F = 2, S = 8 Modes (Length = 1 Frame)

OCTET

NIBBLE

DA0

0

1

0

1

2

3

0x012

0x3

DA1

0x45

0x01

0x45

0x01

0x67

0x23

0x67

0x23

DA2

0x8

0x4

0x8

0x4

0x9AB

0x567

0x9AB

0x567

DA3

0xCDE

0x012

0xF

0x3

0xF

DA4

DA5

DB0

DB1

DB2

DB3

0xCDE

DB4

DB5

表7-63. Short Transport Test Pattern for N' = 12, F = 2, S = 4 Modes (Length = 1 Frame)

OCTET

NIBBLE

DA0

0

1

0

1

2

3

0x012

0x3

DA1

0x45

0x67

DA2

0x8

0x9AB

DB0

0x012

0x3

DB1

DB2

7.4.6.5.2 Long Transport Test Pattern

The long-transport test mode is used in all of the JMODE modes where N' equals 16 due to the use of control

bits. Patterns are generated in accordance with the JESD204C standard and are different for each output format

as defined in Operating Modes. The rules for the pattern are defined below. 方程式 15 gives the length of the

test pattern. The long transport test pattern is the same for link A and link B, where DAx lanes belong to link A

and DBx lanes belong to link B.

Long Test Pattern Length (Frames) = K × ceil[(M × S + 2) / K]

(15)

• Sample Data:

– Frame 0: Each sample contains N bits, with all samples set to the converter ID (CID) plus 1 (CID + 1). The

CID is defined based on the converter number within the link; two links are used in all modes. Within a

link, the converters are numbered by channel (A or B) and in-phase (I) and quadrature-phase (Q). The

numbering resets for the second link. For instance, in JMODE 11, channel A and channel B data are

separated into separate links (Link A and Link B). The in-phase component for each channel has CID = 0

and the quadrature-phase component has CID = 1.

– Frame 1: Each sample contains N bits, with each sample (for each converter) set as its individual sample

ID (SID) within the frame plus 1 (SID + 1)

– Frame 2 +: Each sample contains N bits, with the data set to 2^N–1for all samples (for example, if N is 15

then 2^N–1= 16384)

• Control Bits (if CS > 0):

– Frame 0 to M × S –1: The control bit belonging to the sample mod (i, S) of the converter floor (i, S) is set

to 1 and all others are set to 0, where i is the frame index (i = 0 is the first frame of the pattern).

Essentially, the control bit walks from the lowest indexed sample to the highest indexed sample and from

the lowest indexed converter to the highest indexed converter, changing position every frame.

– Frame M × S +: All control bits are set to 0

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表7-64 describes an example long transport test pattern for when JMODE = 10, K = 10.

表7-64. Example Long Transport Test Pattern (JMODE = 10, K = 10)

PATTERN REPEATS

→

TIME →

OCTET

0

1

2

3

4

5

6

7

8

9

10

11

12 13 14 15 16 17 18 19 20 21

NUM

DA0

DA1

DB0

DB1

0x0003

0x0004

0x0003

0x0004

0x0002

0x0003

0x0002

0x0003

0x8000

0x0003

0x0004

0x0003

0x0004

Frame

n

Frame

n + 1

Frame

n + 2

Frame

n + 3

Frame

n + 4

Frame

n + 5

Frame

n + 6

Frame

n + 7

Frame

n + 8

Frame

n + 9

Frame

n + 10

The pattern starts at the end of the initial lane alignment sequence (ILAS) and repeats indefinitely as long as the

link remains running. For more details see the JESD204C specification, section 5.1.6.3.

7.4.6.6 D21.5 Test Mode

In this test mode, the controller transmits a continuous stream of D21.5 characters (alternating 0s and 1s). This

mode applies to 8B/10B and 64B/66B modes.

7.4.6.7 K28.5 Test Mode

In this test mode, the controller transmits a continuous stream of K28.5 characters. This mode only applies to

8B/10B modes.

7.4.6.8 Repeated ILA Test Mode

In this test mode, the JESD204C link layer operates normally, except that the ILA sequence (ILAS) repeats

indefinitely instead of starting the data phase. Whenever the receiver issues a synchronization request, the

transmitter initiates code group synchronization. Upon completion of code group synchronization, the transmitter

repeatedly transmits the ILA sequence. This mode only applies to 8B/10B modes.

7.4.6.9 Modified RPAT Test Mode

A 12-octet repeating pattern is defined in INCITS TR-35-2004. The purpose of this pattern is to generate white

spectral content for JESD204C compliance and jitter testing. 表 7-65 lists the pattern before and after 8B/10B

encoding. This mode only applies to 8B/10B modes.

表7-65. Modified RPAT Pattern Values

20b OUTPUT OF 8B/10B ENCODER

OCTET NUMBER

Dx.y NOTATION

8-BIT INPUT TO 8B/10B ENCODER

(Two Characters)

0

1

D30.5

D23.6

D3.1

0xBE

0xD7

0x23

0x47

0x6B

0x8F

0xB3

0x14

0x5E

0xFB

0x35

0x59

0x86BA6

2

0xC6475

0xD0E8D

0xCA8B4

0x7949E

0xAA665

3

D7.2

4

D11.3

D15.4

D19.5

D20.0

D30.2

D27.7

D21.1

D25.2

5

6

7

8

9

10

11

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7.4.7 Calibration Modes and Trimming

ADC12DJ5200SE has two calibration modes available: foreground calibration and background calibration. When

foreground calibration is initiated the ADCs are automatically taken offline and the output data becomes mid-

code (0x000 in 2's complement) while a calibration is occurring. Background calibration allows the ADC to

continue normal operation while the ADC cores are calibrated in the background by swapping in a different ADC

core to take its place. Additional offset calibration features are available in both foreground and background

calibration modes. Further, a number of ADC parameters can be trimmed to optimize performance in a user

system.

ADC12DJ5200SE consists of a total of six sub-ADCs, each referred to as a bank, with two banks forming an

ADC core. The banks sample out-of-phase so that each ADC core is two-way interleaved. The six banks form

three ADC cores, referred to as ADC A, ADC B, and ADC C. In foreground calibration mode, ADC A samples

INA and ADC B samples INB in dual-channel mode and both ADC A and ADC B sample INA (or INB) in single-

channel mode. In the background calibration modes, the third ADC core, ADC C, is swapped in periodically for

ADC A and ADC B so that they can be calibrated without disrupting operation. 图7-26 provides a diagram of the

calibration system including labeling of the banks that make up each ADC core. When calibration is performed

the linearity, gain and offset voltage for each bank are calibrated to an internally generated calibration signal.

The analog inputs can be driven during calibration, in both foreground and background calibration, except that

when offset calibration (OS_CAL or BGOS_CAL) is used there must be no signals (or aliased signals) near DC

for proper estimation of the offset (see the Offset Calibration section).

ADC A

Bank 0

MUX

Calibration

Signal

INA

Bank 1

ADC A

Output

MUX

Calibration

Engine

ADC C

Bank 2

Bank 3

Calibration

Engine

MUX

Calibration

Signal

Calibration

Engine

ADC B

Output

ADC B

MUX

INB

Bank 4

Bank 5

MUX

Calibration

Engine

Calibration

Signal

Calibration

Engine

图7-26. ADC12DJ5200SE Calibration System Block Diagram

In addition to calibration, a number of ADC parameters are user controllable to provide trimming for optimal

performance. These parameters include input offset voltage, ADC gain, interleaving timing, and input termination

resistance. The default trim values are programmed at the factory to unique values for each device that are

determined to be optimal at the test system operating conditions. The user can read the factory-programmed

values from the trim registers and adjust as desired. The register fields that control the trimming are labeled

according to the input that is being sampled (INA or INB), the bank that is being trimmed, or the ADC core that is

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being trimmed. The user is not expected to change the trim values as operating conditions change, however

optimal performance can be obtained by doing so. Any custom trimming must be done on a per device basis

because of process variations, meaning that there is no global optimal setting for all parts. See the Trimming

section for information about the available trim parameters and associated registers.

7.4.7.1 Foreground Calibration Mode

Foreground calibration requires the ADC to stop converting the analog input signals during the procedure.

Foreground calibration always runs on power-up and the user must wait a sufficient time before programming

the device to be sure the calibration is finished. Foreground calibration can be initiated by triggering the

calibration engine. The trigger source can be either the CAL_TRIG pin or CAL_SOFT_TRIG (see the calibration

software trigger register) and is chosen by setting CAL_TRIG_EN (see the calibration pin configuration register).

7.4.7.2 Background Calibration Mode

Background calibration mode allows the ADC to continuously operate, with no interruption of data. This

continuous operation is accomplished by activating an extra ADC core that is calibrated and then takes over

operation for one of the other previously active ADC cores. When that ADC core is taken off-line, that ADC is

calibrated and can in turn take over to allow the next ADC to be calibrated. This process operates continuously,

ensuring the ADC cores always provide the optimum performance regardless of system operating condition

changes. Because of the additional active ADC core, background calibration mode has increased power

consumption in comparison to foreground calibration mode. The low-power background calibration (LPBG) mode

discussed in the Low-Power Background Calibration (LPBG) Mode section provides reduced average power

consumption in comparison with the standard background calibration mode. Background calibration can be

enabled by setting CAL_BG (see the calibration configuration 0 register). CAL_TRIG_EN must be set to 0 and

CAL_SOFT_TRIG must be set to 1.

Great care has been taken to minimize effects on converted data as the core switching process occurs, however,

small brief glitches may still occur on the converter data as the cores are swapped.

7.4.7.3 Low-Power Background Calibration (LPBG) Mode

Low-power background calibration (LPBG) mode reduces the power-overhead of enabling additional ADC cores.

Off-line cores are powered down until ready to be calibrated and put on-line. Set LP_EN = 1 to enable the low-

power background calibration feature. LP_SLEEP_DLY is used to adjust the amount of time an ADC sleeps

before waking up for calibration (if LP_EN = 1 and LP_TRIG = 0). LP_WAKE_DLY sets how long the core is

allowed to stabilize before calibration and being put on-line. LP_TRIG is used to select between an automatic

switching process or one that is controlled by the user via CAL_SOFT_TRIG or CAL_TRIG. In this mode there is

an increase in power consumption during the ADC core calibration. The power consumption roughly alternates

between the power consumption in foreground calibration when the spare ADC core is sleeping to the power

consumption in background calibration when the spare ADC is being calibrated. Design the power-supply

network to handle the transient power requirements for this mode. LPBG calibration mode is not recommended

to be used in single channel operating modes.

7.4.8 Offset Calibration

Foreground calibration and background calibration modes inherently calibrate the offsets of the ADC cores;

however, the input buffers sit outside of the calibration loop and therefore their offsets are not calibrated by the

standard calibration process. In both dual-channel mode and single-channel mode, uncalibrated input buffer

offsets result in a shift in the mid-code output (DC offset). Further, in single-channel mode uncalibrated input

buffer offsets can result in a fixed spur at f_S/ 2. A separate calibration is provided to correct the input buffer

offsets.

There must be no signals at or near DC or aliased signals that fall at or near DC to properly calibration the

offsets. Requiring the system to be sure of the condition during normal operation, or have the ability to mute the

input signal during calibration. The lower bandwidth of the balun will signficantly suppress signals near DC, but

care must the taken to avoid AC signals near the sample rate from aliasing near DC. Foreground offset

calibration is enabled via CAL_OS and only performs the calibration one time as part of the foreground

calibration procedure. Background offset calibration is enabled via CAL_BGOS and continues to correct the

offset as part of the background calibration routine to account for operating condition changes. When

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CAL_BGOS is set, the system must be sure there are no DC or near DC signals or aliased signals that fall at or

near DC during normal operation. When background offset calibration is used the analog to digital conversion is

disturbed by a bandwidth difference. The calibration time is relatively long becuase the offset calibration engine

requires a lot of averaging. A preferred method for offset calibration is to use foreground calibration as a one-

time operation so the timing of the disturbing glitch can be controlled. A one time foreground calibration can be

performed by setting CAL_OS to 1 before setting CAL_EN. However, this will not correct for variations as

operating conditions change.

The offset calibration correction uses the input offset voltage trim registers (see 表 7-66) to correct the offset;

therefore, must not be written by the user when offset calibration is used. The user can read the calibrated

values by reading the OADJ_x_VINy registers, where x is the ADC core and y is the input (INA or INB), after

calibration is completed. Only read the values when FG_DONE is read as 1 when using foreground offset

calibration (CAL_OS = 1) and do not read the values when using background offset calibration (CAL_BGOS =

1).

7.4.9 Trimming

表 7-66 lists the parameters that can be trimmed and the associated registers. User trimming is limited to

foreground (FG) calibration mode only.

表7-66. Trim Register Descriptions

TRIM PARAMETER

TRIM REGISTER

NOTES

Band-gap reference

BG_TRIM

Measurement on BG output pin.

RTRIM_x,

where x = A for INA or B for INB)

Input termination resistance

The device must be powered on with a clock applied.

OADJ_A_FG0_VINx, OADJ_A_FG90_VINx and

OADJ_B_FG0_VINx,

Input offset adjustment in dual channel mode consists

where OADJ_A applies to ADC core A and OADJ_B of changing OADJ_A_FG0_VINA for channel A and

applies to ADC core B, FG0 applies to dual channel OADJ_B_FG0_VINB for channel B. In single channel

mode for ADC cores A and B and single channel mode, OADJ_A_FG90_VINx and OADJ_B_FG0_VINx

mode for ADC core B, FG90 applies to ADC core A must be adjusted together to trim the input offset or

in single channel mode and x = A for INA or B for adjusted separate to compensate the f_S/2 offset spur.

INB)

Input offset voltage

Set FS_RANGE_A and FS_RANGE_B to default values

before trimming the input. Use FS_RANGE_A and

FS_RANGE_B to adjust the full-scale input voltage. The

GAIN_xy_FGDUAL registers apply to Dual Channel

Mode and the GAIN_xy_FGDES registers apply to the

GAIN_xy_FGDUAL or GAIN_xy_FGDES,

Single Channel Mode. To trim the gain of ADC core A or

where x = ADC channel (A or B) and y = bank

INA and INB gain

B, change GAIN_x0_FGDUAL and GAIN_x1_FGDUAL

number (0 or 1)

(or GAIN_x0_FGDES and GAIN_x1_FGDES) together

in the same direction. To trim the gain of the two banks

within ADC A or B, change GAIN_x0_FGDUAL and

GAIN_x1_FGDUAL (or GAIN_x0_FGDES and

GAIN_x1_FGDES) in opposite directions.

Full-scale input voltage adjustment for each input. The

default value is effected by GAIN_Bx (x = 0, 1, 4 or 5).

INA and INB full-scale input

voltage

FS_RANGE_x,

Trim GAIN_Bx with FS_RANGE_x set to the default

where x = A for INA or B for INB)

value. FS_RANGE_x can then be used to trim the full-

scale input voltage.

Trims the timing between the two banks of an ADC core

(ADC A or B). The 0° clock phase is used for dual

channel mode and for ADC B in single channel mode.

The –90° clock phase is used only for ADC A in single-

channel mode. A mismatch in the timing between the

two banks of an ADC core can result in an f_S/2-f_INspur

Bx_TIME_y,

where x = bank number (0, 1, 4 or 5)

and y = 0° (0) or –90° (90) clock phase

Intra-ADC core timing (bank

timing)

in dual channel mode or f_S/4±f_INspurs in single channel

mode.

The suffix letter (A or B) indicates the ADC core that is

Inter-ADC core timing (dual-

channel mode)

being trimmed. Changing either TADJ_A or TADJ_B

adjusts the sampling instance of ADC A relative to ADC

TADJ_A, TADJ_B

B in dual channel mode.

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表7-66. Trim Register Descriptions (continued)

TRIM PARAMETER

TRIM REGISTER

NOTES

These trim registers are used to adjust the timing of

ADC core A relative to ADC core B in single channel

mode. A mismatch in the timing will result in an f_S/2-f_IN

spur that is signal dependent. Changing either

TADJ_A_FG90_VINx or TADJ_B_FG0_VINx changes

the relative timing of ADC core A relative to ADC core B

in single channel mode.

Inter-ADC core timing

(single-channel mode)

TADJ_A_FG90_VINx, TADJ_B_FG0_VINx,

where x = analog input (INA or INB)

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7.5 Programming

7.5.1 Using the Serial Interface

The serial interface is accessed using the following four pins: serial clock (SCLK), serial data in (SDI), serial data

out (SDO), and serial interface chip-select ( SCS). Register access is enabled through the SCS pin.

7.5.1.1 SCS

This signal must be asserted low to access a register through the serial interface. Setup and hold times with

respect to the SCLK must be observed.

7.5.1.2 SCLK

Serial data input is accepted at the rising edge of this signal. SCLK has no minimum frequency requirement.

7.5.1.3 SDI

Each register access requires a specific 24-bit pattern at this input. This pattern consists of a read-and-write

(R/W) bit, register address, and register value. The data are shifted in MSB first and multi-byte registers are

always in little-endian format (least significant byte stored at the lowest address). Setup and hold times with

respect to the SCLK must be observed (see the Timing Requirements table).

7.5.1.4 SDO

The SDO signal provides the output data requested by a read command. This output is high impedance during

write bus cycles and during the read bit and register address portion of read bus cycles.

As shown in 图7-27, each register access consists of 24 bits. The first bit is high for a read and low for a write.

The next 15 bits are the address of the register that is to be written to. During write operations, the last eight bits

are the data written to the addressed register. During read operations, the last eight bits on SDI are ignored and,

during this time, the SDO outputs the data from the addressed register. 图7-27 shows the serial protocol details.

Single Register Access

SCS

1

8

16

17

24

SCLK

SDI

Command Field

Data Field

R/W A14 A13 A12 A11 A10 A9

A8

A7

A6

A5

A4

A3

A2

A1 A0

D7

D6

D5

D4

D3

D2

D1 D0

Data Field

High Z

SDO

(read mode)

D7

D6

D5

D4

D3 D2

D1

D0

图7-27. Serial Interface Protocol: Single Read/Write

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7.5.1.5 Streaming Mode

The serial interface supports streaming reads and writes. In this mode, the initial 24 bits of the transaction

specifics the access type, register address, and data value as normal. Additional clock cycles of write or read

data are immediately transferred, as long as the SCS input is maintained in the asserted (logic low) state. The

register address auto increments (default) or decrements for each subsequent 8-bit transfer of the streaming

transaction. The ADDR_ASC bit (register 000h, bits 5 and 2) controls whether the address value ascends

(increments) or descends (decrements). Streaming mode can be disabled by setting the ADDR_HOLD bit (see

the user SPI configuration register). 图7-28 shows the streaming mode transaction details.

Multiple Register Access

SCS

1

8

16

17

24

25

32

SCLK

SDI

Command Field

Data Field (write mode)

D4 D3 D2 D1

Data Field (write mode)

D5 D4 D3 D2

A1

1

R/W A14 A13 A12

A10 A9

A8

A7

A6

A5

A4

A3

A2

A1

A0

D7

D6

D5

D0

D7

D6

D1

D0

Data Field

D4 D3 D2

Data Field

D3 D2

High Z

SDO

(read mode)

D7

D6

D5

D1

D0

D7

D6

D5

D4

D1

D0

图7-28. Serial Interface Protocol: Streaming Read/Write

See the SPI Register Map section for detailed information regarding the registers.

备注

The serial interface must not be accessed during ADC calibration. Accessing the serial interface

during this time impairs the performance of the device until the device is calibrated correctly. Writing or

reading the serial registers also reduces dynamic ADC performance for the duration of the register

access time.

English Data Sheet: SLVSGH5

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7.6 SPI Register Map

表 7-67 lists the SPI_Register_Map registers. All register offset addresses not listed in 表 7-67 should be

considered as reserved locations and the register contents should not be modified.

表7-67. SPI REGISTER MAP Registers

Address

0x0

Acronym

Register Name

Section

Go

CONFIG_A

DEVICE_CONFIG

CHIP_TYPE

CHIP_ID

Configuration A (default: 0x30)

0x2

Device Configuration (default: 0x00)

0x3

Chip Type (Default: 0x03)

0x4

Chip Identification

0xC

VENDOR_ID

USR0

Vendor Identification (Default = 0x0451)

User SPI Configuration (Default: 0x00)

Clock Control 0 (default: 0x00)

0x10

0x29

0x2A

0x02B

0x2C

0x30

0x32

0x38

0x3B

0x48

0x60

0x61

0x62

0x64

0x68

0x6A

0x6B

0x6C

0x6E

0x70

0x71

0x7A

0x7B

0x7C

0x7E

0x7F

0x9D

0x102

0x103

0x112

0x113

0x142

0x152

0x160

0x200

0x201

CLK_CTRL0

CLK_CTRL1

CLK_CNTL2

SYSREF_POS

FS_RANGE_A

FS_RANGE_B

BG_BYPASS

TMSTP_CTRL

SER_PE

Clock Control 1 (default: 0x00)

Clock Control 2 (default: 0x11)

SYSREF Capture Position (Read-Only, Default: undefined)

FS_RANGE_A (default: 0xA000)

FS_RANGE_B (default: 0xA000)

Band-Gap Bypass (default: 0x00)

TMSTP Control (default: 0x00)

Serializer Pre-Emphasis Control (default: 0x00)

Input Mux Control (default: 0x01)

INPUT_MUX

CAL_EN

Calibration Enable (Default: 0x01)

CAL_CFG0

CAL_CFG2

CAL_AVG

Calibration Configuration 0 (Default: 0x01)

Calibration Configuration 0 (Default: 0x02)

Calibration Averaging (default: 0x61)

CAL_STATUS

CAL_PIN_CFG

CAL_SOFT_TRIG

CAL_LP

Calibration Status (default: undefined) (read-only)

Calibration Pin Configuration (default: 0x00)

Calibration Software Trigger (default: 0x01)

Low-Power Background Calibration (default: 0x88)

Calibration Data Enable (default: 0x00)

Calibration Data (default: undefined)

CAL_DATA_EN

CAL_DATA

GAIN_TRIM_A

GAIN_TRIM_B

BG_TRIM

Gain DAC Trim A (default from Fuse ROM)

Gain DAC Trim B (default from Fuse ROM)

Band-Gap Trim (default from Fuse ROM)

Resistor Trim for VinA (default from Fuse ROM)

Resistor Trim for VinB (default from Fuse ROM)

ADC Dither Control (default from Fuse ROM)

Time Adjustment for Bank 0 (0° clock) (default from Fuse ROM)

Time Adjustment for Bank 0 (-90° clock) (default from Fuse ROM)

Time Adjustment for Bank 1 (0° clock) (default from Fuse ROM)

Time Adjustment for Bank 1 (-90° clock) (default from Fuse ROM)

Time Adjustment for Bank 4 (0° clock) (default from Fuse ROM)

Time Adjustment for Bank 5 (0° clock) (default from Fuse ROM)

LSB Control Bit Output (default: 0x00)

JESD204C Subsystem Enable (default: 0x01)

JESD204C Mode (default: 0x02)

RTRIM_A

RTRIM_B

ADC_DITH

B0_TIME_0

B0_TIME_90

B1_TIME_0

B1_TIME_90

B4_TIME_0

B5_TIME_0

LSB_CTRL

JESD_EN

JMODE

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表7-67. SPI REGISTER MAP Registers (continued)

Address

0x202

0x203

0x204

0x205

0x206

0x207

0x208

0x209

0x20A

0x20B

0x20F

0x210

0x211

0x212

0x213

0x214

0x215

0x216

0x217

0x219

0x220

0x224

0x228

0x22C

0x230

0x234

0x238

0x23C

0x240

0x244

0x248

0x24C

0x250

0x254

0x258

0x25C

0x270

0x297

0x2A2

0x2B0

0x2B1

0x2B2

0x2B5

0x2B8

0x2C0

Acronym

KM1

Register Name

Section

Go

JESD204C K Parameter (default: 0x1F)

JSYNC_N

JCTRL

JESD204C Manual Sync Request (default: 0x01)

JESD204C Control (default: 0x03)

JTEST

JESD204C Test Control (default: 0x00)

DID

JESD204C DID Parameter (default: 0x00)

FCHAR

JESD204C Frame Character (default: 0x00)

JESD204C / System Status Register

JESD_STATUS

PD_CH

JESD204C Channel Power Down (default: 0x00)

JESD204C Extra Lane Enable (Link A) (default: 0x00)

JESD204C Extra Lane Enable (Link B) (default: 0x00)

JESD204C Sync Word Mode (default: 0x00)

DDC Configuration (default: 0x00)

JEXTRA_A

JEXTRA_B

SHMODE

DDC_CFG

OVR_T0

OVR_T1

OVR_CFG

CMODE

Over-range Threshold 0 (default: 0xF2)

Over-range Threshold 1 (default: 0xAB)

Over-range Enable / Hold Off (default: 0x07)

DDC NCO Configuration Preset Mode (default: 0x00)

DDC NCO Configuration Preset Select (default: 0x00)

Digital Channel Binding (default: 0x02)

CSEL

DIG_BIND

NCO_RDIV

NCO_SYNC

FREQA0

PHASEA0

FREQA1

PHASEA1

FREQA2

PHASEA2

FREQA3

PHASEA3

FREQB0

PHASEB0

FREQB1

PHASEB1

FREQB2

PHASEB2

FREQB3

PHASEB3

INIT_STATUS

SPIN_ID

TESTBUS

SRC_EN

SRC_CFG

SRC_STATUS

TAD

NCO Reference Divisor (default: 0x0000)

NCO Synchronization (default: 0x02)

NCO Frequency (Channel A, Preset 0) (default: 0xC0000000)

NCO Phase (Channel A, Preset 0) (default: 0x0000)

NCO Frequency (Channel A, Preset 1) (default: 0xC0000000)

NCO Phase (Channel A, Preset 1) (default: 0x0000)

NCO Frequency (Channel A, Preset 2) (default: 0xC0000000)

NCO Phase (Channel A, Preset 2) (default: 0x0000)

NCO Frequency (Channel A, Preset 3) (default: 0xC0000000)

NCO Phase (Channel A, Preset 3) (default: 0x0000)

NCO Frequency (Channel B, Preset 0) (default: 0xC0000000)

NCO Phase (Channel B, Preset 0) (default: 0x0000)

NCO Frequency (Channel B, Preset 1) (default: 0xC0000000)

NCO Phase (Channel B, Preset 1) (default: 0x0000)

NCO Frequency (Channel B, Preset 2) (default: 0xC0000000)

NCO Phase (Channel B, Preset 2) (default: 0x0000)

NCO Frequency (Channel B, Preset 3) (default: 0xC0000000)

NCO Phase (Channel B, Preset 3) (default: 0x0000)

Initialization Status (read-only)

Chip Spin Identifier (default: See description, read-only)

Analog Test Bus Control (default: 0x00)

SYSREF Calibration Enable (default: 0x00)

SYSREF Calibration Configuration (default: 0x05)

SYSREF Calibration Status (read-only, default: undefined)

DEVCLK Timing Adjust (default: 0x00)

TAD_RAMP

ALARM

DEVCLK Timing Adjust Ramp Control (default: 0x00)

Alarm Interrupt (read-only)

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表7-67. SPI REGISTER MAP Registers (continued)

Address

0x2C1

0x2C2

0x2C4

0x310

0x313

0x314

Acronym

Register Name

Section

Go

ALM_STATUS

ALM_MASK

FIFO_LANE_ALM

TADJ_A

Alarm Status (default: 0x3F, write to clear)

Alarm Mask Register (default: 0x3F)

Go

FIFO Overflow/Underflow Alarm (default: 0xFFFF)

Timing Adjust for A-ADC operating in Dual Channel Mode (default from Fuse ROM)

Timing Adjust for B-ADC operating in Dual Channel Mode (default from Fuse ROM)

Go

TADJ_B

Go

TADJ_A_FG90_VINA

Timing Adjust for A-ADC operating in Single Channel Mode and sampling INA

(default from Fuse ROM)

Go

0x315

0x31A

0x31B

0x344

0x346

0x348

0x34A

TADJ_B_FG0_VINA

TADJ_A_FG90_VINB

TADJ_B_FG0_VINB

OADJ_A_FG0_VINA

OADJ_A_FG0_VINB

OADJ_A_FG90_VINA

OADJ_A_FG90_VINB

Timing Adjust for B-ADC operating in Single Channel Mode and sampling INA

(default from Fuse ROM)

Go

Timing Adjust for A-ADC operating in Single Channel Mode and sampling INB

(default from Fuse ROM)

Timing Adjust for B-ADC operating in Single Channel Mode and sampling INB

(default from Fuse ROM)

Offset Adjustment for A-ADC operating in Dual Channel Mode sampling INA (default

from Fuse ROM)

Offset Adjustment for A-ADC operating in Dual Channel Mode sampling INB (default

from Fuse ROM)

Offset Adjustment for A-ADC operating in Single Channel Mode sampling INA

(default from Fuse ROM)

Offset Adjustment for A-ADC operating in Single Channel Mode sampling INB

(default from Fuse ROM)

0x34C

0x34E

0x350

0x351

0x352

0x353

0x354

OADJ_B_FG0_VINA

OADJ_B_FG0_VINB

GAIN_A0_FGDUAL

GAIN_A1_FGDUAL

GAIN_B0_FGDUAL

GAIN_B1_FGDUAL

GAIN_A0_FGDES

Offset Adjustment for B-ADC sampling INA (default from Fuse ROM)

Go

Offset Adjustment for B-ADC sampling INB (default from Fuse ROM)

Fine Gain Adjust for ADC A Bank 0 in Dual Channel Mode (default from Fuse ROM)

Fine Gain Adjust for ADC A Bank 1 in Dual Channel Mode (default from Fuse ROM)

Fine Gain Adjust for ADC B Bank 0 in Dual Channel Mode (default from Fuse ROM)

Fine Gain Adjust for ADC B Bank 1 in Dual Channel Mode (default from Fuse ROM)

Fine Gain Adjust for ADC A Bank 0 in Single Channel Mode (default from Fuse

ROM)

0x355

0x356

0x357

GAIN_A1_FGDES

GAIN_B0_FGDES

GAIN_B1_FGDES

Fine Gain Adjust for ADC A Bank 1 in Single Channel Mode (default from Fuse

ROM)

Go

Fine Gain Adjust for ADC B Bank 0 in Single Channel Mode (default from Fuse

ROM)

Fine Gain Adjust for ADC B Bank 1 in Single Channel Mode (default from Fuse

ROM)

0x400

0x418

0x41A

0x41C

0x41E

0x420

0x423

0x425

0x427

0x429

0x448

0x44A

0x44C

0x44E

PFIR_CFG

PFIR_A0

PFIR_A1

PFIR_A2

PFIR_A3

PFIR_A4

PFIR_A5

PFIR_A6

PFIR_A7

PFIR_A8

PFIR_B0

PFIR_B1

PFIR_B2

PFIR_B3

Programmable FIR Mode (default: 0x00)

PFIR Coefficient A0

PFIR Coefficient A1

PFIR Coefficient A2

PFIR Coefficient A3

PFIR Coefficient A4

PFIR Coefficient A5

PFIR Coefficient A6

PFIR Coefficient A7

PFIR Coefficient A8

PFIR Coefficient B0

PFIR Coefficient B1

PFIR Coefficient B2

PFIR Coefficient B3

Go

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表7-67. SPI REGISTER MAP Registers (continued)

Address

0x450

0x453

0x455

0x457

0x459

Acronym

PFIR_B4

PFIR_B5

PFIR_B6

PFIR_B7

PFIR_B8

Register Name

Section

Go

PFIR Coefficient B4

PFIR Coefficient B5

PFIR Coefficient B6

PFIR Coefficient B7

PFIR Coefficient B8

Go

Complex bit access types are encoded to fit into small table cells. 表 7-68 shows the codes that are used for

access types in this section.

表7-68. SPI_Register_Map Access Type Codes

Access Type

Read Type

R

Code

Description

R

Read

Write Type

W

Write

Reset or Default Value

-n

Value after reset or the default

value

Register Array Variables

i,j,k,l,m,n

When these variables are used in

a register name, an offset, or an

address, they refer to the value of

a register array where the register

is part of a group of repeating

registers. The register groups

form a hierarchical structure and

the array is represented with a

formula.

y

When this variable is used in a

register name, an offset, or an

address it refers to the value of a

register array.

7.6.1 CONFIG_A Register (Address = 0x0) [reset = 0x30]

CONFIG_A is shown in 图7-29 and described in 表7-69.

Return to the Summary Table.

Configuration A (default: 0x30)

图7-29. CONFIG_A Register

7

6

5

4

3

2

1

0

SOFT_RESET

R/W-0x0

RESERVED

R/W-0x0

ASCEND

R/W-0x1

SDO_ACTIVE

R-0x1

RESERVED

R/W-0x0

表7-69. CONFIG_A Register Field Descriptions

Bit

Field

Type

Reset

Description

7

SOFT_RESET

R/W

0x0

Setting this bit causes a full reset of the chip and all SPI registers

(including CONFIG_A). This bit is self-clearing. After writing this bit,

the part may take up to 750ns to reset. During this time, do not

perform any SPI transactions.

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表7-69. CONFIG_A Register Field Descriptions (continued)

Bit

6

Field

Type

R/W

Reset

Description

RESERVED

ASCEND

0x0

5

0x1

0 : Address is decremented during streaming reads/writes

1 : Address is incremented during streaming reads/writes (default)

4

SDO_ACTIVE

RESERVED

R

0x1

0x0

Always returns 1. Always use SDO for SPI reads.

No SDIO mode supported.

3:0

R/W

7.6.2 DEVICE_CONFIG Register (Address = 0x2) [reset = 0x00]

DEVICE_CONFIG is shown in 图7-30 and described in 表7-70.

Return to the Summary Table.

Device Configuration (default: 0x00)

图7-30. DEVICE_CONFIG Register

7

6

5

4

3

2

1

0

RESERVED

R/W-0x0

MODE

R/W-0x0

表7-70. DEVICE_CONFIG Register Field Descriptions

Bit

Field

Type

R/W

Reset

Description

7:2

1:0

RESERVED

MODE

0x0

0 : Normal operation (default)

1 : Reserved

2 : Reserved

3 : Power down (lowest power, slower resume)

7.6.3 CHIP_TYPE Register (Address = 0x3) [reset = 0x03]

CHIP_TYPE is shown in 图7-31 and described in 表7-71.

Return to the Summary Table.

Chip Type (Default: 0x03)

图7-31. CHIP_TYPE Register

7

6

5

4

3

2

1

0

RESERVED

R/W-0x0

CHIP_TYPE

R-0x3

表7-71. CHIP_TYPE Register Field Descriptions

Bit

Field

Type

R/W

R

Reset

Description

7:4

3:0

RESERVED

CHIP_TYPE

0x0

0x3

Always returns 0x3, indicating that the part is a high speed ADC.

7.6.4 CHIP_ID Register (Address = 0x4) [reset = 0x0]

CHIP_ID is shown in 图7-32 and described in 表7-72.

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Return to the Summary Table.

Chip Identification

图7-32. CHIP_ID Register

15

14

13

5

12

11

10

2

9

1

8

0

CHIP_ID

R-0x0

7

6

4

3

CHIP_ID

R-0x0

表7-72. CHIP_ID Register Field Descriptions

Bit

15:0

Field

Type

Reset

Description

CHIP_ID

R

0x0

Returns 0x0021 indicating the device is in the ADC12DJ5200RF

family.

7.6.5 VENDOR_ID Register (Address = 0xC) [reset = 0x0]

VENDOR_ID is shown in 图7-33 and described in 表7-73.

Return to the Summary Table.

Vendor Identification (Default = 0x0451)

图7-33. VENDOR_ID Register

15

7

14

6

13

5

12

11

10

2

9

1

8

0

VENDOR_ID

R-0x0

4

3

VENDOR_ID

R-0x0

表7-73. VENDOR_ID Register Field Descriptions

Bit

15:0

Field

VENDOR_ID

Type

Reset

Description

R

0x0

Always returns 0x0451 (Vendor ID for Texas Instruments)

7.6.6 USR0 Register (Address = 0x10) [reset = 0x00]

USR0 is shown in 图7-34 and described in 表7-74.

Return to the Summary Table.

User SPI Configuration (Default: 0x00)

图7-34. USR0 Register

7

6

5

4

3

2

1

0

RESERVED

R/W-0x0

ADDR_HOLD

R/W-0x0

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表7-74. USR0 Register Field Descriptions

Bit

7:1

0

Field

Type

R/W

Reset

Description

RESERVED

0x0

ADDR_HOLD

0x0

0 : Use ASCEND register to select address ascend/descend mode

(default)

1 : Address stays constant throughout streaming operation; useful for

reading and writing calibration vector information at the CAL_DATA

register

7.6.7 CLK_CTRL0 Register (Address = 0x29) [reset = 0x00]

CLK_CTRL0 is shown in 图7-35 and described in 表7-75.

Return to the Summary Table.

Clock Control 0 (default: 0x00)

图7-35. CLK_CTRL0 Register

7

6

5

4

3

2

1

0

RESERVED

SYSREF_PRO SYSREF_REC SYSREF_ZOO

SYSREF_SEL

R/W-0x0

C_EN

V_EN

M

R/W-0x0

表7-75. CLK_CTRL0 Register Field Descriptions

Bit

7

Field

RESERVED

Type

R/W

Reset

Description

0x0

6

SYSREF_PROC_EN

0x0

This bit enables the SYSREF processor, which allows the device to

process SYSREF events (default: disabled). SYSREF_RECV_EN

must be set before setting SYSREF_PROC_EN.

5

4

SYSREF_RECV_EN

SYSREF_ZOOM

R/W

0x0

Set this bit to enable the SYSREF receiver circuit (default: disabled)

Set this bit to zoom in the SYSREF windowing status and delays

(impacts SYSERF_POS and SYSREF_SEL). When set, the delays

used in the SYSREF windowing feature (reported in the

SYSREF_POS register) become smaller. Use SYSREF_ZOOM for

high clock rates, specifically when multiple SYSREF valid windows

are encountered in the SYSREF_POS register; see the SYSREF

Position Detector and Sampling Position Selection (SYSREF

Windowing) section.

3:0

SYSREF_SEL

R/W

0x0

Set this field to select which SYSREF delay to use. Set this field

based on the results returned by SYSREF_POS; see the SYSREF

Position Detector and Sampling Position Selection (SYSREF

Windowing) section. These bits must be set to 0 to use SYSREF

calibration; see the Automatic SYSREF Calibration section.

7.6.8 CLK_CTRL1 Register (Address = 0x2A) [reset = 0x00]

CLK_CTRL1 is shown in 图7-36 and described in 表7-76.

Return to the Summary Table.

Clock Control 1 (default: 0x00)

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图7-36. CLK_CTRL1 Register

7

6

5

4

3

2

1

0

RESERVED

R/W-0x0

SYSREF_TIME DEVCLK_LVPE SYSREF_LVPE SYSREF_INVE

_STAMP_EN

CL_EN

RTED

R/W-0x0

表7-76. CLK_CTRL1 Register Field Descriptions

Bit

Field

RESERVED

Type

Reset

Description

7:4

3

R/W

0x0

SYSREF_TIME_STAMP_ R/W

EN

0x0

The SYSREF signal can be observed on the LSB of the JESD204C

output samples when SYSREF_TIMESTAMP_EN and

TIME_STAMP_EN are both set. Only supported in DDC bypass

modes (i.e. D=1). This bit allows SYSREF± to be used as the

timestamp input.

2

1

0

DEVCLK_LVPECL_EN

SYSREF_LVPECL_EN

SYSREF_INVERTED

R/W

0x0

Activate DC-coupled, low-voltage PECL mode for CLK±; see the Pin

Functions table.

Activate DC-coupled, low-voltage PECL mode for SYSREF±; see the

Pin Functions table.

This bit inverts the SYSREF signal used for alignment.

7.6.9 CLK_CTRL2 Register (Address = 0x02B) [reset = 0x11]

CLK_CTRL2 is shown in and described in 图7-37 and described in 表7-77.

Return to the Summary Table.

Clock Control 2 (default: 0x11)

图7-37. CLK_CTRL2 Register

7

6

5

4

3

2

1

0

RESERVED

C_CLK_FEEDB

ACK_GAIN

Reserved

EN_VA11_NOIS

E_SUPPR

CLKSAMP_DEL

R/W-0x0

R/W-0x1

R/W-0x0

R/W-0x1

表7-77. CLK_CTRL2 Register Field Descriptions

Bit

Field

RESERVED

Type

Reset

Description

7:5

4

R/W

0x0

C_CLK_FEEDBACK_GAI R/W

N

0x1

Adjustable feedback gain for CMLtoCMOS converter (high gain:1)

Reserved

3

2

Reserved

R/W

0x0

EN_VA11_NOISE_SUPPR R/W

When set, noise on VA11 is suppressed. It is recommended to have

this set, as it reduces noise coupling from the digital circuits to

analog clock, at the expense of a small increase in power.

1:0

CLKSAMP_DEL

R/W

0x1

Adjustable delay for the sampling clock (one hot encoded)

7.6.10 SYSREF_POS Register (Address = 0x2C) [reset = 0x0]

SYSREF_POS is shown in 图7-38 and described in 表7-78.

Return to the Summary Table.

SYSREF Capture Position (Read-Only, Default: undefined)

English Data Sheet: SLVSGH5

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图7-38. SYSREF_POS Register

23

22

14

6

21

13

5

20

12

4

19

11

3

18

10

2

17

9

16

8

SYSREF_POS

R/W-0x0

15

7

SYSREF_POS

R/W-0x0

1

0

SYSREF_POS

R/W-0x0

表7-78. SYSREF_POS Register Field Descriptions

Bit

Field

Type

Reset

Description

23:0

SYSREF_POS

R/W

0x0

Returns a 24-bit status value that indicates the position of the

SYSREF edge with respect to CLK±. Use this to program

SYSREF_SEL.

7.6.11 FS_RANGE_A Register (Address = 0x30) [reset = 0xA000]

FS_RANGE_A is shown in 图7-39 and described in 表7-79.

Return to the Summary Table.

FS_RANGE_A (default: 0xA000)

图7-39. FS_RANGE_A Register

15

7

14

6

13

5

12

11

10

2

9

1

8

0

FS_RANGE_A

R/W-0xA000

4

3

FS_RANGE_A

R/W-0xA000

表7-79. FS_RANGE_A Register Field Descriptions

Bit

15:0

Field

FS_RANGE_A

Type

Reset

Description

R/W

0xA000

These bits enable adjustment of the analog full-scale range for INA.

0x0000: Settings below 0x2000 result in degraded performance

0x2000: -5 dBm Recommended minimum setting

0xA000: -1 dBm (default)

0xFFFF: 1 dBm - Maximum setting

7.6.12 FS_RANGE_B Register (Address = 0x32) [reset = 0xA000]

FS_RANGE_B is shown in 图7-40 and described in 表7-80.

Return to the Summary Table.

FS_RANGE_B (default: 0xA000)

图7-40. FS_RANGE_B Register

15

14

13

12

11

10

9

8

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图7-40. FS_RANGE_B Register (continued)

FS_RANGE_B

R/W-0xA000

7

6

5

4

3

2

1

0

FS_RANGE_B

R/W-0xA000

表7-80. FS_RANGE_B Register Field Descriptions

Bit

15:0

Field

FS_RANGE_B

Type

Reset

Description

R/W

0xA000

These bits enable adjustment of the analog full-scale range for INB.

0x0000: Settings below 0x2000 result in degraded performance

0x2000: -5 dBm - Recommended minimum setting

0xA000: -1 dBm (default)

0xFFFF: 1 dBm - Maximum setting

7.6.13 BG_BYPASS Register (Address = 0x38) [reset = 0x00]

BG_BYPASS is shown in 图7-41 and described in 表7-81.

Return to the Summary Table.

Band-Gap Bypass (default: 0x00)

图7-41. BG_BYPASS Register

7

6

5

4

3

2

1

0

RESERVED

R/W-0x0

BG_BYPASS

R/W-0x0

表7-81. BG_BYPASS Register Field Descriptions

Bit

Field

Type

R/W

Reset

Description

7:1

0

RESERVED

BG_BYPASS

0x0

When set, VA11 is used as the voltage reference instead of the

band-gap voltage.

7.6.14 TMSTP_CTRL Register (Address = 0x3B) [reset = 0x00]

TMSTP_CTRL is shown in 图7-42 and described in 表7-82.

Return to the Summary Table.

TMSTP Control (default: 0x00)

图7-42. TMSTP_CTRL Register

7

6

5

4

3

2

1

0

RESERVED

R/W-0x0

TMSTP_LVPEC TMSTP_RECV

L_EN

_EN

R/W-0x0

表7-82. TMSTP_CTRL Register Field Descriptions

Bit

7:2

Field

RESERVED

Type

Reset

Description

R/W

0x0

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表7-82. TMSTP_CTRL Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

1

TMSTP_LVPECL_EN

R/W

0x0

When set, activates the low voltage PECL mode for the differential

TMSTP± input.

0

TMSTP_RECV_EN

R/W

0x0

Enables the differential TMSTP± input.

7.6.15 SER_PE Register (Address = 0x48) [reset = 0x00]

SER_PE is shown in 图7-43 and described in 表7-83.

Return to the Summary Table.

Serializer Pre-Emphasis Control (default: 0x00)

图7-43. SER_PE Register

7

6

5

4

3

2

1

0

RESERVED

R/W-0x0

SER_PE_BOO

ST

SER_PE

R/W-0x0

表7-83. SER_PE Register Field Descriptions

Bit

Field

Type

R/W

Reset

Description

7:4

3

RESERVED

0x0

SER_PE_BOOST

0x0

Additional pre-emphesis boost that increases the pre-emphesis

slightly and extends it in time.

2:0

SER_PE

R/W

0x0

Sets the pre-emphasis for the SerDes output lanes. Pre-emphasis

can be used to compensate for the high-frequency loss of the PCB

trace. This is a global setting that affects all 16 lanes (DA[7:0]±,

DB[7:0]±).

7.6.16 INPUT_MUX Register (Address = 0x60) [reset = 0x01]

INPUT_MUX is shown in 图7-44 and described in 表7-84.

Return to the Summary Table.

Input Mux Control (default: 0x01)

图7-44. INPUT_MUX Register

7

6

5

4

3

2

1

0

RESERVED

R/W-0x0

DUAL_INPUT

R/W-0x0

RESERVED

R/W-0x0

SINGLE_INPUT

R/W-0x1

表7-84. INPUT_MUX Register Field Descriptions

Bit

Field

Type

R/W

Reset

Description

7:5

4

RESERVED

0x0

DUAL_INPUT

0x0

Select inputs for dual channel modes. If JMODE is selecting a single

channel mode, this register has no effect.

0: A channel samples INA, B channel samples INB (no swap)

(default)

1: A channel samples INB, B channel samples INA (swap)

3:2

RESERVED

R/W

0x0

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表7-84. INPUT_MUX Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

1:0

SINGLE_INPUT

R/W

0x1

Defines which input is sampled in single channel mode. If JMODE is

not selecting a single channel mode, this register has no effect.

0: RESERVED

1: INA is used (default)

2: INB is used

3: ADC channel A samples INA and ADC channel B samples INB

(DUAL DES mode). A calibration needs to be performance after

switching the input mux for the changes to take effect.

7.6.17 CAL_EN Register (Address = 0x61) [reset = 0x01]

CAL_EN is shown in 图7-45 and described in 表7-85.

Return to the Summary Table.

Calibration Enable (Default: 0x01)

图7-45. CAL_EN Register

7

6

5

4

3

2

1

0

RESERVED

R/W-0x0

CAL_EN

R/W-0x1

表7-85. CAL_EN Register Field Descriptions

Bit

Field

Type

R/W

Reset

Description

7:1

0

RESERVED

CAL_EN

0x0

0x1

Calibration Enable. Set high to run calibration. Set low to hold

calibration in reset to program new calibration settings. Clearing

CAL_EN also resets the clock dividers that clock the digital block and

JESD204C interface.

Some calibration registers require clearing CAL_EN before making

any changes. All registers with this requirement contain a note in

their descriptions. After changing the registers, set CAL_EN to re-run

calibration with the new settings. Always set CAL_EN before setting

JESD_EN. Always clear JESD_EN before clearing CAL_EN.

7.6.18 CAL_CFG0 Register (Address = 0x62) [reset = 0x01]

CAL_CFG0 is shown in 图7-46 and described in 表7-86.

Return to the Summary Table.

Calibration Configuration 0 (Default: 0x01)

图7-46. CAL_CFG0 Register

7

6

5

4

3

2

1

0

RESERVED

R/W-0x0

CAL_BGOS

R/W-0x0

CAL_OS

R/W-0x0

CAL_BG

R/W-0x0

CAL_FG

R/W-0x1

表7-86. CAL_CFG0 Register Field Descriptions

Bit

7:4

Field

RESERVED

Type

Reset

Description

R/W

0x0

English Data Sheet: SLVSGH5

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表7-86. CAL_CFG0 Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

3

CAL_BGOS

R/W

0x0

0 : Disable background offset calibration (default)

1 : Enable background offset calibration (requires CAL_BG to be

set).

2

1

0

CAL_OS

CAL_BG

CAL_FG

R/W

0x0

0x1

0 : Disable foreground offset calibration (default)

1 : Enable foreground offset calibration (requires CAL_FG to be set).

0 : Disable background calibration (default)

1 : Enable background calibration

0 : Reset calibration values, skip foreground calibration.

1 : Reset calibration values, then run foreground calibration (default).

7.6.19 CAL_CFG2 Register (Address = 0x64) [reset = 0x02]

CAL_CFG2 is shown in 图7-47and described in 表7-87.

Return to the Summary Table.

Calibration Configuration 2 (Default: 0x02)

图7-47. CAL_CFG2 Register

7

6

5

4

3

2

1

0

RESERVED

R/W-0x00

ADC_OFF

R/W-0x10

表7-87. CAL_CFG2 Register Field Descriptions

Bit

Field

Type

R/W

Reset

0x00

0x1

Description

7:2

1:0

RESERVED

ADC_OFF

Reserved

If background calibration is disabled, this selects which ADC will be

disabled and never calibrated. Only change ADC_OFF while

JESD_EN is 0.

0 : ADC0 (ADC1 will stand in for ADC0)

1 : ADC1

2 : ADC2 (ADC1 will stand in for ADC2)

3 : Reserved

7.6.20 CAL_AVG Register (Address = 0x68) [reset = 0x61]

CAL_AVG is shown in 图7-48 and described in 表7-88.

Return to the Summary Table.

Calibration Averaging (default: 0x61)

图7-48. CAL_AVG Register

7

6

5

4

3

2

1

0

RESERVED

R/W-0x0

OS_AVG

R/W-0x6

RESERVED

R/W-0x0

CAL_AVG

R/W-0x1

表7-88. CAL_AVG Register Field Descriptions

Bit

Field

Type

Reset

Description

7

RESERVED

R/W

0x0

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表7-88. CAL_AVG Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

6:4

OS_AVG

R/W

0x6

Select the amount of averaging used for the offset correction routine.

A larger number corresponds to more averaging.

3

RESERVED

CAL_AVG

R/W

0x0

0x1

2:0

Select the amount of averaging used for the linearity calibration

routine. A larger number corresponds to more averaging.

7.6.21 CAL_STATUS Register (Address = 0x6A) [reset = 0x0]

CAL_STATUS is shown in 图7-49 and described in 表7-89.

Return to the Summary Table.

Calibration Status (default: undefined) (read-only)

图7-49. CAL_STATUS Register

7

6

5

4

3

2

1

0

RESERVED

CAL_STAT

R-0x0

CAL_STOPPE

D

FG_DONE

R-0x0

表7-89. CAL_STATUS Register Field Descriptions

Bit

Field

Type

Reset

Description

7:5

4:2

RESERVED

CAL_STAT

R

0x0

R

0x0

Calibration status code

1

CAL_STOPPED

R

0x0

This bit returns a 1 when background calibration is successfully

stopped at the requested phase. This bit returns a 0 when calibration

starts operating again. If background calibration is disabled, this bit is

set when foreground calibration is completed or skipped.

0

FG_DONE

This bit is high to indicate that foreground calibration has completed

(or was skipped).

7.6.22 CAL_PIN_CFG Register (Address = 0x6B) [reset = 0x00]

CAL_PIN_CFG is shown in 图7-50 and described in 表7-90.

Return to the Summary Table.

Calibration Pin Configuration (default: 0x00)

图7-50. CAL_PIN_CFG Register

7

6

5

4

3

2

1

0

RESERVED

R/W-0x0

CAL_STATUS_SEL

R/W-0x0

CAL_TRIG_EN

R/W-0x0

表7-90. CAL_PIN_CFG Register Field Descriptions

Bit

7:3

Field

RESERVED

Type

Reset

Description

R/W

0x0

English Data Sheet: SLVSGH5

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表7-90. CAL_PIN_CFG Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

2:1

CAL_STATUS_SEL

R/W

0x0

0 : CALSTAT output matches FG_DONE.

1 : CALSTAT output matches CAL_STOPPED.

2 : CALSTAT output matches ALARM.

3 : CALSTAT output is always low.

0

CAL_TRIG_EN

R/W

0x0

This bit selects the hardware or software trigger source.

0 : Use the CAL_SOFT_TRIG register for the calibration trigger. The

CALTRIG input is disabled (ignored).

1 : Use the CALTRIG input for the calibration trigger. The

CAL_SOFT_TRIG register is ignored.

7.6.23 CAL_SOFT_TRIG Register (Address = 0x6C) [reset = 0x01]

CAL_SOFT_TRIG is shown in 图7-51 and described in 表7-91.

Return to the Summary Table.

Calibration Software Trigger (default: 0x01)

图7-51. CAL_SOFT_TRIG Register

7

6

5

4

3

2

1

0

RESERVED

CAL_SOFT_TR

IG

R/W-0x0

R/W-0x1

表7-91. CAL_SOFT_TRIG Register Field Descriptions

Bit

Field

Type

R/W

Reset

Description

7:1

0

RESERVED

0x0

CAL_SOFT_TRIG

0x1

CAL_SOFT_TRIG is a software bit to provide the functionality of the

CALTRIG input pin when there are no hardware resources to drive

CALTRIG. Program CAL_TRIG_EN=0 to use CAL_SOFT_TRIG for

the calibration trigger.

Note: If no calibration trigger is needed, leave CAL_TRIG_EN=0 and

CAL_SOFT_TRIG=1 (trigger set high).

7.6.24 CAL_LP Register (Address = 0x6E) [reset = 0x88]

CAL_LP is shown in 图7-52 and described in 表7-92.

Return to the Summary Table.

Low-Power Background Calibration (default: 0x88)

图7-52. CAL_LP Register

7

6

5

4

3

2

1

0

LP_SLEEP_DLY

R/W-0x4

LP_WAKE_DLY

R/W-0x1

RESERVED

R/W-0x0

LP_TRIG

R/W-0x0

LP_EN

R/W-0x0

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表7-92. CAL_LP Register Field Descriptions

Bit

Field

Type

Reset

Description

7:5

LP_SLEEP_DLY

R/W

0x4

These bits adjust how long an ADC sleeps before waking for

calibration (only applies when LP_EN = 1 and LP_TRIG = 0). Values

below 4 are not recommended because of limited overall power

reduction benefits.

0: Sleep delay = (23 + 1) × 256 × tCLK

1: Sleep delay = (215 + 1) × 256 × tCLK

2: Sleep delay = (218 + 1) × 256 × tCLK

3: Sleep delay = (221 + 1) × 256 × tCLK

4: Sleep delay = (224 + 1) × 256 × tCLK (default, approximately

1.338 seconds with a 3.2-GHz clock)

5: Sleep delay = (227 + 1) × 256 × tCLK

6: Sleep delay = (230 + 1) × 256 × tCLK

7: Sleep delay = (233 + 1) × 256 × tCLK

4:3

LP_WAKE_DLY

R/W

0x1

These bits adjust how much time is provided for settling before

calibrating an ADC after the ADC wakes up (only applies when

LP_EN = 1). Values lower than 1 are not recommended because

there is insufficient time for the core to stabilize before calibration

begins.

0: Wake delay = (23 + 1) × 256 × tCLK

1: Wake delay = (218 + 1) × 256 × tCLK (default, approximately 21

ms with a 3.2-GHz clock)

2: Wake delay = (221 + 1) × 256 × tCLK

3: Wake delay = (224 + 1) × 256 × tCLK

2

1

RESERVED

LP_TRIG

R/W

0x0

0 : ADC sleep duration is set by LP_SLEEP_DLY (autonomous

mode).

1 : ADCs sleep until awoken by a trigger. An ADC is awoken when

the calibration trigger is low.

0

LP_EN

R/W

0x0

0 : Disable low-power background calibration (default)

1 : Enable low-power background calibration (only applies when

CAL_BG=1).

7.6.25 CAL_DATA_EN Register (Address = 0x70) [reset = 0x00]

CAL_DATA_EN is shown in 图7-53 and described in 表7-93.

Return to the Summary Table.

Calibration Data Enable (default: 0x00)

图7-53. CAL_DATA_EN Register

7

6

5

4

3

2

1

0

RESERVED

R/W-0x0

CAL_DATA_EN

R/W-0x0

表7-93. CAL_DATA_EN Register Field Descriptions

Bit

7:1

Field

RESERVED

Type

Reset

Description

R/W

0x0

English Data Sheet: SLVSGH5

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表7-93. CAL_DATA_EN Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

0

CAL_DATA_EN

R/W

0x0

Set this bit to enable the CAL_DATA register to enable reading and

writing of calibration data; see the CAL_DATA register for more

information.

7.6.26 CAL_DATA Register (Address = 0x71) [reset = 0x0]

CAL_DATA is shown in 图7-54 and described in 表7-94.

Return to the Summary Table.

Calibration Data (default: undefined)

图7-54. CAL_DATA Register

7

6

5

4

3

2

1

0

CAL_DATA

R/W-0x0

表7-94. CAL_DATA Register Field Descriptions

Bit

7:0

Field

CAL_DATA

Type

Reset

Description

R/W

0x0

After setting CAL_DATA_EN, repeated reads of this register return all

calibration values for the ADCs. Repeated writes of this register input

all calibration values for the ADCs. To read the calibration data, read

the register 673 times. To write the vector, write the register 673

times with previously stored calibration data. To speed up the read or

write operation, set ADDR_HOLD = 1 and use streaming read or

write process.

IMPORTANT: Accessing the CAL_DATA register when

CAL_STOPPED = 0 corrupts the calibration. Also, stopping the

process before reading or writing 673 times leaves the calibration

data in an invalid state.

7.6.27 GAIN_TRIM_A Register (Address = 0x7A) [reset = 0x0]

GAIN_TRIM_A is shown in 图7-55 and described in 表7-95.

Return to the Summary Table.

Gain DAC Trim A (default from Fuse ROM)

图7-55. GAIN_TRIM_A Register

7

6

5

4

3

2

1

0

GAIN_TRIM_A

R/W-0x0

表7-95. GAIN_TRIM_A Register Field Descriptions

Bit

7:0

Field

GAIN_TRIM_A

Type

Reset

Description

R/W

0x0

This register enables gain trim of INA. After reset, the factory

trimmed value can be read and adjusted as required. Use

FS_RANGE_A to adjust the analog full-scale voltage (Vfs) of INA.

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7.6.28 GAIN_TRIM_B Register (Address = 0x7B) [reset = 0x0]

GAIN_TRIM_B is shown in 图7-56 and described in 表7-96.

Return to the Summary Table.

Gain DAC Trim B (default from Fuse ROM)

图7-56. GAIN_TRIM_B Register

7

6

5

4

3

2

1

0

GAIN_TRIM_B

R/W-0x0

表7-96. GAIN_TRIM_B Register Field Descriptions

Bit

7:0

Field

GAIN_TRIM_B

Type

Reset

Description

R/W

0x0

This register enables gain trim of INB. After reset, the factory

trimmed value can be read and adjusted as required. Use

FS_RANGE_B to adjust the analog full-scale voltage (Vfs) of INB.

7.6.29 BG_TRIM Register (Address = 0x7C) [reset = 0x0]

BG_TRIM is shown in 图7-57 and described in 表7-97.

Return to the Summary Table.

Band-Gap Trim (default from Fuse ROM)

图7-57. BG_TRIM Register

7

6

5

4

3

2

1

0

RESERVED

R/W-0x0

BG_TRIM

R/W-0x0

表7-97. BG_TRIM Register Field Descriptions

Bit

Field

Type

R/W

Reset

Description

7:4

3:0

RESERVED

BG_TRIM

0x0

This register enables trimming of the internal band-gap reference.

After reset, the factory trimmed value can be read and adjusted as

required.

7.6.30 RTRIM_A Register (Address = 0x7E) [reset = 0x0]

RTRIM_A is shown in 图7-58 and described in 表7-98.

Return to the Summary Table.

Resistor Trim for VinA (default from Fuse ROM)

图7-58. RTRIM_A Register

7

6

5

4

3

2

1

0

RTRIM_A

R/W-0x0

English Data Sheet: SLVSGH5

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表7-98. RTRIM_A Register Field Descriptions

Bit

Field

RTRIM_A

Type

Reset

Description

7:0

R/W

0x0

This register controls the INA ADC input termination trim. After reset,

the factory trimmed value can be read and adjusted as required.

7.6.31 RTRIM_B Register (Address = 0x7F) [reset = 0x0]

RTRIM_B is shown in 图7-59 and described in 表7-99.

Return to the Summary Table.

Resistor Trim for VinB (default from Fuse ROM)

图7-59. RTRIM_B Register

7

6

5

4

3

2

1

0

RTRIM_B

R/W-0x0

表7-99. RTRIM_B Register Field Descriptions

Bit

7:0

Field

Type

Reset

Description

RTRIM_B

R/W

0x0

This register controls the INB ADC input termination trim. After reset,

the factory trimmed value can be read and adjusted as required.

7.6.32 ADC_DITH Register (Address = 0x9D) [reset = 0x01]

ADC_DITH is shown in 图7-60 and described in 表7-100.

Return to the Summary Table.

ADC Dither Control (default from Fuse ROM)

图7-60. ADC_DITH Register

7

6

5

4

3

2

1

0

RESERVED

ADC_DITH_ER ADC_DITH_AM ADC_DITH_EN

R

P

R/W-0x0

R/W-0x1

表7-100. ADC_DITH Register Field Descriptions

Bit

Field

Type

R/W

Reset

Description

7:3

2

RESERVED

0x0

ADC_DITH_ERR

0x0

Small rounding errors may occur when subtracting the dither signal.

The error can be chosen to either slightly degrade SNR or to slightly

increase the DC offset and FS/2 spur. In addition, the FS/4 spur will

also be increased slightly while in single channel mode.

0 : Rounding error degrades SNR

1 : Rounding error degrades DC offset, FS/2 spur and FS/4 spur

1

0

ADC_DITH_AMP

ADC_DITH_EN

R/W

0x0

0x1

0 : Small dither for better SNR (default)

1 : Large dither for better spurious performance

Set this bit to enable ADC dither. Dither can improve spurious

performance at the expense of slightly degraded SNR. The dither

amplitude (ADC_DITH_AMP) can be used to further tradeoff SNR

and spurious performance.

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7.6.33 B0_TIME_0 Register (Address = 0x102) [reset = 0x0]

B0_TIME_0 is shown in 图7-61 and described in 表7-101.

Return to the Summary Table.

Time Adjustment for Bank 0 (0° clock) (default from Fuse ROM)

图7-61. B0_TIME_0 Register

7

6

5

4

3

2

1

0

B0_TIME_0

R/W-0x0

表7-101. B0_TIME_0 Register Field Descriptions

Bit

7:0

Field

B0_TIME_0

Type

Reset

Description

R/W

0x0

Time adjustment for bank 0 applied when ADC A is configured for 0°

clock phase (dual channel mode). After reset, the factory trimmed

value can be read and adjusted as required.

7.6.34 B0_TIME_90 Register (Address = 0x103) [reset = 0x0]

B0_TIME_90 is shown in 图7-62 and described in 表7-102.

Return to the Summary Table.

Time Adjustment for Bank 0 (-90° clock) (default from Fuse ROM)

图7-62. B0_TIME_90 Register

7

6

5

4

3

2

1

0

B0_TIME_90

R/W-0x0

表7-102. B0_TIME_90 Register Field Descriptions

Bit

7:0

Field

B0_TIME_90

Type

Reset

Description

R/W

0x0

Time adjustment for bank 0 applied when ADC A is configured for

-90° clock phase(single channel mode). After reset, the factory

trimmed value can be read and adjusted as required.

7.6.35 B1_TIME_0 Register (Address = 0x112) [reset = 0x0]

B1_TIME_0 is shown in 图7-63 and described in 表7-103.

Return to the Summary Table.

Time Adjustment for Bank 1 (0° clock) (default from Fuse ROM)

图7-63. B1_TIME_0 Register

7

6

5

4

3

2

1

0

B1_TIME_0

R/W-0x0

English Data Sheet: SLVSGH5

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表7-103. B1_TIME_0 Register Field Descriptions

Bit

Field

B1_TIME_0

Type

Reset

Description

7:0

R/W

0x0

Time adjustment for bank 1 applied when ADC A is configured for 0°

clock phase (dual channel mode). After reset, the factory trimmed

value can be read and adjusted as required.

7.6.36 B1_TIME_90 Register (Address = 0x113) [reset = 0x0]

B1_TIME_90 is shown in 图7-64 and described in 表7-104.

Return to the Summary Table.

Time Adjustment for Bank 1 (-90° clock) (default from Fuse ROM)

图7-64. B1_TIME_90 Register

7

6

5

4

3

2

1

0

B1_TIME_90

R/W-0x0

表7-104. B1_TIME_90 Register Field Descriptions

Bit

7:0

Field

B1_TIME_90

Type

Reset

Description

R/W

0x0

Time adjustment for bank 1 applied when ADC A is configured for

-90° clock phase(single channel mode). After reset, the factory

trimmed value can be read and adjusted as required.

7.6.37 B4_TIME_0 Register (Address = 0x142) [reset = 0x0]

B4_TIME_0 is shown in 图7-65 and described in 表7-105.

Return to the Summary Table.

Time Adjustment for Bank 4 (0° clock) (default from Fuse ROM)

图7-65. B4_TIME_0 Register

7

6

5

4

3

2

1

0

B4_TIME_0

R/W-0x0

表7-105. B4_TIME_0 Register Field Descriptions

Bit

7:0

Field

B4_TIME_0

Type

Reset

Description

R/W

0x0

Time adjustment for bank 4 applied when ADC B is configured for 0°

clock phase (dual channel mode and single channel mode). After

reset, the factory trimmed value can be read and adjusted as

required.

7.6.38 B5_TIME_0 Register (Address = 0x152) [reset = 0x0]

B5_TIME_0 is shown in 图7-66 and described in 表7-106.

Return to the Summary Table.

Time Adjustment for Bank 5 (0° clock) (default from Fuse ROM)

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图7-66. B5_TIME_0 Register

7

6

5

4

3

2

1

0

B5_TIME_0

R/W-0x0

表7-106. B5_TIME_0 Register Field Descriptions

Bit

7:0

Field

B5_TIME_0

Type

Reset

Description

R/W

0x0

Time adjustment for bank 5 applied when ADC B is configured for 0°

clock phase (dual channel mode and single channel mode). After

reset, the factory trimmed value can be read and adjusted as

required.

7.6.39 LSB_CTRL Register (Address = 0x160) [reset = 0x00]

LSB_CTRL is shown in 图7-67 and described in 表7-107.

Return to the Summary Table.

LSB Control Bit Output (default: 0x00)

图7-67. LSB_CTRL Register

7

6

5

4

3

2

1

0

RESERVED

TIME_STAMP_

EN

R/W-0x0

表7-107. LSB_CTRL Register Field Descriptions

Bit

Field

Type

R/W

Reset

Description

7:1

0

RESERVED

0x0

TIME_STAMP_EN

0x0

When set, the timestamp signal is transmitted on the LSB of the

output samples. The latency of the timestamp signal (through the

entire chip) matches the latency of the analog ADC inputs. Also set

SYNC_RECV_EN when using TIME_STAMP_EN.

Note 1: In 8-bit modes, the control bit is placed on the LSB of the 8-

bit samples (leaving 7-bits of sample data). If the part is configured

for 12-bit data, the control bit is placed on the LSB of the 12-bit bit

data (leaving 11-bits of sample data).

Note 2: The control bit that is enabled by this register is never

advertised in the ILA (CS is 0 in the ILA).

7.6.40 JESD_EN Register (Address = 0x200) [reset = 0x01]

JESD_EN is shown in 图7-68 and described in 表7-108.

Return to the Summary Table.

JESD204C Subsystem Enable (default: 0x01)

图7-68. JESD_EN Register

7

6

5

4

3

2

1

0

RESERVED

R/W-0x0

JESD_EN

R/W-0x1

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表7-108. JESD_EN Register Field Descriptions

Bit

7:1

0

Field

Type

R/W

Reset

Description

RESERVED

JESD_EN

0x0

0x1

0 : Disable JESD204C interface

1 : Enable JESD204C interface

Note: Before altering other JESD204C registers, you must clear

JESD_EN. When JESD_EN is 0, the block is held in reset and the

serializers are powered down. The clocks are gated off to save

power. The LMFC/LEMC counter is also held in reset, so SYSREF

will not align the LMFC/LEMC.

Note 2: Always set CAL_EN before setting JESD_EN.

Note 3: Always clear JESD_EN before clearing CAL_EN.

7.6.41 JMODE Register (Address = 0x201) [reset = 0x02]

JMODE is shown in 图7-69 and described in 表7-109.

Return to the Summary Table.

JESD204C Mode (default: 0x02)

图7-69. JMODE Register

7

6

5

4

3

2

1

0

表7-109. JMODE Register Field Descriptions

Bit

Field

Type

Reset

Description

7.6.42 KM1 Register (Address = 0x202) [reset = 0x1F]

KM1 is shown in 图7-70 and described in 表7-110.

Return to the Summary Table.

JESD204C K Parameter (default: 0x1F)

图7-70. KM1 Register

7

6

5

4

3

2

1

0

KM1

R/W-0x1F

表7-110. KM1 Register Field Descriptions

Bit

7:0

Field

Type

Reset

Description

KM1

R/W

0x1F

K is the number of frames per multiframe and this register must be

programmed as K-1. Depending on the JMODE setting, there are

constraints on the legal values of K (see KR).

The default values is KM1=31, which corresponds to K=32.

Note: For modes using the 64b/66b link layer, the KM1 register is

ignored and the value of K is determined from JMODE. The effective

value of K is 256*E/F.

Note: This register should only be changed when JESD_EN is 0.

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7.6.43 JSYNC_N Register (Address = 0x203) [reset = 0x01]

JSYNC_N is shown in 图7-71 and described in 表7-111.

Return to the Summary Table.

JESD204C Manual Sync Request (default: 0x01)

图7-71. JSYNC_N Register

7

6

5

4

3

2

1

0

RESERVED

R/W-0x0

JSYNC_N

R/W-0x1

表7-111. JSYNC_N Register Field Descriptions

Bit

Field

Type

R/W

Reset

Description

7:1

0

RESERVED

JSYNC_N

0x0

0x1

Set this bit to 0 to request JESD204C synchronization (equivalent to

the SYNC~ signal being asserted). For normal operation, leave this

bit set to 1.

Note: The JSYNC_N register can always generate a synchronization

request, regardless of the SYNC_SEL register. However, if the

selected sync pin is stuck low, you cannot de-assert the

synchronization request unless you program SYNC_SEL=2.

7.6.44 JCTRL Register (Address = 0x204) [reset = 0x03]

JCTRL is shown in 图7-72 and described in 表7-112.

Return to the Summary Table.

JESD204C Control (default: 0x03)

图7-72. JCTRL Register

7

6

5

4

3

2

1

0

RESERVED

R/W-0x0

ALT_LANES

R/W-0x0

SYNC_SEL

R/W-0x0

SFORMAT

R/W-0x1

SCR

R/W-0x1

表7-112. JCTRL Register Field Descriptions

Bit

Field

Type

R/W

Reset

Description

7:5

4

RESERVED

ALT_LANES

0x0

0 : Normal lane mapping (default). Link A uses lanes DA0 to DA3

and link B uses lanes DB0 to DB3. Other lanes are powered down.

1 : Alternate lane mapping (use upper lanes). Link A uses lanes DA4

to DA7 and link B uses lanes DB4 to DB7. Lanes DA0 to DA3 and

DB0 to DB3 are powered down.

Note: This option is only supported when JMODE selects a mode

that uses 8 or less lanes. The behavior is undefined for modes that

do not meet this requirement.

3:2

SYNC_SEL

R/W

0x0

0 : Use the SYNCSE input for SYNC~ function (default)

1 : Use the TMSTP input for SYNC~ function. TMSTP_RECV_EN

must also be set.

2 : Do not use any sync input pin (use software SYNC~ through

JSYNC_N)

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表7-112. JCTRL Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

1

SFORMAT

R/W

0x1

Output sample format for JESD204C samples

0 : Offset binary

1 : Signed 2’s complement (default)

0

SCR

R/W

0x1

0 : 8B/10B Scrambler disabled (applies only to 8B/10B modes)

1 : 8b/10b Scrambler enabled (default)

Note 1: 64B/66B modes always use scrambling. This register does

not apply to 64B/66B modes.

Note 2: This register should only be changed when JESD_EN is 0.

7.6.45 JTEST Register (Address = 0x205) [reset = 0x00]

JTEST is shown in 图7-73 and described in 表7-113.

Return to the Summary Table.

JESD204C Test Control (default: 0x00)

图7-73. JTEST Register

7

6

5

4

3

2

1

0

RESERVED

R/W-0x0

JTEST

R/W-0x0

表7-113. JTEST Register Field Descriptions

Bit

Field

Type

R/W

Reset

Description

7:5

4:0

RESERVED

JTEST

0x0

0 : Test mode disabled. Normal operation (default)

1 : PRBS7 test mode

2 : PRBS15 test mode

3 : PRBS23 test mode

4 : Ramp test mode

5 : Transport Layer test mode

6 : D21.5 test mode

7 : K28.5 test mode*

8 : Repeated ILA test mode*

9 : Modified RPAT test mode*

10: Serial outputs held low

11: Serial outputs held high

12: RESERVED

13: PRBS9 test mode

14: PRBS31 test mode

15: Clock test pattern (0x00FF)

16: K28.7 test mode*

17-31: RESERVED

* These test modes are only supported when JMODE is selecting a

mode that utilizes 8b/10b encoding.

Note: This register should only be changed when JESD_EN is 0.

7.6.46 DID Register (Address = 0x206) [reset = 0x00]

DID is shown in 图7-74 and described in 表7-114.

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Return to the Summary Table.

JESD204C DID Parameter (default: 0x00)

图7-74. DID Register

7

6

5

4

3

2

1

0

DID

R/W-0x0

表7-114. DID Register Field Descriptions

Bit

7:0

Field

Type

Reset

Description

DID

R/W

0x0

Specifies the DID (Device ID) value that is transmitted during the

second multiframe of the JESD204B ILA. Link A will transmit DID,

and link B will transmit DID+1. Bit 0 is ignored and always returns 0

(if you program an odd number, it will be decremented to an even

number).

Note: This register should only be changed when JESD_EN is 0.

7.6.47 FCHAR Register (Address = 0x207) [reset = 0x00]

FCHAR is shown in 图7-75 and described in 表7-115.

Return to the Summary Table.

JESD204C Frame Character (default: 0x00)

图7-75. FCHAR Register

7

6

5

4

3

2

1

0

RESERVED

R/W-0x0

FCHAR

R/W-0x0

表7-115. FCHAR Register Field Descriptions

Bit

Field

Type

R/W

Reset

Description

7:2

1:0

RESERVED

FCHAR

0x0

Specify which comma character is used to denote end-of-frame. This

character is transmitted opportunistically. This only applies to modes

that utilize 8B/10B encoding.

0 : Use K28.7 (default) (JESD204C compliant)

1 : Use K28.1 (not JESD204C compliant)

2 : Use K28.5 (not JESD204C compliant)

3 : Reserved

When using a JESD204C receiver, always use FCHAR=0.

When using a general purpose 8B/10B receiver, the K28.7 character

may cause issues. When K28.7 is combined with certain data

characters, a false, misaligned comma character can result, and

some receivers will re-align to the false comma. To avoid this,

program FCHAR to 1 or 2.

Note: This register should only be changed when JESD_EN is 0.

7.6.48 JESD_STATUS Register (Address = 0x208) [reset = 0x0]

JESD_STATUS is shown in 图7-76 and described in 表7-116.

Return to the Summary Table.

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JESD204C / System Status Register

图7-76. JESD_STATUS Register

7

6

5

4

3

2

1

0

RESERVED

R/W-0x0

LINK_UP

R/W-0x0

SYNC_STATUS REALIGNED

R/W-0x0 R/W-0x0

ALIGNED

R/W-0x0

PLL_LOCKED

R/W-0x0

RESERVED

R/W-0x0

表7-116. JESD_STATUS Register Field Descriptions

Bit

7

Field

RESERVED

Type

R/W

Reset

Description

0x0

6

LINK_UP

0x0

When set, indicates that the JESD204C link is up.

5

4

3

SYNC_STATUS

R/W

0x0

Returns the state of the JESD204C SYNC~ signal.

0 : SYNC~ asserted

1 : SYNC~ de-asserted

REALIGNED

ALIGNED

When high, indicates that the digital block clock, frame clock, or

multiframe (LMFC) clock phase was realigned by SYSREF. Writing a

1 to this bit will clear it.

When high, indicates that the multiframe (LMFC) clock phase has

been established by SYSREF. The first SYSREF event after enabling

the JESD204B encoder will set this bit. Writing a 1 to this bit will clear

it.

2

PLL_LOCKED

RESERVED

R/W

0x0

When high, indicates that the serializer PLL is locked.

1:0

7.6.49 PD_CH Register (Address = 0x209) [reset = 0x00]

PD_CH is shown in 图7-77 and described in 表7-117.

Return to the Summary Table.

JESD204C Channel Power Down (default: 0x00)

图7-77. PD_CH Register

7

6

5

4

3

2

1

0

RESERVED

R/W-0x0

PD_BCH

R/W-0x0

PD_ACH

R/W-0x0

表7-117. PD_CH Register Field Descriptions

Bit

7:2

Field

RESERVED

Type

Reset

Description

R/W

0x0

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表7-117. PD_CH Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

1

PD_BCH

R/W

0x0

When set, the “B”ADC channel is powered down. The digital

channels that are bound to the “B”ADC channel are also powered

down (see DIG_BIND).

Important notes:

1. You must set JESD_EN=0 before changing PD_CH.

2. To power down both ADC channels, use the MODE register.

3. If both channels are powered down, then the entire JESD204C

subsystem is powered down, including serializer PLL and LMFC.

4. If the selected JESD204C mode transmits A and B data on link A,

and the B digital channel is disabled, link A remains operational, but

the B-channel samples are undefined. For proper operation in

foreground calibration mode, ADC_OFF in the CAL_CFG register

should be programmed to 0x1.

0

PD_ACH

R/W

0x0

When set, the “A”ADC channel is powered down. The digital

channels that are bound to the “A”ADC channel are also powered

down (see DIG_BIND).

Important notes:

1. You must set JESD_EN=0 before changing PD_CH.

2. To power down both ADC channels, use the MODE register.

3. If both channels are powered down, then the entire JESD204C

subsystem is powered down, including serializer PLL and LMFC.

4. If the selected JESD204C mode transmits A and B data on link A,

and the B digital channel is disabled, link A remains operational, but

the B-channel samples are undefined. For proper operation in

foreground calibration mode, ADC_OFF in the CAL_CFG register

should be programmed to 0x1.

7.6.50 JEXTRA_A Register (Address = 0x20A) [reset = 0x00]

JEXTRA_A is shown in 图7-78 and described in 表7-118.

Return to the Summary Table.

JESD204C Extra Lane Enable (Link A) (default: 0x00)

图7-78. JEXTRA_A Register

7

6

5

4

3

2

1

0

EXTRA_LANE_A

R/W-0x0

EXTRA_SER_A

R/W-0x0

表7-118. JEXTRA_A Register Field Descriptions

Bit

7:1

Field

EXTRA_LANE_A

Type

Reset

Description

R/W

0x0

Program these register bits to enable extra lanes (even if the

selected JMODE does not require the lanes to be enabled).

EXTRA_LANE_A(n) enables An (n=1 to 7). This register enables the

link layer clocks for the affected lanes. To also enable the extra

serializes set EXTRA_SER_A=1.

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表7-118. JEXTRA_A Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

0

EXTRA_SER_A

R/W

0x0

0 : Only the link layer clocks for extra lanes are enabled.

1 : Serializers for extra lanes are enabled (as well as link layer

clocks). Use this mode to transmit data from the extra lanes.

Important Notes:

1. This register should only be changed when JESD_EN is 0.

2. The bit-rate and mode of the extra lanes are set by JMODE and

JTEST (see exception below).

3. If a lane is enabled by this register (and was not enabled by

JMODE), and JTEST is 0 or 5, the extra lanes will use an octet ramp

(same as JTEST=4).

4. This register does not override the PD_CH register, so the link is

enabled to use this feature.

5. To enable serializer 'n', the lower number lanes 0 to n-1 must also

be enabled, otherwise, serializer 'n' will not receive a clock.

7.6.51 JEXTRA_B Register (Address = 0x20B) [reset = 0x00]

JEXTRA_B is shown in 图7-79 and described in 表7-119.

Return to the Summary Table.

JESD204C Extra Lane Enable (Link B) (default: 0x00)

图7-79. JEXTRA_B Register

7

6

5

4

3

2

1

0

EXTRA_LANE_B

R/W-0x0

EXTRA_SER_B

R/W-0x0

表7-119. JEXTRA_B Register Field Descriptions

Bit

7:1

Field

Type

Reset

Description

EXTRA_LANE_B

R/W

0x0

Program these register bits to enable extra lanes (even if the

selected JMODE does not require the lanes to be enabled).

EXTRA_LANE_B(n) enables Bn (n=1 to 7). This register enables the

link layer clocks for the affected lanes. To also enable the extra

serializes set EXTRA_SER_B=1.

0

EXTRA_SER_B

R/W

0x0

0 : Only the link layer clocks for extra lanes are enabled.

1 : Serializers for extra lanes are enabled (as well as link layer

clocks). Use this mode to transmit data from the extra lanes.

Important Notes:

1. This register should only be changed when JESD_EN is 0.

2. The bit-rate and mode of the extra lanes are set by JMODE and

JTEST (see exception below).

3. If a lane is enabled by this register (and was not enabled by

JMODE), and JTEST is 0 or 5, the extra lanes will use an octet ramp

(same as JTEST=4).

4. This register does not override the PD_CH register, so the link is

enabled to use this feature.

5. To enable serializer 'n', the lower number lanes 0 to n-1 must also

be enabled, otherwise, serializer 'n' will not receive a clock.

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7.6.52 SHMODE Register (Address = 0x20F) [reset = 0x00]

SHMODE is shown in 图7-80 and described in 表7-120.

Return to the Summary Table.

JESD204C Sync Word Mode (default: 0x00)

图7-80. SHMODE Register

7

6

5

4

3

2

1

0

RESERVED

R/W-0x0

SHMODE

R/W-0x0

表7-120. SHMODE Register Field Descriptions

Bit

Field

Type

R/W

Reset

Description

7:2

1:0

RESERVED

SHMODE

0x0

Select the mode for the 64b/66b sync word (32 bits of data per multi-

block). This only applies when JMODE is selecting a 64b/66b mode.

0 : Transmit CRC-12 signal (default setting)

1 : RESERVED

2 : Transmit FEC signal

3 : RESERVED

Note: This device does not support any JESD204C command

features. All command fields will be set to zero (idle headers).

Note: This register should only be changed when JESD_EN is 0.

7.6.53 DDC_CFG Register (Address = 0x210) [reset = 0x00]

DDC_CFG is shown in 图7-81 and described in 表7-121.

Return to the Summary Table.

DDC Configuration (default: 0x00)

图7-81. DDC_CFG Register

7

6

5

4

3

2

1

0

RESERVED

R/W-0x0

BOOST

R/W-0x0

表7-121. DDC_CFG Register Field Descriptions

Bit

Field

Type

R/W

Reset

Description

7:1

0

RESERVED

BOOST

0x0

DDC gain control.

0 : DDC filter has 0dB gain (default).

1 : DDC filter has 6.02dB gain. Only use this setting when you are

certain the negative image of your input signal is filtered out by the

DDC, otherwise clipping may occur.

7.6.54 OVR_T0 Register (Address = 0x211) [reset = 0xF2]

OVR_T0 is shown in 图7-82 and described in 表7-122.

Return to the Summary Table.

Over-range Threshold 0 (default: 0xF2)

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图7-82. OVR_T0 Register

7

6

5

4

3

2

1

0

OVR_T0

R/W-0xF2

表7-122. OVR_T0 Register Field Descriptions

Bit

Field

OVR_T0

Type

Reset

Description

7:0

R/W

0xF2

This parameter defines the absolute sample level that causes control

bit 0 to be set. Control bit 0 is attached to the DDC I output samples.

The detection level in dBFS (peak) is 20log10(OVR_T0/256)

(Default: 0xF2 = 242-> -0.5dBFS)

7.6.55 OVR_T1 Register (Address = 0x212) [reset = 0xAB]

OVR_T1 is shown in 图7-83 and described in 表7-123.

Return to the Summary Table.

Over-range Threshold 1 (default: 0xAB)

图7-83. OVR_T1 Register

7

6

5

4

3

2

1

0

OVR_T1

R/W-0xAB

表7-123. OVR_T1 Register Field Descriptions

Bit

7:0

Field

Type

Reset

Description

OVR_T1

R/W

0xAB

This parameter defines the absolute sample level that causes control

bit 1 to be set. Control bit 1 is attached to the DDC Q output

samples. The detection level in dBFS (peak) is

20log10(OVR_T1/256) (Default: 0xAB = 171 -> -3.5dBFS)

7.6.56 OVR_CFG Register (Address = 0x213) [reset = 0x07]

OVR_CFG is shown in 图7-84 and described in 表7-124.

Return to the Summary Table.

Over-range Enable / Hold Off (default: 0x07)

图7-84. OVR_CFG Register

7

6

5

4

3

2

1

0

RESERVED

R/W-0x0

OVR_EN

R/W-0x0

OVR_N

R/W-0x7

表7-124. OVR_CFG Register Field Descriptions

Bit

7:4

Field

RESERVED

Type

Reset

Description

R/W

0x0

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表7-124. OVR_CFG Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

3

OVR_EN

R/W

0x0

Enables over-range status output pins when set high. The ORA0,

ORA1, ORB0 and ORB1 outputs are held low when OVR_EN is set

low. This register only affects the over-range output pins (ORxx).

JESD204C modes that transmit over-range bits are not affected by

this register.

2:0

OVR_N

R/W

0x7

Program this register to adjust the pulse extension for the ORA0/1

and ORB0/1 outputs. The minimum pulse duration of the over-range

outputs is 8 * 2^OVR_NDEVCLK cycles. Incrementing this field doubles

the monitoring period.

7.6.57 CMODE Register (Address = 0x214) [reset = 0x00]

CMODE is shown in 图7-85 and described in 表7-125.

Return to the Summary Table.

DDC NCO Configuration Preset Mode (default: 0x00)

图7-85. CMODE Register

7

6

5

4

3

2

1

0

RESERVED

R/W-0x0

CMODE

R/W-0x0

表7-125. CMODE Register Field Descriptions

Bit

Field

Type

R/W

Reset

Description

7:2

1:0

RESERVED

CMODE

0x0

This register sets the selection mode for the NCO frequency used in

the DDC block. The NCO frequency and phase for DDC A are set by

the FREQAx and PHASEAx registers and the NCO frequency and

phase for DDC B are set by the FREQBx and PHASEBx registers,

where x is the configuration preset (0 through 3). In single channel

mode, the NCO selection method for DDC A in dual channel mode is

used to set the NCO for the single channel DDC.

0: Use CSEL register to select the active NCO configuration preset

for DDC A and DDC B

1: Use NCOA[1:0] pins to select the active NCO configuration preset

for DDC A and use NCOB[1:0] pins to select the active NCO

configuration preset for DDC B

2: Use NCOA[1:0] pins to select the active NCO configuration preset

for both DDC A and DDC B

3: RESERVED

7.6.58 CSEL Register (Address = 0x215) [reset = 0x00]

CSEL is shown in 图7-86 and described in 表7-126.

Return to the Summary Table.

DDC NCO Configuration Preset Select (default: 0x00)

图7-86. CSEL Register

7

6

5

4

3

2

1

0

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图7-86. CSEL Register (continued)

RESERVED

R/W-0x0

CSELB

CSELA

R/W-0x0

表7-126. CSEL Register Field Descriptions

Bit

7:4

3:2

Field

Type

R/W

Reset

Description

RESERVED

CSELB

0x0

When CMODE=0, this register is used to select the active NCO

configuration preset for DDC B In single channel mode, this register

is ignored and CSELA must be used instead.

1:0

CSELA

R/W

0x0

When CMODE=0, this register is used to select the active NCO

configuration preset for DDC A Example: If CSELA=0, then FREQA0

and PHASEA0 are the active settings. If CSELA=1, then FREQA1

and PHASEA1 are the active settings.

In single channel mode CSELA selects the NCO frequency for the

DDC.

7.6.59 DIG_BIND Register (Address = 0x216) [reset = 0x02]

DIG_BIND is shown in 图7-87 and described in 表7-127.

Return to the Summary Table.

Digital Channel Binding (default: 0x02)

图7-87. DIG_BIND Register

7

6

5

4

3

2

1

0

RESERVED

R/W-0x0

DIG_BIND[1]

R/W-0x1

DIG_BIND[0]

R/W-0x0

表7-127. DIG_BIND Register Field Descriptions

Bit

Field

Type

R/W

Reset

Description

7:2

1

RESERVED

DIG_BIND[1]

0x0

0x1

Digital channel B input select:

0: Digital channel B receives data from ADC channel A

1: Digital channel B receives data from ADC channel B (default)

0

DIG_BIND[0]

R/W

0x0

Digital channel A input select:

0: Digital channel A receives data from ADC channel A (default)

1: Digital channel A receives data from ADC channel B

Note 1: When using single channel mode, you must always use the

default setting for DIG_BIND or the device will not work.

Note 2: You must set JESD_EN=0 and CAL_EN=0 before changing

DIG_BIND.

Note 3: The DIG_BIND setting is combined with PD_ACH/PD_BCH

to determine if a digital channel is powered down. Each digital

channel (and link) is powered down when the ADC channel it is

bound to is powered down (by PD_ACH/PD_BCH).

7.6.60 NCO_RDIV Register (Address = 0x217) [reset = 0x0000]

NCO_RDIV is shown in 图7-88 and described in 表7-128.

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Return to the Summary Table.

NCO Reference Divisor (default: 0x0000)

图7-88. NCO_RDIV Register

15

7

14

6

13

12

11

10

2

9

1

8

0

NCO_RDIV

R/W-0x0

5

4

3

NCO_RDIV

R/W-0x0

表7-128. NCO_RDIV Register Field Descriptions

Bit

15:0

Field

NCO_RDIV

Type

Reset

Description

R/W

0x0

Sometimes the 32-bit NCO frequency word does not provide the

desired frequency step size and can only approximate the desired

frequency. This results in a frequency error. Use this register to

eliminate the frequency error.

The default value of 0 disables the reference divisor and the NCO

operates as a traditional 32-bit NCO.

Any combination of FS and FSTEP that results in a fractional value

for NCO_RDIV is not supported. Values of NCO_RDIV larger than

8192 may degrade the NCO’s SFDR performance and are not

recommended. This register is used for all NCO configuration

presets.

7.6.61 NCO_SYNC Register (Address = 0x219) [reset = 0x02]

NCO_SYNC is shown in 图7-89 and described in 表7-129.

Return to the Summary Table.

NCO Synchronization (default: 0x02)

图7-89. NCO_SYNC Register

7

6

5

4

3

2

1

0

RESERVED

R/W-0x0

NCO_SYNC_IL NCO_SYNC_N

A

EXT

R/W-0x1

R/W-0x0

表7-129. NCO_SYNC Register Field Descriptions

Bit

Field

Type

R/W

Reset

Description

7:2

1

RESERVED

0x0

NCO_SYNC_ILA

0x1

When this bit is set, the NCO phase is initialized on the LMFC/LEMC

boundary immediately after the rising edge of the SYNC~ signal

(default). This feature works in 8B/10B and 64B/66B modes. This

feature can be used to precisely align the NCO phase in several

ADCs. In 64B/66B modes SYNC~ is only used for this purpose and

does not affect the link operation.

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表7-129. NCO_SYNC Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

0

NCO_SYNC_NEXT

R/W

0x0

After writing ‘0’and then ‘1’to this bit, the next SYSREF rising

edge will initialize the NCO phase. Once the NCO phase has been

initialized by SYSREF, the NCO will not re-initialize on future

SYSREF edges unless ‘0’and ‘1’is written to this bit again.

Use this to align the NCO in multiple parts (without the need to

restart the JESD link).

1. Make sure the part is powered up, JESD_EN is set, and the

device clock is running.

2. Make sure that SYSREF is disabled (not toggling).

3. Program NCO_SYNC_ILA=0 on all parts.

4. Write NCO_SYNC_NEXT=0 on all parts.

5. Write NCO_SYNC_NEXT=1 on all parts. NCO sync is armed.

6. Instruct the SYSREF source to generate 1 or more SYSREF

pulses.

7. All parts initialize their NCO using the first SYSREF rising edge.

7.6.62 FREQA0 Register (Address = 0x220) [reset = 0xC0000000]

FREQA0 is shown in 图7-90 and described in 表7-130.

Return to the Summary Table.

NCO Frequency (Channel A, Preset 0) (default: 0xC0000000)

图7-90. FREQA0 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

FREQA0

R/W-0xC0000000

表7-130. FREQA0 Register Field Descriptions

Bit

Field

Type

Reset

Description

31:0

FREQA0

R/W

0xC0000000

The following description applies to FREQA0 thru FREQA3 and

FREQB0 thru FREQB3.

The NCO frequency (FNCO) is:

FNCO = FREQA0 * 2³²* FADC

FADC is the sampling frequency of the ADC. FREQA0 is the integer

value of this register. This register can be interpreted as signed or

unsigned (both interpretations are valid).

Use this equation to determine the value to program:

FREQA0 = 2³²* FNCO /FS

If the equation does not result in an integer value, you must choose

an alternate frequency step (FSTEP) and program the NCO_RDIV

register. Then use one of these equations to compute FREQA0:

FREQA0 = round(2³²* FNCO/FS)

FREQA0 = round(2²⁵* FNCO/FSTEP/NCO_RDIV)

Changing this register after the NCO has been synchronized is

running will result in non-deterministic NCO phase. If deterministic

phase is required, the NCO should be re-synchronized after

changing this register.

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7.6.63 PHASEA0 Register (Address = 0x224) [reset = 0x0000]

PHASEA0 is shown in 图7-91 and described in 表7-131.

Return to the Summary Table.

NCO Phase (Channel A, Preset 0) (default: 0x0000)

图7-91. PHASEA0 Register

15

7

14

6

13

5

12

4

11

3

10

2

9

1

8

0

PHASEA0

R/W-0x0

PHASEA0

R/W-0x0

表7-131. PHASEA0 Register Field Descriptions

Bit

15:0

Field

Type

Reset

Description

PHASEA0

R/W

0x0

NCO phase for configuration preset 0. This value is left justified into

a 32−bit field and then added to the phase accumulator. The phase

(in radians) is PHASEA0 * 2^-16* 2π. This register can be interpreted

as signed or unsigned.

7.6.64 FREQA1 Register (Address = 0x228) [reset = 0xC0000000]

FREQA1 is shown in 图7-92 and described in 表7-132.

Return to the Summary Table.

NCO Frequency (Channel A, Preset 1) (default: 0xC0000000)

图7-92. FREQA1 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

FREQA1

R/W-0xC0000000

表7-132. FREQA1 Register Field Descriptions

Bit

Field

Type

Reset

Description

31:0

FREQA1

R/W

0xC0000000

NCO frequency for channel A, NCO preset 1

7.6.65 PHASEA1 Register (Address = 0x22C) [reset = 0x0000]

PHASEA1 is shown in 图7-93 and described in 表7-133.

Return to the Summary Table.

NCO Phase (Channel A, Preset 1) (default: 0x0000)

图7-93. PHASEA1 Register

15

7

14

6

13

5

12

4

11

3

10

2

9

1

8

0

PHASEA1

R/W-0x0

PHASEA1

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图7-93. PHASEA1 Register (continued)

R/W-0x0

表7-133. PHASEA1 Register Field Descriptions

Bit

Field

PHASEA1

Type

Reset

Description

15:0

R/W

0x0

NCO phase for channel A, preset 1

7.6.66 FREQA2 Register (Address = 0x230) [reset = 0xC0000000]

FREQA2 is shown in 图7-94 and described in 表7-134.

Return to the Summary Table.

NCO Frequency (Channel A, Preset 2) (default: 0xC0000000)

图7-94. FREQA2 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

FREQA2

R/W-0xC0000000

表7-134. FREQA2 Register Field Descriptions

Bit

Field

Type

Reset

Description

31:0

FREQA2

R/W

0xC0000000

NCO frequency for channel A, NCO preset 2

7.6.67 PHASEA2 Register (Address = 0x234) [reset = 0x0000]

PHASEA2 is shown in 图7-95 and described in 表7-135.

Return to the Summary Table.

NCO Phase (Channel A, Preset 2) (default: 0x0000)

图7-95. PHASEA2 Register

15

7

14

6

13

5

12

4

11

3

10

2

9

1

8

0

PHASEA2

R/W-0x0

PHASEA2

R/W-0x0

表7-135. PHASEA2 Register Field Descriptions

Bit

15:0

Field

Type

Reset

Description

PHASEA2

R/W

0x0

NCO phase for channel A, preset 2

7.6.68 FREQA3 Register (Address = 0x238) [reset = 0xC0000000]

FREQA3 is shown in 图7-96 and described in 表7-136.

Return to the Summary Table.

NCO Frequency (Channel A, Preset 3) (default: 0xC0000000)

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图7-96. FREQA3 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

FREQA3

R/W-0xC0000000

表7-136. FREQA3 Register Field Descriptions

Bit

Field

Type

Reset

Description

31:0

FREQA3

R/W

0xC0000000

NCO frequency for channel A, NCO preset 3

7.6.69 PHASEA3 Register (Address = 0x23C) [reset = 0x0000]

PHASEA3 is shown in 图7-97 and described in 表7-137.

Return to the Summary Table.

NCO Phase (Channel A, Preset 3) (default: 0x0000)

图7-97. PHASEA3 Register

15

7

14

6

13

5

12

4

11

3

10

2

9

1

8

0

PHASEA3

R/W-0x0

PHASEA3

R/W-0x0

表7-137. PHASEA3 Register Field Descriptions

Bit

15:0

Field

Type

Reset

Description

PHASEA3

R/W

0x0

NCO phase for channel A, preset 3

7.6.70 FREQB0 Register (Address = 0x240) [reset = 0xC0000000]

FREQB0 is shown in 图7-98 and described in 表7-138.

Return to the Summary Table.

NCO Frequency (Channel B, Preset 0) (default: 0xC0000000)

图7-98. FREQB0 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

FREQB0

R/W-0xC0000000

表7-138. FREQB0 Register Field Descriptions

Bit

Field

Type

Reset

Description

31:0

FREQB0

R/W

0xC0000000

NCO frequency for channel B, NCO preset 0.

Note: If the ADC is in DES mode, the NCO frequency and phase

settings for channel B are ignored. Use the NCO frequency and

phase registers for channel A only.

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7.6.71 PHASEB0 Register (Address = 0x244) [reset = 0x0000]

PHASEB0 is shown in 图7-99 and described in 表7-139.

Return to the Summary Table.

NCO Phase (Channel B, Preset 0) (default: 0x0000)

图7-99. PHASEB0 Register

15

7

14

6

13

5

12

4

11

3

10

2

9

1

8

0

PHASEB0

R/W-0x0

PHASEB0

R/W-0x0

表7-139. PHASEB0 Register Field Descriptions

Bit

15:0

Field

Type

Reset

Description

PHASEB0

R/W

0x0

NCO phase for channel B, preset 0

7.6.72 FREQB1 Register (Address = 0x248) [reset = 0xC0000000]

FREQB1 is shown in 图7-100 and described in 表7-140.

Return to the Summary Table.

NCO Frequency (Channel B, Preset 1) (default: 0xC0000000)

图7-100. FREQB1 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

FREQB1

R/W-0xC0000000

表7-140. FREQB1 Register Field Descriptions

Bit

Field

Type

Reset

Description

31:0

FREQB1

R/W

0xC0000000

NCO frequency for channel B, NCO preset 1

7.6.73 PHASEB1 Register (Address = 0x24C) [reset = 0x0000]

PHASEB1 is shown in 图7-101 and described in 表7-141.

Return to the Summary Table.

NCO Phase (Channel B, Preset 1) (default: 0x0000)

图7-101. PHASEB1 Register

15

7

14

6

13

5

12

4

11

3

10

2

9

1

8

0

PHASEB1

R/W-0x0

PHASEB1

R/W-0x0

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表7-141. PHASEB1 Register Field Descriptions

Bit

Field

Type

Reset

Description

15:0

PHASEB1

R/W

0x0

NCO phase for channel B, preset 1

7.6.74 FREQB2 Register (Address = 0x250) [reset = 0xC0000000]

FREQB2 is shown in 图7-102 and described in 表7-142.

Return to the Summary Table.

NCO Frequency (Channel B, Preset 2) (default: 0xC0000000)

图7-102. FREQB2 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

FREQB2

R/W-0xC0000000

表7-142. FREQB2 Register Field Descriptions

Bit

Field

Type

Reset

Description

31:0

FREQB2

R/W

0xC0000000

NCO frequency for channel B, NCO preset 2

7.6.75 PHASEB2 Register (Address = 0x254) [reset = 0x0000]

PHASEB2 is shown in 图7-103 and described in 表7-143.

Return to the Summary Table.

NCO Phase (Channel B, Preset 2) (default: 0x0000)

图7-103. PHASEB2 Register

15

7

14

6

13

5

12

4

11

3

10

2

9

1

8

0

PHASEB2

R/W-0x0

PHASEB2

R/W-0x0

表7-143. PHASEB2 Register Field Descriptions

Bit

15:0

Field

Type

Reset

Description

PHASEB2

R/W

0x0

NCO phase for channel B, preset 2

7.6.76 FREQB3 Register (Address = 0x258) [reset = 0xC0000000]

FREQB3 is shown in 图7-104 and described in 表7-144.

Return to the Summary Table.

NCO Frequency (Channel B, Preset 3) (default: 0xC0000000)

图7-104. FREQB3 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

FREQB3

R/W-0xC0000000

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图7-104. FREQB3 Register (continued)

表7-144. FREQB3 Register Field Descriptions

Bit

Field

FREQB3

Type

Reset

Description

31:0

R/W

0xC0000000

NCO frequency for channel B, NCO preset 3

7.6.77 PHASEB3 Register (Address = 0x25C) [reset = 0x0000]

PHASEB3 is shown in 图7-105 and described in 表7-145.

Return to the Summary Table.

NCO Phase (Channel B, Preset 3) (default: 0x0000)

图7-105. PHASEB3 Register

15

7

14

6

13

5

12

4

11

3

10

2

9

1

8

0

PHASEB3

R/W-0x0

PHASEB3

R/W-0x0

表7-145. PHASEB3 Register Field Descriptions

Bit

15:0

Field

Type

Reset

Description

PHASEB3

R/W

0x0

NCO phase for channel B, preset 3

7.6.78 INIT_STATUS Register (Address = 0x270) [reset = undefined]

INIT_STATUS is shown in 图7-106 and described in 表7-146.

Return to the Summary Table.

Chip Spin Identifier (default: See description, read-only)

图7-106. INIT_STATUS Register

7

6

5

4

3

2

1

0

RESERVED

R-undefined

INIT_STATUS

R-undefined

表7-146. INIT_STATUS Register Field Descriptions

Bit

Field

Type

Reset

Description

7:1

0

RESERVED

INIT_DONE

R

undefined

RESERVED

R

Returns 1 when the initialization logic has finished initializing the

device. This indicates that it is now safe to proceed with startup. No

SPI transactions should be performed before INIT_DONE returns

1(except SOFT_RESET).

7.6.79 SPIN_ID Register (Address = 0x297) [reset = 0x03]

SPIN_ID is shown in 图7-107 and described in 表7-147.

Return to the Summary Table.

Chip Spin Identifier (default: See description, read-only)

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图7-107. SPIN_ID Register

7

6

5

4

3

2

1

0

RESERVED

R/W-0x0

SPIN_ID

R/W-0x03

表7-147. SPIN_ID Register Field Descriptions

Bit

Field

Type

R/W

Reset

Description

7:5

4:0

RESERVED

SPIN_ID

0x0

Spin identification value:

3 : ADC12DJ5200SE

7.6.80 TESTBUS Register (Address = 0x2A2) [reset = 0x0]

TESTBUS is shown in 图7-108 and described in 表7-148.

Return to the Summary Table.

TESTBUS Register (default: 0x0)

图7-108. TESTBUS Register

7

6

5

4

3

2

1

0

RESERVED

R/W-0x0

EN_VD11_NOI EN_VS11_NOI

RESERVED

R/W-0x0

SE_SUPPR

R/W-0x0

表7-148. TESTBUS Register Field Descriptions

Bit

Field

Type

Reset

Description

7:6

5

RESERVED

R/W

0x0

RESERVED

EN_VD11_NOISE_SUPP R/W

R

0x0

When set, noise on VD11 is suppressed. It is recommended to have

this set, as it reduces noise coupling from the digital circuits to

analog clock, at the expense of a small increase in power.

4

EN_VS11_NOISE_SUPP R/W

R

When set, noise on VS11 is suppressed. It is recommended to have

this set, as it reduces noise coupling from the digital circuits to

analog clock, at the expense of a small increase in power.

3:0

RESERVED

R/W

RESERVED

7.6.81 SRC_EN Register (Address = 0x2B0) [reset = 0x00]

SRC_EN is shown in 图7-109 and described in 表7-149.

Return to the Summary Table.

SYSREF Calibration Enable (default: 0x00)

图7-109. SRC_EN Register

7

6

5

4

3

2

1

0

RESERVED

R/W-0x0

SRC_EN

R/W-0x0

表7-149. SRC_EN Register Field Descriptions

Bit

7:1

Field

RESERVED

Type

Reset

Description

R/W

0x0

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表7-149. SRC_EN Register Field Descriptions (continued)

Bit

Field

SRC_EN

Type

Reset

Description

0

R/W

0x0

0: SYSREF Calibration Disabled. Use the TAD register to manually

control the tad[16:0] output and adjust the DEVCLK delay. (default)

1: SYSREF Calibration Enabled. The DEVCLK delay is automatically

calibrated. The TAD register is ignored.

A 0-to-1 transition on SRC_EN starts the SYSREF calibration

sequence. Program SRC_CFG before setting SRC_EN. Make sure

the ADC calibration is not currently running before setting SRC_EN.

7.6.82 SRC_CFG Register (Address = 0x2B1) [reset = 0x05]

SRC_CFG is shown in 图7-110 and described in 表7-150.

Return to the Summary Table.

SYSREF Calibration Configuration (default: 0x05)

图7-110. SRC_CFG Register

7

6

5

4

3

2

1

0

RESERVED

R/W-0x0

SRC_AVG

R/W-0x1

SRC_HDUR

R/W-0x1

表7-150. SRC_CFG Register Field Descriptions

Bit

Field

Type

R/W

Reset

Description

7:4

3:2

RESERVED

SRC_AVG

0x0

0x1

Specifies the amount of averaging used for SYSREF Calibration.

Larger values will increase calibration time and reduce the variance

of the calibrated value.

0: 4 averages

1: 16 averages

2: 64 averages

3: 256 averages

1:0

SRC_HDUR

R/W

0x1

Specifies the duration of each high-speed accumulation for SYSREF

Calibration. If the SYSREF period exceeds the supported value,

calibration will fail. Larger values will increase calibration time and

support longer SYSREF periods. For a given SYSREF period, larger

values will also reduce the variance of the calibrated value.

0: 4 cycles per accumulation, max SYSREF period of 128 DEVCLK

cycles

1: 16 cycles per accumulation, max SYSREF period of 1664

DEVCLK cycles

2: 64 cycles per accumulation, max SYSREF period of 7808

DEVCLK cycles

3: 256 cycles per accumulation, max SYSREF period of 32384

DEVCLK cycles

Max duration of SYSREF calibration is bounded by: TSYSREFCAL

(in DEVCLK cycles) = 384 * 19 * 4^(SRC_AVG + SRC_HDUR + 2)

7.6.83 SRC_STATUS Register (Address = 0x2B2) [reset = 0x0]

SRC_STATUS is shown in 图7-111 and described in 表7-151.

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Return to the Summary Table.

SYSREF Calibration Status (read-only, default: undefined)

图7-111. SRC_STATUS Register

23

15

7

22

14

6

21

13

5

20

12

4

19

11

3

18

10

2

17

16

RESERVED

R/W-0x0

SRC_DONE

R/W-0x0

SRC_TAD

R/W-0x0

9

8

SRC_TAD

R/W-0x0

1

0

SRC_TAD

R/W-0x0

表7-151. SRC_STATUS Register Field Descriptions

Bit

Field

Type

R/W

Reset

Description

23:18

17

RESERVED

SRC_DONE

0x0

This bit returns ‘1’when SRC_EN=1 and SYSREF Calibration

has been completed.

16:0

SRC_TAD

R/W

0x0

This field returns the value for TAD[16:0] computed by SYSREF

Calibration. It is only valid if SRC_DONE=1.

SRC_TAD[16] indicates if DEVCLK has been inverted.

SRC_TAD[15:8] indicates the coarse delay adjustment.

SRC_TAD[7:0] indicates the fine delay adjustment.

7.6.84 TAD Register (Address = 0x2B5) [reset = 0x00]

TAD is shown in 图7-112 and described in 表7-152.

Return to the Summary Table.

DEVCLK Timing Adjust (default: 0x00)

图7-112. TAD Register

23

15

7

22

14

6

21

13

5

20

19

18

10

2

17

9

16

RESERVED

R/W-0x0

TAD_INV

R/W-0x0

12

11

3

8

TAD_COARSE

R/W-0x0

4

1

0

RESERVED

R-0x0

表7-152. TAD Register Field Descriptions

Bit

Field

Type

R/W

Reset

Description

23:17

16

RESERVED

TAD_INV

0x0

Inverts the sampling clock when set.

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表7-152. TAD Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

15:8

TAD_FINE

R/W

0x0

Refer to Switching Characteristics for TAD_FINE resolution.

15:8

TAD_COARSE

R/W

0x0

This register controls the sampling aperture delay adjustment when

SRC_EN=0. Use this register to manually control the DEVCLK

aperture delay when SYSREF Calibration is disabled. If ADC

calibration or JESD204B is running, it is recommended that you

gradually increase or decrease this value (1 code at a time) to avoid

clock glitches. Refer to Switching Characteristics for TAD_COARSE

resolution.

If ADC calibration is enabled (CAL_EN=1), or the JESD204C link is

enabled (JESD_EN=1), the following rules must be obeyed to avoid

clock glitches and unpredictable behavior:

1. Do not change TAD_INV. You must program CAL_EN=0 and

JESD_EN=0 before changing TAD_INV.

2. TAD_COARSE must be increased or decreased gradually (no

more than 4 codes at a time). This rule can be obeyed manually via

SPI writes, or by setting TAD_RAMP_EN.

3. TAD_FINE may be changed to any value at any time (its

adjustment is too fine to cause clock glitches).

7:0

RESERVED

R

0x0

7.6.85 TAD_RAMP Register (Address = 0x2B8) [reset = 0x00]

TAD_RAMP is shown in 图7-113 and described in 表7-153.

Return to the Summary Table.

DEVCLK Timing Adjust Ramp Control (default: 0x00)

图7-113. TAD_RAMP Register

7

6

5

4

3

2

1

0

RESERVED

R/W-0x0

TAD_RAMP_R TAD_RAMP_E

ATE

N

R/W-0x0

表7-153. TAD_RAMP Register Field Descriptions

Bit

Field

Type

R/W

Reset

Description

7:2

1

RESERVED

0x0

TAD_RAMP_RATE

0x0

Specifies the ramp rate for TAD_COARSE when the TAD_COARSE

register is written while TAD_RAMP_EN=1.

0: TAD_COARSE ramps up or down one code per 384 sampling

clock cycles.

1: TAD_COARSE ramps up or down 4 codes per 384 sampling clock

cycles.

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表7-153. TAD_RAMP Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

0

TAD_RAMP_EN

R/W

0x0

TAD ramp enable. Set this bit if you want the coarse TAD adjustment

(TAD_COARSE) to ramp up or down instead of changing abruptly.

0 : After writing the TAD_COARSE register, the applied

TAD_COARSE setting is updated within 1536 CLK cycles (ramp

feature disabled).

1 : After writing the TAD_COARSE register, the applied

TAD_COARSE setting ramps up or down gradually until it matches

the TAD_COARSE register.

7.6.86 ALARM Register (Address = 0x2C0) [reset = 0x0]

ALARM is shown in 图7-114 and described in 表7-154.

Return to the Summary Table.

Alarm Interrupt (read-only)

图7-114. ALARM Register

7

6

5

4

3

2

1

0

RESERVED

R-0x0

ALARM

R-0x0

表7-154. ALARM Register Field Descriptions

Bit

Field

Type

Reset

Description

7:1

0

RESERVED

ALARM

R

0x0

R

0x0

This bit returns a ‘1’whenever any alarm occurs that is

unmasked in the ALM_STATUS register. Use ALM_MASK to mask

(disable) individual alarms. CAL_STATUS_SEL can be used to drive

the ALARM bit onto the CALSTAT output pin to provide a hardware

alarm interrupt signal.

7.6.87 ALM_STATUS Register (Address = 0x2C1) [reset = 0x3F]

ALM_STATUS is shown in 图7-115 and described in 表7-155.

Return to the Summary Table.

Alarm Status (default: 0x3F, write to clear)

图7-115. ALM_STATUS Register

7

6

5

4

3

2

1

0

RESERVED

R/W-0x0

FIFO_ALM

PLL_ALM

LINK_ALM

REALIGNED_A

LM

NCO_ALM

CLK_ALM

R/W-0x1

表7-155. ALM_STATUS Register Field Descriptions

Bit

7:6

Field

Type

Reset

Description

RESERVED

R/W

0x0

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表7-155. ALM_STATUS Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

5

FIFO_ALM

R/W

0x1

FIFO overflow/underflow alarm: This bit is set whenever an active

JESD204C lane FIFO experiences an underflow or overflow

condition. Write a ‘1’to clear this bit. To inspect which lane

generated the alarm, read FIFO_LANE_ALM.

4

3

PLL_ALM

R/W

0x1

PLL Lock Lost Alarm: This bit is set whenever the PLL is not locked.

Write a ‘1’to clear this bit.

LINK_ALM

Link Alarm: This bit is set whenever the JESD204C link is enabled,

but is not in the data encoder state (for 8B/10B modes). In 64B/66B

modes, there is no data encoder state, so this alarm will be set when

the link first starts up, and will also be set if any event causes a

FIFO/serializer realignment. Write a ‘1’to clear this bit.

2

1

REALIGNED_ALM

NCO_ALM

R/W

0x1

Realigned Alarm: This bit is set whenever SYSREF causes the

internal clocks (including the LMFC/LEMC) to be realigned. Write a

‘1’to clear this bit.

NCO Alarm: This bit can be used to detect an upset to the NCO

phase. This bit is set when any of the following occur:

- The NCOs are disabled (JESD_EN=0).

- The NCOs are synchronized (intentionally or unintentionally)

- Any phase accumulators in channel A do not match channel B.

Write a ‘1’to clear this bit. Refer to the alarm section for the

proper usage of this register.

0

CLK_ALM

R/W

0x1

Clock Alarm: This bit can be used to detect an upset to the internal

DDC/JESD204C clocks. This bit is set whenever the internal clock

dividers for the A and B channels do not match. Write a ‘1’to

clear this bit. Refer to the alarm section for the proper usage of this

register.

Note: After power-on reset or soft-reset, all alarm bits are set to

‘1.’

Note: When JESD_EN=0, all alarms (except CLK_ALM) are

undefined. It is recommended that the user clears the alarms after

setting JESD_EN=1.

7.6.88 ALM_MASK Register (Address = 0x2C2) [reset = 0x3F]

ALM_MASK is shown in 图7-116 and described in 表7-156.

Return to the Summary Table.

Alarm Mask Register (default: 0x3F)

图7-116. ALM_MASK Register

7

6

5

4

3

2

1

0

RESERVED

R/W-0x0

MASK_FIFO_A MASK_PLL_AL MASK_LINK_A MASK_REALIG MASK_NCO_A MASK_CLK_AL

LM

M

LM

NED_ALM

LM

M

R/W-0x1

表7-156. ALM_MASK Register Field Descriptions

Bit

7:6

Field

Type

Reset

Description

RESERVED

R/W

0x0

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表7-156. ALM_MASK Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

5

MASK_FIFO_ALM

R/W

0x1

When set, FIFO_ALM is masked and will not impact the ALARM

register bit.

4

3

2

1

0

MASK_PLL_ALM

MASK_LINK_ALM

R/W

0x1

When set, PLL_ALM is masked and will not impact the ALARM

register bit.

When set, LINK_ALM is masked and will not impact the ALARM

register bit.

MASK_REALIGNED_ALM R/W

When set, REALIGNED_ALM is masked and will not impact the

ALARM register bit.

MASK_NCO_ALM

MASK_CLK_ALM

R/W

When set, NCO_ALM is masked and will not impact the ALARM

register bit.

When set, CLK_ALM is masked and will not impact the ALARM

register bit.

7.6.89 FIFO_LANE_ALM Register (Address = 0x2C4) [reset = 0xFFFF]

FIFO_LANE_ALM is shown in 图7-117 and described in 表7-157.

Return to the Summary Table.

FIFO Overflow/Underflow Alarm (default: 0xFFFF)

图7-117. FIFO_LANE_ALM Register

15

7

14

6

13

5

12

FIFO_LANE_ALM

R/W-0xFFFF

11

10

2

9

1

8

0

4

3

FIFO_LANE_ALM

R/W-0xFFFF

表7-157. FIFO_LANE_ALM Register Field Descriptions

Bit

15:0

Field

FIFO_LANE_ALM

Type

Reset

Description

R/W

0xFFFF

FIFO_LANE_ALM[i] is set if the FIFO for lane i experiences overflow

or underflow. Use this register to determine which lane(s) generated

an alarm. Writing a ‘1’to any bit in this register will clear the alarm

(the alarm may immediately trip again if the overflow/underflow

condition persists). Writing a ‘1’to the FIFO_ALM bit in the

ALM_STATUS register will clear all bits of this register.

7.6.90 TADJ_A Register (Address = 0x310) [reset = 0x0]

TADJ_A is shown in 图7-118 and described in 表7-158.

Return to the Summary Table.

Timing Adjust for A-ADC operating in Dual Channel Mode (default from Fuse ROM)

图7-118. TADJ_A Register

7

6

5

4

3

2

1

0

TADJ_A

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图7-118. TADJ_A Register (continued)

R/W-0x0

表7-158. TADJ_A Register Field Descriptions

Bit

Field

TADJ_A

Type

Reset

Description

7:0

R/W

0x0

This register (and other TADJ* registers that follow it) are used to

adjust the sampling instant of each ADC core. Different TADJ

registers apply to different ADCs under different modes. The default

values for all TADJ* registers are factory programmed values. The

factory trimmed values can be read out and adjusted as required.

7.6.91 TADJ_B Register (Address = 0x313) [reset = 0x0]

TADJ_B is shown in 图7-119 and described in 表7-159.

Return to the Summary Table.

Timing Adjust for B-ADC operating in Dual Channel Mode (default from Fuse ROM)

图7-119. TADJ_B Register

7

6

5

4

3

2

1

0

TADJ_B

R/W-0x0

表7-159. TADJ_B Register Field Descriptions

Bit

7:0

Field

Type

Reset

Description

TADJ_B

R/W

0x0

See TADJ_A register for description. Adjusts timing of B-ADC in dual

channel mode with foreground calibration enabled.

7.6.92 TADJ_A_FG90_VINA Register (Address = 0x314) [reset = 0x0]

TADJ_A_FG90_VINA is shown in 图7-120 and described in 表7-160.

Return to the Summary Table.

Timing Adjust for A-ADC operating in Single Channel Mode and sampling INA (default from Fuse ROM)

图7-120. TADJ_A_FG90_VINA Register

7

6

5

4

3

2

1

0

TADJ_A_FG90_VINA

R/W-0x0

表7-160. TADJ_A_FG90_VINA Register Field Descriptions

Bit

7:0

Field

Type

Reset

Description

TADJ_A_FG90_VINA

R/W

0x0

See TADJ_A register for description. Adjusts timing of A-ADC in

single channel mode with foreground calibration enabled and

sampling INA.

7.6.93 TADJ_B_FG0_VINA Register (Address = 0x315) [reset = 0x0]

TADJ_B_FG0_VINA is shown in 图7-121 and described in 表7-161.

Return to the Summary Table.

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Timing Adjust for B-ADC operating in Single Channel Mode and sampling INA (default from Fuse ROM)

图7-121. TADJ_B_FG0_VINA Register

7

6

5

4

3

2

1

0

TADJ_B_FG0_VINA

R/W-0x0

表7-161. TADJ_B_FG0_VINA Register Field Descriptions

Bit

7:0

Field

Type

Reset

Description

TADJ_B_FG0_VINA

R/W

0x0

See TADJ_A register for description. Adjusts timing of B-ADC in

single channel mode with foreground calibration enabled and

sampling INA.

7.6.94 TADJ_A_FG90_VINB Register (Address = 0x31A) [reset = 0x0]

TADJ_A_FG90_VINB is shown in 图7-122 and described in 表7-162.

Return to the Summary Table.

Timing Adjust for A-ADC operating in Single Channel Mode and sampling INB (default from Fuse ROM)

图7-122. TADJ_A_FG90_VINB Register

7

6

5

4

3

2

1

0

TADJ_A_FG90_VINB

R/W-0x0

表7-162. TADJ_A_FG90_VINB Register Field Descriptions

Bit

7:0

Field

Type

Reset

Description

TADJ_A_FG90_VINB

R/W

0x0

See TADJ_A register for description. Adjusts timing of A-ADC in

single channel mode with foreground calibration enabled and

sampling INB.

7.6.95 TADJ_B_FG0_VINB Register (Address = 0x31B) [reset = 0x0]

TADJ_B_FG0_VINB is shown in 图7-123 and described in 表7-163.

Return to the Summary Table.

Timing Adjust for B-ADC operating in Single Channel Mode and sampling INB (default from Fuse ROM)

图7-123. TADJ_B_FG0_VINB Register

7

6

5

4

3

2

1

0

TADJ_B_FG0_VINB

R/W-0x0

表7-163. TADJ_B_FG0_VINB Register Field Descriptions

Bit

7:0

Field

Type

Reset

Description

TADJ_B_FG0_VINB

R/W

0x0

See TADJ_A register for description. Adjusts timing of B-ADC in

single channel mode with foreground calibration enabled and

sampling INB.

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7.6.96 OADJ_A_FG0_VINA Register (Address = 0x344) [reset = 0x0]

OADJ_A_FG0_VINA is shown in 图7-124 and described in 表7-164.

Return to the Summary Table.

Offset Adjustment for A-ADC operating in Dual Channel Mode sampling INA (default from Fuse ROM)

图7-124. OADJ_A_FG0_VINA Register

15

7

14

6

13

12

11

10

9

8

0

RESERVED

R/W-0x0

OADJ_A_FG0_VINA

R/W-0x0

5

4

3

2

1

OADJ_A_FG0_VINA

R/W-0x0

表7-164. OADJ_A_FG0_VINA Register Field Descriptions

Bit

Field

Type

R/W

Reset

Description

15:12

11:0

RESERVED

0x0

OADJ_A_FG0_VINA

0x0

Offset adjustment value applied to A-ADC when it samples INA in

dual channel mode and foreground calibration is enabled.

7.6.97 OADJ_A_FG0_VINB Register (Address = 0x346) [reset = 0x0]

OADJ_A_FG0_VINB is shown in 图7-125 and described in 表7-165.

Return to the Summary Table.

Offset Adjustment for A-ADC operating in Dual Channel Mode sampling INB (default from Fuse ROM)

图7-125. OADJ_A_FG0_VINB Register

15

7

14

6

13

5

12

11

10

9

8

0

RESERVED

R/W-0x0

OADJ_A_FG_VINB

R/W-0x0

4

3

2

1

OADJ_A_FG_VINB

R/W-0x0

表7-165. OADJ_A_FG0_VINB Register Field Descriptions

Bit

Field

Type

R/W

Reset

Description

15:12

11:0

RESERVED

0x0

OADJ_A_FG_VINB

0x0

Offset adjustment value applied to A-ADC when it samples INB in

dual channel mode and foreground calibration is enabled.

7.6.98 OADJ_A_FG90_VINA Register (Address = 0x348) [reset = 0x0]

OADJ_A_FG90_VINA is shown in 图7-126 and described in 表7-166.

Return to the Summary Table.

Offset Adjustment for A-ADC operating in Single Channel Mode sampling INA (default from Fuse ROM)

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图7-126. OADJ_A_FG90_VINA Register

15

7

14

6

13

12

11

10

9

8

RESERVED

R/W-0x0

OADJ_A_FG90_VINA

R/W-0x0

5

4

3

2

1

0

OADJ_A_FG90_VINA

R/W-0x0

表7-166. OADJ_A_FG90_VINA Register Field Descriptions

Bit

Field

Type

R/W

Reset

Description

15:12

11:0

RESERVED

0x0

OADJ_A_FG90_VINA

0x0

Offset adjustment value applied to A-ADC when it samples INA in

single channel mode and foreground calibration is enabled.

7.6.99 OADJ_A_FG90_VINB Register (Address = 0x34A) [reset = 0x0]

OADJ_A_FG90_VINB is shown in 图7-127 and described in 表7-167.

Return to the Summary Table.

Offset Adjustment for A-ADC operating in Single Channel Mode sampling INB (default from Fuse ROM)

图7-127. OADJ_A_FG90_VINB Register

15

7

14

6

13

5

12

11

10

9

8

0

RESERVED

R/W-0x0

OADJ_A_FG90_VINB

R/W-0x0

4

3

2

1

OADJ_A_FG90_VINB

R/W-0x0

表7-167. OADJ_A_FG90_VINB Register Field Descriptions

Bit

Field

Type

R/W

Reset

Description

15:12

11:0

RESERVED

0x0

OADJ_A_FG90_VINB

0x0

Offset adjustment value applied to A-ADC when it samples INB using

90° clock phase and foreground calibration is enabled.

7.6.100 OADJ_B_FG0_VINA Register (Address = 0x34C) [reset = 0x0]

OADJ_B_FG0_VINA is shown in 图7-128 and described in 表7-168.

Return to the Summary Table.

Offset Adjustment for B-ADC sampling INA (default from Fuse ROM)

图7-128. OADJ_B_FG0_VINA Register

15

7

14

6

13

5

12

11

10

9

8

0

RESERVED

R/W-0x0

OADJ_B_FG0_VINA

R/W-0x0

4

3

2

1

OADJ_B_FG0_VINA

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图7-128. OADJ_B_FG0_VINA Register (continued)

R/W-0x0

表7-168. OADJ_B_FG0_VINA Register Field Descriptions

Bit

15:12

11:0

Field

Type

R/W

Reset

Description

RESERVED

0x0

OADJ_B_FG0_VINA

0x0

Offset adjustment value applied to B-ADC when it samples INA and

foreground calibration is enabled. Applies to both dual channel mode

and single channel mode.

7.6.101 OADJ_B_FG0_VINB Register (Address = 0x34E) [reset = 0x0]

OADJ_B_FG0_VINB is shown in 图7-129 and described in 表7-169.

Return to the Summary Table.

Offset Adjustment for B-ADC sampling INB (default from Fuse ROM)

图7-129. OADJ_B_FG0_VINB Register

15

7

14

6

13

5

12

11

10

9

8

0

RESERVED

R/W-0x0

OADJ_B_FG0_VINB

R/W-0x0

4

3

2

1

OADJ_B_FG0_VINB

R/W-0x0

表7-169. OADJ_B_FG0_VINB Register Field Descriptions

Bit

Field

Type

R/W

Reset

Description

15:12

11:0

RESERVED

0x0

OADJ_B_FG0_VINB

0x0

Offset adjustment value applied to B-ADC when it samples INB and

foreground calibration is enabled. Applies to both dual channel mode

and single channel mode.

7.6.102 GAIN_A0_FGDUAL Register (Address = 0x350) [reset = 0x0]

GAIN_A0_FGDUAL is shown in 图7-130 and described in 表7-170.

Return to the Summary Table.

Fine Gain Adjust for ADC A Bank 0 in Dual Channel Mode (default from Fuse ROM)

图7-130. GAIN_A0_FGDUAL Register

7

6

5

4

3

2

1

0

RESERVED

R/W-0x0

GAIN_A0_FGDUAL

R/W-0x0

表7-170. GAIN_A0_FGDUAL Register Field Descriptions

Bit

Field

Type

R/W

Reset

Description

7:5

4:0

RESERVED

0x0

GAIN_A0_FGDUAL

0x0

Fine gain adjustment for ADC A bank 0.

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7.6.103 GAIN_A1_FGDUAL Register (Address = 0x351) [reset = 0x0]

GAIN_A1_FGDUAL is shown in 图7-131 and described in 表7-171.

Return to the Summary Table.

Fine Gain Adjust for ADC A Bank 1 in Dual Channel Mode (default from Fuse ROM)

图7-131. GAIN_A1_FGDUAL Register

7

6

5

4

3

2

1

0

RESERVED

R/W-0x0

GAIN_A1_FGDUAL

R/W-0x0

表7-171. GAIN_A1_FGDUAL Register Field Descriptions

Bit

Field

Type

R/W

Reset

Description

7:5

4:0

RESERVED

0x0

GAIN_A1_FGDUAL

0x0

Fine gain adjustment for ADC A bank 1.

7.6.104 GAIN_B0_FGDUAL Register (Address = 0x352) [reset = 0x0]

GAIN_B0_FGDUAL is shown in 图7-132 and described in 表7-172.

Return to the Summary Table.

Fine Gain Adjust for ADC B Bank 0 in Dual Channel Mode (default from Fuse ROM)

图7-132. GAIN_B0_FGDUAL Register

7

6

5

4

3

2

0

RESERVED

R/W-0x0

GAIN_A0_FGDUAL

R/W-0x0

表7-172. GAIN_B0_FGDUAL Register Field Descriptions

Bit

Field

Type

R/W

Reset

Description

7:5

4:0

RESERVED

0x0

GAIN_A0_FGDUAL

0x0

Fine gain adjustment for ADC B bank 0.

7.6.105 GAIN_B1_FGDUAL Register (Address = 0x353) [reset = 0x0]

GAIN_B1_FGDUAL is shown in 图7-133 and described in 表7-173.

Return to the Summary Table.

Fine Gain Adjust for ADC B Bank 1 in Dual Channel Mode (default from Fuse ROM)

图7-133. GAIN_B1_FGDUAL Register

7

6

5

4

3

2

0

RESERVED

R/W-0x0

GAIN_B1_FGDUAL

R/W-0x0

表7-173. GAIN_B1_FGDUAL Register Field Descriptions

Bit

Field

Type

R/W

Reset

Description

7:5

4:0

RESERVED

0x0

GAIN_B1_FGDUAL

0x0

Fine gain adjustment for ADC B bank 1.

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7.6.106 GAIN_A0_FGDES Register (Address = 0x354) [reset = 0x0]

GAIN_A0_FGDES is shown in 图7-134 and described in 表7-174.

Return to the Summary Table.

Fine Gain Adjust for ADC A Bank 0 in Single Channel Mode (default from Fuse ROM)

图7-134. GAIN_A0_FGDES Register

7

6

5

4

3

2

1

0

RESERVED

R/W-0x0

GAIN_A0_FGDUAL

R/W-0x0

表7-174. GAIN_A0_FGDES Register Field Descriptions

Bit

Field

Type

R/W

Reset

Description

7:5

4:0

RESERVED

0x0

GAIN_A0_FGDUAL

0x0

Fine gain adjustment for ADC A bank 0.

7.6.107 GAIN_A1_FGDES Register (Address = 0x355) [reset = 0x0]

GAIN_A1_FGDES is shown in 图7-135 and described in 表7-175.

Return to the Summary Table.

Fine Gain Adjust for ADC A Bank 1 in Single Channel Mode (default from Fuse ROM)

图7-135. GAIN_A1_FGDES Register

7

6

5

4

3

2

RESERVED

R/W-0x0

GAIN_A1_FGDUAL

R/W-0x0

表7-175. GAIN_A1_FGDES Register Field Descriptions

Bit

Field

Type

R/W

Reset

Description

7:5

4:0

RESERVED

0x0

GAIN_A1_FGDUAL

0x0

Fine gain adjustment for ADC A bank 1.

7.6.108 GAIN_B0_FGDES Register (Address = 0x356) [reset = 0x0]

GAIN_B0_FGDES is shown in 图7-136 and described in 表7-176.

Return to the Summary Table.

Fine Gain Adjust for ADC B Bank 0 in Single Channel Mode (default from Fuse ROM)

图7-136. GAIN_B0_FGDES Register

7

6

5

4

3

2

RESERVED

R/W-0x0

GAIN_A0_FGDUAL

R/W-0x0

表7-176. GAIN_B0_FGDES Register Field Descriptions

Bit

Field

Type

R/W

Reset

Description

7:5

4:0

RESERVED

0x0

GAIN_A0_FGDUAL

0x0

Fine gain adjustment for ADC B bank 0.

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7.6.109 GAIN_B1_FGDES Register (Address = 0x357) [reset = 0x0]

GAIN_B1_FGDES is shown in 图7-137 and described in 表7-177.

Return to the Summary Table.

Fine Gain Adjust for ADC B Bank 1 in Single Channel Mode (default from Fuse ROM)

图7-137. GAIN_B1_FGDES Register

7

6

5

4

3

2

1

0

RESERVED

R/W-0x0

GAIN_B1_FGDUAL

R/W-0x0

表7-177. GAIN_B1_FGDES Register Field Descriptions

Bit

Field

Type

R/W

Reset

Description

7:5

4:0

RESERVED

0x0

GAIN_B1_FGDUAL

0x0

Fine gain adjustment for ADC B bank 1.

7.6.110 PFIR_CFG Register (Address = 0x400) [reset = 0x00]

PFIR_CFG is shown in 图7-138 and described in 表7-178.

Return to the Summary Table.

Programmable FIR Mode (default: 0x00)

图7-138. PFIR_CFG Register

7

6

5

4

3

2

1

0

RESERVED

R/W-0x0

PFIR_SHARE PFIR_MERGE

R/W-0x0 R/W-0x0

PFIR_SCW

R/W-0x0

PFIR_MODE

R/W-0x0

表7-178. PFIR_CFG Register Field Descriptions

Bit

7

Field

RESERVED

Type

R/W

Reset

Description

0x0

6

PFIR_SHARE

PFIR_MERGE

PFIR_SCW

0x0

When set, the PFIR on the B channel uses the same coefficients as

the PFIR on the A channel. When PFIR_SHARE=0, the B channel

filter uses its own set of coefficients (unique from channel A). See

Programmable FIR Filter (PFIR) section for usage details.

5

R/W

0x0

When set, the PFIR filters are merged into a single logical filter. This

mode processes ADC data samples as if they belong to a single

sample stream. Set PFIR_MERGE=1 whenever the ADC is setup in

Single Channel Mode.

4:2

Side coefficient weight for PFIR. This field determines the weight of

the coefficients (except for the center coefficient). Increasing the

coefficient weight increases the range of the coefficients at the

expense of reduced precision. The LSB weight is 2^PFIR_SCW-16

where PFIR_SCW weight can be programmed from 0 to 6. The

default is 0 which provides an LSB weight of 2^-16

,

.

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表7-178. PFIR_CFG Register Field Descriptions (continued)

Bit

Field

PFIR_MODE

Type

Reset

Description

1:0

R/W

0x0

0 : PFIR block is disabled (default)

1 : RESERVED

2 : Enable PFIR block

3 : RESERVED

Note: When using the PFIR, you must also program the filter

coefficients.

Note: All PFIR_* register should only be changed when JESD_EN=0.

7.6.111 PFIR_A0 Register (Address = 0x418) [reset = 0x0]

PFIR_A0 is shown in 图7-139 and described in 表7-179.

Return to the Summary Table.

PFIR Coefficient A0

图7-139. PFIR_A0 Register

15

7

14

6

13

5

12

11

10

2

9

1

8

0

RESERVED

R/W-0x0

PFIR_A0

R/W-0x0

4

3

PFIR_A0

R/W-0x0

表7-179. PFIR_A0 Register Field Descriptions

Bit

Field

Type

R/W

Reset

Description

15:12

11:0

RESERVED

PFIR_A0

0x0

Signed, 2’s complement coefficient for the PFIR filter. This is the

first tap for the ADC A programmable FIR filter in Dual Channel

Mode or the first tap for the programmable FIR filter in Single

Channel Mode.

7.6.112 PFIR_A1 Register (Address = 0x41A) [reset = 0x0]

PFIR_A1 is shown in 图7-140 and described in 表7-180.

Return to the Summary Table.

PFIR Coefficient A1

图7-140. PFIR_A1 Register

15

7

14

6

13

5

12

11

10

2

9

1

8

0

RESERVED

R/W-0x0

PFIR_A1

R/W-0x0

4

3

PFIR_A1

R/W-0x0

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表7-180. PFIR_A1 Register Field Descriptions

Bit

15:12

11:0

Field

Type

R/W

Reset

Description

RESERVED

PFIR_A1

0x0

Signed, 2’s complement coefficient for the PFIR filter. This is the

second tap for the ADC A programmable FIR filter in Dual Channel

Mode or the second tap for the programmable FIR filter in Single

Channel Mode.

7.6.113 PFIR_A2 Register (Address = 0x41C) [reset = 0x0]

PFIR_A2 is shown in 图7-141 and described in 表7-181.

Return to the Summary Table.

PFIR Coefficient A2

图7-141. PFIR_A2 Register

15

7

14

6

13

5

12

11

10

2

9

1

8

0

RESERVED

R/W-0x0

PFIR_A2

R/W-0x0

4

3

PFIR_A2

R/W-0x0

表7-181. PFIR_A2 Register Field Descriptions

Bit

Field

Type

R/W

Reset

Description

15:12

11:0

RESERVED

PFIR_A2

0x0

Signed, 2’s complement coefficient for the PFIR filter. This is the

third tap for the ADC A programmable FIR filter in Dual Channel

Mode or the third tap for the programmable FIR filter in Single

Channel Mode.

7.6.114 PFIR_A3 Register (Address = 0x41E) [reset = 0x0]

PFIR_A3 is shown in 图7-142 and described in 表7-182.

Return to the Summary Table.

PFIR Coefficient A3

图7-142. PFIR_A3 Register

15

7

14

6

13

5

12

11

10

2

9

1

8

0

RESERVED

R/W-0x0

PFIR_A3

R/W-0x0

4

3

PFIR_A3

R/W-0x0

表7-182. PFIR_A3 Register Field Descriptions

Bit

15:12

Field

RESERVED

Type

Reset

Description

R/W

0x0

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表7-182. PFIR_A3 Register Field Descriptions (continued)

Bit

Field

PFIR_A3

Type

Reset

Description

11:0

R/W

0x0

Signed, 2’s complement coefficient for the PFIR filter. This is the

fourth tap for the ADC A programmable FIR filter in Dual Channel

Mode or the fourth tap for the programmable FIR filter in Single

Channel Mode.

7.6.115 PFIR_A4 Register (Address = 0x420) [reset = 0x0]

PFIR_A4 is shown in 图7-143 and described in 表7-183.

Return to the Summary Table.

PFIR Coefficient A4

图7-143. PFIR_A4 Register

23

15

7

22

14

6

21

13

5

20

12

4

19

11

3

18

10

2

17

9

16

8

RESERVED

R/W-0x0

PFIR_A4

R/W-0x0

PFIR_A4

R/W-0x0

1

0

PFIR_A4

R/W-0x0

表7-183. PFIR_A4 Register Field Descriptions

Bit

Field

Type

R/W

Reset

Description

23:18

17:0

RESERVED

PFIR_A4

0x0

Signed, 2’s complement coefficient for the PFIR filter. This is the

fifth tap for the ADC A programmable FIR filter in Dual Channel

Mode or the fifth tap for the programmable FIR filter in Single

Channel Mode. This is the center tap of the 9-tap filter and therefore

has a resolution of 18-bits.

7.6.116 PFIR_A5 Register (Address = 0x423) [reset = 0x0]

PFIR_A5 is shown in 图7-144 and described in 表7-184.

Return to the Summary Table.

PFIR Coefficient A5

图7-144. PFIR_A5 Register

15

7

14

6

13

5

12

11

10

2

9

1

8

0

RESERVED

R/W-0x0

PFIR_A5

R/W-0x0

4

3

PFIR_A5

R/W-0x0

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表7-184. PFIR_A5 Register Field Descriptions

Bit

15:12

11:0

Field

Type

R/W

Reset

Description

RESERVED

PFIR_A5

0x0

Signed, 2’s complement coefficient for the PFIR filter. This is the

sixth tap for the ADC A programmable FIR filter in Dual Channel

Mode or the sixth tap for the programmable FIR filter in Single

Channel Mode.

7.6.117 PFIR_A6 Register (Address = 0x425) [reset = 0x0]

PFIR_A6 is shown in 图7-145 and described in 表7-185.

Return to the Summary Table.

PFIR Coefficient A6

图7-145. PFIR_A6 Register

15

7

14

6

13

5

12

11

10

2

9

1

8

0

RESERVED

R/W-0x0

PFIR_A6

R/W-0x0

4

3

PFIR_A6

R/W-0x0

表7-185. PFIR_A6 Register Field Descriptions

Bit

Field

Type

R/W

Reset

Description

15:12

11:0

RESERVED

PFIR_A6

0x0

Signed, 2’s complement coefficient for the PFIR filter. This is the

seventh tap for the ADC A programmable FIR filter in Dual Channel

Mode or the seventh tap for the programmable FIR filter in Single

Channel Mode.

7.6.118 PFIR_A7 Register (Address = 0x427) [reset = 0x0]

PFIR_A7 is shown in 图7-146 and described in 表7-186.

Return to the Summary Table.

PFIR Coefficient A7

图7-146. PFIR_A7 Register

15

7

14

6

13

5

12

11

10

2

9

1

8

0

RESERVED

R/W-0x0

PFIR_A7

R/W-0x0

4

3

PFIR_A7

R/W-0x0

表7-186. PFIR_A7 Register Field Descriptions

Bit

15:12

Field

RESERVED

Type

Reset

Description

R/W

0x0

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表7-186. PFIR_A7 Register Field Descriptions (continued)

Bit

Field

PFIR_A7

Type

Reset

Description

11:0

R/W

0x0

Signed, 2’s complement coefficient for the PFIR filter. This is the

eighth tap for the ADC A programmable FIR filter in Dual Channel

Mode or the eighth tap for the programmable FIR filter in Single

Channel Mode.

7.6.119 PFIR_A8 Register (Address = 0x429) [reset = 0x0]

PFIR_A8 is shown in 图7-147 and described in 表7-187.

Return to the Summary Table.

PFIR Coefficient A8

图7-147. PFIR_A8 Register

15

7

14

6

13

5

12

11

10

2

9

1

8

0

RESERVED

R/W-0x0

PFIR_A8

R/W-0x0

4

3

PFIR_A8

R/W-0x0

表7-187. PFIR_A8 Register Field Descriptions

Bit

Field

Type

R/W

Reset

Description

15:12

11:0

RESERVED

PFIR_A8

0x0

Signed, 2’s complement coefficient for the PFIR filter. This is the

ninth tap for the ADC A programmable FIR filter in Dual Channel

Mode or the ninth tap for the programmable FIR filter in Single

Channel Mode.

7.6.120 PFIR_B0 Register (Address = 0x448) [reset = 0x0]

PFIR_B0 is shown in 图7-148 and described in 表7-188.

Return to the Summary Table.

PFIR Coefficient B0

图7-148. PFIR_B0 Register

15

7

14

6

13

5

12

11

10

2

9

1

8

0

RESERVED

R/W-0x0

PFIR_B0

R/W-0x0

4

3

PFIR_B0

R/W-0x0

表7-188. PFIR_B0 Register Field Descriptions

Bit

15:12

Field

RESERVED

Type

Reset

Description

R/W

0x0

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表7-188. PFIR_B0 Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

11:0

PFIR_B0

R/W

0x0

Signed, 2’s complement coefficient for the PFIR filter. This is the

first tap for the ADC B programmable FIR filter in Dual Channel

Mode.

7.6.121 PFIR_B1 Register (Address = 0x44A) [reset = 0x0]

PFIR_B1 is shown in 图7-149 and described in 表7-189.

Return to the Summary Table.

PFIR Coefficient B1

图7-149. PFIR_B1 Register

15

7

14

6

13

5

12

11

10

2

9

1

8

0

RESERVED

R/W-0x0

PFIR_B1

R/W-0x0

4

3

PFIR_B1

R/W-0x0

表7-189. PFIR_B1 Register Field Descriptions

Bit

Field

Type

R/W

Reset

Description

15:12

11:0

RESERVED

PFIR_B1

0x0

Signed, 2’s complement coefficient for the PFIR filter. This is the

second tap for the ADC B programmable FIR filter in Dual Channel

Mode.

7.6.122 PFIR_B2 Register (Address = 0x44C) [reset = 0x0]

PFIR_B2 is shown in 图7-150 and described in 表7-190.

Return to the Summary Table.

PFIR Coefficient B2

图7-150. PFIR_B2 Register

15

7

14

6

13

5

12

11

10

2

9

1

8

0

RESERVED

R/W-0x0

PFIR_AB2

R/W-0x0

4

3

PFIR_AB2

R/W-0x0

表7-190. PFIR_B2 Register Field Descriptions

Bit

15:12

Field

RESERVED

Type

Reset

Description

R/W

0x0

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表7-190. PFIR_B2 Register Field Descriptions (continued)

Bit

Field

PFIR_AB2

Type

Reset

Description

11:0

R/W

0x0

Signed, 2’s complement coefficient for the PFIR filter. This is the

third tap for the ADC B programmable FIR filter in Dual Channel

Mode.

7.6.123 PFIR_B3 Register (Address = 0x44E) [reset = 0x0]

PFIR_B3 is shown in 图7-151 and described in 表7-191.

Return to the Summary Table.

PFIR Coefficient B3

图7-151. PFIR_B3 Register

15

7

14

6

13

5

12

11

10

2

9

1

8

0

RESERVED

R/W-0x0

PFIR_B3

R/W-0x0

4

3

PFIR_B3

R/W-0x0

表7-191. PFIR_B3 Register Field Descriptions

Bit

Field

Type

R/W

Reset

Description

15:12

11:0

RESERVED

PFIR_B3

0x0

Signed, 2’s complement coefficient for the PFIR filter. This is the

fourth tap for the ADC B programmable FIR filter in Dual Channel

Mode.

7.6.124 PFIR_B4 Register (Address = 0x450) [reset = 0x0]

PFIR_B4 is shown in 图7-152 and described in 表7-192.

Return to the Summary Table.

PFIR Coefficient B4

图7-152. PFIR_B4 Register

23

15

7

22

14

6

21

13

5

20

12

4

19

11

3

18

10

2

17

9

16

8

RESERVED

R/W-0x0

PFIR_B4

R/W-0x0

PFIR_B4

R/W-0x0

1

0

PFIR_B4

R/W-0x0

表7-192. PFIR_B4 Register Field Descriptions

Bit

23:18

Field

RESERVED

Type

Reset

Description

R/W

0x0

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表7-192. PFIR_B4 Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

17:0

PFIR_B4

R/W

0x0

Signed, 2’s complement coefficient for the PFIR filter. This is the

fifth tap for the ADC B programmable FIR filter in Dual Channel

Mode. This is the center tap of the 9-tap filter and therefore has a

resolution of 18-bits.

7.6.125 PFIR_B5 Register (Address = 0x453) [reset = 0x0]

PFIR_B5 is shown in 图7-153 and described in 表7-193.

Return to the Summary Table.

PFIR Coefficient B5

图7-153. PFIR_B5 Register

15

7

14

6

13

5

12

11

10

2

9

1

8

0

RESERVED

R/W-0x0

PFIR_B5

R/W-0x0

4

3

PFIR_B5

R/W-0x0

表7-193. PFIR_B5 Register Field Descriptions

Bit

Field

Type

R/W

Reset

Description

15:12

11:0

RESERVED

PFIR_B5

0x0

Signed, 2’s complement coefficient for the PFIR filter. This is the

sixth tap for the ADC B programmable FIR filter in Dual Channel

Mode.

7.6.126 PFIR_B6 Register (Address = 0x455) [reset = 0x0]

PFIR_B6 is shown in 图7-154 and described in 表7-194.

Return to the Summary Table.

PFIR Coefficient B6

图7-154. PFIR_B6 Register

15

7

14

6

13

5

12

11

10

2

9

1

8

0

RESERVED

R/W-0x0

PFIR_B6

R/W-0x0

4

3

PFIR_B6

R/W-0x0

表7-194. PFIR_B6 Register Field Descriptions

Bit

15:12

Field

RESERVED

Type

Reset

Description

R/W

0x0

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表7-194. PFIR_B6 Register Field Descriptions (continued)

Bit

Field

PFIR_B6

Type

Reset

Description

11:0

R/W

0x0

Signed, 2’s complement coefficient for the PFIR filter. This is the

seventh tap for the ADC B programmable FIR filter in Dual Channel

Mode.

7.6.127 PFIR_B7 Register (Address = 0x457) [reset = 0x0]

PFIR_B7 is shown in 图7-155 and described in 表7-195.

Return to the Summary Table.

PFIR Coefficient B7

图7-155. PFIR_B7 Register

15

7

14

6

13

5

12

11

10

2

9

1

8

0

RESERVED

R/W-0x0

PFIR_B7

R/W-0x0

4

3

PFIR_B7

R/W-0x0

表7-195. PFIR_B7 Register Field Descriptions

Bit

Field

Type

R/W

Reset

Description

15:12

11:0

RESERVED

PFIR_B7

0x0

Signed, 2’s complement coefficient for the PFIR filter. This is the

eighth tap for the ADC B programmable FIR filter in Dual Channel

Mode.

7.6.128 PFIR_B8 Register (Address = 0x459) [reset = 0x0]

PFIR_B8 is shown in 图7-156 and described in 表7-196.

Return to the Summary Table.

PFIR Coefficient B8

图7-156. PFIR_B8 Register

15

7

14

6

13

5

12

11

10

2

9

1

8

0

RESERVED

R/W-0x0

PFIR_B8

R/W-0x0

4

3

PFIR_B8

R/W-0x0

表7-196. PFIR_B8 Register Field Descriptions

Bit

15:12

Field

RESERVED

Type

Reset

Description

R/W

0x0

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表7-196. PFIR_B8 Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

11:0

PFIR_B8

R/W

0x0

Signed, 2’s complement coefficient for the PFIR filter. This is the

ninth tap for the ADC B programmable FIR filter in Dual Channel

Mode.

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8 Application Information Disclaimer

备注

Information in the following applications sections is not part of the TI component specification, and TI

does not warrant its accuracy or completeness. TI’s customers are responsible for determining

suitability of components for their purposes, as well as validating and testing their design

implementation to confirm system functionality.

8.1 Application Information

ADC12DJ5200SE can be used in a wide range of applications including radar, satellite communications, test

equipment (communications testers), and software-defined radios (SDRs). The wide input bandwidth enables

direct RF sampling to at least 8 GHz and the high sampling rate allows signal bandwidths of greater than 5 GHz.

The Typical Applications section describes two configurations that meet the needs of a number of these

applications.

8.2 Typical Applications

8.2.1 Wideband RF Sampling Receiver

This section demonstrates the use of ADC12DJ5200SE as a wideband RF sampling receiver. The solution is

flexible and can be used as either a 2-channel receiver (such as a diversity receiver) or as a single channel

receiver allowing double the signal bandwidth. The ADC is driven by single-ended RF amplifiers connected

through an anti-alias filter to the ADC input. The device includes digital down-converters (DDCs) in both single-

channel and dual-channel modes to mix the desired frequency band to baseband and down-sample the data to

reduce the interface rate. The block diagram for the wideband RF sampling receiver is shown in 图 8-1 with the

device is configured in single-channel mode for maximum signal bandwidth.

Up to 16 lanes

JESD204C

LNA

LNA An -Alias BPF

ADC

(Interleaved)

JESD

204C

DDC

SYNC~

JESD

204C

FPGA or ASIC

Clocking

Subsystem

User Control

Logic

SPI

Device

Clock

LMK04832

÷

LMX

2594

10 MHz

Reference

SYSREF

N÷

R÷

÷

Device Clock

SYSREF

图8-1. Typical Configuration for Wideband RF Sampling

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8.2.1.1 Design Requirements

8.2.1.1.1 Input Signal Path

Use appropriate band-limiting filters to reject unwanted frequencies in the input signal path.

Drivers must be selected to provide any needed signal gain and that have the necessary bandwidth capabilities.

8.2.1.1.2 Clocking

The ADC12DJ5200SE clock inputs must be AC-coupled to the device for rated performance. The clock source

must have extremely low jitter (integrated phase noise) to enable rated performance. Recommended clock

synthesizers include LMX2594 and LMX2572.

The JESD204C data converter system (ADC plus logic device) requires additional SYSREF and device clocks.

LMK04832, LMK04828, LMK04826, and LMK04821 devices are suitable to generate these clocks. Depending

on the ADC clock frequency and jitter requirements, this device can also be used as the system clock

synthesizer or as a device clock and SYSREF distribution device when multiple ADC12DJ5200SE devices are

used in a system. For clock frequencies higher than 3.2 GHz, LMX2594 and LMX2572 can supply both the

device clock and SYSREF from a single device as demonstrated in 图8-1.

English Data Sheet: SLVSGH5

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8.2.1.2 Application Curves

The ADC12DJ5200SE can be used to digitize frequencies between ~ 2 and 6 GHz. 图8-2 to 图8-4 show device

output spectra at various input frequencies with 10.4 GSPS and DES with JMODE 1.

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

0

1000

2000

3000

4000

5000

0

1000

2000

3000

4000

5000

Frequency (MHz)

图8-2. FFT for 2397 MHz Input Signal, 10.4 GSPS,

图8-3. FFT for 4197 MHz Input Signal, 10.4 GSPS,

JMODE1

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

0

1000

2000

3000

4000

5000

Frequency (MHz)

图8-4. FFT for 5597 MHz Input Signal, 10.4 GSPS, JMODE1

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8.3 Initialization Set Up

The device and JESD204C interface require a specific startup and alignment sequence. The order of that

sequence is listed in the following steps.

1. Power-up or reset the device.

2. Apply a stable device CLK signal at the desired frequency.

3. Perform a software reset by toggling SOFT_RESET to 1. Wait at least 1 µs before continuing.

4. Program JESD_EN = 0 to stop the JESD204C state machine and allow setting changes.

5. Program CAL_EN = 0 to stop the calibration state machine and allow setting changes.

6. Program the desired JMODE.

7. Program the desired KM1 value. KM1 = K–1.

8. Program SYNC_SEL as needed. Choose SYNCSE or timestamp differential inputs.

9. Configure device calibration settings as desired. Select foreground or background calibration modes and

offset calibration as needed.

10. Program CAL_EN = 1 to enable the calibration state machine.

11. Enable overrange via OVR_EN and adjust settings if desired.

12. Program JESD_EN = 1 to re-start the JESD204C state machine and allow the link to restart.

13. The JESD204C interface operates in response to the applied SYNC signal from the receiver.

14. Program CAL_SOFT_TRIG = 0.

15. Program CAL_SOFT_TRIG = 1 to initiate a calibration.

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8.4 Power Supply Recommendations

The device requires two different power-supply voltages. 1.9-V DC is required for the VA19 power bus and 1.1-V

DC is required for the VA11 and VD11 power buses. The power-supply voltages must be low noise and provide

the needed current to achieve rated device performance. There are two recommended power supply

architectures:

1. Step down using high-efficiency switching converters, followed by a second stage of regulation to provide

switching noise reduction and improved voltage accuracy.

2. Directly step down the final ADC supply voltage using high-efficiency switching converters. This approach

provides the best efficiency, but care must be taken for switching noise to be minimized to prevent degraded

ADC performance. This approach is best described in the following application note: Powering Sensitive

ADC Designs with the TPS62913 Low-Ripple and Low-Noise Buck Converter.

TI WEBENCH^®Power Designer can be used to select and design the individual power supply elements needed:

see the WEBENCH® Power Designer

• Decouple all power supply rails and bus voltages as they come onto the system board and near/at the ADC

itself. Typically, one decoupling capacitor per power supply pin is sufficent unless specified in the datasheet

or EVM assembly.

• Remember that approximately 20 dB/decade noise suppression is gained for each additional filtering stage.

• Decouple for both high and low frequencies, which might require multiple capacitor values.

• Series ferrite beads are commonly used at the power plain entry point. This should be done for each

individual supply voltage on the system board whether it comes from an LDO or a switching regulator.

• For added capacitance, use tightly stacked power and ground plane pairs (≤4 mil spacing) this adds inherent

high-frequency (>500MHz) decoupling to the PCB design.

• Keep supplies away from sensitive analog circuitry such as the front-end RF stage of the ADC and high-

speed clocking & digital circuits if possible.

• Some switcher regulator circuitry/components could be located on the opposite side of the PCB for added

isolation.

• Follow the IC manufacture recommendations; if they are not directly stated in the application note or data

sheet, then study the evaluation board. These are great vehicles to learn from. Applying these points above

can help provide a solid power supply design yielding datasheet performance in many applications.

Each application will have different tolerances for noise on the supply voltage so understanding these trades is

best described in the following two application notes for more details:

1. Clutter-free power supplies for RF converters in radar applications (Part 1)

2. Clutter-free power supplies for RF converters in radar applications (Part 2)

Also refer to both 图8-5 and 图8-6 to illustrate a few different approaches.

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+12V, 4A

+1.4V

Ext PWR

SUPPLY

SW SUPPLY

TPS62913

LDO

TPS7A8400

FB

VA11, +1.1V

10u 0.1u

+2.2V

SW SUPPLY

TPS62913

FB

LDO

TPS7A8400

VA19, +1.9V

VDDL19, +1.9V

10u 0.1u

SW SUPPLY

TPS62913

FB

VD11, +1.1V

10u 0.1u

+3.6V

SW SUPPLY

TPS62913

FB

LDO

TPS7A8400

VCLK, +3.3V

VLMK, +3.3V

VDDD33, +3.3V

10u 0.1u

FB = ferrite bead filter.

图8-5. LDO Linear Regulator Approach Example

+12V, 4A

FB

Ext PWR

SUPPLY

Switcher

TPS62913

VA11, +1.1V

VA19, +1.9V

10u 0.1u

FB

Switcher

TPS62913

VDDL19, +1.9V

VD11, +1.1V

FB

Switcher

TPS62913

Switcher

TPS62913

FB

VCLK, +3.3V

FB

VLMK, +3.3V

VDDD33, +3.3V

FB = ferrite bead filter.

图8-6. Switcher-Only Approach Example

8.4.1 Power Sequencing

The voltage regulators must be sequenced using the power-good outputs and enable inputs to be sure the Vx11

regulator is enabled after the VA19 supply is good. Similarly, as soon as the VA19 supply drops out of regulation

on power-down, the Vx11 regulator is disabled.

The general requirement for the ADC is that VA19 ≥Vx11 during power-up, operation, and power-down.

TI also recommends that VA11 and VD11 are derived from a common 1.1-V regulator. This recommendation

makes sure that all 1.1-V blocks are at the same voltage, and no sequencing problems exist between these

supplies. Also use ferrite bead filters to isolate any noise on the VA11 and VD11 buses from affecting each other.

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8.5 Layout

8.5.1 Layout Guidelines

There are many critical signal connections that require specific care and attention during PC board design:

1. Analog input signals

2. CLK and SYSREF

3. JESD204C data outputs

4. Power connections

5. Power and grounding strategy

In general, there are many considerations to take note of when developing a high-speed PCB design. Here are a

few recommendations to follow for any high-speed PCB design:

1. Route using loosely coupled 100-Ωdifferential traces when possible on the digital outputs. This routing

minimizes impact of corners and length-matching serpentines on pair impedance.

2. Provide adequate pair-to-pair spacing to minimize crosstalk, especially with loosely coupled differential

traces. Tightly coupled differential traces may be used to reduce self-radiated noise or to improve

neighboring trace noise immunity when adequate spacing cannot be provided.

3. Provide adequate ground plane pour spacing to minimize coupling with the high-speed traces. Any ground

plane pour must have sufficient via connections to the main ground plane of the board. Do not use floating or

poorly connected ground pours.

4. Use smoothly radiused corners and avoid 45- or 90-degree bends to reduce impedance mismatches on all

high-speed inputs/outputs for both analog and digital signal traces.

5. Incorporate any ground plane cutouts necessary at component landing pads, ie –SMA connectors, baluns,

etc., to avoid impedance discontinuities at these locations. Cut-outs below these landing pads on one or

multiple ground planes to achieve a pad size or stackup height that achieves the needed 50 Ω, single-ended

impedance. See 图8-8.

6. Avoid routing traces near irregularities in the reference ground planes. Irregularities include cuts in the

ground plane or ground plane clearances associated with power and signal vias and through-hole

component leads.

7. Provide symmetrically located ground tie stitching vias adjacent to any high-speed signal at an appropriate

spacing as determined by the maximum frequency the trace will transport (λ/4). See 图8-7 and 图8-9.

8. When high-speed signals must transition to another layer using vias, transition as far through the board as

possible (top to bottom is best case) to minimize via stubs on top or bottom of the vias. If layer selection is

not flexible, use back-drilled or buried, blind vias to eliminate stubs. Always place two ground vias (“return

vias”) close to critical high-speed signal trace via when transitioning between layers to provide a nearby

ground return path.

9. Pay particular attention to potential coupling between JESD204x data output routing and the analog input

routing. Switching noise from the JESD204x outputs can couple into the analog input traces and show up as

wideband noise due to the high input bandwidth of the ADC. Route the JESD204x data outputs on a

separate layer, if possible, from the ADC input traces to avoid noise coupling (not shown in the Layout

Example section).

10. Keep in mind, a reduction in the clock amplitude may degrade ADC noise performance, make sure the clock

signal has adequate drive strength, especially at high input frequencies. To help avoid this, keep the clock

source close to the ADC if using a passive balun to drive or interface with the sampling clock pins of the

converter (as shown in the Layout Example section). If trace routes are longer than a few inches it might be

necessary to implement impedance matching at the ADC’s sampling clock input pins.

In addition, TI recommends the following PCB fabrication considerations for high-speed PCB designs:

1. Use high quality dielectric materials for any critical signal layers within the PCB stack-up. Typically, the top

and bottom layers are the most critical and more board houses can implement a mix of high and standard

quality dielectrics, also known as a hybrid stack-up.

2. Use multiple power layers if necessary to provide a robust power delivery system to the converter.

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3. Use multiple ground, power, ground layer stacks within the PCB to develop high frequency decoupling within

the PCB itself, it is recommended these layers are 4mils or less.

4. Use a solid ground plane, do not split or “slot”the ground plane to create an analog vs. digital barrier or

divider. This typically causes more harm than good.

8.5.2 Layout Example

图8-7 to provide examples of the critical traces routed on the device evaluation module (EVM).

图8-7. Single Ended Input Path

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图8-8. Example of Ground Cut-outs on Top Signal Pad

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图8-9. Example of Analog Signal Via Stitching

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9 Device and Documentation Support

9.1 Device Support

9.1.1 Development Support

9.2 Documentation Support

9.2.1 Related Documentation

For related documentation see the following:

• JESD204B multi-device synchronization: Breaking down the requirements

• Synchronizing multi-channel data converter DDC and NCO features for RF systems reference design

• Multi-Channel JESD204B 15 GHz Clocking Reference Design for DSO, Radar and 5G Wireless Testers

• Flexible 3.2 GSPS Multi-Channel AFE Reference Design for DSOs, RADAR, and 5G Wireless Test Systems

• Low noise power-supply reference design maximizing performance in 12.8 GSPS data acquisition systems

• Direct RF-Sampling Radar Receiver for L-, S-, C-, and X-Band Using ADC12DJ3200 Reference Design

• LMX2594 Multiple PLL Reference Design

• LMX2594 15-GHz Wideband PLLatinum™ RF Synthesizer With Phase Synchronization and JESD204B

• LMX2572 6.4-GHz Low Power Wideband RF Synthesizer With Phase Synchronization and JESD204B

• LMK04832 Ultra Low-Noise JESD204B Compliant Clock Jitter Cleaner With Dual Loop PLLs

• LMK0482x Ultra Low-Noise JESD204B Compliant Clock Jitter Cleaner with Dual Loop PLLs

• LMK61E2 Ultra-Low Jitter Programmable Oscillator With Internal EEPROM

• LMH5401 8-GHz, Low-Noise, Low-Power, Fully-Differential Amplifier

• LMH6401 DC to 4.5 GHz, Fully-Differential, Digital Variable-Gain Amplifier

• TPSM84424 4.5-V to 17-V Input, 0.6-V to 10-V Output, 4-A Power Module

• TPS7A470x 36-V, 1-A, 4-µVRMS, RF LDO Voltage Regulator

• TPS7A83A 2-A, High-Accuracy (0.75%), Low-Noise (4.4 µVRMS) LDO Regulator

• TPS7A84 High-Current (3 A), High-Accuracy (1%), Low-Noise (4.4 µVRMS), LDO Voltage Regulator

• DAC8560 16-Bit, Ultra-Low Glitch, Voltage Output Digital-to-Analog Converter With 2.5-V, 2-ppm/°C

Reference

• LM95233 Dual Remote Diode and Local Temperature Sensor with SMBus Interface and TruTherm™

• TMP461 High-Accuracy Remote and Local Temperature Sensor with Pin-Programmable Bus Address

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9.3 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper

right corner, click on Alert me to register and receive a weekly digest of any product information that has

changed. For change details, review the revision history included in any revised document.

9.4 Support Resources

9.5 Trademarks

WEBENCH^®is a registered trademark of Texas Instruments.

所有商标均为其各自所有者的财产。

10 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	ADC12DJ5200SE
厂家：	TEXAS INSTRUMENTS
描述：	具有双通道 5.2GSPS 或单通道 10.4GSPS 的单端输入射频采样 12 位 ADC 射频
文件：	总178页 (文件大小：6008K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ADC12DJ5200SE [TI]

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