ADC12J2700NKER [TI]
12 位、2.7GSPS、射频采样模数转换器 (ADC) | NKE | 68 | -40 to 85;
| 型号： | ADC12J2700NKER |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 12 位、2.7GSPS、射频采样模数转换器 (ADC) | NKE | 68 | -40 to 85 射频 转换器 模数转换器 |
| 文件： | 总101页 (文件大小：2371K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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ADC12J1600, ADC12J2700
ZHCSCX0D –JANUARY 2014–REVISED OCTOBER 2017
具有集成 DDC 的 ADC12Jxx00 12 位 1.6 或 2.7GSPS ADC
1 特性
2 应用
1
•
出色的噪声和线性性能，最高可达 FIN = 3GHz 以
上
•
•
•
•
•
•
•
•
无线基础设施
RF 采样软件定义无线电
•
•
•
•
可配置数字下变频器 (DDC)
抽取因数范围为 4 至 32（复杂基带输出）
旁路模式适用于整个奈奎斯特输出带宽
宽带微波回程
军用通信
通信情报
在 4x 抽取率和 2700MSPS 条件下，
可用输出带宽为 540MHz
雷达和激光雷达
电缆数据服务接口规范 (DOCSIS)/电缆基础设施
测试和测量
•
•
•
在 4x 抽取率和 1600MSPS 条件下，
可用输出带宽为 320MHz
在 32x 抽取率和 2700MSPS 条件下，
可用输出带宽为 67.5MHz
3 说明
ADC12J1600 和 ADC12J2700 器件为宽带采样和数字
调谐器件。德州仪器 (TI) 的千兆次采样模数转换器
(ADC) 技术支持采用射频直接对大范围频谱采样。集
成 DDC（数字下变频器）可进行数字滤波和下变频转
换。所选频率块适用于 JESD204B 串行接口。数据以
基带 15 位复数信息形式输出，以减轻下游处理压力。
根据数字下变频器 (DDC) 抽取率和链接输出率设置，
该数据将通过串行接口的 1 至 5 通道输出。
在 32x 抽取率和 1600MSPS 条件下，
可用输出带宽为 40MHz
•
•
•
•
•
低引脚数目 JESD204B 子类 1 接口
自动优化输出通道计数
嵌入式低延迟信号范围指示
低功耗
主要规格：
–
–
–
–
–
–
–
最大采样率：1600 或 2700MSPS
最小采样率：1000MSPS
DDC 旁路模式还支持输出全速率 12 位原始 ADC 数
据。此运行模式需要 8 个串行输出通道。
DDC 输出字大小：15 位复数（共 30 位）
旁路输出字大小：12 位偏移二进制数
噪底：–147.3dBFS/Hz (ADC12J2700)
噪底：–145dBFS/Hz (ADC12J1600)
ADC12J1600 和 ADC12J2700 器件采用 68 引脚超薄
四方扁平无引线 (VQFN) 封装。该器件的工业环境运
行温度范围为 –40°C ≤ TA ≤ 85°C。
三阶互调失真 (IMD3)：−64dBc（−13dBFS
时，FIN = 2140MHz ± 30MHz）
器件信息(1)
器件型号
ADC12J1600
ADC12J2700
封装
VQFN (68)
VQFN (68)
封装尺寸（标称值）
10.00mm x 10.00mm
10.00mm x 10.00mm
–
–
–
–
全功率带宽 (FPBW) (–3dB)：3.2GHz））
峰值噪声功率比 (NPR)：46dB
电源电压：1.9V 和 1.2V
功耗
(1) 如需了解所有可用封装，请见数据表末尾的可订购产品附录。
–
–
–
旁路 (2700MSPS)：1.8W
旁路 (1600MSPS)：1.6W
断电模式：< 50mW
旁路 — 频谱响应
ƒS = 2.7GHz，FIN = 1897MHz（–1dBFS 时）
0
-20
-40
-60
-80
-100
0
225
450
675
900
1125
1350
Frequency (MHz)
C001
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLAS969
ADC12J1600, ADC12J2700
ZHCSCX0D –JANUARY 2014–REVISED OCTOBER 2017
www.ti.com.cn
目录
7.6 Register Map........................................................... 57
Application and Implementation ........................ 82
8.1 Application Information............................................ 82
8.2 Typical Application ................................................. 82
8.3 Initialization Set-Up ................................................. 86
8.4 Dos and Don'ts........................................................ 86
Power Supply Recommendations...................... 87
9.1 Supply Voltage........................................................ 87
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 8
6.1 Absolute Maximum Ratings ...................................... 8
6.2 ESD Ratings.............................................................. 8
6.3 Recommended Operating Conditions....................... 9
6.4 Thermal Information.................................................. 9
6.5 Electrical Characteristics........................................... 9
6.6 Timing Requirements.............................................. 16
6.7 Internal Characteristics ........................................... 18
6.8 Switching Characteristics........................................ 19
6.9 Typical Characteristics............................................ 20
Detailed Description ............................................ 30
7.1 Overview ................................................................. 30
7.2 Functional Block Diagram ....................................... 30
7.3 Feature Description................................................. 31
7.4 Device Functional Modes........................................ 49
7.5 Programming........................................................... 55
8
9
10 Layout................................................................... 87
10.1 Layout Guidelines ................................................. 87
10.2 Layout Example .................................................... 88
10.3 Thermal Management........................................... 90
11 器件和文档支持 ..................................................... 90
11.1 器件支持................................................................ 90
11.2 文档支持................................................................ 91
11.3 相关链接................................................................ 91
11.4 社区资源................................................................ 92
11.5 商标....................................................................... 92
11.6 静电放电警告......................................................... 92
11.7 Glossary................................................................ 92
12 机械、封装和可订购信息....................................... 92
7
4 修订历史记录
Changes from Revision C (July 2015) to Revision D
Page
•
•
•
Changed reset value of address 0x006 from 0x03 to 0x13 in Memory Map table............................................................... 57
Changed reset value of address 0x006 from 0x03 to 0x13 in Standard SPI-3.0 Registers table........................................ 60
Changed 0x03 to 0x13 in reset value and description of bits 7-0 and changed 0000 0011 to 0001 0011 in Chip
Version Register section....................................................................................................................................................... 61
Changes from Revision B (September 2014) to Revision C
Page
•
•
•
Added additional voltage difference parameters to the Absolute Maximum Ratings table .................................................... 8
Added junction temperature to the Absolute Maximum Ratings table ................................................................................... 8
Added common mode voltage parameter to the Recommended Operating Conditions table. Changed CLK to
SYSREF, and ~SYNC ........................................................................................................................................................... 9
•
•
•
Changed some of the maximum interleaving offset values for both devices to tighten the levels ...................................... 10
Deleted the Differential Analog Input Connection image in The Analog Inputs section ...................................................... 31
Added note about offset adjust in Background Calibration Mode to the Offset Adjust section and I/O offset register
tables .................................................................................................................................................................................... 35
•
•
Added the Calibration Cycle Timing for Different Calibration Modes and Options table in the Timing Calibration
Mode section ........................................................................................................................................................................ 50
Changed 0x004-0x005 to RESERVED in the Standard SPI-3.0 Registers summary table................................................. 60
Changes from Revision A (February 2014) to Revision B
Page
•
已更改 器件状态，从产品预览改为量产数据 .......................................................................................................................... 1
2
Copyright © 2014–2017, Texas Instruments Incorporated
ADC12J1600, ADC12J2700
www.ti.com.cn
ZHCSCX0D –JANUARY 2014–REVISED OCTOBER 2017
5 Pin Configuration and Functions
NKE Package
68-Pin VQFN With Thermal Pad
Top View
1
2
3
4
5
6
7
51
RBIAS+
RBIASœ
VCMO
VA19
DS6+/NCO_1b
50
DS6œ/NCO_1a
49
VD12
48
DS5+/NCO_0b
47
VNEG
VA12
DS5œ/NCO_0a
46
VD12
45
VA19
DS4+
44
8
VIN+
DS4œ
9
43
VINœ
VD12
10
11
12
13
14
15
16
17
42
VA19
DS3+
41
VA12
DS3œ
40
VNEG
VA19
VD12
39
DS2+
38
VA12
DS2œ
37
DEVCLK+
DEVCLKœ
VA12
VD12
36
DS1+
35
DS1œ
DNC = Make no external connection
Copyright © 2014–2017, Texas Instruments Incorporated
3
ADC12J1600, ADC12J2700
ZHCSCX0D –JANUARY 2014–REVISED OCTOBER 2017
www.ti.com.cn
Pin Functions
PIN
EQUIVALENT CIRCUIT
TYPE
DESCRIPTION
NAME
NO.
ANALOG
RBIAS+
VA19
1
External Bias Resistor Connections
External bias resistor terminals. A 3.3 kΩ (±0.1%) resistor should be connected
between RBIAS+ and RBIAS–. The RBIAS resistor is used as a reference for
internal circuits which affect the linearity of the converter. The value and precision
of this resistor should not be compromised. These pins must be isolated from all
other signals and grounds.
VBIAS
I/O
RBIAS–
2
GND
TDIODE–
TDIODE+
63
64
Tdiode+
Temperature Diode
These pins are the positive (anode) and negative (cathode) diode connections for
die temperature measurements. Leave these pins unconnected if they are not
used. See the Built-In Temperature Monitor Diode section for more details.
Passive
Tdiodeœ
VA19
Bandgap Output Voltage
This pin is capable of sourcing or sinking 100 μA and can drive a load up to 80 pF.
Leave this pin unconnected if it is not used in the application. See the The
Reference Voltage section for more details.
VBG
68
O
VCM
Common Mode Voltage
The voltage output at this pin must be the common-mode input voltage at the VIN+
and VIN– pins when DC coupling is used. This pin is capable of sourcing or sinking
100 μA and can drive a load up to 80 pF. Leave this pin unconnected if it is not
used in the application.
VCMO
VIN+
3
8
O
GND
VA19
VIN+
To T&H+
LPEAK
GND
Signal Input
50 Ω
20 kΩ
The differential full-scale input range is determined by the full-scale voltage adjust
register. An internal peaking inductor (LPEAK) of 5 nH is included for parasitic
compensation.
VCM
I
VIN–
9
50 Ω
VA19
GND
LPEAK
VINœ
To T&Hœ
4
Copyright © 2014–2017, Texas Instruments Incorporated
ADC12J1600, ADC12J2700
www.ti.com.cn
ZHCSCX0D –JANUARY 2014–REVISED OCTOBER 2017
Pin Functions (continued)
PIN
NAME
EQUIVALENT CIRCUIT
TYPE
DESCRIPTION
NO.
DATA
DS0–
32
33
35
36
38
39
41
42
44
45
47
48
50
51
53
VD12
VA19
DS0+
DS1–
DS1+
+
50 ꢀ
50 ꢀ
Data
DS2–
CML These pins are the high-speed serialized-data outputs with user-configurable
pre-emphasis. These outputs must always be terminated with a 100-Ω differential
resistor at the receiver.
O
œ
DS2+
DS3–
DS3+
GND
DS4–
DS4+
DS5–/NCO_0
DS5+/NCO_0
DS6−/NCO_1
DS6+/NCO_1
DS7−/NCO_2
VA19
Data
VD12
DS5–/NCO_0,
DS5+/NCO_0,
DS6–/NCO_1,
DS6+/NCO_1,
DS7–/NCO_2 and DS7+/NCO_2: When decimation is enabled, these
pins become LVCMOS inputs and allow the host device to select the
specific NCO frequency or phase accumulator that is active. In this mode
the positive (+) and negative (–) pins should be connected together and
both driven. An acceptable alternative is to let one of the pair float while
the other pin is driven. Connect these inputs to GND if they are not used
in the application.
+
50 ꢀ
O/I
50 ꢀ
œ
OE
DS7+/NCO_2
54
GND
GROUND, RESERVED, DNC
Do Not Connect
Do not connect DNC to any circuitry, power, or ground signals.
DNC
67
—
—
VA19
Reserved
Connect to Ground or Leave Unconnected: This reserved pin is a logic input for
possible future device versions. It is recommended to connect this pin to ground.
Floating this pin is also permissible.
RSV
66
Reserved
RSV2
61
—
—
Connect to Ground Connect this reserved input pin to ground for proper operation.
GND
Ground (GND)
The exposed pad on the bottom of the package is the ground return for all supplies.
This pad must be connected with multiple vias to the printed circuit board (PCB)
ground planes to ensure proper electrical and thermal performance.
The exposed center pad on the bottom of the package must be thermally and
electrically connected (soldered) to a ground plane to ensure rated performance.
Thermal Pad
LVCMOS
VA19
OR_T0
25
26
Over-Range
O
Over-range detection status for T0 and T1 thresholds. Leave these pins
unconnected if they are not used in the application.
OR_T1
GND
Copyright © 2014–2017, Texas Instruments Incorporated
5
ADC12J1600, ADC12J2700
ZHCSCX0D –JANUARY 2014–REVISED OCTOBER 2017
www.ti.com.cn
Pin Functions (continued)
PIN
EQUIVALENT CIRCUIT
TYPE
DESCRIPTION
NAME
NO.
Serial Interface Clock
This pin functions as the serial-interface clock input which clocks the serial data in
and out. The Using the Serial Interface section describes the serial interface in
more detail.
SCLK
58
I
I
VA19
Serial Data In
SDI
57
30
59
This pin functions as the serial-interface data input. The Using the Serial Interface
section describes the serial interface in more detail.
SYNC~
This pin provides the JESD204B-required synchronizing request input. A logic-low
applied to this input initiates a lane alignment sequence. The choice of LVCMOS or
differential SYNC~ is selected through bit 6 of the configuration register 0x202h.
Connect this input to GND or VA19 if differential SYNC~ input is used.
SYNC~
SCS
I
I
GND
Serial Chip Select (active low)
This pin functions as the serial-interface chip select. The Using the Serial Interface
section describes the serial interface in more detail.
VA19
Serial Data Out
SDO
56
O
This pin functions as the serial-interface data output. The Using the Serial Interface
section describes the serial interface in more detail.
GND
DIFFERENTIAL INPUT
DEVCLK+
DEVCLK–
SYSREF+
15
16
19
Device Clock Input
The differential device clock signal must be AC coupled to these pins. The input
signal is sampled on the rising edge of CLK.
I
I
VA19
SYSREF
The differential periodic waveform on these pins synchronizes the device per
JESD204B. If JESD204B subclass 1 synchronization is not required and these
inputs are not utilized they may be left unconnected. In that case ensure
SysRef_Rcvr_En=0 and SysRef_Pr_En=0.
SYSREF–
20
22
50 ꢀ
1 kꢀ
AGND
VA19
SYNC~+/TMST+
SYNC~/TMST
V
(CM_CLK)
This differential input provides the JESD204B-required synchronizing request input.
A differential logic-low applied to these inputs initiates a lane alignment sequence.
For differential SYNC~ usage, ensure that SYNC_DIFF_PD = 0 and
SYNC_DIFFSEL = 1.
50 ꢀ
I
When the LVCMOS SYNC~ is selected these inputs can be used as the differential
TIMESTAMP input. For TMST usage, ensure that SYNC_DIFF_PD = 0,
SYNC_DIFFSEL = 0, and TIME_STAMP_EN = 1. For additional information see
the Time Stamp section.
SYNC~-/TMST–
23
AGND
These inputs may be left unconnected if they are not used for either the SYNC~ or
TIMESTAMP functions.
6
Copyright © 2014–2017, Texas Instruments Incorporated
ADC12J1600, ADC12J2700
www.ti.com.cn
ZHCSCX0D –JANUARY 2014–REVISED OCTOBER 2017
Pin Functions (continued)
PIN
NAME
EQUIVALENT CIRCUIT
TYPE
DESCRIPTION
NO.
POWER
6
11
14
17
18
21
65
4
Analog 1.2 V power supply pins
Bypass these pins to ground using one 10-µF capacitor and two 1-µF capacitors for
bulk decoupling plus one 0.1-µF capacitor per pin for individual decoupling.
VA12
—
7
10
13
24
27
60
62
28
31
34
37
40
43
46
49
52
55
5
Analog 1.9 V power supply pins
Bypass these pins to ground using one 10-µF capacitor and two 1-µF capacitors for
bulk decoupling plus one 0.1-µF capacitor per pin for individual decoupling.
VA19
—
Digital 1.2 V power supply pins
Bypass these pins to ground using one 10-µF capacitor and two 1-µF capacitors for
bulk decoupling plus one 0.1-µF capacitor per pin for individual decoupling.
VD12
—
VNEG
These pins must be decoupled to ground with a 0.1-µF ceramic capacitor near
each pin. These power input pins must be connected to the VNEG_OUT pin with a
low resistance path. The connections must be isolated from any noisy digital
signals and must also be isolated from the analog input and clock input pins.
VNEG
I
12
VNEG_OUT
The voltage on this output can range from –1V to +1V. This pin must be decoupled
to ground with a 4.7-µF, low ESL, low ESR multi-layer ceramic chip capacitor and
connected to the VNEG input pins. This voltage must be isolated from any noisy
digital signals, clocks, and the analog input.
VNEG_OUT
29
O
Copyright © 2014–2017, Texas Instruments Incorporated
7
ADC12J1600, ADC12J2700
ZHCSCX0D –JANUARY 2014–REVISED OCTOBER 2017
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
The soldering process must comply with TI's Reflow Temperature Profile specifications. Refer to www.ti.com/packaging.(1)(2)(3)
MIN
MAX
1.4
UNIT
1.2-V supply
VA12, VD12
VA19
V
Supply voltage
Voltage
1.9-V supply
2.2
1.2-V supply difference between VA12 and VD12
–200
–0.15
0
200
mV
V(VA19)
0.15
+
On any input pin (except VIN+ or VIN–)
V
On VIN+ or VIN–
|(VIN+) – (VIN–)|(4)
2
2
2
2
1
|(DEVCLK+) – (DEVCLK–)|
|(SYSREF+) – (SYSREF–)|
|(~SYNC+) – (~SYNC–)|
Voltage difference
V
On VIN+, VIN–, with proper input common mode maintained. FIN ≥ 3 GHz,
Z(SOURCE) = 100 Ω, Input_Clamp_EN = 0 or 1
11.07
14.95
20.97
On VIN+, VIN–, with proper input common mode maintained. FIN = 1 GHz,
Z(SOURCE) = 100 Ω, Input_Clamp_EN = 1
RF input power, PI
Input current
dBm
On VIN+, VIN–, with proper input common mode maintained. FIN ≤ 100 MHz,
Z(SOURCE) = 100 Ω, Input_Clamp_EN = 1
At any pin other than VIN+ or VIN–(5)
–25
–50
25
50
mA
VIN+ or VIN–
mA DC
Package(5) (sum of absolute value of all currents forced in or out, not including
power supply current)
100
mA
Junction
temperature, TJ
Power applied. Verified by High Temperature Operation Life testing to 1000
hours.
–40
–65
150
150
°C
°C
Storage temperature, Tstg
(1) Reflow temperature profiles are different for lead-free and non-lead-free packages.
(2) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(3) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
(4) The analog inputs are protected as in the following circuit. Input-voltage magnitudes beyond the Absolute Maximum Ratings may
damage this device.
VA19
To Internal
Circuitry
I/O
GND
(5) When the input voltage at any pin (other than VIN+ or VIN–) exceeds the power supply limits (that is, less than GND or greater than
VA19), the current at that pin must be limited to 25 mA. The 100-mA maximum package input current rating limits the number of pins
that can safely exceed the power supplies. This limit is not placed upon the power pins or thermal pad (GND).
6.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1)
±2000
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per JEDEC specification JESD22-C101, all
pins(2)
±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
8
Copyright © 2014–2017, Texas Instruments Incorporated
ADC12J1600, ADC12J2700
www.ti.com.cn
ZHCSCX0D –JANUARY 2014–REVISED OCTOBER 2017
6.3 Recommended Operating Conditions
All voltages are measured with respect to GND = 0 V, unless otherwise specified.
MIN
1.14
1.8
MAX
1.26
2
UNIT
1.2-V supply: VA12, VD12
VDD
Supply voltage
V
1.9-V supply: VA19
1.9 supply ≥ 1.2
Supply sequence (power-up and power-down)
V
supply
VCMI
Analog input common mode voltage
V(VCMO) – 0.15
V(VCMO) + 0.15
V
V
VIN+, VIN– voltage (maintaining common mode)
DEVCLK±, SYSREF±, ~SYNC± pin voltage range
Differential DEVCLK±, SYSREF±, ~SYNC± amplitude
0
0
V(VA19)
V(VA19)
2
V
VID(CLK)
0.4
0.64
–40
VPP
V
VCM(CLK) SYSREF±, ~SYNC± Common Mode
1.1
TA
TJ
Ambient temperature
Junction temperature
85
°C
°C
135
6.4 Thermal Information
ADC12J1x00
THERMAL METRIC(1)
NKE (VQFN)
68 PINS
19.8
UNIT
RθJA
Thermal resistance, junction-to-ambient
Thermal resistance, junction-to-case (bottom)
Characterization parameter, junction-to-board
°C/W
°C/W
°C/W
RθJCbot
ψJB
2.7
9.1
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
Unless otherwise noted, these specifications apply for V(VA12) = V(VD12) = 1.2 V, V(VA19) = 1.9 V, VIN full scale range at default
setting (725 mVPP), VIN = –1 dBFS, differential AC-coupled sinewave input clock, ƒ(DEVCLK) = 2.7 or 1.6 GHz at 0.5 VPP with
50% duty cycle, R(RBIAS) = 3.3 kΩ ±0.1%, after a foreground (FG) mode calibration with timing calibration enabled. Typical
values are at TA = 25°C.(1)(2)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DYNAMIC PERFORMANCE CHARACTERISTICS
RES
ADC core resolution
Resolution with no missing codes
12
±2
Bits
TA = 25°C
INL
Integral non-linearity
LSB
TA = TMIN to TMAX
TA = 25°C
±3
±0.25
±0.3
DNL
Differential non-linearity
Peak noise power ratio
LSB
TA = TMIN to TMAX
500-kHz tone spacing from 1 MHz to ƒS / 2−1 MHz, DDC bypass mode
25-MHz wide notch at 320 MHz
Peak NPR
IMD3
46
dB
Third-order intermodulation
distortion
F1 = 2110 MHz at −13 dBFS
F2 = 2170 MHz at −13 dBFS
–64
dBc
(1) To ensure accuracy, the VA19, VA12, and VD12 pins are required to be well bypassed. Each supply pin must be decoupled with one or
more bypass capacitors.
(2) Interleave related fixed frequency spurs at ƒS / 4 and ƒS / 2 are excluded from all SNR, SINAD, ENOB and SFDR specifications. The
magnitude of these spurs is provided separately.
Copyright © 2014–2017, Texas Instruments Incorporated
9
ADC12J1600, ADC12J2700
ZHCSCX0D –JANUARY 2014–REVISED OCTOBER 2017
www.ti.com.cn
Electrical Characteristics (continued)
Unless otherwise noted, these specifications apply for V(VA12) = V(VD12) = 1.2 V, V(VA19) = 1.9 V, VIN full scale range at default
setting (725 mVPP), VIN = –1 dBFS, differential AC-coupled sinewave input clock, ƒ(DEVCLK) = 2.7 or 1.6 GHz at 0.5 VPP with
50% duty cycle, R(RBIAS) = 3.3 kΩ ±0.1%, after a foreground (FG) mode calibration with timing calibration enabled. Typical
values are at TA = 25°C.(1)(2)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DDC BYPASS MODE, ADC12J2700, ƒ(DEVCLK) = 2.7 GHz
FIN = 350 MHz, –1 dBFS, 12-bit DDC bypass mode
TA = 25°C
55.1
54.9
Signal-to-noise ratio,
integrated across entire
Nyquist bandwidth
Input frequency-dependent
interleaving spurs included
TA = TMIN to TMAX
52.5
52.4
FIN = 600 MHz, –1 dBFS, 12-bit DDC bypass
mode
SNR
TA = 25°C, calibration = BG
TA = TMIN to TMAX, calibration = BG
54.8
dBFS
FIN = 1500 MHz, –1 dBFS, 12-bit DDC bypass mode
FIN = 2400 MHz, –1 dBFS, 12-bit DDC bypass mode
FIN = 350 MHz, –1 dBFS, 12-bit DDC bypass mode
52.5
50
55
TA = 25°C
54.8
Signal-to-noise and distortion
ratio, integrated across entire
Nyquist bandwidth
Input frequency-dependent
interleaving spurs included
TA = TMIN to TMAX
52.3
52.2
FIN = 600 MHz, –1 dBFS, 12-bit DDC bypass
mode
SINAD
ENOB
SFDR
TA = 25°C, calibration = BG
TA = TMIN to TMAX, calibration = BG
54.7
dBFS
FIN = 1500 MHz, –1 dBFS, 12-bit DDC bypass mode
FIN = 2400 MHz, –1 dBFS, 12-bit DDC bypass mode
FIN = 350 MHz, –1 dBFS, 12-bit DDC bypass mode
52.4
50
8.8
8.8
TA = 25°C
Effective number of bits,
integrated across entire
Nyquist bandwidth
Input frequency-dependent
interleaving spurs included
TA = TMIN to TMAX
8.4
8.4
FIN = 600 MHz, –1 dBFS, 12-bit DDC bypass
mode
TA = 25°C, calibration = BG
TA = TMIN to TMAX, calibration = BG
8.8
Bits
FIN = 1500 MHz, –1 dBFS, 12-bit DDC bypass mode
FIN = 2400 MHz, –1 dBFS, 12-bit DDC bypass mode
FIN = 350 MHz, –1 dBFS, 12-bit DDC bypass mode
8.4
8
66.7
71.6
TA = 25°C
TA = TMIN to TMAX
61
59
FIN = 600 MHz, –1 dBFS, 12-bit DDC bypass
mode
Spurious-free dynamic range
Input frequency-dependent
interleaving spurs included
TA = 25°C, calibration = BG
TA = TMIN to TMAX, calibration = BG
70
dBFS
FIN = 1500 MHz, –1 dBFS, 12-bit DDC bypass mode
FIN = 2400 MHz, –1 dBFS, 12-bit DDC bypass mode
65.2
58.6
–77
TA = 25°C
TA = TMIN to TMAX
–59.5
–57.5
–54.5
–53
Interleaving offset spur at ½
sampling rate
FIN = 600 MHz, –1 dBFS, 12-bit DDC bypass
mode
ƒS/2
dBFS
dBFS
dBFS
dBFS
dBFS
TA = 25°C, calibration = BG
TA = TMIN to TMAX, calibration = BG
TA = 25°C
–74
–70
–68
–78
–76
–76
–71
–77
–76
TA = TMIN to TMAX
Interleaving offset spur at ¼
sampling rate
FIN = 600 MHz, –1 dBFS, 12-bit DDC bypass
mode
ƒS/4
TA = 25°C, calibration = BG
TA = TMIN to TMAX, calibration = BG
TA = 25°C
Interleaving offset spur at ½
sampling rate – input
frequency
TA = TMIN to TMAX
–62
FIN = 600 MHz, –1 dBFS, 12-bit DDC bypass
mode
ƒS/2 – FIN
ƒS/4 + FIN
ƒS/4 – FIN
TA = 25°C, calibration = BG
TA = TMIN to TMAX, calibration = BG
TA = 25°C
–61
Interleaving offset spur at ¼
sampling rate + input
frequency
TA = TMIN to TMAX
–61
FIN = 600 MHz, –1 dBFS, 12-bit DDC bypass
mode
TA = 25°C, calibration = BG
TA = TMIN to TMAX, calibration = BG
TA = 25°C
–59
Interleaving offset spur at ¼
sampling rate – input
frequency
TA = TMIN to TMAX
–61.4
–61
FIN = 600 MHz, –1 dBFS, 12-bit DDC bypass
mode
TA = 25°C, calibration = BG
TA = TMIN to TMAX, calibration = BG
10
Copyright © 2014–2017, Texas Instruments Incorporated
ADC12J1600, ADC12J2700
www.ti.com.cn
ZHCSCX0D –JANUARY 2014–REVISED OCTOBER 2017
Electrical Characteristics (continued)
Unless otherwise noted, these specifications apply for V(VA12) = V(VD12) = 1.2 V, V(VA19) = 1.9 V, VIN full scale range at default
setting (725 mVPP), VIN = –1 dBFS, differential AC-coupled sinewave input clock, ƒ(DEVCLK) = 2.7 or 1.6 GHz at 0.5 VPP with
50% duty cycle, R(RBIAS) = 3.3 kΩ ±0.1%, after a foreground (FG) mode calibration with timing calibration enabled. Typical
values are at TA = 25°C.(1)(2)
PARAMETER
TEST CONDITIONS
MIN
TYP
–73
–70
MAX
UNIT
FIN = 350 MHz, –1 dBFS, 12-bit DDC bypass mode
TA = 25°C
TA = TMIN to TMAX
–61
–62
FIN = 600 MHz, –1 dBFS, 12-bit DDC bypass
mode
THD
Total harmonic distortion
TA = 25°C, calibration = BG
TA = TMIN to TMAX, calibration = BG
–72
dBFS
FIN = 1500 MHz, –1 dBFS, 12-bit DDC bypass mode
FIN = 2400 MHz, –1 dBFS, 12-bit DDC bypass mode
FIN = 350 MHz, –1 dBFS, 12-bit DDC bypass mode
–68
–68
–72
–79
TA = 25°C
TA = TMIN to TMAX
–62
–64
FIN = 600 MHz, –1 dBFS, 12-bit DDC bypass
mode
HD2
Second harmonic distortion
TA = 25°C, calibration = BG
TA = TMIN to TMAX, calibration = BG
–81
dBFS
FIN = 1500 MHz, –1 dBFS, 12-bit DDC bypass mode
FIN = 2400 MHz, –1 dBFS, 12-bit DDC bypass mode
FIN = 350 MHz, –1 dBFS, 12-bit DDC bypass mode
–76
–70
–72
–75
TA = 25°C
TA = TMIN to TMAX
–63
–64
FIN = 600 MHz, –1 dBFS, 12-bit DDC bypass
mode
HD3
Third harmonic distortion
TA = 25°C, calibration = BG
TA = TMIN to TMAX, calibration = BG
–81
dBFS
FIN = 1500 MHz, –1 dBFS, 12-bit DDC bypass mode
FIN = 2400 MHz, –1 dBFS, 12-bit DDC bypass mode
–70
–76
–147.3
–149.1
–146.2
–148.0
dBFS/Hz
dBm/Hz
dBFS/Hz
dBm/Hz
50-Ω AC-coupled terminated input
Noise spectral density,
average NSD across Nyquist
bandwidth
12-bit DDC bypass mode, ADC12J2700,
ƒ(DEVCLK) = 2.7 GHz
NSD
FIN = 600 MHz, –1 dBFS
DDC BYPASS MODE, ADC12J1600, ƒ(DEVCLK) = 1.6 GHz
FIN = 350 MHz, –1 dBFS, 12-bit DDC bypass mode
55.3
54.9
TA = 25°C
Signal-to-noise ratio,
integrated across entire
Nyquist bandwidth
Input frequency-dependent
interleaving spurs included
TA = TMIN to TMAX
52.3
52.2
FIN = 600 MHz, –1 dBFS, 12-bit DDC bypass
mode
SNR
TA = 25°C, calibration = BG
TA = TMIN to TMAX, calibration = BG
54.8
dBFS
dBFS
Bits
FIN = 1500 MHz, –1 dBFS, 12-bit DDC bypass mode
FIN = 2400 MHz, –1 dBFS, 12-bit DDC bypass mode
FIN = 350 MHz, –1 dBFS, 12-bit DDC bypass mode
52.5
49.8
55.2
54.8
TA = 25°C
Signal-to-noise and distortion
ratio, integrated across entire
Nyquist bandwidth
Input frequency-dependent
interleaving spurs included
TA = TMIN to TMAX
52.1
52
FIN = 600 MHz, –1 dBFS, 12-bit DDC bypass
mode
SINAD
TA = 25°C, calibration = BG
TA = TMIN to TMAX, calibration = BG
54.7
FIN = 1500 MHz, –1 dBFS, 12-bit DDC bypass mode
FIN = 2400 MHz, –1 dBFS, 12-bit DDC bypass mode
FIN = 350 MHz, –1 dBFS, 12-bit DDC bypass mode
52.4
49.7
8.9
TA = 25°C
8.8
Effective number of bits,
integrated across entire
Nyquist bandwidth
Input frequency-dependent
interleaving spurs included
TA = TMIN to TMAX
8.4
8.4
FIN = 600 MHz, –1 dBFS, 12-bit DDC bypass
mode
ENOB
TA = 25°C, calibration = BG
TA = TMIN to TMAX, calibration = BG
8.8
FIN = 1500 MHz, –1 dBFS, 12-bit DDC bypass mode
FIN = 2400 MHz, –1 dBFS, 12-bit DDC bypass mode
8.4
8
Copyright © 2014–2017, Texas Instruments Incorporated
11
ADC12J1600, ADC12J2700
ZHCSCX0D –JANUARY 2014–REVISED OCTOBER 2017
www.ti.com.cn
Electrical Characteristics (continued)
Unless otherwise noted, these specifications apply for V(VA12) = V(VD12) = 1.2 V, V(VA19) = 1.9 V, VIN full scale range at default
setting (725 mVPP), VIN = –1 dBFS, differential AC-coupled sinewave input clock, ƒ(DEVCLK) = 2.7 or 1.6 GHz at 0.5 VPP with
50% duty cycle, R(RBIAS) = 3.3 kΩ ±0.1%, after a foreground (FG) mode calibration with timing calibration enabled. Typical
values are at TA = 25°C.(1)(2)
PARAMETER
TEST CONDITIONS
MIN
TYP
72.9
74.8
MAX
UNIT
FIN = 350 MHz, –1 dBFS, 12-bit DDC bypass mode
TA = 25°C
TA = TMIN to TMAX
61.8
60.7
FIN = 600 MHz, –1 dBFS, 12-bit DDC bypass
mode
Spurious-free dynamic range
Input frequency-dependent
interleaving spurs included
SFDR
TA = 25°C, calibration = BG
TA = TMIN to TMAX, calibration = BG
71
dBFS
FIN = 1500 MHz, –1 dBFS, 12-bit DDC bypass mode
FIN = 2400 MHz, –1 dBFS, 12-bit DDC bypass mode
66.7
59.8
–77
TA = 25°C
TA = TMIN to TMAX
–59.8
–57.3
–54.3
–54
Interleaving offset spur at ½
sampling rate
FIN = 600 MHz, –1 dBFS, 12-bit DDC bypass
mode
ƒS/2
dBFS
dBFS
dBFS
dBFS
dBFS
TA = 25°C, calibration = BG
TA = TMIN to TMAX, calibration = BG
TA = 25°C
–73
–72
–69
–77
–79
–76
–74
–76
–77
TA = TMIN to TMAX
Interleaving offset spur at ¼
sampling rate
FIN = 600 MHz, –1 dBFS, 12-bit DDC bypass
mode
ƒS/4
TA = 25°C, calibration = BG
TA = TMIN to TMAX, calibration = BG
TA = 25°C
Interleaving offset spur at ½
sampling rate – input
frequency
TA = TMIN to TMAX
–62
FIN = 600 MHz, –1 dBFS, 12-bit DDC bypass
mode
ƒS/2 – FIN
ƒS/4 + FIN
ƒS/4 – FIN
TA = 25°C, calibration = BG
TA = TMIN to TMAX, calibration = BG
TA = 25°C
–62
Interleaving offset spur at ¼
sampling rate + input
frequency
TA = TMIN to TMAX
–61.8
–61
FIN = 600 MHz, –1 dBFS, 12-bit DDC bypass
mode
TA = 25°C, calibration = BG
TA = TMIN to TMAX, calibration = BG
TA = 25°C
Interleaving offset spur at ¼
sampling rate – input
frequency
TA = TMIN to TMAX
–62
FIN = 600 MHz, –1 dBFS, 12-bit DDC bypass
mode
TA = 25°C, calibration = BG
TA = TMIN to TMAX, calibration = BG
–61
FIN = 350 MHz, –1 dBFS, 12-bit DDC bypass mode
TA = 25°C
–72
–72
TA = TMIN to TMAX
–60.9
–61
FIN = 600 MHz, –1 dBFS, 12-bit DDC bypass
mode
THD
HD2
HD3
Total harmonic distortion
Second harmonic distortion
Third harmonic distortion
TA = 25°C, calibration = BG
TA = TMIN to TMAX, calibration = BG
–71
dBFS
dBFS
dBFS
FIN = 1500 MHz, –1 dBFS, 12-bit DDC bypass mode
FIN = 2400 MHz, –1 dBFS, 12-bit DDC bypass mode
FIN = 350 MHz, –1 dBFS, 12-bit DDC bypass mode
–69
–69
–79
–78
TA = 25°C
TA = TMIN to TMAX
–62
–63
FIN = 600 MHz, –1 dBFS, 12-bit DDC bypass
mode
TA = 25°C, calibration = BG
TA = TMIN to TMAX, calibration = BG
–79
FIN = 1500 MHz, –1 dBFS, 12-bit DDC bypass mode
FIN = 2400 MHz, –1 dBFS, 12-bit DDC bypass mode
FIN = 350 MHz, –1 dBFS, 12-bit DDC bypass mode
–73
–70
–76
–81
TA = 25°C
TA = TMIN to TMAX
–65
–61
FIN = 600 MHz, –1 dBFS, 12-bit DDC bypass
mode
TA = 25°C, calibration = BG
TA = TMIN to TMAX, calibration = BG
–76
FIN = 1500 MHz, –1 dBFS, 12-bit DDC bypass mode
FIN = 2400 MHz, –1 dBFS, 12-bit DDC bypass mode
–72
–76
12
Copyright © 2014–2017, Texas Instruments Incorporated
ADC12J1600, ADC12J2700
www.ti.com.cn
ZHCSCX0D –JANUARY 2014–REVISED OCTOBER 2017
Electrical Characteristics (continued)
Unless otherwise noted, these specifications apply for V(VA12) = V(VD12) = 1.2 V, V(VA19) = 1.9 V, VIN full scale range at default
setting (725 mVPP), VIN = –1 dBFS, differential AC-coupled sinewave input clock, ƒ(DEVCLK) = 2.7 or 1.6 GHz at 0.5 VPP with
50% duty cycle, R(RBIAS) = 3.3 kΩ ±0.1%, after a foreground (FG) mode calibration with timing calibration enabled. Typical
values are at TA = 25°C.(1)(2)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
–145
dBFS/Hz
dBm/Hz
dBFS/Hz
dBm/Hz
50-Ω AC-coupled terminated input
Noise spectral density,
average NSD across Nyquist
bandwidth
–146.8
–143.9
–145.7
12-bit DDC bypass mode, ADC12J1600,
ƒ(DEVCLK) = 1.6 GHz
NSD
FIN = 600 MHz, –1 dBFS
DECIMATE-BY-8 MODE, ADC12J2700, ƒ(DEVCLK) = 2.7 GHz
62.8
62.7
53.3
62.8
62.7
53.3
10.1
10.1
8.6
Signal-to-noise ratio,
integrated across DDC output
bandwidth
FIN = 600 MHz, –1 dBFS, decimate-by-8
mode
SNR
Calibration = BG
Calibration = BG
Calibration = BG
dBFS
dBFS
Bits
Interleaving spurs included
FIN = 2400 MHz, –1 dBFS, Decimate-by-8 mode
Signal-to-noise and distortion
ratio, integrated across DDC
output bandwidth
FIN = 600 MHz, –1 dBFS, decimate-by-8
mode
SINAD
ENOB
Interleaving spurs included
FIN = 2400 MHz, –1 dBFS, decimate-by-8 mode
Effective number of bits,
integrated across DDC output
bandwidth
FIN = 600 MHz, –1 dBFS, decimate-by-8
mode
Interleaving spurs included
FIN = 2400 MHz, –1 dBFS, decimate-by-8 mode
75.9
74.7
–73
–72
–70
–70
–80
Spurious-free dynamic range FIN = 600 MHz, –1 dBFS, decimate-by-8
SFDR
ƒS/2
dBFS
dBFS
dBFS
Interleaving spurs included
mode
Calibration = BG
Calibration = BG
Calibration = BG
Interleaving offset spur at ½
sampling rate(3)
FIN = 600 MHz, –1 dBFS, decimate-by-8
mode
Interleaving offset spur at ¼
sampling rate(3)
FIN = 600 MHz, –1 dBFS, decimate-by-8
mode
ƒS/4
Interleaving spur at ½
sampling rate – input
frequency(3)
FIN = 600 MHz, –1 dBFS, decimate-by-8
mode
ƒS/2 – FIN
ƒS/4 + FIN
ƒS/4 – FIN
dBFS
dBFS
dBFS
Calibration = BG
Calibration = BG
–79
–73
–70
–77
–77
Interleaving spur at ¼
sampling rate + input
frequency(3)
FIN = 600 MHz, –1 dBFS, decimate-by-8
mode
Interleaving spur at ¼
sampling rate – input
frequency(3)
FIN = 600 MHz, –1 dBFS, decimate-by-8
mode
Calibration = BG
calibration = BG
–70
–71
–65
–78
–76
–67
–74
–81
–73
FIN = 600 MHz, –1 dBFS, decimate-by-8
mode
THD
HD2
HD3
Total harmonic distortion(3)
Second harmonic distortion(3)
Third harmonic distortion(3)
dBFS
dBFS
dBFS
FIN = 2400 MHz, –1 dBFS, decimate-by-8 mode
FIN = 600 MHz, –1 dBFS, decimate-by-8
mode
Calibration = BG
FIN = 2400 MHz, –1 dBFS, decimate-by-8 mode
FIN = 600 MHz, –1 dBFS, decimate-by-8
mode
Calibration = BG
FIN = 2400 MHz, –1 dBFS, decimate-by-8 mode
DECIMATE-BY-8 MODE, ADC12J1600, ƒ(DEVCLK) = 1.6 GHz
63.5
63.4
55.8
63.5
63.4
55.8
10.3
10.2
9.0
Signal-to-noise ratio,
integrated across DDC output
bandwidth
FIN = 600 MHz, –1 dBFS, decimate-by-8
mode
SNR
Calibration = BG
Calibration = BG
Calibration = BG
dBFS
dBFS
Bits
Interleaving spurs included
FIN = 2400 MHz, –1 dBFS, decimate-by-8 mode
Signal-to-noise and distortion
ratio, integrated across DDC
output bandwidth
FIN = 600 MHz, –1 dBFS, decimate-by-8
mode
SINAD
ENOB
Interleaving spurs included
FIN = 2400 MHz, –1 dBFS, decimate-by-8 mode
Effective number of bits,
integrated across DDC output
bandwidth
FIN = 600 MHz, –1 dBFS, decimate-by-8
mode
Interleaving spurs included
FIN = 2400 MHz, –1 dBFS, decimate-by-8 mode
76.2
76.7
–73
Spurious-free dynamic range FIN = 600 MHz, –1 dBFS, decimate-by-8
SFDR
ƒS/2
dBFS
dBFS
Interleaving Spurs Included
mode
Calibration = BG
Calibration = BG
Interleaving offset spur at ½
sampling rate(3)
FIN = 600 MHz, –1 dBFS, decimate-by-8
mode
–72
(3) Magnitude of reported tones in output spectrum of ADC core. This tone will only be present in the DDC output for specific Decimation
and NCO settings. Careful frequency planning can be used to intentionally place unwanted tones outside the DDC output spectrum.
Copyright © 2014–2017, Texas Instruments Incorporated
13
ADC12J1600, ADC12J2700
ZHCSCX0D –JANUARY 2014–REVISED OCTOBER 2017
www.ti.com.cn
Electrical Characteristics (continued)
Unless otherwise noted, these specifications apply for V(VA12) = V(VD12) = 1.2 V, V(VA19) = 1.9 V, VIN full scale range at default
setting (725 mVPP), VIN = –1 dBFS, differential AC-coupled sinewave input clock, ƒ(DEVCLK) = 2.7 or 1.6 GHz at 0.5 VPP with
50% duty cycle, R(RBIAS) = 3.3 kΩ ±0.1%, after a foreground (FG) mode calibration with timing calibration enabled. Typical
values are at TA = 25°C.(1)(2)
PARAMETER
TEST CONDITIONS
MIN
TYP
–70
–69
–78
MAX
UNIT
Interleaving offset spur at ¼
sampling rate(3)
FIN = 600 MHz, –1 dBFS, decimate-by-8
ƒS/4
dBFS
mode
Calibration = BG
Calibration = BG
Interleaving spur at ½
sampling rate – input
frequency(3)
FIN = 600 MHz, –1 dBFS, decimate-by-8
mode
ƒS/2 – FIN
dBFS
dBFS
dBFS
–79
–76
–77
–77
–72
Interleaving spur at ¼
sampling rate + input
frequency(3)
FIN = 600 MHz, –1 dBFS, decimate-by-8
mode
ƒS/4 + FIN
ƒS/4 – FIN
Calibration = BG
Interleaving spur at ¼
sampling rate – input
frequency(3)
FIN = 600 MHz, –1 dBFS, decimate-by-8
mode
Calibration = BG
Calibration = BG
–71
–71
–63
–77
–78
–65
–80
–77
–74
FIN = 600 MHz, –1 dBFS, decimate-by-8
mode
THD
HD2
HD3
Total harmonic distortion(3)
Second harmonic distortion(3)
Third harmonic distortion(3)
dBFS
dBFS
dBFS
dB
FIN = 2400 MHz, –1 dBFS, decimate-by-8 mode
FIN = 600 MHz, –1 dBFS, decimate-by-8
mode
Calibration = BG
FIN = 2400 MHz, –1 dBFS, decimate-by-8 mode
FIN = 600 MHz, –1 dBFS, decimate-by-8
mode
Calibration = BG
FIN = 2400 MHz, –1 dBFS, decimate-by-8 mode
DDC CHARACTERISTICS
Alias protection(4)
80
80
% of
output BW
Alias protected bandwidth(4)
Spurious-free dynamic range
of digital down-converter(4)
SFDR-DDC
100
dB
dB
Implementation loss(4)
0.5
ANALOG INPUT CHARACTERISTICS
Minimum FSR setting(5)
Default FSR setting, TA = TMIN to TMAX
Maximum FSR setting(5)
Differential
500
725
950
0.05
1.5
95
Full-scale analog-differential
input range
VID(VIN)
650
80
800
mVPP
pF
pF
Ω
CI(VIN)
Analog input capacitance(4)
Differential input resistance
Full power bandwidth
Each input pin to ground
RID(VIN)
FPBW
110
–3 dB — calibration = BG
–3 dB — calibration = FG
DC to 2 GHz
2.8
3.2
1.2
3.8
1.5
4.5
GHz
2 GHz to 4 GHz
Gain flatness
dB
DC to 2 GHz — calibration = BG
2 GHz to 4 GHz — calibration = BG
ANALOG OUTPUT CHARACTERISTICS (VCMO, VBG)
I(VCMO) = ±100 µA, TA = 25°C
I(VCMO) = ±100 µA, TA = TMIN to TMAX
1.225
-21
Common-mode output
voltage
V(VCMO)
V
1.185
1.265
Common-mode output-
voltage temperature
coefficient
TCVO(VCMO)
TA = TMIN to TMAX
ppm/°C
Maximum VCMO output load
capacitance
C(LOAD_VCMO)
80
pF
V
I(BG) = ±100 µA, TA = 25°C
1.248
0
Bandgap reference output
voltage
VO(BG)
I(BG) = ±100 µA, TA = TMIN to TMAX
1.195
1.3
Bandgap reference voltage
temperature coefficient
TA = TMIN to TMAX
,
TCVref(BG)
C(LOAD_BG)
ppm/°C
pF
I(BG) = ±100 µA
Maximum bandgap reference
output load capacitance
80
(4) This parameter is specified by design and is not tested in production.
(5) This parameter is specified by design, characterization, or both and is not tested in production.
14
Copyright © 2014–2017, Texas Instruments Incorporated
ADC12J1600, ADC12J2700
www.ti.com.cn
ZHCSCX0D –JANUARY 2014–REVISED OCTOBER 2017
Electrical Characteristics (continued)
Unless otherwise noted, these specifications apply for V(VA12) = V(VD12) = 1.2 V, V(VA19) = 1.9 V, VIN full scale range at default
setting (725 mVPP), VIN = –1 dBFS, differential AC-coupled sinewave input clock, ƒ(DEVCLK) = 2.7 or 1.6 GHz at 0.5 VPP with
50% duty cycle, R(RBIAS) = 3.3 kΩ ±0.1%, after a foreground (FG) mode calibration with timing calibration enabled. Typical
values are at TA = 25°C.(1)(2)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
TEMPERATURE DIODE CHARACTERISTICS
Offset voltage (approx. 0.77 V) varies with
100-µA forward current
Device active
–1.6
–1.6
mV/°C
mV/°C
process and must be measured for each
part. Offset measurement should be done
with PowerDown=1 to minimize device self-
heating.
Temperature diode voltage
slope
V(TDIODE)
100-µA forward current
Device in power-down
CLOCK INPUT CHARACTERISTICS (DEVCLK±, SYSREF±, SYNC~/TMST±)
Sine wave clock, TA = TMIN to TMAX
0.4
0.4
0.6
0.6
±1
2
2
VPP
VPP
µA
pF
pF
Ω
VID(CLK)
II(CLK)
Differential clock input level
Input current
Square wave clock, TA = TMIN to TMAX
VI = 0 or VI = VA
Differential
0.02
1
CI(CLK)
Input capacitance(4)
Each input to ground
TA = 25°C
95
RID(CLK)
Differential input resistance
TA = TMIN to TMAX
80
110
Ω
CML OUTPUT CHARACTERISTICS (DS0–DS7±)
Assumes ideal 100-Ω load
Measured differentially
VOD
Differential output voltage
280
305
330 mV peak
Default pre-emphasis setting
VO(ofs)
IOS
Output offset voltage
0.6
±6
V
mA
Ω
Output+ and output– shorted together
Output+ or output– shorted to 0 V
Output short-circuit current
Differential output impedance
12
ZOD
100
LVCMOS INPUT CHARACTERISTICS (SDI, SCLK, SCS, SYNC~)
(5)
VIH
VIL
CI
Logic high input voltage
Logic low input voltage
Input capacitance(4)(6)
See
See
0.83
1.65
V
(5)
0.4
V
Each input to ground
1
pF
LVCMOS OUTPUT CHARACTERISTICS (SDO, OR_T0, OR_T1)
VOH
VOL
CMOS H level output
CMOS L level output
IOH = –400 µA(5)
IOH = 400 µA(5)
1.9
V
V
0.01
0.15
POWER SUPPLY CHARACTERISTICS
ADC12J2700, ƒ(DEVCLK) = 2.7 GHz
PD = 0, calibration = FG, bypass DDC
PD = 0, calibration = BG, bypass DDC
457
557
557
245
261
270
330
341
366
1.56
1.78
1.82
< 50
495
594
598
296
312
322
541
588
610
1.94
2.21
2.25
I(VA19)
I(VA12)
I(VD12)
Analog 1.9-V supply current
Analog 1.2-V supply current
Digital 1.2-V supply current
mA
mA
mA
PD = 0, calibration = BG, decimate by 8, DDR = 0, P54 = 1
PD = 0, calibration = FG, bypass DDC
PD = 0, calibration = BG, bypass DDC
PD = 0, calibration = BG, decimate by 8, DDR = 0, P54 = 1
PD = 0, calibration = FG, bypass DDC
PD = 0, calibration = BG, bypass DDC
PD = 0, calibration = BG, decimate by 8, DDR = 0, P54 = 1
PD = 0, calibration = FG, bypass DDC
PD = 0, calibration = BG, bypass DDC
W
PC
Power consumption
PD = 0, calibration = BG, decimate by 8, DDR = 0, P54 = 1
PD = 1
mW
(6) The digital control pin capacitances are die capacitances only and is in addition to package and bond-wire capacitance of approximately
0.4 pF.
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Electrical Characteristics (continued)
Unless otherwise noted, these specifications apply for V(VA12) = V(VD12) = 1.2 V, V(VA19) = 1.9 V, VIN full scale range at default
setting (725 mVPP), VIN = –1 dBFS, differential AC-coupled sinewave input clock, ƒ(DEVCLK) = 2.7 or 1.6 GHz at 0.5 VPP with
50% duty cycle, R(RBIAS) = 3.3 kΩ ±0.1%, after a foreground (FG) mode calibration with timing calibration enabled. Typical
values are at TA = 25°C.(1)(2)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ADC12J1600, ƒ(DEVCLK) = 1.6 GHz
PD = 0, calibration = FG, bypass DDC
454
553
553
180
190
196
225
237
255
1.35
1.56
1.59
< 50
493
591
598
222
233
243
460
529
568
1.75
2.04
2.11
I(VA19)
I(VA12)
I(VD12)
Analog 1.9-V supply current
PD = 0, calibration = BG, bypass DDC
mA
PD = 0, calibration = BG, decimate by 8, DDR = 0, P54 = 1
PD = 0, calibration = FG, bypass DDC
Analog 1.2-V supply current
Digital 1.2-V supply current
PD = 0, calibration = BG, bypass DDC
mA
PD = 0, calibration = BG, decimate by 8, DDR = 0, P54 = 1
PD = 0, calibration = FG, bypass DDC
PD = 0, calibration = BG, bypass DDC
mA
PD = 0, calibration = BG, decimate by 8, DDR = 0, P54 = 1
PD = 0, calibration = FG, bypass DDC
PD = 0, calibration = BG, bypass DDC
W
PC
Power consumption
PD = 0, calibration = BG, decimate by 8, DDR = 0, P54 = 1
PD = 1
mW
6.6 Timing Requirements
MIN
NOM
MAX
UNIT
DEVICE (SAMPLING) CLOCK
Sampling rate is equal to clock input, ADC12J2700
1
1
2.7
1.6
ƒ(DEVCLK) Input DEVCLK frequency
GHz
Sampling rate is equal to clock input, ADC12J1600
Input CLK transition to sampling instant
td(A)
t(AJ)
Sampling (aperture) delay
Aperture jitter
0.64
0.1
ns
ps RMS
t(DEVCLK)
t(LAT)
ADC core latency(1)
Decimation = 1, DDR = 1, P54 = 0
Decimation = 4, DDR = 1, P54 = 0
Decimation = 4, DDR = 1, P54 = 1
Decimation = 8, DDR = 0, P54 = 0
Decimation = 8, DDR = 0, P54 = 1
Decimation = 8, DDR = 1, P54 = 0
Decimation = 8, DDR = 1, P54 = 1
Decimation = 10, DDR = 0, P54 = 0
Decimation = 10, DDR = 1, P54 = 0
Decimation = 16, DDR = 0, P54 = 0
Decimation = 16, DDR = 0, P54 = 1
Decimation = 16, DDR = 1, P54 = 0
Decimation = 16, DDR = 1, P54 = 1
Decimation = 20, DDR = 0, P54 = 0
Decimation = 20, DDR = 1, P54 = 0
Decimation = 32, DDR = 0, P54 = 0
Decimation = 32, DDR = 0, P54 = 1
Decimation = 32, DDR = 1, P54 = 0
64
292
284
384
368
392
368
386
386
608
560
608
560
568
568
1044
948
1044
t(LAT_DDC) ADC core and DDC latency(1)
t(DEVCLK)
(1) Unless otherwise specified, delays quoted are exact un-rounded functional delays (assuming zero propagation delay).
16
Copyright © 2014–2017, Texas Instruments Incorporated
ADC12J1600, ADC12J2700
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ZHCSCX0D –JANUARY 2014–REVISED OCTOBER 2017
Timing Requirements (continued)
MIN
NOM
MAX
UNIT
JESD204B INTERFACE LINK TIMING CHARACTERISTICS (REFER TO Figure 1)
SYSREF to LMFC delay
Functional delay between SYSREF
td(LMFC)
All decimation modes
40
t(DEVCLK)
assertion latched and LMFC frame
boundary(1)
LMFC to frame boundary delay - DDC
bypass mode
td(TX)
Functional delay from LMFC frame boundary Decimation = 1, DDR = 1, P54 = 0
to beginning of next multi-frame in
52.7
t(DEVCLK)
transmitted data.(2)
Decimation = 4, DDR = 1, P54 = 0
Decimation = 4, DDR = 1, P54 = 1
Decimation = 8, DDR = 0, P54 = 0
Decimation = 8, DDR = 0, P54 = 1
Decimation = 8, DDR = 1, P54 = 0
Decimation = 8, DDR = 1, P54 = 1
Decimation = 10, DDR = 0, P54 = 0
52.7
43.9
60.7
51.5
52.7
43.9
60.7
52.7
60.7
51.5
52.7
43.9
60.7
52.7
60.7
51.5
52.7
LMFC to frame boundary delay - decimation
Decimation = 10, DDR = 1, P54 = 0
modes
Functional delay from LMFC frame boundary Decimation = 16, DDR = 0, P54 = 0
to beginning of next multi-frame in
Decimation = 16, DDR = 0, P54 = 1
transmitted data(2)
td(TX)
t(DEVCLK)
Decimation = 16, DDR = 1, P54 = 0
Decimation = 16, DDR = 1, P54 = 1
Decimation = 20, DDR = 0, P54 = 0
Decimation = 20, DDR = 1, P54 = 0
Decimation = 32, DDR = 0, P54 = 0
Decimation = 32, DDR = 0, P54 = 1
Decimation = 32, DDR = 1, P54 = 0
tsu(SYNC~- SYNC~ to LMFC setup time(3)
40
–8
Required SYNC~ setup time relative to the internal LMFC boundary.
F)
t(DEVCLK)
th(SYNC~- SYNC~ to LMFC hold time(3)
Required SYNC~ hold time relative to the internal LMFC boundary.
F)
SYNC~ assertion time
Required SYNC~ assertion time before deassertion to initiate a link resynchronization.
Frame clock
cycles
t(SYNC~)
4
40
4
td(LMFC)
t(ILA)
Delay from SYSREF sampled high by DEVCLK to internal LMFC boundary
Duration of initial lane alignment sequence
t(DEVCLK)
Multi-frame
clock cycles
SYSREF
tsu(SYS)
th(SYS)
Setup time SYSREF relative to DEVCLK rising edge(4)
Hold time SYSREF relative to DEVCLK rising edge(4)
40
40
ps
ps
t(PH_SYS) SYSREF assertion duration after rising edge event.
t(PL_SYS) SYSREF deassertion duration after falling edge event.
8
8
t(DEVCLK)
t(DEVCLK)
K × F ×
10
DDR = 0, P54 = 0
K × F ×
8
DDR = 0, P54 = 1
DDR = 1, P54 = 0
DDR = 1, P54 = 1
t(SYS)
Period SYSREF±
t(DEVCLK)
K × F ×
5
K × F ×
4
(2) The values given are functional delays only. Additional propagation delay of 0 to 3 clock cycles will be present.
(3) This parameter must be met to achieve deterministic alignment of the data frame and NCO phase to other similar devices. If this
parameter is not met the device will still function correctly but will not be aligned to other devices.
(4) This parameter is specified by design, characterization, or both and is not tested in production.
Copyright © 2014–2017, Texas Instruments Incorporated
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UNIT
Timing Requirements (continued)
MIN
NOM
MAX
SERIAL INTERFACE (REFER TO Figure 2)
ƒ(SCK)
t(PH)
t(PL)
tsu
Serial clock frequency(5)
20
MHz
ns
Serial clock high time
20
20
10
10
10
10
10
Serial clock low time
ns
Serial-data to serial-clock rising setup time(5)
Serial-data to serial clock rising hold time(5)
SCS-to-serial clock rising setup time
SCS-to-serial clock falling hold time
Inter-access gap
ns
th
ns
t(CSS)
t(CSH)
t(IAG)
ns
ns
ns
(5) This parameter is specified by design and is not tested in production.
6.7 Internal Characteristics
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX
UNIT
DEVICE (SAMPLING) CLOCK
td(A)
t(AJ)
Sampling (aperture) delay
Aperture jitter
Input CLK transition to sampling instant
Decimation = 1, DDR = 1, P54 = 0
0.64
0.1
64
ns
ps RMS
t(DEVCLK)
(1)
t(LAT)
ADC core latency. See
CALIBRATION TIMING CHARACTERISTICS (REFER TO THE CALIBRATION SECTION)
227 ×
106
Calibration = FG, T_AUTO=1
t(CAL)
Calibration cycle time
t(DEVCLK)
102 ×
106
Calibration = FG, T_AUTO=0
JESD204B INTERFACE LINK TIMING CHARACTERISTICS (REFER TO Figure 1)
SYSREF to LMFC delay
td(LMFC)
Functional delay between SYSREF assertion
All decimation modes
40
t(DEVCLK)
latched and LMFC frame boundary(1)
LMFC to Frame Boundary delay - DDC
Bypass Mode
td(TX)
Functional delay from LMFC frame boundary
to beginning of next multi-frame in transmitted
data(2)
Decimation = 1, DDR = 1, P54 = 0
52.7
t(DEVCLK)
Decimation = 4, DDR = 1, P54 = 0
Decimation = 4, DDR = 1, P54 = 1
Decimation = 8, DDR = 0, P54 = 0
Decimation = 8, DDR = 0, P54 = 1
Decimation = 8, DDR = 1, P54 = 0
Decimation = 8, DDR = 1, P54 = 1
Decimation = 10, DDR = 0, P54 = 0
Decimation = 10, DDR = 1, P54 = 0
Decimation = 16, DDR = 0, P54 = 0
Decimation = 16, DDR = 0, P54 = 1
Decimation = 16, DDR = 1, P54 = 0
Decimation = 16, DDR = 1, P54 = 1
Decimation = 20, DDR = 0, P54 = 0
Decimation = 20, DDR = 1, P54 = 0
Decimation = 32, DDR = 0, P54 = 0
Decimation = 32, DDR = 0, P54 = 1
Decimation = 32, DDR = 1, P54 = 0
52.7
43.9
60.7
51.5
52.7
43.9
60.7
52.7
60.7
51.5
52.7
43.9
60.7
52.7
60.7
51.5
52.7
40
LMFC to frame boundary delay - decimation
modes
Functional delay from LMFC frame boundary
to beginning of next multi-frame in transmitted
data(2)
td(TX)
t(DEVCLK)
td(LMFC)
t(ILA)
Delay from SYSREF sampled high by DEVCLK to internal LMFC boundary
Duration of initial lane alignment sequence
t(DEVCLK)
Multi-frame
clock cycles
4
(1) Unless otherwise specified, delays quoted are exact un-rounded functional delays (assuming zero propagation delay).
(2) The values given are functional delays only. Additional propagation delay of 0 to 3 clock cycles will be present.
18
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ADC12J1600, ADC12J2700
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ZHCSCX0D –JANUARY 2014–REVISED OCTOBER 2017
6.8 Switching Characteristics
Unless otherwise noted, these specifications apply for V(VA12) = V(VD12) = 1.2 V, V(VA19) = 1.9 V, VIN FSR (AC coupled) =
Default setting, differential AC-coupled sinewave input clock, ƒ(DEVCLK) = 2.7 or 1.6 GHz at 0.5 VPP with 50% duty cycle,
R(RBIAS) = 3.3 kΩ ±0.1%, after a foreground mode calibration with timing calibration enabled. Typical values are at TA = 25°C.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SERIAL DATA OUTPUTS
Serialized output bit rate
Serialized output bit rate
1
10
DDR = 0, P54 = 0
ƒS
1.25 ×
ƒS
DDR = 0, P54 = 1
DDR = 1, P54 = 0
DDR = 1, P54 = 1
Gbps
2 × ƒS
2.5 ×
ƒS
tTLH
tTHL
UI
LH transition time — differential
HL transition time — differential
Unit interval
10% to 90%, 8 Gbps
10% to 90%, 8 Gbps
8 Gbps serial rate
8 Gbps serial rate
8 Gbps serial rate
35
35
ps
ps
ps
ps
ps
125
11.3
1.4
DDJ
RJ
Data dependent jitter
Random Jitter
SERIAL INTERFACE
t(OZD)
t(ODZ)
t(OD)
SDO tri-state to driven
5
5
ns
ns
ns
SDO driven to tri-state
SDO output delay
See Figure 2
2.5
20
SYSREF assertion
latched
SYNC~ assertion
latched
SYNC~ de-assertion
latched
t
(SYNC~)
tsu(SYNC~-F)
th(-SYNC~-F)
SYNC~
t
(ILA)
XXX
XXX
K28.5
K28.5
ILA
d(TX)
ILA
Valid Data
Serial Data
t
t
h(SYS)
t
t
d(TX)
t
su(SYS)
DEVCLK
SYSREF
(PL-SYS)
t
(PH-SYS)
Tx Frame Clk
t
Tx LMFC Boundary
d(LMFC)
Code Group
Synchronization
Initial Frame and Lane
Synchronization
Data
Transmission
Frame Clock
Alignment
Figure 1. JESD204 Synchronization
st
th
th
24 clock
1
clock
16 clock
SCLK
SCS
t
(CSS)
t
t
(PL)
t
t
(CSS)
(PH)
(CSH)
t
(CSH)
t
(IAG)
t
+ t
(PL)
= t = 1 / ƒ
(P)
(PH)
(SCK)
t
su
t
t
su
t
h
h
SDI
D7
D1
D1
D0
Write Command
D0
COMMAND FIELD
Hi-Z
t
(OD)
Hi-Z
SDO
D7
t
t
(OZD)
(ODZ)
Read Command
Figure 2. Serial Interface Timing
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ADC12J1600, ADC12J2700
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6.9 Typical Characteristics
Unless otherwise noted, these specifications apply for V(VA12) = V(VD12) = 1.2 V, V(VA19) = 1.9 V, VIN FSR (AC coupled) =
Default setting, differential AC-coupled sinewave input clock, ƒ(DEVCLK) = 2.7 or 1.6 GHz at 0.5 VPP with 50% duty cycle,
R(RBIAS) = 3.3 kΩ ±0.1%, after a Foreground mode calibration with Timing Calibration enabled. TA = 25°C. VI = –1 dBFS.
10
9
80
75
70
65
60
55
50
45
SNR (dBFS)
SINAD (dBFS)
SFDR (dBFS)
8
7
6
5
1500
2000
2500
3000
1500
2000
2500
3000
Sampling Rate (MSPS)
Sampling Rate (MSPS)
D122
D120
DDC bypass mode
FIN = 608 MHz
DDC bypass mode
FIN = 608 MHz
Figure 4. ENOB vs Sampling Rate
Figure 3. SNR, SINAD, SFDR vs Sampling Rate
2
1.8
1.6
1.4
1.2
1
0.6
0.5
0.4
0.3
0.2
0.1
VA19
VA12
VD12
1500
2000
2500
3000
1500
2000
2500
3000
Sampling Rate (MSPS)
Sampling Rate (MSPS)
D124
D123
DDC bypass mode
FIN = 608 MHz
DDC bypass mode
FIN = 608 MHz
Figure 5. Power Consumption vs Sampling Rate
Figure 6. Supply Current vs Sampling Rate
100
90
80
70
60
50
40
80
75
70
65
60
55
50
45
SNR (dBFS)
SINAD (dBFS)
SFDR (dBFS)
SNR (dBFS)
SINAD (dBFS)
SFDR (dBFS)
0
300 600 900 1200 1500 1800 2100 2400 2700 3000
Input Frequency (MHz)
0
4
8
12
16
20
24
28
32
Decimation Factor
D073
D086
ADC12J2700
DDC bypass mode
ADC12J2700
FIN = 608 MHz
Figure 7. SNR, SINAD, SFDR vs Input Frequency
Figure 8. SNR, SINAD, SFDR vs Decimation Setting
20
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ADC12J1600, ADC12J2700
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ZHCSCX0D –JANUARY 2014–REVISED OCTOBER 2017
Typical Characteristics (continued)
Unless otherwise noted, these specifications apply for V(VA12) = V(VD12) = 1.2 V, V(VA19) = 1.9 V, VIN FSR (AC coupled) =
Default setting, differential AC-coupled sinewave input clock, ƒ(DEVCLK) = 2.7 or 1.6 GHz at 0.5 VPP with 50% duty cycle,
R(RBIAS) = 3.3 kΩ ±0.1%, after a Foreground mode calibration with Timing Calibration enabled. TA = 25°C. VI = –1 dBFS.
100
90
80
70
60
50
40
80
75
70
65
60
55
50
45
SNR (dBFS)
SINAD (dBFS)
SFDR (dBFS)
SNR (dBFS)
SINAD (dBFS)
SFDR (dBFS)
0
4
8
12
16
20
24
28
32
-10
-5
0
5
10
Decimation Factor
All Supply Voltage Variation from Nominal (%)
D091
D076
ADC12J2700
FIN = 2483 MHz
ADC12J2700
DDC bypass mode
FIN = 608 MHz
Figure 9. SNR, SINAD, SFDR vs Decimation Setting
Figure 10. SNR, SINAD, SFDR vs Supply Voltage
80
75
70
65
60
55
50
45
10
9
SNR (dBFS)
SINAD (dBFS)
SFDR (dBFS)
8
7
6
5
-50
-25
0
25
50
75
100
0
300 600 900 1200 1500 1800 2100 2400 2700 3000
Input Frequency (MHz)
Ambient Temperature (°C)
D079
D075
ADC12J2700
DDC bypass mode
FIN = 608 MHz
ADC12J2700
DDC bypass mode
Figure 11. SNR, SINAD, SFDR vs Temperature
Figure 12. ENOB vs Input Frequency
11
10
9
10
9
8
8
7
0
4
8
12
16
20
24
28
32
0
4
8
12
16
20
24
28
32
Decimation Factor
Decimation Factor
D088
D093
ADC12J2700
FIN = 608 MHz
ADC12J2700
FIN = 2483 MHz
Figure 13. ENOB vs Decimation Setting
Figure 14. ENOB vs Decimation Setting
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Typical Characteristics (continued)
Unless otherwise noted, these specifications apply for V(VA12) = V(VD12) = 1.2 V, V(VA19) = 1.9 V, VIN FSR (AC coupled) =
Default setting, differential AC-coupled sinewave input clock, ƒ(DEVCLK) = 2.7 or 1.6 GHz at 0.5 VPP with 50% duty cycle,
R(RBIAS) = 3.3 kΩ ±0.1%, after a Foreground mode calibration with Timing Calibration enabled. TA = 25°C. VI = –1 dBFS.
10
10
9
9
8
8
7
7
6
6
5
5
-10
-5
0
5
10
-50
-25
0
25
50
75
100
All Supply Variation from Nominal (%)
Temperature (°C)
D077
D080
ADC12J2700
DDC bypass mode
FIN = 608 MHz
ADC12J2700
DDC bypass mode
FIN = 608 MHz
Figure 15. ENOB vs Supply Voltage
Figure 16. ENOB vs Temperature
ADC12J2700
-50
-60
-50
-60
THD (dBFS)
HD2 (dBFS)
HD3 (dBFS)
THD (dBFS)
HD2 (dBFS)
HD3 (dBFS)
-70
-70
-80
-80
-90
-90
-100
-100
0
300 600 900 1200 1500 1800 2100 2400 2700 3000
Input Frequency (MHz)
-10
-5
0
5
10
All Supply Variation from Nominal (%)
D074
D078
ADC12J2700
DDC bypass mode
ADC12J2700
DDC bypass mode
FIN = 608 MHz
Figure 17. THD, H2, H3 vs Input Frequency
Figure 18. THD, H2, H3 vs Supply Voltage
-50
-60
1.9
1.8
1.7
1.6
1.5
1.4
THD (dBFS)
HD2 (dBFS)
HD3 (dBFS)
-70
-80
-90
-100
-50
-25
0
25
50
75
100
0
4
8
12
16
20
24
28
32
Temperature (°C)
Decimation Factor
D081
D089
ADC12J2700
DDC bypass mode
FIN = 608 MHz
ADC12J2700
FIN = 608 MHz
Figure 19. THD, H2, H3 vs Temperature
Figure 20. Power Consumption vs Decimation Setting
22
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ADC12J1600, ADC12J2700
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ZHCSCX0D –JANUARY 2014–REVISED OCTOBER 2017
Typical Characteristics (continued)
Unless otherwise noted, these specifications apply for V(VA12) = V(VD12) = 1.2 V, V(VA19) = 1.9 V, VIN FSR (AC coupled) =
Default setting, differential AC-coupled sinewave input clock, ƒ(DEVCLK) = 2.7 or 1.6 GHz at 0.5 VPP with 50% duty cycle,
R(RBIAS) = 3.3 kΩ ±0.1%, after a Foreground mode calibration with Timing Calibration enabled. TA = 25°C. VI = –1 dBFS.
1.8
1.7
1.6
1.5
1.4
1.3
1.8
1.6
1.4
1.2
-10
-5
0
5
10
-50
-25
0
25
50
75
100
All Supply Voltage Variation from Nominal (%)
Ambient Temperature (°C)
D082
D084
ADC12J2700
DDC bypass mode
FIN = 608 MHz
ADC12J2700
DDC bypass mode
FIN = 608 MHz
Figure 21. Power Consumption vs Supply Voltage
Figure 22. Power Consumption vs Temperature
0.6
0.5
0.4
0.3
0.2
0.1
0.6
0.5
0.4
0.3
0.2
0.1
VA19
VA12
VD12
VA19
VA12
VD12
0
4
8
12
16
20
24
28
32
-10
-5
0
5
10
Decimation Factor
All Supply Voltage Variation from Nominal (%)
D090
D083
ADC12J2700
FIN = 608 MHz
ADC12J2700
DDC bypass mode
FIN = 608 MHz
Figure 23. Supply Current vs Decimation Setting
Figure 24. Supply Current vs Supply Voltage
0.6
0.5
0.4
0.3
0.2
0.1
80
75
70
65
60
55
50
45
VA19
VA12
VD12
SNR (dBFS)
SINAD (dBFS)
SFDR (dBFS)
-50
-25
0
25
50
75
100
0
300 600 900 1200 1500 1800 2100 2400 2700 3000
Input Frequency (MHz)
Ambient Temperature (°C)
D085
D099
ADC12J2700
DDC bypass mode
FIN = 608 MHz
ADC12J1600
DDC bypass mode
Figure 25. Supply Current vs Temperature
Figure 26. SNR, SINAD, SFDR vs Input Frequency
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Typical Characteristics (continued)
Unless otherwise noted, these specifications apply for V(VA12) = V(VD12) = 1.2 V, V(VA19) = 1.9 V, VIN FSR (AC coupled) =
Default setting, differential AC-coupled sinewave input clock, ƒ(DEVCLK) = 2.7 or 1.6 GHz at 0.5 VPP with 50% duty cycle,
R(RBIAS) = 3.3 kΩ ±0.1%, after a Foreground mode calibration with Timing Calibration enabled. TA = 25°C. VI = –1 dBFS.
100
90
80
70
60
50
40
100
90
80
70
60
50
40
SNR (dBFS)
SINAD (dBFS)
SFDR (dBFS)
SNR (dBFS)
SINAD (dBFS)
SFDR (dBFS)
0
4
8
12
16
20
24
28
32
0
4
8
12
16
20
24
28
32
Decimation Factor
Decimation Factor
D112
D117
ADC12J1600
FIN = 608 MHz
ADC12J1600
FIN = 2483 MHz
Figure 27. SNR, SINAD, SFDR vs Decimation Setting
Figure 28. SNR, SINAD, SFDR vs Decimation Setting
80
75
70
65
60
55
50
45
80
75
70
65
60
55
50
45
SNR (dBFS)
SINAD (dBFS)
SFDR (dBFS)
SNR (dBFS)
SINAD (dBFS)
SFDR (dBFS)
-10
-5
0
5
10
-50
-25
0
25
50
75
100
All Supply Voltage Variation from Nominal (%)
Ambient Temperature (°C)
D014032
D105
ADC12J1600
DDC bypass mode
FIN = 608 MHz
ADC12J1600
DDC bypass mode
FIN = 608 MHz
Figure 29. SNR, SINAD, SFDR vs Supply Voltage
Figure 30. SNR, SINAD, SFDR vs Temperature
10
9
11
10
9
8
7
6
5
8
0
300 600 900 1200 1500 1800 2100 2400 2700 3000
Input Frequency (MHz)
0
4
8
12
16
20
24
28
32
Decimation Factor
D101
D114
ADC12J1600
DDC bypass mode
ADC12J1600
FIN = 608 MHz
Figure 31. ENOB vs Input Frequency
Figure 32. ENOB vs Decimation Setting
24
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Typical Characteristics (continued)
Unless otherwise noted, these specifications apply for V(VA12) = V(VD12) = 1.2 V, V(VA19) = 1.9 V, VIN FSR (AC coupled) =
Default setting, differential AC-coupled sinewave input clock, ƒ(DEVCLK) = 2.7 or 1.6 GHz at 0.5 VPP with 50% duty cycle,
R(RBIAS) = 3.3 kΩ ±0.1%, after a Foreground mode calibration with Timing Calibration enabled. TA = 25°C. VI = –1 dBFS.
10
10
9
9
8
7
8
6
7
5
0
4
8
12
16
20
24
28
32
-10
-5
0
5
10
Decimation Factor
All Supply Variation from Nominal (%)
D119
D103
ADC12J1600
FIN = 2483 MHz
ADC12J1600
DDC bypass mode
FIN = 608 MHz
Figure 33. ENOB vs Decimation Setting
Figure 34. ENOB vs Supply Voltage
-50
-60
10
9
THD (dBFS)
HD2 (dBFS)
HD3 (dBFS)
-70
8
-80
7
-90
6
5
-100
-50
-25
0
25
50
75
100
0
300 600 900 1200 1500 1800 2100 2400 2700 3000
Input Frequency (MHz)
Temperature (°C)
D106
D100
ADC12J1600
DDC bypass mode
FIN = 608 MHz
ADC12J1600
DDC bypass mode
Figure 35. ENOB vs Temperature
Figure 36. THD, H2, H3 vs Input Frequency
-50
-60
-50
-60
THD (dBFS)
HD2 (dBFS)
HD3 (dBFS)
THD (dBFS)
HD2 (dBFS)
HD3 (dBFS)
-70
-70
-80
-80
-90
-90
-100
-100
-10
-5
0
5
10
-50
-25
0
25
50
75
100
All Supply Variation from Nominal (%)
Temperature (°C)
D104
D107
ADC12J1600
DDC bypass mode
FIN = 608 MHz
ADC12J1600
DDC bypass mode
FIN = 608 MHz
Figure 37. THD, H2, H3 vs Supply Voltage
Figure 38. THD, H2, H3 vs Temperature
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Typical Characteristics (continued)
Unless otherwise noted, these specifications apply for V(VA12) = V(VD12) = 1.2 V, V(VA19) = 1.9 V, VIN FSR (AC coupled) =
Default setting, differential AC-coupled sinewave input clock, ƒ(DEVCLK) = 2.7 or 1.6 GHz at 0.5 VPP with 50% duty cycle,
R(RBIAS) = 3.3 kΩ ±0.1%, after a Foreground mode calibration with Timing Calibration enabled. TA = 25°C. VI = –1 dBFS.
1.7
1.6
1.5
1.4
1.3
1.2
1.6
1.5
1.4
1.3
1.2
1.1
0
4
8
12
16
20
24
28
32
-10
-5
0
5
10
Decimation Factor
All Supply Voltage Variation from Nominal (%)
D115
D108
ADC12J1600
FIN = 608 MHz
ADC12J1600
DDC bypass mode
FIN = 608 MHz
Figure 39. Power Consumption vs Decimation Setting
Figure 40. Power Consumption vs Supply Voltage
1.5
0.6
0.5
0.4
0.3
0.2
0.1
VA19
VA12
VD12
1.4
1.3
1.2
-50
-25
0
25
50
75
100
0
4
8
12
16
20
24
28
32
Ambient Temperature (°C)
Decimation Factor
D110
D116
ADC12J1600
DDC bypass mode
FIN = 608 MHz
ADC12J1600
FIN = 608 MHz
Figure 41. Power Consumption vs Temperature
Figure 42. Supply Current vs Decimation Setting
0.6
0.5
0.4
0.3
0.2
0.1
0.6
0.5
0.4
0.3
0.2
0.1
VA19
VA12
VD12
VA19
VA12
VD12
-10
-5
0
5
10
-50
-25
0
25
50
75
100
All Supply Voltage Variation from Nominal (%)
Ambient Temperature (°C)
D109
D111
ADC12J1600
DDC bypass mode
FIN = 608 MHz
ADC12J1600
DDC bypass mode
FIN = 608 MHz
Figure 43. Supply Current vs Supply Voltage
Figure 44. Supply Current vs Temperature
26
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Typical Characteristics (continued)
Unless otherwise noted, these specifications apply for V(VA12) = V(VD12) = 1.2 V, V(VA19) = 1.9 V, VIN FSR (AC coupled) =
Default setting, differential AC-coupled sinewave input clock, ƒ(DEVCLK) = 2.7 or 1.6 GHz at 0.5 VPP with 50% duty cycle,
R(RBIAS) = 3.3 kΩ ±0.1%, after a Foreground mode calibration with Timing Calibration enabled. TA = 25°C. VI = –1 dBFS.
6
6
Corrected for Setup Losses
Raw Insertion Loss
Curve Fit
Corrected for Setup Losses
Raw Insertion Loss
Curve Fit
3
3
0
0
-3
-3
-6
-6
-9
-9
-12
-15
-12
-15
0
500 1000 1500 2000 2500 3000 3500 4000 4500 5000
Input Frequency (MHz)
0
500 1000 1500 2000 2500 3000 3500 4000 4500 5000
Input Frequency (MHz)
D037
D038
Foreground calibration mode
Background calibration mode
Figure 45. Insertion Loss vs Input Frequency
Figure 46. Insertion Loss vs Input Frequency
0.75
0.5
4
2
0.25
0
0
-0.25
-0.5
-0.75
-2
-4
0
4095
0
4095
Output Code
Output Code
D069
D070
Figure 47. DNL versus Code - ADC12J2700
Figure 48. INL versus Code - ADC12J2700
0.75
0.5
4
2
0.25
0
0
-0.25
-0.5
-0.75
-2
-4
0
4095
0
4095
Output Code
Output Code
D071
D072
Figure 49. DNL versus Code - ADC12J1600
Figure 50. INL versus Code - ADC12J1600
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Typical Characteristics (continued)
Unless otherwise noted, these specifications apply for V(VA12) = V(VD12) = 1.2 V, V(VA19) = 1.9 V, VIN FSR (AC coupled) =
Default setting, differential AC-coupled sinewave input clock, ƒ(DEVCLK) = 2.7 or 1.6 GHz at 0.5 VPP with 50% duty cycle,
R(RBIAS) = 3.3 kΩ ±0.1%, after a Foreground mode calibration with Timing Calibration enabled. TA = 25°C. VI = –1 dBFS.
30
0.0025
Filter Response
-80dB
0
0
-30
-0.0025
-0.005
-0.0075
-0.01
-60
-90
-120
-150
-180
0
0
0
0.1
0.2
0.3
0.4
0.5
0
0.025
0.05
0.075
0.1
0.125
Normalized to Filter Input Sample Rate
Normalized to Filter Input Sample Rate
D055
D056
Figure 51. Decimate by 4 - Stopband Response
Figure 52. Decimate by 4 - Passband Response
30
0
0.0025
0
Filter Response
-80dB
-30
-0.0025
-0.005
-0.0075
-0.01
-60
-90
-120
-150
-180
0.1
0.2
0.3
0.4
0.5
0
0.01
0.02
0.03
0.04
0.05
0.06
Normalized to Filter Input Sample Rate
Normalized to Filter Input Sample Rate
D057
D058
Figure 53. Decimate by 8 - Stopband Response
Figure 54. Decimate by 8 - Passband Response
30
0
0.0025
0
Filter Response
-80dB
-30
-0.0025
-0.005
-0.0075
-0.01
-60
-90
-120
-150
-180
0.1
0.2
0.3
0.4
0.5
0
0.01
0.02
0.03
0.04
0.05
Normalized to Filter Input Sample Rate
Normalized to Filter Input Sample Rate
D059
D060
Figure 55. Decimate by 10 - Stopband Response
Figure 56. Decimate by 10 - Passband Response
28
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Typical Characteristics (continued)
Unless otherwise noted, these specifications apply for V(VA12) = V(VD12) = 1.2 V, V(VA19) = 1.9 V, VIN FSR (AC coupled) =
Default setting, differential AC-coupled sinewave input clock, ƒ(DEVCLK) = 2.7 or 1.6 GHz at 0.5 VPP with 50% duty cycle,
R(RBIAS) = 3.3 kΩ ±0.1%, after a Foreground mode calibration with Timing Calibration enabled. TA = 25°C. VI = –1 dBFS.
30
0.0025
Filter Response
-80dB
0
0
-30
-0.0025
-0.005
-0.0075
-0.01
-60
-90
-120
-150
-180
0
0
0
0.1
0.2
0.3
0.4
0.5
0
0.006
0.012
0.018
0.024
0.03
Normalized to Filter Input Sample Rate
Normalized to Filter Input Sample Rate
D061
D062
Figure 57. Decimate by 16 - Stopband Response
Figure 58. Decimate by 16 - Passband Response
30
0
0.0025
0
Filter Response
-80dB
-30
-0.0025
-0.005
-0.0075
-0.01
-60
-90
-120
-150
-180
0.1
0.2
0.3
0.4
0.5
0
0.005
0.01
0.015
0.02
0.025
Normalized to Filter Input Sample Rate
Normalized to Filter Input Sample Rate
D063
D064
Figure 59. Decimate by 20 - Stopband Response
Figure 60. Decimate by 20 - Passband Response
30
0
0.0025
0
Filter Response
-30
-0.0025
-0.005
-0.0075
-0.01
-60
-90
-120
-150
-180
0.1
0.2
0.3
0.4
0.5
0
0.003
0.006
0.009
0.012
0.015
Normalized to Filter Input Sample Rate
Normalized to Filter Input Sample Rate
D065
D066
Figure 61. Decimate by 32 - Stopband Response
Figure 62. Decimate by 32 - Passband Response
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7 Detailed Description
7.1 Overview
The ADC12J1600 and ADC12J2700 devices are an ultra-wideband sampling and digital tuning subsystem. The
devices combine a very-wideband and high sampling-rate ADC front-end with a configurable digital-down
conversion block. This combination provides the necessary features to facilitate the development of flexible
software-defined radio products for a wide range of communications applications.
The ADC12J1600 and ADC12J2700 devices are based on an ultra high-speed ADC core. The core uses an
interleaved calibrated folding and interpolating architecture that results in very high sampling rate, very good
dynamic performance, and relatively low-power consumption. This ADC core is followed by a configurable DDC
block which is implemented on a small geometry CMOS. The DDC block provides a range of decimation settings
that allow the product to work in ultra-wideband, wideband, and more-narrow-band receive systems. The output
data from the DDC block is transmitted through a JESD204B-compatible multi-lane serial-output system. This
system minimizes the number of data pairs required to convey the output data to the downstream processing
circuitry.
7.2 Functional Block Diagram
DS7+/NCO_2
Buffer
DS7œ/NCO_2
VIN+
ADC
VINœ
DS6+/NCO_1
DDC
DS6œ/NCO_1
VCM
REF
VCMO
DS5+/NCO_0
DS5œ/NCO_0
VBG
RBIAS+
RBIASœ
DDC
Bypass
DS4+
DS4œ
DEVCLK+
DS3+
DS3œ
DEVCLKœ
Clock
Sync
VCM CLK
DS2+
SYSREF+
DS2œ
SYSREFœ
DS1+
DS1œ
SYNC~/TMST+
SYNC~/TMSTœ
SYNC~
DS0+
DS0œ
OR_T0
OR_T1
Overrange
Detection
TDIODE+
TDIODEœ
SCS
SCLK
SDI
Configuration
Registers
SPI
Interface
SDO
30
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Functional Block Diagram (continued)
Configurable 32-bit NCO
and Mixer
Configurable
Decimation Filters
15 bit I
Filter
Filter
Complex Baseband
Output
12 bit
15 bit Q
90°
Oscillator
Figure 63. DDC Details Block Diagram
7.3 Feature Description
7.3.1 Signal Acquisition
The analog input is sampled on the rising edge of CLK and the digital equivalent of that data is available in the
serialized datastream t(LAT) or t(LAT_DDC) input clock cycles later.
The ADC12J1600 and ADC12J2700 devices convert as long as the input clock signal is present. The fully-
differential comparator design and the innovative design of the sample-and-hold amplifier, together with
calibration, enables very good performance at input frequencies beyond 3 GHz. The ADC12J1600 and
ADC12J2700 data is output on a high-speed serial JESD204B interface.
7.3.2 The Analog Inputs
A differential input signal must be used to drive the ADC12J1600 and ADC12J2700 devices. Operation with a
single-ended signal is not recommended as performance suffers. The input signals can be either be AC coupled
or DC coupled. The analog inputs are internally connected to the VCMO bias voltage. When DC-coupled input
signals are used, the common mode voltage of the applied signal must meet the device Input common mode
requirements. See VCMI in the Recommended Operating Conditions table.
The full-scale input range for each converter can be adjusted through the serial interface. See the Full Scale
Range Adjust section.
The buffered analog inputs simplify the task of driving these inputs and the RC pole that is generally used at
sampling ADC inputs is not required. If an amplifier circuit before the ADC is desired, use care when selecting an
amplifier with adequate noise and distortion performance and adequate gain at the frequencies used for the
application. If gain is not required, a balun (balanced-to-unbalanced transformer) is generally used to provide
single ended (SE) to differential conversion.
The input impedance of VIN± consists of two 50-Ω resistors in series between the inputs and a capacitance from
each of these inputs to ground. A resistance of approximately 20 kΩ exists from the center point of the 50-Ω
resistors to the on-chip VCMO providing self-biasing for AC-coupled applications.
Performance is good in both DC-coupled mode and AC coupled mode, provided the common-mode voltage at
the analog input is within specifications.
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Feature Description (continued)
7.3.2.1 Input Clamp
The ADC12J1600 and ADC12J2700 maximum DC input voltage is limited to the range 0 to 2 V to prevent
damage to the device. To help maintain these limits, an active input clamping circuit is incorporated which
sources or sinks input currents up to ±50 mA. The clamping circuit is enabled by default and is controlled via the
Input_Clamp_EN bit (register 0x034, bit 5). The protection provided by this circuit is limited as follows:
•
•
Shunt current-clamping is only effective for non-zero source impedances.
At frequencies above 3 GHz the clamping is ineffective because of the finite turn-on and turn-off time of the
switch.
With these limitations in mind, analysis has been done to determine the allowable input signal levels as a
function of input frequency when the Input Clamp is enabled, assuming the source impedance matches the input
impedance of the device (100-Ω differential). This information is incorporated in the Absolute Maximum Ratings
table.
7.3.2.2 AC Coupled Input Usage
The easiest way to accomplish SE-to-differential conversion for AC-coupled signals is with an appropriate balun.
C
(couple)
VIN+
50-ꢀ
Source
R(VIN)
VINœ
1:2 Balun
C
(couple)
Figure 64. Single-Ended-to-Differential Signal Conversion With a Balun
Figure 64 shows a generic depiction of a SE-to-differential signal conversion using a balun. The circuitry specific
to the balun depends on the type of balun selected and the overall board layout. TI recommends that the system
designer contact the manufacturer of the selected balun to aid in designing the best performing single-ended to
differential conversion circuit using that particular balun.
When selecting a balun, understanding the input architecture of the ADC is important. Specific balun parameters
must be considered. The balun must match the impedance of the analog source to the on-chip 100-Ω differential
input termination of the ADC12J1600 and ADC12J2700 devices. The range of this input termination resistor is
described in the Electrical Characteristics table as the specification RID.
Also, as a result of the ADC architecture, the phase and amplitude balance are important. The lowest possible
phase and amplitude imbalance is desired when selecting a balun. The phase imbalance must be no more than
±2.5° and the amplitude imbalance must be limited to less than 1 dB at the desired input frequency range.
Finally, when selecting a balun, the voltage standing-wave ratio (VSWR), bandwidth, and insertion loss of the
balun must also be considered. The VSWR aids in determining the overall transmission line termination
capability of the balun when interfacing to the ADC input. The insertion loss must be considered so that the
signal at the balun output is within the specified input range of the ADC as described in the Electrical
Characteristics table as the specification VID.
Table 1 lists the recommended baluns for specific signal frequency ranges.
Table 1. Balun Recommendations
MINIMUM
MAXIMUM
IMPEDANCE RATIO
PART NUMBER
MANUFACTURER
FREQUENCY (MHz) FREQUENCY (MHz)
4.5
400
30
3000
3000
1800
4000
1:1
1:2
1:2
1:2
TC1-1-13MA+
B0430J50100AHF
ADTL2-18+
Mini-Circuits
Anaren
Mini-Circuits
Mini-Circuits
10
TCM2-43X+
32
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7.3.2.3 DC Coupled Input Usage
When a DC-coupled signal source is used, the common mode voltage of the applied signal must be within a
specified range (VCMI). To achieve this range, the common mode of the driver should be based on the VCMO
output provided for this purpose.
Full-scale distortion performance degrades as the input common-mode voltage deviates from VCMO. Therefore,
maintaining the input common-mode voltage within the VCMI range is important.
Table 2 lists the recommended amplifiers for DC-coupled usage or if AC-coupling with gain is required.
Table 2. Amplifier Recommendations
–3-dB BANDWIDTH (MHz)
MIN GAIN (dB)
MAX GAIN (dB)
GAIN TYPE
Fixed
PART NUMBER
LMH3401
7000
2800
2400
900
16
0
16
17
Resistor set
LMH6554
6
26
Digital programmable
Digital programmable
LMH6881
–1.16
38.8
LMH6518
7.3.2.4 Handling Single-Ended Input Signals
The ADC12J1600 and ADC12J2700 devices have no provision to adequately process single-ended input signals.
The best way to handle single-ended signals is to convert these signals to balanced differential signals before
presenting the signals to the ADC.
7.3.3 Clocking
The ADC12J1600 and ADC12J2700 devices have a differential clock input, DEVCLK+ and DEVCLK–, that must
be driven with an AC-coupled differential clock-signal. The clock inputs are internally terminated and biased. The
input clock signal must be capacitively coupled to the clock pins as shown in Figure 65.
C
(couple)
CLK+
C
(couple)
CLKœ
Figure 65. Differential Sample-Clock Connection
The differential sample-clock line pair must have a characteristic impedance of 100 Ω and must be terminated at
the clock source of that 100-Ω characteristic impedance. The input clock line must be as short and direct as
possible. The ADC12J1600 and ADC12J2700 clock input is internally terminated with an untrimmed 100-Ω
resistance.
Insufficient input clock levels results in poor dynamic performance. Excessively-high input-clock levels can cause
a change in the analog-input offset voltage. To avoid these issues, maintain the input clock level within the range
specified in the Electrical Characteristics table.
The low times and high times of the input clock signal can affect the performance of any ADC. The ADC12J1600
and ADC12J2700 devices feature a duty-cycle clock-correction circuit which maintains performance over
temperature. The ADC meets the performance specification when the input clock high times and low times are
maintained as specified in the Electrical Characteristics table.
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High-speed high-performance ADCs such as the ADC12J1600 and ADC12J2700 devices require a very-stable
input clock-signal with minimum phase noise or jitter. ADC jitter requirements are defined by the ADC resolution
or ENOB (effective number of bits), maximum ADC input frequency, and the input signal amplitude relative to the
ADC input full-scale range. Use Equation 1 to calculate the maximum jitter (the sum of the jitter from all sources)
allowed to prevent a jitter-induced reduction in SNR.
VFSR
1
RMStot(J)
=
ì
2(n+1) ì p ì F
V
I(PP)
IN
where
•
•
•
•
•
RMStot(J) is the RMS total of all jitter sources in seconds
VI(PP) is the peak-to-peak analog input signal
VFSR is the full-scale range of the ADC
n is the ADC resolution in bits
FIN is the maximum input frequency, in Hertz, at the ADC analog input
(1)
Note that the maximum jitter previously described is the root sum square (RSS) of the jitter from all sources,
including that from the clock source, the jitter added by noise coupling at board level and that added internally by
the ADC clock circuitry, in addition to any jitter added to the input signal. Because the effective jitter added by the
ADC is beyond user control, the best option is to minimize the jitter from the clock source, the sum of the
externally-added input clock jitter and the jitter added by any circuitry to the analog signal.
Input clock amplitudes above those specified in the Recommended Operating Conditions table can result in
increased input-offset voltage. Increased input-offset voltage causes the converter to produce an output code
other than the expected 2048 when both input pins are at the same potential.
7.3.4 Over-Range Function
To ensure that system-gain management has the quickest-possible response time, a low-latency configurable
over-range function is included. The over-range function works by monitoring the raw 12-bit samples exiting the
ADC module. The upper 8 bits of the magnitude of the ADC data are checked against two programmable
thresholds, OVR_T0 and OVR_T1. The following table lists how a raw ADC value is converted to an absolute
value for a comparison of the thresholds.
ADC SAMPLE
(OFFSET BINARY)
ADC SAMPLE
(2's COMPLEMENT)
UPPER 8 BITS USED FOR
COMPARISON
ABSOLUTE VALUE
1111 1111 1111 (4095)
1111 1111 0000 (4080)
1000 0000 0000 (2048)
0000 0001 0000 (16)
0000 0000 0000 (0)
0111 1111 1111 (+2047)
0111 1111 0000 (+2032)
0000 0000 0000 (0)
111 1111 1111 (2047)
111 1111 0000 (2032)
000 0000 0000 (0)
1111 1111 (255)
1111 1110 (254)
0000 0000 (0)
1000 0001 0000 (-2032)
1000 0000 0000 (-2048)
111 1111 0000 (2032)
111 1111 1111 (2047)
1111 1110 (254)
1111 1111 (255)
If the upper 8 bits of the absolute value equal or exceed the OVR_T0 or OVR_T1 threshold during the monitoring
period, then the over-range bit associated with the threshold is set to 1, otherwise the over-range bit is 0. The
resulting over-range bits are embedded into the complex output data samples and output on OR_T0 and OR_T1.
Table 3 lists the outputs, related data samples, threshold settings and the monitoring period equation.
Table 3. Threshold and Monitor Period for Embedded OR Bits
EMBEDDED OVER-RANGE
OUTPUTS
MONITORING PERIOD
(ADC SAMPLES)
ASSOCIATED THRESHOLD
ASSOCIATED SAMPLES
OR_T0
OR_T1
OVR_T0
OVR_T1
In-Phase (I) samples
2OVR_N(1)
Quadrature (Q) samples
(1) OVR_N is the monitoring period register setting.
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Table 4. Over-Range Monitoring Period
OVR_N
MONITORING PERIOD
0
1
2
3
4
5
6
7
1
2
4
8
16
32
64
128
Typically, the OVR_T0 threshold can be set near the full-scale value (228 for example). When the threshold is
triggered, a typical system can turn down the system gain to avoid clipping. The OVR_T1 threshold can be set
much lower. For example, the OVR_T1 threshold can be set to 64 (−12 dBFS). If the input signal is strong, the
OVR_T1 threshold is tripped occasionally. If the input is quite weak, the threshold is never tripped. The
downstream logic device monitors the OVR_T1 bit. If OVR_T1 stays low for an extended period of time, then the
system gain can be increased until the threshold is occasionally tripped (meaning the peak level of the signal is
above −12 dBFS).
The OR_T0 threshold is embedded as the LSB along with the upper 15 bits of every complex I sample. The
OR_T1 threshold is embedded as the LSB along with the upper 15 bits of every complex Q sample.
7.3.5 ADC Core Features
7.3.5.1 The Reference Voltage
The reference voltage for the ADC12J1600 and ADC12J2700 devices is derived from an internal bandgap
reference. A buffered version of the reference voltage is available at the VBG pin for user convenience. This
output has an output-current capability of ±100 μA. The VBG output must be buffered if more current is required.
No provision exists for the use of an external reference voltage, but the full-scale input voltage can be adjusted
through the full-scale-range register settings.
7.3.5.2 Common-Mode Voltage Generation
The internal reference voltage is used to generate a stable common-mode voltage reference for the analog
Inputs and the DEVCLK and SYSREF differential-clock inputs.
7.3.5.3 Bias Current Generation
An external bias resistor, in combination with the on-chip voltage reference is used to provide an accurate and
stable source of bias currents for internal circuitry. Using an external accurate resistor minimizes variation in
device power consumption and performance.
7.3.5.4 Full Scale Range Adjust
The ADC input full-scale range can be adjusted through the GAIN_FS register setting (registers 0x022 and
0x023). The adjustment range is approximately 500 mVPP to 950 mVPP. The full-scale range adjustment is useful
for matching the input-signal amplitude to the ADC full scale, or to match the full-scale range of multiple ADCs
when developing a multi-converter system.
7.3.5.5 Offset Adjust
The ADC-input offset voltage can be adjusted through the OFFSET_FS register setting (registers 0x025 and
0x026). The adjustment range is approximately 28 mV to –28 mV differential.
NOTE
Offset adjust has no effect when background calibration mode is enabled.
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7.3.5.6 Power-Down
The power-down bit (PD) allows the ADC12J1600 and ADC12J2700 devices to be entirely powered down. The
serial data output drivers are disabled when PD is high. When the device returns to normal operation, the
JESD204 link must be re-established, and the ADC pipeline and decimation filters contain meaningless
information and must be flushed.
7.3.5.7 Built-In Temperature Monitor Diode
A built-in thermal monitoring diode junction is made available on the TDIODE+ and TDIODE– pins. This diode
facilitates temperature monitoring and characterization of the device in higher ambient temperature
environments. While the on-chip diode is not highly characterized, the diode can be used effectively by
performing a baseline measurement at a known ambient or board temperature with the device in power-down
(PD) mode. Recommended monitoring ICs include the LM95233 device and similar remote-diode temperature
monitoring products from Texas Instruments.
7.3.6 Digital Down Converter (DDC)
The digitized data is the input to the digital down-converter block. This block provides frequency conversion and
decimation filtering to allow a specific range of frequencies to be selected and output in the digital data stream.
7.3.6.1 NCO/Mixer
The DDC contains a complex numerically-controlled oscillator and a complex mixer. The oscillator generates a
complex exponential sequence shown in Equation 2.
x[n] = ejωn
(2)
The frequency (ω) is specified by the a 32-bit register setting. The complex exponential sequence is multiplied by
the real input from the ADC to mix the desired carrier down to 0 Hz.
7.3.6.2 NCO Settings
7.3.6.2.1 NCO Frequency Phase Selection
Within the DDC, eight different frequency and phase settings are always available for use. Each of the eight
settings uses a different phase accumulator within the NCO. Because all eight phase accumulators are
continuously running independently, rapid switching between different NCO frequencies is possible allowing rapid
tuning of different signals.
The specific frequency-phase pair in use is selected through either the NCO_x input pins, or the NCO_SEL
configuration bits (register 0x20D, bits 2:0). The CFG_MODE bit (register 0x20C, bit 0) is used to choose
whether the input pins or selection bits are used. When the CFG_MODE bit is set to 0, the NCO_x input pins
select the active NCO frequency and phase setting. When the CFG_MODE bit is set to 1, the NCO_SEL register
settings select the active NCO frequency and phase setting.
The frequency for each phase accumulator is programmed independently through the NCO_FREQn (and
optionally NCO_RDIV) settings. The phase offset for each accumulator is programmed independently through
the NCO_PHASEn register settings.
7.3.6.2.2 NCO_0, NCO_1, and NCO_2 (NCO_x)
When the CFG_MODE bit is set to 0, the state of these three inputs determines the active NCO frequency and
phase accumulator settings.
7.3.6.2.3 NCO_SEL Bits (2:0)
When the CFG_MODE bit is set to 1, the state of these register bits determines the active NCO frequency and
phase accumulator settings.
36
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7.3.6.2.4 NCO Frequency Setting (Eight Total)
7.3.6.2.4.1 Basic NCO Frequency-Setting Mode
In basic NCO frequency-setting mode, the NCO frequency setting is set by the 32-bit register value,
NCO_FREQn (n = preset 0 trough 7, see the NCO Frequency (Preset x) Register section).
(n = 0 – 7) ƒ(NCO) = NCO_FREQn × 2–32 × ƒ(DEVCLK)
(3)
NOTE
Changing the register setting after the JESD204B interface is running results in non-
deterministic NCO phase. If deterministic phase is required, the JESD204B link must be
re-initialized after changing the register setting. See the Multiple ADC Synchronization
section.
7.3.6.2.4.2 Rational NCO Frequency Setting Mode
In basic NCO frequency mode, the frequency step size is very small and many frequencies can be synthesized,
but sometimes an application requires very specific frequencies that fall between two frequency steps. For
example with ƒS equal to 2457.6 MHz and a desired ƒ(NCO) equal to 5.02 MHz the value for NCO_FREQ is
8773085.867. Truncating the fractional portion results in an ƒ(NCO) equal to 5.0199995 MHz, which is not the
desired frequency.
To produce the desired frequency, the NCO_RDIV parameter is used to force the phase accumulator to arrive at
specific frequencies without error. First, select a frequency step size (ƒ(STEP)) that is appropriate for the NCO
frequency steps required. The typical value of ƒ(STEP) is 10 kHz. Next, program the NCO_RDIV value according
to Equation 4.
≈
’
ƒ(DEVCLK)
ƒ(STEP)
128
∆
∆
«
÷
÷
◊
NCO_RDIV =
(4)
The result of Equation 4 must be an integer value. If the value is not an integer, adjust either of the parameters
until the result in an integer value.
For example, select a value of 1920 for NCO_RDIV.
NOTE
NCO_RDIV values larger than 8192 can degrade the NCO SFDR performance and are
not recommended.
Now use Equation 5 to calculate the NCO_FREQ register value.
225 ì N
NCO _RDIV
≈
’
NCO _FREQ = round ì
∆
∆
÷
÷
«
◊
(5)
Alternatively, the following equations can be used:
ƒ(NCO)
N =
ƒ(STEP)
(6)
(7)
225 ì N
NCO _RDIV
≈
’
NCO _FREQ = round ì
∆
∆
÷
÷
«
◊
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Table 5. Common NCO_RDIV Values (For 10-kHz Frequency Steps)
ƒ(DEVCLK) (MHz)
2457.6
NCO_RDIV
1920
1966.08
1536
1474.56
1152
1228.8
960
7.3.6.2.5 NCO Phase-Offset Setting (Eight Total)
The NCO phase-offset setting is set by the 16-bit register value NCO_PHASEn (n = preset 0 trough 7, see the
NCO Phase (Preset x) Register section). The value is left-justified into a 32-bit field and then added to the phase
accumulator.
Use Equation 8 to calculate the phase offset in radians.
NCO_PHASEn × 2–16 × 2 × π
(8)
NOTE
Changing the register setting after the JESD204B interface is running results in non-
deterministic NCO phase. If deterministic phase is required, the JESD204B link must be
re-initialized after changing the register setting. See Multiple ADC Synchronization.
7.3.6.2.6 Programmable DDC Delay
The DDC Filter elements incorporate a programmable sample delay. The delay can be programmed from 0 to
(decimation setting – 0.5) ADC sample periods. The delay step-size is 0.5 ADC sample periods. The delay
settings are programmed through the DDC_DLYn parameter.
Table 6. Programmable DDC Delay Range
D (Decimation Setting)
Min Delay (t(DEVCLK)
)
Max Delay (t(DEVCLK))
4
0
0
0
0
0
0
3.5
7.5
8
10
16
20
32
9.5
15.5
19.5
31.5
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7.3.6.3 Decimation Filters
The decimation filters are arranged to provide a programmable overall decimation of 4, 8, 10, 16, 20, or 32. The
input and output of each filter is complex. The output data consists of 15-bit complex baseband information.
Table 7 lists the effective output sample rates.
Table 7. Output Sample Rates
COMPLEX SAMPLE OUTPUT RATE AND RESULTING BANDWIDTH
(OUTPUT SAMPLE = 15-BIT I + 15-BIT Q + 2-BIT OR)
ƒ(DEVCLK)
ƒ(DEVCLK) = 4000 MHz
DECIMATION
SETTING
ALIAS
PROTECTED
BANDWIDTH
(MHz)
ALIAS
PROTECTED
BANDWIDTH
(MHz)
RAW OUTPUT
BANDWIDTH
(MHz)
RAW OUTPUT
BANDWIDTH
(MHz)
OUTPUT RATE
(MSPS)
OUTPUT RATE
(MSPS)
4
ƒ(DEVCLK) / 4
ƒ(DEVCLK) / 8
ƒ(DEVCLK) / 10
ƒ(DEVCLK) / 16
ƒ(DEVCLK) / 20
ƒ(DEVCLK) / 32
ƒ(DEVCLK) / 4
ƒ(DEVCLK)N / 8
ƒ(DEVCLK) / 10
ƒ(DEVCLK) / 16
ƒ(DEVCLK) / 20
ƒ(DEVCLK) / 32
0.8 × ƒ(DEVCLK) / 4
0.8 × ƒ(DEVCLK) / 8
0.8 × ƒ(DEVCLK) / 10
0.8 × ƒ(DEVCLK) / 16
0.8 × ƒ(DEVCLK) / 20
0.8 × ƒ(DEVCLK) / 32
1000
500
400
250
200
125
1000
500
400
250
200
125
800
400
320
200
160
100
8
10
16
20
32
For maximum efficiency a group of high speed filter blocks are implemented with specific blocks used for each
decimation setting. The first table below describes the combination of filter blocks used for each decimation
setting. The next table lists the coefficient details and decimation factor of each filter block.
Table 8. Decimation Mode Filter Usage
Decimation Setting
Filter Blocks Used
CS19, CS55
4
8
CS11, CS15, CS55
CS11, CS139
10
16
20
32
CS7, CS11, CS15, CS55
CS7, CS11, CS139
CS7, CS7, CS11, CS15, CS55
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Table 9. Filter Coefficient Details
Filter Coefficient Set (Decimation Factor of Filter)
CS7 (2)
CS11 (2)
CS15 (2)
CS19 (2)
CS55 (2)
CS139 (5)
–5
–65
0
–65
0
109
0
109
0
–327
0
–327
0
22
0
22
0
–37
–37
0
–5
–9
0
–9
577
1024
577
–837
0
–837
0
2231
0
2231
0
–174
0
–174
0
118
118
0
–9
–9
0
–291
0
–5
–5
4824
8192
4824
–8881
0
–8881
0
744
0
744
0
–291
0
0
0
20
20
39742
65536
39742
–2429
0
–2429
0
612
0
612
0
33
33
33
33
10029
16384
10029
–1159
0
–1159
0
21
21
0
0
2031
0
2031
0
–54
–88
–89
–56
0
–54
–88
–89
–56
0
–3356
0
–3356
0
5308
0
5308
0
119
196
199
125
0
119
196
199
125
0
–8140
0
–8140
0
12284
0
12284
0
–18628
0
–18628
0
–234
–385
–393
–248
0
–234
–385
–393
–248
0
29455
0
29455
0
–53191
0
–53191
0
422
696
711
450
0
422
696
711
450
0
166059
262144
166059
–711
–711
–1176
–1206
–766
0
–1176
–1206
–766
0
1139
1893
1949
1244
0
1139
1893
1949
1244
0
–1760
–2940
–3044
–1955
0
–1760
–2940
–3044
–1955
0
2656
4472
4671
3026
0
2656
4472
4671
3026
0
–3993
–6802
–7196
–4730
0
–3993
–6802
–7196
–4730
0
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Table 9. Filter Coefficient Details (continued)
Filter Coefficient Set (Decimation Factor of Filter)
CS7 (2)
CS11 (2)
CS15 (2) CS19 (2)
CS55 (2)
CS139 (5)
6159
6159
10707
11593
7825
10707
11593
7825
0
0
–10423
–18932
–21629
–15618
0
–10423
–18932
–21629
–15618
0
24448
52645
78958
97758
104858
24448
52645
78958
97758
7.3.6.4 DDC Output Data
The DDC output data consist of 15-bit complex data plus the two over-range threshold-detection control bits. The
following table lists the data format:
16-BIT OUTPUT WORD
CHANNEL 15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
I
DDC Output In-Phase (I) 15 bit
OR_T0
OR_T1
Q
DDC Output Quadrature (Q) 15 bit
7.3.6.5 Decimation Settings
7.3.6.5.1 Decimation Factor
The decimation setting is adjustable over the following settings:
•
•
•
•
•
•
•
Bypass — no decimation
Decimate-by-4
Decimate-by-8
Decimate-by-10
Decimate-by-16
Decimate-by-20
Decimate-by-32
NOTE
Because the output format is complex I+Q, the effective output bandwidth is approximately
two-times the value for a real output with the same decimation factor.
7.3.6.5.2 DDC Gain Boost
The DDC gain boost (register 0x200, bit 4) provides additional gain through the DDC block. With a setting of 1
the final filter has 6.02-dB gain. With a setting of 0, the final filter has a 0-dB gain. This setting is recommended
when the NCO is set near DC.
7.3.7 Data Outputs
The data outputs (DSx±) are very high-speed differential outputs and conform to the JESD204B JEDEC
standard. A CML (current-mode logic)-type output driver is used for each output pair. Output pre-emphasis is
adjustable to compensate for longer PCB-trace lengths.
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7.3.7.1 The Digital Outputs
The ADC12J1600 and ADC12J2700 output data is transmitted on up to eight high-speed serial-data lanes. The
output data from the ADC or DDC is formatted to the eight lanes, 8b10b encoded, and serialized. Up to four
different serial output rates are possible depending on the decimation mode setting: 1x, 1.25x, 2x, and 2.5x. In 1x
mode, the output serializers run at the same bit rate as the frequency of the applied DEVCLK. In 1.25x mode, the
output serializers run at a bit rate that is 1.25-times that of the applied DEVCLK, and so on. For example, for a
1.6-GHz input DEVCLK, the output rates are 1.6 Gbps in 1x mode, 2 Gbps in 1.25x mode, 3.2 Gbps in 2x mode
and 4 Gbps in 2.5x mode.
7.3.7.2 JESD204B Interface Features and Settings
7.3.7.2.1 Scrambler Enable
Scrambling randomizes the 8b10b encoded data, spreading the frequency content of the data interface. This
reduces the peak EMI energy at any given frequency reducing the possibility of feedback to the device inputs
impacting performance. The scrambler is disabled by default and is enabled via SCR (register 0x201, bit 7).
7.3.7.2.2 Frames Per Multi-Frame (K-1)
The frames per multi-frame (K) setting can be adjusted within constraints that are dependant on the selected
decimation (D) and serial rate (DDR) settings. The K-minus-1 (KM1) register setting (register 0x201, bits 6:2)
must be one less than the desired K setting.
7.3.7.2.3 DDR
The serial rate can be either 1ƒ(CLK) (DDR = 0) or 2ƒ(CLK) (DDR = 1).
7.3.7.2.4 JESD Enable
The JESD interface must be disabled (JESD_EN is set to 0) while any of the other JESD parameters are
changed. While JESD_EN is set 0 the block is held in reset and the serializers are powered down. The clocks for
this section are also gated off to further save power. When the parameters have been set as desired the JESD
block can be enabled (JESD_EN is set to 1).
7.3.7.2.5 JESD Test Modes
Several different JESD204B test modes are available to assist in link verification and debugging. The list of
modes follows.
NOTE
PRBS test signals are output directly, without 8b10b encoding.
•
•
•
•
•
•
•
•
•
•
•
•
Normal operation
PRBS7 test mode
PRBS15 test mode
PRBS23 test mode
Ramp test mode
Short or long transport-layer test mode
D21.5 test mode
K28.5 test mode
Repeated ILA test mode
Modified RPAT test mode
Serial-outputs differential 0 test mode
Serial-outputs differential 1 test mode
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7.3.7.2.6 Configurable Pre-Emphasis
The high-speed serial-output drivers incorporate a configurable pre-emphasis feature. This feature allows the
output drive waveform to be optimized for different PCB materials and signal transmission distances. The pre-
emphasis setting is adjusted through the serializer pre-emphasis setting in register 0x040, bits 3 to 0. The default
setting is 4d. Higher values will increase the pre-emphasis to compensate for more lossy PCB materials. This
adjustment is best used in conjunction with an eye-diagram analysis capability in the receiver. The pre-emphasis
setting should be adjusted to optimize the eye-opening for the hardware configuration and line rates needed.
7.3.7.2.7 Serial Output-Data Formatting
Output data is generated by the DDC then formatted according to the selected decimation and output rate
settings. When less than the maximum of eight lanes are active, lanes are disabled beginning with the highest
numerical lanes. For example when only two lanes are active, lanes 0 and 1 are active, while all higher lanes are
inactive.
Table 10. Parameter Definitions
USER
CONFIGURED
OR DERIVED
STANDARD
JESD204B LINK
PARAMETER
PARAMETER
DESCRIPTION
D
Decimation factor, determined by DMODE register
Serial line rate: 1 = DDR rate (2x), 0 = SDR rate (1x)
Enable 5/4 PLL to increase line rate by 1.25x.
0 = no PLL (1x), 1 = enable PLL (1.25x)
Number of frames per multiframe
User
User
User
No
No
No
DDR
P54
K
N
User
Yes
Yes
Yes
Bits per sample (before adding control bits and tails bits)
Control bits per sample
Derived
Derived
CS
Bits per sample (after adding control bits and tail bits). Must be a multiple of
4.
N’
Derived
Yes
L
F
Number of serial lanes
Derived
Derived
Derived
Derived
Derived
Yes
Yes
Yes
Yes
Yes
Number of octets (bytes) per frame (per lane)
Number of (logical) converters
M
S
Number of samples per converter per frame
Number of control words per frame
CF
1=High density mode (samples may be broken across lanes), 0 = normal
mode (samples may not be broken across lanes)
HD
KS
Derived
Derived
Yes
No
Legal adjustment step for K, to ensure that the multi-frame clock is a sub-
harmonic of other internal clocks
Table 11. Serial Link Parameters(1)
USER SPECIFIED PARAMETERS
DECIMATION
DERIVED PARAMETERS
OTHER INFORMATION
LEGAL K
RANGE
BIT RATE / ADC
CLOCK(2)
DDR
P54
N
CS
N’
L
F
M
S
KS
FACTOR (D)
1
4
1
1
1
0
0
1
1
0
1
0
0
0
0
1
0
1
0
1
0
0
0
1
12
15
15
15
15
15
15
15
15
15
15
0
1
1
1
1
1
1
1
1
1
1
12
16
16
16
16
16
16
16
16
16
16
8
5
4
5
4
3
2
4
2
3
2
8
4
2
4
2
8
2
2
2
8
2
8
2
2
2
2
2
2
2
2
2
2
5
5
2
5
2
5
1
2
1
5
1
2
4
2
2
1
2
2
4
8
1
1
4-32
8-32
2x
2x
4
10-32
6-32
2.5x
1x
8
8
9-32
1.25x
2x
8
4-32
8
10-32
12-32
16-32
3-32
2.5x
1x
10
10
16
16
2x
1x
9-32
1.25x
(1) In all modes: HD = 0 and CF = 0
(2) x = times (for example, 2x = 2-times)
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Table 11. Serial Link Parameters() (continued)
USER SPECIFIED PARAMETERS
DECIMATION
DERIVED PARAMETERS
OTHER INFORMATION
LEGAL K
RANGE
BIT RATE / ADC
CLOCK(2)
DDR
P54
N
CS
N’
L
F
M
S
KS
FACTOR (D)
16
16
20
20
32
32
32
1
1
0
1
0
0
1
0
1
0
0
0
1
0
15
15
15
15
15
15
15
1
1
1
1
1
1
1
16
16
16
16
16
16
16
2
1
2
1
2
1
1
16
4
2
2
2
2
2
2
2
5
1
1
1
5
1
5
1
1
4
4
1
1
1
2-32
5-32
12-32
8-32
2-32
5-32
1-32
2x
2.5x
1x
2
4
2x
16
4
1x
1.25x
2x
32
Output data is formatted in a specific optimized fashion for each decimation and DDR setting combination. For
bypass mode (decimation = 1) the 12-bit offset binary values are mapped to the 8-bit characters. For the DDC
mode the 16-bit values (15-bit complex data plus 1 bit OR_Tn) are mapped to the 8-bit characters. The following
tables list the specific mapping formats. In all mappings the T or tail bits are 0 (zero).
Table 12. Bypass Mode, No Decimation, DDR = 1, P54 = 0, LMF = 8,8,8
TIME →
CHAR
0
1
2
3
4
5
6
7
NUMBER
Lane 0
Lane 1
Lane 2
Lane 3
Lane 4
Lane 5
Lane 6
Lane 7
C0S0
C1S0
C2S0
C3S0
C4S0
C5S0
C6S0
C7S0
C0S1
C1S1
C2S1
C3S1
C4S1
C5S1
C6S1
C7S1
C0S2
C1S2
C2S2
C3S2
C4S2
C5S2
C6S2
C7S2
C0S3
C1S3
C2S3
C3S3
C4S3
C5S3
C6S3
C7S3
C0S4
C1S4
C2S4
C3S4
C4S4
C5S4
C6S4
C7S4
T
T
T
T
T
T
T
T
Frame n
Table 13. Bypass Mode, No Decimation, DDR = 1, P54 = 0, Composite View of Interleaved Converters
TIME →
CHAR
0
1
2
3
4
5
6
7
NUMBER
Lane 0
Lane 1
Lane 2
Lane 3
Lane 4
Lane 5
Lane 6
Lane 7
S0
S1
S2
S3
S4
S5
S6
S7
S8
S16
S17
S18
S19
S20
S21
S22
S23
S24
S25
S26
S27
S28
S29
S30
S31
S32
S33
S34
S35
S36
S37
S38
S39
T
T
T
T
T
T
T
T
S9
S10
S11
S12
S13
S14
S15
Frame n
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Table 14. Decimate-by-4, DDR = 1, P54 = 0, LMF = 5,2,4
TIME →
CHAR NUMBER
Lane 0
0
1
2
3
I0
I2
I1
Lane 1
I3
Lane 2
I4
Q0
Q2
Q4
Lane 3
Q1
Q3
Lane 4
Frame n
Table 15. Decimate-by-4, DDR = 1, P54 = 1, LMF = 4,2,2
TIME →
CHAR NUMBER
Lane 0
0
1
2
3
4
5
I0
I1
I2
I3
I4
I5
Lane 1
Lane 2
Q0
Q1
Q2
Q3
Q4
Q5
Lane 3
Frame
n
Frame
n + 1
Frame
n + 2
Table 16. Decimate-by-8, DDR = 0, P54 = 0, LMF = 5,2,4
TIME →
CHAR NUMBER
Lane 0
0
1
2
3
I0
I2
I1
Lane 1
I3
Lane 2
I4
Q0
Q2
Q4
Lane 3
Q1
Q3
Lane 4
Frame n
Table 17. Decimate-by-8, DDR = 0, P54 = 1, LMF = 4,2,2
TIME →
CHAR NUMBER
Lane 0
0
1
2
3
4
5
I0
I1
I2
I3
I4
I5
Lane 1
Lane 2
Q0
Q1
Q2
Q3
Q4
Q5
Lane 3
Frame
n
Frame
n + 1
Frame
n + 2
Table 18. Decimate-by-8, DDR = 1, P54 = 0, LMF = 3,2,8
TIME →
CHAR NUMBER
Lane 0
0
1
2
3
4
5
6
7
I0
I4
I1
I2
Q1
T
I3
Lane 1
Q0
Q4
Q2
T
Lane 2
Q3
Frame n
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Table 19. Decimate-by-8, DDR = 1, P54=1, LMF = 2,2,2
TIME →
CHAR NUMBER
Lane 0
0
1
2
3
4
5
I0
I1
I2
Lane 1
Q0
Q1
Q2
Frame
n
Frame
n + 1
Frame
n + 2
Table 20. Decimate-by-10, DDR = 0, P54 = 0, LMF = 4,2,2
TIME →
CHAR NUMBER
Lane 0
0
1
2
3
4
5
6
7
I0
I1
I2
I3
I4
I5
I6
Lane 1
I7
Lane 2
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Lane 3
Frame
n
Frame
n + 1
Frame
n + 2
Frame
n + 3
Table 21. Decimate-by-10, DDR = 1, P54 = 0, LMF = 2,2,2
TIME →
CHAR NUMBER
Lane 0
0
1
2
3
4
5
6
7
I0
I1
I2
I3
Lane 1
Q0
Q1
Q2
Q3
Frame
n
Frame
n + 1
Frame
n + 2
Frame
n+3
Table 22. Decimate-by-16, DDR = 0, P54 = 0, LMF = 3,2,8
TIME →
CHAR NUMBER
Lane 0
0
1
2
3
4
5
6
7
I0
I4
I1
I2
Q1
T
I3
Q2
T
Lane 1
Q0
Q4
Lane 2
Q3
Frame n
Table 23. Decimate-by-16, DDR = 0, P54 = 1, LMF = 2,2,2
TIME →
CHAR NUMBER
Lane 0
0
1
2
3
4
5
I0
I1
I2
Q2
Lane 1
Q0
Q1
Frame
n
Frame
n + 1
Frame
n + 2
Table 24. Decimate-by-16, DDR = 1, P54 = 0, LMF = 2,2,16
TIME →
CHAR
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
NUMBER
Lane 0
Lane 1
I0
I1
I2
T
I3
T
I4
T
Q0
T
Q1
T
Q2
T
Q3
Q4
Frame n
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Table 25. Decimate-by-16, DDR = 1, P54 = 1, LMF = 1,2,4
TIME →
CHAR NUMBER
0
1
2
3
4
5
6
7
8
9
10
11
Lane 0
I0
Q0
I1
Q1
I2
Q2
Frame n
Frame n + 1
Frame n + 2
Table 26. Decimate-by-20, DDR = 0, P54 = 0, LMF = 2,2,2
TIME →
CHAR NUMBER
Lane 0
0
1
2
3
4
5
6
7
I0
I1
I2
I3
Lane 1
Q0
Q1
Q2
Q3
Frame
n
Frame
n + 1
Frame
n + 2
Frame
n + 3
Table 27. Decimate-by-20, DDR = 1, P54 = 0, LMF = 1,2,2
TIME →
CHAR NUMBER
0
1
2
3
4
5
6
7
Lane 0
I0
Q0
I1
Q1
Frame n
Frame n + 1
Table 28. Decimate-by-32, DDR = 0, P54 = 0, LMF = 2,2,16
TIME →
CHAR
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
NUMBER
Lane 0
Lane 1
I0
I1
I2
T
I3
T
I4
T
Q0
T
Q1
Q2
T
Q3
Q4
T
Frame n
Table 29. Decimate-by-32, DDR = 0, P54 = 1, LMF = 1,2,4
TIME →
CHAR NUMBER
0
1
2
3
4
5
6
7
8
9
10
11
Lane 0
I0
Q0
I1
Q1
I2
Q2
Frame n
Frame n + 1
Frame n + 2
Table 30. Decimate-by-32, DDR = 1, P54 = 0, LMF = 1,2,32
TIME →
CHAR
NUMBE
R
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Lane 0
I0
I1
I2
I3
I4
Q0
Q1
Q2
Q3
Frame n
Q4
T
T
T
T
T
T
The formatted data is 8b10b encoded and output on the serial lanes. The 8b10b encoding provides a number of
specific benefits, including:
•
Standard encoding format. Therefore the IP is readily available in off-the-shelf FPGAs and ASIC building
blocks.
•
•
Inherent DC balance allows AC coupling of lanes with small on-chip capacitors
Inherent error checking
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7.3.7.2.8 JESD204B Synchronization Features
The JESD204B standard defines methods for synchronization and deterministic latency in a multi-converter
system. These devices are a JESD204B Subclass 1 device and conforms to the various aspects of link operation
as described in section 5.3.3 of the JESD204B standard. The specific signals used to achieve link operation are
described briefly in the following sections.
7.3.7.2.9 SYSREF
The SYSREF is a periodic signal which is sampled by the device clock, and is used to align the boundary of the
local multi-frame clock inside the data converter. SYSREF
is required to be a sub-harmonic of the LMFC internal timing. To meet this requirement, the timing of SYSREF is
dependent on the device clock frequency and the LMFC frequency as determined by the selected DDC
decimation and frames per multi-frame settings. This clock is typically in the range of 10 MHz to 300 MHz. See
the Multiple ADC Synchronization section for more details on SYSREF timing requirements.
7.3.7.2.10 SYNC~
SYNC~ is asserted by the receiver to initiate a synchronization event.
Single ended and differential SYNC~ inputs are provided. The SYNC_DIFFSEL bit (register 0x202, bit 6) is used
to select which input is used. Using the single ended SYNC~ input is recommended, as this frees the differential
SYNC~/TMST input pair for use in the Time Stamp function. To assert SYNC~, a logic low is applied. To
deassert SYNC~ a logic high is applied.
7.3.7.2.11 Time Stamp
When configured through the TIME_STAMP_EN register setting (register 0x050, bit 5), the SYNC~ differential
input (pins 22 and 23) can be used as a time-stamp input. The time-stamp feature enables the user to capture
the timing of an external trigger event relative to the sampled signal. When enabled, the LSB of the 12-bit ADC
digital output captures the trigger information. In effect, the 12-bit converter becomes an 11-bit converter and the
LSB acts as a 1-bit converter with the same latency as the 11-bit converter. The trigger must be applied to the
differential SYNC~/TMST inputs. The trigger can be asynchronous to the ADC sampling clock and is sampled at
approximately the same time as the analog input.
7.3.7.2.12 Code-Group Synchronization
Code-group synchronization is achieved using the following process:
•
•
•
•
•
The receiver issues a synchronization request through the SYNC~ input
The transmitter issues a stream of K28.5 symbols
The receiver synchronizes and waits for correct reception of at least 4 consecutive K symbols
The receiver deactivates the synchronization request
Upon detecting that the receiver has deactivated the SYNC~ pin, the transmitter continues emitting K symbols
until the next LMFC boundary (or optionally a later LMFC boundary)
•
On the first frame following the selected LMFC boundary the transmitters emit an initial lane-alignment
sequence
The initial-lane alignment sequence transmitted by the ADC device is defined in additional detail in JESD204B
section 5.3.3.5.
7.3.7.2.13 Multiple ADC Synchronization
The second function for the SYSREF input is to facilitate the precise synchronization of multiple ADCs in a
system.
One key challenge is to ensure that this synchronization works is to ensure that the SYSREF inputs are
repeatedly captured by the input CLK. Two key elements must occur for the SYSREF inputs to be captured.
First, the SYSREF input must be created so that it is synchronous to the input DEVCLK, be an integer sub-
harmonic of the multi-frame (K × t(FRAME)) and a repeatable and fixed-phase offset. When this constraint is
achieved, repeatedly capturing SYSREF is easier. To further ease this task, the SYSREF signal is routed
through a user-adjustable delay which eases the timing requirements with respect to the input DEVCLK signal.
The SYSREF delay RDEL is adjusted through bits 3 through 0 in register 0x032.
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As long as the SYSREF signal has a fixed timing relationship to DEVCLK, the internal delay can be used to
maximize the setup and hold times between the internally delayed SYSREF and the internal DEVCLK signal.
These timing relationships are listed in the Timing Requirements table. To find the proper delay setting, the
RDEL value is adjusted from minimum to maximum while applying SYSREF and monitoring the SysRefDet and
Dirty Capture detect bits. The SysRefDet bit is set whenever a rising edge of SYSREF is detected. The Dirty
Capture bit is set whenever the setup or hold time between DEVCLK and the delayed SYSREF is insufficient.
The SysRefDetClr bit is used to clear the SysRefDet bit. The Clear Dirty Capture bit is used to clear that bit.
This procedure should be followed to determine the range of delay settings where a clean SYSREF capture is
achieved. The delay value at the center of the clean capture range must be loaded as the final RDEL setting.
Table 31 lists a summary of the control bits that are used and the monitor bits that are read.
Table 31. SYSREF Capture Control and Status
BIT NAME
RDEL
REGISTER ADDRESS
REGISTER BIT
FUNCTION
Adjust relative delay between DEVCLK and SYSREF
0x032
0x031
0x031
0x030
0x030
3:0
7
SysRefDet
Detect if a SYSREF rising edge has been captured (not self clearing)
Detect if SYSREF rising edge capture failed setup/hold (not self clearing)
Clear SYSREF detection bit
Dirty Capture
SysRefDetClr
Clear Dirty Capture
6
5
4
Clear Dirty Capture detection bit
Enable SYSREF receiver. See the CLKGEN_0 descriptions in the Clock Generator Control 0 Register section
for more information.
SysRef_Rcvr_En
SysRef_Pr_En
0x030
0x030
7
6
Enable SYSREF processing. See the CLKGEN_0 descriptions in the Clock Generator Control 0 Register
section for more information.
One final aspect of multi-device synchronization relates to phase alignment of the NCO phase accumulators
when DDC modes are enabled. The NCO phase accumulators are reset during the ILA phase of link startup
which means that for multiple ADCs to have NCO phase alignment, all links must be enabled in the same LMFC
period. Enabling all links in the same LMFC period requires synchronizing the SYNC~ de-assertion across all
data receivers in the system, so that all of the SYNC~ signals are released during the same LMFC period. Using
large K values and resulting longer LMFC periods will ease this task, at the expense of potentially higher latency
in the receiving device.
7.4 Device Functional Modes
7.4.1 DDC Bypass Mode
In DDC bypass mode (decimation = 1) the raw 12 bit data from the ADC is output at the full sampling rate.
7.4.2 DDC Modes
In the DDC modes (decimation > 1) complex (I,Q) data is output at a lower sample rate as determined by the
decimation factor (4, 8, 10, 16, 20, and 32).
7.4.3 Calibration
Calibration adjusts the ADC core to optimize the following device parameters:
•
•
•
•
ADC core linearity
ADC core-to-core offset matching
ADC core-to-core full-scale range matching
ADC core 4-way interleave timing
All calibration processes occur internally. Calibration does not require any external signals to be present and
works properly as long as the device is maintained within the values listed in the Recommended Operating
Conditions table.
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Device Functional Modes (continued)
7.4.3.1 Foreground Calibration Mode
In foreground mode the calibration process interrupts normal ADC operation and no output data is available
during this time (the output code is forced to a static value). The calibration process should be repeated if the
device temperature changes by more than 20ºC to ensure rated performance is maintained. Foreground
calibration is initiated by setting the CAL_SFT bit (register 0x050, bit 3) which is self clearing. The foreground
calibration process finishes within t(CAL) number of DEVCLK cycles. The process occurs somewhat longer when
the timing calibration mode is enabled.
NOTE
Initiating a foreground calibration asynchronously resets the calibration control logic and
may glitch internal device clocks. Therefore after setting the CAL_SFT bit clearing and
then setting JESD_EN is necessary. If resetting the JESD204B link is undesirable for
system reasons, background calibration mode may be preferred.
7.4.3.2 Background Calibration Mode
In background mode an additional ADC core is powered-up for a total of 5 ADC cores. At any given time, one
core is off-line and not used for data conversion. This core is calibrated in the background and then placed on-
line simultaneous with another core going off-line for calibration. This process operates continuously without
interrupting data flow in the application and ensures that all cores are optimized in performance regardless of any
changes of temperature. The background calibration cycle rate is fixed and is not adjustable by the user.
Because of the additional circuitry active in background calibration mode, a slight degradation in performance
occurs in comparison to foreground calibration mode at a fixed temperature. As a result of this degradation, using
foreground calibration mode is recommended if the expected change in operating temperature is <30°C. Using
background calibration mode is recommended if the expected change in operating temperature is >30°C. The
exact difference in performance is dependent on the DEVCLK (sampling clock) frequency, and the analog input
signal frequency and amplitude. For this reason, device and system performance should be evaluated using both
calibration modes before finalizing the choice of calibration mode.
To enable the background calibration feature, set the CAL_BCK bit (register 0x057, bit 0) and the CAL_CONT bit
(register 0x057, bit 1). The value written to the register 0x057 to enable background calibration is therefore
0x013h. After writing this value to register 0x057, set the CAL_SFT bit in register 0x050 to perform the one-time
foreground calibration to begin the process.
NOTE
The ADC offset-adjust feature has no effect when background calibration mode is
enabled.
7.4.4 Timing Calibration Mode
The timing calibration process optimizes the matching of sample timing for the 4 internally interleaved converters.
This process minimize the presence of any timing related interleaving spurs in the captured spectrum. The timing
calibration feature is disabled by default, but using this feature is highly recommended. To enable timing
calibration, set the T_AUTO bit (register 0x066, bit 0). When this bit is set, the timing calibration performs each
time the CAL_SFT bit is set.
50
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Device Functional Modes (continued)
Table 32. Calibration Cycle Timing for Different Calibration Modes and Options
INITIAL ONE-TIME
CALIBRATION
CAL_SFT 0 → 1
BACKGROUND
CALIBRATION CYCLE(1)
(ALL CORES)
CAL_CONT, CAL_BCK
T_AUTO
LOW_SIG_EN
(tDEVCLK
)
(tDEVCLK
)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
102 E+6
64 E+6
N/A
N/A
227 E+6
N/A
189 E+6
N/A
127.5 E+6
80 E+6
816 E+6
512 E+6
816 E+6
512 E+6
283.75 E+6
236.25 E+6
(1) N/A = not applicable
7.4.5 Test-Pattern Modes
A number of device test modes are available. These modes insert known patterns of information into the device
data path for assistance with system debug, development, or characterization.
7.4.5.1 ADC Test-Pattern Mode
The 12-bit ADC core has a built-in test-pattern generator. This mode is helpful for verifying the full data link from
the ADC to the data receiver when in DDC bypass mode. When the test-pattern mode is enabled, the ADC
output data is replaced by a pattern that repeats every two frames. The data sequence is is shown in Table 33
(shown for default settings with foreground calibration mode).
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Table 33. ADC Test Pattern(1)
LANE
(CONVERTER
ID)
SAMPLE NUMBER (SID)
0
1
2
3
4
5
6
7
8
9
0
1
2
3
4
5
6
7
0x000
0x008
0x010
0x020
0x040
0x100
0x200
0x400
0xFFF
0xFF7
0xFEF
0xFDF
0xFBF
0xEFF
0xDFF
0xBFF
0x000
0x008
0x010
0x020
0x040
0x100
0x200
0x400
0xFFF
0xFF7
0xFEF
0xFDF
0xFBF
0xEFF
0xDFF
0xBFF
0x000
0x008
0x010
0x020
0x040
0x100
0x200
0x400
0xFFF
0xFF7
0xFEF
0xFDF
0xFBF
0xEFF
0xDFF
0xBFF
0x000
0x008
0x010
0x020
0x040
0x100
0x200
0x400
0xFFF
0xFF7
0xFEF
0xFDF
0xFBF
0xEFF
0xDFF
0xBFF
0x000
0x008
0x010
0x020
0x040
0x100
0x200
0x400
0xFFF
0xFF7
0xFEF
0xFDF
0xFBF
0xEFF
0xDFF
0xBFF
(1) When background-calibration mode is enabled, the pattern values are dynamic because the internal converter banks are output on
different lanes during the calibration bank-switching process. Each converter bank has dedicated pattern values as listed in Table 34.
Table 34. ADC Bank Pattern Values
BANK
LOCATION
Lane n
LOW VALUE
0x000
HIGH VALUE
0xFFF
0
Lane n+4
Lane n
0x040
0xFBF
0xFFE
0xF7F
0x004
1
2
3
4
Lane n+4
Lane n
0x080
0x008
0xFF7
Lane n+4
Lane n
0x100
0xEFF
0xFEF
0xDFF
0xFDF
0xBFF
0x010
Lane n+4
Lane n
0x200
0x020
Lane n+4
0x400
7.4.5.2 Serializer Test-Mode Details
Test modes are enabled by setting the appropriate configuration of the JESD204B_TEST setting (Register
0x202, Bits 3:0). Each test mode is described in detail in the following sections. Regardless of the test mode, the
serializer outputs are powered up based on the configuration decimation and DDR settings. The test modes
should only be enabled while the JESD204B link is disabled.
JESD204B
Transport Layer
JESD204B
Link Layer
8b10b
Encoder
JESD204B
TX
ADC
DDC
Scrambler
Active Lanes and Serial Rates
Set by D, DDR, and P54 Parameters
ADC
Test Pattern Enable
Long or Short Transport
Octet Ramp
Test Mode Enable
Repeated ILA
Modified RPAT
Test Mode Enable
PRBSn
D21.5
K28.5
Serial Outputs High/Low
Test Mode Enable
Figure 66. Test-Mode Insertion Points
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7.4.5.3 PRBS Test Modes
The PRBS test modes bypass the 8B10B encoder. These test modes produce pseudo-random bit streams that
comply with the ITU-T O.150 specification. These bit streams are used with lab test equipment that can self-
synchronize to the bit pattern and therefore the initial phase of the pattern is not defined.
The sequences are defined by a recursive equation. For example, the PRBS7 sequence is defined as shown in
Equation 9.
y[n] = y[n – 6]y[n – 7]
where
•
Bit n is the XOR of bit [n – 6] and bit [n – 7] which are previously transmitted bits
(9)
Table 35. PBRS Mode Equations
PRBS TEST MODE
PRBS7
SEQUENCE
SEQUENCE LENGTH (bits)
y[n] = y[n – 6]y[n – 7]
y[n] = y[n – 14]y[n – 15]
y[n] = y[n – 18]y[n – 23]
127
PRBS15
32767
8388607
PRBS23
The initial phase of the pattern is unique for each lane.
7.4.5.4 Ramp Test Mode
In the ramp test mode, the JESD204B link layer operates normally, but the transport layer is disabled and the
input from the formatter is ignored. After the ILA sequence, each lane transmits an identical octet stream that
increments from 0x00 to 0xFF and repeats.
7.4.5.5 Short and Long-Transport Test Mode
The short-transport test mode is available when the device is operated in DDC bypass mode (decimation = 1).
The short transport pattern has a length of one frame. Table 36 lists the formula followed by each sample of the
pattern.
Table 36. Short Transport Test Pattern Definition
BIT
11
10
9
8
7
6
5
4
3
2
1
0
~LID
LID
SID+1
LID is the lane ID (0 to 7) and SID is the sample number within the frame (0 to 4). The entire pattern has a length
of one frame and is listed in Table 37.
Table 37. Short Transport Test Pattern
LANE (CONVERTER ID)
SAMPLE NUMBER (SID)
0
1
2
3
4
0
1
2
3
4
5
6
7
0xF01
0xE11
0xD21
0xC31
0xB41
0xA51
0x961
0x871
0xF02
0xE12
0xD22
0xC32
0xB42
0xA52
0x962
0x872
0xF03
0xE13
0xD23
0xC33
0xB43
0xA53
0x963
0x873
0xF04
0xE14
0xD24
0xC34
0xB44
0xA54
0x964
0x874
0xF05
0xE15
0xD25
0xC35
0xB45
0xA55
0x965
0x875
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The long-transport test mode is available in all DDC modes (decimation > 1). Patterns are generated in
accordance with the JESD204B standard and are different for each output format.
Table 38 lists one example of the long transport test pattern:
Table 38. Long Transport Test Pattern - Decimate-by-4, DDR = 1, P54 = 1, K=10
TIME →
CHAR
NO.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
Lane 0
Lane 1
Lane 2
Lane 3
0x0003
0x0002
0x8000
0x8000
0x8000
0x8000
0x8000
0x8000
0x8000
0x8000
0x0003
0x0002
0x0004
0x0004
0x0005
0x0002
0x0004
0x8000
0x8001
0x8000
0x8000
0x8000
0x8001
0x8000
0x8000
0x8000
0x8000
0x8000
0x8000
0x8000
0x8000
0x8000
0x8000
0x8000
0x8000
0x8000
0x8000
0x8000
0x8000
0x8000
0x8000
0x0002
0x0004
0x0004
Frame
n
Frame
n + 1
Frame
n + 2
Frame
n + 3
Frame
n + 4
Frame
n + 5
Frame
n + 6
Frame
n + 7
Frame
n + 8
Frame
n + 9
Frame
n + 10
If multiple devices are all programmed to the transport layer test mode (while JESD_EN = 0), then JESD_EN is
set to 1, and then SYSREF is used to align the LMFC of the devices, the patterns will be aligned to the SYSREF
event (within the skew budget of JESD204B). For more details see JESD204B, section 5.1.6.3.
7.4.5.6 D21.5 Test Mode
In this test mode, the controller transmits a continuous stream of D21.5 characters (alternating 0s and 1s).
7.4.5.7 K28.5 Test Mode
In this test mode, the controller transmits a continuous stream of K28.5 characters.
7.4.5.8 Repeated ILA Test Mode
In this test mode, the JESD204B link layer operates normally with one exception: when the ILA sequence
completes, the sequence repeats indefinitely. Whenever the receiver issues a synchronization request, the
transmitter will initiate code group synchronization. Upon completion of code group synchronization, the
transmitter will repeatedly transmit the ILA sequence. If there is no active code group synchronization request at
the moment the transmitter enters the test mode, the transmitter will behave as if it received one.
7.4.5.9 Modified RPAT Test Mode
A 12-octet repeating pattern is defined in INCITS TR-35-2004. The purpose of this pattern is to generate white
spectral content for JESD204B compliance and jitter testing. Table 39 lists the pattern before and after 8b10b
encoding.
Table 39. Modified RPAT Pattern Values
20b OUTPUT OF 8b10b ENCODER
OCTET NUMBER
Dx.y NOTATION
8-BIT INPUT TO 8b10b ENCODER
(2 CHARACTERS)
0
1
D30.5
D23.6
D3.1
0xBE
0xD7
0x23
0x47
0x6B
0x8F
0xB3
0x14
0x5E
0xFB
0x35
0x59
0x86BA6
2
0xC6475
0xD0E8D
0xCA8B4
0x7949E
0xAA665
3
D7.2
4
D11.3
D15.4
D19.5
D20.0
D30.2
D27.7
D21.1
D25.2
5
6
7
8
9
10
11
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7.5 Programming
7.5.1 Using the Serial Interface
The serial interface is accessed using the following four pins: serial clock (SCLK), serial-data in (SDI), serial-data
out (SDO), and serial-interface chip-select (SCS). Registers access is enabled through the SCS pin.
SCS
SCLK
SDI
This signal must be asserted low to access a register through the serial interface. Setup and hold
times with respect to the SCLK must be observed.
Serial data input is accepted at the rising edge of this signal. SCLK has no minimum frequency
requirement.
Each register access requires a specific 24-bit pattern at this input. This pattern consists of a read-
and-write (R/W) bit, register address, and register value. The data is shifted in MSB first. Setup and
hold times with respect to the SCLK must be observed (see Figure 2).
SDO
The SDO signal provides the output data requested by a read command. This output is high
impedance during write bus cycles and during the read bit and register address portion of read bus
cycles.
Each register access consists of 24 bits, as shown in Figure 2. The first bit is high for a read and low for a write.
The next 15 bits are the address of the register that is to be written to. During write operations, the last 8 bits are
the data written to the addressed register. During read operations, the last 8 bits on SDI are ignored, and, during
this time, the SDO outputs the data from the addressed register. The serial protocol details are illustrated in
Figure 67.
Single Register Access
SCS
1
8
16
17
24
SCLK
SDI
Command Field
Data Field
R/W A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
Data Field
Hi Z
Hi Z
SDO
D7 D6 D5 D4 D3 D2 D1 D0
(read mode)
Figure 67. Serial Interface Protocol - Single Read / Write
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Programming (continued)
7.5.1.1 Streaming Mode
The serial interface supports streaming reads and writes. In this mode, the initial 24 bits of the transaction
specifics the access type, register address, and data value as normal. Additional clock cycles of write or read
data are immediately transferred, as long as the SCS input is maintained in the asserted (logic low) state. The
register address auto increments (default) or decrements for each subsequent 8 bit transfer of the streaming
transaction. The ADDR_ASC bit (register 000h, bits 5 and 2) controls whether the address value ascends
(increments) or descends (decrements). Streaming mode can be disabled by setting the ADDR_STATIC bit
(register 010h, bit 0). The streaming mode transaction details are shown in Figure 68.
Multiple Register Access
SCS
8
1
24 25
32
17
16
SCLK
SDI
Command Field
R/W A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
Data Field (write mode)
Data Field (write mode)
D7 D6 D5 D4 D3 D2 D1 D0
Data Field
Data Field
SDO
(read mode)
Hi Z
Hi Z
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
Figure 68. Serial Interface Protocol - Streaming Read / Write
See the Register Map section for detailed information regarding the registers.
NOTE
The serial interface must not be accessed during calibration of the ADC. Accessing the
serial interface during this time impairs the performance of the device until the device is
calibrated correctly. Writing or reading the serial registers also reduces dynamic
performance of the ADC for the duration of the register access time.
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7.6 Register Map
Several groups of registers provide control and configuration options for this device. Each following register
description also shows the power-on reset (POR) state of each control bit.
NOTE
All multi-byte registers are arranged in little-endian format (the least-significant byte is
stored at the lowest address) unless explicitly stated otherwise.
Memory Map
Address
Reset
Type
Standard SPI-3.0 (0x000 to 0x00F)
Register
0x000
0x001
0x3C
0x00
R/W
R
Configuration A Register
Configuration B Register
Device Configuration Register
Chip Type Register
RESERVED
0x002
0x00
R/W
R
0x003
0x03
0x004-0x005
0x006
Undefined
0x13
R
R
Chip Version Register
RESERVED
0x007-0x00B
0x00C-0x00D
0x00E-0x00F
Undefined
0x0451
Undefined
R
R
Vendor Identification Register
RESERVED
R
User SPI Configuration (0x010 to 0x01F)
0x010
0x00
R/W
R
User SPI Configuration Register
RESERVED
0x011-0x01F
Undefined
General Analog, Bias, Band Gap, and Track and Hold (0x020 to 0x02F)
0x020
0x021
0x9D
0x00
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
RESERVED
Power-On Reset Register
I/O Gain 0 Register
I/O Gain 1 Register
RESERVED
0x022
0x40
0x023
0x00
0x024
0x00
0x025
0x40
I/O Offset 0 Register
I/O Offset 1 Register
RESERVED
0x026
0x00
0x027
0x06
0x028
0xBA
0xD4
0xEA
Undefined
RESERVED
0x029
RESERVED
0x02A
RESERVED
0x02B-0x02F
RESERVED
Clock (0x030 to 0x03F)
Clock Generator Control 0 Register
Clock Generator Status Register
Clock Generator Control 2 Register
Analog Miscellaneous Register
Input Clamp Enable Register
RESERVED
0x030
0x031
0xC0
0x07
R/W
R
0x032
0x80
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0x033
0xC3
0x034
0x2F
0x035
0xDF
0x00
0x036
RESERVED
0x037
0x45
RESERVED
0x038-0x03F
Undefined
RESERVED
Serializer (0x040 to 0x04F)
Serializer Configuration Register
RESERVED
0x040
0x04
R/W
R
0x041-0x04F
Undefined
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Register Map (continued)
Memory Map (continued)
Address
Reset
Type
ADC Calibration (0x050 to 0x1FF)
R/W Calibration Configuration 0 Register
Register
0x050
0x051
0x06
0xF4
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
Calibration Configuration 1 Register
RESERVED
0x052
0x00
0x053
0x5C
RESERVED
0x054
0x1C
RESERVED
0x055
0x92
RESERVED
0x056
0x20
RESERVED
0x057
0x10
Calibration Background Control Register
ADC Pattern and Over-Range Enable Register
RESERVED
0x058
0x00
0x059
0x00
0x05A
0x05B
0x05C
0x05D-0x05E
0x05F
0x060
0x00
Calibration Vectors Register
Calibration Status Register
RESERVED
Undefined
0x00
R/W
R/W
R/W
R
Undefined
0x00
RESERVED
RESERVED
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
0x02
RESERVED
0x061
R
RESERVED
0x062
R
RESERVED
0x063
R
RESERVED
0x064
R
RESERVED
0x065
R
RESERVED
0x066
R/W
R/W
R
Timing Calibration Register
RESERVED
0x067
0x01
0x068
Undefined
Undefined
0x00
RESERVED
0x069
R
RESERVED
0x06A
0x06B
0x06C-0x1FF
R/W
R/W
R
RESERVED
0x20
RESERVED
Undefined
RESERVED
Digital Down Converter and JESD204B (0x200-0x27F)
0x200
0x201
0x10
0x0F
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Digital Down-Converter (DDC) Control
JESD204B Control 1
0x202
0x00
JESD204B Control 2
0x203
0x00
JESD204B Device ID (DID)
JESD204B Control 3
0x204
0x00
0x205
Undefined
0xF2
JESD204B and System Status Register
Overrange Threshold 0
0x206
0x207
0xAB
0x00
Overrange Threshold 1
0x208
Overrange Period
0x209-0x20B
0x20C
0x00
RESERVED
0x00
DDC Configuration Preset Mode
DDC Configuration Preset Select
Rational NCO Reference Divisor
0x20D
0x00
0x20E-0x20F
PRESET 0
0x210-0x213
0x214-0x215
0x0000
0xC0000000
0x0000
R/W
R/W
NCO Frequency (Preset 0)
NCO Phase (Preset 0)
58
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Register Map (continued)
Memory Map (continued)
Address
0x216
Reset
0xFF
0x00
Type
Register
R/W
R/W
DDC Delay (Preset 0)
RESERVED
0x217
PRESET 1
0x218-0x21B
0x21C-0x21D
0x21E
0xC0000000
0x0000
0xFF
R/W
R/W
R/W
R/W
NCO Frequency (Preset 1)
NCO Phase (Preset 1)
DDC Delay (Preset 1)
RESERVED
0x21F
0x00
PRESET 2
0x220-0x223
0x224-0x225
0x226
0xC0000000
0x0000
0xFF
R/W
R/W
R/W
R/W
NCO Frequency (Preset 2)
NCO Phase (Preset 2)
DDC Delay (Preset 2)
RESERVED
0x227
0x00
PRESET 3
0x228-0x22B
0x22C-0x22D
0x22E
0xC0000000
0x0000
0xFF
R/W
R/W
R/W
R/W
NCO Frequency (Preset 3)
NCO Phase (Preset 3)
DDC Delay (Preset 3)
RESERVED
0x22F
0x00
PRESET 4
0x230-0x233
0x234-0x235
0x236
0xC0000000
0x0000
0xFF
R/W
R/W
R/W
R/W
NCO Frequency (Preset 4)
NCO Phase (Preset 4)
DDC Delay (Preset 4)
RESERVED
0x237
0x00
PRESET 5
0x238-0x23B
0x23C-0x23D
0x23E
0xC0000000
0x0000
0xFF
R/W
R/W
R/W
R/W
NCO Frequency (Preset 5)
NCO Phase (Preset 5)
DDC Delay (Preset 5)
RESERVED
0x23F
0x00
PRESET 6
0x240-0x243
0x244-0x245
0x246
0xC0000000
0x0000
0xFF
R/W
R/W
R/W
R/W
NCO Frequency (Preset 6)
NCO Phase (Preset 6)
DDC Delay (Preset 6)
RESERVED
0x247
0x00
PRESET 7
0x248-0x24B
0x24C-0x24D
0x24E
0xC0000000
0x0000
0xFF
R/W
R/W
R/W
R/W
R
NCO Frequency (Preset 7)
NCO Phase (Preset 7)
DDC Delay (Preset 7)
RESERVED
0x24F-0x251
0x252-0x27F
0x00
Undefined
RESERVED
Reserved
0x0280-0x7FFF
Undefined
R
RESERVED
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7.6.1 Register Descriptions
7.6.1.1 Standard SPI-3.0 (0x000 to 0x00F)
Table 40. Standard SPI-3.0 Registers
Address
0x000
Reset
0x3C
Acronym
Register Name
Section
Go
CFGA
Configuration A Register
Configuration B Register
Device Configuration Register
Chip Type Register
RESERVED
0x001
0x00
CFGB
Go
0x002
0x00
DEVCFG
Go
0x003
0x03
CHIP_TYPE
RESERVED
CHIP_VERSION
RESERVED
VENDOR_ID
RESERVED
Go
0x004-0x005
0x006
0x0000
0x13
Go
Chip Version Register
RESERVED
Go
0x007-0x00B
0x00C-0x00D
0x00E-0x00F
Undefined
0x0451
Undefined
Vendor Identification Register
RESERVED
Go
7.6.1.1.1 Configuration A Register (address = 0x000) [reset = 0x3C]
All writes to this register must be a palindrome (for example: bits [3:0] are a mirror image of bits [7:4]). If the data
is not a palindrome, the entire write is ignored.
Figure 69. Configuration A Register (CFGA)
7
6
5
4
3
2
1
0
SWRST
R/W-0
RESERVED
R/W-0
ADDR_ASC
R/W-1
RESERVED
R/W-1
RESERVED
R/W-1
ADDR_ASC
R/W-1
RESERVED
R/W-0
SWRST
R/W-0
Table 41. CFGA Field Descriptions
Bit
Field
Type
Reset
Description
7
SWRST
R/W
0
Setting this bit causes all registers to be reset to their default
state. This bit is self-clearing.
6
5
RESERVED
ADDR_ASC
R/W
R/W
0
1
This bit is NOT reset by a soft reset (SWRST)
0 : descend – decrement address while streaming (address
wraps from 0x0000 to 0x7FFF)
1 : ascend – increment address while streaming (address wraps
from 0x7FFF to 0x0000) (default)
4
3
2
1
0
RESERVED
RESERVED
ADDR_ASC
RESERVED
SWRST
R/W
R/W
R/W
R/W
R/W
1
Always returns 1
Palindrome bits
bit 3 = bit 4, bit 2 = bit 5, bit 1 = bit 6, bit 0 = bit 7
1100
7.6.1.1.2 Configuration B Register (address = 0x001) [reset = 0x00]
Figure 70. Configuration B Register (CFGB)
7
6
5
4
3
2
1
0
RESERVED
R - 0x00h
Table 42. CFGB Field Descriptions
Bit
Field
Type
Reset
Description
7:0
RESERVED
R
0000 0000
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7.6.1.1.3 Device Configuration Register (address = 0x002) [reset = 0x00]
Figure 71. Device Configuration Register (DEVCFG)
7
6
5
4
3
2
1
0
RESERVED
R/W-000000
MODE
R/W-00
Table 43. DEVCFG Field Descriptions
Bit
7-2
1-0
Field
Type
R/W
R/W
Reset
0000 00
00
Description
RESERVED
MODE
SPI 3.0 specification has 1 as low power functional mode and 2
as low power fast resume. This chip does not support these
modes.
0: Normal Operation – full power and full performance (default)
1: Normal Operation – full power and full performance (default)
2: Power Down – Everything powered down
3: Power Down – Everything powered down
7.6.1.1.4 Chip Type Register (address = 0x003) [reset = 0x03]
Figure 72. Chip Type Register (CHIP_TYPE)
7
6
5
4
3
2
1
0
RESERVED
R-0000
CHIP_TYPE
R-0011
Table 44. CHIP_TYPE Field Descriptions
Bit
7-4
3-0
Field
Type
R
Reset
0000
0011
Description
RESERVED
CHIP_TYPE
R
Always returns 0x3, indicating that the part is a high speed ADC.
7.6.1.1.5 Chip Version Register (address = 0x006) [reset = 0x13]
Figure 73. Chip Version Register (CHIP_VERSION)
7
6
5
4
3
2
1
0
CHIP_VERSION
R-0001 0011
Table 45. CHIP_VERSION Field Descriptions
Bit
Field
CHIP_VERSION
Type
Reset
Description
7-0
R
0001 0011 Chip version, returns 0x13
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7.6.1.1.6 Vendor Identification Register (address = 0x00C to 0x00D) [reset = 0x0451]
Figure 74. Vendor Identification Register (VENDOR_ID)
15
14
13
12
11
10
9
1
8
0
VENDOR_ID
R-0x04h
7
6
5
4
3
2
VENDOR_ID
R-0x51h
Table 46. VENDOR_ID Field Descriptions
Bit
15-0
Field
VENDOR_ID
Type
Reset
Description
R
0x0451h
Always returns 0x0451 (TI Vendor ID)
7.6.1.2 User SPI Configuration (0x010 to 0x01F)
Table 47. User SPI Configuration Registers
Address
0x010
Reset
0x00
Acronym
USR0
Register Name
Section
User SPI Configuration Register
RESERVED
Go
0x011-0x01F
Undefined
RESERVED
7.6.1.2.1 User SPI Configuration Register (address = 0x010) [reset = 0x00]
Figure 75. User SPI Configuration Register (USR0)
7
6
5
4
3
2
1
0
RESERVED
R/W-0000 000
ADDR_STATIC
R/W-0
Table 48. USR0 Field Descriptions
Bit
7-1
0
Field
Type
R/W
R/W
Reset
0000 000
0
Description
RESERVED
ADDR_STATIC
0 : Use ADDR_ASC bit to define what happens to address
during streaming (default).
1 : Address stays static throughout streaming operation. Useful
for reading/writing calibration vector information at
CAL_VECTOR register.
62
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7.6.1.3 General Analog, Bias, Band Gap, and Track and Hold (0x020 to 0x02F)
Table 49. General Analog, Bias, Band Gap, and Track and Hold Registers
Address
0x020
Reset
0x9D
0x00
Acronym
Register Name
RESERVED
Section
RESERVED
POR
0x021
Power-On Reset Register
I/O Gain 0 Register
I/O Gain 1 Register
RESERVED
Go
Go
Go
0x022
0x40
IO_GAIN_0
IO_GAIN_1
RESERVED
IO_OFFSET_0
IO_OFFSET_1
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
0x023
0x00
0x024
0x00
0x025
0x40
I/O Offset 0 Register
I/O Offset 1 Register
RESERVED
Go
Go
0x026
0x00
0x027
0x06
0x028
0xBA
0xD4
0xAA
Undefined
RESERVED
0x029
RESERVED
0x02A
RESERVED
0x02B-0x02F
RESERVED
7.6.1.3.1 Power-On Reset Register (address = 0x021) [reset = 0x00]
Figure 76. Power-On Reset Register (POR)
7
6
5
4
3
2
1
0
RESERVED
R/W-0000 000
SPI_RES
R/W-0
Table 50. POR Field Descriptions
Bit
7-1
0
Field
Type
R/W
R/W
Reset
0000 000
0
Description
RESERVED
SPI_RES
Reset all digital. Emulates a power on reset (not self-clearing).
Write a 0 and then write a 1 to emulate a reset. Transition from
0—>1 initiates reset.
Default: 0
7.6.1.3.2 I/O Gain 0 Register (address = 0x022) [reset = 0x40]
Figure 77. I/O Gain 0 Register (IO_GAIN_0)
7
6
5
4
3
2
1
0
RESERVED
R/W-0
GAIN_FS[14]
R/W-1
GAIN_FS[13]
R/W-0
GAIN_FS[12]
R/W-0
GAIN_FS[11]
R/W-0
GAIN_FS[10]
R/W-0
GAIN_FS[9]
R/W-0
GAIN_FS[8]
R/W-0
Table 51. IO_GAIN_0 Field Descriptions
Bit
7
Field
RESERVED
GAIN_FS[14:8]
Type
R/W
R/W
Reset
Description
0
6-0
100 0000 MSB Bits for GAIN_FS[14:0]. (See the IO_GAIN_1 description in
General Analog, Bias, Band Gap, and Track and Hold (0x020 to
0x02F))
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7.6.1.3.3 IO_GAIN_1 Register (address = 0x023) [reset = 0x00]
Figure 78. IO_GAIN_1 Register (IO_GAIN_1)
7
6
5
4
3
2
1
0
GAIN_FS[7]
R/W-0
GAIN_FS[6]
R/W-0
GAIN_FS[5]
R/W-0
GAIN_FS[4]
R/W-0
GAIN_FS[3]
R/W-0
GAIN_FS[2]
R/W-0
GAIN_FS[1]
R/W-0
GAIN_FS[0]
R/W-0
Table 52. IO_GAIN_1 Field Descriptions
Bit
Field
GAIN_FS[7:0]
Type
Reset
Description
7-0
R/W
0000 0000 LSB bits for GAIN_FS[14:0]
GAIN_FS[14:0] Value
0x0000 500 mVp-p
0x4000 725 mVp-p (default)
0x7FFF 950 mVp-p
7.6.1.3.4 I/O Offset 0 Register (address = 0x025) [reset = 0x40]
Figure 79. I/O Offset 0 Register (IO_OFFSET_0)
7
6
5
4
3
2
1
0
RESERVED
OFFSET_FS[1 OFFSET_FS[1 OFFSET_FS[1 OFFSET_FS[1 OFFSET_FS[1 OFFSET_FS[9] OFFSET_FS[8]
4]
3]
2]
1]
0]
R/W-0
R/W-1
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
Table 53. IO_OFFSET_0 Field Descriptions
Bit
7
Field
RESERVED
OFFSET_FS[14:8]
Type
R/W
R/W
Reset
Description
0
6-0
100 0000 MSB Bits for OFFSET_FS[14:0].
The ADC offset adjust feature has no effect when Background
Calibration Mode is enabled. (See IO_OFFSET_1 description in
the General Analog, Bias, Band Gap, and Track and Hold
(0x020 to 0x02F) section).
7.6.1.3.5 I/O Offset 1 Register (address = 0x026) [reset = 0x00]
Figure 80. I/O Offset 1 Register (IO_OFFSET_1)
7
6
5
4
3
2
1
0
OFFSET_FS[7] OFFSET_FS[6] OFFSET_FS[5] OFFSET_FS[4] OFFSET_FS[3] OFFSET_FS[2] OFFSET_FS[1] OFFSET_FS[0]
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
Table 54. IO_OFFSET_1 Field Descriptions
Bit
7-0
Field
OFFSET_FS[7:0]
Type
Reset
Description
R/W
0000 0000 LSB bits for OFFSET_FS[14:0]. OFFSET_FS[14:0] adjusts the
offset of the entire ADC (all banks are impacted).
OFFSET_FS[14:0] Value
0x0000 –28-mV offset
0x4000 no offset (default)
0x7FFF 28-mV offset
The ADC offset adjust feature has no effect when Background
Calibration Mode is enabled.
64
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7.6.1.4 Clock (0x030 to 0x03F)
Table 55. Clock Registers
Address
0x030
Reset
0xC0
Acronym
Register Name
Section
CLKGEN_0
CLKGEN_1
CLKGEN_2
ANA_MISC
IN_CL_EN
RESERVED
RESERVED
RESERVED
RESERVED
Clock Generator Control 0 Register
Clock Generator Status Register
Clock Generator Control 2 Register
Analog Miscellaneous Register
Clamp Enable Register
RESERVED
Go
Go
Go
Go
Go
0x031
0x07
0x032
0x80
0x033
0xC3
0x034
0x2F
0x035
0xDF
0x00
0x036
RESERVED
0x037
0x45
RESERVED
0x038-0x03F
Undefined
RESERVED
7.6.1.4.1 Clock Generator Control 0 Register (address = 0x030) [reset = 0xC0]
Figure 81. Clock Generator Control 0 Register (CLKGEN_0)
7
6
5
4
3
2
1
0
SysRef_Rcvr_E SysRef_Pr_En
n
SysRefDetClr
Clear Dirty
Capture
RESERVED
DC_LVPECL_C DC_LVPECL_S DC_LVPECL_T
LK_en
YSREF_en
S_en
R/W-1
R/W-1
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
Table 56. CLKGEN_0 Field Descriptions
Bit
Field
Type
Reset
Description
7
SysRef_Rcvr_En
R/W
1
Default: 1
0 : SYSREF receiver is disabled.
1 : SYSREF receiver is enabled (default)
6
SysRef_Pr_En
R/W
1
To power down the SYSREF receiver, clear this bit first, then
clear SysRef_Rcvr_En. To power up the SYSREF receiver, set
SysRef_Rcvr_En first, then set this bit.
Default: 1
0 : SYSREF Processor is disabled.
1 : SYSREF Processor is enabled (default)
5
4
SysRefDetClr
R/W
R/W
0
0
Default: 0
Write a 1 and then a 0 to clear the SysRefDet status bit.
Clear Dirty Capture
Default: 0
Write a 1 and then a 0 to clear the DC status bit.
3
2
RESERVED
R/W
R/W
0
0
Default: 0
DC_LVPECL_CLK_en
Default: 0
Set this bit if DEVCLK is a DC-coupled LVPECL signal through
a 50-Ω resistor.
1
0
DC_LVPECL_SYSREF_en
DC_LVPECL_TS_en
R/W
R/W
0
0
Default: 0
Set this bit if SYSREF is a DC-coupled LVPECL signal through
a 50-Ω resistor.
Default: 0
Set this bit if TimeStamp is a DC-coupled LVPECL signal
through a 50-Ω resistor.
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7.6.1.4.2 Clock Generator Status Register (address = 0x031) [reset = 0x07]
Figure 82. Clock Generator Status Register (CLKGEN_1)
7
6
5
4
3
2
1
0
SysRefDet
R-0
Dirty Capture
R-0
RESERVED
R-00 0111
Table 57. CLKGEN_1 Field Descriptions
Bit
Field
SysRefDet
Type
Reset
Description
7
R
0
When high, indicates that a SYSREF rising edge was detected.
To clear this bit, write SysRefDetClr to 1 and then back to 0.
6
Dirty Capture
R
0
When high, indicates that a SYSREF rising edge occurred very
close to the device clock edge, and setup or hold is not ensured
(dirty capture). To clear this bit, write CDC to1 and then back to
0.
NOTE: When sweeping the timing on SYSREF, it may jump
across the clock edge without triggering this bit. The
REALIGNED status bit must be used to detect this (see the
JESD_STATUS register description in Digital Down Converter
and JESD204B (0x200-0x27F))
5-0
RESERVED
R
00 0111
Reserved register. Always returns 000111b
7.6.1.4.3 Clock Generator Control 2 Register (address = 0x032) [reset = 0x80]
Figure 83. Clock Generator Control 2 Register (CLKGEN_2)
7
6
5
4
3
2
1
0
RESERVED
R/W-1000
RDEL
R/W-0000
Table 58. CLKGEN_2 Field Descriptions
Bit
7-4
3-0
Field
Type
R/W
R/W
Reset
1000
0000
Description
RESERVED
RDEL
Default: 1000b
Adjusts the delay of the SYSREF input signal with respect to
DEVCLK.
Each step delays SYSREF by 20 ps (nominal)
Default: 0
Range: 0 to 15 decimal
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7.6.1.4.4 Analog Miscellaneous Register (address = 0x033) [reset = 0xC3]
Figure 84. Analog Miscellaneous Register (ANA_MISC)
7
6
5
4
3
2
1
0
RESERVED
R/W-1100 0
SYNC_DIFF_PD
R/W-0
RESERVED
R/W-11
Table 59. ANA_MISC Field Descriptions
Bit
Field
Type
R/W
R/W
Reset
1100 0
0
Description
7-3
2
RESERVED
SYNC_DIFF_PD
Set this bit to power down the differential SYNC~± inputs for the
JESD204B interface. The SYNC~± inputs can also serve as the
TimeStamp input receiver for the TimeStamp function.
The receiver must be powered up to support the time stamp or
differential SYNC~.
Default: 0b
1-0
RESERVED
R/W
11
Default: 11b
7.6.1.4.5 Input Clamp Enable Register (address = 0x034) [reset = 0x2F]
Figure 85. Input Clamp Enable Register (IN_CL_EN)
7
6
5
4
3
2
1
0
RESERVED
R/W-00
INPUT_CLAMP_EN
R/W-1
RESERVED
R/W-0 1111
Table 60. IN_CL_EN Field Descriptions
Bit
Field
Type
R/W
R/W
Reset
00
Description
7-6
5
RESERVED
Default: 00b
INPUT_CLAMP_EN
1
Set this bit to enable the analog input active clamping circuit.
Enabled by default.
Default: 1b
4-0
RESERVED
R/W
0 1111
Default: 01111b
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7.6.1.5 Serializer (0x040 to 0x04F)
Table 61. Serializer Registers
Address
0x040
Reset
0x04
Acronym
Register Name
Section
SER_CFG
RESERVED
Serializer Configuration Register
RESERVED
Go
0x041-0x04F
Undefined
7.6.1.5.1 Serializer Configuration Register (address = 0x040) [reset = 0x04]
Figure 86. Serializer configuration Register (SER_CFG)
7
6
5
4
3
2
1
0
RESERVED
R/W-0000
SERIALIZER PRE-EMPHASIS
R/W-0100
Table 62. SER_CFG Field Descriptions
Bit
7-4
3-0
Field
Type
R/W
R/W
Reset
0000
0100
Description
RESERVED
SERIALIZER PRE-EMPHASIS
Control bits for the pre-emphasis strength of the serializer output
driver. Pre-emphasis is required to compensate the low pass
behavior of the PCB trace.
Default: 4d
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7.6.1.6 ADC Calibration (0x050 to 0x1FF)
Table 63. ADC Calibration Registers
Address
0x050
0x051
0x052
0x053
0x054
0x055
0x056
0x057
0x058
Reset
0x06
0xF4
0x00
0x5C
0x1C
0x92
0x20
0x10
0x00
Acronym
Register Name
Section
Go
CAL_CFG0
CAL_CFG1
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
CAL_BACK
ADC_PAT_OVR_EN
Calibration Configuration 0 Register
Calibration Configuration 1 Register
RESERVED
Go
RESERVED
RESERVED
RESERVED
RESERVED
Calibration Background Control Register
Go
Go
ADC Pattern and Over-Range Enable
Register
0x059
0x05A
0x00
0x00
RESERVED
CAL_VECTOR
CAL_STAT
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
T_CAL
RESERVED
Calibration Vectors Register
Calibration Status Register
RESERVED
Go
Go
0x05B
Undefined
0x00
0x05C
0x05D-0x05E
0x05F
Undefined
0x00
RESERVED
RESERVED
0x060
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
0x02
RESERVED
0x061
RESERVED
0x062
RESERVED
0x063
RESERVED
0x064
RESERVED
0x065
RESERVED
0x066
Timing Calibration Register
RESERVED
Go
0x067
0x01
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
0x068
Undefined
Undefined
0x00
RESERVED
0x069
RESERVED
0x06A
RESERVED
0x06B
0x20
RESERVED
0x06C-0x1FF
Undefined
RESERVED
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7.6.1.6.1 Calibration Configuration 0 Register (address = 0x050) [reset = 0x06]
Figure 87. Calibration Configuration 0 Register (CAL_CFG0)
7
6
5
4
3
2
1
0
RESERVED
R/W-00
TIME_STAMP_EN CALIBRATION_READ_WRITE_EN
R/W-0 R/W-0
CAL_SFT
R/W-0
RESERVED
R/W-110
Table 64. CAL_CFG0 Field Descriptions
Bit
7-
5
Field
RESERVED
TIME_STAMP_EN
Type
R/W
R/W
Reset
00
Description
0
Enables the capture of the external time stamp signal to allow
tracking of input signal.
Default: 0
4
3
CALIBRATION_READ_WRITE_EN R/W
0
0
Enables the scan register to read or write calibration vectors at
register 0x05A.
Default: 0
CAL_SFT(1)
R/W
Software calibration bit. Set bit to initiate foreground calibration.
This bit is self-clearing.
This bit resets the calibration state machine. Most calibration
SPI registers are not synchronized to the calibration clock.
Changing them may corrupt the calibration state machine.
Always set CAL_SFT AFTER making any changes to the
calibration registers.
2-0
RESERVED
R/W
110
Default: 110
(1) IMPORTANT NOTE: Setting CAL_SFT can glitch internal state machines. The JESD_EN bit must be cleared and then set after setting
CAL_SFT.
7.6.1.6.2 Calibration Configuration 1 Register (address = 0x051) [reset = 0xF4]
Figure 88. Calibration Configuration 1 Register (CAL_CFG1)
7
6
5
4
3
2
1
0
RESERVED
R/W-1
LOW_SIG_EN
R/W-111
RESERVED
R/W-0100
Table 65. CAL_CFG1 Field Descriptions
Bit
7
Field
RESERVED
Type
R/W
R/W
Reset
1
Description
6-4
LOW_SIG_EN
111
Controls signal range optimization for calibration processes.
111: Calibration is optimized for lower amplitude input signals (<
–10dBFS).
000: Calibration is optimized for large (-1dBFS) input
signals.
Default: 111 but recommend 000 for large input signals.
3-0
RESERVED
R/W
0100
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7.6.1.6.3 Calibration Background Control Register (address = 0x057) [reset = 0x10]
Figure 89. Calibration Background Control Register (CAL_BACK)
7
6
5
4
3
2
1
0
RESERVED
R/W-0001 00
CAL_CONT
R/W-0
CAL_BCK
R/W-0
Table 66. CAL_BACK Field Descriptions
Bit
7-2
1
Field
Type
R/W
R/W
Reset
0001 00
0
Description
RESERVED
CAL_CONT
Set to 0001 00b
CAL_CONT is the only calibration register bit that can be
modified while background calibration is ongoing. This bit must
be set to 0 before modifying any of the other bits.
0 : Pause or stop background calibration sequence.
1 : Start background calibration sequence.
0
CAL_BCK
R/W
0
Background calibration mode enabled. When pausing
background calibration leave this bit set, only change
CAL_CONT to 0.
If CAL_BCK is set to 0 after background calibration has been
operation the calibration processes may stop in an incomplete
condition. Set CAL_SFT to perform a foreground calibration
7.6.1.6.4 ADC Pattern and Over-Range Enable Register (address = 0x058) [reset = 0x00]
Figure 90. ADC Pattern and Over-Range Enable Register (ADC_PAT_OVR_EN)
7
6
5
4
3
2
1
0
RESERVED
R/W-0000 0
ADC_PAT_EN
R/W-0
OR_EN
R/W-0
RESERVED
R/W-0
Table 67. ADC_PAT_OVR_EN Field Descriptions
Bit
7-3
2
Field
Type
R/W
R/W
R/W
R/W
Reset
Description
RESERVED
0000 0
Set to 00000b
ADC_PAT_EN
OR_EN
0
0
0
Enable ADC test pattern
Enable over-range output
Set to 0
1
0
RESERVED
7.6.1.6.5 Calibration Vectors Register (address = 0x05A) [reset = 0x00]
Figure 91. Calibration Vectors Register (CAL_VECTOR)
7
6
5
4
3
2
1
0
CAL_DATA
R/W-0000 0000
Table 68. CAL_VECTOR Field Descriptions
Bit
Field
Type
Reset
Description
7-0
CAL_DATA
R/W
0000 0000 Repeated reads of this register outputs all the calibration register
values for analysis if the CALIBRATION_READ_WRITE_EN bit
is set.
Repeated writes of this register inputs all the calibration register
values for configuration if the CAL_RD_EN bit is set.
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7.6.1.6.6 Calibration Status Register (address = 0x05B) [reset = undefined]
Figure 92. Calibration Status Register (CAL_STAT)
7
6
5
4
RESERVED
R-0000 10
3
2
1
CAL_CONT_OFF
R-X
0
FIRST_CAL_DONE
R-X
Table 69. CAL_STAT Field Descriptions
Bit
Field
Type
Reset
Description
7-2
RESERVED
R
0000
10XX
1
CAL_CONT_OFF
R
R
X
After clearing CAL_CONT, calibration does not stop
immediately. Use this register to confirm it has stopped before
changing calibration settings.
0: Indicates calibration is running (foreground or background)
1: Indicates that calibration is finished or stopped because
CAL_CONT = 0
0
FIRST_CAL_DONE
X
Indicates first calibration sequence has been done and ADC is
operational.
7.6.1.6.7 Timing Calibration Register (address = 0x066) [reset = 0x02]
Figure 93. Timing Calibration Register (T_CAL)
7
6
5
4
3
2
1
0
RESERVED
R/W-0000 001
T_AUTO
R/W-0
Table 70. CAL_STAT Field Descriptions
Bit
7-1
0
Field
Type
R/W
R/W
Reset
Description
RESERVED
T_AUTO
0000 001 Set to 0000001b
0
Set to enable automatic timing optimization. Timing calibration
will occur once CAL_SFT is set.
72
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7.6.1.7 Digital Down Converter and JESD204B (0x200-0x27F)
Table 71. Digital Down Converter and JESD204B Registers
Address
0x200
Reset
0x10
Acronym
Register Name
Section
Go
DDC_CTRL1
JESD_CTRL1
JESD_CTRL2
JESD_DID
Digital Down-Converter (DDC) Control
JESD204B Control 1
JESD204B Control 2
JESD204B Device ID (DID)
JESD204B Control 3
JESD204B and System Status Register
Overrange Threshold 0
Overrange Threshold 1
Overrange Period
0x201
0x0F
Go
0x202
0x00
Go
0x203
0x00
Go
0x204
0x00
JESD_CTRL3
JESD_STATUS
OVR_T0
Go
0x205
Undefined
0xF2
Go
0x206
Go
0x207
0xAB
OVR_T1
Go
0x208
0x00
OVR_N
Go
0x209-0x20B
0x20C
0x00
RESERVED
NCO_MODE
NCO_SEL
RESERVED
0x00
DDC Configuration Preset Mode
DDC Configuration Preset Select
Rational NCO Reference Divisor
NCO Frequency (Preset 0)
NCO Phase (Preset 0)
DDC Delay (Preset 0)
RESERVED
Go
Go
Go
Go
Go
Go
0x20D
0x00
0x20E-0x20F
0x210-0x213
0x214-0x215
0x216
0x0000
0xC0000000
0x0000
0xFF
NCO_RDIV
NCO_FREQ0
NCO_PHASE0
DDC_DLY0
RESERVED
NCO_FREQ1
NCO_PHASE1
DDC_DLY1
RESERVED
NCO_FREQ2
NCO_PHASE2
DDC_DLY2
RESERVED
NCO_FREQ3
NCO_PHASE3
DDC_DLY3
RESERVED
NCO_FREQ4
NCO_PHASE4
DDC_DLY4
RESERVED
NCO_FREQ5
NCO_PHASE5
DDC_DLY5
RESERVED
NCO_FREQ6
NCO_PHASE6
DDC_DLY6
RESERVED
NCO_FREQ7
NCO_PHASE7
DDC_DLY7
RESERVED
RESERVED
0x217
0x00
0x218-0x21B
0x21C-0x21D
0x21E
0xC0000000
0x0000
0xFF
NCO Frequency (Preset 1)
NCO Phase (Preset 1)
DDC Delay (Preset 1)
RESERVED
Go
Go
Go
0x21F
0x00
0x220-0x223
0x224-0x225
0x226
0xC0000000
0x0000
0xFF
NCO Frequency (Preset 2)
NCO Phase (Preset 2)
DDC Delay (Preset 2)
RESERVED
Go
Go
Go
0x227
0x00
0x228-0x22B
0x22C-0x22D
0x22E
0xC0000000
0x0000
0xFF
NCO Frequency (Preset 3)
NCO Phase (Preset 3)
DDC Delay (Preset 3)
RESERVED
Go
Go
Go
0x22F
0x00
0x230-0x233
0x234-0x235
0x236
0xC0000000
0x0000
0xFF
NCO Frequency (Preset 4)
NCO Phase (Preset 4)
DDC Delay (Preset 4)
RESERVED
Go
Go
Go
0x237
0x00
0x238-0x23B
0x23C-0x23D
0x23E
0xC0000000
0x0000
0xFF
NCO Frequency (Preset 5)
NCO Phase (Preset 5)
DDC Delay (Preset 5)
RESERVED
Go
Go
Go
0x23F
0x00
0x240-0x243
0x244-0x245
0x246
0xC0000000
0x0000
0xFF
NCO Frequency (Preset 6)
NCO Phase (Preset 6)
DDC Delay (Preset 6)
RESERVED
Go
Go
Go
0x247
0x00
0x248-0x24B
0x24C-0x24D
0x24E
0xC0000000
0x0000
0xFF
NCO Frequency (Preset 7)
NCO Phase (Preset 7)
DDC Delay (Preset 7)
RESERVED
Go
Go
Go
0x24F-0x251
0x252-0x27F
0x00
Undefined
RESERVED
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7.6.1.7.1 Digital Down-Converter (DDC) Control Register (address = 0x200) [reset = 0x10]
Figure 94. Digital Down-Converter (DDC) Control Register (DDC_CTRL1)
7
6
5
4
3
2
1
0
RESERVED
R/W-00
SFORMAT
DDC GAIN
BOOST
DMODE
R/W-0
R/W-1
R/W-0000
Table 72. DDC_CTRL1 Field Descriptions
Bit
7-6
5
Field
Type
R/W
R/W
Reset
00
Description
RESERVED
SFORMAT
0
Output sample format for bypass mode:
0 : Offset binary (default)
1 : Signed 2s complement(1)
4
DDC GAIN BOOST
DMODE(2)
R/W
R/W
1
0 : Final filter has 0-dB gain (recommended when NCO is set
near DC).
1 : Final filter has 6.02-dB gain (default)
3-0
0000
0 : Bypass mode (12-bit output, decimate-by-1, DDC off)
(default)
1 : Reserved
2 : decimate-by-4
3 : decimate-by-8
4 : decimate-by-10
5 : decimate-by-16
6 : decimate-by-20
7 : decimate-by-32
8..15 : RESERVED
(1) Decimated modes always output in signed 2s complement.
(2) The DMODE setting must only be changed when JESD_EN is 0.
7.6.1.7.2 JESD204B Control 1 Register (address = 0x201) [reset = 0x0F]
Figure 95. JESD204B Control 1 Register (JESD_CTRL1)
7
6
5
4
3
2
1
0
SCR
R/W-0
K_Minus_1
R/W-000 11
DDR
R/W-1
JESD_EN
R/W-1
Table 73. JESD_CTRL1 Field Descriptions
Bit
Field
Type
Reset
Description
7
SCR
R/W
0
0 : Scrambler disabled (default)
1 : Scrambler enabled
6-2
K_Minus_1
R/W
000 11
K is the number of frames per multiframe, and K – 1 is
programmed here.
Default: K = 4, K_Minus_1 = 3.
Depending on the decimation (D) and serial rate (DDR), there
are constraints on the legal values of K.
1
0
DDR
R/W
R/W
1
1
0 : SDR serial rate (ƒ(BIT) = ƒS)
1 : DDR serial rate (ƒ(BIT) = 2ƒS) (default)
JESD_EN(1)
0 : Block disabled
1 : Normal operation (default)
(1) Before altering any parameters in the JESD_CTRL1 register, you must set JESD_EN to 0. When JESD_EN is 0, the block is held in
reset and the serializers are powered down. The clocks are gated off to save power.
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7.6.1.7.3 JESD204B Control 2 Register (address = 0x202) [reset = 0x00]
Figure 96. JESD204B Control 2 Register (JESD_CTRL2)
7
6
5
4
3
2
1
0
P54
SYNC_DIFFSEL
R/W-0
RESERVED
R/W-00
JESD204B_TEST
R/W-0000
R/W-0
Table 74. JESD_CTRL2 Field Descriptions
Bit
Field
Type
Reset
Description
7
P54
R/W
0
0 : Disable 5/4 PLL. Serial bit rate is 1x or 2x based on DDR
parameter.
1 : Enable 5/4 PLL. Serial bit rate is 1.25x or 2.5x based on
DDR parameter.
6
SYNC_DIFFSEL
R/W
0
0 : Use SYNC_SE_N input for SYNC_N function
1 : Use SYNC_DIFF_N input for SYNC_N function
5-4
3-0
RESERVED
JESD204B_TEST(1)
R/W
R/W
00
Set to 00b
0000
See
0 : Test mode disabled. Normal operation (default)
1 : PRBS7 test mode
2 : PRBS15 test mode
3 : PRBS23 test mode
4 : Ramp test mode
5 : Short and long transport layer test mode
6 : D21.5 test mode
7 : K28.5 test mode
8 : Repeated ILA test mode
9 : Modified RPAT test mode
10: Serial outputs held low
11: Serial outputs held high
12 through 15 : RESERVED
(1) The JESD_CTRL2 register must only be changed when JESD_EN is 0.
7.6.1.7.4 JESD204B Device ID (DID) Register (address = 0x203) [reset = 0x00]
Figure 97. JESD204B Device ID (DID) Register (JESD_DID)
7
6
5
4
3
2
1
0
JESD_DID
R/W-0000 0000
Table 75. JESD_DID Field Descriptions
Bit
Field
JESD_DID(1)
Type
Reset
Description
7-0
R/W
0000 0000 Specifies the DID value that is transmitted during the second
multiframe of the JESD204B ILA.
(1) The DID setting must only be changed when JESD_EN is 0.
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7.6.1.7.5 JESD204B Control 3 Register (address = 0x204) [reset = 0x00]
Figure 98. JESD204B Control 3 Register (JESD_CTRL3)
7
6
5
4
3
2
1
0
RESERVED
R/W-0000 00
FCHAR
R/W-00
Table 76. JESD_CTRL3 Field Descriptions
Bit
7-2
1-0
Field
Type
R/W
R/W
Reset
0000 00
00
Description
RESERVED
FCHAR(1)
Specify which comma character is used to denote end-of-frame.
This character is transmitted opportunistically according to
JESD204B Section 5.3.3.4.
When using a JESD204B receiver, always use FCHAR=0.
When using a general purpose 8-b or 10-b receiver, the K28.7
character can cause issues. When K28.7 is combined with
certain data characters, a false, misaligned comma character
can result, and some receivers realign to the false comma. To
avoid this, program FCHAR to 1 or 2.
0 : Use K28.7 (default) (JESD204B compliant)
1 : Use K28.1 (not JESD204B compliant)
2 : Use K28.5 (not JESD204B compliant)
3 : Reserved
(1) The JESD_CTRL3 register must only be changed when JESD_EN is 0.
7.6.1.7.6 JESD204B and System Status Register (address = 0x205) [reset = Undefined]
See the JESD204B Synchronization Features section for more details.
Figure 99. JESD204B and System Status Register (JESD_STATUS)
7
6
5
4
3
2
1
0
RESERVED
R/W-0
LINK_UP
R/W-0
SYNC_STATUS
R/W-X
REALIGNED
R/W-X
ALIGNED
R/W-0
PLL_LOCKED
R/W-0
RESERVED
R/W-00
Table 77. JESD_STATUS Field Descriptions
Bit
7
Field
RESERVED
Type
R/W
R/W
Reset
Description
0
0
Always returns 0
6
LINK_UP
When set, indicates that the JESD204B link is in the DATA_ENC
state.
5
SYNC_STATUS
R/W
X
Returns the state of the JESD204B SYNC~ signal (SYNC_SE_N
or SYNC_DIFF_N).
0 : SYNC~ asserted
1 : SYNC~ deasserted
4
3
REALIGNED
ALIGNED
R/W
R/W
X
0
When high, indicates that the div8 clock, frame clock, or
multiframe clock phase was realigned by SYSREF.
Writing a 1 to this bit clears it.
When high, indicates that the multiframe clock phase has been
established by SYSREF. The first SYSREF event after enabling
the JESD204B encoder will set this bit.
Writing a 1 to this bit clears it.
2
PLL_LOCKED
RESERVED
R/W
R/W
0
0
When high, indicates that the PLL is locked.
Always returns 0
1-0
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7.6.1.7.7 Overrange Threshold 0 Register (address = 0x206) [reset = 0xF2]
Figure 100. Overrange Threshold 0 Register (OVR_T0)
7
6
5
4
3
2
1
0
OVR_T0
R/W-1111 0010
Table 78. OVR_T0 Field Descriptions
Bit
Field
Type
Reset
Description
7-0
OVR_T0
R/W
1111 0010 Over-range threshold 0. This parameter defines the absolute
sample level that causes control bit 0 to be set. Control bit 0 is
attached to the DDC I output samples. The detection level in
dBFS (peak) is
20log10(OVR_T0 / 256)
Default: 0xF2 = 242 → –0.5 dBFS
7.6.1.7.8 Overrange Threshold 1 Register (address = 0x207) [reset = 0xAB]
Figure 101. Overrange Threshold 1 Register (OVR_T1)
7
6
5
4
3
2
1
0
OVR_T1
R/W-1010 1011
Table 79. OVR_T1 Field Descriptions
Bit
Field
Type
Reset
Description
7-0
OVR_T1
R/W
1010 1011 Overrange threshold 1. This parameter defines the absolute
sample level that causes control bit 1 to be set. Control bit 1 is
attached to the DDC Q output samples. The detection level in
dBFS (peak) is
20log10(OVR_T1 / 256)
Default: 0xAB = 171 → –3.5 dBFS
7.6.1.7.9 Overrange Period Register (address = 0x208) [reset = 0x00]
Figure 102. Overrange Period Register (OVR_N)
7
6
5
4
3
2
1
0
RESERVED
R/W-0000 0
OVR_N
R/W-000
Table 80. OVR_N Field Descriptions
Bit
7-3
2-0
Field
Type
R/W
R/W
Reset
0000 0
000
Description
RESERVED
OVR_N(1)
This bit adjusts the monitoring period for the OVR[1:0] output
bits. The period is scaled by 2OVR_N. Incrementing this field
doubles the monitoring period.
(1) Changing the OVR_N setting while JESD_EN=1 may cause the phase of the monitoring period to change.
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7.6.1.7.10 DDC Configuration Preset Mode Register (address = 0x20C) [reset = 0x00]
Figure 103. DDC Configuration Preset Mode Register (NCO_MODE)
7
6
5
4
3
2
1
0
RESERVED
R/W-0000 000
CFG_MODE
R/W-0
Table 81. NCO_MODE Field Descriptions
Bit
7-1
0
Field
Type
R/W
R/W
Reset
0000 000
0
Description
RESERVED
CFG_MODE
The NCO frequency and phase are set by the NCO_FREQx and
NCO_PHASEx registers, where x is the configuration preset (0
through 7). The DDC delay setting is defined by the DDC_DLYx
register.
0 : Use NCO_[2:0] input pins to select the active DDC and NCO
configuration preset.
1 : Use the NCO_SEL register to select the active DDC and
NCO configuration preset.
7.6.1.7.11 DDC Configuration Preset Select Register (address = 0x20D) [reset = 0x00]
Figure 104. DDC Configuration Preset Select Register (NCO_SEL)
7
6
5
4
3
2
1
0
RESERVED
R/W-0000 0
NCO_SEL
R/W-000
Table 82. NCO_SEL Field Descriptions
Bit
7-3
2-0
Field
Type
R/W
R/W
Reset
0000 0
000
Description
RESERVED
NCO_SEL
When NCO_MODE = 1, this register is used to select the active
configuration preset.
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7.6.1.7.12 Rational NCO Reference Divisor Register (address = 0x20E to 0x20F) [reset = 0x0000]
Figure 105. Rational NCO Reference Divisor Register (NCO_RDIV)
15
14
13
12
11
10
9
8
0
NCO_RDIV
R/W-0x00h
7
6
5
4
3
2
1
NCO_RDIV
R/W-0x00h
Table 83. NCO_RDIV Field Descriptions
Bit
15-0
Field
Type
Reset
Description
NCO_RDIV
R/W
0x0000h
Sometimes the 32-bit NCO frequency word does not provide the
desired frequency step size and can only approximate the
desired frequency. This results in a frequency error. Use this
register to eliminate the frequency error. Use this equation to
compute the proper value to program:
NCO_RDIV = ƒS / ƒ(STEP) / 128
where
•
•
ƒS is the ADC sample rate
ƒ(STEP) is the desired NCO frequency step size
(10)
For example, if ƒS= 3072 MHz, and ƒ(STEP) = 10 KHz then:
NCO_RDIV = 3072 MHz / 10 KHz / 128 = 2400
Any combination of ƒS and ƒ(STEP) that results in a fractional
(11)
value for NCO_RDIV is not supported. Values of NCO_RDIV
larger than 8192 can degrade the NCO’s SFDR performance
and are not recommended. This register is used for all
configuration presets.
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7.6.1.7.13 NCO Frequency (Preset x) Register (address = see Table 71) [reset = see Table 71]
Figure 106. NCO Frequency (Preset x) Register (NCO_FREQ_x)
31
23
15
7
30
22
14
6
29
21
13
5
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
NCO_FREQ_x
R/W-0xC0h
NCO_FREQ_x
R/W-0x00h
NCO_FREQ_x
R/W-0x00h
1
0
NCO_FREQ_x
R/W-0x00h
Table 84. NCO_FREQ_x Field Descriptions
Bit
31-0
Field
NCO_FREQ_x
Type
Reset
Description
R/W
0xC00000 Changing this register after the JESD204B interface is running
00h
results in non-deterministic NCO phase. If deterministic phase is
required, the JESD204B interface must be re-initialized after
changing this register.
The NCO frequency (ƒ(NCO)) is:
ƒ(NCO) = NCO_FREQ_x × 2–32 × ƒS
where
•
•
ƒS is the sampling frequency of the ADC
NCO_FREQ_x is the integer value of this
register
(12)
(13)
This register can be interpreted as signed or unsigned.
Use this equation to determine the value to program:
NCO_FREQ_x = 232 × ƒ(NCO) / ƒS
If the equation does not result in an integer value, you must
choose an alternate frequency step (ƒ(STEP) ) and program the
NCO_RDIV register. Then use one of the following equations to
compute NCO_FREQ_x:
NCO_FREQ_x = round(232 × ƒ(NCO) / ƒS)
(14)
NCO_FREQ_x = round(225 × ƒ(NCO) / ƒ(STEP)
NCO_RDIV)
/
(15)
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7.6.1.7.14 NCO Phase (Preset x) Register (address = see Table 71) [reset = see Table 71]
Figure 107. NCO Phase (Preset) Register (NCO_PHASE_x)
15
14
13
12
11
10
9
1
8
0
NCO_PHASE_x
R/W-0x00h
7
6
5
4
3
2
NCO_PHASE_x
R/W-0x00h
Table 85. NCO_PHASE_x Field Descriptions
Bit
15-0
Field
NCO_PHASE_x
Type
Reset
Description
R/W
0x0000h
This value is MSB-justified into a 32−bit field and then added to
the phase accumulator. The phase (in radians) is
NCO_PHASE_x × 2–16 × 2π
(16)
This register can be interpreted as signed or unsigned.
7.6.1.7.15 DDC Delay (Preset x) Register (address = see Table 71) [reset = see Table 71]
Figure 108. DDC Delay (Preset) Register (DDC_DLY_x)
7
6
5
4
3
2
1
0
DDC_DLY_x
R/W-0xFFh
Table 86. DDC_DLY_x Field Descriptions
Bit
Field
DDC_DLY_x
Type
Reset
Description
7-0
R/W
0xFFh
DDC delay for configuration preset 0
This register provides fine adjustments to the DDC group delay.
The step size is one half of an ADC sample period (t(DEVCLK)
2). This is equivalent to Equation 17.
/
tO / (2 × D)
where
•
•
tO is the DDC output sample period
D is the decimation factor
(17)
The legal range for this register is 0 to 2D-1. Illegal values result
in undefined behavior.
Example: When D = 8, the legal register range is 0 to 15. The
step size is tO / 16 and the maximum delay is 15 × tO / 16.
Programming this register to 0xFF (the default value) powers
down and bypasses the fractional delay filter which reduces the
DDC latency by 34 ADC sample periods (as compared to the 0
setting).
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8 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The ADC12J1600 and ADC12J2700 devices are a wideband sampling and digital tuning device. The ADC input
captures input signals from DC to greater than 3 GHz. The DDC performs digital-down conversion and
programmable decimation filtering, and outputs complex (15 bit I and 15 bit Q) data. In DDC Bypass Mode
(Decimation = 1) the raw 12 bit ADC data is also available. The resulting output data is output on the JESD204B
data interface for capture by the downstream capture or processing device. Most frequency-domain applications
benefit from DDC capability to select the desired frequency band and provide only the necessary bandwidth of
output data, minimizing the required number of data signals. Time domain applications generally require the raw
12-bit ADC output data provided by the DDC bypass feature.
8.2 Typical Application
8.2.1 RF Sampling Receiver
An RF Sampling Receiver is used to directly sample a signal in the RF frequency range and provide the data for
the captured signal to downstream processing. The wide input bandwidth, high sampling rate, and DDC features
of the ADC12J1600 and ADC12J2700 make them ideally suited for this application.
SPI
Master
Over-Range Logic
FPGA
4.7 nF
1:2 Balun
BPF
L Lanes
ADC
Limiter
Diode
JESD204B
Receiver
Data Processing
and Storage
SYNC~
4.7 nF
SYSREF
and FPGA
CLKs
JESD204B
Clock Generator
图 109. Simplified Schematic
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Typical Application (接下页)
8.2.1.1 Design Requirements
For this design example, use the parameters listed in 表 87.
表 87. Design Parameters
DESIGN PARAMETERS
Signal center frequency
EXAMPLE VALUES
2500 MHz
100 MHz
–7 dBm
Signal bandwidth
Signal nominal amplitude
Signal maximum amplitude
6 dBm
Minimum SINAD (in bandwidth of interest)
Minimum SFDR (in bandwidth of interest)
48 dBc
60 dBc
8.2.1.2 Detailed Design Procedure
Use the following steps to design the RF receiver:
•
Use the signal-center frequency and signal bandwidth to select an appropriate sampling rate (DEVCLK
frequency) and decimate factor (x / 4 to x / 32).
•
•
•
•
Select the sampling rate so that the band of interest is completely within a Nyquist zone.
Select the sampling rate so that the band of interest is away from any harmonics or interleaving tones.
Use a frequency planning tool, such as the ADC harmonic calculator (see the 开发支持 section).
Select the decimation factor that provides the highest factor possible with an adequate alias-protected output
bandwidth to capture the frequency bandwidth of interest.
•
•
•
Select other system components to provide the needed signal frequency range and DEVCLK rate.
See Table 1 for recommended balun components.
Select bandpass filters and limiter components based on the requirement to attenuate unwanted signals
outside the band of interest (blockers) and to prevent large signals from damaging the ADC inputs. See the
Absolute Maximum Ratings table.
The LMK048xx JESD204B clocking devices can provide the DEVCLK clock and other system clocks for ƒ(DEVCLK)
< 3101 MHz.
For DEVCLK frequencies up to 4 GHz the consider using the LMX2581 and TRF3765 devices as the DEVCLK
source. Use the LMK048xx device to provide the JESD204B clocks. For additional device information, see the 相
关文档 section.
8.2.1.3 Application Curves
The following curves show an RF signal at 2497.97 MHz captured at a sample rate of 1600 MSPS. 图 110 shows
the spectrum for the full Nyquist band. 图 111 shows the spectrum for the output data in decimate-by-32 mode
with ƒ(NCO) equal to 700 MHz. 图 111 shows the ability to provide only the spectrum of interest in the decimated
output data. 图 111 also shows how proper selection of the sampling rate can ensure interleaving tones are
outside the band of interest and outside the decimated frequency range. Lastly, 图 111 shows the reduction in
the noise floor provided by the processing gain of decimation.
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0
-25
0
-20
-40
-50
-60
-75
-80
-100
-125
-100
-120
0
80 160 240 320 400 480 560 640 720 800
-25
-12.5
0
12.5
25
Frequency (MHz)
Frequency (MHz)
D095
D094
DDC Bypass Mode
ƒS = 1600 MSPS
ƒS = 1600 MSPS
FIN = 2497.97 MHz at –1 dBFS
ƒ(NCO) = 2500 MHz
FIN = 2497.97 MHz at –1 dBFS
图 110. Spectrum — DDC Bypass Mode
图 111. Spectrum — Decimate-by-32
8.2.2 Oscilloscope
The ADC12J1600 and ADC12J2700 devices are equally well-suited for high-speed time-domain applications
such as oscilloscopes. The following typical application is for a generic high-speed oscilloscope. Adjustable gain
is provided by the front-end resistor ladder and selection mux, and the gain adjustments of the LMH6518 device.
Additional gain fine-tuning can be achieved using the full-scale range adjustment features of the ADC.
MEMORY
DISPLAY
Display Interface
Memory Interface
SPI
Master
1 nF
Over-Range Logic
LMH6518
Output Amp
900 kΩ
90 kΩ
10 kΩ
Hi-Z
50-Ω Switch
8 Lanes
SYNC~
ADC
MUX
JESD204
Receiver
Data Processing /
Storage
JFET LNA
VCMO
50 Ω
SYSREF
and FPGA
CLKs
Trigger Logic
Gain Control
JESD204
Clock Generator
LMH6518
Aux Amp
+
LMH7220
DAC101C085
DAC
图 112. Simplified Schematic for an Oscilloscope
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8.2.2.1 Design Requirements
For this design example, use the parameters listed in 表 88.
表 88. Design Parameters
DESIGN PARAMETERS
Maximum sample rate
EXAMPLE VALUES
1600 MSPS
1500 MHz
Maximum input frequency
1-dB flat-frequency range
Signal maximum amplitude
Signal minimum amplitude
Maximum capture depth
0 to 1000 MHz
6 dBm
48 dBc
1 million points
8.2.2.2 Detailed Design Procedure
Use the following primary steps to design a 12-bit oscilloscope:
•
•
Select the desired sampling rate based on the maximum sampling-rate requirement.
Select the input path components (LNA, amplifier, and other components) based on the maximum input
frequency and 1-dB flat-frequency range requirements.
•
•
Set the attenuation range steps based on the required minimum and maximum values for the signal
amplitude.
Select the memory size based on the resolution of the ADC output (12 bits) and the required maximum
number of sample points.
8.2.2.3 Application Curves
The following curves show the time-domain sample data for a 150-MHz input signal at –1 dBFS, sampled at
1600 MSPS using the ADC12J1600 device. 图 113 shows the raw time-domain data. 图 114 shows the spectrum
of the captured signal which shows the additional capability of a 12-bit ADC oscilloscope to provide basic
spectrum-analysis functions with reasonable performance.
4000
3200
2400
1600
800
0
-20
-40
-60
-80
0
-100
0
8
16
24
32
40
0
80 160 240 320 400 480 560 640 720 800
Frequency (MHz)
Sample Number (n)
D097
D098
FIN = 147.97 MHz at –1 dBFS
ƒS = 1600 MSPS
FIN = 147.97 MHz at –1 dBFS
ƒS = 1600 MSPS
图 113. Raw Time-Domain Data
图 114. Captured Signal Spectrum
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8.3 Initialization Set-Up
8.3.1 JESD204B Startup Sequence
The JESD204B interface requires a specific startup and alignment sequence. The general order of that sequence
is listed in the following steps.
1. Power up or reset the ADC12J1600 and ADC12J2700 devices.
2. Program JESD_EN = 0 to shut down the link and enable configuration changes.
3. Program DECIMATE, SCRAM_EN, KM1 and DDR to the desired settings.
4. Configure the device calibration settings as desired, and initiate a calibration (set CAL_SFT = 1).
5. Program JESD_EN = 1 to enable the link.
6. Apply at least one SYSREF rising edge to establish the LMFC phase.
7. Assert SYNC~ from the data receiver to initiate link communications.
8. After the JESD204B receiver has established code group synchronization, SYNC~ is de-asserted and the ILA process begins.
9. Immediately following the end of the ILA sequence normal data output begins.
注
If deterministic latency is not required this step can be omitted.
8.4 Dos and Don'ts
8.4.1 Common Application Pitfalls
Driving the inputs (analog or digital) beyond the power supply rails. For device reliability, an input must not
go more than 150 mV below the ground pins or 150 mV above the supply pins. Exceeding these limits even on a
transient basis can cause faulty, or erratic, operation and can impair device reliability. High-speed digital circuits
exhibiting undershoot that goes more than a volt below ground is common. To control overshoot, the impedance
of high-speed lines must be controlled and these lines must be terminated in the characteristic impedance.
Care must be taken not to overdrive the inputs of the ADC12J1600 and ADC12J2700 devices. Such practice can
lead to conversion inaccuracies and even to device damage.
Incorrect analog input common-mode voltage in the DC-coupled mode. As described in the The Analog
Inputs and DC Coupled Input Usage sections, the input common-mode voltage (VCMI) must remain the specified
range as referenced to the VCMO pin, which has a variability with temperature that must also be tracked.
Distortion performance is degraded if the input common mode voltage is outside the specified VCMI range.
Using an inadequate amplifier to drive the analog input. Use care when choosing a high frequency amplifier
to drive the ADC12J1600 and ADC12J2700 devices because many high-speed amplifiers have higher distortion
than the ADC12J1600 and ADC12J2700 devices which results in overall system performance degradation.
Driving the clock input with an excessively high level signal. The ADC input clock level must not exceed the
level described in the Recommended Operating Conditions table because the input offset can change if these
levels are exceeded.
Inadequate input clock levels. As described in the Using the Serial Interface section, insufficient input clock
levels can result in poor performance. Excessive input-clock levels can result in the introduction of an input
offset.
Using a clock source with excessive jitter, using an excessively long input clock signal trace, or having
other signals coupled to the input clock signal trace. These pitfalls cause the sampling interval to vary which
causes excessive output noise and a reduction in SNR performance.
Failure to provide adequate heat removal. As described in the Thermal Management section, providing
adequate heat removal is important to ensure device reliability. Adequate heat removal is primarily provided by
properly connecting the thermal pad to the circuit board ground planes. Multiple vias should be arranged in a grid
pattern in the area of the thermal pad. These vias will connect the topside pad to the internal ground planes and
to a copper pour area on the opposite side of the printed circuit board.
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9 Power Supply Recommendations
Data-converter-based systems draw sufficient transient current to corrupt their own power supplies if not
adequately bypassed. A 10-µF capacitor must be placed within one inch (2.5 cm) of the device power pins for
each supply voltage. A 0.1-µF capacitor must be placed as close as possible to each supply pin, preferably
within 0.5 cm. Leadless chip capacitors are preferred due to their low-lead inductance.
As is the case with all high-speed converters, the ADC12J1600 and ADC12J2700 devices must be assumed to
have little power-supply noise-rejection. Any power supply used for digital circuitry in a system where a large
amount of digital power is consumed must not be used to supply power to the ADC12J1600 and ADC12J2700
devices. If not a dedicated supply, the ADC supplies must be the same supply used for other analog circuitry.
9.1 Supply Voltage
The ADC12J1600 and ADC12J2700 devices are specified to operate with nominal supply voltages of 1.9 V
(VA19) and 1.2 V (VA12, VD12). For detailed information regarding the operating voltage minimums and
maximums see the Recommended Operating Conditions table.
During power-up the voltage on all 1.9-V supplies must always be equal to or greater than the voltage on the 1.2-
V supplies. Similarly, during power-down, the voltage on the 1.2-V supplies must always be lower than or equal
to that of the 1.9-V supplies. In general, supplying all 1.9-V buses from a single regulator, and all 1.2-V buses
from a single regulator is the easiest method to ensure that the 1.9-V supplies are greater than the 1.2-V
supplies. If the 1.2-V buses are generated from separate regulators, they must rise and fall together (within 200
mV).
The voltage on a pin, including a transient basis, must not have a voltage that is in excess of the supply voltage
or below ground by more than 150 mV. A pin voltage that is higher than the supply or that is below ground can
be a problem during startup and shutdown of power. Ensure that the supplies to circuits driving any of the input
pins, analog or digital, do not rise faster than the voltage at the ADC12J1600 and ADC12J2700 power pins.
The values in the Absolute Maximum Ratings table must be strictly observed including during power up and
power down. A power supply that produces a voltage spike at power turnon, turnoff, or both can destroy the
ADC12J1600 and ADC12J2700 devices. Many linear regulators produce output spiking at power on unless there
is a minimum load provided. Active devices draw very little current until the supply voltages reach a few hundred
millivolts. The result can be a turn-on spike that destroys the ADC12J1600 and ADC12J2700 devices, unless a
minimum load is provided for the supply. A 100-Ω resistor at the regulator output provides a minimum output
current during power up to ensure that no turn-on spiking occurs. Whether a linear or switching regulator is used,
TI recommends using a soft-start circuit to prevent overshoot of the supply.
10 Layout
10.1 Layout Guidelines
Proper grounding and proper routing of all signals is essential to ensure accurate conversion. Each ground layer
should be a single unified ground plane, rather than splitting the ground planes into analog and digital areas.
Because digital switching transients are composed largely of high frequency components, the skin effect dictates
that the total ground-plane copper weight has little effect upon the logic-generated noise. Total surface area is
more important than the total ground-plane volume. Coupling between the typically-noisy digital circuitry and the
sensitive analog circuitry can lead to poor performance that can be impossible to isolate and remedy. The
solution is to keep the analog circuitry well separated from the digital circuitry.
High-power digital components must not be located on or near any linear component or power-supply trace or
plane that services analog or mixed-signal components because the resulting common return current path could
cause fluctuation in the analog input ground return of the ADC which causes excessive noise in the conversion
result.
In general, assume that analog and digital lines must cross each other at 90° to avoid digital noise into the
analog path. In high frequency systems, however, avoid crossing analog and digital lines altogether. The input
clock lines must be isolated from all other lines, both analog and digital. The generally-accepted 90° crossing
must be avoided because even a same amount of coupling causes problems at high frequencies. Best
performance at high frequencies is obtained with a straight signal path.
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Layout Guidelines (接下页)
Coupling onto or between the clock and input signal paths must be avoided using any isolation techniques
available including distance isolation, orientation planning to prevent field coupling of components like inductors
and transformers, and providing well coupled reference planes. Via stitching around the clock signal path and the
input analog signal path provides a quiet ground reference for the critical signal paths and reduces noise
coupling onto these paths. Sensitive signal traces must not cross other signal traces or power routing on
adjacent PCB layers, rather a ground plane must separate the traces. If necessary, the traces should cross at
90° angles to minimize crosstalk.
Isolation of the analog input is important because of the low-level drive required of the ADC12J1600 and
ADC12J2700 devices. Quality analog input signal and clock signal path layout is required for full dynamic
performance. Symmetry of the differential signal paths and discrete components in the path is mandatory and
symmetrical shunt-oriented components should have a common grounding via. The high frequency requirements
of the input and clock signal paths necessitate using differential routing with controlled impedances and
minimizing signal path stubs (including vias) when possible.
Layout of the high-speed serial-data lines is of particular importance. These traces must be routed as tightly
coupled 100-Ω differential pairs, with minimal vias. When vias must be used, care must be taken to implement
control-impedance vias (that is, 50-Ω) with adjacent ground vias for image current control.
10.2 Layout Example
The following examples show layout-example plots (top and bottom layers only). 图 117 shows a typical stackup
for a 10 layer board.
Single ended VIN
path via balun
selected if capacitors
installed here.
Large bulk
decoupling
capacitor near
device.
Power supply decoupling capacitors
very close to power pins.
Balun transformer for SE to
differential conversion.
RBIAS+
RBIASœ
VCMO
VA19
1
2
51 DS6+/NCO_1
50 DS6œ/NCO_1
49 VD12
3
4
48 DS5+/NCO_0
47 DS5œ/NCO_0
46 VD12
VNEG
VA12
5
Straight analog input path with
minimal adjacent circuitry.
Power supply
decoupling
6
VA19
7
45 DS4+
capacitors near
VIN and DEVCLK
are located on
opposite side of
board to minimize
noise coupling.
VIN+
8
44 DS4œ
VINœ
9
43 VD12
VA19
10
11
12
13
14
15
16
17
42 DS3+
VA12
41 DS3œ
VNEG
VA19
40 VD12
39 DS2+
VA12
38 DS2œ
DEVCLK+
DEVCLKœ
VA12
37 VD12
36 DS1+
35 DS1œ
AC coupling capacitors on serial
output pairs.
DEVCLK path B
selected if capacitors
installed here.
Straight DEVCLK path with
minimal adjacent circuitry.
GND reference vias near where high
speed signals transition to inner layer.
图 115. ADC12J1600 and ADC12J2700 Layout Example 1 — Top Side
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Layout Example (接下页)
Additional decoupling capacitors near
device.
RBIAS resistor
near to RBIAS+
and RBIAS- pins.
RBIAS+
RBIASœ
VCMO
VA19
1
2
51 DS6+/NCO_1
50 DS6œ/NCO_1
49 VD12
3
4
48 DS5+/NCO_0
47 DS5œ/NCO_0
46 VD12
VNEG
VA12
5
6
Decoupling
capacitors power
pins near VIN and
DEVCLK on this
side of board.
VA19
7
45 DS4+
Optional differential VIN path
selected if capacitors or
resistors installed here.
VIN+
8
44 DS4œ
VINœ
9
43 VD12
VA19
10
11
12
13
14
15
16
17
42 DS3+
VA12
41 DS3œ
VNEG
VA19
40 VD12
39 DS2+
VA12
38 DS2œ
DEVCLK+
DEVCLKœ
VA12
37 VD12
36 DS1+
35 DS1œ
DEVCLK path A
selected if capacitors
installed here.
Larger bulk
decoupling
capacitors on this
side of board, near
device.
图 116. ADC12J1600 and ADC12J2700 Layout Example 2 — Bottom Side
L1 œ SIG
L2 œ GND
L3 œ SIG
L4 œ GND
L5 œ PWR
0.0040''
0.0067''
0.0060''
0.0041''
0.0060''
0.0578''
L6 œ SIG
L7 œ GND
L8 œ SIG
0.0067''
0.0040''
0.0073''
0.0040''
L9 œ GND
L10 œ SIG
1/2 oz. Copper on L1, L3, L6, L8, L10
1 oz. Copper on L2, L4, L5, L7, L9
100 Differential Signaling on SIG Layers
Low loss dielectric adjacent very high speed trace layers
Finished thickness 0.0620" including plating and solder mask
图 117. ADC12J1600 and ADC12J2700 Typical Stackup — 10 Layer Board
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10.3 Thermal Management
The ADC12J1600 and ADC12J2700 devices are capable of impressive speeds and performance at low power
levels for speed. However, the power consumption is still high enough to require attention to thermal
management. The VQFN package has a primary-heat transfer path through the center pad on the bottom of the
package. The thermal resistance of this path is provided as RθJCbot
.
For reliability reasons, the die temperature must be kept to a maximum of 135°C which is the ambient
temperature (TA) plus the ADC power consumption multiplied by the net junction-to-ambient thermal resistance
(RθJA). Maintaining this temperature is not a problem if the ambient temperature is kept to a maximum of 85°C as
specified in the Recommended Operating Conditions table and the center ground pad on the bottom of the
package is thermally connected to a large-enough copper area of the PC board.
The package of the ADC12J1600 and ADC12J2700 devices have a center pad that provides the primary heat-
removal path as well as excellent electrical grounding to the PCB. Recommended land pattern and solder paste
examples are provided in the 机械、封装和可订购信息 section. The center-pad vias shown must be connected to
internal ground planes to remove the maximum amount of heat from the package, as well as to ensure best
product parametric performance.
If needed to further reduce junction temperature, TI recommends to build a simple heat sink into the PCB which
occurs by including a copper area of about 1 to 2 cm2 on the opposite side of the PCB. This copper area can be
plated or solder-coated to prevent corrosion, but should not have a conformal coating which would provide
thermal insulation. Thermal vias will be used to connect these top and bottom copper areas and internal ground
planes. These thermal vias act as heat pipes to carry the thermal energy from the device side of the board to the
opposite side of the board where the heat can be more effectively dissipated.
11 器件和文档支持
11.1 器件支持
11.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
11.1.2 开发支持
如需 ADC 谐波计算器，请访问 http://www.ti.com/tool/adc-harmonic-calc。
11.1.3 器件命名规则
孔径（采样）延迟 是在时钟输入的采样边沿测得的延迟量，经过此段延迟后将在器件内部对输入引脚的信号进行
采样。
孔径抖动 (t(AJ))是采样与采样之间的孔径延迟变化。孔径抖动以输入噪声的形式出现。
时钟占空比 是时钟波形为逻辑高电平的时间与一个时钟周期总时长的比率。
全功率带宽 (FPBW)是一个频率测量值，在此频率下，重构的输出基频会降至满量程输入的低频值以下 3dB。
交错毛刺
是 ADC 多组交叉架构中的非理想条件产生的频域 (FFT) 效应。
各组间的偏移误差在 ƒS/4 和 ƒS/2 时会产生固定毛刺。增益和时序误差在 ƒS / 4 ± FIN 以及 ƒS / 2 ±
FIN 时会产生输入信号相关毛刺。
互调失真 (IMD)是由于两个正弦频率同时被施加到 ADC 输入上所产生的额外频谱分量。IMD 定义为二阶和三阶互
调产品功率与某原始频率下的功率之比。IMD 通常以 dBFS 为单位。
最低有效位 (LSB)是所有位中具有最小值或最低权重的位。此值根据公式 18 进行计算。
VFS(dif) / 2n
其中
•
VFS(dif) 为 VI 的差分满量程幅值，如 FSR 输入所设（引脚 14）
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器件支持 (接下页)
•
n 为 ADC 分辨率（以位为单位），ADC12J1600 和 ADC12J2700 器件对应的 n = 12
(18)
电流模式逻辑 (CML) 差分输出电压 (VOD)是正负输出电压间差值的绝对值。所有输出均相对于接地端测量。
VD+
VD-
VOD
VD+
VOS
VD-
GND
VOD = | VD+ - VD- |
图 118. CML 输出信号电平
CML 输出偏移电压 (VO(ofs))是 D+ 和 D– 引脚间输出电压的平均值。公式 19 为 VOS 示例。
[(VD+) + ( VD–)] / 2
(19)
最高有效位 (MSB)是具有最大值或最高权重的位。MSB 的值为满量程的一半。
超量程恢复时间 是转换器差分输入电压从 ±1.2V 变为 0V 后恢复并以额定精度进行转换所需的时间。
其它毛刺
是所有高次谐波（四次及以上）、交错毛刺和所有其它固定毛刺或输入相关毛刺的总和。
数据延迟（延迟） 是开始转换到串行器输出相关数据期间的输入时钟周期数。
无杂散动态范围 (SFDR)是输出端输入信号与杂散信号峰值的均方根 (RMS) 值间的差值（以 dB 为单位），其中杂
散信号是出现在输出频谱但未出现在输入频谱的所有信号，直流信号除外。
总谐波失真 (THD)是输出端前九个谐波总值与输出端基频值之比的 RMS 值（以 dB 为单位）。总谐波失真 (THD)
根据公式 20 计算。
2
2
f10
A
+ . . . + A
f2
THD = 20 x log
2
A
f1
其中
•
•
A(f1) 是基频（输出）的 RMS 功率
A(f2) 到 A(f10) 是输出频谱中前九个谐波频率的 RMS 功率
(20)
二次谐波失真 (2nd Harm)是输出端检测到的输入频率 RMS 功率与输出端二次谐波功率之间的差值（以 dB 为单
位）。
三次谐波失真 (3rd Harm)是输出端检测到的输入频率 RMS 功率与输出端三次谐波功率之间的差值（以 dB 为单
位）。
误字率
是出错率，定义为单位时间内可能出错的字数除以该时间内检查的字数。误字率 10–18 指大约每四年
会有一个转换出现统计误差。
11.2 文档支持
11.2.1 相关文档
请参阅如下相关文档：
•
•
•
•
LMH3401 7GHz 超宽带固定增益全差分放大器，SBOS695
LMK0482x 具有双环 PLL 的超低噪声 JESD204B 兼容时钟抖动消除器，SNAS605
LMX2581 具有集成压控振荡器 (VCO) 的宽带频率合成器，SNAS601
TRF3765 具有集成 VCO 的整数 N/分数 N 锁相环 (PLL)，SLWS230
11.3 相关链接
以下是为加速设计活动所提供的信息直接链接。范围包括技术信息、社区资源、设计信息，并且可在做出决定后快
速访问样片或购买链接。
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相关链接 (接下页)
部件
产品文件夹
请单击此处
请单击此处
样片与购买
请单击此处
请单击此处
技术文档
请单击此处
请单击此处
工具与软件
请单击此处
请单击此处
支持与社区
请单击此处
请单击此处
ADC12J1600
ADC12J2700
11.4 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
11.5 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.6 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
11.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。这些数据如有变更，恕不另行通知
和修订此文档。如欲获取此数据表的浏览器版本，请参阅左侧的导航。
92
版权 © 2014–2017, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
ADC12J1600NKE
ADC12J1600NKER
ADC12J1600NKET
ADC12J2700NKE
ADC12J2700NKER
ADC12J2700NKET
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
NKE
NKE
NKE
NKE
NKE
NKE
68
68
68
68
68
68
168
RoHS & Green
SN
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
ADC12J1600
2000 RoHS & Green
SN
SN
SN
SN
SN
ADC12J1600
ADC12J1600
ADC12J2700
ADC12J2700
ADC12J2700
250
168
RoHS & Green
RoHS & Green
2000 RoHS & Green
250 RoHS & Green
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
ADC12J1600NKER
ADC12J1600NKET
ADC12J2700NKER
ADC12J2700NKET
VQFN
VQFN
VQFN
VQFN
NKE
NKE
NKE
NKE
68
68
68
68
2000
250
330.0
178.0
330.0
178.0
24.4
24.4
24.4
24.4
10.3
10.3
10.3
10.3
10.3
10.3
10.3
10.3
1.1
1.1
1.1
1.1
16.0
16.0
16.0
16.0
24.0
24.0
24.0
24.0
Q1
Q1
Q1
Q1
2000
250
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
ADC12J1600NKER
ADC12J1600NKET
ADC12J2700NKER
ADC12J2700NKET
VQFN
VQFN
VQFN
VQFN
NKE
NKE
NKE
NKE
68
68
68
68
2000
250
367.0
213.0
367.0
213.0
367.0
191.0
367.0
191.0
45.0
55.0
45.0
55.0
2000
250
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TRAY
L - Outer tray length without tabs
KO -
Outer
tray
height
W -
Outer
tray
width
Text
P1 - Tray unit pocket pitch
CW - Measurement for tray edge (Y direction) to corner pocket center
CL - Measurement for tray edge (X direction) to corner pocket center
Chamfer on Tray corner indicates Pin 1 orientation of packed units.
*All dimensions are nominal
Device
Package Package Pins SPQ Unit array
Max
matrix temperature
(°C)
L (mm)
W
K0
P1
CL
CW
Name
Type
(mm) (µm) (mm) (mm) (mm)
ADC12J1600NKE
ADC12J2700NKE
NKE
NKE
VQFNP
VQFNP
68
68
168
168
8 X 21
8 X 21
150
150
322.6 135.9 7620 14.65
322.6 135.9 7620 14.65
11
11
11.95
11.95
Pack Materials-Page 3
PACKAGE OUTLINE
NKE0068A
VQFN - 0.9 mm max height
SCALE 1.700
PLASTIC QUAD FLATPACK - NO LEAD
10.1
9.9
A
B
PIN 1 ID
10.1
9.9
0.9 MAX
C
SEATING PLANE
0.1 C
0.05
0.00
(0.2)
7.7 0.1
4X (45 X0.42)
18
34
17
35
SYMM
4X
8
1
51
0.3
68X
64X 0.5
0.2
52
68
0.1
C A
C
B
0.7
0.5
SYMM
PIN 1 ID
(OPTIONAL)
68X
0.05
4214820/A 12/2014
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
NKE0068A
VQFN - 0.9 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
7.7)
SYMM
(1.19) TYP
52
68X (0.8)
68X (0.25)
68
1
51
(1.19)
TYP
64X (0.5)
SYMM
(9.6)
(
0.2) TYP
VIA
17
35
34
18
(9.6)
LAND PATTERN EXAMPLE
SCALE:8X
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214820/A 12/2014
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
www.ti.com
EXAMPLE STENCIL DESIGN
NKE0068A
VQFN - 0.9 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(9.6)
(1.19) TYP
68X (0.8)
68X (0.25)
36X
68
52
(
0.99)
1
51
(1.19)
TYP
64X (0.5)
SYMM
(9.6)
METAL
TYP
35
17
18
34
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
60% PRINTED SOLDER COVERAGE BY AREA
SCALE:8X
4214820/A 12/2014
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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