ADC12L080CIVY/NOPB [TI]

12 位、80MSPS、450MHz 输入带宽模数转换器 (ADC) | NEY | 32 | -40 to 85;


型号：	ADC12L080CIVY/NOPB
厂家：	TEXAS INSTRUMENTS
描述：	12 位、80MSPS、450MHz 输入带宽模数转换器 (ADC) \| NEY \| 32 \| -40 to 85 转换器模数转换器
文件：	总33页 (文件大小：1184K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ADC12L080

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SNAS200B –OCTOBER 2004–REVISED MARCH 2013

ADC12L080 12-Bit, 80 MSPS, 450 MHz Bandwidth A/D Converter with Internal Reference

Check for Samples: ADC12L080

FEATURES

DESCRIPTION

The ADC12L080 is a monolithic CMOS analog-to-

digital converter capable of converting analog input

signals into 12-bit digital words at 80 Megasamples

•

Single Supply Operation

Low Power Consumption

Power Down Mode

•

per second (MSPS). This converter uses

Internal or External Reference

differential, pipeline architecture with digital error

correction and an on-chip sample-and-hold circuit to

minimize die size and power consumption while

providing excellent dynamic performance. The

ADC12L080 can be operated with either the internal

or an external reference. Operating on a single 3.3V

power supply, this device consumes just 425 mW at

80 MSPS, including the reference current. The Power

Down feature reduces power consumption to just 50

mW.

Selectable Offset Binary or 2's Complement

Data Format

•

Pin-Compatible with ADC12010, ADC12020,

ADC12040, ADC12L063, ADC12L066

APPLICATIONS

•

Ultrasound and Imaging

Instrumentation

Cellular Base Stations/Communication

Receivers

The differential inputs provide a full scale input swing

equal to ±V_REF. The buffered, high impedance, single-

ended external reference input is converted on-chip

to a differential reference for use by the processing

circuitry. Output data format may be selected as

either offset binary or two's complement.

•

Sonar/Radar

xDSL

Wireless Local Loops

Data Acquisition Systems

DSP Front Ends

This device is available in the 32-lead LQFP package

and operates over the industrial temperature range of

−40°C to +85°C.

KEY SPECIFICATIONS

•

Full Power Bandwidth: 450 MHz

DNL: ±0.4 LSB (typ)

SNR (f_IN= 10 MHz): 66 dB (typ)

SFDR (f_IN= 10 MHz): 80 dB (typ)

Power Consumption, 80 MHz

–

Operating: 425 mW (typ)

Power Down: 50 mW (typ)

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

ADC12L080

SNAS200B –OCTOBER 2004–REVISED MARCH 2013

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Connection Diagram

Figure 1. 32-Lead LQFP Package

See Package Number NEY0032A

Block Diagram

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Pin Descriptions and Equivalent Circuits

Pin No.

ANALOG I/O

Symbol

Equivalent Circuit

Description

V_IN

Differential analog signal Input pins. With a 1.0V reference voltage

the full-scale differential input signal level is 2.0 V_P-Pwith each input

pin centered on a common mode voltage, V_CM. The V_IN- pin may be

connected to V_CMfor single-ended operation, but a differential input

signal is required for best performance.

−

V_IN

Reference input. This pin should be connected to V_Ato use the

internal 1.0V reference. If it is desired to use an external reference

voltage, this pin should be bypassed to AGND with a 0.1 µF low ESL

capacitor. Specified operation is with a V_REFof 1.0V, but the device

will function well with a V_REFrange indicated in the Electrical Tables.

V_REF

V_RP

V_RM

These pins are high impedance reference bypass pins only. Connect

a 0.1 µF capacitor from each of these pins to AGND. Connect a 1.0

µF capacitor from V_RPto V_RN. DO NOT LOAD these pins.

V_RN

DIGITAL I/O

Digital clock input. The range of frequencies for this input is 10 MHz

to 80 MHz with guaranteed performance at 80 MHz. The input is

sampled on the rising edge of this input.

CLK

Output format selection. When this pin is LOW, the output format is

offset binary. When this pin is HIGH the output format is two's

complement. This pin may be changed asynchronously, but such a

change will result in errors for one or two conversions.

PD is the Power Down input pin. When high, this input puts the

converter into the power down mode. When this pin is low, the

converter is in the active mode.

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Pin Descriptions and Equivalent Circuits (continued)

Pin No.

Symbol

Equivalent Circuit

Description

14–19,

22–27

Digital data output pins that make up the 12-bit conversion results.

D0 is the LSB, while D11 is the MSB of the output word.

D0–D11

ANALOG POWER

Positive analog supply pins. These pins should be connected to a

quiet +3.3V source and bypassed to AGND with 0.1 µF low ESL

capacitors located within 1 cm of these power pins, and with a 10 µF

capacitor.

5, 6, 29

V_A

4, 7, 28

AGND

The ground return for the analog supply.

DIGITAL POWER

Positive digital supply pin. This pin should be connected to the same

quiet +3.3V source as is V_Aand bypassed to DGND with a 0.1 µF

monolithic capacitor in parallel with a 10 µF capacitor, both located

within 1 cm of the power pin.

V_D

9, 12

DGND

The ground return for the digital supply.

Positive digital supply pin for the ADC12L080's output drivers. This

pin should be connected to a voltage source in the range indicated in

the Operating Ratings table and be bypassed to DR GND with a 0.1

µF capacitor. If the supply for this pin is different from the supply

used for V_Aand V_D, it should also be bypassed with a 10 µF

capacitor. The voltage at this pin should never exceed the voltage on

V_Dby more than 300 mV. All bypass capacitors should be located

within 1 cm of the supply pin.

V_DR

The ground return for the digital supply for the ADC12L080's output

drivers. This pin should be connected to the system digital ground,

but not be connected in close proximity to the ADC12L080's DGND

or AGND pins. See LAYOUT AND GROUNDING for more details.

DR GND

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

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Absolute Maximum Ratings^(1)(2)(3)

V_A, V_D, V_DR

4.2V

≤ 100 mV

|V_A–V_D|

V_DR–V_D

≤ 300 mV

Voltage on Any Pin

−0.3V to V_Aor (V_D+ 0.3V)

±25 mA

Input Current at Any Pin⁽⁴⁾

Package Input Current⁽⁴⁾

Package Dissipation at T_A= 25°C

ESD Susceptibility

±50 mA

See⁽⁵⁾

Human Body Model⁽⁶⁾

Machine Model⁽⁶⁾

2500V

250V

Soldering Temperature, Infrared, 10 sec.⁽⁷⁾

Storage Temperature

235°C

−65°C to +150°C

(1) All voltages are measured with respect to GND = AGND = DGND = 0V, unless otherwise specified.

(2) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for

which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see

the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics

may degrade when the device is not operated under the listed test conditions.

(3) If Military/Aerospace specified devices are required, please contact the TI Sales Office/ Distributors for availability and specifications.

(4) When the input voltage at any pin exceeds the power supplies (that is, V_IN< AGND, or V_IN> V_A, V_Dor V_DR), the current at that pin

should be limited to 25 mA. The 50 mA maximum package input current rating limits the number of pins that can safely exceed the

power supplies with an input current of 25 mA to two.

(5) The absolute maximum junction temperature (T_Jmax) for this device is 150°C. The maximum allowable power dissipation is dictated by

T_Jmax, the junction-to-ambient thermal resistance (θ_JA), and the ambient temperature, (T_A), and can be calculated using the formula

P_DMAX = (T_Jmax - T_A)/θ_JA. The values for maximum power dissipation will be reached only when the device is operated in a severe

fault condition (e.g. when input or output pins are driven beyond the power supply voltages, or the power supply polarity is reversed).

Obviously, such conditions should always be avoided.

(6) Human body model is 100 pF capacitor discharged through a 1.5 kΩ resistor. Machine model is 220 pF discharged through 0Ω.

(7) The 235°C reflow temperature refers to infrared reflow. For Vapor Phase Reflow (VPR), the following Conditions apply: Maintain the

temperature at the top of the package body above 183°C for a minimum 60 seconds. The temperature measured on the package body

must not exceed 220°C. Only one excursion above 183°C is allowed per reflow cycle.

Operating Ratings⁽¹⁾⁽²⁾

Operating Temperature

Supply Voltage (V_A, V_D)

Output Driver Supply (V_DR

V_REF

−40°C ≤ T_A≤ +85°C

+3.0V to +3.60V

+2.4V to V_D

)

0.8V to 1.5V

CLK, PD, OF

−0.05V to V_D+ 0.05V

−0V to (V_A− 0.5V)

0.5V to (V_A-1.5V)

V_INInput

V_CM

|AGND–DGND|

(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for

which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see

the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics

may degrade when the device is not operated under the listed test conditions.

(2) All voltages are measured with respect to GND = AGND = DGND = 0V, unless otherwise specified.

Package Thermal Resistances

Package

θ_J-A

32-Lead LQFP

79°C / W

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Converter Electrical Characteristics

Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, V_A= V_D= +3.3V, V_DR

+2.5V, PD = 0V, V_REF= +1.0V external, V_CM= 1.65V, R_S< 100Ω, f_CLK= 80 MHz, t_r= t_f= 2 ns, f_IN= 70 MHz, C_L= 15 pF/pin.

Boldface limits apply for T_J= T_MINto T_MAX: all other limits T_J= 25°C^(1)(2)(3)(4)

Units

(Limits)

Symbol

Parameter

Conditions

Typical⁽⁴⁾Limits⁽⁴⁾

STATIC CONVERTER CHARACTERISTICS

Resolution with No Missing Codes

Bits

4.0

LSB (max)

LSB (min)

LSB (max)

LSB (min)

INL

Integral Non Linearity

Best Fit Method

±1.2

-3.3

1.5

DNL

Differential Non Linearity

No missing codes

±0.4

-1.0

+5.7

-2

%FS (max)

%FS (min)

Positive Error

Negative Error

−0.15

Gain Error

-3.7

%FS (max)

%FS (min)

+0.4

Offset Error (V_IN+ = V_IN−)

+1.7

-0.6

+0.2

%FS (max)

Under Range Output Code

Over Range Output Code

4095

REFERENCE AND ANALOG INPUT CHARACTERISTICS

0.5

2.0

V (min)

V (max)

V_CM

Common Mode Input Voltage

1.65

(CLK LOW)

(CLK HIGH)

V_INInput Capacitance

(each pin to GND)

C_IN

V_IN= 1.0 Vdc + 1 V_P-P

0.8

1.5

V (min)

V (max)

V_REF

Reference Voltage⁽⁵⁾⁽⁶⁾

1.0

(1) The inputs are protected as shown below. Input voltages above V_Aor below GND will not damage this device, provided current is limited

per⁽⁶⁾. However, errors in the A/D conversion can occur if the input goes above V_Aor below GND by more than 100 mV. As an example,

if V_Ais 3.3V, the full-scale input voltage must be ≤3.4V to ensure accurate conversions.

(2) To guarantee accuracy, it is required that |V_A–V_D| ≤ 100 mV and separate bypass capacitors are used at each power supply pin.

(3) With the test condition for V_REF= +1.0V (2 V_P-Pdifferential input), the 12-bit LSB is 488 µV.

(4) Typical figures are at T_A= T_J= 25°C, and represent most likely parametric norms. Test limits are guaranteed to TI's AOQL (Average

Outgoing Quality Level).

(5) Optimum dynamic performance will be obtained by keeping the reference input in the 0.8V to 1.5V range. The LM4051CIM3-ADJ or the

LM4051CIM3-1.2 band gap voltage reference is recommended for this application.

(6) When the input voltage at any pin exceeds the power supplies (that is, V_IN< AGND, or V_IN> V_A, V_Dor V_DR), the current at that pin

should be limited to 25 mA. The 50 mA maximum package input current rating limits the number of pins that can safely exceed the

power supplies with an input current of 25 mA to two.

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DC and Logic Electrical Characteristics

Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, V_A= V_D= +3.3V, V_DR

+2.5V, PD = 0V, V_REF= +1.0V external, V_CM= 1.65V, R_S< 100Ω, f_CLK= 80 MHz, t_r= t_f= 2 ns, f_IN= 70 MHz, C_L= 15 pF/pin.

Boldface limits apply for T_J= T_MINto T_MAX: all other limits T_J= 25°C^(1)(2)(3)(4)

Units

(Limits)

Symbol

Parameter

Conditions

Typical⁽⁴⁾Limits⁽⁴⁾

DYNAMIC CONVERTER CHARACTERISTICS

Full Power Bandwidth

Signal-to-Noise Ratio

-0.5 dBFS Input, Output at −3 dB

450

MHz

dB (min)

f_IN= 10 MHz, Differential V_IN= −0.5 dBFS

f_IN= 40 MHz, Differential V_IN= −0.5 dBFS

f_IN= 70 MHz, Differential V_IN= −0.5 dBFS

f_IN= 150 MHz, Differential V_IN= −0.5 dBFS

f_IN= 10 MHz, Differential V_IN= −0.5 dBFS

f_IN= 40 MHz, Differential V_IN= −0.5 dBFS

f_IN= 70 MHz, Differential V_IN= −0.5 dBFS

f_IN= 150 MHz, Differential V_IN= −0.5 dBFS

f_IN= 10 MHz, Differential V_IN= −0.5 dBFS

f_IN= 40 MHz, Differential V_IN= 0.5 dBFS

f_IN= 70 MHz, Differential V_IN= −0.5 dBFS

f_IN= 150 MHz, Differential V_IN= −0.5 dBFS

f_IN= 10 MHz, Differential V_IN= −0.5 dBFS

f_IN= 40 MHz, Differential V_IN= −0.5 dBFS

f_IN= 70 MHz, Differential V_IN= −0.5 dBFS

f_IN= 150 MHz, Differential V_IN= −0.5 dBFS

f_IN= 10 MHz, Differential V_IN= −0.5 dBFS

f_IN= 40 MHz, Differential V_IN= −0.5 dBFS

f_IN= 70 MHz, Differential V_IN= −0.5 dBFS

f_IN= 150 MHz, Differential V_IN= −0.5 dBFS

f_IN= 10 MHz, Differential V_IN= −0.5 dBFS

f_IN= 40 MHz, Differential V_IN= −0.5 dBFS

f_IN= 70 MHz, Differential V_IN= −0.5 dBFS

f_IN= 150 MHz, Differential V_IN= −0.5 dBFS

f_IN= 10 MHz, Differential V_IN= −0.5 dBFS

f_IN= 40 MHz, Differential V_IN= −0.5 dBFS

f_IN= 70 MHz, Differential V_IN= −0.5 dBFS

f_IN= 150 MHz, Differential V_IN= −0.5 dBFS

SNR

dB (min)

64.5

SINAD Signal-to-Noise & Distortion

62.7

10.2

10.1

-66

dB (min)

10.7

10.4

10.3

10.0

−77

-74

-71

-70

−80

-80

-79

−84

-81

-79

-78

Bits (min)

Bits

ENOB

THD

Effective Number of Bits

Total Harmonic Distortion

Second Harmonic Distortion

Third Harmonic Distortion

Bits (min)

Bits

dB (max)

-65

dB (max)

-68

dB (max)

2nd

Harm

-65.5

-69

dB (max)

3rd

Harm

-66

dB (max)

dB (min)

SFDR

IMD

Spurious Free Dynamic Range

Intermodulation Distortion

-65.5

dB (min)

f_IN1 = 19.6MHz, f_IN2 = 20.5 MHz,

each = -6.0 dBFS

dBFS

(1) The inputs are protected as shown below. Input voltages above V_Aor below GND will not damage this device, provided current is limited

per⁽⁶⁾. However, errors in the A/D conversion can occur if the input goes above V_Aor below GND by more than 100 mV. As an example,

if V_Ais 3.3V, the full-scale input voltage must be ≤3.4V to ensure accurate conversions.

(2) To guarantee accuracy, it is required that |V_A–V_D| ≤ 100 mV and separate bypass capacitors are used at each power supply pin.

(3) With the test condition for V_REF= +1.0V (2 V_P-Pdifferential input), the 12-bit LSB is 488 µV.

(4) Typical figures are at T_A= T_J= 25°C, and represent most likely parametric norms. Test limits are guaranteed to TI's AOQL (Average

Outgoing Quality Level).

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DC and Logic Electrical Characteristics (continued)

Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, V_A= V_D= +3.3V, V_DR

+2.5V, PD = 0V, V_REF= +1.0V external, V_CM= 1.65V, R_S< 100Ω, f_CLK= 80 MHz, t_r= t_f= 2 ns, f_IN= 70 MHz, C_L= 15 pF/pin.

Boldface limits apply for T_J= T_MINto T_MAX: all other limits T_J= 25°C^(1)(2)(3)(4)

Units

(Limits)

Symbol

Parameter

Conditions

Typical⁽⁴⁾Limits⁽⁴⁾

CLK, PD, OF DIGITAL INPUT CHARACTERISTICS

V_IN(1)

V_IN(0)

I_IN(1)

I_IN(0)

C_IN

Logical “1” Input Voltage

Logical “0” Input Voltage

Logical “1” Input Current

Logical “0” Input Current

Digital Input Capacitance

V_D= 3.3V

2.0

V (min)

V (max)

µA

V_D= 3.3V

0.8

V_IN+, V_IN− = 3.3V

V_IN+, V_IN− = 0V

−10

µA

D0–D11 DIGITAL OUTPUT CHARACTERISTICS

V_OUT(1)Logical “1” Output Voltage

V_OUT(0)Logical “0” Output Voltage

I_OUT= −0.5 mA

_DR− 0.18

V (min)

V (max)

I_OUT= 1.6 mA

V_OUT= 2.5V

0.4

+I_SC

Output Short Circuit Source Current V_OUT= 0V

−20

−I_SC

Output Short Circuit Sink Current

POWER SUPPLY CHARACTERISTICS

PD Pin = DGND

PD Pin = V_DR

120

168

mA (max)

I_A

Analog Supply Current

PD Pin = DGND

PD Pin = V_DR

11.5

mA (max)

I_D

Digital Supply Current

PD Pin = DGND, f_in= 0⁽⁵⁾⁽⁶⁾

PD Pin = V_DR

PD Pin = DGND, C_L= 0 pF⁽⁷⁾

PD Pin = V_DR

I_DR

Digital Output Supply Current

Total Power Consumption

425

590

mW (max)

Rejection of Full-Scale Gain Error

change with V_A= 3.0V vs. 3.6V

PSRR1 Power Supply Rejection Ratio

(5) I_DRis the current consumed by the switching of the output drivers and is primarily determined by load capacitance on the output pins,

the supply voltage, V_DR, and the rate at which the outputs are switching (which is signal dependent). I_DR=V_DR(C₀x f₀+ C₁x f₁+....C₁₁

f₁₁) where V_DRis the output driver power supply voltage, C_nis total capacitance on the output pin, and f_nis the average frequency at

which that pin is toggling.

(6) When the input voltage at any pin exceeds the power supplies (that is, V_IN< AGND, or V_IN> V_A, V_Dor V_DR), the current at that pin

should be limited to 25 mA. The 50 mA maximum package input current rating limits the number of pins that can safely exceed the

power supplies with an input current of 25 mA to two.

(7) Power consumption excludes output driver power. See Note 5.

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AC Electrical Characteristics

Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, V_A= V_D= +3.3V, V_DR

+2.5V, PD = 0V, V_REF= +1.0V external, V_CM= 1.65V, R_S< 100Ω, f_CLK= 80 MHz, t_r= t_f= 2 ns, f_IN= 70 MHz, C_L= 15 pF/pin.

Boldface limits apply for T_J= T_MINto T_MAX: all other limits T_J= 25°C^{(1)(2)(3)(4)(5)(6)}

Units

Symbol

Parameter

Conditions

Typical⁽⁴⁾Limits⁽⁴⁾

(Limits)

MHz (min)

MHz

Maximum Clock Frequency

Minimum Clock Frequency

% (max)

% (min)

Clock Duty Cycle

t_CH

Clock High Time

Clock Low Time

Conversion Latency

5.5

ns (min)

Clock Cycles

ns (max)

t_CL

t_CONV

V_DR= 2.5V

V_DR= 3.3V

5.2

4.8

8.3

7.5

t_OD

Data Output Delay after Rising CLK Edge

t_AD

t_AJ

Aperture Delay

Aperture Jitter

0.7

ps rms

0.1 µF on pins 30, 31, 32,

and 1.0 µF from pin 30 to 31

t_PD

Power Down Mode Exit Cycle

µs

(1) The inputs are protected as shown below. Input voltages above V_Aor below GND will not damage this device, provided current is limited

per⁽⁶⁾. However, errors in the A/D conversion can occur if the input goes above V_Aor below GND by more than 100 mV. As an example,

if V_Ais 3.3V, the full-scale input voltage must be ≤3.4V to ensure accurate conversions.

(2) To guarantee accuracy, it is required that |V_A–V_D| ≤ 100 mV and separate bypass capacitors are used at each power supply pin.

(3) With the test condition for V_REF= +1.0V (2 V_P-Pdifferential input), the 12-bit LSB is 488 µV.

(4) Typical figures are at T_A= T_J= 25°C, and represent most likely parametric norms. Test limits are guaranteed to TI's AOQL (Average

Outgoing Quality Level).

(5) Timing specifications are tested at TTL logic levels, V_IL= 0.4V for a falling edge and V_IH= 2.4V for a rising edge.

(6) When the input voltage at any pin exceeds the power supplies (that is, V_IN< AGND, or V_IN> V_A, V_Dor V_DR), the current at that pin

should be limited to 25 mA. The 50 mA maximum package input current rating limits the number of pins that can safely exceed the

power supplies with an input current of 25 mA to two.

Specification Definitions

APERTURE DELAY is the time after the rising edge of the clock to when the input signal is acquired or held for

conversion.

APERTURE JITTER (APERTURE UNCERTAINTY) is the variation in aperture delay from sample to sample.

Aperture jitter manifests itself as noise in the output.

COMMON MODE VOLTAGE (V_CM) is the d.c. potential present at both signal inputs to the ADC.

CONVERSION LATENCY See PIPELINE DELAY.

DIFFERENTIAL NON-LINEARITY (DNL) is the measure of the maximum deviation from the ideal step size of 1

LSB.

DUTY CYCLE is the ratio of the time that a repetitive digital waveform is high to the total time of one period. The

specification here refers to the ADC clock input signal.

EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE BITS) is another method of specifying Signal-to-Noise

and Distortion or SINAD. ENOB is defined as (SINAD - 1.76) / 6.02 and says that the converter is equivalent to a

perfect ADC of this (ENOB) number of bits.

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FULL POWER BANDWIDTH is a measure of the frequency at which the reconstructed output fundamental

drops 3 dB below its low frequency value for a full scale input.

GAIN ERROR is the deviation from the ideal slope of the transfer function. It can be calculated as:

Gain Error = Positive Full Scale Error − Offset Error

(1)

INTEGRAL NON LINEARITY (INL) is a measure of the deviation of each individual code from a best fit straight

line. The deviation of any given code from this straight line is measured from the center of that code value.

INTERMODULATION DISTORTION (IMD) is the creation of additional spectral components as a result of two

sinusoidal frequencies being applied to the ADC input at the same time. It is defined as the ratio of the power in

the second and third order intermodulation products to the power in one of the original frequencies. IMD is

usually expressed in dBFS.

MISSING CODES are those output codes that will never appear at the ADC outputs. The ADC12L080 is

guaranteed not to have any missing codes.

NEGATIVE FULL SCALE ERROR is the difference between the input voltage (V_IN+ − V_IN−) just causing a

transition from negative full scale to the first code and its ideal value of 0/5 LSB.

OFFSET ERROR is the input voltage that will cause a transition from a code of 01 1111 1111 to a code of 10

0000 0000/

OUTPUT DELAY is the time delay after the rising edge of the clock before the data update is presented at the

output pins.

PIPELINE DELAY (LATENCY) is the number of clock cycles between initiation of conversion and when that data

is presented to the output driver stage. Data for any given sample is available at the output pins the Pipeline

Delay plus the Output Delay after the sample is taken. New data is available at every clock cycle, but the data

lags the conversion by the pipeline delay.

POSITIVE FULL SCALE ERROR is the difference between the actual last code transition and its ideal value of

1½ LSB below positive full scale.

POWER SUPPLY REJECTION RATIO (PSRR) is a measure of how well the ADC rejects a change in the power

supply voltage. PSRR1 is the ratio of the change in Full-Scale Gain Error that results from a change in the d.c.

power supply voltage, expressed in dB. PSRR2 is a measure of how well an a.c. signal riding upon the power

supply is rejected at the output.

SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in dB, of the rms value of the input signal to the rms

value of the sum of all other spectral components below one-half the sampling frequency, not including

harmonics or d.c.

SIGNAL TO NOISE PLUS DISTORTION (S/N+D or SINAD) Is the ratio, expressed in dB, of the rms value of the

input signal to the rms value of all of the other spectral components below half the clock frequency, including

harmonics but excluding d.c.

SPURIOUS FREE DYNAMIC RANGE (SFDR) is the difference, expressed in dB, between the rms values of the

input signal and the peak spurious signal, where a spurious signal is any signal present in the output spectrum

that is not present at the input.

TOTAL HARMONIC DISTORTION (THD) is the ratio, expressed in dBc, of the rms total of the first nine

harmonic levels at the output to the level of the fundamental at the output. THD is calculated as

f10

+ . . . + A

THD = 20 x log

(2)

where A_f1is the RMS power of the fundamental (output) frequency and A_f2through A_f10are the RMS power in

the first 9 harmonic frequencies.

Second Harmonic Distortion (2nd Harm) is the difference expressed in dB, between the RMS power in the

input frequency at the output and the power in its 2nd harmonic level at the output.

Third Harmonic Distortion (3rd Harm) is the difference, expressed in dB, between the RMS power in the input

frequency at the output and the power in its 3rd harmonic level at the output.

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Timing Diagram

Sample N + 7

Sample N + 6

Sample N + 5

Sample N

Sample N + 8

Sample N + 9

CLK

Clock N

Clock N + 6

90%

10%

90%

10%

CLK

D0 - D11

Data N + 1 Data N + 2

Data N - 1

Data N

Latency

Figure 2. Output Timing

Transfer Characteristic

Figure 3. Transfer Characteristic

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Typical Performance Characteristics DNL, INL

V_A= V_D= 3.3V, V_DR= 2.5V, V_REF= 1.0V external, V_CM= 1.65V, f_CLK= 80 MHz, f_IN= 0, unless otherwise stated.

DNL

INL

Figure 4.

Figure 5.

DNL vs. f_CLK

INL vs. f_CLK

Figure 6.

Figure 7.

DNL vs. Clock Duty Cycle

INL vs. Clock Duty Cycle

Figure 8.

Figure 9.

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Typical Performance Characteristics DNL, INL (continued)

V_A= V_D= 3.3V, V_DR= 2.5V, V_REF= 1.0V external, V_CM= 1.65V, f_CLK= 80 MHz, f_IN= 0, unless otherwise stated.

DNL vs. Temperature

INL vs. Temperature

Figure 10.

Figure 11.

DNL vs. V_DR

INL vs. V_DR

Figure 12.

Figure 13.

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Typical Performance Characteristics

V_A= V_D= 3.3V, V_DR= 2.5V, V_REF= 1.0V external, V_CM= 1.65V, f_CLK= 80 MHz, f_IN= 70 MHz, unless otherwise stated.

SNR,SINAD,SFDR vs. V_A

Distortion vs. V_A

Figure 14.

Figure 15.

SNR,SINAD,SFDR vs. V_DR

Distortion vs. V_DR

Figure 16.

Figure 17.

SNR,SINAD,SFDR vs. V_CM

Distortion vs. V_CM

Figure 18.

Figure 19.

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Typical Performance Characteristics (continued)

V_A= V_D= 3.3V, V_DR= 2.5V, V_REF= 1.0V external, V_CM= 1.65V, f_CLK= 80 MHz, f_IN= 70 MHz, unless otherwise stated.

SNR,SINAD,SFDR vs. f_CLK

Distortion vs. f_CLK

Figure 20.

Figure 21.

SNR,SINAD,SFDR vs. Clock Duty Cycle

Distortion vs. Clock Duty Cycle

Figure 22.

Figure 23.

SNR,SINAD,SFDR vs. V_REF

Distortion vs. V_REF

Figure 24.

Figure 25.

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Typical Performance Characteristics (continued)

V_A= V_D= 3.3V, V_DR= 2.5V, V_REF= 1.0V external, V_CM= 1.65V, f_CLK= 80 MHz, f_IN= 70 MHz, unless otherwise stated.

SNR,SINAD,SFDR vs. f_IN

Distortion vs. f_IN

Figure 26.

Figure 27.

SNR,SINAD,SFDR vs. Temperature

Distortion vs. Temperature

Figure 28.

t_ODvs. V_DR

Figure 29.

Spectral Response @ 10 MHz Input

Figure 30.

Figure 31.

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Typical Performance Characteristics (continued)

V_A= V_D= 3.3V, V_DR= 2.5V, V_REF= 1.0V external, V_CM= 1.65V, f_CLK= 80 MHz, f_IN= 70 MHz, unless otherwise stated.

Spectral Response @ 40 MHz Input

Spectral Response @ 70 MHz Input

Figure 32.

Figure 33.

Spectral Response @ 150 MHz Input

Intermodulation Distortion, f_IN1= 19.6 MHz, f_IN2 = 20.5 MHz

Figure 34.

Figure 35.

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FUNCTIONAL DESCRIPTION

Operating on a single +3.3V supply, the ADC12L080 uses a pipeline architecture with error correction circuitry to

help ensure maximum performance.

Differential analog input signals are digitized to 12 bits. Each analog input signal should have a peak-to-peak

voltage equal to the input reference voltage, V_REF, be centered around V_REFand be 180° out of phase with each

other. Table 1 and Table 2 indicate the input to output relationship of the ADC12L080. Although a differential

input signal is required for rated operation, single-ended operation is possible with reduced performance if one

input is biased to V_REFand the other input is driven. If the driven input is presented with its full range signal, there

will be a 6 dB reduction of the output range, limiting it to the range of ¼ to ¾ of the minimum output range

obtainable if both inputs were driven with complimentary signals. Signal Inputs explains how to avoid this signal

reduction.

Table 1. Input to Output Relationship—Differential Input

V_IN

V_IN−

Output

_CM− V_REF

V_CM+ V_REF

V_CM+0.5 * V_REF

V_CM

0000 0000 0000

0100 0000 0000

1000 0000 0000

1100 0000 0000

1111 1111 1111

_CM−0.5 * V_REF

V_CM

V_CM+0.5 * V_REF

V_CM+ V_REF

V_CM−0.5 * V_REF

V_CM− V_REF

Table 2. Input to Output Relationship—Single-Ended Input

−

V_IN

Output

_CM− 2 * V_REF

V_CM

0000 0000 0000

0100 0000 0000

1000 0000 0000

1100 0000 0000

1111 1111 1111

V_CM− V_REF

V_CM

V_CM+ V_REF

V_CM+ 2 * V_REF

The output word rate is the same as the clock frequency, which may be in within the range indicated in the

Electrical Tables. The analog input voltage is acquired at the rising edge of the clock and the digital data for that

sample is delayed by the pipeline for 6 clock cycles.

A logic high on the power down (PD) pin reduces the converter power consumption to 50 mW.

Applications Information

OPERATING CONDITIONS

We recommend that the conditions in the Operating Table be observed for operation of the ADC12L080.

ANALOG INPUTS

The ADC12L080 has two analog signal inputs, V_IN+ and V_IN−, which form a differential input pair. There is one

reference input pin, V_REF

Reference Pins

The ADC12L080 can be used with the internal 1.0V reference or with an external reference. While designed and

specified to operate with a 1.0V reference, the ADC12L080 performs well with reference voltages in the range of

indicated in the Operating Ratings table. Lower reference voltages will decrease the signal-to-noise ratio (SNR)

of the ADC12L080. Higher reference voltages (and input signal swing) will degrade THD performance for a full-

scale input.

An input voltage below 2.0V at pin 1 (V_REF) is interpreted to be an external reference and is used as such.

Connecting this pin to the analog supply (V_A) will force the use of the internal 1.0V reference.

It is very important that all grounds associated with the reference voltage and the input signal make connection to

the analog ground plane at a single, quiet point to minimize the effects of noise currents in the ground path.

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The reference input pin serves two functions. When the input at this pin at or below 2V, this voltage is accepted

as the reference for the converter. When this voltage is connected to V_A, then internal 1.0V reference is used.

Functionality is undefined with voltages at this pin between 2V and V_A.

The three Reference Bypass Pins (V_RP, V_RMand V_RN) are made available for bypass purposes only. These pins

should each be bypassed to ground with a 0.1 µF capacitor, and a 1.0 µF should be connected from V_RPto V_RN

Higher capacitances will result in a longer power down exit cycle. Lower capacitances may result in degraded

dynamic performance. DO NOT LOAD these pins.

Signal Inputs

The signal inputs are V_IN+ and V_IN−. The input signal, V_IN, is defined as

V_IN= (V_IN) – (V_IN−)

(3)

Figure 36 shows the expected input signal range. Note that the nominal input common mode voltage, V_CM, is

V_A/2 and the nominal input signals each run between the limits of AGND and V_REF. The Peaks of the input

signals should never exceed the voltage described as

Peak Input Voltage = V_A− 0.5V

(4)

to maintain dynamic performance.

REF

(a) Differential Input

REF

(b) Single-Ended Input

Figure 36. Expected Input Signal Range

The ADC12L080 performs best with a differential input, each of which should be centered around a common

mode voltage, V_CM. The peak-to-peak voltage swing at both V_IN+ and V_IN− should not exceed the value of the

reference voltage or the output data will be clipped. The two input signals should be exactly 180° out of phase

from each other and of the same amplitude. For single frequency inputs, angular errors result in a reduction of

the effective full scale input. For a complex waveform, however, angular errors will result in distortion.

The full scale error in LSB for a sine wave input can be described as approximately

E_FS= 4096 ( 1 - sin (90° + dev))

(5)

Where dev is the angular difference between the two signals having a 180° relative phase relationship to each

other (see Figure 37). Drive the analog inputs with a source impedance less than 100Ω.

Figure 37. Angular Errors Between the Two Input Signals Will Reduce the Output Level or Cause

Distortion

For differential operation, each analog input signal should have a peak-to-peak voltage equal to the input

reference voltage, V_REF, and be centered around V_CM. For single-ended operation (which will result in reduced

performance), one of the analog inputs should be connected to the d.c. common mode voltage of the driven

input. The peak-to-peak differential input signal should be twice the reference voltage to maximize SNR and

SINAD performance (Figure 36b). For example, set V_REFto 1.0V, bias V_IN− to 1.0V and drive V_IN+ with a signal

range of 0V to 2.0V.

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Because very large input signal swings can degrade distortion performance, better performance with a single-

ended input can be obtained by reducing the reference voltage while maintaining a full-range output. Table 1 and

Table 2 indicate the input to output relationship of the ADC12L080.

The V_IN+ and the V_IN− inputs of the ADC12L080 consist of an analog switch followed by a switched-capacitor

amplifier. The internal switching action at the analog inputs causes energy to be output from the input pins. As

the driving source tries to compensate for this, it adds noise to the signal. To minimize this, use 33Ω series

resistors at each of the signal inputs with a 51 pF capacitor to ground, as can be seen in Figure 39 and

Figure 40. These components should be placed close to the ADC because the input pins of the ADC is the most

sensitive part of the system and this is the last opportunity to filter the input. The 51 pF capacitor value is for

Nyquist applications and should be replaced with a smaller capacitor for undersampling applications. The

resulting pole should be at 1.7 to 2.0 times the highest input frequency. When determining this capacitor value,

take into consideration the 8 pF ADC input capacitance.

Table 3 gives component values for Figure 39 to convert a signals to a range 1.0V ±0.5V at each of the

differential input pins of the ADC12L080.

Table 3. Resistor values for Circuit of Figure 39

SIGNAL RANGE

0 - 0.25V

0 - 0.5V

0Ω

R5, R6

1000Ω

499Ω

open

1210Ω

200Ω

249Ω

100Ω

1780Ω

1400Ω

1210Ω

0Ω

±0.5V

100Ω

499Ω

DIGITAL INPUTS

Digital inputs consist of CLK, OF and PD. All digital inputs are 3V CMOS compatible.

CLK

The CLK signal controls the timing of the sampling process. Drive the clock input with a stable, low jitter clock

signal in the range indicated in the Electrical Table with rise and fall times of less than 2 ns. The trace carrying

the clock signal should be as short as possible and should not cross any other signal line, analog or digital, not

even at 90°.

The CLK signal also drives an internal state machine. If the CLK is interrupted, or its frequency is too low, the

charge on internal capacitors can dissipate to the point where the accuracy of the output data will degrade. This

is what limits the minimum sample rate.

The duty cycle of the clock signal can affect the performance of any A/D Converter. Because achieving a precise

duty cycle is difficult, the ADC12L080 is designed to maintain performance over a range of duty cycles. While it is

specified and performance is guaranteed with a 50% clock duty cycle, performance is typically maintained over a

clock duty cycle range indicated in the Electrical Table.

The clock line should be terminated at its source in the characteristic impedance of that line. Take care to

maintain a constant clock line impedance throughout the length of the line. Refer to Application Note AN-905 for

information on setting characteristic impedance.

It is highly desirable that the the source driving the ADC CLK pin only drive that pin. However, if that source is

used to drive other things, each driven pin should be a.c. terminated with a series RC to ground, as shown in

Figure 38, such that the resistor value is equal to the characteristic impedance of the clock line and the capacitor

value is

(6)

where t_PDis the signal propagation rate down the clock line, "L" is the line length and Z_Ois the characteristic

impedance of the clock line. This termination should be as close as possible to the ADC clock pin but beyond it

as seen from the clock source. Typical t_PDis about 150 ps/inch (60 ps/cm) on FR-4 board material. The units of

"L" and t_PDshould be the same (inches or centimeters).

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The OF pin is used to determine the digital data output format. When this pin is high, the output formant is two's

complement. When this pin is low the output format is offset binary. Changing this pin while the device is

operating will result in uncertainty of the data for a few conversion cycles.

The PD pin, when high, holds the ADC12L080 in a power-down mode to conserve power when the converter is

not being used. The power consumption in this state is 50 mW and is not affected by the clock frequency, or by

whether there is a clock signal present. The output data pins are undefined and the data in the pipeline is

corrupted while in the power down mode.

The Power Down Mode Exit Cycle time is determined by the value of the capacitors on pins 30, 31 and 32.

These capacitors loose their charge in the Power Down mode and must be recharged by on-chip circuitry before

conversions can be accurate. See Reference Pins.

OUTPUTS

The ADC12L080 has 12 TTL/CMOS compatible Data Output pins. The output data is present at these outputs

while the PD pin is low. While the t_ODtime provides information about output timing, a simple way to capture a

valid output is to latch the data on the rising edge of the conversion clock (pin 10).

Be very careful when driving a high capacitance bus. The more capacitance the output drivers must charge for

each conversion, the more instantaneous digital current flows through V_DRand DR GND. These large charging

current spikes can cause on-chip noise and couple into the analog circuitry, degrading dynamic performance.

Adequate bypassing, limiting output capacitance and careful attention to the ground plane will reduce this

problem. Additionally, bus capacitance beyond the specified 15 pF/pin will cause t_ODto increase, making it

difficult to properly latch the ADC output data. The result could be an apparent reduction in dynamic

performance.

To minimize noise due to output switching, minimize the load currents at the digital outputs. This can be done by

connecting buffers between the ADC outputs and any other circuitry (74ACQ541, for example). Only one driven

input should be connected to each output pin. Additionally, inserting series 100Ω resistors at the digital outputs,

close to the ADC pins, will isolate the outputs from trace and other circuit capacitances and limit the output

currents, which could otherwise result in performance degradation. See Figure 38.

While the ADC12L080 will operate with V_DRvoltages down to 1.8V, t_ODincreases with reduced V_DR. Be careful of

external timing when using reduced V_DR

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+1.8V to 3.6V

+3.3V

10 mF

470

200

REF

0.1 mF

VDR

Power

Down

1.00k

LM4150-1.2

1 mF

REF

12 x 47W

D11 (MSB)

Ground for the 1.00k resistor, the

0.1 mF bypass capacitor, the ground

pin for the LM4050-2.5, the bypass

capacitors on pins 30, 31 and 32 of

the ADC12L080 and pin 28 of the

ADC12L080 should be connected to

a common point in the analog

ground plane.

0.1 mF

D10

1 mF

74ACQ541

ADC12L080

12 BIT

DATA

OUTPUT

CLK

Differential

Drive

See Fig 5

SIGNAL

INPUT

D0 (LSB)

CLOCK

INPUT

74ACQ541

CLK

1/4

74ACQ04

AGND

DGND

DRGND

see

text

See

Text

CLK

Figure 38. Simple Application Circuit with Single-Ended to Differential Buffer

Figure 39. Differential Drive Circuit of Figure 38

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+1.8V to +3.6V

+3.3V

10 mF

470

200

REF

0.1 mF

0.1 mF *

1.00k

LM4140-1.2

1 mF

Power Down

REF

Ground for the 1.00k resistor, the

1 mF bypass capacitor, the ground

pin for the LM4040-2.5, the bypass

capacitors on pins 30, 31 and 32 of

the ADC12L080 and pin 28 of the

ADC12L080 should be connected to

a common point in the ground plane.

D11 (MSB)

0.1 mF

D10

1 mF

0.1 mF

Output

Word

ADC12L080

51 pF

0.1 mF

SIGNAL

INPUT

D0 (LSB)

MiniCircuits

T4-6T

51 pF

CLOCK

INPUT

CLK

AGND

DGND

DRGND

see

text

The 51 pF capacitors at

pins 2 and 3 are for

oversampling applications.

See text for

undersampling applications.

Figure 40. Driving the Signal Inputs with a Transformer

POWER SUPPLY CONSIDERATIONS

The power supply pins should be bypassed with a 10 µF capacitor and with a 0.1 µF low ESL ceramic chip

capacitor within 3 millimeters of each power pin.

As is the case with all high-speed converters, the ADC12L080 is sensitive to power supply noise. Accordingly,

the noise on the analog supply pin should be kept below 100 mV_P-P

No pin should ever have a voltage on it that is in excess of the supply voltages, not even on a transient basis. Be

especially careful of this during turn on and turn off of power.

The V_DRpin provides power for the output drivers and may be operated from a supply in the range of 1.8V to V_D.

This can simplify interfacing to devices and systems operating with supplies less than V_D. DO NOT operate the

V_DRpin at a voltage higher than V_D.

LAYOUT AND GROUNDING

Proper grounding and proper routing of all signals are essential to ensure accurate conversion. Maintaining

separate analog and digital areas of the board, with the ADC12L080 between these areas, is required to achieve

specified performance.

The ground return for the data outputs (DR GND) carries the ground current for the output drivers. The output

current can exhibit high transients that could add noise to the conversion process. To prevent this from

happening, the DR GND pins should NOT be connected to system ground in close proximity to any of the

ADC12L080's other ground pins.

Capacitive coupling between the typically noisy digital circuitry and the sensitive analog circuitry can lead to poor

performance. The solution is to keep the analog circuitry separated from the digital circuitry, and to keep the

clock line as short as possible.

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Digital circuits create substantial supply and ground current transients. The logic noise thus generated could

have significant impact upon system noise performance. The best logic family to use in systems with A/D

converters is one which employs non-saturating transistor designs, or has low noise characteristics, such as the

74LS, 74HC(T) and 74AC(T)Q families. The worst noise generators are logic families that draw the largest

supply current transients during clock or signal edges, like the 74F and the 74AC(T) families.

The effects of the noise generated from the ADC output switching can be minimized through the use of 100Ω

resistors in series with each data output line. Locate these resistors as close to the ADC output pins as possible.

Since digital switching transients are composed largely of high frequency components, total ground plane copper

weight will have little effect upon the logic-generated noise. This is because of the skin effect. Total surface area

is more important than is total ground plane volume.

Generally, analog and digital lines should cross each other at 90° to avoid crosstalk. To maximize accuracy in

high speed, high resolution systems, however, avoid crossing analog and digital lines altogether. It is important to

keep clock lines as short as possible and isolated from ALL other lines, including other digital lines. Even the

generally accepted 90° crossing should be avoided with the clock line as even a little coupling can cause

problems at high frequencies. This is because other lines can introduce jitter into the clock line, which can lead to

degradation of SNR. Also, the high speed clock can introduce noise into the analog chain.

Best performance at high frequencies and at high resolution is obtained with a straight signal path. That is, the

signal path through all components should form a straight line wherever possible.

Be especially careful with the layout of inductors. Mutual inductance can change the characteristics of the circuit

in which they are used. Inductors should not be placed side by side, even with just a small part of their bodies

beside each other.

Figure 41. Example of a Suitable Layout

The analog input should be isolated from noisy signal traces to avoid coupling of spurious signals into the input.

Any external component (e.g., a filter capacitor) connected between the converter's input pins and ground or to

the reference input pin and ground should be connected to a very clean point in the ground plane.

Figure 41 gives an example of a suitable layout. All analog circuitry (input amplifiers, filters, reference

components, etc.) should be placed in the analog area of the board. All digital circuitry and I/O lines should be

placed in the digital area of the board. Furthermore, all components in the reference circuitry and the input signal

chain that are connected to ground should be connected together with short traces and enter the ground plane at

a single point. All ground connections should have a low inductance path to ground.

Best performance will be obtained with a single ground plane and separate analog and digital power planes. The

power planes define analog and digital board areas of the board. Analog and digital components and signal lines

should be kept within their own areas.

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DYNAMIC PERFORMANCE

To achieve the best dynamic performance, the clock source driving the CLK input must be free of jitter. The

maximum allowable jitter to avoid the addition of noise to the conversion process is

Max Jitter = 1 / (2ⁿ⁺¹× π × f_IN)

(7)

Isolate the ADC clock from any digital circuitry with buffers, as with the clock tree shown in Figure 42. To avoid

adding jitter to the clock signal, the elements of Figure 42 should be capable of toggling at a up to ten times the

frequency used.

As mentioned in LAYOUT AND GROUNDING, it is good practice to keep the ADC clock line as short as possible

and to keep it well away from any other signals. Other signals can introduce jitter into the clock signal, which can

lead to reduced SNR performance, and the clock can introduce noise into other lines. Even lines with 90°

crossings have capacitive coupling, so try to avoid even these 90° crossings of the clock line.

Figure 42. Isolating the ADC Clock from other Circuitry with a Clock Tree

COMMON APPLICATION PITFALLS

Driving the inputs (analog or digital) beyond the power supply rails. For proper operation, all inputs should

not go more than 100 mV beyond the supply rails (more than 100 mV below the ground pins or 100 mV above

the supply pins). Exceeding these limits on even a transient basis may cause faulty or erratic operation. It is not

uncommon for high speed digital components (e.g., 74F and 74AC devices) to exhibit overshoot or undershoot

that goes above the power supply or below ground. A resistor of about 50Ω to 100Ω in series with any offending

digital input, close to the signal source, will eliminate the problem.

Do not allow input voltages to exceed the supply voltage, even on a transient basis. Not even during power up or

power down.

Be careful not to overdrive the inputs of the ADC12L080 with a device that is powered from supplies outside the

range of the ADC12L080 supply. Such practice may lead to conversion inaccuracies and even to device

damage.

Attempting to drive a high capacitance digital data bus. The more capacitance the output drivers must

charge for each conversion, the more instantaneous digital current flows through V_DRand DR GND. These large

charging current spikes can couple into the analog circuitry, degrading dynamic performance. Adequate

bypassing and maintaining separate analog and digital areas on the PC board will reduce this problem.

Additionally, bus capacitance beyond the specified 15 pF/pin will cause t_ODto increase, making it difficult to

properly latch the ADC output data. The result could, again, be an apparent reduction in dynamic performance.

The digital data outputs should be buffered (with 74ACQ541, for example). Dynamic performance can also be

improved by adding series resistors at each digital output, close to the ADC12L080, which reduces the energy

coupled back into the converter output pins by limiting the output current. A reasonable value for these resistors

is 100Ω.

Using an inadequate amplifier to drive the analog input. As explained in Signal Inputs, the sampling input is

difficult to drive without degrading dynamic performance.

If the amplifier exhibits overshoot, ringing, or any evidence of instability, even at a very low level, it will degrade

performance. A small series resistor at each amplifier output and a capacitor at each of the ADC analog inputs to

ground (as shown in Figure 39 and Figure 40) will improve performance. The LMH6702, LMH6628, LMH6622

and LMH6655 have been successfully used to drive the analog inputs of the ADC12L080.

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Product Folder Links: ADC12L080

ADC12L080

SNAS200B –OCTOBER 2004–REVISED MARCH 2013

www.ti.com

Also, it is important that the signals at the two inputs have exactly the same amplitude and be exactly 180º out of

phase with each other. Board layout, including equality of the length of the two traces to the input pins, will affect

the effective phase between these two signals. Remember that an operational amplifier operated in the non-

inverting configuration will exhibit more time delay than will the same device operating in the inverting

configuration.

Operating with the reference pins outside of the specified range. As mentioned in Reference Pins, V_REF

should be in the range specified in the Operating Ratings table. Operating outside of these limits could lead to

performance degradation.

Using a clock source with excessive jitter, using excessively long clock signal trace, or having other

signals coupled to the clock signal trace. This will cause the sampling interval to vary, causing excessive

output noise and a reduction in SNR and SINAD performance.

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Product Folder Links: ADC12L080

ADC12L080

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SNAS200B –OCTOBER 2004–REVISED MARCH 2013

REVISION HISTORY

Changes from Revision A (March 2013) to Revision B

Page

•

Changed layout of National Data Sheet to TI format .......................................................................................................... 26

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Product Folder Links: ADC12L080

PACKAGE OPTION ADDENDUM

www.ti.com

10-Dec-2020

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

ADC12L080CIVY/NOPB

ACTIVE

LQFP

NEY

250

RoHS & Green

Level-3-260C-168 HR

-40 to 85

ADC12L0

80CIVY

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

23-Jun-2023

TRAY

L - Outer tray length without tabs

KO -

Outer

tray

height

W -

Outer

tray

width

Text

P1 - Tray unit pocket pitch

CW - Measurement for tray edge (Y direction) to corner pocket center

CL - Measurement for tray edge (X direction) to corner pocket center

Chamfer on Tray corner indicates Pin 1 orientation of packed units.

*All dimensions are nominal

Device

Package Package Pins SPQ Unit array

Max

matrix temperature

(°C)

L (mm)

Name

Type

(mm) (µm) (mm) (mm) (mm)

ADC12L080CIVY/NOPB

NEY

LQFP

250

9 X 24

150

322.6 135.9 7620 12.2

11.1 11.25

Pack Materials-Page 1

PACKAGE OUTLINE

NEY0032A

LQFP - 1.6 mm max height

SCALE 1.800

PLASTIC QUAD FLATPACK

7.1

6.9

PIN 1 ID

7.1

6.9

9.4

TYP

8.6

0.27

0.17

OPTIONAL:

SHARP CORNERS EXCEPT

PIN 1 ID CORNER

28X 0.8

4X 5.6

32X

0.2

C A B

SEE DETAIL A

1.6 MAX

SEATING PLANE

0.09-0.20

TYP

0.25

GAGE PLANE

(1.4)

0.1

0.15

0.05

0.75

0.45

0 -7

DETAIL

DETAIL A

TYPICAL

4219901/A 10/2016

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. Reference JEDEC registration MS-026.

www.ti.com

EXAMPLE BOARD LAYOUT

NEY0032A

LQFP - 1.6 mm max height

PLASTIC QUAD FLATPACK

SYMM

32X (1.6)

32X (0.4)

SYMM

(8.5)

28X (0.8)

(R0.05) TYP

(8.5)

LAND PATTERN EXAMPLE

SCALE:8X

0.07 MAX

ALL AROUND

0.07 MIN

ALL AROUND

METAL

METAL UNDER

SOLDER MASK

OPENING

SOLDER MASK

DEFINED

NON SOLDER MASK

DEFINED

SOLDER MASK DETAILS

4219901/A 10/2016

NOTES: (continued)

4. Publication IPC-7351 may have alternate designs.

5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com

EXAMPLE STENCIL DESIGN

NEY0032A

LQFP - 1.6 mm max height

PLASTIC QUAD FLATPACK

SYMM

32X (1.6)

32X (0.4)

SYMM

(8.5)

28X (0.8)

(R0.05) TYP

(8.5)

SOLDER PASTE EXAMPLE

SCALE 8X

4219901/A 10/2016

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

7. Board assembly site may have different recommendations for stencil design.

www.ti.com

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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD

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These resources are subject to change without notice. TI grants you permission to use these resources only for development of an

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TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

ADC12L080CIVY/NOPB [TI]

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