ADC3244E [TI]
具有扩展温度范围的双通道 14 位 125MSPS 模数转换器 (DAC);
| 型号： | ADC3244E |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有扩展温度范围的双通道 14 位 125MSPS 模数转换器 (DAC) 转换器 模数转换器 |
| 文件： | 总53页 (文件大小：2799K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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ADC3244E
ZHCSJF0 –FEBRUARY 2019
ADC3244E 双通道、14 位、125MSPS 模数转换器
1 特性
3 说明
1
•
•
•
•
•
双通道
ADC3244E 是一款高线性度、超低功耗、双通道、14
位、25MSPS 至 125MSPS 模数转换器 (ADC)。该器
件专门用于支持严苛的、高输入频率信号（具有较大动
态范围的要求）。输入时钟分频器使得系统时钟架构设
计更加灵活，SYSREF 输入可实现系统完全同步。
14 位分辨率
单电源：1.8V
串行 LVDS 接口 (SLVDS)
支持 1 分频、2 分频和 4 分频的灵活输入时钟缓冲
器
ADC3244E 支持串行、低压、差分信令 (LVDS)，从而
减少接口线路的数量，实现高系统集成密度。串行
LVDS 接口为双线制，可对每个 ADC 的数据进行串行
并通过两对 LVDS 输出。内部锁相环 (PLL) 会将传入
的 ADC 采样时钟加倍，以获得串行输出各通道的 14
位输出数据时所使用的位时钟。除了串行数据流之外，
数据帧和位时钟也作为 LVDS 输出进行传送。
•
•
fIN = 70MHz 时，信噪比 (SNR) = 72.4dBFS，无杂
散动态范围 (SFDR) = 87dBc
超低功耗：
–
125MSPS 时为每通道 116mW
•
•
•
•
•
•
通道隔离：105dB
内部抖动和斩波
器件信息(1)
支持多芯片同步
与 12 位版本之间具有引脚到引脚兼容性
封装：VQFN-48 (7mm × 7mm)
扩展温度范围：-50°C 至 +105°C
器件型号
ADC3244E
封装
VQFN (48)
封装尺寸（标称值）
7.00mm × 7.00mm
(1) 要了解所有可用封装，请见数据表末尾的封装选项附录。
2 应用
•
•
•
•
•
•
•
•
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多载波、多模式蜂窝基站
雷达和智能天线阵列
军需品指导
电机控制反馈
网络和矢量分析器
通信测试设备
无损检测
微波接收器
软件定义的无线电 (SDR)
正交和多样性无线电接收器
手持式无线电和仪表
fS = 125MSPS、fIN = 10MHz 时的性能
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
0
12.5
25
37.5
50
62.5
Frequency (MHz)
D101
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SBAS716
ADC3244E
ZHCSJF0 –FEBRUARY 2019
www.ti.com.cn
目录
1
2
3
4
5
6
7
特性.......................................................................... 1
9
Detailed Description ............................................ 20
9.1 Overview ................................................................. 20
9.2 Functional Block Diagram ....................................... 20
9.3 Feature Description................................................. 21
9.4 Device Functional Modes........................................ 25
9.5 Programming........................................................... 26
9.6 Register Maps......................................................... 30
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Device Comparison Table..................................... 3
Pin Configuration and Functions......................... 3
Specifications......................................................... 5
7.1 Absolute Maximum Ratings ...................................... 5
7.2 ESD Ratings.............................................................. 5
7.3 Recommended Operating Conditions....................... 5
7.4 Thermal Information.................................................. 6
7.5 Electrical Characteristics: General............................ 6
7.6 Electrical Characteristics: AC Performance.............. 7
7.7 Digital Characteristics ............................................... 9
7.8 Timing Requirements: General ................................. 9
7.9 Timing Requirements: LVDS Output....................... 10
7.10 Typical Characteristics.......................................... 11
7.11 Typical Characteristics: Contour ........................... 17
Parameter Measurement Information ................ 18
8.1 Timing Diagrams..................................................... 18
10 Applications and Implementation...................... 42
10.1 Application Information.......................................... 42
10.2 Typical Applications .............................................. 43
11 Power Supply Recommendations ..................... 45
12 Layout................................................................... 46
12.1 Layout Guidelines ................................................. 46
12.2 Layout Example .................................................... 46
13 器件和文档支持 ..................................................... 47
13.1 接收文档更新通知 ................................................. 47
13.2 社区资源................................................................ 47
13.3 商标....................................................................... 47
13.4 静电放电警告......................................................... 47
13.5 术语表 ................................................................... 47
14 机械、封装和可订购信息....................................... 47
8
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
日期
修订版本
说明
2019 年2 月
*
初始发行版。
2
Copyright © 2019, Texas Instruments Incorporated
ADC3244E
www.ti.com.cn
ZHCSJF0 –FEBRUARY 2019
5 Device Comparison Table
RESOLUTION
INTERFACE
(Bits)
25 MSPS
ADC3221
ADC3241
—
50 MSPS
ADC3222
ADC3242
—
80 MSPS
ADC3223
ADC3243
—
125 MSPS
160 MSPS
12
ADC3224
ADC3244
ADC3244E(1)
ADC32J24
ADC32J44
—
—
Serial LVDS
14
—
12
14
—
ADC32J22
ADC32J42
ADC32J23
ADC32J43
ADC32J25
ADC32J45
JESD204B
—
(1) The ADC3244E is specified at extended temperature range of –50°C to +105°C. Other devices in the table are specified at standard
industrial temperature range of –40°C to +85°C.
6 Pin Configuration and Functions
RGZ Package
48-Pin VQFN
Top View
GND
DVDD
GND
1
36
35
34
33
32
31
30
29
28
27
26
25
GND
2
DVDD
GND
3
DVDD
GND
4
DVDD
GND
5
AVDD
AVDD
AVDD
AVDD
INAP
6
PDN
Thermal Pad
7
AVDD
AVDD
AVDD
INBP
INBM
AVDD
8
9
10
11
12
INAM
AVDD
Not to scale
Copyright © 2019, Texas Instruments Incorporated
3
ADC3244E
ZHCSJF0 –FEBRUARY 2019
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Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
6-9, 12, 17, 20, 25,
28-30
AVDD
I
Analog 1.8-V power supply
CLKM
CLKP
DA0M
DA0P
DA1M
DA1P
DB0M
DB0P
DB1M
DB1P
DCLKM
DCLKP
DVDD
FCLKM
FCLKP
GND
18
I
Negative differential clock input for the ADC
Positive differential clock input for the ADC
Negative serial LVDS output for channel A0
Positive serial LVDS output for channel A0
Negative serial LVDS output for channel A1
Positive serial LVDS output for channel A1
Negative serial LVDS output for channel B0
Positive serial LVDS output for channel B0
Negative serial LVDS output for channel B1
Positive serial LVDS output for channel B1
Negative bit clock output
19
I
48
O
O
O
O
O
O
O
O
O
O
I
47
46
45
40
39
38
37
44
43
Positive bit clock output
2, 4, 33, 35
Digital 1.8-V power supply
42
O
O
I
Negative frame clock output
41
Positive frame clock output
1, 3, 5, 32, 34, 36
Ground, 0 V
INAM
11
10
26
27
I
Negative differential analog input for channel A
Positive differential analog input for channel A
Negative differential analog input for channel B
Positive differential analog input for channel B
INAP
I
INBM
I
INBP
I
Power-down control. This pin can be configured using the SPI.
This pin has an internal 150-kΩ pulldown resistor.
PDN
31
I
RESET
SCLK
21
13
14
16
I
I
Hardware reset; active high. This pin has an internal 150-kΩ pulldown resistor.
Serial interface clock input. This pin has an internal 150-kΩ pulldown resistor.
Serial interface data input. This pin has an internal 150-kΩ pulldown resistor.
Serial interface data output
SDATA
SDOUT
I
O
Serial interface enable; active low.
This pin has an internal 150-kΩ pullup resistor to AVDD.
SEN
15
I
SYSREFM
SYSREFP
VCM
23
22
24
I
I
Negative external SYSREF input
Positive external SYSREF input
Common-mode voltage for analog inputs
Thermal pad. Connect to ground.
O
I
Thermal Pad
4
Copyright © 2019, Texas Instruments Incorporated
ADC3244E
www.ti.com.cn
ZHCSJF0 –FEBRUARY 2019
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
MAX
UNIT
V
Analog supply voltage, AVDD
Digital supply voltage, DVDD
INAP, INBP, INAM, INBM
2.1
2.1
V
min (1.9, AVDD + 0.3)
CLKP, CLKM
AVDD + 0.3
AVDD + 0.3
3.9
Voltage applied to input
pins
V
SYSREFP, SYSREFM
SCLK, SEN, SDATA, RESET, PDN
TJ
Operating junction temperature
Storage temperature
125
ºC
ºC
Tstg
–65
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings
VALUE
UNIT
V(ESD)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±2000
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)(1)
MIN
NOM
MAX
UNIT
SUPPLIES
AVDD
Analog supply voltage
Digital supply voltage
1.7
1.7
1.8
1.8
1.9
1.9
V
V
DVDD
ANALOG INPUT
For input frequencies < 450 MHz
For input frequencies < 600 MHz
2
1
VID
VIC
Differential input voltage
Input common-mode voltage
VPP
V
VCM ± 0.025
CLOCK INPUT
Input clock frequency(2)
Sampling clock frequency
Sine wave, ac-coupled
LVPECL, ac-coupled
LVDS, ac-coupled
10
125
MSPS
VPP
0.2
1.5
1.6
Input clock amplitude (differential)
0.7
Input clock duty cycle
35%
50%
0.95
65%
Input clock common-mode voltage
V
DIGITAL OUTPUTS
CLOAD
RLOAD
Maximum external load capacitance from each output pin to GND
Differential load resistance placed externally
3.3
pF
100
Ω
TEMPERATURE
TA Operating free-air temperature
–50
105
°C
(1) After power-up, to reset the device for the first time, only use the RESET pin; see the Register Initialization section.
(2) With the clock divider enabled by default for divide-by-1. Maximum sampling clock frequency for the divide-by-4 option is 500 MSPS.
Copyright © 2019, Texas Instruments Incorporated
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ZHCSJF0 –FEBRUARY 2019
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7.4 Thermal Information
ADC3244E
THERMAL METRIC(1)
RGZ (VQFN)
UNIT
48 PINS
25.7
18.9
3.0
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.2
ψJB
3
RθJC(bot)
0.5
(1) For more information about traditional and new thermal metrics, see the Semicinductor and IC Package Thermal Metrics application
report.
7.5 Electrical Characteristics: General
typical values at TA = 25°C, ADC sampling rate = 125 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS
differential input (unless otherwise noted); minimum and maximum values at full temperature range of –50°C to +105°C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
125
106
95
UNIT
MSPS
mA
ADC clock frequency
1.8-V analog supply current
1.8-V digital supply current
Total power dissipation
65
64
mA
233
5
325
17
mW
Global power-down dissipation
Standby power-down dissipation
mW
78
103
mW
RESOLUTION
Resolution
ANALOG INPUT
14
Bits
Differential input full-scale
Input resistance
2.0
6.6
3.7
0.95
10
VPP
kΩ
RIN
Differential at dc
CIN
Input capacitance
Differential at dc
pF
VOC(VCM)
VCM common-mode voltage output
VCM output current capability
Input common-mode current
V
mA
Per analog input pin
1.5
µA/MSPS
50-Ω differential source driving 50-Ω
termination across INP and INM
Analog input bandwidth (3 dB)
540
MHz
DC ACCURACY
EO
Offset error
–25
–2
25
2
mV
°C
Temperature coefficient of offset
error
αEO
±0.024
Gain error as a result of internal
reference inaccuracy alone
EG(REF)
%FS
EG(CHAN)
Gain error of channel alone
–2
%FS
α(EGCHAN)
Temperature coefficient of EG(CHAN)
±0.008
Δ%FS/°C
CHANNEL-TO-CHANNEL ISOLATION
fIN = 10 MHz
fIN = 100 MHz
fIN = 200 MHz
fIN = 230 MHz
fIN = 300 MHz
105
105
105
105
105
Crosstalk(1)
dB
(1) Crosstalk is measured with a –1-dBFS input signal on one channel and no input on the other channel.
6
Copyright © 2019, Texas Instruments Incorporated
ADC3244E
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ZHCSJF0 –FEBRUARY 2019
7.6 Electrical Characteristics: AC Performance
typical values at TA = 25°C, ADC sampling rate = 125 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS
differential input (unless otherwise noted); minimum and maximum values at full temperature range of –50°C to +105°C
fS = 125 MSPS
DITHER ON
DITHER OFF
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
UNIT
DYNAMIC AC CHARACTERISTICS
fIN = 10 MHz
72.9
72.6
72.4
71.7
71
73.3
73
fIN = 70 MHz
fIN = 100 MHz
fIN = 170 MHz
fIN = 230 MHz
fIN = 10 MHz
fIN = 70 MHz
fIN = 100 MHz
fIN = 170 MHz
fIN = 230 MHz
fIN = 10 MHz
fIN = 70 MHz
fIN = 100 MHz
fIN = 170 MHz
fIN = 230 MHz
fIN = 10 MHz
fIN = 70 MHz
fIN = 100 MHz
fIN = 170 MHz
fIN = 230 MHz
fIN = 10 MHz
fIN = 70 MHz
fIN = 100 MHz
fIN = 170 MHz
fIN = 230 MHz
fIN = 10 MHz
fIN = 70 MHz
fIN = 100 MHz
fIN = 170 MHz
fIN = 230 MHz
71
Signal-to-noise ratio
(from 1-MHz offset)
72.8
72.2
71.6
72.9
72.6
72.5
71.9
71.3
–151.1
–150.9
–150.7
–150.1
–149.5
73
SNR
dBFS
72.5
72.2
72.1
71.4
70.7
–150.8
Signal-to-noise ratio
(full Nyquist band)
–150.5 –148.9
–150.3
–149.6
–148.9
72.8
Noise spectral density
NSD(1)
dBFS/Hz
dBFS
Bits
(averaged across Nyquist zone)
69.6
11.3
82
72.6
72.9
72.5
71.9
71.1
11.8
11.8
11.8
11.6
11.5
86
Signal-to-noise and distortion
ratio
SINAD(1)
ENOB(1)
SFDR
72.3
71.5
70.7
11.8
11.8
Effective number of bits
11.7
11.6
11.5
93
94
89
Spurious-free dynamic range
89
85
dBc
85
85
83
82
(1) Reported from a 1-MHz offset.
Copyright © 2019, Texas Instruments Incorporated
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Electrical Characteristics: AC Performance (continued)
typical values at TA = 25°C, ADC sampling rate = 125 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS
differential input (unless otherwise noted); minimum and maximum values at full temperature range of –50°C to +105°C
fS = 125 MSPS
DITHER ON
MIN
DITHER OFF
MIN
PARAMETER
TEST CONDITIONS
fIN = 10 MHz
TYP
95
96
91
85
83
94
94
91
97
87
100
99
99
100
96
91
91
87
84
81
MAX
TYP
96
95
90
85
83
86
89
85
89
85
95
95
95
91
92
85
86
83
82
80
MAX
UNIT
fIN = 70 MHz
fIN = 100 MHz
fIN = 170 MHz
fIN = 230 MHz
fIN = 10 MHz
fIN = 70 MHz
fIN = 100 MHz
fIN = 170 MHz
fIN = 230 MHz
fIN = 10 MHz
fIN = 70 MHz
fIN = 100 MHz
fIN = 170 MHz
fIN = 230 MHz
fIN = 10 MHz
fIN = 70 MHz
fIN = 100 MHz
fIN = 170 MHz
fIN = 230 MHz
82
83
86
76
Second-order harmonic
distortion
HD2
dBc
HD3
Non
Third-order harmonic distortion
Spurious-free dynamic range
dBc
dBc
HD2, HD3 (excluding HD2, HD3)
THD
Total harmonic distortion
dBc
fIN1 = 45 MHz,
fIN2 = 50 MHz
–97
–91
–95
–90
Two-tone, third-order
intermodulation distortion
IMD3
dBFS
fIN1 = 185 MHz,
fIN2 = 190 MHz
8
Copyright © 2019, Texas Instruments Incorporated
ADC3244E
www.ti.com.cn
ZHCSJF0 –FEBRUARY 2019
7.7 Digital Characteristics
dc specifications refer to the condition where the digital outputs are not switching, but are permanently at a valid logic level of
0 or 1, AVDD = DVDD = 1.8 V, and –1-dBFS differential input (unless otherwise noted)
)PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DIGITAL INPUTS (RESET, SCLK, SDATA, SEN, PDN)
All digital inputs support 1.8-V and
3.3-V CMOS logic levels
VIH
VIL
High-level input voltage
Low-level input voltage
1.3
V
V
All digital inputs support 1.8-V and
3.3-V CMOS logic levels
0.4
RESET, SDATA, SCLK, PDN
SEN(1)
VHIGH = 1.8 V
VHIGH = 1.8 V
VLOW = 0 V
10
0
High-level input
current
IIH
µA
µA
RESET, SDATA, SCLK, PDN
SEN
0
Low-level input
current
IIL
VLOW = 0 V
10
DIGITAL INPUTS (SYSREFP, SYSREFM)
VIH
VIL
High-level input voltage
1.3
0.5
0.9
V
V
V
Low-level input voltage
Common-mode voltage for SYSREF
DIGITAL OUTPUTS, CMOS INTERFACE (SDOUT)
VOH
VOL
High-level output voltage
Low-level output voltage
DVDD – 0.1
DVDD
0
V
V
0.1
DIGITAL OUTPUTS, LVDS INTERFACE
VODH
VODL
VOCM
High-level output differential voltage
Low-level output differential voltage
Output common-mode voltage
With an external 100-Ω termination
With an external 100-Ω termination
280
410
–410
1.05
460
mV
mV
V
–460
–280
(1) SEN has an internal 150-kΩ pull-up resistor to AVDD. Because the pull-up resistor is weak, SEN can also be driven by 1.8-V or 3.3-V
CMOS buffers.
7.8 Timing Requirements: General
typical values at TA = 25°C, AVDD = DVDD = 1.8 V, and –1-dBFS differential input (unless otherwise noted); minimum and
maximum values at full temperature range of –50°C to +105°C
MIN
TYP
1.44
±70
±150
130
35
MAX
UNIT
tA
Aperture delay
1.24
1.64
ns
Aperture delay matching between two channels of the same device
Variation of aperture delay between two devices at the same temperature and supply voltage
Aperture jitter
ps
ps
tJ
fS rms
Time to valid data after exiting standby power-down mode
65
Wake-up time
µs
Time to valid data after exiting global power-down mode
(in this mode, both channels power down)
85
140
2-wire mode (default)
9
8
Clock
cycles
ADC latency(1)
1-wire mode
tSU_SYSREF
tH_SYSREF
SYSREF reference setup time Setup time for SYSREF referenced to input clock rising edge
1000
100
ps
SYSREF reference hold time
Hold time for SYSREF referenced to input clock rising edge
(1) Overall latency = ADC latency + tPDI
.
Copyright © 2019, Texas Instruments Incorporated
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ZHCSJF0 –FEBRUARY 2019
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7.9 Timing Requirements: LVDS Output
typical values at 25°C, AVDD = DVDD = 1.8 V, –1-dBFS differential input, 7x serialization, CLOAD = 3.3 pF(1), and RLOAD = 100
Ω
(2) (unless otherwise noted); minimum and maximum values at full temperature range of –50°C to +105°C(3)(4)
MIN
TYP
MAX
UNIT
Data setup time: data valid to zero-crossing of differential output clock
(CLKOUTP – CLKOUTM)(5)
tSU
0.36
0.42
ns
Data hold time: zero-crossing of differential output clock (CLKOUTP – CLKOUTM) to data
becoming invalid(5)
tHO
0.36
0.47
ns
LVDS bit clock duty cycle: duty cycle of differential clock (CLKOUTP – CLKOUTM)
49%
4.5
Clock propagation delay: input clock falling edge cross-over to frame 1-wire mode
clock rising edge cross-over 10 MSPS < sampling frequency <
2.7
6.5
tPDI
ns
2-wire mode
125 MSPS
0.44 × tS + tDELAY
tDELAY
Delay time
3
4.5
5.9
ns
ns
tFALL
tRISE
,
Data fall time, data rise time: rise time measured from –100 mV to 100 mV,
10 MSPS ≤ Sampling frequency ≤ 125 MSPS
0.11
tCLKRISE
tCLKFALL
,
Output clock rise time, output clock fall time: rise time measured from –100 mV to 100 mV,
10 MSPS ≤ Sampling frequency ≤ 125 MSPS
0.11
ns
(1) CLOAD is the effective external single-ended load capacitance between each output pin and ground
(2) RLOAD is the differential load resistance between the LVDS output pair.
(3) Measurements are done with a transmission line of a 100-Ω characteristic impedance between the device and load. Setup and hold time
specifications take into account the effect of jitter on the output data and clock.
(4) Timing parameters are specified by design and characterization and are not tested in production.
(5) Data valid refers to a logic high of +100 mV and a logic low of –100 mV.
Table 1. LVDS Timings at Lower Sampling Frequencies: 7x Serialization (2-Wire Mode)
SETUP TIME
(tSU, ns)
HOLD TIME
(tHO, ns)
SAMPLING FREQUENCY
(MSPS)
MIN
2.27
1.44
1.2
TYP
MAX
MIN
2.41
1.51
1.24
0.97
0.72
0.53
TYP
MAX
25
40
2.6
1.6
2.6
1.7
50
1.32
1.04
0.75
0.57
1.4
60
0.95
0.68
0.5
1.09
0.81
0.62
80
100
Table 2. LVDS Timings at Lower Sampling Frequencies: 14x Serialization (1-Wire Mode)
SETUP TIME
(tSU, ns)
HOLD TIME
(tHO, ns)
SAMPLING FREQUENCY
(MSPS)
MIN
1.1
TYP
MAX
MIN
1.19
0.74
0.54
0.42
0.3
TYP
MAX
25
40
50
60
80
1.24
0.72
0.55
0.41
0.24
1.34
0.82
0.64
0.51
0.38
0.66
0.48
0.35
0.17
10
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ADC3244E
www.ti.com.cn
ZHCSJF0 –FEBRUARY 2019
7.10 Typical Characteristics
typical values at TA = 25°C, ADC sampling rate = 125 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1-dBFS
differential input, 2-VPP full-scale, 32k-point FFT, chopper disabled, and SNR reported with a 1-MHz offset from dc when
chopper is disabled and from fS / 2 when chopper is enabled (unless otherwise noted)
0
-10
0
-10
-20
-20
-30
-30
-40
-40
-50
-50
-60
-60
-70
-70
-80
-80
-90
-90
-100
-110
-120
-100
-110
-120
0
12.5
25
37.5
50
62.5
0
12.5
25
37.5
50
62.5
Frequency (MHz)
Frequency (MHz)
D101
D102
SFDR = 102.6 dBc, SNR = 72.9 dBFS, SINAD = 72.8 dBFS,
THD = 99.8 dBc, HD2 = –108.6 dBc, HD3 = –104.0 dBc
SFDR = 91.8 dBc, SNR = 73.5 dBFS, SINAD = 73.4 dBFS,
THD = 87.3 dBc, HD2 = –93.8 dBc, HD3 = –91.8 dBc
图 1. FFT for 10-MHz Input Signal
图 2. FFT for 10-MHz Input Signal
(Chopper On, Dither On)
(Chopper On, Dither Off)
0
-10
0
-10
-20
-20
-30
-30
-40
-40
-50
-50
-60
-60
-70
-70
-80
-80
-90
-90
-100
-110
-120
-100
-110
-120
0
12.5
25
37.5
50
62.5
0
12.5
25
37.5
50
62.5
Frequency (MHz)
Frequency (MHz)
D103
D104
SFDR = 95.9 dBc, SNR = 72.7 dBFS, SINAD = 72.7 dBFS,
THD = 93.6 dBc, HD2 = –100.6 dBc, HD3 = –95.9 dBc
SFDR = 90.9 dBc, SNR = 73.3 dBFS, SINAD = 73.1 dBFS,
THD = 87 dBc, HD2 = –90.9 dBc, HD3 = –94.9 dBc
图 3. FFT for 70-MHz Input Signal (Dither On)
图 4. FFT for 70-MHz Input Signal (Dither Off)
0
-10
0
-10
-20
-20
-30
-30
-40
-40
-50
-50
-60
-60
-70
-70
-80
-80
-90
-90
-100
-110
-120
-100
-110
-120
0
12.5
25
37.5
50
62.5
0
12.5
25
37.5
50
62.5
Frequency (MHz)
Frequency (MHz)
D105
D106
SFDR = 96.4 dBc, SNR = 72.1 dBFS, SINAD = 72.0 dBFS,
THD = 92.6 dBc, HD2 = –96.4 dBc, HD3 = –98.8 dBc
SFDR = 89.9 dBc, SNR = 72.8 dBFS, SINAD = 72.6 dBFS,
THD = 87.1 dBc, HD2 = –97.2 dBc, HD3 = –89.9 dBc
图 5. FFT for 170-MHz Input Signal (Dither On)
图 6. FFT for 170-MHz Input Signal (Dither Off)
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Typical Characteristics (接下页)
typical values at TA = 25°C, ADC sampling rate = 125 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1-dBFS
differential input, 2-VPP full-scale, 32k-point FFT, chopper disabled, and SNR reported with a 1-MHz offset from dc when
chopper is disabled and from fS / 2 when chopper is enabled (unless otherwise noted)
0
0
-10
-10
-20
-20
-30
-30
-40
-40
-50
-50
-60
-60
-70
-70
-80
-80
-90
-90
-100
-110
-120
-100
-110
-120
0
12.5
25
37.5
50
62.5
0
12.5
25
37.5
50
62.5
Frequency (MHz)
Frequency (MHz)
D107
D108
SFDR = 76.1 dBc, SNR = 70.8 dBFS, SINAD = 69.8 dBFS,
THD = 74.8 dBc, HD2 = –76.1 dBc, HD3 = –80.9 dBc
SFDR = 76.1 dBc, SNR = 71.2 dBFS, SINAD = 70.2 dBFS,
THD = 74.9 dBc, HD2 = –76.1 dBc, HD3 = –81.6 dBc
图 7. FFT for 270-MHz Input Signal (Dither On)
图 8. FFT for 270-MHz Input Signal (Dither Off)
0
-10
0
-10
-20
-20
-30
-30
-40
-40
-50
-50
-60
-60
-70
-70
-80
-80
-90
-90
-100
-110
-120
-100
-110
-120
0
12.5
25
37.5
50
62.5
0
12.5
25
37.5
50
62.5
Frequency (MHz)
Frequency (MHz)
D109
D110
SFDR = 76.2 dBc, SNR = 68.3 dBFS, SINAD = 67.5 dBFS,
THD = 74.3 dBc, HD2 = –76.2 dBc, HD3 = –79.2 dBc
SFDR = 75.3 dBc, SNR = 69.1 dBFS, SINAD = 67.8 dBFS,
THD = 72.7 dBc, HD2 = –76.7 dBc, HD3 = –75.3 dBc
图 9. FFT for 450-MHz Input Signal (Dither On)
图 10. FFT for 450-MHz Input Signal (Dither Off)
0
-10
0
-10
-20
-20
-30
-30
-40
-40
-50
-50
-60
-60
-70
-70
-80
-80
-90
-90
-100
-110
-120
-100
-110
-120
0
12.5
25
37.5
50
62.5
0
12.5
25
37.5
50
62.5
Frequency (MHz)
Frequency (MHz)
D111
D112
fIN1 = 46 MHz, fIN2 = 50 MHz, IMD3 = 88.3 dBFS,
each tone at –7 dBFS
fIN1 = 46 MHz, fIN2 = 50 MHz, IMD3 = 90.8 dBFS,
each tone at –36 dBFS
图 11. FFT for Two-Tone Input Signal
图 12. FFT for Two-Tone Input Signal
12
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ADC3244E
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ZHCSJF0 –FEBRUARY 2019
Typical Characteristics (接下页)
typical values at TA = 25°C, ADC sampling rate = 125 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1-dBFS
differential input, 2-VPP full-scale, 32k-point FFT, chopper disabled, and SNR reported with a 1-MHz offset from dc when
chopper is disabled and from fS / 2 when chopper is enabled (unless otherwise noted)
0
0
-10
-10
-20
-20
-30
-30
-40
-40
-50
-50
-60
-60
-70
-70
-80
-80
-90
-90
-100
-110
-120
-100
-110
-120
0
12.5
25
37.5
50
62.5
0
12.5
25
37.5
50
62.5
Frequency (MHz)
Frequency (MHz)
D113
D114
fIN1 = 185 MHz, fIN2 = 190 MHz, IMD3 = 86.4 dBFS,
each tone at –7 dBFS
fIN1 = 185 MHz, fIN2 = 190 MHz, IMD3 = 87.28 dBFS,
each tone at –36 dBFS
图 13. FFT for Two-Tone Input Signal
图 14. FFT for Two-Tone Input Signal
-85
-80
-85
-90
-90
-95
-95
-100
-105
-110
-100
-105
-110
-35
-31
-27
-23
-19
-15
-11
-7
-35
-31
-27
-23
-19
-15
-11
-7
Each Tone Amplitude (dBFS)
Each Tone Amplitude (dBFS)
D115
D116
fIN1 = 46 MHz, fIN2 = 50 MHz
fIN1 = 185 MHz, fIN2 = 190 MHz
图 15. Intermodulation Distortion vs Input Amplitude
图 16. Intermodulation Distortion vs Input Amplitude
74
100
Dither_EN
Dither_EN
Dither_DIS
Dither_DIS
73
95
72
71
70
69
68
90
85
80
75
70
0
50
100
150
200
250
300
350
400
0
50
100
150
200
250
300
350
400
Frequency (MHz)
Frequency (MHz)
D117
D118
图 17. Signal-to-Noise Ratio vs Input Frequency
图 18. Spurious-Free Dynamic Range vs
Input Frequency
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Typical Characteristics (接下页)
typical values at TA = 25°C, ADC sampling rate = 125 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1-dBFS
differential input, 2-VPP full-scale, 32k-point FFT, chopper disabled, and SNR reported with a 1-MHz offset from dc when
chopper is disabled and from fS / 2 when chopper is enabled (unless otherwise noted)
74.5
180
160
140
120
100
80
74
73.5
73
180
160
140
120
100
80
SNR (dBFS)
SFDR (dBc)
SFDR (dBFS)
SNR (dBFS)
SFDR (dBc)
SFDR (dBFS)
74
73.5
73
72.5
72
72.5
72
71.5
71
71.5
71
60
60
40
70.5
70
40
70.5
20
20
-70
-60
-50
-40
-30
-20
-10
0
-70
-60
-50
-40
-30
-20
-10
0
Amplitude (dBFS)
Amplitude (dBFS)
D119
D120
fIN = 30 MHz
fIN = 170 MHz
图 19. Performance vs Input Amplitude
图 20. Performance vs Input Amplitude
78
76
74
72
70
68
96
94
92
90
88
86
78
76
74
72
70
68
92
90
88
86
84
82
SNR
SFDR
SNR
SFDR
0.85
0.9
0.95
1
1.05
1.1
0.85
0.9
0.95
1
1.05
1.1
Input Common-Mode Voltage (V)
Input Common-Mode Voltage (V)
D121
fIN = 170 MHz
fIN = 30 MHz
图 22. Performance vs Input Common-Mode Voltage
图 21. Performance vs Input Common-Mode Voltage
92
90
88
86
84
82
73
AVDD = 1.7 V
AVDD = 1.75 V
AVDD = 1.8 V
AVDD = 1.85 V
AVDD = 1.9 V
AVDD = 1.7 V
AVDD = 1.75 V
AVDD = 1.8 V
AVDD = 1.85 V
AVDD = 1.9 V
72.5
72
71.5
71
70.5
70
-40
-15
10
35
60
85
-40
-15
10
35
60
85
Temperature (°C)
Temperature (°C)
D123
D124
fIN = 170 MHz
fIN = 170 MHz
图 23. Spurious-Free Dynamic Range vs
图 24. Signal-to-Noise Ratio vs
AVDD Supply and Temperature
AVDD Supply and Temperature
14
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ADC3244E
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ZHCSJF0 –FEBRUARY 2019
Typical Characteristics (接下页)
typical values at TA = 25°C, ADC sampling rate = 125 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1-dBFS
differential input, 2-VPP full-scale, 32k-point FFT, chopper disabled, and SNR reported with a 1-MHz offset from dc when
chopper is disabled and from fS / 2 when chopper is enabled (unless otherwise noted)
92
90
88
86
84
82
73
72.6
72.2
71.8
71.4
71
DVDD = 1.7 V
DVDD = 1.75 V
DVDD = 1.8 V
DVDD = 1.85 V
DVDD = 1.9 V
DVDD = 1.7 V
DVDD = 1.75 V
DVDD = 1.8 V
DVDD = 1.85 V
DVDD = 1.9 V
-40
-15
10
35
60
85
-40
-15
10
35
60
85
Temperature (°C)
Temperature (°C)
D125
D126
fIN = 170 MHz
fIN = 170 MHz
图 25. Spurious-Free Dynamic Range vs
图 26. Signal-to-Noise Ratio vs
DVDD Supply and Temperature
DVDD Supply and Temperature
74.5
94
93
92
91
90
89
88
77
95
SNR
SFDR
SNR
SFDR
74
73.5
73
75
73
71
69
67
65
90
85
80
75
70
72.5
72
71.5
65
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6 1.8
2
2.2
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6 1.8
2
2.2
Differential Clock Amplitude (Vpp)
Differential Clock Amplitude (Vpp)
D127
D128
fIN = 40 MHz
fIN = 150 MHz
图 27. Performance vs Clock Amplitude
图 28. Performance vs Clock Amplitude
74.2
73.8
73.4
73
95
94
93
92
91
90
72.4
72.2
72
90
SNR
SFDR
SNR
SFDR
87.5
85
71.8
71.6
71.4
82.5
80
72.6
72.2
77.5
30
35
40
45
50
55
60
65
70
30
35
40
45
50
55
60
65
70
Input Clock Duty Cycle (%)
Input Clock Duty Cycle (%)
D129
D130
fIN = 30 MHz
fIN = 150 MHz
图 29. Performance vs Clock Duty Cycle
图 30. Performance vs Clock Duty Cycle
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Typical Characteristics (接下页)
typical values at TA = 25°C, ADC sampling rate = 125 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1-dBFS
differential input, 2-VPP full-scale, 32k-point FFT, chopper disabled, and SNR reported with a 1-MHz offset from dc when
chopper is disabled and from fS / 2 when chopper is enabled (unless otherwise noted)
0
20
-5
-10
16
-15
-20
12
-25
-30
-35
-40
-45
-50
8
4
0
0
50
100
150
200
250
300
Frequency of Signal on Supply (MHz)
D001
D131
fIN = 30 MHz, AIN = –1 dBFS,
test signal amplitude = 50 mVPP
Output Code (LSB)
RMS Noise = 1.4 LSBs
图 32. Power-Supply Rejection Ratio vs
图 31. Idle Channel Histogram
Test Signal Frequency
0
0
-10
-20
-5
-10
-15
-20
-25
-30
-35
-40
-45
-50
-55
-60
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
0
12.5
25
37.5
50
62.5
0
50
100
150
200
250
300
Frequency (MHz)
Frequency of Input Common-Mode Signal (MHz)
D003
D0021
fIN = 30 MHz, AIN = –1 dBFS,
test signal amplitude = 50 mVPP
fIN = 30.1 MHz, fPSRR = 3 MHz, APSRR = 50 mVPP
SNR = 58.51 dBFS, SINAD = 58.51 dBFS, SFDR = 60.53 dBc,
THD = –90.71 dBc, SFDR = 60.53 dBc (non 23)
,
图 33. Power-Supply Rejection Ratio Spectrum
图 34. Common-Mode Rejection Ratio vs
Test Signal Frequency
240
200
160
120
80
0
-10
Analog Power
Digital Power
Total Power
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
40
5
15 25 35 45 55 65 75 85 95 105 115 125
Sampling Speed (MSPS)
0
12.5
25
37.5
50
62.5
Frequency (MHz)
D004
fIN = 170.1 MHz, fCMRR = 5 MHz, ACMRR = 50 mVPP
,
SNR = 69.72 dBFS, SINAD = 69.66 dBFS, SFDR = 75.66 dBc,
THD = –86.98 dBc, SFDR = 75.66 dBc (non 23)
图 36. Power vs Sampling Frequency (1-Wire Mode)
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图 35. Common-Mode Rejection Ratio Spectrum
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ZHCSJF0 –FEBRUARY 2019
7.11 Typical Characteristics: Contour
typical values at TA = 25°C, ADC sampling rate = 125 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1-dBFS
differential input, 2-VPP full-scale, 32k-point FFT, chopper disabled, and SNR reported with a 1-MHz offset from dc when
chopper is disabled and from fS / 2 when is chopper enabled (unless otherwise noted)
80
85
120
110
100
90
90
80
90
75
90
85
80
75
80
70
70
60
90
50
85
40
70
75
90
80
30
50
100
150
200
250
300
350
400
450
90
Input Frequency, MHz
70
75
80
85
图 37. Spurious-Free Dynamic Range (SFDR)
120
110
100
90
72.5
73
72
71.5
71
70.5
69.5
69
70
80
72.5
73
71.5
70
72
71
70.5
69.5
69
70
60
50
40
68.5
72.5
70.5
71.5
70
71
73
72
69.5
69
30
68
67.5
50
100
150
200
250
300
350
400
450
73
Input Frequency, MHz
70
67
68
69
71
72
图 38. Signal-to-Noise Ratio (SNR)
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8 Parameter Measurement Information
8.1 Timing Diagrams
DAn_P
DBn_P
Logic 0
ODL = -410 mV(1)
Logic 1
VODH = +410 mV(1)
V
DAn_M
DBn_M
VOCM
GND
(1) With an external 100-Ω termination.
图 39. Serial LVDS Output Voltage Levels
CLKIN
FCLK
DCLK
1-Wire (14x Serialization)
Dx0P
Dx0M
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
8
D
9
D
D
D
D
D
0
D
13
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
8
D
9
D
D
D
D
D
0
10 11 12 13
10 11 12 13
CLKIN
FCLK
DCLK
Dx0P
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
0
2-Wire (7x Serialization)
Dx0M
Dx1P
Dx1M
D
7
D
8
D
9
D
10
D
11
D
12
D
13
D
7
D
8
D
9
D
10
D
11
D
12
D
13
D
7
SAMPLE N-1
SAMPLE N
SAMPLE N+1
图 40. Output Timing Diagram
18
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ZHCSJF0 –FEBRUARY 2019
Timing Diagrams (接下页)
DCLK
t HO
Dx0P
Dx0M
t SU
图 41. Setup and Hold Time
N+10
N+1
N+9
Sample N
TA
Input Signal
on INxP, INxM pins
Data Latency(1) = 9 Input Clock Cycles
Sample N
CLKINP,
CLKINM
tPDI
FCLKP,
FCLKM
DCLKP,
DCLKM
DCLK edges are centered within the data valid
window.
DA0P, DA0M,
DB0P, DB0M
5
6
0
7
1
8
2
9
3
4
5
6
0
7
1
8
2
9
3
4
12 13
10 11 12 13
Sample N
10 11
DA1P, DA1M,
DB1P, DB1M
Sample N+1
th
tsu
(1) Overall latency = data latency + tPDI
.
图 42. Latency Diagram
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9 Detailed Description
9.1 Overview
The ADC3244E is a high-performance, 14-bit, 125-MSPS, dual channel analog-to-digital converter (ADC) with
ultra-low power consumption. The ADC3244E supports the extended ambient temperature range of –50°C to
+105°C, making this device a great choice for extreme temperature conditions while delivering excellent noise
and linearity performance.
The LVDS output interface reduces number of connections between the ADC and receiving device, such as an
FPGA, which results in power saving and higher system integration. The device supports an input dynamic range
of 2 VPP, and is equipped with digital features such as chopper function and dither algorithm. The chopper
function helps in shifting the ADC 1/f noise spectrum to the Nyquist frequency, while preserving the signal
spectrum, thus making this device useful for dc-coupling applications. The internal dither algorithms help clean
higher-order harmonic spurs from the ADC output spectrum. See the Chopper Functionality and Internal Dither
Algorithm sections for more details on chopper and dither functions, respectively.
9.2 Functional Block Diagram
DA0P
INAP
Digital Encoder
and Serializer
14-Bit
ADC
DA0M
DA1P
INAM
DA1M
CLKP
CLKM
DCLKP
Divide by
1,2,4
Bit Clock
DCLKM
FCLKP
PLL
Frame Clock
SYSREFP
SYSREFM
FCLKM
DB0P
INBP
INBM
14-Bit
ADC
Digital Encoder
and Serializer
DB0M
DB1P
DB1M
Common
Mode
VCM
Configuration Registers
20
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9.3 Feature Description
9.3.1 Analog Inputs
The ADC3244E analog signal inputs are designed to be driven differentially. Each input pin (INP, INM) must
swing symmetrically between (VCM + 0.5 V) and (VCM – 0.5 V), resulting in a 2-VPP (default) differential input
swing. The input sampling circuit has a 3-dB bandwidth that extends up to 540 MHz (50-Ω source driving 50-Ω
termination between INP and INM).
9.3.2 Clock Input
The device clock inputs can be driven differentially (sine, LVPECL, or LVDS) or single-ended (LVCMOS), with
little or no difference in performance between them. The common-mode voltage of the clock inputs is set to
0.95 V using internal 5-kΩ resistors. The self-bias clock inputs of the ADC3244E are driven by the transformer-
coupled, sine-wave clock source or by the ac-coupled, LVPECL and LVDS clock sources, as shown in 图 43, 图
44, and 图 45. See 图 46 for details regarding the internal clock buffer.
0.1 …F
0.1 …F
ZO
CLKP
CLKP
Differential
Sine-Wave
Clock Input
Typical LVDS
Clock Input
RT
TI Device
100 Ω
0.1 …F
TI Device
0.1 …F
ZO
CLKM
CLKM
NOTE: RT = termination resistor, if necessary.
图 43. Differential Sine-Wave Clock Driving Circuit
图 44. LVDS Clock Driving Circuit
0 …F
ZO
CLKP
150 Ω
Typical LVPECL
Clock Input
100 Ω
TI Device
CLKM
0 …F
ZO
150 Ω
图 45. LVPECL Clock Driving Circuit
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Clock Buffer
LPKG
2 nH
20 W
CLKP
CBOND
1 pF
CEQ
CEQ
5 kW
RESR
100 W
1.4 V
LPKG
2 nH
5 kW
20 W
CLKM
CBOND
1 pF
RESR
100 W
NOTE: CEQ is 1 pF to 3 pF and is the equivalent input capacitance of the clock buffer.
图 46. Internal Clock Buffer
A single-ended CMOS clock can be ac-coupled to the CLKP input, with CLKM connected to ground with a 0.1-μF
capacitor, as shown in 图 47. However, for best performance the clock inputs must be driven differentially,
thereby reducing susceptibility to common-mode noise. For high input frequency sampling, TI recommends using
a clock source with very low jitter. Band-pass filtering of the clock source can help reduce the effects of jitter.
There is no change in performance with a non-50% duty cycle clock input.
0.1 …F
CMOS
Clock Input
CLKP
TI Device
0.1 …F
CLKM
图 47. Single-Ended Clock Driving Circuit
9.3.2.1 SNR and Clock Jitter
The signal-to-noise ratio of the ADC is limited by three different factors, as shown in 公式 1. Quantization noise
(typically 86 dB for a 14-bit ADC) and thermal noise limit SNR at low input frequencies while the clock jitter sets
SNR for higher input frequencies.
2
2
2
SNRQuantization_Noise
SNRThermal_Noise
SNRJitter
20
≈
’
÷
÷
◊
≈
’
÷
÷
◊
≈
’
÷
-
-
-
∆
∆
20
20
∆
SNRADC[dBc] = -20 ∂log 10
+ 10
+ 10
∆
«
∆
«
∆
«
÷
◊
(1)
(2)
The SNR limitation resulting from sample clock jitter can be calculated with 公式 2.
SNRJitter [dBc] = -20 ∂log 2p∂ f ∂ t
in Jitter
The total clock jitter (tJitter) has two components: the internal aperture jitter (130 fs for the device) that is set by
the noise of the clock input buffer and the external clock. tJitter can be calculated with 公式 3.
2
2
tJitter
=
t
+ t
Aperture _ ADC
Jitter,Ext.Clock _Input
(3)
22
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External clock jitter can be minimized by using high-quality clock sources and jitter cleaners as well as bandpass
filters at the clock input while a faster clock slew rate improves the ADC aperture jitter. The ADC3244E has a
typical thermal noise of 73.5 dBFS and internal aperture jitter of 130 fs. 图 48 shows SNR (from 1 MHz offset
leaving the 1/f flicker noise) for different jitter of clock driver.
73.0
Ext Clock Jitter
72.5
35 fs
72.0
71.5
71.0
70.5
70.0
69.5
69.0
68.5
68.0
67.5
67.0
50 fs
100 fs
150 fs
200 fs
10
100
1000
Input Frequency (MHz)
D03061
图 48. SNR vs Frequency for Different Clock Jitter
9.3.3 Digital Output Interface
The devices offer two different output format options, thus making interfacing to a field-programmable gate array
(FPGA) or an application-specific integrated circuit (ASIC) easy. Each option can be easily programmed using
the serial interface, as shown in 表 3. The output interface options are:
•
•
One-wire, 1x frame clock, 14x serialization with the DDR bit clock and
Two-wire, 0.5x frame clock, 7x serialization with the DDR bit clock.
表 3. Interface Rates
RECOMMENDED SAMPLING
FREQUENCY (MSPS)
BIT CLOCK
FREQUENCY
(MHz)
FRAME CLOCK
FREQUENCY
(MHz)
INTERFACE
OPTIONS
SERIAL DATA
RATE (Mbps)
SERIALIZATION
MINIMUM
15(1)
—
MAXIMUM
—
80
105
560
15
80
210
1120
140
1-wire
14x
7x
20(1)
—
70
10
2-wire (default
after reset)
—
125
437.5
62.5
875
(1) Use the LOW SPEED ENABLE register bits for low speed operation; see 表 22.
9.3.3.1 One-Wire Interface: 14x Serialization
In this interface option, the device outputs the data of each ADC serially on a single LVDS pair (one-wire). The
data are available at the rising and falling edges of the bit clock (DDR bit clock). The ADC outputs a new word at
the rising edge of every frame clock, starting with the MSB. The data rate is 14x sample frequency (14x
serialization).
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9.3.3.2 Two-Wire Interface: 7x Serialization
The two-wire interface is recommended for sampling frequencies above 65 MSPS. The output data rate is 7x
sample frequency because seven data bits are output every clock cycle on each differential pair. Each ADC
sample is sent over the two wires with the seven MSBs on Dx1P, Dx1M and the seven LSBs on Dx0P, Dx0M, as
shown in 图 49. Note that in two-wire mode, the frame clock (FCLK) frequency is half of sampling clock (CLKIN)
frequency.
CLKIN
FCLK
DCLK
1-Wire (14x Serialization)
Dx0P
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
8
D
9
D
D
D
D
D
0
D
13
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
8
D
9
D
D
D
D
D
0
10 11 12 13
10 11 12 13
Dx0M
CLKIN
FCLK
DCLK
Dx0P
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
0
2-Wire (7x Serialization)
Dx0M
Dx1P
Dx1M
D
7
D
8
D
9
D
10
D
11
D
12
D
13
D
7
D
8
D
9
D
10
D
11
D
12
D
13
D
7
SAMPLE N-1
SAMPLE N
SAMPLE N+1
图 49. Output Timing Diagram
24
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9.4 Device Functional Modes
9.4.1 Input Clock Divider
The devices are equipped with an internal divider on the clock input. The clock divider allows operation with a
faster input clock, thus simplifying the system clock distribution design. The clock divider can be bypassed for
operation with a 125-MHz clock while the divide-by-2 option supports a maximum input clock of 250 MHz and the
divide-by-4 option provides a maximum input clock frequency of 500 MHz.
9.4.2 Chopper Functionality
The devices are equipped with an internal chopper front-end. Enabling the chopper function swaps the ADC
noise spectrum by shifting the 1/f noise from dc to fS / 2. 图 50 shows the noise spectrum with the chopper off
and 图 51 shows the noise spectrum with the chopper on. This function is especially useful in applications
requiring good ac performance at low input frequencies or in dc-coupled applications. The chopper can be
enabled via SPI register writes and is recommended for input frequencies below 30 MHz. The chopper function
creates a spur at fS / 2 that must be filtered out digitally.
0
-10
0
-10
-20
-20
-30
-30
-40
-40
-50
-50
-60
-60
-70
-70
-80
-80
-90
-90
-100
-110
-120
-100
-110
-120
0
12.5
25
37.5
50
62.5
0
12.5
25
37.5
50
62.5
Frequency (MHz)
Frequency (MHz)
D052
D051
fIN = 10 MHz, fS = 125 MHz
图 50. ADC Output Spectrum With Chopper Off
fIN = 10 MHz, fS = 125 MHz
图 51. ADC Output Spectrum With Chopper On
9.4.3 Power-Down Control
The power-down functions of the ADC3244E can be controlled either through the parallel control pin (PDN) or
through an SPI register setting (see register 15h). The PDN pin can also be configured using the SPI to a global
power-down or standby functionality, as shown in 表 4.
表 4. Power-Down Modes
FUNCTION
Global power-down
Standby
POWER CONSUMPTION (mW)
WAKE-UP TIME (µs)
5
85
35
81
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9.4.3.1 Improving Wake-Up Time From Global Power-Down
The device has an internal low-pass filter in the sampling clock path. This low-pass filter helps improve the
aperture jitter of the device. However, in applications where input frequencies are < 200 MHz, noise from the
aperture jitter does not dominate the overall SNR of the device. In such applications, the wake-up time from a
global power-down can be reduced by bypassing the low-pass filter using the DIS CLK FILT register bit (write
80h to register address 70Ah). As shown in 表 5, setting the DIS CLK FILT bit improves the wake-up time from a
global power-down from 85 µs to 55 µs.
表 5. Wake-Up Time From Global Power-Down
WAKE-UP TIME
DIS CLK FILT
REGISTER BIT
GLOBAL PDN
REGISTER BIT
TYP
85
MAX
140
81
UNIT
µs
0
1
0→1→0
0→1→0
55
µs
9.4.4 Internal Dither Algorithm
The ADC3244E uses an internal dither algorithm to achieve high SFDR and a clean spectrum. However, the
dither algorithm marginally degrades SNR, creating a trade-off between SNR and SFDR. If desired, the dither
algorithm can be turned off by using the DIS DITH CHx registers bits. 图 52 and 图 53 show the effect of using
dither algorithms.
0
-10
0
-10
-20
-20
-30
-30
-40
-40
-50
-50
-60
-60
-70
-70
-80
-80
-90
-90
-100
-110
-120
-100
-110
-120
0
12.5
25
37.5
50
62.5
0
12.5
25
37.5
50
62.5
Frequency (MHz)
Frequency (MHz)
D103
D104
SFDR = 95.9 dBc, SNR = 72.7 dBFS, SINAD = 72.7 dBFS,
THD = 93.6 dBc, HD2 = –100.6 dBc, HD3 = –95.9 dBc
SFDR = 90.9 dBc, SNR = 73.3 dBFS, SINAD = 73.1 dBFS,
THD = 87 dBc, HD2 = –90.9 dBc, HD3 = –94.9 dBc
图 52. FFT with Dither On
图 53. FFT with Dither Off
9.5 Programming
The ADC3244E can be configured using a serial programming interface, as described in this section.
9.5.1 Serial Interface
The device has a set of internal registers that can be accessed by the serial interface formed by the SEN (serial
interface enable), SCLK (serial interface clock), SDATA (serial interface data), and SDOUT (serial interface data
output) pins. Serially shifting bits into the device is enabled when SEN is low. Serial data SDATA are latched at
every SCLK rising edge when SEN is active (low). The serial data are loaded into the register at every 24th
SCLK rising edge when SEN is low. When the word length exceeds a multiple of 24 bits, the excess bits are
ignored. Data can be loaded in multiples of 24-bit words within a single active SEN pulse. The interface can
function with SCLK frequencies from 20 MHz down to very low speeds (of a few hertz) and also with a non-50%
SCLK duty cycle.
26
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Programming (接下页)
9.5.1.1 Register Initialization
After power-up, the internal registers must be initialized to their default values through a hardware reset by
applying a high pulse on the RESET pin (of durations greater than 10 ns), as shown in 图 54. If required, the
serial interface registers can be cleared during operation either:
1. Through a hardware reset, or
2. By applying a software reset. When using the serial interface, set the RESET bit (D0 in register address 06h)
high. This setting initializes the internal registers to the default values and then self-resets the RESET bit low.
In this case, the RESET pin is kept low.
9.5.1.1.1 Serial Register Write
The device internal register can be programmed with these steps:
1. Drive the SEN pin low,
2. Set the R/W bit to 0 (bit A15 of the 16-bit address),
3. Set bit A14 in the address field to 1,
4. Initiate a serial interface cycle by specifying the address of the register (A13 to A0) whose content must be
written, and
5. Write the 8-bit data that are latched in on the SCLK rising edge.
图 54 and 表 6 show the timing requirements for the serial register write operation.
Register Address [13:0]
A13 A12 A11 A1
Register Data [7:0]
SDATA
R/W
= 0
1
A0
D7
D6
D5
D4
D3
D2
D1
tDH
D0
tSCLK
tDSU
SCLK
SEN
tSLOADS
tSLOADH
RESET
图 54. Serial Register Write Timing Diagram
表 6. Serial Interface Timing(1)
MIN
TYP
MAX
UNIT
MHz
ns
fSCLK
tSLOADS
tSLOADH
tDSU
SCLK frequency (equal to 1 / tSCLK
SEN to SCLK setup time
SCLK to SEN hold time
SDIO setup time
)
> dc
25
20
25
ns
25
ns
tDH
SDIO hold time
25
ns
(1) Full temperature range is from –50°C to +105°C, and AVDD = DVDD = 1.8 V.
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9.5.1.1.2 Serial Register Readout
The device includes a mode where the contents of the internal registers can be read back using the SDOUT pin.
This readback mode can be useful as a diagnostic check to verify the serial interface communication between
the external controller and the ADC. Given below is the procedure to read contents of serial registers:
1. Drive the SEN pin low.
2. Set the R/W bit (A15) to 1. This setting disables any further writes to the registers.
3. Set bit A14 in the address field to 1.
4. Initiate a serial interface cycle specifying the address of the register (A13 to A0) whose content must be read.
5. The device outputs the contents (D7 to D0) of the selected register on the SDOUT pin.
6. The external controller can latch the contents at the SCLK rising edge.
7. To enable register writes, reset the R/W register bit to 0.
When READOUT is disabled, the SDOUT pin is in a high-impedance mode. If serial readout is not used, the
SDOUT pin must float. 图 55 shows a timing diagram of the serial register read operation. Data appear on the
SDOUT pin at the SCLK falling edge with an approximate delay (tSD_DELAY) of 20 ns, as shown in 图 56.
Register Address [13:0]
A13 A12 A11 A1
Register Data: Don‘t Care
D5 D4 D3 D2
SDATA
R/W
= 1
A0
D7
D7
D6
D6
D1
D1
D0
D0
1
Register Read Data [7:0]
SDOUT
SCLK
D5
D4
D3
D2
SEN
图 55. Serial Register Read Timing Diagram
SCLK
tSD_DELAY
SDOUT
图 56. SDOUT Timing Diagram
28
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9.5.2 Register Initialization
After power-up, the internal registers must be initialized to their default values through a hardware reset by
applying a high pulse on the RESET pin, as shown in 图 57 and 表 7.
Power
Supplies
t1
RESET
t2
t3
SEN
图 57. Initialization of Serial Registers after Power-Up
表 7. Power-Up Timing
MIN
TYP
MAX
UNIT
ms
ns
t1
t2
t3
Power-on delay: delay from power up to active high RESET pulse
1
10
Reset pulse duration: active high RESET pulse duration
1000
Register write delay: delay from RESET disable to SEN active
100
ns
If required, the serial interface registers can be cleared during operation either:
1. Through hardware reset, or
2. By applying a software reset. When using the serial interface, set the RESET bit (D0 in register address 06h)
high. This setting initializes the internal registers to the default values and then self-resets the RESET bit low.
In this case, the RESET pin is kept low.
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9.6 Register Maps
表 8. Register Map Summary
REGISTER
ADDRESS
REGISTER DATA
A[13:0] (Hex)
D7
0
D6
0
D5
D4
D3
D2
D1
0
D0
0
01
03
04
05
DIS DITH CHA
DIS DITH CHB
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
ODD EVEN
FLIP WIRE
1W-2W
0
0
0
0
0
0
TEST PATTERN
EN
06
07
09
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0
OVR ON LSB
DATA FORMAT
ALIGN TEST
PATTERN
0A
0B
0
0
0
CHA TEST PATTERN
CHB TEST PATTERN
0
0
0
0
0
0
0
0E
CUSTOM PATTERN[13:6]
CUSTOM PATTERN[5:0]
0F
13
0
0
0
0
0
0
0
0
LOW SPEED ENABLE
15
CHA PDN
CHB PDN
STANDBY
GLOBAL PDN
CONFIG PDN PIN
25
LVDS SWING
27
CLK DIV
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
41D
422
434
439
51D
522
534
539
608
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
HIGH IF MODE0
0
0
0
DIS CHOP CHA
0
DIS DITH CHA
DIS DITH CHA
0
0
0
SP1 CHA
0
0
0
0
HIGH IF MODE1
0
0
0
DIS CHOP CHB
0
DIS DITH CHB
DIS DITH CHB
0
0
0
0
0
0
0
0
SP1 CHB
0
HIGH IF MODE[3:2]
DIS CLK FILT
0
0
0
70A
0
PDN SYSREF
30
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9.6.1 Summary of Special Mode Registers
表 9 lists the location, value, and functions of special mode registers in the device.
表 9. Special Modes Summary
MODE
REGISTER SETTINGS
DESCRIPTION
Special modes
Registers 439h (bit 3) and 539h (bit 3)
Always set these bits high for best performance
Registers 1h (bits 5-2), 434h (bits 5 and 3), and
534h (bits 5 and 3)
Disable dither
Disable chopper
High IF modes
Disable dither to improve SNR
Registers 422h (bit 1) and 522h (bit 1)
Disable chopper to shift 1/f noise floor at dc
Improves HD3 for IF > 100 MHz
Registers 41Dh (bit 1), 51Dh (bit 1), and
608h (bits 7-6)
9.6.2 Serial Register Description
9.6.2.1 Register 01h
图 58. Register 01h
7
0
6
0
5
4
3
2
1
0
0
0
DIS DITH CHA
R/W-0h
DIS DITH CHB
R/W-0h
W-0h
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; R = Read only; W = Write only; -n = value after reset
表 10. Register 01h Description
Bit
Field
Type
Reset
Description
7-6
0
W
0h
Must write 0
These bits enable or disable the on-chip dither. Control this bit
with bits 5 and 3 of register 434h.
5-4
DIS DITH CHA
R/W
0h
00 = Default
11 = Dither is disabled for channel A. In this mode, SNR typically
improves by 0.5 dB at 70 MHz.
These bits enable or disable the on-chip dither. Control this bit
with bits 5 and 3 of register 434h.
3-2
1-0
DIS DITH CHB
0
R/W
W
0h
0h
00 = Default
11 = Dither is disabled for channel B. In this mode, SNR typically
improves by 0.5 dB at 70 MHz.
Must write 0
9.6.2.2 Register 03h
图 59. Register 03h
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
ODD EVEN
R/W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; R = Read only; W = Write only; -n = value after reset
表 11. Register 03h Description
Bit
Field
Type
Reset
Description
7-1
0
W
0h
Must write 0
This bit selects the bit sequence on the output lanes
(in 2-wire mode only).
0 = Bits 0, 1, and 2 appear on lane 0; bits 7, 8, and 9 appear on lane 1
1 = Bits 0, 2, and 4 appear on lane 0; bits 1, 3, and 5 appear on lane 1
0
ODD EVEN
R/W
0h
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9.6.2.3 Register 04h
图 60. Register 04h
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
FLIP WIRE
R/W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; R = Read only; W = Write only; -n = value after reset
表 12. Register 04h Description
Bit
Field
Type
Reset
Description
7-1
0
W
0h
Must write 0
This bit flips the data on the output wires. Valid only in two wire
configuration.
0
FLIP WIRE
R/W
0h
0 = Default
1 = Data on output wires is flipped. Pin D0x becomes D1x, and
vice versa.
9.6.2.4 Register 05h
图 61. Register 05h
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
1W-2W
R/W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; R = Read only; W = Write only; -n = value after reset
表 13. Register 05h Description
Bit
Field
Type
Reset
Description
7-1
0
W
0h
Must write 0
This bit transmits output data on either one or two wires.
0 = Output data are transmitted on two wires (Dx0P, Dx0M and
Dx1P, Dx1M)
0
1W-2W
R/W
0h
1 = Output data are transmitted on one wire (Dx0P, Dx0M). In this
mode, the recommended fS is less than 62.5 MSPS.
9.6.2.5 Register 06h
图 62. Register 06h
7
0
6
0
5
0
4
0
3
2
0
1
0
0
TEST PATTERN EN
R/W-0h
RESET
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; R = Read only; W = Write only; -n = value after reset
表 14. Register 06h Description
Bit
Field
Type
Reset
Description
7-2
0
W
0h
Must write 0
This bit enables test pattern selection for the digital outputs.
0 = Normal output
1 = Test pattern output enabled
1
0
TEST PATTERN EN
RESET
R/W
W
0h
0h
This bit applies a software reset.
This bit resets all internal registers to the default values and self-
clears to 0.
32
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9.6.2.6 Register 07h
图 63. Register 07h
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
OVR ON LSB
R/W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; R = Read only; W = Write only; -n = value after reset
表 15. Register 07h Description
Bit
Field
Type
Reset
Description
7-1
0
W
0h
Must write 0
This bit provides the overrange (OVR) information on the LSB bits.
0 = Output data bit 0 functions as the LSB of the 14-bit data
1 = Output data bit 0 carries the OVR information.
0
OVR ON LSB
R/W
0h
9.6.2.7 Register 09h
图 64. Register 09h
7
0
6
0
5
0
4
0
3
0
2
0
1
0
ALIGN TEST
PATTERN
DATA FORMAT
R/W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W = Write only; -n = value after reset
表 16. Register 09h Description
Bit
Field
Type
Reset
Description
7-2
0
W
0h
Must write 0
This bit aligns the test patterns across the outputs of both channels.
0 = Test patterns of both channels are free running
1 = Test patterns of both channels are aligned
1
0
ALIGN TEST PATTERN
DATA FORMAT
R/W
R/W
0h
0h
This bit programs the digital output data format.
0 = Twos complement
1 = Offset binary
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9.6.2.8 Register 0Ah
图 65. Register 0Ah
7
0
6
0
5
0
4
0
3
2
1
0
CHA TEST PATTERN
R/W-0h
W-0h
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; R = Read only; W = Write only; -n = value after reset
表 17. Register 0Ah Description
Bit
Field
Type
Reset
Description
7-4
0
W
0h
Must write 0
These bits control the test pattern for channel A after the TEST
PATTERN EN bit is set.
0000 = Normal operation
0001 = All 0's
0010 = All 1's
0011 = Toggle pattern: data alternate between 10101010101010 and
01010101010101
0100 = Digital ramp: data increment by 1 LSB every clock cycle from
code 0 to 16383
3-0
CHA TEST PATTERN
R/W
0h
0101 = Custom pattern: output data are the same as programmed by
the CUSTOM PATTERN register bits
0110 = Deskew pattern: data are 2AAAh
1000 = PRBS pattern: data are a sequence of pseudo random
numbers
1001 = 8-point sine-wave: data are a repetitive sequence of the
following eight numbers that form a sine-wave: 0, 2399, 8192, 13984,
16383, 13984, 8192, 2399.
Others = Do not use
9.6.2.9 Register 0Bh
图 66. Register 0Bh
7
6
5
4
3
0
2
0
1
0
0
0
CHB TEST PATTERN
R/W-0h
W-0h
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; R = Read only; W = Write only; -n = value after reset
表 18. Register 0Bh Description
Bit
7-4
3-0
Field
Type
R/W
W
Reset
Description
These bits control the test pattern for channel B after the TEST
PATTERN EN bit is set.
0000 = Normal operation
0001 = All 0's
0010 = All 1's
0011 = Toggle pattern: data alternate between 10101010101010 and
01010101010101
0100 = Digital ramp: data increment by 1 LSB every clock cycle from
code 0 to 16383
0101 = Custom pattern: output data are the same as programmed by
the CUSTOM PATTERN register bits
0110 = Deskew pattern: data are 2AAAh
1000 = PRBS pattern: data are a sequence of pseudo random
numbers
1001 = 8-point sine-wave: data are a repetitive sequence of the
following eight numbers that form a sine-wave: 0, 2399, 8192, 13984,
16383, 13984, 8192, 2399.
CHB TEST PATTERN
0h
Others = Do not use
0
0h
Must write 0
34
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9.6.2.10 Register 0Eh
图 67. Register 0Eh
7
6
5
4
3
2
1
0
CUSTOM PATTERN[13:6]
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 19. Register 0Eh Description
Bit
Field
Type
Reset
Description
These bits set the 14-bit custom pattern (bits 13-6) for all channels.
7-0
CUSTOM PATTERN[13:6]
R/W
0h
9.6.2.11 Register 0Fh
图 68. Register 0Fh
7
6
5
4
3
2
1
0
0
0
CUSTOM PATTERN[5:0]
R/W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; R = Read only; W = Write only; -n = value after reset
表 20. Register 0Fh Description
Bit
7-2
1-0
Field
Type
R/W
W
Reset
0h
Description
CUSTOM PATTERN[5:0]
0
These bits set the 14-bit custom pattern (bits 5-0) for all channels.
Must write 0
0h
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9.6.2.12 Register 13h (address = 13h)
图 69. Register 13h
7
0
6
0
5
0
4
0
3
0
2
0
1
0
LOW SPEED ENABLE
R/W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
表 21. Register 13h Field Descriptions
Bit
7-2
1-0
Field
Type
W
Reset
0h
Description
0
Must write 0.
LOW SPEED ENABLE
R/W
0h
Enables low speed operation in 1-wire and 2-wire mode.
Depending upon sampling frequency, write this bit as per 表 22.
表 22. LOW SPEED ENABLE Register Bit Settings Across fS
fS (MSPS)
REGISTER BIT LOW SPEED ENABLE
MIN
25
MAX
125
25
1-WIRE MODE
2-WIRE MODE
00
00
10
00
10
20
15
20
Not supported
9.6.2.13 Register 15h
图 70. Register 15h
7
0
6
5
4
0
3
2
1
0
0
CHA PDN
R/W-0h
CHB PDN
R/W-0h
STANDBY
R/W-0h
GLOBAL PDN
R/W-0h
CONFIG PDN PIN
R/W-0h
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; R = Read only; W = Write only; -n = value after reset
表 23. Register 15h Description
Bit
Field
Type
Reset
Description
7
0
W
0h
Must write 0
0 = Normal operation
1 = Power-down channel A
6
CHA PDN
R/W
0h
0 = Normal operation
1 = Power-down channel B
5
4
CHB PDN
0
R/W
W
0h
0h
Must write 0
The ADCs of both channels enter standby.
0 = Normal operation
3
STANDBY
R/W
0h
1 = Standby
0 = Normal operation
1 = Global power-down
2
1
GLOBAL PDN
0
R/W
W
0h
0h
Must write 0
This bit configures the PDN pin as either a global power-down or
standby pin.
0
CONFIG PDN PIN
R/W
0h
0 = Logic high voltage on the PDN pin sends the device into global
power-down
1 = Logic high voltage on the PDN pin sends the device into standby
36
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9.6.2.14 Register 25h
图 71. Register 25h
7
6
5
4
3
2
1
0
LVDS SWING
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 24. Register 25h Description
Bit
Field
Type
Reset
Description
These bits control the swing of the LVDS outputs (including the
data output, bit clock, and frame clock). For details see 表 25.
7-0
LVDS SWING
R/W
0h
表 25. LVDS Output Swing
BITS 7-4
0h
BITS 3-0
0h
LVDS OUTPUT SWING
Default (±425 mV)
Dh
9h
Swing reduces by 50 mV
Swing reduces by 100 mV
Swing reduces by 300 mV
Swing increases by 100 mV
Do not use
Eh
Ah
Fh
Dh
Ch
Eh
Others
Others
9.6.2.15 Register 27h
图 72. Register 27h
7
6
5
0
4
0
3
0
2
0
1
0
0
0
CLK DIV
R/W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; R = Read only; W = Write only; -n = value after reset
表 26. Register 27h Description
Bit
7-6
5-0
Field
CLK DIV
0
Type
R/W
W
Reset
Description
These bits set the internal clock divider for the input sampling clock.
00 = Divide-by-1
01 = Divide-by-1
10 = Divide-by-2
11 = Divide-by-4
0h
0h
Must write 0
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9.6.2.16 Register 41Dh
图 73. Register 41Dh
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
HIGH IF MODE0
R/W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; R = Read only; W = Write only; -n = value after reset
表 27. Register 41Dh Description
Bit
Field
Type
Reset
Description
7-2
0
W
0h
Must write 0
This bit improves HD3 for IF > 100 MHz.
0 = Normal operation
For best HD3 at IF > 100 MHz, set HIGH IF MODE[3:0] to 1111.
1
0
HIGH IF MODE0
0
R/W
W
0h
0h
Must write 0
9.6.2.17 Register 422h
图 74. Register 422h
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
DIS CHOP CHA
R/W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; R = Read only; W = Write only; -n = value after reset
表 28. Register 422h Description
Bit
Field
Type
Reset
Description
7-2
0
W
0h
Must write 0
Disable chopper.
Set this bit to shift a 1/f noise floor at dc.
1
DIS CHOP CHA
R/W
W
0h
0h
0 = 1/f noise floor is centered at fS / 2 (default)
1 = Chopper mechanism is disabled; 1/f noise floor is centered at
dc
0
0
Must write 0
9.6.2.18 Register 434h
图 75. Register 434h
7
0
6
0
5
4
0
3
2
0
1
0
0
0
DIS DITH CHA
R/W-0h
DIS DITH CHA
R/W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; R = Read only; W = Write only; -n = value after reset
表 29. Register 434h Description
Bit
Field
Type
Reset
Description
7-6
0
W
0h
Must write 0
Set this bit with bits 5 and 4 of register 01h.
00 = Default
11 = Dither is disabled for channel A. In this mode, SNR typically
improves by 0.5 dB at 70 MHz.
5
4
DIS DITH CHA
R/W
W
0h
0h
0h
0h
0
Must write 0
Set this bit with bits 5 and 4 of register 01h.
00 = Default
11 = Dither is disabled for channel A. In this mode, SNR typically
improves by 0.5 dB at 70 MHz.
3
DIS DITH CHA
0
R/W
W
2-0
Must write 0
38
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9.6.2.19 Register 439h
图 76. Register 439h
7
0
6
0
5
0
4
0
3
2
0
1
0
0
SP1 CHA
R/W-0h
0
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; R = Read only; W = Write only; -n = value after reset
表 30. Register 439h Description
Bit
Field
Type
Reset
Description
7-4
0
W
0h
Must write 0
Special mode for best performance on channel A.
Always write 1 after reset.
3
SP1 CHA
0
R/W
W
0h
0h
2-0
Must write 0
9.6.2.20 Register 51Dh
图 77. Register 51Dh
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
HIGH IF MODE1
R/W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; R = Read only; W = Write only; -n = value after reset
表 31. Register 51Dh Description
Bit
Field
Type
Reset
Description
7-2
0
W
0h
Must write 0
This bit improves HD3 for IF > 100 MHz.
0 = Normal operation
For best HD3 at IF > 100 MHz, set HIGH IF MODE[3:0] to 1111.
1
0
HIGH IF MODE1
0
R/W
W
0h
0h
Must write 0
9.6.2.21 Register 522h
图 78. Register 522h
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
DIS CHOP CHB
R/W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; R = Read only; W = Write only; -n = value after reset
表 32. Register 522h Description
Bit
Field
Type
Reset
Description
7-2
0
W
0h
Must write 0
Disable chopper.
Set this bit to shift a 1/f noise floor at dc.
1
0
DIS CHOP CHB
0
R/W
W
0h
0h
0 = 1/f noise floor is centered at fS / 2 (default)
1 = Chopper mechanism is disabled; 1/f noise floor is centered
at dc
Must write 0
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9.6.2.22 Register 534h
图 79. Register 534h
7
0
6
0
5
4
0
3
2
0
1
0
0
0
DIS DITH CHA
R/W-0h
DIS DITH CHA
R/W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; R = Read only; W = Write only; -n = value after reset
表 33. Register 534h Description
Bit
Field
Type
Reset
Description
7-6
0
W
0h
Must write 0
Set this bit with bits 3 and 2 of register 01h.
00 = Default
11 = Dither is disabled for channel B. In this mode, SNR typically
improves by 0.5 dB at 70 MHz.
5
4
DIS DITH CHA
R/W
W
0h
0h
0h
0h
0
Must write 0
Set this bit with bits 3 and 2 of register 01h.
00 = Default
11 = Dither is disabled for channel B. In this mode, SNR typically
improves by 0.5 dB at 70 MHz.
3
DIS DITH CHA
0
R/W
W
2-0
Must write 0
9.6.2.23 Register 539h
图 80. Register 539h
7
0
6
0
5
0
4
0
3
2
0
1
0
0
0
SP1 CHB
R/W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; R = Read only; W = Write only; -n = value after reset
表 34. Register 539h Description
Bit
Field
Type
Reset
Description
7-4
0
W
0h
Must write 0
Special mode for best performance on channel B.
Always write 1 after reset.
3
0
SP1 CHB
0
R/W
W
0h
0h
Must write 0
9.6.2.24 Register 608h
图 81. Register 608h
7
6
5
0
4
0
3
0
2
0
1
0
0
0
HIGH IF MODE[3:2]
R/W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; R = Read only; W = Write only; -n = value after reset
表 35. Register 608h Description
Bit
7-6
5-0
Field
Type
R/W
W
Reset
Description
This bit improves HD3 for IF > 100 MHz.
0 = Normal operation
For best HD3 at IF > 100 MHz, set HIGH IF MODE[3:0] to 1111.
HIGH IF MODE[3:2]
0
0h
0h
Must write 0
40
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9.6.2.25 Register 70Ah
图 82. Register 70Ah
7
6
0
5
0
4
0
3
0
2
0
1
0
DIS CLK FILT
R/W-0h
0
PDN SYSREF
R/W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; R = Read only; W = Write only; -n = value after reset
表 36. Register 70Ah Description
Bit
7
Field
Type
R/W
W
Reset
Description
Set this bit to improve wake-up time from global power-down
mode; see the Improving Wake-Up Time From Global Power-
Down section for details.
DIS CLK FILT
0
0h
6-1
0h
Must write 0
If the SYSREF pins are not used in the system, the SYSREF
buffer must be powered down by setting this bit.
0 = Normal operation
0
PDN SYSREF
R/W
0h
1 = Powers down the SYSREF buffer
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10 Applications and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
Typical applications involving transformer coupled circuits are discussed in this section. Transformers (such as
ADT1-1WT or WBC1-1) can be used up to 250 MHz to achieve good phase and amplitude balances at ADC
inputs. While designing the dc driving circuits, the ADC input impedance must be considered. 图 83 and 图 84
show the impedance (Zin = Rin || Cin) across the ADC input pins.
10
6
5
4
3
2
1
1
0.1
0.01
0
100 200 300 400 500 600 700 800 900 1000
Frequency (MHz)
0
100 200 300 400 500 600 700 800 900 1000
Frequency (MHz)
D024
D00215
图 83. Differential Input Resistance (RIN
)
图 84. Differential Input Capacitance (CIN)
42
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10.2 Typical Applications
10.2.1 Driving Circuit Design: Low Input Frequencies
0.1 µF
0.1 µF
INP
50 ꢀ
0.1 µF
50 Ω
22 pF
50 Ω
25 Ω
25 Ω
TI Device
50 ꢀ
1:1
1:1
INM
0.1 µF
VCM
图 85. Driving Circuit for Low Input Frequencies
10.2.1.1 Design Requirements
For optimum performance, the analog inputs must be driven differentially. An optional 5-Ω to 15-Ω resistor in
series with each input pin can be kept to damp out ringing caused by package parasitic. The drive circuit may
have to be designed to minimize the impact of kick-back noise generated by sampling switches opening and
closing inside the ADC, as well as providing low insertion loss over the desired frequency range and matched
impedance to the source.
10.2.1.2 Detailed Design Procedure
A typical application involving using two back-to-back coupled transformers is shown in 图 85. The circuit is
optimized for low input frequencies. An external R-C-R filter using 50-Ω resistors and a 22-pF capacitor is used
with the series inductor (39 nH), this combination helps absorb the sampling glitches.
10.2.1.3 Application Curve
图 86 shows the performance obtained by using circuit shown in 图 85.
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
0
12.5
25
37.5
50
62.5
Frequency (MHz)
D101
SFDR = 102.6 dBc, SNR = 72.9 dBFS, SINAD = 72.8 dBFS,
THD = 99.8 dBc, HD2 = –108.6 dBc, HD3 = –104.0 dBc
图 86. Performance FFT at 10 MHz (Low Input Frequency)
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Typical Applications (接下页)
10.2.2 Driving Circuit Design: Input Frequencies Between 100 MHz to 230 MHz
0.1 µF
10 ꢀ
0.1 µF
INP
15 Ω
25 Ω
0.1 pF
TI Device
10 pF
56 nH
25 Ω
15 Ω
1:1
1:1
INM
10 ꢀ
0.1 µF
VCM
图 87. Driving Circuit for Mid-Range Input Frequencies (100 MHz < fIN < 230 MHz)
10.2.2.1 Design Requirements
See the previous Design Requirements section for further details.
10.2.2.2 Detailed Design Procedure
When input frequencies are between 100 MHz to 230 MHz, an R-LC-R circuit can be used to optimize
performance, as shown in 图 87.
10.2.2.3 Application Curve
图 88 shows the performance obtained by using circuit shown in 图 87.
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
0
12.5
25
37.5
50
62.5
Frequency (MHz)
D105
SFDR = 96.4 dBc, SNR = 72.1 dBFS, SINAD = 72.0 dBFS,
THD = 92.6 dBc, HD2 = –96.4 dBc, HD3 = –98.8 dBc
图 88. Performance FFT at 170 MHz (Mid Input Frequency)
44
版权 © 2019, Texas Instruments Incorporated
ADC3244E
www.ti.com.cn
ZHCSJF0 –FEBRUARY 2019
Typical Applications (接下页)
10.2.3 Driving Circuit Design: Input Frequencies Greater than 230 MHz
0.1 µF
0.1 µF
10 Ω
INP
0.1 µF
25 ꢀ
25 ꢀ
TI Device
10 Ω
INM
1:1
1:1
0.1 µF
VCM
图 89. Driving Circuit for High input Frequencies ( fIN > 230 MHz)
10.2.3.1 Design Requirements
See the first Design Requirements section for further details.
10.2.3.2 Detailed Design Procedure
For high input frequencies (> 230 MHz), using the R-C-R or R-LC-R circuit does not show significant
improvement in performance. However, a series resistance of 10 Ω can be used as shown in 图 89.
10.2.3.3 Application Curve
图 90 shows the performance obtained by using circuit shown in 图 89.
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
0
12.5
25
37.5
50
62.5
Frequency (MHz)
D109
SFDR = 76.2 dBc, SNR = 68.3 dBFS, SINAD = 67.5 dBFS,
THD = 74.3 dBc, HD2 = –76.2 dBc, HD3 = –79.2 dBc
图 90. Performance FFT at 450 MHz (High Input Frequency)
11 Power Supply Recommendations
The device requires a 1.8-V nominal supply for AVDD and DVDD. There are no specific sequence power-supply
requirements during device power-up. AVDD and DVDD can power up in any order.
版权 © 2019, Texas Instruments Incorporated
45
ADC3244E
ZHCSJF0 –FEBRUARY 2019
www.ti.com.cn
12 Layout
12.1 Layout Guidelines
The ADC3244E EVM layout can be used as a reference layout to obtain the best performance. A layout diagram
of the EVM top layer is provided in 图 91. Some important points to remember during laying out the board are:
1. Place the analog inputs on opposite sides of the device pin out to provide minimum crosstalk on the package
level. To minimize crosstalk onboard, the analog inputs must exit the pin out in opposite directions, as shown
in the reference layout of 图 91 as much as possible.
2. In the device pin out, place the sampling clock on a side perpendicular to the analog inputs in order to
minimize coupling between them. This configuration is also maintained on the reference layout of 图 91 as
much as possible.
3. Keep digital outputs away from the analog inputs. When these digital outputs exit the pin out, do not keep the
digital output traces parallel to the analog input traces because this configuration can result in coupling from
digital outputs to analog inputs and degrade performance. All digital output traces to the receiver [such as a
field-programmable gate array (FPGA) or an application-specific integrated circuit (ASIC)] must be matched
in length to avoid skew among outputs.
4. At each power-supply pin (AVDD and DVDD), keep a 0.1-µF decoupling capacitor close to the device. A
separate decoupling capacitor group consisting of a parallel combination of 10-µF, 1-µF, and 0.1-µF
capacitors can be kept close to the supply source.
12.2 Layout Example
Sampling
Clock
Analog
Input
Routing
Routing
ADC32xx
Digital
Output
Routing
图 91. Typical Layout of the ADC3244E Board
46
版权 © 2019, Texas Instruments Incorporated
ADC3244E
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ZHCSJF0 –FEBRUARY 2019
13 器件和文档支持
13.1 接收文档更新通知
要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我 进行注册，即可每周接收产
品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
13.2 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
13.3 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
13.4 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
13.5 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、缩写和定义。
14 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。
版权 © 2019, Texas Instruments Incorporated
47
PACKAGE OPTION ADDENDUM
www.ti.com
23-Apr-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
ADC3244EIRGZT
ACTIVE
VQFN
RGZ
48
250
RoHS & Green
NIPDAUAG
Level-3-260C-168 HR
-50 to 105
AZ3244E
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
GENERIC PACKAGE VIEW
RGZ 48
7 x 7, 0.5 mm pitch
VQFN - 1 mm max height
PLASTIC QUADFLAT PACK- NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224671/A
www.ti.com
PACKAGE OUTLINE
RGZ0048D
VQFN - 1 mm max height
S
C
A
L
E
1
.
9
0
0
PLASTIC QUAD FLATPACK - NO LEAD
7.1
6.9
A
B
0.5
0.3
PIN 1 INDEX AREA
7.1
6.9
0.30
0.18
DETAIL
OPTIONAL TERMINAL
TYPICAL
1.0
0.8
C
SEATING PLANE
0.08 C
0.05
0.00
5.6 0.1
2X 5.5
(0.2) TYP
13
24
44X 0.5
12
25
EXPOSED
THERMAL PAD
2X
49
SYMM
5.5
SEE TERMINAL
DETAIL
1
36
0.30
48X
0.18
37
48
PIN 1 ID
(OPTIONAL)
SYMM
0.1
C A B
0.5
0.3
48X
0.05
4219046/B 11/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RGZ0048D
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
5.6)
SYMM
48
37
48X (0.6)
1
36
48X (0.24)
6X
(1.22)
44X (0.5)
SYMM
10X
(1.33)
49
(6.8)
(R0.05)
TYP
(
0.2) TYP
VIA
25
12
13
24
10X (1.33)
6X (1.22)
(6.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:12X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4219046/B 11/2019
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RGZ0048D
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(0.665 TYP)
(1.33) TYP
16X ( 1.13)
37
48
48X (0.6)
49
36
1
48X (0.24)
44X (0.5)
(1.33)
TYP
(0.665)
TYP
SYMM
(6.8)
(R0.05) TYP
25
12
METAL
TYP
13
24
SYMM
(6.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 49
66% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:15X
4219046/B 11/2019
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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Copyright © 2022，德州仪器 (TI) 公司
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