ADC3543IRSBT_技术文档

ADC3541, ADC3542, ADC3543

ZHCSLJ1C –JULY 2020 –REVISED DECEMBER 2022

ADC354x 14 位10MSPS 至65MSPS 低噪声、超低功耗ADC

1 特性

3 说明

• 14 位10/25/65 MSPS ADC

• 本底噪声：–155 dBFS/Hz

• 超低功耗，具备优化的功耗调节：

35 mW (10 MSPS) 至84 mW (65 MSPS)

• 延迟：1 个时钟周期

• INL：±0.6 LSB；DNL：±0.1 LSB

• 基准：外部或内部

• 输入带宽：900 MHz (3dB)

• 工业温度范围：-40°C 至+105°C

• 片上数字滤波器（可选）

– 2 倍、4 倍、8 倍、16 倍、32 倍抽取率

– 32 位NCO

• SDR/DDR 和串行CMOS 接口

• 小尺寸: 40 引脚WQFN (5mm × 5mm) 封装

• 1.8V 单电源

ADC3541、ADC3542 和 ADC3543 (ADC354x) 系列

器件是低噪声、超低功耗、14 位、10 至 65 MSPS 高

速模数转换器 (ADC)。这些器件可实现低功耗，噪声

频谱密度为 –155 dBFS/Hz。ADC354x 可实现出色的

直流精度并支持中频采样，因此是各种应用的完美选

择。高速控制环路受益于只有一个时钟周期的低延迟。

该ADC 在65 MSPS 下的功耗仅为 79 mW，功耗有效

地随低采样率而变化。

ADC354x 使用SDR、DDR 或串行CMOS 接口输出数

据，提供功耗超低的数字接口，并能以灵活的方式最大

限度地减少数字互连的次数。这些器件属于引脚对引脚

兼容系列，具有不同的速度等级。这些器件支持 –

40°C 至+105⁰C 的扩展工业温度范围。

封装信息

封装⁽¹⁾

封装尺寸（标称值）

器件型号

• 性能规格(f_IN= 10 MHz)：

ADC354x

WQFN (40)

5.00mm × 5.00mm

– SNR：79.0 dBFS

– SFDR：87 dBc HD2、HD3

– SFDR：99 dBFS 最严重毛刺

• 频谱性能(f_IN= 64 MHz)：

– SNR：78.0 dBFS

(1) 如需了解所有可用封装，请参阅数据表末尾的封装选项附录。

器件比较

器件型号

分辨率

14 位

采样率

ADC3544

125 MSPS

– SFDR：70 dBc HD2、HD3

– SFDR：91 dBFS 最严重毛刺

ADC3543

ADC3542

ADC3541

65 MSPS

25 MSPS

10 MSPS

2 应用

• 高速数据采集

• 工业监控

• 热成像

• 成像和声纳

• 软件定义无线电

• 电能质量分析

• 通信基础设施

• 高速控制环路

• 仪表

REFBUF

VREF

1.2V REF

Digital Downconverter

NCO

ADC

14bit

N

AIN

DCLK

0.95V

VCM

Dig I/F

CMOS

• 智能电网

• 光谱分析

• 雷达

D0..15

CLK

ADC354x 方框图

本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SBAS840

ADC3541, ADC3542, ADC3543

ZHCSLJ1C –JULY 2020 –REVISED DECEMBER 2022

www.ti.com.cn

Table of Contents

8 Detailed Description......................................................28

8.1 Overview...................................................................28

8.2 Functional Block Diagram.........................................28

8.3 Feature Description...................................................29

8.4 Device Functional Modes..........................................54

8.5 Programming............................................................ 55

8.6 Register Map.............................................................57

9 Application Information Disclaimer.............................71

9.1 Application Information............................................. 71

9.2 Typical Application.................................................... 71

9.3 Initialization Set Up................................................... 74

10 Power Supply Recommendations..............................75

11 Layout...........................................................................77

11.1 Layout Guidelines................................................... 77

11.2 Layout Example...................................................... 77

12 Device and Documentation Support..........................78

12.1 Receiving Notification of Documentation Updates..78

12.2 支持资源..................................................................78

12.3 Trademarks.............................................................78

12.4 Electrostatic Discharge Caution..............................78

12.5 术语表..................................................................... 78

13 Mechanical, Packaging, and Orderable

1 特性................................................................................... 1

2 应用................................................................................... 1

3 说明................................................................................... 1

4 Revision History.............................................................. 2

5 Pin Configuration and Functions...................................3

6 Specifications.................................................................. 5

6.1 Absolute Maximum Ratings........................................ 5

6.2 ESD Ratings............................................................... 5

6.3 Recommended Operating Conditions.........................5

6.4 Thermal Information....................................................5

6.5 Electrical Characteristics - Power Consumption.........6

6.6 Electrical Characteristics - DC Specifications.............7

6.7 Electrical Characteristics - AC Specifications

ADC3541.......................................................................9

6.8 Electrical Characteristics - AC Specifications

ADC3542.....................................................................10

6.9 Electrical Characteristics - AC Specifications

ADC3543.....................................................................11

6.10 Timing Requirements..............................................12

6.11 Typical Characteristics: ADC3541...........................14

6.12 Typical Characteristics: ADC3542.......................... 17

6.13 Typical Characteristics: ADC3543.......................... 21

7 Parameter Measurement Information..........................26

Information.................................................................... 78

4 Revision History

注：以前版本的页码可能与当前版本的页码不同

Changes from Revision B (February 2022) to Revision C (December 2022)

Page

• 删除了器件比较表中ADC3543 和ADC3544 的“产品预发布”说明................................................................1

Changes from Revision A (July 2020) to Revision B (February 2022)

Page

• 将数据表从预告信息更改为量产数据................................................................................................................ 1

2

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5 Pin Configuration and Functions

图5-1. RSB Package, 40-Pin WQFN

(Top View)

表5-1. Pin Descriptions

I/O

DESCRIPTION

NAME

NO.

INPUT/REFERENCE

AINM

AINP

14

13

I

Negative analog input

Positive analog input

1.2-V external voltage reference input for use with internal reference buffer. Internal 100 kΩ

pull-up resistor to AVDD. This pin is also used to configure default operating conditions.

REFBUF

4

I

REFGND

VCM

3

9

2

I

O

I

Reference ground input, 0 V

Common-mode voltage output for the analog inputs, 0.95 V

External voltage reference input, 1.6 V.

VREF

CLOCK

CLKM

7

6

I

Negative differential sampling clock input for the ADC

Positive differential sampling clock input for the ADC

CLKP

CONFIGURATION

Power down, synchronization input. This pin can be configured via the SPI interface. Active

high. This pin has an internal 21 kΩpull-down resistor.

PDN/SYNC

1

I

RESET

SCLK

SDIO

SEN

10

40

39

17

I

Hardware reset; active high. This pin has an internal 21 kΩpull-down resistor.

Serial interface clock input. This pin has an internal 21 kΩpull-down resistor.

Serial interface data input and output. This pin has an internal 21 kΩpull-down resistor.

Serial interface enable. Active low. This pin has an internal 21 kΩpull-up resistor to AVDD.

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表5-1. Pin Descriptions (continued)

I/O

DESCRIPTION

NAME

NO.

DIGITAL INTERFACE

DCLK

D0

26

O

CMOS output for data bit clock.

SDR CMOS output used with 18 bit output (configured via output bit formatter). This

becomes the LSB. When not used it can be left unconnected.

See 节8.3.5.4 and 节8.3.5.5 on how to change the output resolution and output bit

mapping.

38

SDR CMOS output used with 16 bit output (configured via output bit formatter). This

becomes the LSB. When not used it can be left unconnected.

D1

D2

37

36

O

SDR CMOS output for data bit D0 (14 bit LSB).

D3/

DCLKIN

35

I/O

SDR CMOS output for data bit D1. Used as DCLKIN for serial CMOS output modes.

D4

D5

D6

D7

D8

D9

D10

34

33

32

30

29

28

27

O

SDR CMOS output for data bit D2.

SDR CMOS output for data bit D3.

SDR CMOS output for data bit D4.

SDR CMOS output for data bit D5.

SDR CMOS output for data bit D6.

SDR CMOS output for data bit D7.

SDR CMOS output for data bit D8.

D11/ Serial

Lane 0

SDR CMOS output for data bit D9. DDR CMOS output for data bits D6/D13 (MSB). Lane 0

in serial CMOS output mode.

24

23

O

D12/

Serial Lane 1

SDR CMOS output for data bit D10. DDR CMOS output for data bits D5/D12. Lane 1 in

serial CMOS output mode.

SDR CMOS output for data bit D11.

DDR CMOS output for data bits D4/D11.

D13

D14

D15

22

21

20

O

SDR CMOS output for data bit D12.

DDR CMOS output for data bits D3/D10.

CMOS output for data bit D13 (MSB).

DDR CMOS output for data bits D2/D9.

SDR CMOS output used with 16 bit output (configured via output bit formatter). This

becomes the MSB. When not used it can be left unconnected.

DDR CMOS output for data bits D1/D8. Frame clock output in serial CMOS output mode.

D16/ FCLK

D17

19

18

O

SDR CMOS output used with 18 bit output (configured via output bit formatter). This

becomes the MSB. When not used it can be left unconnected.

DDR CMOS output for data bits D0/D7 (LSB).

POWER SUPPLY

AVDD

5,8,11,16

I

Analog 1.8-V power supply

Ground, 0 V

GND

12,15

25

IOGND

I

Ground, 0 V for digital interface

1.8-V power supply for digital interface

Connect to ground.

IOVDD

31

I

PowerPAD^™

--

4

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6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

PARAMETER

TEST CONDITIONS

MIN

–0.3

MAX UNIT

Supply voltage range, AVDD, IOVDD

2.1

0.3

V

Supply voltage range, GND, IOGND, REFGND

AINP/M, CLKP/M, VREF, REFBUF

Voltage applied

to input pins

D3 (DCLKIN)

Junction temperature, T_J

MIN(2.1, AVDD+0.3)

MIN(2.1, IOVDD+0.3)

105

V

PDN, RESET, SCLK, SEN, SDIO

V

°C

Storage temperature, T_stg

150

–65

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under

Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device

reliability.

6.2 ESD Ratings

VALUE

2500

UNIT

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins⁽¹⁾

Charged device model (CDM), per ANSI/ESDA/JEDEC JS-002, all pins⁽²⁾

V_(ESD)

Electrostatic discharge

V

1000

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

1.75

–40

NOM

1.8

MAX

1.85

UNIT

AVDD⁽¹⁾

V

Supply

voltage range

IOVDD⁽¹⁾

1.8

1.85

T_A

T_J

Operating free-air temperature

Operating junction temperature

105

°C

105⁽²⁾

(1) Measured to GND.

(2) Prolonged use above this junction temperature may increase the device failure-in-time (FIT) rate.

6.4 Thermal Information

ADC354x

THERMAL METRIC⁽¹⁾

RSB (QFN)

40 Pins

30.7

UNIT

R_ΘJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

R_ΘJC(top)

R_ΘJB

16.4

10.5

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

0.2

Ψ_JT

10.5

Ψ_JB

R_ΘJC(bot)

2.0

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report, SPRA953.

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6.5 Electrical Characteristics - Power Consumption

Typical values are over the operating free-air temperature range, at T_A= 25°C, full temperature range is T_MIN= –40°C to

T_MAX= 105°C, ADC sampling rate = 65 MSPS, 50% clock duty cycle, AVDD, IOVDD = 1.8 V, external 1.6V reference, 5 pF

output load, and –1-dBFS differential input, unless otherwise noted

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

ADC3541 - 10 MSPS

I_AVDD

I_IOVDD

P_DIS

Analog supply current

I/O supply current⁽¹⁾

Power dissipation⁽¹⁾

External reference

15.5

4

mA

SDR CMOS

External reference, SDR CMOS

DDR CMOS

35

4

mW

Serial CMOS 2-wire

Serial CMOS 1-wire

5

I_IOVDD

I/O supply current⁽¹⁾

mA

6

4x complex decimation, Serial CMOS

2-wire

6.5

ADC3542 - 25 MSPS

I_AVDD

I_IOVDD

P_DIS

Analog supply current

External reference

SDR CMOS

20

6

31

13

mA

mW

I/O supply current⁽¹⁾

Power dissipation⁽¹⁾

External reference, SDR CMOS

DDR CMOS

46

6

Serial CMOS 2-wire

7

I_IOVDD

I/O supply current⁽¹⁾

mA

4x complex decimation, Serial CMOS

2-wire

10

ADC3543 - 65 MSPS

I_AVDD

I_IOVDD

P_DIS

Analog supply current

External reference

SDR CMOS

35

11

84

11

47

20

mA

I/O supply current⁽¹⁾

Power dissipation⁽¹⁾

External reference, SDR CMOS

DDR CMOS

mW

I_IOVDD

I/O supply current⁽¹⁾

mA

8x complex decimation, Serial CMOS

2-wire

16

MISCELLANEOUS

Internal reference, additional analog supply current

2

External 1.2V reference (REFBUF), additional analog supply current

0.3

I_AVDD

mA

Single ended clock input, reduces

Enabled via SPI

0.7

5

analog supply current by

Default power down mask, internal

reference

Power consumption in global power

down mode

P_DIS

mW

Default power down mask, external

reference

9

(1) Measured with full-scale sine wave input signal at specified sample rate, with ~ 5 pF loading on each CMOS output pin.

6

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6.6 Electrical Characteristics - DC Specifications

Typical values are over the operating free-air temperature range, at T_A= 25°C, full temperature range is T_MIN= –40°C to

T_MAX= 105°C, ADC sampling rate = 65 MSPS, 50% clock duty cycle, AVDD, IOVDD = 1.8 V, external 1.6V reference, 5 pF

output load, and –1-dBFS differential input, unless otherwise noted

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

bits

dB

No missing codes

PSRR

14

F_IN= 1 MHz

38

ADC3541 - 10 MSPS: DC ACCURACY

DNL

Differential nonlinearity

Integral nonlinearity

Offset error

F_IN= 1.1 MHz

± 0.2

± 0.6

12

± 0.85

± 2.1

130

LSB

INL

V_{OS_ERR}

V_{OS_DRIFT}

GAIN_ERR

GAIN_DRIFT

GAIN_ERR

GAIN_DRIFT

LSB

Offset drift over temperature

Gain error

0.01

0.5

LSB/ºC

%FSR

ppm/ºC

%FSR

ppm/ºC

LSB_RMS

External 1.6 V reference

Internal reference

Gain drift over temperature

Gain error

25

-2.3

151

0.45

Gain drift over temperature

Internal reference

Transition Noise

ADC3542 - 25 MSPS: DC ACCURACY

DNL

Differential nonlinearity

Integral nonlinearity

Offset error

F_IN= 1.1 MHz

± 0.2

± 0.6

12

± 0.85

± 2.1

130

LSB

INL

V_{OS_ERR}

V_{OS_DRIFT}

GAIN_ERR

GAIN_DRIFT

GAIN_ERR

GAIN_DRIFT

LSB

Offset drift over temperature

Gain error

-0.01

-0.2

31

LSB/ºC

%FSR

ppm/ºC

%FSR

ppm/ºC

LSB_RMS

External 1.6 V reference

Internal reference

Gain drift over temperature

Gain error

-2.8

151

0.45

Gain drift over temperature

Internal reference

Transition Noise

ADC3543 - 65 MSPS: DC ACCURACY

DNL

Differential nonlinearity

Integral nonlinearity

Offset error

F_IN= 5 MHz

± 0.1

± 0.6

5.9

± 0.75

± 4.3

55

LSB

INL

V_{OS_ERR}

V_{OS_DRIFT}

GAIN_ERR

GAIN_DRIFT

GAIN_ERR

GAIN_DRIFT

LSB

Offset drift over temperature

Gain error

0.02

0.7

LSB/ºC

%FSR

ppm/ºC

%FSR

ppm/ºC

LSB_RMS

External 1.6 V reference

Internal reference

Gain drift over temperature

Gain error

25

0.8

Gain drift over temperature

Internal reference

96

Transition Noise

0.45

ADC ANALOG INPUT (AINP/M)

FS

Input full scale

Default, differential

2.25

0.95

8

Vpp

V

V_CM

R_IN

Input common mode voltage

Differential input resistance

Differential input capacitance

Output common mode voltage

Analog input bandwidth (-3dB)

0.9

1.0

F_IN= 100 kHz

kΩ

pF

C_IN

7

V_OCM

BW

0.95

900

V

MHz

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6.6 Electrical Characteristics - DC Specifications (continued)

Typical values are over the operating free-air temperature range, at T_A= 25°C, full temperature range is T_MIN= –40°C to

T_MAX= 105°C, ADC sampling rate = 65 MSPS, 50% clock duty cycle, AVDD, IOVDD = 1.8 V, external 1.6V reference, 5 pF

output load, and –1-dBFS differential input, unless otherwise noted

PARAMETER

Internal Voltage Reference

V_REFInternal reference voltage

TEST CONDITIONS

MIN

TYP

MAX

UNIT

1.6

8

V

V_REFOutput Impedance

Ω

Reference Input Buffer (REFBUF)

External reference voltage

1.2

V

External voltage reference (VREF)

V_REF

External voltage reference

1.6

0.3

5.3

V

Input Current

mA

kΩ

Input impedance

Clock Input (CLKP/M)

Input clock frequency

0.5

65

MHz

Vpp

V

V_ID

V_CM

R_IN

C_IN

Differential input voltage

1

0.9

5

3.6

Input common mode voltage

Single ended input resistance to common mode

Single ended input capacitance

kΩ

pF

1.5

50

Clock duty cycle

40

60

%

Digital Inputs (RESET, PDN, SCLK, SEN, SDIO)

V_IH

V_IL

I_IH

I_IL

High level input voltage

Low level input voltage

High level input current

Low level input current

Input capacitance

1.5

V

0.4

90

150

uA

pF

-150

C_I

1.5

Digital Output (SDOUT)

IOVDD

–0.1

V_OH

V_OL

High level output voltage

Low level output voltage

I_LOAD= -400 uA

IOVDD

V

I_LOAD= 400 uA

0.1

CMOS Interface (D0:D17)

Output data rate

per CMOS output pin

I_LOAD= -400 uA

250

MHz

V

IOVDD

–0.1

V_OH

V_OL

V_IH

V_IL

High level output voltage

IOVDD

Low level output voltage

High level input voltage

Low level input voltage

I_LOAD= 400 uA

0.1

IOVDD

–0.1

Input clock (Serial CMOS)

V

8

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6.7 Electrical Characteristics - AC Specifications ADC3541

Typical values are over the operating free-air temperature range, at T_A= 25°C, full temperature range is T_MIN= –40°C to

T_MAX= 105°C, ADC sampling rate = 10 MSPS, external reference, 50% clock duty cycle, AVDD, IOVDD = 1.8 V, external

1.6V reference, 5 pF output load, and –1-dBFS differential input, unless otherwise noted

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

dBFS/Hz

dBFS

ADC3541: 10 MSPS

NSD

SNR

Noise Spectral Density

Signal to noise ratio

f_IN= 1.1 MHz, A_IN= -20 dBFS

f_IN= 1.1 MHz

f_IN= 4.9 MHz

f_IN= 9.9 MHz

f_IN= 1.1 MHz

f_IN= 4.9 MHz

f_IN= 9.9 MHz

f_IN= 1.1 MHz

f_IN= 4.9 MHz

f_IN= 9.9 MHz

f_IN= 1.1 MHz

f_IN= 4.9 MHz

f_IN= 9.9 MHz

f_IN= 1.1 MHz

f_IN= 4.9 MHz

f_IN= 9.9 MHz

f_IN= 1.1 MHz

f_IN= 4.9 MHz

f_IN= 9.9 MHz

-146.5

79.0

12.8

90

76.0

12.3

79

SINAD

ENOB

THD

Signal to noise and distortion ratio

Effective number of bits

dBFS

bit

Total Harmonic Distortion (First five

harmonics)

94

dBc

87

93

Spur free dynamic range including

second and third harmonic distortion

SFDR

85

95

87

99

Spur free dynamic range (excluding

HD2 and HD3)

Non HD2,3

IMD3

90

100

dBFS

dBc

f₁= 3 MHz, f₂= 4 MHz, A_IN= -7 dBFS/

tone

Two tone inter-modulation distortion

92

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6.8 Electrical Characteristics - AC Specifications ADC3542

Typical values are over the operating free-air temperature range, at T_A= 25°C, full temperature range is T_MIN= –40°C to

T_MAX= 105°C, ADC sampling rate = 25 MSPS, external reference, 50% clock duty cycle, AVDD, IOVDD = 1.8 V, external

1.6V reference, 5 pF output load, and –1-dBFS differential input, unless otherwise noted

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

ADC3542: 25 MSPS

NSD

SNR

Noise Spectral Density

Signal to noise ratio

f_IN= 1.1 MHz, A_IN= -20 dBFS

f_IN= 1.1 MHz

f_IN= 5 MHz

-150.7

79.0

78.5

79.0

78.5

12.8

90

dBFS/Hz

76.0

f_IN= 10 MHz

f_IN= 20 MHz

f_IN= 40 MHz

f_IN= 1.1 MHz

f_IN= 5 MHz

dBFS

bit

76.0

12.3

79

SINAD

ENOB

THD

Signal to noise and distortion ratio

f_IN= 10 MHz

f_IN= 20 MHz

f_IN= 40 MHz

f_IN= 1.1 MHz

f_IN= 5 MHz

Effective number of bits

f_IN= 10 MHz

f_IN= 20 MHz

f_IN= 40 MHz

f_IN= 1.1 MHz

f_IN= 5 MHz

95

Total Harmonic Distortion (First five

harmonics)

f_IN= 10 MHz

f_IN= 20 MHz

f_IN= 40 MHz

f_IN= 1.1 MHz

f_IN= 5 MHz

94

dBc

91

88

93

85

97

Spur free dynamic range including

second and third harmonic distortion

SFDR

f_IN= 10 MHz

f_IN= 20 MHz

f_IN= 40 MHz

f_IN= 1.1 MHz

f_IN= 5 MHz

95

dBc

93

89

101

103

102

99

90

Spur free dynamic range (excluding

HD2 and HD3)

Non HD2,3

f_IN= 10 MHz

f_IN= 20 MHz

f_IN= 40 MHz

dBFS

dBc

f₁= 3 MHz, f₂= 4 MHz, A_IN= -7 dBFS/

tone

95

IMD3

Two tone inter-modulation distortion

f₁= 10 MHz, f₂= 12 MHz, A_IN= -7

dBFS/tone

101

10

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6.9 Electrical Characteristics - AC Specifications ADC3543

Typical values are over the operating free-air temperature range, at T_A= 25°C, full temperature range is T_MIN= –40°C to

T_MAX= 105°C, ADC sampling rate = 65 MSPS, external reference, 50% clock duty cycle, AVDD, IOVDD = 1.8 V, external

1.6V reference, 5 pF output load, and –1-dBFS differential input, unless otherwise noted

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

ADC3543: 65 MSPS

NSD

SNR

Noise Spectral Density

Signal to noise ratio

f_IN= 1.1 MHz, A_IN= -20 dBFS

f_IN= 1.1 MHz

f_IN= 5 MHz

-154.7

79.0

78.5

78.0

79.0

78.5

78.0

12.8

12.5

12.0

92

dBFS/Hz

77.0

f_IN= 10 MHz

f_IN= 20 MHz

f_IN= 40 MHz

f_IN= 64 MHz

f_IN= 1.1 MHz

f_IN= 5 MHz

dBFS

bit

76.0

12.0

78

f_IN= 10 MHz

f_IN= 20 MHz

f_IN= 40 MHz

f_IN= 64 MHz

f_IN= 1.1 MHz

f_IN= 5 MHz

SINAD

ENOB

THD

Signal to noise and distortion ratio

f_IN= 10 MHz

f_IN= 20 MHz

f_IN= 40 MHz

f_IN= 64 MHz

f_IN= 1.1 MHz

f_IN= 5 MHz

Effective number of bits

89

f_IN= 10 MHz

f_IN= 20 MHz

f_IN= 40 MHz

f_IN= 64 MHz

f_IN= 1.1 MHz

f_IN= 5 MHz

84

Total Harmonic Distortion (First five

harmonics)

dBc

86

82

78

95

82

90

f_IN= 10 MHz

f_IN= 20 MHz

f_IN= 40 MHz

f_IN= 64 MHz

f_IN= 1.1 MHz

f_IN= 5 MHz

87

Spur free dynamic range including

second and third harmonic distortion

SFDR

dBc

88

85

80

100

101

99

93

f_IN= 10 MHz

f_IN= 20 MHz

f_IN= 40 MHz

f_IN= 64 MHz

Spur free dynamic range (excluding

HD2 and HD3)

Non HD2,3

IMD3

dBFS

dBc

97

96

91

f₁= 10 MHz, f₂= 12 MHz, A_IN= -7

dBFS/tone

Two tone inter-modulation distortion

92

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6.10 Timing Requirements

Typical values are over the operating free-air temperature range, at T_A= 25°C, full temperature range is T_MIN= –40°C to

T_MAX= 105°C, ADC sampling rate = 65 MSPS, 50% clock duty cycle, AVDD, IOVDD = 1.8 V, and –1-dBFS differential input,

unless otherwise noted

PARAMETER

ADC Timing Specifications

t_ADAperture delay

t_A

TEST CONDITIONS

MIN NOM MAX

UNIT

0.85

180

ns

fs

Aperture jitter

Square wave clock with fast edges

Serial CMOS output mode

t_J

Jitter on DCLKIN

± 50 ps (pk-pk)

Clock

cycle

Recory time from +6 dB overload condition

SNR within 1 dB of expected value

1

F_S= 10 Msps

F_S= 25 Msps

F_S= 65 Msps

-T_S/2

-T_S/4

Sampling

Clock

Period

Signal acquisition period, referenced to

sampling clock falling edge

t_ACQ

+T_S×

1/5

F_S= 10 Msps

F_S= 25 Msps

F_S= 65 Msps

Sampling

Clock

Period

Signal conversion period, referenced to

sampling clock falling edge

+T_S×

3/8

t_CONV

+T_S×

5/8

Bandgap reference enabled, single ended

clock

14.6

14

us

ms

us

Bandgap reference enabled, differential clock

Time to valid data after coming out of power

down. Internal reference.

Bandgap reference disabled, single ended

clock

1.6

Bandgap reference disabled, differential clock

1.6

Wake up

time

Bandgap reference enabled, single ended

clock

14.6

14

Bandgap reference enabled, differential clock

Time to valid data after coming out of power

down. External 1.6V reference.

Bandgap reference disabled, single ended

clock

1.13

ms

ps

Bandgap reference disabled, differential clock

t_S,SYNC

t_H,SYNC

Setup time for SYNC input signal

Hold time for SYNC input signal

500

600

Referenced to sampling clock rising edge

SDR CMOS

1

DDR CMOS

ADC

Latency

Clock

cycles

Signal input to data output

Serialized CMOS: 2-wire

Serialized CMOS: 1-wire

2

1

Real decimation by 2

21

22

23

Output

clock

cycles

Add.

Latency

Complex decimation by 2

Real or complex decimation by 4, 8, 16, 32

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6.10 Timing Requirements (continued)

Typical values are over the operating free-air temperature range, at T_A= 25°C, full temperature range is T_MIN= –40°C to

T_MAX= 105°C, ADC sampling rate = 65 MSPS, 50% clock duty cycle, AVDD, IOVDD = 1.8 V, and –1-dBFS differential input,

unless otherwise noted

PARAMETER

Interface Timing - SDR CMOS

t_PDPropagation delay: sampling clock falling edge to DCLK rising edge

TEST CONDITIONS

MIN NOM MAX

UNIT

3

-0.3

99.9

39.9

15.1

5

-0.2

99.9

39.9

15.3

7

ns

DCLK rising edge to output data delay

Data valid, SDR CMOS

Fout = 10 MSPS

Fout = 25 MSPS

Fout = 65 MSPS

Fout = 10 MSPS

Fout = 25 MSPS

Fout = 65 MSPS

t_CD

ns

t_DV

Data valid, SDR CMOS

ns

Data valid, SDR CMOS

Interface Timing - DDR CMOS

t_PDPropagation delay: sampling clock falling edge to DCLK rising edge

3

-0.3

-0.4

49.5

19.6

7.4

5

-0.2

49.9

19.8

7.5

7

ns

DCLK rising edge to output data delay

Data valid, DDR CMOS

Fout = 10 MSPS

Fout = 25 MSPS

Fout = 65 MSPS

Fout = 10 MSPS

Fout = 25 MSPS

Fout = 65 MSPS

t_CD

t_DV

Data valid, DDR CMOS

ns

Data valid, DDR CMOS

Interface Timing - SERIAL CMOS

Delay between sampling clock falling edge to

DCLKIN falling edge < 2.5ns.

T_DCLK= DCLK period

t_CDCLK= Sampling clock falling edge to

DCLKIN falling edge

2 +

3 +

4 +

T_DCLKT_DCLKT_DCLK

+

t_CDCLKt_CDCLKt_CDCLK

Propagation delay: sampling clock falling

edge to DCLK rising edge

t_PD

ns

Delay between sampling clock falling edge to

DCLKIN falling edge >= 2.5ns.

T_DCLK= DCLK period

t_CDCLK= Sampling clock falling edge to

DCLKIN falling edge

2 +

3 +

4 +

t_CDCLKt_CDCLKt_CDCLK

Fout = 10 MSPS, D11/12 = 70 MBPS

Fout = 25 MSPS, D11/12 = 175 MBPS

0.04

0.01

0.18

DCLK rising edge to output data delay,

2-wire serial CMOS

t_CD

ns

DCLK rising edge to output data delay,

1-wire serial CMOS

Fout = 10 MSPS, D11 = 140 MBPS

0.05

0.19

Fout = 10 MSPS, D11/12 = 70 MBPS

Fout = 25 MSPS, D11/12 = 175 MBPS

Fout = 10 MSPS, D11 = 140 MBPS

13.4

5.2

13.8

5.5

Data valid, 2-wire serial CMOS

t_DV

Data valid, 1-wire serial CMOS

6.2

6.8

SERIAL PROGRAMMING INTERFACE (SCLK, SEN, SDIO) - Input

f_CLK(SCLK)Serial clock frequency

20

MHz

ns

t_SU(SEN)

t_H(SEN)

t_SU(SDIO)

t_H(SDIO)

SEN to rising edge of SCLK

SEN from rising edge of SCLK

SDIO to rising edge of SCLK

SDIO from rising edge of SCLK

10

9

17

9

SERIAL PROGRAMMING INTERFACE (SDIO) - Output

t_(OZD)

t_(ODZ)

t_(OD)

SDIO tri-state to driven

3.9

3.4

3.9

10.8

14

SDIO data to tri-state

ns

SDIO valid from falling edge of SCLK

10.8

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6.11 Typical Characteristics: ADC3541

Typical values at T_A= 25 °C, ADC sampling rate = 10 MSPS, A_IN= –1 dBFS differential input, AVDD = IOVDD

= 1.8 V, 65k FFT, 1.6 V external reference, 5 pF load capacitance, unless otherwise noted.

SNR = 79.3 dBFS, SFDR = 85 dBc, Non HD23 = 97 dBFS

A_IN= - 7 dBFS/tone, IMD3 = 94 dBc

图6-1. Single Tone FFT at F_IN= 1.1 MHz

图6-2. Two Tone FFT at F_IN= 3,4 MHz

A_IN= -20 dBFS/tone, IMD3 = 87 dBc

spacer

图6-3. Two Tone FFT at F_IN= 3,4 MHz

图6-4. AC Performance vs Input Frequency

spacer

F_IN= 1.1 MHz

图6-5. ENOB vs Input Frequency

图6-6. AC Performance vs Input Amplitude

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6.11 Typical Characteristics: ADC3541 (continued)

F_IN= 1.1 MHz

Differential (Diff) vs Single ended (SE) clock, F_IN= 1.1 MHz

图6-7. AC Performance vs Sampling Rate

图6-8. AC Performance vs Clock Amplitude

F_IN= 1.1 MHz

图6-9. AC Performance vs AVDD

图6-10. AC Performance vs VCM vs Temperature

F_IN= 1.1 MHz

图6-11. INL vs Code

图6-12. DNL vs Code

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6.11 Typical Characteristics: ADC3541 (continued)

图6-13. DC Histogram

Pulse Input = 1 MHz

图6-14. Pulse Response

13

10.5

8

25

Bypass

/2 real

I_AVDD, ADC3541/42

I_IOVDD, SDR

I_IOVDD, DDR

I_IOVDD, 2-w

I_IOVDD, 1-w

/4 real

/8 real

/32 real

/4 complex

/8 complex

/32 complex

20

15

10

5

5.5

3

0

5

10

15

20

25

5

10

15

20

25

Sampling Rate (MSPS)

F_IN= 1 MHz, 2-w serial CMOS

F_IN= 1 MHz

图6-16. I_IOVDDCurrent vs Decimation

图6-15. Current vs Sampling Rate

12

SDR, 5 pF

DDR, 5 pF

SDR, 15 pF

SDR, 22 pF

DDR, 15 pF

DDR, 22 pF

10

8

6

4

2

5

10

15

20

25

Sampling Rate (MSPS)

F_IN= 1 MHz

图6-17. I_IOVDDCurrent vs Output Load

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6.12 Typical Characteristics: ADC3542

Typical values at T_A= 25 °C, ADC sampling rate = 25 MSPS, A_IN= –1 dBFS differential input, AVDD = IOVDD

= 1.8 V, 65k FFT, 1.6 V external reference, 5 pF load capacitance, unless otherwise noted.

SNR = 79.4 dBFS, SFDR = 89 dBc, Non HD23 = 99 dBFS

SNR = 79.3 dBFS, SFDR = 99 dBc, Non HD23 = 99 dBFS

图6-18. Single Tone FFT at F_IN= 1.1 MHz

图6-19. Single Tone FFT at F_IN= 10 MHz

A_IN= -10 dBFS, SNR = 79.9 dBFS, SFDR = 98 dBc, Non

HD23 = 93 dBFS

SNR = 78.6 dBFS, SFDR = 88 dBc, Non HD23 = 98 dBFS

图6-21. Single Tone FFT at F_IN= 40 MHz

图6-20. Single Tone FFT at F_IN= 10 MHz

A_IN= -7 dBFS/tone, IMD3 = 90 dBc

A_IN= -20 dBFS/tone, IMD3 = 87 dBc

图6-22. Two Tone FFT at F_IN= 3, 4 MHz

图6-23. Two Tone FFT at F_IN= 3, 4 MHz

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6.12 Typical Characteristics: ADC3542 (continued)

0

-20

-40

-60

-80

-100

-120

-140

0

5

10

12.5

Input Frequency (MHz)

A_IN= -7 dBFS/tone, IMD3 = 100 dBc

图6-24. Two Tone FFT at F_IN= 10, 12 MHz

图6-25. AC Performance vs Input Frequency

图6-26. ENOB vs Input Frequency

F_IN= 5 MHz

图6-27. AC Performance vs Input Amplitude

F_IN= 1.1 MHz

Differential (Diff) vs Single ended (SE) clock, F_IN= 5 MHz

图6-28. AC Performance vs Sampling Rate

图6-29. AC Performance vs Clock Amplitude

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6.12 Typical Characteristics: ADC3542 (continued)

F_IN= 1.1 MHz

图6-30. AC Performance vs AVDD

图6-31. AC Performance vs VCM vs Temperature

F_IN= 1.1 MHz

图6-32. INL vs Code

图6-33. DNL vs Code

图6-34. DC Histogram

Pulse Input = 1 MHz

图6-35. Pulse Response

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6.12 Typical Characteristics: ADC3542 (continued)

13

10.5

8

25

Bypass

/4 real

/8 real

/32 real

/2 real

I_AVDD, ADC3541/42

I_IOVDD, SDR

I_IOVDD, DDR

I_IOVDD, 2-w

I_IOVDD, 1-w

/4 complex

/8 complex

/32 complex

20

15

10

5

5.5

3

0

5

10

15

20

25

5

10

15

20

25

Sampling Rate (MSPS)

F_IN= 1 MHz, 2-w serial CMOS

F_IN= 1 MHz

图6-37. I_IOVDDCurrent vs Decimation

图6-36. Current vs Sampling Rate

12

SDR, 5 pF

DDR, 5 pF

SDR, 15 pF

SDR, 22 pF

DDR, 15 pF

DDR, 22 pF

10

8

6

4

2

5

10

15

20

25

Sampling Rate (MSPS)

F_IN= 1 MHz

图6-38. I_IOVDDCurrent vs Output Load

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6.13 Typical Characteristics: ADC3543

Typical values at T_A= 25 °C, ADC sampling rate = 65 MSPS, A_IN= –1 dBFS differential input, AVDD = IOVDD

= 1.8 V, 65k FFT, 1.6 V external reference, 5 pF load capacitance, unless otherwise noted.

SNR = 79.3 dBFS, SFDR = 91 dBc, Non HD23 = 100 dBFS

SNR = 79.2 dBFS, SFDR = 87 dBc, Non HD23 = 102 dBFS

图6-39. Single Tone FFT at F_IN= 1.1 MHz

图6-40. Single Tone FFT at F_IN= 10 MHz

A_IN= -10 dBFS, SNR = 79.7 dBFS, SFDR = 93 dBc, Non

HD23 = 105 dBFS

SNR = 78.5 dBFS, SFDR = 85 dBc, Non HD23 = 97 dBFS

图6-42. Single Tone FFT at F_IN= 40 MHz

图6-41. Single Tone FFT at F_IN= 10 MHz

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6.13 Typical Characteristics: ADC3543 (continued)

SNR = 78.0 dBFS, SFDR = 69 dBc, Non HD23 = 94 dBFS

SNR = 77.1 dBFS, SFDR = 77 dBc, Non HD23 = 87 dBFS

图6-43. Single Tone FFT at F_IN= 64 MHz

图6-44. Single Tone FFT at F_IN= 100 MHz

A_IN= -7 dBFS/tone, IMD3 = 100 dBc

A_IN= -20 dBFS/tone, IMD3 = 93 dBc

图6-45. Two Tone FFT at F_IN= 10, 12 MHz

图6-46. Two Tone FFT at F_IN= 10, 12 MHz

spacer

A_IN= -7 dBFS/tone, IMD3 = 89 dBc

图6-48. AC Performance vs Input Frequency

图6-47. Two Tone FFT at F_IN= 35,40 MHz

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6.13 Typical Characteristics: ADC3543 (continued)

F_IN= 5 MHz

spacer

图6-50. AC Performance vs Input Amplitude

图6-49. ENOB vs Input Frequency

F_IN= 5 MHz

Differential (Diff) vs Single ended (SE) clock, F_IN= 5 MHz

图6-51. AC Performance vs Sampling Rate

图6-52. AC Performance vs Clock Amplitude

F_IN= 5 MHz

图6-53. AC Performance vs AVDD

图6-54. AC Performance vs VCM vs Temperature

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6.13 Typical Characteristics: ADC3543 (continued)

F_IN= 5 MHz

图6-55. INL vs Code

图6-56. DNL vs Code

图6-57. DC Histogram

Pulse Input = 1 MHz

图6-58. Pulse Response

F_IN= 5 MHz

图6-59. AC Performance vs Clock Duty Cycle

图6-60. Current vs Sampling Rate

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6.13 Typical Characteristics: ADC3543 (continued)

F_IN= 5 MHz, 2-w serial CMOS

F_IN= 5 MHz, DDC Bypass

图6-61. I_IOVDDCurrent vs Decimation

图6-62. I_IOVDDCurrent vs Output Interface

F_IN= 5 MHz, DDC Bypass

图6-63. I_IOVDDCurrent vs Output Load

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7 Parameter Measurement Information

Sample N

Sample N+1

Input Signal

t_AD

t_PD

Sampling

Clock

t_ACQ

t_CONV

t_CD

T_DCLK

DCLK

t_DV

D2..15

Sample N

Sample N-1

图7-1. Timing Diagram: SDR CMOS

Sample N

Sample N+1

Input Signal

t_AD

t_PD

Sampling

Clock

t_ACQ

t_CONV

T_DCLK

t_CD

DCLK

t_DV

D11

D12

D13

D12

D6

D5

D13

D12

D6

D13

D12

D5

D16/

FCLK

D8

D7

D1

D0

D8

D7

D1

D0

D8

D7

D17

Sample N-2

Sample N-1

Sample N

图7-2. Timing Diagram: DDR CMOS (default bit mapper)

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Sample N

Sample N+1

Input Signal

t_AD

t_PD

Sampling

Clock

t_ACQ

t_CONV

t_CDCLK

DCLKIN

(D3)

DCLK

FCLK

T_DCLK

t_CD

t_DV

D13 D11

D12 D10

D9

D8

D7

D6

D5

D4

D3

D1

D0

D13 D11

D12 D10

D9

D8

D7

D5

D4

D3

D2

D1

D0

D12

D11

D2

D6

Sample N-2

Sample N-1

图7-3. Timing Diagram: Serial CMOS 2-wire (default bit mapper)

Sample N

Sample N+1

Input Signal

t_AD

t_PD

Sampling

Clock

t_ACQ

t_CONV

t_CDCLK

DCLKIN

(D3)

DCLK

FCLK

D11

t_CD

T_DCLK

t_DV

D2

D1

D0

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Sample N-2

Sample N-1

图7-4. Timing Diagram: Serial CMOS 1-wire (default bit mapper)

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8 Detailed Description

8.1 Overview

The ADC354x is a low noise, ultra-low power 14-bit high-speed ADC family supporting sampling rates from 10 to

65 Msps. It offers good DC precision together with IF sampling support which makes it suited for a wide range of

applications. The ADC354x is equipped with an on-chip internal reference option but it also supports the use of

an external, high precision 1.6 V voltage reference or an external 1.2 V reference which is buffered and gained

up internally. Because of the inherent low latency architecture, the digital output result is available after only one

clock cycle. Single ended as well as differential input signaling is supported.

An optional programmable digital down converter enables external anti-alias filter relaxation as well as output

data rate reduction. The digital filter provides a 32-bit programmable NCO and supports both real or complex

decimation.

The ADC354x family uses a SDR or DDR as well as a 2-wire or 1-wire serial CMOS interface to output the data

offering lowest power digital interface together with the flexibility to minimize the number of digital interconnects.

The ADC354x includes a digital output formatter which supports output resolutions from 14 to 20-bit. The device

is part of a pin-to-pin compatible family with different speed grades.

The device features and control options can be set up either through pin configurations or via SPI register writes.

8.2 Functional Block Diagram

REFBUF

VREF

1.2V REF

Digital Downconverter

NCO

ADC

14bit

N

AIN

FCLK

DCLKIN

0.95V

VCM

DCLK

Dig I/F

CMOS

D0..15

CLK

Control

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8.3 Feature Description

8.3.1 Analog Input

The analog inputs of ADC354x are intended to be driven differentially. Both AC coupling and DC coupling of the

analog inputs is supported. The analog inputs are designed for an input common mode voltage of 0.95 V which

must be provided externally on each input pin. DC-coupled input signals must have a common mode voltage that

meets the device input common mode voltage range.

The equivalent input network diagram is shown in 图8-1. All four sampling switches, on-resistance shown in red,

are in same position (open or closed) simultaneously.

AVDD

Sampling Switch

0.32 pF

1 ꢀ

125 ꢀ

2 nH

xINP/

xINM

24 ꢀ

1.4 pF

0.15 pF

0.6 pF

GND

0.6 pF

GND

6.4 pF

7 ꢀ

GND

5 ꢀ

0.7 pF

1.6 pF

GND

图8-1. Equivalent Input Network

8.3.1.1 Analog Input Bandwidth

图 8-2 shows the analog full power input bandwidth of the ADC with a 50 Ω differential termination. The -3 dB

bandwidth is approximately 900 MHz and the useful input bandwidth with good AC performance is approximately

120 MHz.

The equivalent input resistance R_INand input capacitance C_INvs frequency are shown in 图8-3.

0

-1

-2

-3

-4

-5

-6

10

100

Input Frequency (MHz)

1000

ADC3

图8-3. Equivant R_IN, C_INvs Input Frequency

图8-2. ADC Analog Input bandwidth response

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8.3.1.2 Analog Front End Design

The ADC354x is an unbuffered ADC and thus a passive kick-back filter is recommended to absorb the glitch

from the sampling operation. Depending on if the input is driven by a balun or a differential amplifier with low

output impedance, a termination network may be needed. Additionally a passive DC bias circuit is needed in AC-

coupled applications which can be combined with the termination network.

8.3.1.2.1 Sampling Glitch Filter Design

The front end sampling glitch filter is designed to optimize the SNR and HD3 performance of the ADC. The filter

performance is dependent on input frequency and therefore the following filter designs are recommended for

different input frequency ranges as shown in 图8-4 and 图8-5.

33 ꢀ

10 ꢀ

180nH

100 pF

Termination

33 ꢀ

180nH

10 ꢀ

图8-4. Sampling glitch filter example for input frequencies from DC to 30 MHz

33 ꢀ

10 ꢀ

100pF

120nH

82 pF

Termination

33 ꢀ

10 ꢀ

100pF

120nH

图8-5. Sampling glitch filter example for input frequencies from 30 to 70 MHz

8.3.1.2.2 Single Ended Input

The ADC can be configured to operate with single ended input instead of differential using just the positive signal

input. This operating mode must be enabled via SPI register write (address 0xE). The single ended signal is

connected to the negative ADC input and both the positive and negative input need to be biased to VCM as

shown in 图8-6.

C

0.56V

0V

0.56V

V_CM

INM

-0.56V

R

V_CM

INP

C

图8-6. Single ended analog input: AC coupled (left) and DC coupled (right)

The signal swing is now reduced by 6-dB (single ended input with 1.125 Vpp vs differential 2.25 Vpp), and the

resulting SNR is reduced by 3-dB.

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8.3.1.2.3 Analog Input Termination and DC Bias

Depending on the input drive circuitry, a termination network and/or DC biasing needs to be provided.

8.3.1.2.3.1 AC-Coupling

The ADC354x requires external DC bias using the common mode output voltage (VCM) of the ADC together

with the termination network as shown in 图 8-7. The termination is located within the glitch filter network. When

using a balun on the input, the termination impedance has to be adjusted to account for the turns ratio of the

transformer. When using an amplifier, the termination impedance can be adjusted to optimize the amplifier

performance.

Glitch Filter

Termination

33 ꢀ

1 uF

10 ꢀ

180nH

25 ꢀ

100 pF

VCM

0.1 …F

25 ꢀ

33 ꢀ

1 uF

VCM

180nH

10 ꢀ

图8-7. AC-Coupling: termination network provides DC bias (glitch filter example for DC - 30 MHz)

8.3.1.2.3.2 DC-Coupling

In DC coupled applications the DC bias needs to be provided from the fully differential amplifier (FDA) using

VCM output of the ADC as shown in 图 8-8. The glitch filter in this case is located between the anti-alias filter

and the ADC. No termination may be needed if amplifier is located close to the ADC or if the termination is part

of the anti-alias filter.

Glitch Filter

33 ꢀ

10 ꢀ

180nH

100 pF

AAF (Anti

Alias Filter)

33 ꢀ

VCM

180nH

10 ꢀ

图8-8. DC-Coupling: DC bias provided by FDA (glitch filter example for DC - 30 MHz)

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8.3.1.3 Auto-Zero Feature

The ADC354x includes an internal auto-zero front end amplifier circuit which improves the 1/f flicker noise. This

auto-zero feature is enabled by default for the ADC3541/2 and can be enabled using SPI register writes for the

ADC3543 (register 0x11, D0). The following 4M point FFTs compare auto-zero feature enabled vs disabled.

图8-9. F_S= 10 MSPS, F_IN= 1.1 MHz

图8-10. F_S= 10 MSPS, F_IN= 1.1 MHz

图8-12. F_S= 25 MSPS, F_IN= 1.1 MHz

图8-14. F_S= 65 MSPS, F_IN= 5 MHz

图8-11. F_S= 25 MSPS, F_IN= 1.1 MHz

图8-13. F_S= 65 MSPS, F_IN= 5 MHz

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8.3.2 Clock Input

In order to maximize the ADC SNR performance, the external sampling clock should be low jitter and differential

signaling with a high slew rate. This is especially important in IF sampling applications. For less jitter sensitive

applications, the ADC354x provides the option to operate with single ended signaling which saves additional

power consumption.

8.3.2.1 Single Ended vs Differential Clock Input

The ADC354x can be operated using a differential or a single ended clock input where the single ended clock

consumes less power consumption. However clock amplitude impacts the ADC aperture jitter and consequently

the SNR. For maximum SNR performance, a large clock signal with fast slew rates needs to be provided.

• Differential Clock Input: The clock input can be AC coupled externally. The ADC354x provides internal biasing

for that use case.

• Single Ended Clock Input: This mode needs to be configured using SPI register (0x0E, D2 and D0) or with

the REFBUF pin. In this mode there is no internal clock biasing and thus the clock input needs to be DC

coupled around a 0.9V center. The unused input needs to be AC coupled to ground.

1.8V

CLKP

0.9V

0V

+

-

5kO

VCM

0.9V

5kO

CLKM

图8-15. External and internal connection using differential (left) and single ended (right) clock input

8.3.2.2 Signal Acquisition Time Adjust

The ADC354x includes a register (DLL PDN (0x11, D2) which increases the signal acquisition time window for

clock rates below 40 MSPS from 25% to 50% of the clock period. Increasing the sampling time provides a longer

time for the driving amplifier to settle out the signal which can improve the SNR performance of the system.

备注

This register needs to be set for the 65 MSPS speed grade (ADC3543) when operating at sampling

rates below 40 MSPS. For the 10 and 25 MSPS device speed grades the sampling time is already set

to T_S/2.

When powering down the DLL, the acquisition time will track the clock duty cycle (50% is recommended).

表8-1. Acquisition time vs DLL PDN setting

SAMPLING CLOCK F_S(MSPS)

DLL PDN (0x11, D2)

ACQUISITION TIME (t_ACQ)

65

0

1

T_S/ 4

T_S/ 2

≤40

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8.3.3 Voltage Reference

The ADC354x provides three different options for supplying the voltage reference to the ADC. An external 1.6 V

reference can be directly connected to the VREF input; a voltage 1.2 V reference can be connected to the

REFBUF input using the internal gain buffer or the internal 1.2 V reference can be enabled to generate a 1.6V

reference voltage. For best performance, the reference noise should be filtered by connecting a 10 uF and a 0.1

uF ceramic bypass capacitor to the VREF pin. The internal reference circuitry of the ADC354x is shown in 图

8-16.

备注

The voltage reference mode can be selected using SPI register writes or by using the REFBUF pin

(default) as a control pin (节 8.5.1). If the REFBUF pin is not used for configuration, the REFBUF pin

should be connected to AVDD (even though the REFBUF pin has a weak internal pullup to AVDD) and

the voltage reference option has to be selected using the SPI interface.

AINP

AINM

0.95V

VCM

VREF

(1.6V)

x1.33

REFBUF

(1.2V)

VREF1.2

REFGND

图8-16. Different voltage reference options for ADC354x

8.3.3.1 Internal voltage reference

The 1.6 V reference for the ADC can be generated internal using the on-chip 1.2V reference along with the

internal gain buffer. A 10 uF and a 0.1 uF ceramic bypass capacitor (C_VREF) should be connected between the

VREF and REFGND pins as close to the pins as possible.

xINP

xINM

0.95V

VCM

VREF

(1.6V)

x1.33

C_VREF

REFBUF

(1.6V)

VREF1.2

REFGND

图8-17. Internal reference

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8.3.3.2 External voltage reference (VREF)

For highest accuracy and lowest temperature drift, the VREF input can be directly connected to an external 1.6 V

reference. A 10 uF and a 0.1 uF ceramic bypass capacitor (C_VREF) connected between the VREF and REFGND

pins and placed as close to the pins as possible is recommended. The load current from the external reference

is about 1 mA.

Note: The internal reference is also used for other functions inside the device, therefore the reference amplifier

should only be powered down in power down state but not during normal operation.

xINP

xINM

0.95V

VCM

VREF

(1.6V)

Reference

1.6V

REFBUF

(1.2V)

x1.33

C_VREF

VREF1.2

REFGND

图8-18. External 1.6 V reference

8.3.3.3 External voltage reference with internal buffer (REFBUF)

The ADC354x is equipped with an on-chip reference buffer that also includes gain to generate the 1.6V

reference voltage from an external 1.2 V reference. A 10 uF and a 0.1 uF ceramic bypass capacitor (C_VREF

)

between the VREF and REFGND pins and a 10 uF and a 0.1 uF ceramic bypass capacitor (C_REFBUF) between

the REFBUF and REFGND pins are recommended. Both capacitors should be placed as close to the pins as

possible. The load current from the external reference is less than 100 uA.

xINP

xINM

0.95V

VCM

VREF

(1.6V)

x1.33

REFBUF

(1.2V)

Reference

1.2V

VREF1.2

C_REFBUF

C_VREF

REFGND

图8-19. External 1.2 V reference using internal reference buffer

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8.3.4 Digital Down Converter

The ADC354x includes an optional on-chip digital down conversion (DDC) decimation filter that can be enabled

via SPI register setting. It supports complex decimation by 2, 4, 8, 16 and 32 using a digital mixer and a 32-bit

numerically controlled oscillator (NCO) as shown in 图8-20. Furthermore it supports a mode with real decimation

where the complex mixer is bypassed (NCO should be set to 0 for lowest power consumption) and the digital

filter acts as a low pass filter.

Internally the decimation filter calculations are performed with a 20-bit resolution in order to avoid any SNR

degradation due to quantization noise. The output formatter (节8.3.5.4) truncates to the selected resolution prior

to outputting the data on the digital interface.

NCO

32bit

Filter

I

Q

I

Q

Digital

Interface

N

ADC

SYNC

图8-20. Internal Digital Decimation Filter

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8.3.4.1 Digital Filter Operation

The complex decimation operation is illustrated with an example in 图 8-21. First the input signal (and the

negative image) are frequency shifted by the NCO frequency as shown on the left. Next a digital filter is applied

(centered around 0 Hz) and the output data rate is decimated - in this example the output data rate F_S,OUT= F_S/8

with a Nyquist zone of F_S/16. During the complex mixing the spectrum (signal and noise) is split into real and

complex parts and thus the amplitude is reduced by 6-dB. In order to compensate this loss, there is a 6-dB

digital gain option in the decimation filter block that can be enabled via SPI write.

Input Signal

(Alias)

Shifted Input

Signal (Alias)

-F_IN+ F_NCO

Shifted Input Signal

Negative Image

Input Signal

Negative Image

Decimation

by 8

F_IN+ F_NCO

0

-FS/16

FS/16

FS/2

-FS/2

FS/2

F_NCO

NCO Tuning Range

图8-21. Complex decimation illustration

The real decimation operation is illustrated with an example in 图 8-22. There is no frequency shift happening

and only the real portion of the complex digital filter is exercised. The output data rate is decimated - a

decimation of 8 would result in an output data rate F_S,OUT= F_S/8 with a Nyquist zone of F_S/16.

During the real mixing the spectrum (signal and noise) amplitude is reduced by 3-dB. In order to compensate this

loss, there is a 3-dB digital gain option in the decimation filter block that can be enabled via SPI write.

Input Signal

Decimation by

32

Decimation by

16

Decimation by 2

Decimation by 4

Decimation by 8

FS/2

FS/16

FS/8

FS/4

FS/32

FS/64

图8-22. Real decimation illustration

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8.3.4.2 FS/4 Mixing with Real Output

In this mode, the output after complex decimation gets mixed with FS/4 (FS = output data rate in this case).

Instead of a complex output with the input signal centered around 0 Hz, the output is transmitted as a real output

at twice the data rate and the signal is centered around FS/4 (Fout/4) as illustrated in 图8-23.

In this example, complex decimation by 8 is used. The output data is transmitted as a real output with an output

rate of Fout = FS'/4 (FS' = ADC sampling rate). The input signal is now centered around FS/4 (Fout/4) or FS'/16.

F_IN

F_NCO

- F_IN+ F_NCO

-F_IN+ F_NCO+ FS/4

/8

FS/4 mix

Fout/4 mix

Complex

Decimation /8

0

FS‘/2

FS/16

FS‘/2

FS/8

0

FS/2

图8-23. FS/4 Mixing with real output

8.3.4.3 Numerically Controlled Oscillator (NCO) and Digital Mixer

The decimation block is equipped with a 32-bit NCO and a digital mixer to fine tune the frequency placement

prior to the digital filtering. The oscillator generates a complex exponential sequence of:

e^jωn(default) or e^–jωn

(1)

where: frequency (ω) is specified as a signed number by the 32-bit register setting

The complex exponential sequence is multiplied with the real input from the ADC to mix the desired carrier to a

frequency equal to f_IN+ f_NCO. The NCO frequency can be tuned from –F_S/2 to +F_S/2 and is processed as a

signed, 2s complement number. After programming a new NCO frequency, the MIXER RESTART register bit or

SYNC pin has to be toggled for the new frequency to get active. Additionally the ADC354x provides the option

via SPI to invert the mixer phase.

The NCO frequency setting is set by the 32-bit register value given and calculated as:

NCO frequency = 0 to + F_S/2: NCO = f_NCO× 2³²/ F_S

NCO frequency = -F_S/2 to 0: NCO = (f_NCO+ F_S) × 2³²/ F_S

where:

• NCO = NCO register setting (decimal value)

• f_NCO= Desired NCO frequency (MHz)

• F_S= ADC sampling rate (MSPS)

The NCO programming is further illustrated with this example:

• ADC sampling rate F_S= 65 MSPS

• Input signal f_IN= 10 MHz

• Desired output frequency f_OUT= 0 MHz

For this example there are four ways to program the NCO and achieve the desired output frequency as shown in

表8-2.

表8-2. NCO value calculations example

Alias or negative image

f_IN= –10 MHz

f_NCO

NCO Value

660764199

3634203097

Mixer Phase

Frequency translation for f_OUT

f_NCO= 10 MHz

f_NCO= –10 MHz

f_OUT= f_IN+ f_NCO= –10 MHz +10 MHz = 0 MHz

f_OUT= f_IN+ f_NCO= 10 MHz + (–10 MHz) = 0 MHz

as is

f_IN= 10 MHz

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表8-2. NCO value calculations example (continued)

Alias or negative image

f_NCO

NCO Value

Mixer Phase

Frequency translation for f_OUT

f_IN= 10 MHz

f_NCO= 10 MHz

660764199

f_OUT= f_IN–f_NCO= 10 MHz –10 MHz = 0 MHz

inverted

f_OUT= f_IN–f_NCO= –10 MHz –(–10 MHz) = 0

3634203097

f_IN= –10 MHz

f_NCO= –10 MHz

MHz

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8.3.4.4 Decimation Filter

The ADC354x supports complex decimation by 2, 4, 8, 16 and 32 with a pass-band bandwidth of ~ 80% and a

stopband rejection of at least 85 dB. 表 8-3 gives an overview of the pass-band bandwidth of the different

decimation settings with respect to ADC sampling rate F_S. In real decimation mode the output bandwidth is half

of the complex bandwidth.

表8-3. Decimation Filter Summary and Maximum Available Output Bandwidth

REAL/COMPLEX

DECIMATION

SETTING N

OUTPUT

BANDWIDTH

OUTPUT RATE

(F_S= 65 MSPS)

OUTPUT BANDWIDTH

(F_S= 65 MSPS)

OUTPUT RATE

2

4

F_S/ 2 complex

F_S/ 4 complex

F_S/ 8 complex

F_S/ 16 complex

F_S/ 32 complex

F_S/ 2 real

0.8 × F_S/ 2

0.8 × F_S/ 4

0.8 × F_S/ 8

0.8 × F_S/ 16

0.8 × F_S/ 32

0.4 × F_S/ 2

0.4 × F_S/ 4

0.4 × F_S/ 8

0.4 × F_S/ 16

0.4 × F_S/ 32

32.5 MSPS complex

16.25 MSPS complex

8.125 MSPS complex

4.0625 MSPS complex

2.03125 MSPS complex

32.5 MSPS

26 MHz

13 MHz

Complex

8

6.5 MHz

16

32

2

3.25 MHz

1.625 MHz

13 MHz

4

F_S/ 4 real

16.25 MSPS

6.5 MHz

Real

8

F_S/ 8 real

8.125 MSPS

3.25 MHz

1.625 MHz

0.8125 MHz

16

32

F_S/ 16 real

4.0625 MSPS

F_S/ 32 real

2.03125 MSPS

The decimation filter responses are normalized to the ADC sampling clock frequency F_Sand illustrated in 图

8-25 to 图8-34. They are interpreted as follows:

Each figure contains the filter pass-band, transition band(s) and alias or stop-band(s) as shown in 图 8-24. The

x-axis shows the offset frequency (after the NCO frequency shift) normalized to the ADC sampling rate F_S.

For example, in the divide-by-4 complex setup, the output data rate is F_S/ 4 complex with a Nyquist zone of F_S/

8 or 0.125 × F_S. The transition band (colored in blue) is centered around 0.125 × F_Sand the alias transition band

is centered at 0.375 × F_S. The stop-bands (colored in red), which alias on top of the pass-band, are centered at

0.25 × F_Sand 0.5 × F_S. The stop-band attenuation is greater than 85 dB.

0

Passband

Transition Band

-20

Alias Band

Attn Spec

Filter

-40

-60

Transition

Bands

Bands that alias on top

of signal band

Pass Band

-80

-100

-120

0

0.1

0.2

0.3

0.4

0.5

Normalized Frequency (Fs)

图8-24. Interpretation of the Decimation Filter Plots

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0

0.1

0.09

0.08

0.07

0.06

0.05

0.04

0.03

0.02

0.01

0

Passband

Transition Band

Alias Band

Attn Spec

Transition Band

Alias Band

Attn Spec

-20

-40

-60

-0.01

-0.02

-0.03

-0.04

-0.05

-0.06

-0.07

-0.08

-0.09

-0.1

-80

-100

-120

0

0.05

0.1

0.15

0.2

0.25

0.3

0.35

0.4

0.45

0.5

0

0.025 0.05 0.075

0.1

0.125 0.15 0.175

0.2

0.225 0.25

Normalized Frequency (Fs)

Decb

图8-25. Decimation by 2 complex frequency

图8-26. Decimation by 2 complex passband ripple

response

0

Passband

Transition Band

Alias Band

Passband

Transition Band

Alias Band

Attn Spec

-0.01

-0.02

-20

-40

Attn Spec

-0.03

-0.04

-0.05

-0.06

-0.07

-0.08

-0.09

-0.1

-60

-80

-100

-120

0

0.05

0.1

0.15

0.2

0.25

0.3

0.35

0.4

0.45

0.5

0

0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1 0.11 0.12

Normalized Frequency (Fs)

Decb

图8-27. Decimation by 4 complex frequency

图8-28. Decimation by 4 complex passband ripple

response

0

-0.08

Passband

Transition Band

Alias Band

Passband

-0.081

-0.082

-0.083

-0.084

-0.085

-0.086

-0.087

-0.088

-0.089

-0.09

Transition Band

Alias Band

Attn Spec

-20

-40

Attn Spec

-60

-0.091

-0.092

-0.093

-0.094

-0.095

-0.096

-0.097

-0.098

-0.099

-0.1

-80

-100

-120

0

0.05

0.1

0.15

0.2

0.25

0.3

0.35

0.4

0.45

0.5

0

0.006 0.012 0.018 0.024 0.03 0.036 0.042 0.048 0.054 0.06

Normalized Frequency (Fs)

Decb

图8-29. Decimation by 8 complex frequency

图8-30. Decimation by 8 complex passband ripple

response

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0

-20

-0.1

-0.11

-0.12

-0.13

-0.14

-0.15

-0.16

-0.17

-0.18

-0.19

-0.2

Passband

Transition Band

Alias Band

Attn Spec

Transition Band

Alias Band

Attn Spec

-40

-60

-80

-100

-120

0

0.05

0.1

0.15

0.2

0.25

0.3

0.35

0.4

0.45

0.5

0

0.003 0.006 0.009 0.012 0.015 0.018 0.021 0.024 0.027 0.03

Normalized Frequency (Fs)

Decb

图8-31. Decimation by 16 complex frequency

图8-32. Decimation by 16 complex passband

response

ripple response

0

-0.2

Passband

Transition Band

Alias Band

Passband

Transition Band

Alias Band

Attn Spec

-0.205

-0.21

-20

-40

Attn Spec

-0.215

-0.22

-60

-0.225

-0.23

-80

-0.235

-0.24

-100

-120

-0.245

-0.25

0

0.05

0.1

0.15

0.2

0.25

0.3

0.35

0.4

0.45

0.5

0

0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018 0.02

Normalized Frequency (Fs)

Decb

图8-33. Decimation by 32 complex frequency

图8-34. Decimation by 32 complex passband

response

ripple response

8.3.4.5 SYNC

The PDN/SYNC pin can be used to synchronize multiple devices using an external SYNC signal. The PDN/

SYNC pin can be configured via SPI (SYNC EN bit) from power down to synchronization functionality and is

latched in by the rising edge of the sampling clock as shown in 图8-35.

CLK

t_S,SYNC

t_H,SYNC

SYNC

图8-35. External SYNC timing diagram

The synchronization signal is only required when using the decimation filter - either using the SPI SYNC register

or the PDN/SYNC pin. It resets internal clock dividers used in the decimation filter and aligns the internal clocks

as well as I and Q data within the same sample. If no SYNC signal is given, the internal clock dividers is not be

synchronized, which can lead to a fractional delay across different devices. The SYNC signal also resets the

NCO phase and loads the new NCO frequency (same as the MIXER RESTART bit).

When trying to resynchronize during operation, the SYNC toggle should occur at 64*K clock cycles, where K is

an integer. This provids the phase continuity of the clock divider.

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8.3.4.6 Output Formatting with Decimation

8.3.4.6.1 Parallel CMOS

In parallel CMOS mode, the ADC354x device supports complex decimation output with DDR CMOS interface

and real output with SDR and DDR CMOS interface as shown in 图8-36 (complex decimation) and 图8-37 (real

decimation). In this illustration the output format is selected to 16-bit.

D16..1

DCLK

D16

(MSB)

D15

D3

D2

D1

Sample

N_I

Sample

N_Q

图8-36. Output Data Format in Complex Decimation (default bit mapper)

表 8-4 illustrates the output interface data rate along with the corresponding DCLK frequency based on complex

decimation setting (N).

Furthermore the table shows an actual lane rate example with complex decimation by 4.

表8-4. Parallel CMOS Data Rate Examples with Complex Decimation

REAL/COMPLEX

DECIMATION

SETTING

ADC SAMPLING RATE

DCLK

DOUT (MHz)

N

4

F_S

F_Sx 2 / N

32.5 MHz

F_Sx 4 / N

65 MHz

Complex

65 MHz

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SDR

DDR CMOS

D17..10

D16..1

DCLK

D16

(MSB)

D10

D11

D7

D6

D15

D14

D7

D15

D6

D14

D15

D3

D2

D1

D15

D16

D17

D2

D1

D0

D10

D9

D2

D1

D0

D10

D9

D8

Sample

A₀

Sample

A₁

Sample

A₀

Sample

A₁

图8-37. Output Data Format in Real Decimation (default bit mapper)

表 8-4 illustrates the output interface data rate along with the corresponding DCLK frequency based on real

decimation setting (M).

Furthermore the table shows an actual lane rate example with complex decimation by 4.

表8-5. Parallel CMOS Data Rate Examples with Decimation

REAL/COMPLEX

DECIMATION

SETTING

SDR/DDR

CMOS

ADC SAMPLING RATE

DCLK

DOUT

SDR

DDR

SDR

DDR

F_S/ M

M

4

F_S

F_S/ M

F_Sx 2 / M

16.25 MHz

32.5 MHz

Real

65 MHz

16.25 MHz

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8.3.4.6.2 Serialized CMOS Interface

In serialized CMOS mode, the ADC354x device supports complex decimation output 图 8-38 and real

decimation output 图8-39. The examples are shown for 16-bit output for 2-wire (8x serialization) and 1-wire (16x

serialization).

FCLK

A_I

D9

A_I

D7

A_I

D5

A_I

D3

A_I

D1

A_QA_Q

D13 D11

A_Q

D9

A_Q

D7

A_Q

D5

A_Q

D3

A_Q

D1

A_Q

D15

D12

D11

D15 D13 D11

2-Wire

8x Serialization

A_I

D8

A_I

D6

A_I

D4

A_I

D2

A_I

D0

A_QA_Q

D12 D10

A_Q

D8

A_Q

D6

A_Q

D4

A_Q

D2

A_Q

D0

A_Q

D14

D14 D12 D10

DCLK

FCLK

D11

1-Wire

16x Serialization

A_I<15:0>

A_Q<15:0>

DCLK

图8-38. Output Data Format in Complex Decimation

表 8-6 illustrates the output interface data rate along with the corresponding DCLK/DCLKIN and FCLK

frequencies based on output resolution (R), number of serial CMOS lanes (L) and complex decimation setting

(N).

Furthermore the table shows an actual lane rate example for the 2- and 1- wire interface, 16-bit output resolution

and complex decimation by 16.

表8-6. Serial CMOS Lane Rate Examples with Complex Decimation and 16-bit Output Resolution

DECIMATION

SETTING

ADC SAMPLING

RATE

OUTPUT

RESOLUTION

# of WIRES

FCLK

DCLKIN, DCLK

DOUT

N

F_S

R

L

2

1

F_S/ N

[DOUT] / 2

32.5 MHz

65 MHz

F_Sx 2 x R / L / N

65 MHz

16

65 MSPS

16

4.0625 MHz

130 MHz

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FCLK

A₀

D9

A₀

D7

A₀

D5

A₀

D3

A₀

D1

A₁

D11

A₁

D9

A₁

D7

A₁

D5

A₁

D3

A₁

D1

D12

D15 D13 D11

D15 D13

2-Wire

8x Serialization

A₀

D14 D12 D10

A₀

D8

A₀

D6

A₀

D4

A₀

D2

A₀

D0

A₁

D14 D12 D10

A₁

D8

A₁

D6

A₁

D4

A₁

D2

A₁

D0

D11

DCLK

FCLK

D11

1-Wire

16x Serialization

A₀<15:0>

A₁<15:0>

DCLK

图8-39. Output Data Format in Real Decimation

表 8-7 illustrates the output interface data rate along with the corresponding DCLK/DCLKIN and FCLK

frequencies based on output resolution (R), number of serial CMOS lanes (L) and real decimation setting (M).

Furthermore the table shows an actual lane rate example for the 2- and 1-wire interface, 16-bit output resolution

and real decimation by 16.

表8-7. Serial CMOS Lane Rate Examples with Real Decimation and 16-bit Output Resolution

DECIMATION

SETTING

ADC SAMPLING

RATE

OUTPUT

RESOLUTION

# of WIRES

FCLK

DCLKIN, DCLK

DOUT

F_S/ M / 2 (L = 2)

F_S/ M (L = 1)

M

F_S

R

L

[DOUT] / 2

F_Sx R / L / M

2

1

2.03125 MHz

4.0625 MHz

16.25 MHz

32.5 MHz

65 MHz

16

65 MSPS

16

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8.3.5 Digital Interface

The ADC354x family supports two different CMOS output modes - parallel SDR/DDR output and serialized

CMOS output formats.

8.3.5.1 Parallel CMOS Output

The low power CMOS interface supports single data rate (SDR) and double data rate (DDR) output options. In

SDR and DDR output mode the output clock is generated inside the ADC354x. The different interface options

are configured using SPI register writes.

8.3.5.2 Serialized CMOS output

In this mode the output data is serialized and transmitted over 2 or 1 wires. Due to CMOS output speed limitation

this mode is only available for reduced output data rates. This mode is similar to the multi-SPI interface.

8.3.5.2.1 SDR Output Clocking

The ADC354x provides a SDR output clocking option for all serial CMOS output modes (including decimation)

which is enabled using the SPI interface. In serial CMOS mode by default the data is output on rising and falling

edge of DCLK. In SDR clocking mode, DCLKIN has to be twice as fast as the default DCLKIN so that the output

data are clocked out only on DCLK rising edge.

Internally DCLKIN is divided by 2 for data processing and this operation can add 1 extra clock cycle latency to

the ADC latency.

Latency (2 clock cycles)

Sample N+1

Sample N+2

Sample N

Sample N+3

Sample N+6

Sample N+4

Sample N+5

t_AD

t_PD

Continous

Clock

DCLKIN

SDR

DCLK

SDR

t_CD

FCLK

D12

D11

Sample N-1

Sample N

Sample N+1

Sample N+2

图8-40. SDR Output Clocking

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8.3.5.3 Output Data Format

The output data can be configured to two's complement (default) or offset binary formatting using SPI register

writes (register 0x8F and 0x92). 表 8-8 provides an overview for minimum and maximum output codes for the

two formatting options. The actual output resolution is set by the output bit mapper.

表8-8. Overview of minimum and maximum output codes vs resolution for different formatting

Two's Complement (default)

Offset Binary

RESOLUTION (BIT)

14

16

18

20

14

16

18

20

V_IN,MAX

0

0x1FFF

0x7FFF

0x1FFFF

0x7FFFF

0x3FFF

0x2000

0xFFFF

0x8000

0x3FFFF

0x20000

0xFFFFF

0x80000

0x0000

0x2000

0x00000

V_IN,MIN

0x8000

0x20000

0x80000

0x0000

0x00000

8.3.5.4 Output Formatter

The digital output interface utilizes a flexible output bit mapper 图 8-41. The bit mapper takes the 14-bit output

directly from the ADC or from digital filter block and reformats it to a resolution of 14, 16, 18 or 20-bit. With

parallel output format the maximum output resolution supported is 16-bit. With serial CMOS output the output

serialization factor gets adjusted accordingly for 2- and 1-wire interface mode. The maximum output data rate

can not be exceeded independently of output resolution and serialization factor.

DIG

I/F

Output

Formatter

14/16/18/

20-bit

NCO

TEST

Output

Bit Mapper

PATTERN

N

图8-41. Interface output bit mapper

表 8-9 provides an overview for the resulting serialization factor depending on output resolution and output

modes. Note that the DCLKIN frequency needs to be adjusted accordingly as well. Changing the output

resolution to 16-bit, 2-wire mode for example would result in DCLKIN = F_S* 4 instead of * 3.5.

The output bit mapper can be used for bypass and decimation filter.

表8-9. Serialization factor vs output resolution for different output modes

OUTPUT

RESOLUTION

Interface SERIALIZATION

FCLK

DCLKIN

DCLK

D0/D1

2-Wire

1-Wire

2-Wire

1-Wire

2-Wire

1-Wire

2-Wire

1-Wire

7x

14x

8x

F_S/2

F_S

F_S* 3.5

F_S* 7

F_S* 3.5

F_S* 7

F_S* 14

F_S* 8

14-bit (default)

F_S/2

F_S

F_S* 4

16-bit

18-bit

20-bit

16x

9x

F_S* 8

F_S* 16

F_S* 9

F_S/2

F_S

F_S* 4.5

F_S* 9

F_S* 4.5

F_S* 9

18x

10x

20x

F_S* 18

F_S* 10

F_S* 20

F_S/2

F_S

F_S* 5

F_S* 10

The programming sequence to change the output interface and/or resolution from default settings is shown in 节

8.3.5.6.

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8.3.5.5 Output Bit Mapper

The output bit mapper allows to change the output bit order for any selected interface mode.

DIG

I/F

Output

Formatter

14/16/18/

20-bit

NCO

TEST

PATTERN

Output

Bit Mapper

N

图8-42. Output Bit Mapper

It is a two step process to change the output bit mapping and assemble the output data bus:

1. In parallel interface mode, the maximum output resolution is 18-bit, in serial interface mode the maximum

output resolution is 20-bit. Each output bit of either channel has a unique identifier bit as shown in the 表

8-10. The MSB starts with bit D19 –depending on output resolution chosen the LSB would be D6 (14-bit) to

D0 (20-bit). The ‘previous sample’is only needed in 2-w mode.

2. The bit mapper is then used to assemble the output sample. The following sections detail how to remap both

a parallel and a serial output format.

表8-10. Unique identifier of each data bit

Bit

D19 (MSB)

D18

D17

D16

D15

D14

D13

D12

D11

D10

D9

Previous sample (2w only)

Current sample

0x6D

0x6C

0x67

0x2D

0x2C

0x27

0x26

0x25

0x24

0x1F

0x1E

0x1D

0x1C

0x17

0x16

0x15

0x14

0x0F

0x0E

0x0D

0x0C

0x07

0x06

0x66

0x65

0x64

0x5F

0x5E

0x5D

0x5C

0x57

D8

0x56

D7

0x55

D6

0x54

D5

0x4F

D4

0x4E

0x4D

0x4C

0x47

D3

D2

D1

D0 (LSB)

0x46

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In parallel SDR mode, a data bit (with unique identifier) needs to be assigned to each output pin using the

register addresses as shown in 图8-43. The example on the right shows the 14-bit output data bus remapped to

reverse order to where the MSB starts on pin D2 instead of pin D15.

DCLK

D2

D3

D13 (0x3B, 0x6D)

D12 (0x3C, 0x6C)

D11 (0x3D, 0x67)

D10 (0x3E, 0x66)

D9 (0x3F, 0x65)

D8 (0x40, 0x64)

D7 (0x41, 0x5F)

D6 (0x42, 0x5E)

D5 (0x43, 0x5D)

D4 (0x4A, 0x5C)

D3 (0x49, 0x57)

D2 (0x48, 0x56)

D1 (0x47, 0x55)

D0 (0x46, 0x54)

D4

D5

D6

D7

D8

D9

D10

D11

D12

D13

D14

D15

图8-43. SDR output mapping (left) and example (right)

In parallel DDR mode, a data bit (with unique identifier) needs to be assigned to each output pin for both the

rising and the falling edge of the DCLK using the register addresses as shown on the left of 图8-44. D9 and D10

are used for 16 and 18-bit output. The example on the right shows the 14-bit output data bus remapped to where

the MSB starts on D17 instead of D11.

DCLK

D0 (0x72, 0x54)

D1 (0x71, 0x55)

D2 (0x70, 0x56)

D3 (0x6F, 0x57)

D4 (0x6E, 0x5C)

D5 (0x6D, 0x5D)

D6 (0x6C, 0x5E)

D11

D12

D13

D14

D15

D16

D17

D7 (0x4A, 0x5F)

D8 (0x49, 0x64)

D9 (0x48, 0x65)

D10 (0x47, 0x66)

D11 (0x46, 0x67)

D12 (0x45, 0x6C)

D13 (0x44, 0x6D)

图8-44. DDR output timing mapping (left) and example (right)

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In the serial output mode, a data bit (with unique identifier) needs to be assigned to each location within the

serial output stream. There are a total of 40 addresses (0x39 to 0x60). When using complex decimation, the

output bit mapper is applied to both the “I”and the “Q”sample.

2-wire mode: in this mode both the current and the previous sample have to be used in the address space as

shown in 图 8-45 below. The address order is different for 14/18-bit and 16/20-bit. Note: there are unused

addresses between samples for resolution less than 20-bit (grey back ground), which can be skipped if not used.

14-bit

16-bit 18-bit 20-bit

14-bit

16-bit 18-bit 20-bit

0x55 0x56 0x53 0x54 0x51 0x52 0x4F 0x50 0x4D 0x4E

0x56 0x55 0x54 0x53 0x52 0x51 0x50 0x4F 0x4E 0x4D

14/18-bit 0x5F 0x60 0x5D 0x5E 0x5B 0x5C 0x59 0x5A 0x57 0x58

0x60 0x5F 0x5E 0x5D 0x5C 0x5B 0x5A 0x59 0x58 0x57

D12

D11

16/20-bit

14/18-bit 0x4B 0x4C 0x49 0x4A 0x47 0x48 0x45 0x46 0x43 0x44 0x41 0x42 0x3F 0x40 0x3D 0x3E 0x3B 0x3C 0x39 0x3A

16/20-bit 0x4C 0x4B 0x4A 0x49 0x48 0x47 0x46 0x45 0x44 0x43 0x42 0x41 0x40 0x3F 0x3E 0x3D 0x3C 0x3B 0x3A 0x39

Previous Sample

Current Sample

图8-45. 2-wire output bit mapper

In the following example (图 8-46), the 16-bit 2-wire serial output is reordered to where pin D12 carries the 8

MSB and pin D11 carries 8 LSBs.

Previous Sample

Current Sample

D19_A

(0x60

0x2D)

D18_A

(0x5F

0x2C)

D17_A

(0x5E

0x27)

D16_A

(0x5D

0x26)

D15_A

(0x5C

0x25)

D14_A

(0x5B

0x24)

D13_A

(0x5A

0x1F)

D12_A

(0x59

0x1E)

D19_A

(0x56

0x6D)

D18_A

(0x55

0x6C)

D17_A

(0x54

0x67)

D16_A

(0x53

0x66)

D15_A

(0x52

0x65)

D14_A

(0x51

0x64)

D13_A

(0x50

0x5F)

D12_A

(0x4F

0x5E)

D12

D11

D11_A

(0x4C

0x1D)

D10_A

(0x4B

0x1C)

D9_A

(0x4A

0x17)

D8_A

(0x49

0x16)

D7_A

(0x48

0x15)

D6_A

(0x47

0x14)

D5_A

(0x46

0x0F)

D4_A

(0x45

0x0E)

D11_A

(0x42

0x5D)

D10_A

(0x41

0x5C)

D9_A

(0x40

0x57)

D8_A

(0x39

0x56)

D7_A

(0x38

0x55)

D6_A

(0x37

0x54)

D5_A

(0x36

0x4F)

D4_A

(0x35

0x4E)

图8-46. Example: 2-wire output mapping

1-wire mode: Only the ‘current’sample needs to programmed in the address space.

14-bit

16-bit

18-bit

20-bit

D11

(default)

0x4C 0x4B 0x4A 0x49 0x48 0x47 0x46 0x45 0x44 0x43 0x42 0x41 0x40 0x3F 0x3E 0x3D 0x3C 0x3B 0x3A 0x39

图8-47. 1-wire output bit mapping

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8.3.5.6 Output Interface/Mode Configuration

The following sequence summarizes all the relevant registers for changing the output interface and/or enabling

the decimation filter. Steps 1 and 2 must come first since the E-Fuse load reset the SPI writes, the remaining

steps can come in any order.

表8-11. Configuration steps for changing interface or decimation

STEP

FEATURE

ADDRESS

DESCRIPTION

Select the output interface bit mapping depending on resolution and output interface.

Output Resolution

14-bit

SDR

DDR

2-wire

0x2B

0x4B

0x2B

0x4B

1-wire

0x6C

1

0x07

0xC8

0xA9

16-bit

18-bit

N/A

20-bit

Load the output interface bit mapping using the E-fuse loader (0x13, D0). Program register 0x13

to 0x01, wait ~ 1ms so that bit mapping is loaded properly followed by 0x13 0x00

2

0x13

3

4

0x0A/B/C

0x18

Power down relevant CMOS output buffers to avoid contention.

For serial CMOS modes, DCLKIN EN (D4) needs to be enabled.

In serial CMOS, configure the FCLK registers based on bypass/decimation and # of lanes used.

FCLK SRC

(D7)

FCLK DIV

(D4)

Bypass/Decimation

SCMOS

2-wire

1-wire

2-wire

1-wire

0

1

0

5

0x19

Bypass/ Real Decimation

Output

Interface

Complex Decimation

6

7

0x1B

0x1F

Select the output interface resolution using the bit mapper (D5-D3).

For serial CMOS modes, DCLKIN EN (D6) and DCLK OB EN (D4) need to be enabled.

In serial CMOS, select the FCLK pattern for decimation for proper duty cycle output of the FCLK.

Output

Decimation

2-wire

1-wire

Resolution

14-bit

16-bit

18-bit

20-bit

14-bit

16-bit

18-bit

20-bit

0xFE000

0xFF000

0xFF800

0xFFC00

0x20

0x21

0x22

Real Decimation

8

use default

Complex Decimation

0xFFFFF

9

0x39..0x72 Change output bit mapping if desired. This also works with the default interface selection.

10

11

12

0x24

0x25

Enable the decimation filter

Configure the decimation filter

0x2A/B/C/D Program the NCO frequency for complex decimation (can be skipped for real decimation)

Configure the complex output data stream (set both bits to 0 for real decimation)

Decimation

Filter

Serial CMOS

2-wire

OP-Order (D4)

Q-Delay (D3)

13

14

0x27

1

0

1

1-wire

0x26

Set the mixer gain and toggle the mixer reset bit to update the NCO frequency.

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8.3.5.6.1 Configuration Example

The following is a step by step programming example to configure the ADC354x to complex decimation by 8 with

1-wire serial CMOS and 16-bit output.

1. 0x07 (address) 0x6C (load bit mapper configuration for 16-bit output with 1-wire serial CMOS)

2. 0x13 0x01, wait 1 ms, 0x13 0x00 (load e-fuse)

3. 0x0A 0xFF, 0x0B 0xFF, 0x0C 0xFD (power down unused CMOS output buffers to avoid contention)

4. 0x18 0x10 (DCLKIN EN for serial CMOS mode)

5. 0x19 0x82 (configure FCLK)

6. 0x1B 0x88 (select 16-bit output resolution)

7. 0x1F 0x50 (DCLKIN EN for serial CMOS mode)

8. 0x20 0xFF, 0x21 0xFF, 0x22 0x0F (configure FCLK pattern)

9. 0x24 0x06 (enable decimation filter)

10. 0x25 0x30 (configure complex decimation by 8)

11. 0x2A/B/C/D (program NCO frequency)

12. 0x27/0x2E 0x08 (configure Q-delay register bit)

13. 0x26 0xAA (set digital mixer gain to 6-dB and toggle the mixer update)

8.3.6 Test Pattern

In order to enable in-circuit testing of the digital interface, the following test patterns are supported and enabled

via SPI register writes (0x14/0x15/0x16). The test pattern generator is located after the decimation filter as

shown in 图 8-48. In decimation mode (real and complex), the test patterns replace the output data of the DDC -

however channel A controls the test patterns for both channels.

DIG

I/F

Output

Formatter

14/16/18/

20-bit

NCO

TEST

Output

Bit Mapper

PATTERN

N

图8-48. Test Pattern Generator

• RAMP Pattern: The step size is set in the CUSTOM PAT register according to the native ADC resolution.

When selecting a higher output resolution then the additional LSBs will still be 0 in RAMP pattern mode.

– 00001: 18-bit output resolution

– 00100: 16-bit output resolution

– 10000: 14-bit output resolution

• Custom Pattern: Configured in the CUSTOM PAT register

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8.4 Device Functional Modes

8.4.1 Normal operation

In normal operating mode, the entire ADC full scale range gets converted to a digital output with 14-bit

resolution. The output is available in as little as 1 clock cycle on the digital CMOS outputs.

8.4.2 Power Down Options

A global power down mode can be enabled via SPI as well as using the power down pin (PDN/SYNC). There is

an internal pull-down 21 kΩ resistor on the PDN/SYNC input pin and the pin is active high - so the pin needs to

be pulled high externally to enter global power down mode.

The SPI register map provides the capability to enable/disable individual blocks directly or via PDN pin mask in

order to trade off power consumption vs wake up time as shown in 表8-12.

REFBUF

VREF

AIN

1.2V REF

Digital Downconverter

NCO

ADC

N

Dig I/F

CLK

图8-49. Power Down Configurations

表8-12. Overview of Power Down Options

PDN

via SPI

Mask for

Global PDN

Feature -

Default

Power

Impact

Wake-up

time

Function/ Register

ADC

Comment

ADC is included in Global PDN

automatically

Yes

-

Enabled

Should only be powered down in power

down state.

Reference gain amplifier

Internal 1.2V reference

Yes

~ 0.4 mA

~3 us

Internal/external reference selection is

available through SPI and REFBUF pin.

External ref

~ 1-3.5 mA

~3 ms

Yes

Single ended clock input saves ~ 1 mA

compared to differential.

Some programmability is available

through the REFBUF pin.

Differential

clock

Clock buffer

Yes

~ 1 mA

varies

n/a

Depending on output interface mode,

unused output drivers can be powered

down for maximum power savings

Output interface drivers

Decimation filter

Yes

-

Enabled

Disabled

n/a

see electrical

table

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8.5 Programming

The device is primarily configured and controlled using the serial programming interface (SPI) however it can

operate in a default configuration without requiring the SPI interface. Furthermore the power down function as

well as internal/external reference configuration is possible via pin control (PDN/SYNC and REFBUF pin).

备注

The power down command (via PIN or SPI) only goes in effect with the ADC sampling clock present.

After initial power up, the default operating configuration for each device is shown in 表8-13.

表8-13. Default device configuration after power up

Feature

Signal Input

Auto-zero

ADC3541

ADC3542

Differential

Enabled

ADC3543

Enabled

Disabled

Clock Input

Reference

Decimation

Interface

Differential

External

DDC bypass

SDR CMOS

2s compliment

Output Format

8.5.1 Configuration using PINs only

The ADC voltage reference can be selected using the REFBUF pin. Even though there is an internal 100 kΩ

pull-up resistor to AVDD, the REFBUF pin should be set to a voltage externally and not left floating.

表8-14. REFBUF voltage levels control voltage reference selection

REFBUF VOLTAGE

VOLTAGE REFERENCE OPTION

CLOCKING OPTION

Digital Interface

> 1.7 V (Default)

External reference

Differential clock input

SDR CMOS

External 1.2 V input on REFBUF pin using internal

gain buffer

1.2 V (1.15-1.25V)

Differential clock input

SDR CMOS

0.5 - 0.7V

< 0.1V

Internal reference

Differential clock input

SDR CMOS

Single ended clock input

Serial CMOS 2-wire

8.5.2 Configuration Using the SPI Interface

The device has a set of internal registers that can be accessed by the serial interface formed by the SEN (serial

interface enable), SCLK (serial interface clock) and SDIO (serial interface data input/output) pins. Serially shifting

bits into the device is enabled when SEN is low. Serial data input are latched at every SCLK rising edge when

SEN is active (low). The serial data are loaded into the register at every 24th SCLK rising edge when SEN is low.

When the word length exceeds a multiple of 24 bits, the excess bits are ignored. Data can be loaded in multiples

of 24-bit words within a single active SEN pulse. The interface can function with SCLK frequencies from 12 MHz

down to low speeds (of a few hertz) and also with a non-50 % SCLK duty cycle.

8.5.2.1 Register Write

The internal registers can be programmed following these steps:

1. Drive the SEN pin low

2. Set the R/W bit to 0 (bit A15 of the 16-bit address) and bits A[14:12] in address field to 0.

3. Initiate a serial interface cycle by specifying the address of the register (A[11:0]) whose content is written and

4. Write the 8-bit data that are latched in on the SCLK rising edges

图8-50 show the timing requirements for the serial register write operation.

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Register Address <11:0>

A7 A6 A5 A4

Register Data <7:0>

R/W

SDIO

0

A11 A10

A9

A8

A3

A2

A1

A0

D7

D6

D5

D4

D3

D2

D1

D0

t_H,SDIO

t_SCLK

t_S,SDIO

SCLK

SEN

t_S,SEN

t_H,SEN

RESET

图8-50. Serial Register Write Timing Diagram

8.5.2.2 Register Read

The device includes a mode where the contents of the internal registers can be read back using the SDIO pin.

This readback mode can be useful as a diagnostic check to verify the serial interface communication between

the external controller and the ADC. The procedure to read the contents of the serial registers is as follows:

1. Drive the SEN pin low

2. Set the R/W bit (A15) to 1. This setting disables any further writes to the registers. Set A[14:12] in address

field to 0.

3. Initiate a serial interface cycle specifying the address of the register (A[11:0]) whose content must be read

4. The device launches the contents (D[7:0]) of the selected register on the SDIO pin on SCLK falling edge

5. The external controller can capture the contents on the SCLK rising edge

Register Address <11:0>

A7 A6 A5 A4

Register Data <7:0>

D5 D4 D3 D2

R/W

1

t_OZD

A0

t_OD

SDIO

0

A11 A10

A9

A8

A3

A2

A1

D7

D6

D1

D0

SCLK

SEN

t_ODZ

图8-51. Serial Register Read Timing Diagram

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8.6 Register Map

表8-15. Register Map Summary

REGISTER

ADDRESS

REGISTER DATA

A[11:0]

0x00

D7

D6

D5

D4

0

D3

0

D2

D1

0

D0

0

RESET

0x07

OP IF MAPPER

0

OP IF EN

OP IF SEL

PDN

REFAMP

PDN

GLOBAL

0x08

0

PDN CLKBUF

0

PDN A

1

0x0A

0x0B

0x0C

CMOS OB DIS [7:0]

CMOS OB DIS [15:8]

CMOS OB DIS [23:16]

MASK

REFSYS A

MASK

CLKBUF

MASK

REFAMP

MASK BG

DIS

0x0D

0x0E

0

SYNC PIN

EN

SPI SYNC SPI SYNC EN

0

REF CTRL

REF SEL

SE CLK EN

0x11

0x13

0x14

0x15

0x16

0x18

0x19

0x1B

0x1E

0x1F

0x20

0x21

0x22

0x24

0x25

0x26

0

SE A

0

DLL PDN

0

AZ EN

E-FUSE LD

CUSTOM PAT [7:0]

CUSTOM PAT [15:8]

0

TEST PAT A

CUSTOM PAT [17:16]

0

DCLKIN EN

FCLK DIV

0

FCLK SRC

MAPPER EN

0

20B EN

0

FCLK EN

BIT MAPPER RES

0

CMOS DCLK DEL

0

LOW DR EN DCLKIN EN

0

DCLK OB EN

2X DCLK

FCLK PAT [7:0]

FCLK PAT [15:8]

0

FCLK PAT [19:16]

0

DIG BYP

DDC EN

0

DECIMATION

MIX RES A

REAL OUT

0

MIX PHASE

0

MIX GAIN A

FS/4 MIX A

FS/4 MIX PH

A

0x27

0

OP ORDER A

Q-DEL A

0

0x2A

0x2B

NCO A [7:0]

NCO A [15:8]

NCO A [23:16]

0x2C

0x2D

NCO A [31:24]

0x39..0x72

0x8F

OUTPUT BIT MAPPER

0

FORMAT A

0

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8.6.1 Detailed Register Description

图8-52. Register 0x00

7

0

6

0

5

0

4

3

2

0

1

0

RESET

R/W-0

表8-16. Register 0x00 Field Descriptions

Bit

Field

0

Type

R/W

Reset

Description

7-1

0

Must write 0

RESET

This bit resets all internal registers to the default values and self

clears to 0.

图8-53. Register 0x07

7

6

5

4

3

2

1

0

OP IF MAPPER

R/W-0

0

OP IF EN

R/W-0

OP IF SEL

R/W-0

表8-17. Register 0x07 Field Descriptions

Bit

Field

Type

Reset

Description

7-5

OP IF MAPPER

R/W

000

This register contains the proper output interface bit mapping for

the different interfaces. The interface bit mapping is internally

loaded from e-fuses and also requires a fuse load command to

go into effect (0x13, D0). Register 0x07 along with the E-Fuse

Load (0x13, D0) needs to be loaded first in the programming

sequence since the E-Fuse load resets the SPI writes.

After initial reset the default output interface variant is loaded

automatically from fuse internally. However when reading back

this register reads 000 until a value is written using SPI.

001: 2-wire, 18 and 14-bit

010: 2-wire, 16-bit

011: 1-wire

100: 0.5-wire

101: DDR

110: SDR

4

3

0

R/W

0

Must write 0

OP IF EN

OP IF SEL

0

Enables changing the default output interface mode (D2-D0).

2-0

000

Selects the output interface mode. OP IF EN (D3) needs to be

enabled also.After initial reset the default output interface is

loaded automatically from fuse internally. However when reading

back this register reads 000 until a value is written using SPI.

000: SDR CMOS

001: DDR CMOS

011: 2-wire

100: 1-wire

101: 0.5-wire

others: not used

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图8-54. Register 0x08

7

0

6

0

5

4

3

2

1

0

PDN CLKBUF PDN REFAMP

R/W-0 R/W-0

0

PDN A

R/W-0

PDN GLOBAL

R/W-0

表8-18. Register 0x08 Field Descriptions

Bit

7-6

5

Field

Type

R/W

Reset

Description

0

Must write 0

PDN CLKBUF

Powers down sampling clock buffer

0: Clock buffer enabled

1: Clock buffer powered down

4

PDN REFAMP

R/W

0

Powers down internal reference gain amplifier

0: REFAMP enabled

1: REFAMP powered down

3

2

0

R/W

0

Must write 0

PDN A

Powers down ADC channel A

0: ADC channel A enabled

1: ADC channel A powered down

1

0

1

R/W

1

0

Must write 1

PDN GLOBAL

Global power down via SPI

0: Global power disabled

1: Global power down enabled. Power down mask (register

0x0D) determines which internal blocks are powered down.

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图8-55. Register 0x0A, B, C

7

6

5

4

3

2

1

0

CMOS OB DIS [23:0]

R/W-0 R/W-0

R/W-0

表8-19. Register 0x0A/B/C Field Descriptions

Bit

Field

CMOS OB DIS [23:0]

Type

Reset

Description

7:0

R/W

0

These register bits power down the individual CMOS output

buffers. See 表8-20 for the actual bit to pin mapping. Unused

pins should be powered down (ie set to 1) for maximum power

savings.

There is a separate control to enable the DCLKIN buffer in

register 0x1F (D6) and 0x18 (D4). DCLK output buffer is

powered down using register 0x1F (D4).

NOTE: When using serial CMOS interface the CMOS output

buffer (D3) has to be powered down because it shares the pin

with DCLKIN.

0: Output buffer enabled

1: Output buffer powered down

表8-20. Output buffer enable bit mapping vs output interface mode

ADDRESS (HEX)

BIT

D7

D6

D5

D4

D3

D2

D1

D0

PIN NAME

SDR CMOS

DDR CMOS

SCMOS 2-w

SCMOS 1-w

D7

-

D7

-

D7

-

D4

D3

D2

D1

D0

D4

D3

D2

D1

D0

0x60

D13

D14

D15

-

0x0A

-

DCLKIN

-

Register setting

0x7F

0xFF

D7

D6

D5

D4

D3

D2

D1

D0

D13

D14

D15

FCLK

-

FCLK

0x0B

-

D8

0x1E

D10

D9

D6

D5

-

D8

0xFE

D10

D9

D6

D5

-

Register setting

0xEF

D7

D6

D5

D4

D3

D2

D1

D0

D10

D9

D6

D5

-

0x0C

-

D11

-

D11

D12

D11

D12

0x0C

D11

D12

0x0C

D11

D12

0xFC

Register setting

0xFD

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图8-56. Register 0x0D (PDN GLOBAL MASK)

7

0

6

0

5

4

3

2

1

0

MASK REFSYS

A

0

MASK CLKBUF MASK REFAMP MASK BG DIS

R/W-0

R/W-0 R/W-0 R/W-0

R/W-0

表8-21. Register 0x0D Field Descriptions

Bit

7

Field

Type

R/W

Reset

Description

Must write 0

0

6

5

MASK REFSYS A

Global power down mask control for internal bias currents, ADC

channel A.

0: Internal bias currents will get powered down when global

power down is exercised.

1: Internal bias currents will NOT get powered down when global

power down is exercised.

4

3

0

R/W

0

Must write 0

MASK CLKBUF

Global power down mask control for sampling clock input buffer.

0: Clock buffer will get powered down when global power down

is exercised.

1: Clock buffer will NOT get powered down when global power

down is exercised.

2

1

MASK REFAMP

MASK BG DIS

R/W

0

Global power down mask control for reference amplifier.

0: Reference amplifier will get powered down when global power

down is exercised.

1: Reference amplifier will NOT get powered down when global

power down is exercised.

Global power down mask control for internal 1.2V bandgap

voltage reference. Setting this bit reduces power consumption in

global power down mode but increases the wake up time. See

the power down option overview.

0: Internal 1.2V bandgap voltage reference will NOT get

powered down when global power down is exercised.

1: Internal 1.2V bandgap voltage reference will get powered

down when global power down is exercised.

0

R/W

0

Must write 0

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图8-57. Register 0x0E

7

6

5

4

3

2

1

0

SYNC PIN EN

R/W-0

SPI SYNC

R/W-0

SPI SYNC EN

R/W-0

0

REF CTL

R/W-0

REF SEL

SE CLK EN

R/W-0

表8-22. Register 0x0E Field Descriptions

Bit

Field

SYNC PIN EN

Type

Reset

Description

7

R/W

0

This bit controls the functionality of the SYNC/PDN pin.

0: SYNC/PDN pin exercises global power down mode when pin

is pulled high.

1: SYNC/PDN pin issues the SYNC command when pin is

pulled high.

6

5

SPI SYNC

R/W

0

Toggling this bit issues the SYNC command using the SPI

register write. SYNC using SPI must be enabled as well (D5).

This bit doesn't self reset to 0.

0: Normal operation

1: SYNC command issued.

SPI SYNC EN

This bit enables synchronization using SPI instead of the

SYNC/PDN pin.

0: Synchronization using SPI register bit disabled.

1: Synchronization using SPI register bit enabled.

4

3

0

R/W

0

Must write 0

REF CTL

This bit determines if the REFBUF pin controls the voltage

reference selection or the SPI register (D2-D1).

0: The REFBUF pin selects the voltage reference option.

1: Voltage reference is selected using SPI (D2-D1) and single

ended clock using D0.

2-1

REF SEL

R/W

00

Selects of the voltage reference option. REF CTRL (D3) must be

set to 1.

00: Internal reference

01: External voltage reference (1.2V) using internal reference

buffer (REFBUF)

10: External voltage reference

11: not used

0

SE CLK EN

0

Selects single ended clock input and powers down the

differential sampling clock input buffer. REF CRTL (D3) must be

set to 1.

0: Differential clock input

1: Single ended clock input

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图8-58. Register 0x11

7

0

6

0

5

4

3

2

1

0

SE A

R/W-0

0

DLL PDN

R/W-0

AZ EN

R/W-0

表8-23. Register 0x11 Field Descriptions

Bit

7-6

5

Field

Type

R/W

Reset

Description

0

Must write 0

SE A

This bit enables single ended analog input, channel A. In this

mode the SNR reduces by 3-dB.

0: Differential input

1: Single ended input.

4-3

2

0

R/W

0

Must write 0

DLL PDN

This register applies ONLY to the ADC3543. It powers down the

internal DLL, which is used to adjust the sampling time. This

register must be enabled when operating at sampling rates

below 40 MSPS. When DLL PDN bit is enabled the sampling

time is directly dependent on sampling clock duty cycle (with a

50/50 duty the sampling time is T_S/2).

0: Sampling time is T_S/ 4

1: Sampling time is T_S/2 (only for sampling rates below 40

MSPS).

1

0

R/W

0

Must write 0

AZ EN

0/1

This bit enables the internal auto-zero circuitry. It is enabled by

default for the ADC3541/42 and disabled for the ADC3543.

0: Auto-zero disabled

1: Auto-zero enabled

图8-59. Register 0x13

7

0

6

0

5

0

4

3

2

0

1

0

E-FUSE LD

R/W-0

表8-24. Register 0x13 Field Descriptions

Bit

Field

Type

R/W

Reset

Description

7-1

0

Must write 0

E-FUSE LD

This register bit loads the internal bit mapping for different

interfaces. After setting the interface in register 0x07, this E-

FUSE LD bit needs to be set to 1 and reset to 0 for loading to go

into effect. Register 0x07 along with the E-Fuse Load (0x13, D0)

needs to be loaded first in the programming sequence since the

E-Fuse load resets the SPI writes.

0: E-FUSE LOAD set

1: E-FUSE LOAD reset

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图8-60. Register 0x14/15/16

7

6

5

4

3

2

1

0

CUSTOM PAT [7:0]

CUSTOM PAT [15:8]

TEST PAT A

R/W-0

CUSTOM PAT [17:16]

R/W-0 R/W-0

0

R/W-0

表8-25. Register 0x14, 15, 16 Field Descriptions

Bit

Field

Type

Reset

Description

7-0

CUSTOM PAT [17:0]

R/W

00000000 This register is used for two purposes:

•

It sets the constant custom pattern starting from MSB

It sets the RAMP pattern increment step size.

00001: Ramp pattern for 18-bit ADC

00100: Ramp pattern for 16-bit ADC

10000: Ramp pattern for 14-bit ADC

7-5

4-2

0

R/W

0

Must write 0.

TEST PAT A

000

Enables test pattern output mode for channel A (NOTE: The test

pattern is set prior to the bit mapper and is based on native

resolution of the ADC starting from the MSB). These work in

either output format.

000: Normal output mode (test pattern output disabled)

010: Ramp pattern: need to set proper increment using

CUSTOM PAT register

011: Constant Pattern using CUSTOM PAT [17:0] in register

0x14/15/16.

others: not used

图8-61. Register 0x18

7

0

6

0

5

0

4

3

2

0

1

0

DCLKIN EN

R/W-0

0

R/W-0

表8-26. Register 0x18 Field Descriptions

Bit

Field

Type

R/W

Reset

Description

7-5

4

0

Must write 0

DCLKIN EN

This bit enables the DCLKIN clock input buffer for serial CMOS

modes. Also DCLKIN EN (0x1F, D6) needs to be set as well.

0: DCLKIN buffer powered down.

1: DCLKIN buffer enabled.

3-0

0

R/W

0

Must write 0

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图8-62. Register 0x19

7

6

0

5

0

4

3

2

0

1

0

FCLK SRC

R/W-0

FCLK DIV

R/W-0

0

FCLK EN

R/W-0

表8-27. Register 0x19 Field Descriptions

Bit

Field

FCLK SRC

Type

Reset

Description

7

R/W

0

User has to select if FCLK signal comes from ADC or from DDC

block. Here real decimation is treated same as bypass mode

0: FCLK generated from ADC. FCLK SRC set to 0 for DDC

bypass and real decimation mode

1: FCLK generated from DDC block. In complex decimation

mode only this bit needs to be set for 2-w and 1-w output

interface mode.

6-5

4

0

R/W

0

Must write 0

FCLK DIV

This bit needs to be set to 1 for 2-w output mode in bypass

mode only (non decimation).

0: All output interface modes except 2-w bypass mode..

1: 2-w output interface mode.

3-2

1

0

R/W

0

Must write 0

FCLK EN

This bit enables FCLK output for CMOS output.

0: Data output pin is used for parallel output data.

1: Data output pin is used for FCLK output in serialized CMOS

mode.

0

R/W

0

Must write 0

表8-28. Configuration of FCLK SRC and FCLK DIV Register Bits vs Serial Interface

BYPASS/DECIMATION

SERIAL INTERFACE

FCLK SRC

FCLK DIV

2-wire

1-wire

2-wire

1-wire

0

1

0

Decimation Bypass/ Real Decimation

Complex Decimation

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图8-63. Register 0x1B

7

6

5

4

3

2

0

1

0

MAPPER EN

R/W-0

20B EN

R/W-0

BIT MAPPER RES

R/W-0

表8-29. Register 0x1B Field Descriptions

Bit

Field

MAPPER EN

Type

Reset

Description

7

R/W

0

This bit enables changing the resolution of the output (including

output serialization factor) in bypass mode only.

0: Output bit mapper disabled.

1: Output bit mapper enabled.

6

20B EN

R/W

0

This bit enables 20-bit output resolution which can be useful for

high decimation settings so that quantization noise doesn't

impact the ADC performance.

0: 20-bit output resolution disabled.

1: 20-bit output resolution enabled.

5-3

BIT MAPPER RES

000

Sets the output resolution using the bit mapper. MAPPER EN bit

(D6) needs to be enabled when operating in bypass mode..

000: 18 bit

001: 16 bit

010: 14 bit

all others, n/a

2-0

0

R/W

0

Must write 0

表8-30. Register Settings for Output Bit Mapper vs Operating Mode

BYPASS/

OUTPUT RESOLUTION

MAPPER EN (D7)

BIT MAPPER RES (D5-D3)

DECIMATION

Decimation Bypass

Real Decimation

Resolution Change

1

0

000: 18-bit

001: 16-bit

010: 14-bit

Resolution Change (default 18-bit)

Complex Decimation

图8-64. Register 0x1E

7

0

6

0

5

4

3

2

0

1

0

CMOS DCLK DEL

R/W-0 R/W-0

0

R/W-0

表8-31. Register 0x1E Field Descriptions

Bit

7-6

5-4

Field

Type

R/W

Reset

Description

0

Must write 0

CMOS DCLK DEL

00

These bits adjust the output timing of CMOS DCLK output.

00: no delay

01: DCLK advanced by 50 ps

10: DCLK delayed by 50 ps

11: DCLK delayed by 100 ps

3-0

0

R/W

0

Must write 0

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图8-65. Register 0x1F

7

6

5

0

4

3

2

0

1

0

LOW DR EN

R/W-0

DCLKIN EN

R/W-0

DCLK OB EN

R/W-0

2X DCLK

R/W-0

表8-32. Register 0x1F Field Descriptions

Bit

Field

LOW DR EN

Type

Reset

Description

7

R/W

0

This bit impacts the output drive strength of the CMOS output

buffers. This bit can be enabled at slow speeds in order to save

power consumption but it will also degrade the rise and fall

times.

0: Low drive strength disabled.

1: Low drive strength enabled.

6

DCLKIN EN

R/W

0

This bit enables the DCLKIN clock input buffer for serial CMOS

modes. Also DCLKIN EN (0x18, D4) needs to be set as well.

0: DCLKIN buffer powered down.

1: DCLKIN buffer enabled.

5

4

0

R/W

0

1

Must write 0

DCLK OB EN

This bit enables DCLK output buffer.

0: DCLK output buffer powered down.

1: DCLK output buffer enabled.

3

2X DCLK

R/W

0

This bit enables SDR output clocking with serial CMOS mode.

When this mode is enabled, DCLKIN required is twice as fast

and data is output only on rising edge of DCLK.

0: Normal operation with data output on DCLK rising and falling

edge.

1: 2x DCLK mode enabled with data output on DCLK rising edge

only.

2-0

0

R/W

0

Must write 0

图8-66. Register 0x20/21/22

7

0

6

5

4

3

2

1

0

FCLK PAT [7:0]

FCLK PAT [15:8]

0

FCLK PAT [19:16]

R/W-0

表8-33. Register 0x20, 21, 22 Field Descriptions

Bit

7-0

Field

Type

Reset

Description

FCLK PAT [19:0]

R/W

0xFFC00

These bits can adjust the duty cycle of the FCLK. In decimation

bypass mode the FCLK pattern gets adjusted automatically for

the different output resolutions. 表8-34 shows the proper FCLK

pattern values for 1-wire in real/complex decimation.

表8-34. FCLK Pattern for different resolution based on interface

DECIMATION

OUTPUT RESOLUTION

2-WIRE

1-WIRE

0xFE000

0xFF000

0xFF800

0xFFFFF

14-bit

16-bit

18-bit

14-bit

16-bit

18-bit

REAL DECIMATION

Use Default

COMPLEX DECIMATION

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图8-67. Register 0x24

7

0

6

0

5

0

4

3

2

1

0

DIG BYP

R/W-0

DDC EN

R/W-0

表8-35. Register 0x24 Field Descriptions

Bit

Field

0

Type

R/W

Reset

Description

7-3

2

0

Must write 0

DIG BYP

This bit needs to be set to enable digital features block which

includes decimation.

0: Digital feature block bypassed - lowest latency

1: Data path includes digital features

1

0

DDC EN

0

R/W

0

Enables internal decimation filter

0: DDC disabled.

1: DDC enabled.

Must write 0

To output

interface

DDC

N

DECIMATION

DIG BYP

图8-68. Register control for digital features

图8-69. Register 0x25

7

0

6

5

4

3

2

1

0

DECIMATION

R/W-0

REAL OUT

R/W-0

0

MIX PHASE

R/W-0

表8-36. Register 0x25 Field Descriptions

Bit

Field

Type

R/W

Reset

Description

7

0

Must write 0

6-4

DECIMATION

000

Complex decimation setting.

000: Bypass mode (no decimation)

001: Decimation by 2

010: Decimation by 4

011: Decimation by 8

100: Decimation by 16

101: Decimation by 32

others: not used

3

REAL OUT

R/W

0

This bit selects real output decimation. In this mode, the

decimation filter is a low pass filter and no complex mixing is

performed to reduce power consumption. For maximum power

savings the NCO in this case should be set to 0.

0: Complex decimation

1: Real decimation

2-1

0

R/W

0

Must write 0

MIX PHASE

This bit used to invert the NCO phase

0: NCO phase as is.

1: NCO phase inverted.

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图8-70. Register 0x26

7

6

5

4

3

2

0

1

0

MIX GAIN A

MIX RES A

R/W-0

FS/4 MIX A

R/W-0

0

R/W-0

表8-37. Register 0x26 Field Descriptions

Bit

Field

Type

Reset

Description

7-6

MIX GAIN A

R/W

00

This bit applies a 0, 3 or 6-dB digital gain to the output of digital

mixer to compensate for the mixing loss for channel A.

00: no digital gain added

01: 3-dB digital gain added

10: 6-dB digital gain added

11: not used

5

4

MIX RES A

FS/4 MIX A

R/W

0

Toggling this bit resets the NCO phase of channel A and loads

the new NCO frequency. This bit does not self reset.

Enables FS/4 mixing for DDC A (complex decimation only).

0: FS/4 mixing disabled.

1: FS/4 mixing enabled.

3-0

0

R/W

0

Must write 0

图8-71. Register 0x27

7

0

6

0

5

0

4

3

2

1

0

OP ORDER A

R/W-0

Q-DEL A

R/W-0

FS/4 MIX PH A

R/W-0

表8-38. Register 0x27 Field Descriptions

Bit

Field

Type

R/W

Reset

Description

7-5

4

0

Must write 0

OP ORDER A

Swaps the I and Q output order for channel A

0: Output order is I[n], Q[n]

1: Output order is swapped: Q[n], I[n]

3

2

Q-DEL A

R/W

0

This delays the Q-sample output of channel A by one.

0: Output order is I[n], Q[n]

1: Q-sample is delayed by 1 sample: I[n], Q[n+1], I[n+1], Q[n+2]

FS/4 MIX PH A

0

Inverts the mixer phase for channel A when using FS/4 mixer

0: Mixer phase is non-inverted

1: Mixer phase is inverted

1-0

Must write 0

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图8-72. Register 0x2A/2B/2C/2D

7

6

5

4

3

2

1

0

NCO A [7:0]

NCO A [15:8]

NCO A [23:16]

NCO A [31:24]

R/W-0

表8-39. Register 0x2A/2B/2C/2D Field Descriptions

Bit

7-0

Field

NCO A [31:0]

Type

Reset

Description

R/W

0

Sets the 32 bit NCO value for decimation filter channel A. The

NCO value is f_NCO× 2³²/F_S

In real decimation these registers are automatically set to 0.

图8-73. Register 0x39...0x72

7

6

5

4

3

2

1

0

OUTPUT BIT MAPPER

R/W-0 R/W-0

R/W-0

表8-40. Register 0x39...0x72 Field Descriptions

Bit

7-0

Field

Type

Reset

Description

OUTPUT BIT MAPPER

R/W

0

These registers are used to reorder the output data bus. See the

节8.3.5.5 on how to program it.

图8-74. Register 0x8F

7

0

6

0

5

0

4

3

2

0

1

0

FORMAT A

R/W-0

表8-41. Register 0x8F Field Descriptions

Bit

Field

Type

R/W

Reset

Description

7-2

1

0

Must write 0

FORMAT A

This bit sets the output data format for channel A. Digital bypass

register bit (0x24, D2) needs to be enabled as well.

0: 2s complement

1: Offset binary

0

R/W

0

Must write 0

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9 Application Information Disclaimer

备注

以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客户应负责确定

器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。

9.1 Application Information

A spectrum analyzer is a typical frequency domain application for the ADC354x and its front end circuitry is

similar to several other systems such as software defined radio (SDR), sonar, radar or communications. Some

applications require frequency coverage including DC or near DC (that is, sonar) so it is included in this example.

9.2 Typical Application

图9-1. Typical configuration for a spectrum analyzer with DC support

9.2.1 Design Requirements

Frequency domain applications cover a wide range of frequencies from low input frequencies at or near DC in

the 1st Nyquist zone to undersampling in higher Nyquist zones. If very low input frequency is supported then the

input has to be DC coupled and the ADC driven by a fully differential amplifier (FDA). If low frequency support is

not needed, then AC coupling and use of a balun may be more suitable.

The internal reference is used since DC precision is not needed. However, the ADC AC performance is highly

dependent on the quality of the external clock source. If in-band interferers can be present, then the ADC SFDR

performance is a key care about. A higher ADC sampling rate is desirable in order to relax the external anti-

aliasing filter –an internal decimation filter can be used to reduce the digital output rate afterwards.

表9-1. Design key care-abouts

FEATURE

DESCRIPTION

Signal Bandwidth

Input Driver

DC to 20 MHz

Single ended to differential signal conversion and DC coupling

External clock with low jitter

Clock Source

When designing the amplifier/filter driving circuit, the ADC input full-scale voltage needs to be taken into

consideration. For example, the ADC354x input full-scale is 2.25 Vpp. When factoring in ~ 1 dB for insertion loss

of the filter, then the amplifier needs to deliver close to 2.5 Vpp. The amplifier distortion performance will degrade

with a larger output swing and considering the ADC common mode input voltage the amplifier may not be able to

deliver the full swing. The ADC354x provides an output common mode voltage of 0.95 V, and the device can

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only swing within 250 mV of the negative supply. A unipolar 3.3 V amplifier power supply limits the maximum

voltage swing to ~ 2.8 V pp. Additionally, input voltage protection diodes may be needed to protect the ADC from

over-voltage events.

表9-2. Output voltage swing of THS4541 vs power supply

DEVICE

MIN OUTPUT VOLTAGE

MAX SWING WITH 3.3 V/ 0 V SUPPLY

THS4541

VS- + 250 mV

2.8 Vpp

9.2.2 Detailed Design Procedure

9.2.2.1 Input Signal Path

Depending on desired input signal frequency range, the device provides a low power options to drive the ADC

inputs. 表 9-3 provides a comparison between the device and the power consumption vs usable frequency trade

off.

表9-3. Fully Differential Amplifier Options

DEVICE

THS4561

THS4551

THS4541

CURRENT (IQ) PER CHANNEL

USABLE FREQUENCY RANGE

0.8 mA

1.4 mA

10 mA

< 3 MHz

< 10 MHz

< 70 MHz

The low pass filter design (topology, filter order) is driven by the application itself. However, when designing the

low pass filter, the optimum load impedance for the amplifier should be taken into consideration as well. Between

the low pass filter and the ADC input the sampling glitch filter must be added as well as shown in 节8.3.1.2.1. In

this example, the DC - 30 MHz glitch filter is selected.

9.2.2.2 Sampling Clock

Applications operating with low input frequencies (such as DC to 20 MHz) typically are less sensitive to

performance degradation due to clock jitter. The internal ADC aperture jitter improves with faster rise and fall

times (i.e. square wave vs sine wave). 表 9-4 provides an overview of the estimated SNR performance of the

ADC354x based on different amounts of jitter of the external clock source. The SNR is estimated based on

ADC354x thermal noise of 79 dBFS and input signal at -1dBFS.

表9-4. ADC SNR performance across vs input frequency for different amounts of external clock jitter

INPUT FREQUENCY

T_J,EXT= 100 fs

T_J,EXT= 250 fs

T_J,EXT= 500 fs

T_J,EXT= 1 ps

5 MHz

79.0

78.9

78.6

78.9

78.7

78.0

78.8

10 MHz

78.0

20 MHz

75.9

Termination of the clock input should be considered for long clock traces.

9.2.2.3 Voltage Reference

The ADC354x is configured to internal reference operation by applying 0.6 V to the REFBUF pin.

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9.2.3 Application Curves

The following FFT plots show the performance of THS4541 driving the ADC354x operated at 65 MSPS with a

full-scale input at -1 dBFS with input frequencies at 1, 5, 10 and 20 MHz.

0

-20

0

-20

-40

-60

-80

-100

-120

-140

-100

-120

-140

0

10

20

Input Frequency (MHz)

30

0

10

20

Input Frequency (MHz)

30

ADC3

SNR = 78.7 dBFS, SFDR = 90 dBc

SNR = 78.6 dBFS, SFDR = 96 dBc

图9-2. Single Tone FFT at F_IN= 1 MHz

图9-3. Single Tone FFT at F_IN= 5 MHz

0

-20

-40

-60

-80

-100

-120

-140

-100

-120

-140

0

10

20

Input Frequency (MHz)

30

0

10

20

Input Frequency (MHz)

30

ADC3

SNR = 78.0 dBFS, SFDR = 92 dBc

SNR = 75.9 dBFS, SFDR = 81 dBc

图9-4. Single Tone FFT at F_IN= 10 MHz

图9-5. Single Tone FFT at F_IN= 20 MHz

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9.3 Initialization Set Up

After power-up, the internal registers must be initialized to their default values through a hardware reset by

applying a high pulse on the RESET pin, as shown in 图9-6.

1. Apply AVDD and IOVDD (no specific sequence required). After AVDD is applied, the internal bandgap

reference powers up and settle out in ~ 2 ms.

2. Configure REFBUF pin (pull high or low even if configured via SPI later on) and apply the sampling clock.

3. Apply hardware reset. After hardware reset is released, the default registers are loaded from internal fuses

and the internal power up capacitor calibration is initiated. The calibration takes approximately 200000 clock

cycles.

4. Begin programming using SPI interface.

AVDD

IOVDD

t₁

REFBUF

Ext VREF

CLK

t₃

t₂

RESET

SEN

图9-6. Initialization of serial registers after power up

表9-5. Power-up timing

MIN

TYP

MAX

UNIT

Power-on delay: delay from power up and logic level of REFBUF pin to

RESET rising edge

t₁

2

ms

t₂

t₃

RESET pulse width

1

us

Delay from RESET disable to SEN active

~ 200000

clock cycles

9.3.1 Register Initialization During Operation

If required, the serial interface registers can be cleared and reset to default settings during operation either:

• through a hardware reset or

• by applying a software reset. When using the serial interface, set the RESET bit (D0 in register address 0x00)

high. This setting initializes the internal registers to the default values and then self-resets the RESET bit low.

In this case, the RESET pin is kept low.

After hardware or software reset the wait time is also ~ 200000 clock cycles before the SPI registers can be

programmed.

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10 Power Supply Recommendations

The ADC354x requires two different power-supplies. The AVDD rail provides power for the internal analog

circuits and the ADC itself while the IOVDD rail powers the digital interface and the internal digital circuits like

decimation filter or output interface mapper. Power sequencing is not required.

The AVDD power supply must be low noise in order to achieve data sheet performance. In applications

operating near DC, the 1/f noise contribution of the power supply needs to be considered as well. The ADC is

designed for very good PSRR which aides with the power supply filter design.

图10-1. Power supply rejection ratio (PSRR) vs frequency

There are two recommended power-supply architectures:

1. Step down using high-efficiency switching converters, followed by a second stage of regulation using a low

noise LDO to provide switching noise reduction and improved voltage accuracy.

2. Directly step down the final ADC supply voltage using high-efficiency switching converters. This approach

provides the best efficiency, but care must be taken to ensure switching noise is minimized to prevent

degraded ADC performance.

TI WEBENCH® Power Designer can be used to select and design the individual power-supply elements

needed: see the WEBENCH® Power Designer

Recommended switching regulators for the first stage include the TPS62821, and similar devices.

Recommended low dropout (LDO) linear regulators include the TPS7A4701, TPS7A90, LP5901, and similar

devices.

For the switch regulator only approach, the ripple filter must be designed with a notch frequency that aligns with

the switching ripple frequency of the DC/DC converter. Note the switching frequency reported from WEBENCH®

and design the EMI filter and capacitor combination to have the notch frequency centered as needed. 图 10-2

and 图10-3 illustrate the two approaches.

AVDD and IOVDD supply voltages should not be shared in order to prevent digital switching noise from coupling

into the analog signal chain.

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FB

2.1V

1.8V

DC/DC

5V-12V

LDO

AVDD

Regulator

10uF 10uF 0.1uF

47uF

GND

FB

IOVDD

10uF 10uF 0.1uF

FB = Ferrite bead filter

GND

图10-2. Example: LDO Linear Regulator Approach

EMI FILTER

FB

1.8V

DC/DC

Regulator

5V-12V

AVDD

10uF 10uF 10uF

10uF 10uF 0.1uF

GND

FB

IOVDD

10uF 10uF 0.1uF

GND

Ripple filter notch frequency to match switching frequency of the DC/DC regulator

FB = Ferrite bead filter

图10-3. Example Switcher-Only Approach

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11 Layout

11.1 Layout Guidelines

There are several critical signals which require specific care during board design:

1. Analog input and clock signals

• Traces should be as short as possible and vias should be avoided where possible to minimize impedance

discontinuities.

• Traces should be routed using loosely coupled 100-Ωdifferential traces.

• Differential trace lengths should be matched as close as possible to minimize phase imbalance and HD2

degradation.

2. Digital output interface

• A 20 ohm series isolation resistor should be used on each CMOS output and placed close the digital

output. This isolation resistor limits the output current into the capacitive load and thus minimizes the

switching noise inside the ADC. When driving longer distances a buffer should be used. The resistor

value should be optimized for the desired output data rate.

3. Voltage reference

• The bypass capacitor should be placed as close to the device pins as possible and connected between

VREF and REFGND –on top layer avoiding vias.

• Depending on configuration an additional bypass capacitor between REFBUF and REFGND may be

recommended and should also be placed as close to pins as possible on top layer.

4. Power and ground connections

• Provide low resistance connection paths to all power and ground pins.

• Use power and ground planes instead of traces.

• Avoid narrow, isolated paths which increase the connection resistance.

• Use a signal/ground/power circuit board stackup to maximize coupling between the ground and power

plane.

11.2 Layout Example

The following screen shot shows the top layer of the ADC354x EVM.

• Signal and clock inputs are routed as differential signals on the top layer avoiding vias.

• CMOS output interface lanes with isolation resistor and digital buffer.

• Bypass caps are close to the VREF pin on the top layer avoiding vias.

Bypass caps on VREF close

to the pins on top layer

Isolation resistors on CMOS

output pins

Clock routing

without vias

Analog inputs on

top layer (no vias)

图11-1. Layout example: top layer of ADC354x EVM

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12 Device and Documentation Support

12.1 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper

right corner, click on Alert me to register and receive a weekly digest of any product information that has

changed. For change details, review the revision history included in any revised document.

12.2 支持资源

TI E2E^™支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解

答或提出自己的问题可获得所需的快速设计帮助。

链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅

TI 的《使用条款》。

12.3 Trademarks

PowerPAD^™and TI E2E^™are trademarks of Texas Instruments.

所有商标均为其各自所有者的财产。

12.4 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

12.5 术语表

TI 术语表

本术语表列出并解释了术语、首字母缩略词和定义。

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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Product Folder Links: ADC3541 ADC3542 ADC3543

PACKAGE OUTLINE

RSB0040E

WQFN - 0.8 mm max height

S

C

A

L

E

2

.

7

0

PLASTIC QUAD FLATPACK - NO LEAD

5.1

4.9

B

A

PIN 1 INDEX AREA

5.1

4.9

C

0.8 MAX

SEATING PLANE

0.08 C

0.05

0.00

2X 3.6

(0.2) TYP

EXPOSED

11

20

THERMAL PAD

36X 0.4

10

21

2X

41

SYMM

3.6

3.15 0.1

1

30

0.25

0.15

40X

40

31

PIN 1 ID

(OPTIONAL)

0.1

C A B

SYMM

0.5

0.3

0.05

40X

4219096/A 11/2017

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

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EXAMPLE BOARD LAYOUT

RSB0040E

WQFN - 0.8 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(

3.15)

SYMM

40

31

40X (0.6)

40X (0.2)

1

30

36X (0.4)

41

SYMM

(4.8)

(1.325)

(

0.2) TYP

VIA

10

21

(R0.05)

TYP

11

20

(1.325)

(4.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:15X

0.05 MIN

ALL AROUND

0.05 MAX

ALL AROUND

SOLDER MASK

OPENING

METAL

EXPOSED

METAL

EXPOSED

METAL

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4219096/A 11/2017

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

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EXAMPLE STENCIL DESIGN

RSB0040E

WQFN - 0.8 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(0.785)

4X ( 1.37)

40

31

40X (0.6)

1

30

40X (0.2)

36X (0.4)

SYMM

(0.785)

(4.8)

41

(R0.05) TYP

10

21

METAL

TYP

20

11

SYMM

(4.8)

SOLDER PASTE EXAMPLE

BASED ON 0.1 mm THICK STENCIL

EXPOSED PAD 41

75% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

SCALE:20X

4219096/A 11/2017

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

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型号：	ADC3543IRSBT
厂家：	TEXAS INSTRUMENTS
描述：	单通道、14 位、65MSPS、低噪声、超低功耗和低延迟 ADC \| RSB \| 40 \| -40 to 105
文件：	总87页 (文件大小：5836K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ADC3543IRSBT [TI]

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