ADC3564 [TI]
具有 SLVDS 接口的单通道、14 位、125MSPS、高 SNR、低功耗 ADC;
| 型号： | ADC3564 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有 SLVDS 接口的单通道、14 位、125MSPS、高 SNR、低功耗 ADC |
| 文件： | 总72页 (文件大小：4484K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ADC3564
ZHCSR25 –AUGUST 2022
ADC3564 14 位、125MSPS、低噪声、超低功耗ADC
1 特性
3 说明
• 14 位125MSPS ADC
ADC3564 器件是一款低噪声、超低功耗、14 位、
125MSPS 高速 ADC。该器件可实现低功耗，噪声频
谱密度为 –156dBFS/Hz，还具有出色的线性度和动态
范围。ADC3564 可提供中频采样支持，使器件适合各
种应用。高速控制环路可从低至一个时钟周期的低延迟
中受益。该 ADC 在 125MSPS 下的功耗仅为
137mW，功耗随采样率减小而迅速降低。
• 本底噪声：-156dBFS/Hz
• 超低功耗：125MSPS 时为137mW
• 延迟：≤2 个时钟周期
• 指定的14 位，无丢码
• INL：±1.5LSB；DNL：±0.5LSB
• 基准：外部或内部
• 输入带宽：1200 MHz (3dB)
• 工业温度范围：-40°C 至+105°C
• 片上数字滤波器（可选）
ADC3564 使用串行 LVDS (SLVDS) 接口输出数据，可
更大限度减少数字互连的次数。该器件提供双通道、单
通道和半通道选项。该器件是具有不同速度等级的引脚
对引脚兼容系列，采用40 引脚VQFN 封装。该器件支
持–40⁰C 至+105⁰C 的工业级工作温度范围。
– 2 倍、4 倍、8 倍、16 倍、32 倍抽取率
– 32 位NCO
• 串行LVDS 数字接口（2 线、1 线和1/2 线）
• 小尺寸: 40 引脚WQFN (5mm × 5mm) 封装
• 频谱性能(fIN = 10MHz)：
封装信息
封装(1)
封装尺寸（标称值）
器件型号
ADC3564
WQFN (40)
5.00 × 5.00mm
– SNR：77.5dBFS
– SFDR：80dBc HD2、HD3
– SFDR：95dBFS 最严重毛刺
• 频谱性能(fIN = 70MHz)：
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
表3-1. 器件比较
分辨率
– SNR：75dBFS
– SFDR：75dBc HD2、HD3
– SFDR：90dBFS 最严重毛刺
器件型号
ADC3561
采样率
10MSPS
16 位
16 位
16 位
14 位
ADC3562
ADC3563
ADC3564
25MSPS
65MSPS
125MSPS
2 应用
• 高速数据采集
• 工业监控
• 热成像
• 成像与声纳
• 软件定义无线电
• 电能质量分析仪
• 通信基础设施
• 控制环路
• 仪表
• 智能电网
• 光谱分析
• 雷达
简化版方框图
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SBAS887
ADC3564
ZHCSR25 –AUGUST 2022
www.ti.com.cn
Table of Contents
8.3 Feature Description...................................................20
8.4 Device Functional Modes..........................................41
8.5 Programming............................................................ 42
8.6 Register Maps...........................................................44
9 Application Information Disclaimer.............................58
9.1 Typical Application.................................................... 58
9.2 Initialization Set Up................................................... 61
9.3 Power Supply Recommendations.............................62
9.4 Layout....................................................................... 63
10 Device and Documentation Support..........................65
10.1 Device Support....................................................... 65
10.2 Documentation Support.......................................... 65
10.3 接收文档更新通知................................................... 65
10.4 支持资源..................................................................65
10.5 商标.........................................................................65
10.6 Electrostatic Discharge Caution..............................65
10.7 术语表..................................................................... 65
11 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 5
6.1 Absolute Maximum Ratings........................................ 5
6.2 ESD Ratings............................................................... 5
6.3 Recommended Operating Conditions.........................5
6.4 Thermal Information....................................................5
6.5 Electrical Characteristics - Power Consumption.........6
6.6 Electrical Characteristics - DC Specifications.............7
6.7 Electrical Characteristics - AC Specifications............. 9
6.8 Timing Requirements................................................10
6.9 Typical Characteristics..............................................12
7 Parameter Measurement Information..........................17
8 Detailed Description......................................................19
8.1 Overview...................................................................19
8.2 Functional Block Diagram.........................................19
Information.................................................................... 65
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
DATE
REVISION
NOTES
August 2022
*
Initial release.
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5 Pin Configuration and Functions
40
39
38
37
36
35
34
33
32
31
1
2
30
29
28
27
26
25
24
23
22
21
PDN/SYNC
VREF
IOVDD
FCLKM
FCLKP
3
REFGND
REFBUF
AVDD
CLKP
4
NC
5
IOGND
DCLKINP
DCLKINM
DCLKP
DCLKM
IOVDD
6
7
CLKM
8
VCM
9
RESET
SDIO
GND PAD (backside)
10
11
12
13
14
15
16
17
18
19
20
图5-1. RSB (WQFN) Package, 40-Pin
(Top View)
表5-1. Pin Descriptions
PIN
I/O
DESCRIPTION
NAME
NO.
INPUT/REFERENCE
AINP
12
13
8
I
I
Positive analog input
Negative analog input
AINM
VCM
O
I
Common-mode voltage output for the analog inputs
External voltage reference input
VREF
2
REFBUF
REFGND
CLOCK
4
I
1.2 V external voltage reference input for use with internal reference buffer
Reference ground input, 0 V
3
I
CLKM
7
6
I
I
Negative differential sampling clock input for the ADC
Positive differential sampling clock input for the ADC
CLKP
CONFIGURATION
Power down/Synchronization input. This pin can be configured via the SPI interface. Active
high. This pin has an internal 21 kΩpull-down resistor.
PDN/SYNC
1
I
RESET
SEN
9
I
I
Hardware reset. Active high. This pin has an internal 21 kΩpull-down resistor.
16
Serial interface enable. Active low. This pin has an internal 21 kΩpull-up resistor to AVDD.
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表5-1. Pin Descriptions (continued)
PIN
I/O
DESCRIPTION
NAME
SCLK
SDIO
NC
NO.
35
I
I
-
Serial interface clock input. This pin has an internal 21 kΩpull-down resistor.
10
Serial interface data input and output. This pin has an internal 21 kΩpull-down resistor.
27,38,39
Do not connect
DIGITAL INTERFACE
DA0P
DA0M
DA1P
DA1M
20
O
O
O
O
Positive differential serial LVDS output for lane 0, channel A
Negative differential serial LVDS output for lane 0, channel A
Positive differential serial LVDS output for lane 1, channel A
Negative differential serial LVDS output for lane 1, channel A
19
18
17
Positive differential serial LVDS output for lane 0, channel B. Used only in dual band
complex decimation. Default is powered down.
DB0P
DB0M
DB1P
DB1M
31
32
33
34
O
O
O
O
Negative differential serial LVDS output for lane 0, channel B. Used only in dual band
complex decimation. Default is powered down.
Positive differential serial LVDS output for lane 1, channel B. Used only in dual band
complex decimation. Default is powered down.
Negative differential serial LVDS output for lane 1, channel B. Used only in dual band
complex decimation. Default is powered down.
DCLKP
23
22
28
29
25
24
O
O
O
O
I
Positive differential serial LVDS bit clock output.
Negative differential serial LVDS bit clock output.
Positive differential serial LVDS frame clock output.
Negative differential serial LVDS frame clock output.
Positive differential serial LVDS bit clock input.
Negative differential serial LVDS bit clock input.
DCLKM
FCLKP
FCLKM
DCLKINP
DCLKINM
POWER SUPPLY
AVDD
I
5,15,36
I
I
Analog 1.8 V power supply
Ground, 0 V
11,14,37,40,
PowerPad
GND
IOGND
IOVDD
26
I
I
Ground, 0 V for digital interface
21,30
1.8 V power supply for digital interface
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
PARAMETER
TEST CONDITIONS
MIN
–0.3
–0.3
MAX
2.1
UNIT
V
Supply voltage range, AVDD, IOVDD
Supply voltage range, GND, IOGND, REFGND
0.3
V
MIN(2.1,
AVDD+0.3)
AINP/M, CLKP/M, DCLKINP/M, VREF, REFBUF
PDN/SYNC, RESET, SCLK, SEN, SDIO
–0.3
–0.3
Voltage applied to
input pins
V
MIN(2.1,
AVDD+0.3)
Junction temperature, TJ
Storage temperature, Tstg
105
150
°C
°C
–65
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
6.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1)
2500
Electrostatic
discharge
V(ESD)
V
Charged device model (CDM), per JEDEC specification JESD22-C101, all
pins(2)
1000
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
1.75
1.75
–40
NOM
1.8
MAX UNIT
AVDD(1)
1.85
1.85
V
V
Supply
voltage range
IOVDD(1)
1.8
TA
TJ
Operating free-air temperature
Operating junction temperature
105
°C
°C
105(2)
(1) Measured to GND.
(2) Prolonged use above this junction temperature may increase the device failure-in-time (FIT) rate.
6.4 Thermal Information
ADC3564
RSB (QFN)
40 Pins
30.7
THERMAL METRIC(1)
UNIT
RΘJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RΘJC(top)
RΘJB
16.4
10.5
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.2
ΨJT
10.5
ΨJB
RΘJC(bot)
2.0
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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6.5 Electrical Characteristics - Power Consumption
Typical values are over the operating free-air temperature range, at TA = 25°C, full temperature range is TMIN = –40°C to
TMAX = 105°C, ADC sampling rate = 125 MSPS, 50% clock duty cycle, AVDD = IOVDD = 1.8 V, external 1.6V reference, and
–1-dBFS differential input, unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
ADC3564: 125 MSPS
IAVDD
IIOVDD
PDIS
Analog supply current
I/O supply current
Power dissipation
External reference
41
35
137
27
41
36
48
45
41
40
62
mA
57
SLVDS 2-wire
External reference, SLVDS 2-wire
SLVDS 2-wire, 1/2-swing
mW
4x real decimation, SLVDS 1-wire
16x real decimation, SLVDS 1-wire
4x complex decimation, SLVDS 1-wire
8x complex decimation, SLVDS 1-wire
16x complex decimation, SLVDS 1-wire
32x complex decimation, SLVDS 1-wire
IIOVDD
I/O supply current
mA
MISCELLANOUS
Internal reference, additional analog
4
0.5
1
supply current
External 1.2V reference (REFBUF),
additional analog supply current
IAVDD
Enabled via SPI
mA
Single ended clock input, reduces
analog supply current by
Power consumption in global power
down mode
PDIS
Default mask settings
12
mW
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6.6 Electrical Characteristics - DC Specifications
Typical values are over the operating free-air temperature range, at TA = 25°C, full temperature range is TMIN = –40°C to
TMAX = 105°C, ADC sampling rate = 125 MSPS, 50% clock duty cycle, AVDD = IOVDD = 1.8 V, 1.6 V external reference, and
–1-dBFS differential input, unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DC ACCURACY
No missing codes
PSRR
14
bits
dB
FIN = 1 MHz
35
± 0.9
± 2.6
± 30
± 0.06
± 2
DNL
Differential nonlinearity
Integral nonlinearity
Offset error
FIN = 5 MHz
FIN = 5 MHz
-0.97
-7.5
-55
0.97
7.5
55
LSB
INL
LSB
VOS_ERR
VOS_DRIFT
GAINERR
GAINDRIFT
GAINERR
GAINDRIFT
LSB
Offset drift over temperature
Gain error
LSB/ºC
%FSR
ppm/ºC
%FSR
ppm/ºC
LSB
External 1.6V Reference
External 1.6V Reference
Internal Reference
Gain drift over temperature
Gain error
± 57
± 3
Gain drift over temperature
Internal Reference
106
Transition Noise
0.7
ADC ANALOG INPUT (AINP/M)
FS
Input full scale
Differential
3.2
0.95
8
Vpp
V
VCM
RIN
Input common model voltage
Input resistance
0.9
1.0
Differential at DC
Differential at DC
kΩ
pF
CIN
Input Capacitance
5.4
0.95
1.4
VOCM
BW
Output common mode voltage
Analog Input Bandwidth (-3dB)
V
GHz
Internal Voltage Reference
VREF
Internal reference voltage
1.6
8
V
VREF Output Impedance
Reference Input Buffer (REFBUF)
External reference voltage
External voltage reference (VREF)
Ω
1.2
V
VREF
External voltage reference
1.6
1
V
Input Current
mA
kΩ
Input impedance
5.3
Clock Input (CLKP/M)
External reference
Internal reference
10
125
125
3.6
MHz
MHz
Vpp
V
Input clock frequency
100
VID
VCM
RIN
CIN
Differential input voltage
Input common mode voltage
1
0.9
5
Single ended input resistance to common mode
Single ended input capacitance
kΩ
pF
1.5
50
Clock duty cycle
45
60
%
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6.6 Electrical Characteristics - DC Specifications (continued)
Typical values are over the operating free-air temperature range, at TA = 25°C, full temperature range is TMIN = –40°C to
TMAX = 105°C, ADC sampling rate = 125 MSPS, 50% clock duty cycle, AVDD = IOVDD = 1.8 V, 1.6 V external reference, and
–1-dBFS differential input, unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Digital Inputs (RESET, PDN, SCLK, SEN, SDIO)
VIH
VIL
IIH
IIL
High level input voltage
Low level input voltage
High level input current
Low level input current
Input capacitance
1.4
V
0.4
90
-90
1.5
150
uA
uA
pF
-150
CI
Digital Output (SDOUT)
IOVDD
–0.1
VOH
VOL
High level output voltage
Low level output voltage
ILOAD = -400 uA
IOVDD
V
ILOAD = 400 uA
0.1
SLVDS Interface
VID
Differential input voltage
Input common mode voltage
200
1
350
1.2
650
1.3
1
mVpp
V
DCLKIN
VCM
Output data rate
per differential SLVDS output
Gbps
mVpp
V
VOD
VCM
Differential output voltage
Output common mode voltage
500
700
1.0
850
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6.7 Electrical Characteristics - AC Specifications
Typical values are over the operating free-air temperature range, at TA = 25°C, full temperature range is TMIN = –40°C to
TMAX = 105°C, ADC sampling rate = 125 MSPS, 50% clock duty cycle, AVDD = IOVDD = 1.8 V, 1.6 V external reference, and
–1-dBFS differential input, unless otherwise noted
PARAMETER
TEST CONDITIONS
fIN = 5 MHz, AIN = -20 dBFS
fIN = 5 MHz
MIN
TYP
-156.9
77.5
78.9
77.6
76.9
75.5
74.1
75.7
74.2
72.6
71.3
72.4
12.6
12.6
12.5
12.3
12.0
80
MAX
UNIT
dBFS/Hz
dBFS
NSD
Noise Spectral Density
72
fIN = 5 MHz, AIN = -20 dBFS
fIN = 10 MHz
fIN = 40 MHz
fIN = 70 MHz
fIN = 100 MHz
fIN = 5 MHz
SNR
Signal to noise ratio
dBFS
dBFS
bit
fIN = 10 MHz
fIN = 40 MHz
fIN = 70 MHz
fIN = 100 MHz
fIN = 5 MHz
SINAD
ENOB
THD
Signal to noise and distortion ratio
fIN = 10 MHz
fIN = 40 MHz
fIN = 70 MHz
fIN = 100 MHz
fIN = 5 MHz
Effective number of bits
71.5
fIN = 10 MHz
fIN = 40 MHz
fIN = 70 MHz
fIN = 100 MHz
fIN = 5 MHz
76
Total Harmonic Distortion (First five
harmonics)
74
dBc
dBc
dBc
72
76
77
84
fIN = 10 MHz
fIN = 40 MHz
fIN = 70 MHz
fIN = 100 MHz
fIN = 5 MHz
78
HD2
Second Harmonic Distortion
Third Harmonic Distortion
75
77
79
73.5
84
fIN = 10 MHz
fIN = 40 MHz
fIN = 70 MHz
fIN = 100 MHz
fIN = 5 MHz
81
HD3
88
76
81
84
92
fIN = 10 MHz
fIN = 40 MHz
fIN = 70 MHz
fIN = 100 MHz
93
Spur free dynamic range (excluding
HD2 and HD3)
Non HD2,3
IMD3
89
dBFS
dBc
84
86
f1 = 10 MHz, f2 = 12 MHz, AIN = -7
dBFS/tone
Two tone inter-modulation distortion
88
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6.8 Timing Requirements
Typical values are over the operating free-air temperature range, at TA = 25°C, full temperature range is TMIN = –40°C to
TMAX = 105°C, ADC sampling rate = 125 MSPS, 50% clock duty cycle, AVDD = IOVDD = 1.8 V, 1.6 V external reference, and
–1-dBFS differential input, unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN NOM MAX
UNIT
ADC Timing Specifications
tAD
tA
Aperture Delay
Aperture Jitter
Jitter on DCLKIN
0.85
250
ns
fs
square wave clock with fast edges
SNR within 1 dB of expected value
tJ
± 50 ps pk-pk
Clock
cycle
Recory time from +6 dB overload condition
1
Sampling
clock
period
tACQ
Signal acquisition period
Signal conversion period
-TS/4
referenced to sampling clock falling edge
tCONV
6
13
ns
Bandgap reference enabled, single ended clock
Bandgap reference enabled, differential clock
Bandgap reference disabled, single ended clock
Bandgap reference disabled, differential clock
Bandgap reference enabled, single ended clock
Bandgap reference enabled, differential clock
Bandgap reference disabled, single ended clock
Bandgap reference disabled, differential clock
us
15
Time to valid data after coming out of
power down. Internal reference.
2.4
2.3
13
ms
us
Wake up
time
Time to valid data after coming out of
power down.
External 1.6V reference.
14
2.0
2.2
ms
ps
tS,SYNC
tH,SYNC
Setup time for SYNC input signal
Hold time for SYNC input signal
500
600
Referenced to sampling clock rising edge
1/2-wire SLVDS
1-wire SLVDS
2-wire SLVDS
1
1
ADC
Latency
Clock
cycles
Signal input to data output
2
Real decimation by 2
21
22
Output
clock
cycles
Add.
Latency
Complex decimation by 2
Real or complex decimation by 4, 8,
16, 32
23
Interface Timing: Serial LVDS Interface
Delay between sampling clock falling edge to
DCLKIN falling edge < 2.5ns.
TDCLK = DCLK period
tCDCLK = Sampling clock falling edge to DCLKIN
falling edge
2 +
3 +
4 +
TDCLK TDCLK TDCLK
+
+
+
tCDCLK tCDCLK tCDCLK
Propagation delay: sampling clock
falling edge to DCLK rising edge
tPD
ns
Delay between sampling clock falling edge to
DCLKIN falling edge >= 2.5ns.
TDCLK = DCLK period
tCDCLK = Sampling clock falling edge to DCLKIN
falling edge
2 +
3 +
4 +
tCDCLK tCDCLK tCDCLK
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6.8 Timing Requirements (continued)
Typical values are over the operating free-air temperature range, at TA = 25°C, full temperature range is TMIN = –40°C to
TMAX = 105°C, ADC sampling rate = 125 MSPS, 50% clock duty cycle, AVDD = IOVDD = 1.8 V, 1.6 V external reference, and
–1-dBFS differential input, unless otherwise noted
PARAMETER
TEST CONDITIONS
Fout = 65 MSPS, DA/B0,1 = 455 MBPS
Fout = 80 MSPS, DA/B0,1 = 560 MBPS
Fout = 125 MSPS, DA/B0,1 = 875 MBPS
MIN NOM MAX
UNIT
0
0
0.1
0.1
0.1
DCLK rising edge to output data
delay,
2-wire SLVDS, 14-bit
-0.2
DCLK rising edge to output data
delay,
Fout = 65 MSPS, DA/B0 = 910 MBPS
0
0.1
1-wire SLVDS, 14-bit
tCD
ns
Fout = 10 MSPS, DA/B0 = 160 MBPS
Fout = 25 MSPS, DA/B0 = 400 MBPS
Fout = 62.5 MSPS, DA/B0= 1000 MBPS
Fout = 5 MSPS, DA0 = 160 MBPS
Fout = 10 MSPS, DA0 = 320 MBPS
Fout = 25 MSPS, DA0 = 800 MBPS
Fout = 65 MSPS, DA/B0,1 = 455 MBPS
Fout = 80 MSPS, DA/B0,1 = 560 MBPS
Fout = 125 MSPS, DA/B0,1 = 875 MBPS
Fout = 65 MSPS, DA/B0 = 910 MBPS
Fout = 10 MSPS, DA/B0 = 160 MBPS
Fout = 25 MSPS, DA/B0 = 400 MBPS
Fout = 62.5 MSPS, DA/B0= 1000 MBPS
Fout = 5 MSPS, DA0 = 160 MBPS
Fout = 10 MSPS, DA0 = 320 MBPS
Fout = 25 MSPS, DA0 = 800 MBPS
0
0
0.1
0.1
0.1
0.1
0.1
0.1
1.9
1.5
0.8
0.8
5.8
2.1
0.6
5.8
2.8
0.9
DCLK rising edge to output data
delay,
1-wire SLVDS, 16-bit
-0.6
0
DCLK rising edge to output data
delay,
1/2-wire SLVDS, 16-bit
0
0
1.8
1.4
0.6
0.6
5.7
2.0
0.5
5.7
2.7
0.8
Data valid, 2-wire SLVDS, 14-bit
Data valid, 1-wire SLVDS, 14-bit
Data valid, 1-wire SLVDS, 16-bit
tDV
ns
Data valid, 1/2-wire SLVDS, 16-bit
SERIAL PROGRAMMING INTERFACE (SCLK, SEN, SDIO) - Input
fCLK,SCLK Serial clock frequency
20
MHz
ns
tS,SEN
tH,SEN
tS,SDIO
tH,SDIO
SEN falling edge to SCLK rising edge
SCLK rising edge to SEN rising edge
SDIO setup time from rising edge of SCLK
SDIO hold time from rising edge of SCLK
10
9
17
9
SERIAL PROGRAMMING INTERFACE (SDIO) - Output
Delay from falling edge of 16th SCLK cycle during read operation for SDIO transition from
tri-state to valid data
tOZD
3.9
10.8
ns
tODZ
tOD
Delay from SEN rising edge for SDIO transition from valid data to tri-state
Delay from falling edge of 16th SCLK cycle during read operation to SDIO valid
3.4
3.9
14
10.8
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6.9 Typical Characteristics
Typical values at TA = 25 °C, ADC sampling rate = 125 MSPS, AIN = –1 dBFS differential input, AVDD = IOVDD
= 1.8 V, external voltage reference, unless otherwise noted.
0
-20
-40
-60
-80
-100
-120
-140
0
10
20
30
40
50
60
Input Frequency (MHz)
SNR = 77.0 dBFS
SNR = 77.5 dBFS
图6-1. Single Tone FFT at FIN = 5 MHz
图6-2. Single Tone FFT at FIN = 10 MHz
AIN = -20 dBFS, SNR = 78.5 dBFS
SNR = 76.5 dBFS
图6-3. Single Tone FFT at FIN = 10 MHz
图6-4. Single Tone FFT at FIN = 40 MHz
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SNR = 75.2 dBFS
AIN = -20 dBFS, SNR = 77.0 dBFS
图6-5. Single Tone FFT at FIN = 70 MHz
图6-6. Single Tone FFT at FIN = 70 MHz
0
-20
-40
-60
-80
-100
-120
-140
0
10
20
30
40
50
60
Input Frequency (MHz)
SNR = 74.0 dBFS
AIN= -7 dBFS/tone
图6-7. Single Tone FFT at FIN = 100 MHz
图6-8. Two Tone FFT at FIN = 10/12 MHz
0
-20
-40
-60
-80
-100
-120
-140
0
10
20
30
40
50
60
Input Frequency (MHz)
图6-10. AC Performance vs Input Frequency
AIN= -20 dBFS/tone
图6-9. Two Tone FFT at FIN = 10/12 MHz
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FIN = 5 MHz
AIN = -1 dBFS
图6-12. AC Performance vs Input Amplitude
图6-11. ENOB vs Input Frequency
80
FIN = 10 MHz
FIN = 30 MHz
FIN = 70 MHz
79
78
77
76
75
74
73
72
0.5
1
1.5 2
Clock Amplitude (Vpp)
2.5
3
D016
AIN = -1 dBFS
FIN = 5 MHz
图6-14. SNR vs Clock Amplitude
图6-13. AC Performance vs Sampling Rate
FIN = 5 MHz
FIN = 5 MHz
图6-15. AC Performance vs AVDD
图6-16. AC Performance vs VCM vs Temperature
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FIN = 5 MHz
FIN = 5 MHz
图6-17. INL vs Code
图6-18. DNL vs Code
300000
250000
200000
150000
100000
50000
0
External VREF
Internal VREF
8186
8187
8188
8189
Output Code
8190
8191
8192
D033
Internal vs external reference, inputs shorted to VCM
Pulse Input = 1 MHz
图6-19. DC Histogram
图6-20. Pulse Response
45
42.5
40
IAVDD, ext REF
IAVDD, int REF
IIOVDD, 2-w
IIOVDD, 1-w
IIOVDD, 2-w, 1/2-swing
IIOVDD, 1-w, 1/2-swing
37.5
35
32.5
30
27.5
25
22.5
20
65 70 75 80 85 90 95 100 105 110 115 120 125
Sampling Rate (MSPS)
FIN = 5 MHz
FIN = 5 MHz
图6-22. Current vs Decimation
图6-21. Current vs Sampling Rate
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FIN = 5 MHz
图6-23. Current vs Interface
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7 Parameter Measurement Information
Sample N
Sample N+1
Input Signal
tAD
tPD
Sampling
Clock
tACQ
tConv
tCDCLK
DCLKIN
DCLK
tCD
TDCLK
FCLK
tDV
D13 D11
D12 D10
D9
D8
D7
D5
D4
D3
D2
D1
D0
D13 D11
D12 D10
D9
D8
D7
D5
D4
D3
D2
D1
D0
DA/DB1
DA/DB0
D6
D6
Sample N-2
Sample N-1
图7-1. Timing diagram: 2-wire SLVDS
Sample N
Sample N+1
Input Signal
tAD
tPD
Sampling
Clock
tACQ
tConv
tCDCLK
DCLKIN
DCLK
FCLK
TDCLK
tCD
tDV
D2
D2
D1
D1
D0
D0
D13 D12 D11 D10
D13 D12 D11 D10
D9
D9
D8
D8
D7
D7
D6
D6
D5
D5
D4
D4
D3
D3
D2
D2
D1
D1
D0
DA0
DB0
D0
Sample N-1
图7-2. Timing diagram: 1-wire SLVDS
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Sample N
tAD
Input Signal
Sample N+1
tPD
Sampling
Clock
tACQ
tConv
tCDCLK
DCLKIN
DCLK
FCLK
tCD
TDCLK
tDV
Channel A
Channel B
D
5
D
4
D D
D
1
D
D
D
D
D
D
D
8
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D D
0 13 12 11 10 9
D
D
D
D
D
8
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
DA0
3
2
0 13 12 11 10 9
Sample N-2
Sample N-1
图7-3. Timing diagram: 1/2-wire SLVDS
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8 Detailed Description
8.1 Overview
The ADC3564 is a low noise, ultra-low power 14-bit 125 MSPS high-speed ADC. It offers DC precision together
with IF sampling support which makes it suited for a wide range of applications. The ADC3564 is equipped with
an on-chip internal reference option but it also supports the use of an external, high precision 1.6 V voltage
reference or an external 1.2 V reference which is buffered and gained up internally. Because of the inherent low
latency architecture, the digital output result is available after only one clock cycle. Single ended as well as
differential input signaling is supported.
备注
The ADC3564 supports the following sampling rates:
• External Reference: 10 to 125 MSPS
• Internal Reference: 100 to 125 MSPS
An optional, programmable digital down converter enables external anti-alias filter relaxation as well as output
data rate reduction. The digital filter provides a 32-bit programmable NCO and supports both real or complex
decimation.
The ADC3564 uses a serial LVDS (SLVDS) interface to output the data which minimizes the number of digital
interconnects. The device supports a two-lane (2-wire), a one-lane (1-wire) and a half-lane (1/2-wire) option. The
ADC3564 includes a digital output formatter which supports output resolutions from 14 to 20-bit.
The device features and control options can be set up either through pin configurations or via SPI register writes.
8.2 Functional Block Diagram
REFBUF
1.2V REF
Digital Downconverter
Crosspoint
Switch
VREF
NCO
N
AIN
ADC
DCLKIN
DCLK
Dig I/F
SLVDS
FCLK
0.95V
VCM
DA0/1
DB0/1
CLK
Control
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8.3 Feature Description
8.3.1 Analog Input
The analog inputs of ADC3564 are intended to be driven differentially. Both AC coupling and DC coupling of the
analog inputs is supported. The analog inputs are designed for an input common mode voltage of 0.95 V which
must be provided externally on each input pin. DC-coupled input signals must have a common mode voltage that
meets the device input common mode voltage range.
The equivalent input network diagram is shown in 图8-1. All four sampling switches, on-resistance shown in red,
are in same position (open or closed) simultaneously.
AVDD
Sampling Switch
0.32 pF
1 ꢀ
125 ꢀ
2 nH
xINP/
xINM
24 ꢀ
1.4 pF
0.15 pF
0.6 pF
GND
0.6 pF
GND
GND
GND
GND
2.6 pF
7 ꢀ
GND
5 ꢀ
0.7 pF
1.6 pF
GND
GND
GND
图8-1. Equivalent Input Network
8.3.1.1 Analog Input Bandwidth
图 8-2 shows the analog full power input bandwidth of the ADC3664 with a 50 Ω differential termination. The -3
dB bandwidth is approximately 1.4 GHz and the useful input bandwidth with good AC performance is
approximately 200 MHz.
The equivalent differential input resistance RIN and input capacitance CIN vs frequency are shown in 图8-3.
图8-3. Equivalent RIN/CIN vs Input Frequency
图8-2. ADC Analog Input bandwidth response
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8.3.1.2 Analog Front End Design
The ADC3564 is an unbuffered ADC and thus a passive kick-back filter is recommended to absorb the glitch
from the sampling operation. Depending on if the input is driven by a balun or a differential amplifier with low
output impedance, a termination network may be needed. Additionally a passive DC bias circuit is needed in AC-
coupled applications which can be combined with the termination network.
8.3.1.2.1 Sampling Glitch Filter Design
The front end sampling glitch filter is designed to optimize the SNR and HD3 performance of the ADC. The filter
performance is dependent on input frequency and therefore the following filter designs are recommended for
different input frequency ranges as shown in 图8-4 and 图8-5.
33 ꢀ
10 ꢀ
82 nH
33 pF
Termination
33 ꢀ
82 nH
10 ꢀ
图8-4. Sampling glitch filter example for input frequencies from DC to 60 MHz
33 ꢀ
10 ꢀ
33 pF
91 nH
75 pF
43 nH
Termination
33 ꢀ
33 pF
91 nH
10 ꢀ
图8-5. Sampling glitch filter example for input frequencies from 60 to 120 MHz
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8.3.1.2.2 Analog Input Termination and DC Bias
Depending on the input drive circuitry, a termination network and/or DC biasing needs to be provided.
8.3.1.2.2.1 AC-Coupling
The ADC3564 requires external DC bias using the common mode output voltage (VCM) of the ADC together
with the termination network as shown in 图 8-6. The termination is located within the glitch filter network. When
using a balun on the input, the termination impedance has to be adjusted to account for the turns ratio of the
transformer. When using an amplifier, the termination impedance can be adjusted to optimize the amplifier
performance.
Glitch Filter
Termination
33 ꢀ
1 uF
10 ꢀ
82 nH
25 ꢀ
33 pF
VCM
0.1 …F
25 ꢀ
33 ꢀ
1 uF
VCM
82 nH
10 ꢀ
图8-6. AC-Coupling: termination network provides DC bias (glitch filter example for up to 60 MHz)
8.3.1.2.2.2 DC-Coupling
In DC coupled applications the DC bias needs to be provided from the fully differential amplifier (FDA) using
VCM output of the ADC as shown in 图 8-7. The glitch filter in this case is located between the anti-alias filter
and the ADC. No termination may be needed if amplifier is located close to the ADC or if the termination is part
of the anti-alias filter.
Glitch Filter
33 ꢀ
10 ꢀ
82 nH
33 pF
AAF (Anti
Alias Filter)
33 ꢀ
VCM
82 nH
10 ꢀ
图8-7. DC-Coupling: DC bias provided by FDA (glitch filter example for DC - 60 MHz)
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8.3.2 Clock Input
In order to maximize the ADC SNR performance, the external sampling clock should be low jitter and differential
signaling with a high slew rate. This is especially important in IF sampling applications. For less jitter sensitive
applications, the ADC3564 provides the option to operate with single ended signaling which saves additional
power consumption.
8.3.2.1 Single Ended vs Differential Clock Input
The ADC3564 can be operated using a differential or a single ended clock input where the single ended clock
consumes less power consumption. However clock amplitude impacts the ADC aperture jitter and consequently
the SNR. For maximum SNR performance, a large clock signal with fast slew rates needs to be provided.
• Differential Clock Input: The clock input can be AC coupled externally. The ADC3564 provides internal
biasing for that use case.
• Single Ended Clock Input: This mode needs to be configured using SPI register (0x0E, D2 and D0) or with
the REFBUF pin. In this mode there is no internal clock biasing and thus the clock input needs to be DC
coupled around a 0.9V center. The unused input needs to be AC coupled to ground.
1.8V
CLKP
CLKP
0.9V
0V
+
-
5kO
VCM
0.9V
5kO
CLKM
CLKM
图8-8. External and internal connection using differential (left) and single ended (right) clock input
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8.3.3 Voltage Reference
The ADC3564 provides three different options for supplying the voltage reference to the ADC. An external 1.6 V
reference can be directly connected to the VREF input; a voltage 1.2 V reference can be connected to the
REFBUF input using the internal gain buffer or the internal 1.2V reference can be enabled to generate a 1.6 V
reference voltage. For best performance, the reference noise should be filtered by connecting a 10 uF and a 0.1
uF ceramic bypass capacitor to the VREF pin. The internal reference circuitry of the ADC3564 is shown in 图
8-9.
备注
The voltage reference mode can be selected using SPI writes or by using the REFBUF pin (default) as
a control pin (节 8.5.1). If the REFBUF pin is not used for configuration, the REFBUF pin should be
connected to AVDD (even though the REFBUF pin has a weak internal pullup to AVDD) and the
voltage reference option has to be selected using the SPI interface.
AINP
AINM
0.95V
VCM
VREF
(1.6V)
x1.33
REFBUF
(1.2V)
VREF1.2
REFGND
图8-9. Different voltage reference options for ADC3564
8.3.3.1 Internal voltage reference
The 1.6V reference for the ADC can be generated internal using the on-chip 1.2 V reference along with the
internal gain buffer. A 10 uF and a 0.1 uF ceramic bypass capacitor (CVREF) should be connected between the
VREF and REFGND pins as close to the pins as possible.
xINP
xINM
0.95V
VCM
VREF
(1.6V)
x1.33
CVREF
REFBUF
(1.6V)
VREF1.2
REFGND
图8-10. Internal reference
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8.3.3.2 External voltage reference (VREF)
For highest accuracy and lowest temperature drift, the VREF input can be directly connected to an external 1.6 V
reference. A 10 uF and a 0.1 uF ceramic bypass capacitor (CVREF) connected between the VREF and REFGND
pins and placed as close to the pins as possible is recommended. The load current from the external reference
is about 1 mA.
备注
The internal reference is also used for other functions inside the device, therefore the reference
amplifier should only be powered down in power down state but not during normal operation.
xINP
xINM
0.95V
VCM
VREF
(1.6V)
Reference
1.6V
REFBUF
(1.2V)
x1.33
CVREF
VREF1.2
REFGND
图8-11. External 1.6V reference
8.3.3.3 External voltage reference with internal buffer (REFBUF)
The ADC3564 is equipped with an on-chip reference buffer that also includes gain to generate the 1.6 V
reference voltage from an external 1.2V reference. A 10 uF and a 0.1 uF ceramic bypass capacitor (CVREF
)
between the VREF and REFGND pins and a 10 uF and a 0.1 uF ceramic bypass capacitor between the
REFBUF and REFGND pins are recommended. Both capacitors should be placed as close to the pins as
possible. The load current from the external reference is less than 100 uA.
xINP
xINM
0.95V
VCM
VREF
(1.6V)
x1.33
REFBUF
(1.2V)
Reference
1.2V
VREF1.2
CREFBUF
CVREF
REFGND
图8-12. External 1.2V reference using internal reference buffer
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8.3.4 Digital Down Converter
The ADC3564 includes an optional on-chip digital down conversion (DDC) decimation filter that can be enabled
via SPI register setting. It supports complex decimation by 2, 4, 8, 16 and 32 using a digital mixer and a 32-bit
numerically controlled oscillator (NCO) as shown in 图8-13. Furthermore it supports a mode with real decimation
where the complex mixer is bypassed (NCO should be set to 0 for lowest power consumption) and the digital
filter acts as a low pass filter.
Internally the decimation filter calculations are performed with a 20-bit resolution in order to avoid any SNR
degradation due to quantization noise. The 节 8.3.5.1 truncates to the selected resolution prior to outputting the
data on the digital interface.
NCO
32bit
Filter
I
Q
I
Q
Digital
Interface
N
ADC
SYNC
图8-13. Internal Digital Decimation Filter
8.3.4.1 DDC MUX for Dual Band Decimation
The ADC3564 includes a MUX in front of the digital decimation filter which allows the ADC to be connected to
two digital down converters (see 图 8-14). This enables dual band complex decimation. The NCO of each digital
down converter can be tuned to an independent frequency across the Nyquist zone as illustrated in the example
in 图8-15. The second DDC is output using the DB0/1 SLVDS interface.
Digital Downconverter
NCO
DDC MUX
ADC
14bit
N
NCO
N
图8-14. DDC MUX
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Decimation
by 8
Input Signal B
Input Signal A
Shifted Input Signal A
Negative Image
Shifted Input Signal B
Negative Image
0
0
-FS/16
FS/16
-FS/16
FS/16
FNCO B
FNCO A
0
FS/2
图8-15. Complex Decimation (by 8) with dual band illustration
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8.3.4.2 Digital Filter Operation
The complex decimation operation is illustrated with an example in 图 8-16. First the input signal (and the
negative image) are frequency shifted by the NCO frequency as shown on the left. Next a digital filter is applied
(centered around 0 Hz) and the output data rate is decimated - in this example the output data rate FS,OUT = FS/8
with a Nyquist zone of FS/16. During the complex mixing the spectrum (signal and noise) is split into real and
complex parts and thus the amplitude is reduced by 6-dB. In order to compensate this loss, there is a 6-dB
digital gain option in the decimation filter block that can be enabled via SPI write.
Input Signal
(Alias)
Shifted Input
Signal (Alias)
-FIN + FNCO
Shifted Input Signal
Negative Image
Input Signal
Negative Image
Decimation
by 8
FIN + FNCO
0
0
-FS/16
FS/16
FS/2
-FS/2
-FS/2
FS/2
FNCO
NCO Tuning Range
图8-16. Complex decimation illustration
The real decimation operation is illustrated with an example in 图 8-17. There is no frequency shift happening
and only the real portion of the complex digital filter is exercised. The output data rate is decimated - a
decimation of 8 would result in an output data rate FS,OUT = FS/8 with a Nyquist zone of FS/16.
During the real mixing the spectrum (signal and noise) amplitude is reduced by 3-dB. In order to compensate this
loss, there is a 3-dB digital gain option in the decimation filter block that can be enabled via SPI write.
Input Signal
Decimation by
32
Decimation by
16
Decimation by 2
Decimation by 4
Decimation by 8
FS/2
FS/16
FS/8
FS/4
FS/32
FS/64
图8-17. Real decimation illustration
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8.3.4.3 FS/4 Mixing with Real Output
In this mode, the output after complex decimation gets mixed with FS/4 (FS = output data rate in this case).
Instead of a complex output with the input signal centered around 0 Hz, the output is transmitted as a real output
at twice the data rate and the signal is centered around FS/4 (Fout/4) as illustrated in 图8-18.
In this example, complex decimation by 8 is used. The output data is transmitted as a real output with an output
rate of Fout = FS'/4 (FS' = ADC sampling rate). The input signal is now centered around FS/4 (Fout/4) or FS'/16.
FIN
FNCO
- FIN + FNCO
-FIN + FNCO + FS/4
/8
FS/4 mix
Fout/4 mix
Complex
Decimation /8
0
0
FS‘/2
FS/16
FS‘/2
FS/8
0
FS/2
图8-18. FS/4 Mixing with real output
8.3.4.4 Numerically Controlled Oscillator (NCO) and Digital Mixer
The decimation block is equipped with a 32-bit NCO and a digital mixer to fine tune the frequency placement
prior to the digital filtering. The oscillator generates a complex exponential sequence of:
ejωn (default) or e–jωn
where: frequency (ω) is specified as a signed number by the 32-bit register setting
The complex exponential sequence is multiplied with the real input from the ADC to mix the desired carrier to a
frequency equal to fIN + fNCO. The NCO frequency can be tuned from –FS/2 to +FS/2 and is processed as a
signed, 2s complement number. After programming a new NCO frequency, the MIXER RESTART register bit or
SYNC pin has to be toggled for the new frequency to get active. Additionally the ADC3564 provides the option
via SPI to invert the mixer phase.
The NCO frequency setting is set by the 32-bit register value given and calculated as:
NCO frequency = 0 to + FS/2: NCO = fNCO × 232 / FS
NCO frequency = -FS/2 to 0: NCO = (fNCO + FS) × 232 / FS
where:
• NCO = NCO register setting (decimal value)
• fNCO = Desired NCO frequency (MHz)
• FS = ADC sampling rate (MSPS)
The NCO programming is further illustrated with this example:
• ADC sampling rate FS = 125 MSPS
• Input signal fIN = 10 MHz
• Desired output frequency fOUT = 0 MHz
For this example there are actually four ways to program the NCO and achieve the desired output frequency as
shown in 表8-1.
表8-1. NCO value calculations example
Alias or negative image
fIN = –10 MHz
fNCO
NCO Value
343597384
373475417
Mixer Phase
Frequency translation for fOUT
fNCO = 10 MHz
fNCO = –10 MHz
fOUT = fIN + fNCO = –10 MHz +10 MHz = 0 MHz
fOUT = fIN + fNCO = 10 MHz + (–10 MHz) = 0 MHz
as is
fIN = 10 MHz
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表8-1. NCO value calculations example (continued)
Alias or negative image
fNCO
NCO Value
Mixer Phase
Frequency translation for fOUT
fIN = 10 MHz
fNCO = 10 MHz
343597384
fOUT = fIN –fNCO = 10 MHz –10 MHz = 0 MHz
inverted
fOUT = fIN –fNCO = –10 MHz –(–10 MHz) = 0
373475417
fIN = –10 MHz
fNCO = –10 MHz
MHz
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8.3.4.5 Decimation Filter
The ADC3564 supports complex decimation by 2, 4, 8, 16 and 32 with a pass-band bandwidth of ~ 80% and a
stopband rejection of at least 85 dB. 表 8-2 gives an overview of the pass-band bandwidth of the different
decimation settings with respect to ADC sampling rate FS. In real decimation mode the output bandwidth is half
of the complex bandwidth.
表8-2. Decimation Filter Summary and Maximum Available Output Bandwidth
REAL/COMPLEX
DECIMATION
DECIMATION
SETTING N
OUTPUT
BANDWIDTH
OUTPUT RATE
(FS = 125 MSPS)
OUTPUT BANDWIDTH
(FS = 125 MSPS)
OUTPUT RATE
2
4
FS / 2 complex
FS / 4 complex
FS / 8 complex
FS / 16 complex
FS / 32 complex
FS / 2 real
0.8 × FS / 2
0.8 × FS / 4
0.8 × FS / 8
0.8 × FS / 16
0.8 × FS / 32
0.4 × FS / 2
0.4 × FS / 4
0.4 × FS / 8
0.4 × FS / 16
0.4 × FS / 32
62.5 MSPS complex
31.25 MSPS complex
15.625 MSPS complex
7.8125 MSPS complex
3.90625 MSPS complex
62.5 MSPS
50 MHz
25 MHz
Complex
8
12.5 MHz
6.25 MHz
3.125 MHz
25 MHz
16
32
2
4
FS / 4 real
31.25 MSPS
12.5 MHz
6.25 MHz
3.125 MHz
1.5625 MHz
Real
8
FS / 8 real
15.625 MSPS
16
32
FS / 16 real
7.8125 MSPS
FS / 32 real
3.90625 MSPS
The decimation filter responses normalized to the ADC sampling clock frequency are illustrated in 图 8-20 to 图
8-29. They are interpreted as follows:
Each figure contains the filter pass-band, transition band(s) and alias or stop-band(s) as shown in 图 8-19. The
x-axis shows the offset frequency (after the NCO frequency shift) normalized to the ADC sampling rate FS.
For example, in the divide-by-4 complex setup, the output data rate is FS / 4 complex with a Nyquist zone of FS /
8 or 0.125 × FS. The transition band (colored in blue) is centered around 0.125 × FS and the alias transition band
is centered at 0.375 × FS. The stop-bands (colored in red), which alias on top of the pass-band, are centered at
0.25 × FS and 0.5 × FS. The stop-band attenuation is greater than 85 dB.
0
Passband
Transition Band
-20
Alias Band
Attn Spec
Filter
-40
-60
Transition
Bands
Bands that alias on top
of signal band
Pass Band
-80
-100
-120
0
0.1
0.2
0.3
0.4
0.5
Normalized Frequency (Fs)
图8-19. Interpretation of the Decimation Filter Plots
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0
-20
0.1
0.09
0.08
0.07
0.06
0.05
0.04
0.03
0.02
0.01
0
Passband
Passband
Transition Band
Alias Band
Attn Spec
Transition Band
Alias Band
Attn Spec
-40
-60
-0.01
-0.02
-0.03
-0.04
-0.05
-0.06
-0.07
-0.08
-0.09
-0.1
-80
-100
-120
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
0
0.025 0.05 0.075
0.1
0.125 0.15 0.175
0.2
0.225 0.25
Normalized Frequency (Fs)
Normalized Frequency (Fs)
Decb
Decb
图8-20. Decimation by 2 complex frequency
图8-21. Decimation by 2 complex passband ripple
response
response
0
0
Passband
Transition Band
Alias Band
Passband
Transition Band
Alias Band
Attn Spec
-0.01
-0.02
-20
-40
Attn Spec
-0.03
-0.04
-0.05
-0.06
-0.07
-0.08
-0.09
-0.1
-60
-80
-100
-120
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
0
0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1 0.11 0.12
Normalized Frequency (Fs)
Normalized Frequency (Fs)
Decb
Decb
图8-22. Decimation by 4 complex frequency
图8-23. Decimation by 4 complex passband ripple
response
response
0
-0.08
Passband
Transition Band
Alias Band
Passband
-0.081
-0.082
-0.083
-0.084
-0.085
-0.086
-0.087
-0.088
-0.089
-0.09
Transition Band
Alias Band
Attn Spec
-20
-40
Attn Spec
-60
-0.091
-0.092
-0.093
-0.094
-0.095
-0.096
-0.097
-0.098
-0.099
-0.1
-80
-100
-120
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
0
0.006 0.012 0.018 0.024 0.03 0.036 0.042 0.048 0.054 0.06
Normalized Frequency (Fs)
Normalized Frequency (Fs)
Decb
Decb
图8-24. Decimation by 8 complex frequency
图8-25. Decimation by 8 complex passband ripple
response
response
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0
-0.1
-0.11
-0.12
-0.13
-0.14
-0.15
-0.16
-0.17
-0.18
-0.19
-0.2
Passband
Passband
Transition Band
Alias Band
Attn Spec
Transition Band
Alias Band
Attn Spec
-20
-40
-60
-80
-100
-120
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
0
0.003 0.006 0.009 0.012 0.015 0.018 0.021 0.024 0.027 0.03
Normalized Frequency (Fs)
Normalized Frequency (Fs)
Decb
Decb
图8-26. Decimation by 16 complex frequency
图8-27. Decimation by 16 complex passband
response
ripple response
0
-0.2
Passband
Transition Band
Alias Band
Passband
Transition Band
Alias Band
Attn Spec
-0.205
-0.21
-20
-40
Attn Spec
-0.215
-0.22
-60
-0.225
-0.23
-80
-0.235
-0.24
-100
-120
-0.245
-0.25
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
0
0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018 0.02
Normalized Frequency (Fs)
Normalized Frequency (Fs)
Decb
Decb
图8-28. Decimation by 32 complex frequency
图8-29. Decimation by 32 complex passband
response
ripple response
8.3.4.6 SYNC
The PDN/SYNC pin can be used to synchronize multiple devices using an external SYNC signal. The PDN/
SYNC pin can be configured via SPI (SYNC EN bit) from power down to synchronization functionality and is
latched in by the rising edge of the sampling clock as shown in 图8-30.
CLK
tS,SYNC
tH,SYNC
SYNC
图8-30. External SYNC timing diagram
The synchronization signal is only required when using the decimation filter - either using the SPI SYNC register
or the PDN/SYNC pin. It resets internal clock dividers used in the decimation filter and aligns the internal clocks
as well as I and Q data within the same sample. If no SYNC signal is given, the internal clock dividers is not be
synchronized, which can lead to a fractional delay across different devices. The SYNC signal also resets the
NCO phase and loads the new NCO frequency (same as the MIXER RESTART bit).
When trying to resynchronize during operation, the SYNC toggle should occur at 64*K clock cycles, where K is
an integer. This provids the phase continuity of the clock divider.
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8.3.4.7 Output Formatting with Decimation
When using decimation, the digital output data is formatted as shown in 图 8-31 (complex decimation) and 图
8-32 (real decimation). The output format is illustrated for 16-bit output resolution.
FCLK
AI
AI
AI
D15 D13 D11
AI
D9
AI
D7
AI
D5
AI
D3
AI
D1
AQ
AQ
AQ
D15 D13 D11
AQ
D9
AQ
D7
AQ
D5
AQ
D3
AQ
D1
DA1
DA0
DB1
Used in
Single
Band
AI AI
D14 D12 D10
AI
AI
D8
AI
D6
AI
D4
AI
D2
AI
D0
AQ AQ
D14 D12 D10
AQ
AQ
D8
AQ
D6
AQ
D4
AQ
D2
AQ
D0
Serial LVDS
2-Wire
(8x Serialization)
BI BI
D15 D13 D11
BI
BI
D9
BI
D7
BI
D5
BI
D3
BI
D1
BQ BQ
D15 D13 D11
BQ
BQ
D9
BQ
D7
BQ
D5
BQ
D3
BQ
D1
Only used for
Dual Band
BI
BI
BI
D14 D12 D10
BI
D8
BI
D6
BI
D4
BI
D2
BI
D0
BQ
BQ
BQ
D14 D12 D10
BQ
D8
BQ
D6
BQ
D4
BQ
D2
BQ
D0
DB0
DCLK
FCLK
DA0
DB0
Used in
Single Band
AI <15:0>
BI <15:0>
AQ <15:0>
BQ <15:0>
Serial LVDS
1-Wire
(16x Serialization) Only used for
Dual Band
DCLK
FCLK
Serial LVDS
1/2-Wire
(32x Serialization)
Only used for
Dual Band
AI <15:0>
BI <15:0>
AQ <15:0>
BQ <15:0>
DA0
DCLK
图8-31. Output Data Format in Complex Decimation
表 8-3 illustrates the output interface data rate along with the corresponding DCLK/DCLKIN and FCLK
frequencies based on output resolution (R), number of SLVDS lanes (L) and complex decimation setting (N).
Furthermore the table shows an actual lane rate example for the 2-, 1- and 1/2-wire interface, 16-bit output
resolution and complex decimation by 4.
表8-3. Serial LVDS Lane Rate Examples with Complex Decimation and 16-bit Output Resolution
DECIMATION
SETTING
ADC SAMPLING
RATE
OUTPUT
RESOLUTION
# of WIRES
FCLK
DCLKIN, DCLK
DA/B0,1
N
FS
R
L
2
FS / N
[DA/B0,1] / 2
250 MHz
FS x 2 x R / L / N
500 MHz
125 MSPS
55 MSPS
31.25 MHz
4
16
1
500 MHz
1000 MHz
1/2
15.625 MHz
500 MHz
1000 MHz
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FCLK
DA1
DA0
DCLK
A0
A0
A0
A0
D9
A0
D7
A0
D5
A0
D3
A0
D1
A1
A1
A1
D11
A1
D9
A1
D7
A1
D5
A1
D3
A1
D1
D15 D13 D11
D15 D13
2-Wire
8x Serialization
A0 A0
D14 D12 D10
A0
A0
D8
A0
D6
A0
D4
A0
D2
A0
D0
A1 A1
D14 D12 D10
A1
A1
D8
A1
D6
A1
D4
A1
D2
A1
D0
FCLK
DA0
1-Wire
16x Serialization
A0 <15:0>
A1 <15:0>
DCLK
图8-32. Output Data Format in Real Decimation
表 8-4 illustrates the output interface data rate along with the corresponding DCLK/DCLKIN and FCLK
frequencies based on output resolution (R), number of SLVDS lanes (L) and real decimation setting (M).
Furthermore the table shows an actual lane rate example for the 2-, 1- and 1/2-wire interface, 16-bit output
resolution and real decimation by 4.
表8-4. Serial LVDS Lane Rate Examples with Real Decimation and 16-bit Output Resolution
DECIMATION
SETTING
ADC SAMPLING
RATE
OUTPUT
RESOLUTION
# of WIRES
FCLK
DCLKIN, DCLK
DA/B0,1
FS / M / 2 (L = 2)
FS / M (L = 1, 1/2)
M
FS
R
L
[DA/B0,1] / 2
FS x R / L / M
2
1
15.625 MHz
125 MHz
250 MHz
500 MHz
250 MHz
500 MHz
1000 MHz
4
125 MSPS
16
31.25 MHz
1/2
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8.3.5 Digital Interface
The serial LVDS interface supports the data output with 2-wire, 1-wire and 1/2-wire operation. The actual data
output rate depends on the output resolution and number of lanes used.
The ADC3564 requires an external serial LVDS clock input (DCLKIN), which is used to transmit the data out of
the ADC along with the data clock (DCLK). The phase relationship between DCLKIN and the sampling clock is
irrelevant but both clocks need to be frequency locked. The SLVDS interface is configured using SPI register
writes.
8.3.5.1 Output Formatter
The digital output interface utilizes a flexible output bit mapper as shown in 图8-33. The bit mapper takes the 14-
bit output directly from the ADC or from digital filter block and reformats it to a resolution of 14, 16, 18 or 20-bit.
The output serialization factor gets adjusted accordingly for 2-, 1- and 1/2-wire interface modes. The maximum
SLVDS interface output data rate can not be exceeded independent of output resolution or serialization factor.
When using a higher resolution like 16-bit output for example in non-decimation mode, the 2 LSBs are set to 0.
DIG
I/F
Output
Formatter
14/16/18/
20-bit
NCO
TEST
Output
Bit Mapper
PATTERN
N
图8-33. Interface output bit mapper
表 8-5 provides an overview for the resulting serialization factor depending on output resolution and output
modes. Note that the DCLKIN frequency needs to be adjusted accordingly as well. Changing the output
resolution to 16-bit, 2-wire mode for example would result in DCLKIN = FS * 4 instead of * 3.5.
The output bit mapper can be used for bypass and decimation filter.
表8-5. Serialization factor vs output resolution for different output modes
OUTPUT
RESOLUTION
Interface SERIALIZATION
FCLK
DCLKIN
DCLK
D0/D1
2-Wire
1-Wire
7x
FS/2
FS
FS* 3.5
FS* 7
FS* 3.5
FS* 7
FS* 7
FS* 14
FS* 28
FS* 8
14-bit (default)
14x
28x
8x
1/2-Wire
2-Wire
FS
FS* 14
FS* 4
FS* 14
FS* 4
FS/2
FS
16-bit
18-bit
20-bit
1-Wire
16x
32x
9x
FS* 8
FS* 8
FS* 16
FS* 32
FS* 9
1/2-Wire
2-Wire
FS
FS* 16
FS* 4.5
FS* 9
FS* 16
FS* 4.5
FS* 9
FS/2
FS
1-Wire
18x
36x
10x
20x
40x
FS* 18
FS* 36
FS* 10
FS* 20
FS* 40
1/2-Wire
2-Wire
FS
FS* 18
FS* 5
FS* 18
FS* 5
FS/2
FS
1-Wire
FS* 10
FS* 20
FS* 10
FS* 20
1/2-Wire
FS
The programming sequence to change the output interface and/or resolution from default settings is shown in 节
8.3.5.3.
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8.3.5.2 Output Bit Mapper
The output bit mapper allows to change the output bit order for any selected interface mode.
DIG
I/F
Output
Formatter
14/16/18/
20-bit
NCO
TEST
PATTERN
Output
Bit Mapper
N
图8-34. Output Bit Mapper
It is a two step process to change the output bit mapping and assemble the output data bus:
1. Both channel A and B can have up to 20-bit output. Each output bit of either channel has a unique identifier
bit as shown in 表8-6. The MSB starts with bit D19 –depending on output resolution chosen the LSB would
be D6 (14-bit) to D0 (20-bit). The previous sample is only needed in 2-w mode.
2. The bit mapper is then used to assemble the output sample. The following sections detail how to remap the
serial output format.
表8-6. Unique identifier of each data bit
Bit
Channel A
Channel B
Previous sample (2w only)
Current sample
0x6D
0x6C
0x67
Previous sample (2w only)
Current sample
0x69
D19 (MSB)
D18
D17
D16
D15
D14
D13
D12
D11
D10
D9
0x2D
0x2C
0x27
0x26
0x25
0x24
0x1F
0x1E
0x1D
0x1C
0x17
0x16
0x15
0x14
0x0F
0x0E
0x0D
0x0C
0x07
0x06
0x29
0x28
0x23
0x22
0x21
0x20
0x1B
0x1A
0x19
0x18
0x13
0x12
0x11
0x10
0x0B
0x0A
0x09
0x08
0x03
0x02
0x68
0x63
0x66
0x62
0x65
0x61
0x64
0x60
0x5F
0x5B
0x5A
0x59
0x5E
0x5D
0x5C
0x57
0x58
0x53
D8
0x56
0x52
D7
0x55
0x51
D6
0x54
0x50
D5
0x4F
0x4B
0x4A
0x49
D4
0x4E
0x4D
0x4C
0x47
D3
D2
0x48
D1
0x43
D0 (LSB)
0x46
0x42
In the serial output mode, a data bit (with unique identifier) needs to be assigned to each location within the
serial output stream. There are a total of 40 addresses available per channel. Channel A spans from address
0x39 to 0x60 and channel B from address 0x61 to 0x88. When using complex decimation, the output bit mapper
is applied to both the “I”and the “Q”sample.
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2-wire mode: in this mode both the current and the previous sample have to be used in the address space as
shown in 图 8-35. The address order is different for 14/18-bit and 16/20-bit. Note: there are unused addresses
between samples for resolution less than 20-bit (grey back ground), which can be skipped if not used.
14-bit
16-bit 18-bit 20-bit
14-bit
16-bit 18-bit 20-bit
0x55 0x56 0x53 0x54 0x51 0x52 0x4F 0x50 0x4D 0x4E
0x56 0x55 0x54 0x53 0x52 0x51 0x50 0x4F 0x4E 0x4D
14/18-bit 0x5F 0x60 0x5D 0x5E 0x5B 0x5C 0x59 0x5A 0x57 0x58
0x60 0x5F 0x5E 0x5D 0x5C 0x5B 0x5A 0x59 0x58 0x57
DA1
DA0
16/20-bit
14/18-bit 0x4B 0x4C 0x49 0x4A 0x47 0x48 0x45 0x46 0x43 0x44 0x41 0x42 0x3F 0x40 0x3D 0x3E 0x3B 0x3C 0x39 0x3A
16/20-bit 0x4C 0x4B 0x4A 0x49 0x48 0x47 0x46 0x45 0x44 0x43 0x42 0x41 0x40 0x3F 0x3E 0x3D 0x3C 0x3B 0x3A 0x39
14/18-bit 0x87 0x88 0x85 0x85 0x83 0x83 0x81 0x81 0x7F 0x7F 0x7D 0x7E 0x7B 0x7C 0x79 0x7A 0x77 0x78 0x75 0x76
16/20-bit 0x88 0x87 0x86 0x86 0x84 0x84 0x82 0x82 0x80 0x80 0x7E 0x7D 0x7C 0x7B 0x7A 0x79 0x78 0x77 0x76 0x75
DB1
DB0
0x73 0x74 0x71 0x72 0x6F 0x70 0x6D 0x6E 0x6B 0x6C 0x69 0x6A 0x67 0x68 0x65 0x66 0x63 0x64 0x61 0x62
0x74 0x73 0x72 0x71 0x70 0x6F 0x6E 0x6D 0x6C 0x6B 0x6A 0x69 0x68 0x67 0x66 0x65 0x64 0x63 0x62 0x61
14/18-bit
16/20-bit
Previous Sample
Current Sample
图8-35. 2-wire output bit mapper
In the following example (图8-36), the 16-bit 2-wire serial output is reordered to where lane DA1/DB1 carries the
8 MSB and lane DA0/DB0 carries 8 LSBs.
Previous Sample
Current Sample
D19A
(0x60
0x2D)
D18A
(0x5F
0x2C)
D17A
(0x5E
0x27)
D16A
(0x5D
0x26)
D15A
(0x5C
0x25)
D14A
(0x5B
0x24)
D13A
(0x5A
0x1F)
D12A
(0x59
0x1E)
D19A
(0x56
0x6D)
D18A
(0x55
0x6C)
D17A
(0x54
0x67)
D16A
(0x53
0x66)
D15A
(0x52
0x65)
D14A
(0x51
0x64)
D13A
(0x50
0x5F)
D12A
(0x4F
0x5E)
DA1
DA0
D11A
(0x4C
0x1D)
D10A
(0x4B
0x1C)
D9A
(0x4A
0x17)
D8A
(0x49
0x16)
D7A
(0x48
0x15)
D6A
(0x47
0x14)
D5A
(0x46
0x0F)
D4A
(0x45
0x0E)
D11A
(0x42
0x5D)
D10A
(0x41
0x5C)
D9A
(0x40
0x57)
D8A
(0x39
0x56)
D7A
(0x38
0x55)
D6A
(0x37
0x54)
D5A
(0x36
0x4F)
D4A
(0x35
0x4E)
D19B
(0x88
0x29)
D18B
(0x87
0x28)
D17B
(0x86
0x23)
D16B
(0x85
0x22)
D15B
(0x84
0x21)
D14B
(0x83
0x20)
D13B
(0x82
0x1B)
D12B
(0x81
0x1A)
D19B
(0x7E
0x69)
D18B
(0x7D
0x68)
D17B
(0x7C
0x63)
D16B
(0x7B
0x62)
D15B
(0x7A
0x61)
D14B
(0x79
0x60)
D13B
(0x78
0x5B)
D12B
(0x77
0x5A)
DB1
DB0
D11B
(0x74
0x19)
D10B
(0x73
0x18)
D9B
(0x72
0x13)
D8B
(0x71
0x12)
D7B
(0x70
0x11)
D6B
(0x6F
0x10)
D5B
(0x6E
0x0B)
D4B
(0x6D
0x0A)
D11B
(0x6A
0x59)
D10B
(0x69
0x58)
D9B
(0x68
0x53)
D8B
(0x67
0x52)
D7B
(0x66
0x51)
D6B
(0x65
0x50)
D5B
(0x64
0x4B)
D4B
(0x63
0x4A)
图8-36. Example: 2-wire output bit mapping
1-wire mode: Only the current sample needs to programmed in the address space. If desired, it can be
duplicated on DA1/DB1 as well (using addresses shown below) in order to have a redundant output. Lane
DA1/DB1 needs to be powered up in that case.
14-bit
16-bit
18-bit
20-bit
DA0
(default)
0x4C 0x4B 0x4A 0x49 0x48 0x47 0x46 0x45 0x44 0x43 0x42 0x41 0x40 0x3F 0x3E 0x3D 0x3C 0x3B 0x3A 0x39
0x60 0x5F 0x5E 0x5D 0x5C 0x5B 0x5A 0x59 0x58 0x57 0x56 0x55 0x54 0x53 0x52 0x51 0x50 0x4F 0x4E 0x4D
DA1
DB0
(default)
0x74 0x73 0x72 0x71 0x70 0x6F 0x6E 0x6D 0x6C 0x6B 0x6A 0x69 0x68 0x67 0x66 0x65 0x64 0x63 0x62 0x61
0x88 0x87 0x86 0x85 0x84 0x83 0x82 0x81 0x80 0x7F 0x7E 0x7D 0x7C 0x7B 0x7A 0x79 0x78 0x77 0x76 0x75
DB1
图8-37. 1-wire output bit mapping
½-wire mode: The output is only lane DA0 and the sample order is programmed into the 40 addresses of chA
(from 0x39 to 0x60). It covers 2 samples (one for chA, one for chB) as shown below. If desired it can be
duplicated on DB0 as well (using addresses shown 图 8-38) in order to have a redundant output. Lane DB0
needs to be powered up in that case.
14-bit
16-bit
18-bit
20-bit
16-bit
18-bit
20-bit
14-bit
DA0
(default)
...
...
0x4C 0x4B
0x88 0x87
0x40 0x3F 0x3E 0x3D 0x3C 0x3B 0x3A 0x39 0x60 0x5F
0x7C 0x7B 0x7A 0x79 0x78 0x77 0x76 0x75 0x74 0x73
0x54 0x53 0x52 0x51 0x50 0x4F 0x4E 0x4D
0x68 0x67 0x66 0x65 0x64 0x63 0x62 0x61
...
...
DB0
图8-38. 1/2-wire output bit mapping
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8.3.5.3 Output Interface/Mode Configuration
The following sequence summarizes all the relevant registers for changing the output interface and/or enabling
the decimation filter. Steps 1 and 2 must come first since the E-Fuse load reset the SPI writes, the remaining
steps can come in any order.
表8-7. Configuration steps for changing interface or decimation
STEP
FEATURE
ADDRESS
DESCRIPTION
Select the output interface bit mapping depending on resolution and output interface.
Output Resolution
14-bit
2-wire
0x2B
0x4B
0x2B
0x4B
1-wire
1/2-wire
0x8D
1
0x07
16-bit
0x6C
18-bit
20-bit
Load the output interface bit mapping using the E-fuse loader (0x13, D0). Program register 0x13 to
0x01, wait ~ 1ms so that bit mapping is loaded properly followed by 0x13 0x00.
2
0x13
Configure the FCLK frequency based on bypass/decimation and number of lanes used.
FCLK SRC
(D7)
FCLK DIV
(D4)
TOG FCLK
(D0)
Bypass/Dec
SLVDS
2-wire
1-wire
0
0
0
1
1
0
1
0
0
0
0
0
0
0
0
0
0
1
Bypass/ Real
Decimation
3
4
0x19
0x1B
1/2-wire
2-wire
Output
Interface
Complex
Decimation
1-wire
1/2-wire
Select the output interface resolution using the bit mapper (D5-D3).
Select the FCLK pattern for decimation for proper duty cycle output of the frame clock.
Output Resolution
14-bit
2-wire
1-wire
1/2-wire
0xFE000
0xFF000
0xFF800
0xFFC00
16-bit
Real Decimation
use default
0x20
0x21
0x22
18-bit
5
20-bit
use default
14-bit
16-bit
Complex
Decimation
0xFFFFF
0xFFFFF
18-bit
20-bit
0x39..0x60 Change output bit mapping for chA and chB if desired. This works also with the default interface
0x61..0x88 selection.
6
7
8
0x24
0x25
Enable the decimation filter
Configure the decimation filter
0x2A/B/C/D
0x31/2/3/4
9
Program the NCO frequency for complex decimation (can be skipped for real decimation)
Configure the complex output data stream (set both bits to 0 for real decimation)
Decimation
Filter
SLVDS
2-wire
OP-Order (D4)
Q-Delay (D3)
0x27
0x2E
10
11
1
0
1
0
1
1
1-wire
1/2-wire
0x26
Set the mixer gain and toggle the mixer reset bit to update the NCO frequency.
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8.3.5.3.1 Configuration Example
The following is a step by step programming example to configure the ADC3564 to complex decimation by 8 with
1-wire SLVDS and 16-bit output.
1. 0x07 (address) 0x6C (load bit mapper configuration for 16-bit output with 1-wire SLVDS)
2. 0x13 0x01 (load e-fuse), wait 1 ms, 0x13 0x00
3. 0x19 0x80 (configure FCLK)
4. 0x1B 0x88 (select 16-bit output resolution)
5. 0x20 0xFF, 0x21 0xFF, 0x22 0x0F (configure FCLK pattern)
6. 0x24 0x06 (enable decimation filter)
7. 0x25 0x30 (configure complex decimation by 8)
8. 0x2A/B/C/D and 0x31/32/33/34 (program NCO frequency)
9. 0x27/0x2E 0x08 (configure Q-delay register bit)
10. 0x26 0xAA, 0x26 0x88 (set digital mixer gain to 6-dB and toggle the mixer update)
8.3.5.4 Output Data Format
The output data can be configured to two's complement (default) or offset binary formatting using SPI register
writes (register 0x8F and 0x92). 表 8-8 provides an overview for minimum and maximum output codes for the
two formatting options. The actual output resolution is set by the output bit mapper.
表8-8. Overview of minimum and maximum output codes vs output resolution for different formatting
Two's Complement (default)
Offset Binary
RESOLUTION (BIT)
14
16
14
16
VIN,MAX
0
0x1FFF
0x7FFF
0x3FFF
0x2000
0xFFFF
0x8000
0x0000
VIN,MIN
0x2000
0x8000
0x0000
8.3.6 Test Pattern
In order to enable in-circuit testing of the digital interface, the following test patterns are supported and enabled
via SPI register writes (0x14/0x15/0x16). The test pattern generator is located after the decimation filter as
shown in 图 8-39. In decimation mode (real and complex), the test patterns replace the output data of the DDC -
however channel A controls the test patterns for both channels.
DIG
I/F
Output
Formatter
14/16/18/
20-bit
NCO
TEST
Output
Bit Mapper
PATTERN
N
图8-39. Test Pattern Generator
• RAMP Pattern: The step size needs to be configured in the CUSTOM PAT register according to the native
resolution of the ADC. When selecting a higher output resolution then the additional LSBs will still be 0 in
RAMP pattern mode.
– 00001: 18-bit output resolution
– 00100: 16-bit output resolution
– 10000: 14-bit output resolution
• Custom Pattern: Configured in the CUSTOM PAT register
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8.4 Device Functional Modes
8.4.1 Normal operation
In normal operating mode, the entire ADC full scale range gets converted to a digital output with 14-bit
resolution. The output is available in as little as 1 clock cycle with 1-wire SLVDS interface.
8.4.2 Power Down Options
A global power down mode can be enabled via SPI as well as using the power down pin (PDN/SYNC). There is
an internal pull-down 21 kΩ resistor on the PDN/SYNC input pin and the pin is active high - so the pin needs to
be pulled high externally to enter global power down mode.
The SPI register map provides the capability to enable/disable individual blocks directly or via PDN pin mask in
order to trade off power consumption vs wake up time as shown in 表8-9.
REFBUF
VREF
AIN
1.2V REF
Digital Downconverter
Crosspoint
Switch
NCO
N
ADC
Dig I/F
CLK
图8-40. Power Down Configurations
表8-9. Overview of Power Down Options
PDN
via SPI
Mask for
Global PDN
Feature -
Default
Power
Impact
Wake-up
time
Function/ Register
ADC
Comment
ADC is included in Global PDN
automatically
Yes
-
Enabled
Enabled
Should only be powered down in power
down state.
Reference gain amplifier
Internal 1.2V reference
Yes
Yes
~ 0.4 mA
~3 us
Internal/external reference selection is
available through SPI and REFBUF pin.
External ref
~ 1-3.5 mA
~3 ms
Yes
Single ended clock input saves ~ 1mA
compared to differential.
Some programmability is available
through the REFBUF pin.
Differential
clock
Clock buffer
Yes
~ 1 mA
varies
n/a
Depending on output interface mode,
unused output drivers can be powered
down for maximum power savings
Output interface drivers
Decimation filter
Yes
Yes
-
-
Enabled
Disabled
n/a
n/a
see electrical
table
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8.5 Programming
The device is primarily configured and controlled using the serial programming interface (SPI) however it can
operate in a default configuration without requiring the SPI interface. Furthermore the power down function as
well as internal/external reference configuration is possible via pin control (PDN/SYNC and REFBUF pin).
备注
The power down command (via PIN or SPI) only goes in effect with the ADC sampling clock present.
After initial power up, the default operating configuration is shown in 表8-10.
表8-10. Default device configuration after power up
FEATURE
Signal Input
Clock Input
Reference
DEFAULT
Differential
Differential
External
Decimation
Interface
DDC bypass
2-wire
Output Format
2s complement
8.5.1 Configuration using PINs only
The ADC voltage reference can be selected using the REFBUF pin. Even though there is an internal 100 kΩ
pull-up resistor to AVDD, the REFBUF pin should be set to a voltage externally and not left floating.
When using a voltage divider to set the REFBUF voltage (R1 and R2 in 表 8-11), resistor values < 5 kΩ should
be used.
AVDD
R1
AVDD
100 k
REFBUF
R2
图8-41. Configuration of external voltage on REFBUF pin
表8-11. REFBUF voltage levels control voltage reference selection
REFBUF VOLTAGE
VOLTAGE REFERENCE OPTION
CLOCKING OPTION
> 1.7 V (Default)
1.2 V (1.15-1.25V)
0.5 - 0.7V
External reference
Differential clock input
Differential clock input
Differential clock input
Single ended clock input
External 1.2V input on REFBUF pin using internal gain buffer
Internal reference
< 0.1V
Internal reference
8.5.2 Configuration using the SPI interface
The device has a set of internal registers that can be accessed by the serial interface formed by the SEN (serial
interface enable), SCLK (serial interface clock) and SDIO (serial interface data input/output) pins. Serially shifting
bits into the device is enabled when SEN is low. Serial data input are latched at every SCLK rising edge when
SEN is active (low). The serial data are loaded into the register at every 24th SCLK rising edge when SEN is low.
When the word length exceeds a multiple of 24 bits, the excess bits are ignored. Data can be loaded in multiples
of 24-bit words within a single active SEN pulse. The interface can function with SCLK frequencies from 12 MHz
down to very low speeds (of a few hertz) and also with a non-50% SCLK duty cycle.
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8.5.2.1 Register Write
The internal registers can be programmed following these steps:
1. Drive the SEN pin low
2. Set the R/W bit to 0 (bit A15 of the 16-bit address) and bits A[14:12] in address field to 0.
3. Initiate a serial interface cycle by specifying the address of the register (A[11:0]) whose content is written and
4. Write the 8-bit data that are latched in on the SCLK rising edges
图8-42 shows the timing requirements for the serial register write operation.
Register Address <11:0>
A7 A6 A5 A4
Register Data <7:0>
R/W
0
SDIO
0
0
0
A11 A10
A9
A8
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
tH,SDIO
tSCLK
tS,SDIO
SCLK
SEN
tS,SEN
tH,SEN
RESET
图8-42. Serial Register Write Timing Diagram
8.5.2.2 Register Read
The device includes a mode where the contents of the internal registers can be read back using the SDIO pin.
This readback mode can be useful as a diagnostic check to verify the serial interface communication between
the external controller and the ADC. The procedure to read the contents of the serial registers is as follows:
1. Drive the SEN pin low
2. Set the R/W bit (A15) to 1. This setting disables any further writes to the registers. Set A[14:12] in address
field to 0.
3. Initiate a serial interface cycle specifying the address of the register (A[11:0]) whose content must be read
4. The device launches the contents (D[7:0]) of the selected register on the SDIO pin on SCLK falling edge
5. The external controller can capture the contents on the SCLK rising edge
Register Address <11:0>
Register Data <7:0>
R/W
1
tOZD
A0
tOD
SDIO
0
0
0
A11 A10
A9
A8
A7 A6 A5 A4
A3
A2
A1
D7
D6
D5 D4 D3
D2
D1
D0
SCLK
SEN
tODZ
图8-43. Serial Register Read Timing Diagram
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8.6 Register Maps
表8-12. Register Map Summary
REGISTER
ADDRESS
REGISTER DATA
A[11:0]
0x00
D7
D6
D5
D4
D3
D2
D1
0
D0
0
0
0
0
0
0
0
RESET
0x07
OP IF MAPPER
0
OP IF EN
0
OP IF SEL
PDN
PDN
GLOBAL
0x08
0x09
0x0D
0x0E
0
0
0
PDN CLKBUF
PDN A
1
REFAMP
PDN
FCLKOUT
PDN
0
0
PDN DA1
PDN DA0
PDN DB1
PDN DB0
0
DCLKOUT
MASK
MASK
REFAMP
MASK BG
DIS
0
0
0
CLKBUF
SYNC PIN
EN
SPI SYNC SPI SYNC EN
REF CTRL
REF SEL
SE CLK EN
0x11
0x13
0x14
0x15
0x16
0x19
0x1A
0x1B
0x1E
0x20
0x21
0x22
0x24
0x25
0x26
0
0
0
0
SE A
0
0
0
0
0
0
0
0
0
0
E-FUSE LD
CUSTOM PAT [7:0]
CUSTOM PAT [15:8]
TEST PAT A
TEST PAT B
CUSTOM PAT [17:16]
FCLK SRC
0
0
0
FCLK DIV
LVDS SWING HIGH
BIT MAPPER RES
0
0
0
0
0
TOG FCLK
0
0
20B EN
0
LVDS SWING LOW
0
MAPPER EN
0
0
LVDS DATA DEL
LVDS DCLK DEL
FCLK PAT [7:0]
FCLK PAT [15:8]
0
0
0
0
0
FCLK PAT [19:16]
0
0
DDC MUX
DIG BYP
0
DDC EN
0
0
DDC MUX EN
DECIMATION
MIX RES A
REAL OUT
MIX PHASE
FS/4 MIX B
MIX GAIN A
FS/4 MIX A
MIX GAIN B
MIX RES B
FS/4 MIX PH
A
0x27
0
0
0
0
0
OP ORDER A
Q-DEL A
0
0
0x2A
0x2B
0x2C
0x2D
NCO A [7:0]
NCO A [15:8]
NCO A [23:16]
NCO A [31:24]
FS/4 MIX PH
B
0x2E
0
OP ORDER B
Q-DEL B
0
0
0x31
0x32
NCO B [7:0]
NCO B [15:8]
0x33
NCO B [23:16]
0x34
NCO B [31:24]
0x39..0x60
0x61..0x88
0x8F
OUTPUT BIT MAPPER CHA
OUTPUT BIT MAPPER CHB
0
0
0
0
0
0
0
0
0
0
0
0
FORMAT A
FORMAT B
0
0
0x92
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8.6.1 Detailed Register Description
图8-44. Register 0x00
7
0
6
0
5
0
4
3
2
0
1
0
0
0
0
RESET
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
表8-13. Register 0x00 Field Descriptions
Bit
Field
0
Type
R/W
R/W
Reset
Description
7-1
0
0
0
Must write 0
RESET
This bit resets all internal registers to the default values and self
clears to 0.
图8-45. Register 0x07
7
6
5
4
3
2
1
0
OP IF MAPPER
R/W-0
0
OP IF EN
R/W-0
OP IF SEL
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
表8-14. Register 0x07 Field Descriptions
Bit
Field
Type
Reset
Description
7-5
OP IF MAPPER
R/W
000
Output interface mapper. This register contains the proper
output interface bit mapping for the different interfaces. The
interface bit mapping is internally loaded from e-fuses and also
requires a fuse load command to go into effect (0x13, D0).
Register 0x07 along with the E-Fuse Load (0x13, D0) needs to
be loaded first in the programming sequence since the E-Fuse
load resets the SPI writes.
After initial reset the default output interface variant is loaded
automatically from fuse internally. However when reading back
this register reads 000 until a value is written using SPI.
001: 2-wire, 18 and 14-bit
010: 2-wire, 16-bit
011: 1-wire
100: 0.5-wire
others: not used
4
3
0
R/W
R/W
R/W
0
Must write 0
OP IF EN
OP IF SEL
0
Enables changing the default output interface mode (D2-D0).
2-0
000
Selection of the output interface mode. OP IF EN (D3) needs to
be enabled also.
After initial reset the default output interface is loaded
automatically from fuse internally. However when reading back
this register reads 000 until a value is written using SPI.
011: 2-wire
100: 1-wire
101: 0.5-wire
others: not used
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图8-46. Register 0x08
7
0
6
0
5
4
3
2
1
1
0
PDN CLKBUF PDN REFAMP
R/W-0 R/W-0
0
PDN A
R/W-0
PDN GLOBAL
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
表8-15. Register 0x08 Field Descriptions
Bit
Field
Type
R/W
R/W
Reset
Description
7-6
5
0
0
0
Must write 0
PDN CLKBUF
Powers down sampling clock buffer
0: Clock buffer enabled
1: Clock buffer powered down
4
PDN REFAMP
R/W
0
Powers down internal reference gain amplifier
0: REFAMP enabled
1: REFAMP powered down
3
2
0
R/W
R/W
0
0
Must write 0
Powers down ADC channel A
0: ADC channel A enabled
PDN A
1: ADC channel A powered down
1
0
R/W
R/W
Must write 1
1
1
0
PDN GLOBAL
Global power down via SPI
0: Global power disabled
1: Global power down enabled. Power down mask (register
0x0D) determines which internal blocks are powered down.
图8-47. Register 0x09
7
0
6
0
5
4
3
2
1
0
PDN FCLKOUT PDN DCLKOUT
R/W-0 R/W-0
PDN DA1
R/W-0
PDN DA0
R/W-0
PDN DBA1
R/W-0
PDN DB0
R/W-0
R/W-0
R/W-0
表8-16. Register 0x09 Field Descriptions
Bit
Field
Type
R/W
R/W
Reset
Description
7-6
5
0
0
0
Must write 0
PDN FCLKOUT
Powers down frame clock (FCLK) LVDS output buffer
0: FCLK output buffer enabled
1: FCLK output buffer powered down
4
3
PDN DCLKOUT
PDN DA1
R/W
R/W
0
1
Powers down DCLK LVDS output buffer
0: DCLK output buffer enabled
1: DCLK output buffer powered down
Powers down LVDS output buffer for channel A, lane 1.
Powered down automatically in 1-wire and 1/2-wire mode.
0: DA1 LVDS output buffer enabled
1: DA1 LVDS output buffer powered down
2
1
PDN DA0
PDN DB1
R/W
R/W
1
0
Powers down LVDS output buffer for channel A, lane 0.
0: DA0 LVDS output buffer enabled
1: DA0 LVDS output buffer powered down
Powers down LVDS output buffer for channel B, lane 1.
Powered down automatically in 1-wire and 1/2-wire mode.
Default is powered down.
0: DB1 LVDS output buffer enabled
1: DB1 LVDS output buffer powered down
0
PDN DB0
R/W
0
Powers down LVDS output buffer for channel B, lane 0.
Powered down automatically in 1/2-wire mode. Default is
powered down.
0: DB0 LVDS output buffer enabled
1: DB0 LVDS output buffer powered down
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图8-48. Register 0x0D (PDN GLOBAL MASK)
7
0
6
0
5
4
3
2
1
0
0
0
MASK CLKBUF MASK REFAMP MASK BG DIS
R/W-0 R/W-0 R/W-0
0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
表8-17. Register 0x0D Field Descriptions
Bit
7-4
3
Field
Type
R/W
R/W
Reset
Description
0
0
0
Must write 0
MASK CLKBUF
MASK REFAMP
MASK BG DIS
Global power down mask control for sampling clock input buffer.
0: Clock buffer will get powered down when global power down
is exercised.
1: Clock buffer will NOT get powered down when global power
down is exercised.
2
1
R/W
R/W
0
0
Global power down mask control for reference amplifier.
0: Reference amplifier will get powered down when global power
down is exercised.
1: Reference amplifier will NOT get powered down when global
power down is exercised.
Global power down mask control for internal 1.2V bandgap
voltage reference. Setting this bit reduces power consumption in
global power down mode but increases the wake up time. See
the power down option overview.
0: Internal 1.2V bandgap voltage reference will NOT get
powered down when global power down is exercised.
1: Internal 1.2V bandgap voltage reference will get powered
down when global power down is exercised.
0
0
R/W
0
Must write 0
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图8-49. Register 0x0E
7
6
5
4
3
2
1
0
SYNC PIN EN
R/W-0
SPI SYNC
R/W-0
SPI SYNC EN
R/W-0
0
REF CTL
R/W-0
REF SEL
SE CLK EN
R/W-0
R/W-0
R/W-0
R/W-0
表8-18. Register 0x0E Field Descriptions
Bit
Field
SYNC PIN EN
Type
Reset
Description
7
R/W
0
This bit controls the functionality of the SYNC/PDN pin.
0: SYNC/PDN pin exercises global power down mode when pin
is pulled high.
1: SYNC/PDN pin issues the SYNC command when pin is
pulled high.
6
5
SPI SYNC
R/W
R/W
0
0
Toggling this bit issues the SYNC command using the SPI
register write. SYNC using SPI must be enabled as well (D5).
This bit doesn't self reset to 0.
0: Normal operation
1: SYNC command issued.
SPI SYNC EN
This bit enables synchronization using SPI instead of the
SYNC/PDN pin.
0: Synchronization using SPI register bit disabled.
1: Synchronization using SPI register bit enabled.
4
3
0
R/W
R/W
0
0
Must write 0
REF CTL
This bit determines if the REFBUF pin controls the voltage
reference selection or the SPI register (D2-D1).
0: The REFBUF pin selects the voltage reference option.
1: Voltage reference is selected using SPI (D2-D1) and single
ended clock using D0.
2-1
REF SEL
R/W
R/W
00
Selects of the voltage reference option. REF CTRL (D3) must be
set to 1.
00: Internal reference
01: External voltage reference (1.2V) using internal reference
buffer (REFBUF)
10: External voltage reference
11: not used
0
SE CLK EN
0
Selects single ended clock input and powers down the
differential sampling clock input buffer. REF CRTL (D3) must be
set to 1.
0: Differential clock input
1: Single ended clock input
图8-50. Register 0x11
7
0
6
0
5
4
3
2
0
1
0
0
0
SE A
R/W-0
0
0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
表8-19. Register 0x11 Field Descriptions
Bit
Field
0
Type
R/W
R/W
Reset
Description
7-6
5
0
0
Must write 0
SE A
This bit enables single ended analog input, channel A. This
mode reduces the SNR by 3-dB.
0: Differential input
1: Single ended input
4-0
0
R/W
0
Must write 0
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图8-51. Register 0x13
7
0
6
0
5
0
4
3
2
0
1
0
0
0
E-FUSE LD
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
表8-20. Register 0x13 Field Descriptions
Bit
7-1
0
Field
Type
R/W
R/W
Reset
Description
0
0
0
Must write 0
E-FUSE LD
This register bit loads the internal bit mapping for different
interfaces. After setting the interface in register 0x07, this E-
FUSE LD bit needs to be set to 1 and reset to 0 for loading to go
into effect. Register 0x07 along with the E-Fuse Load (0x13, D0)
needs to be loaded first in the programming sequence since the
E-Fuse load resets the SPI writes.
0: E-FUSE LOAD set
1: E-FUSE LOAD reset
图8-52. Register 0x14/15/16
7
6
5
4
3
2
1
0
CUSTOM PAT [7:0]
CUSTOM PAT [15:8]
TEST PAT B
R/W-0
TEST PAT A
R/W-0
CUSTOM PAT [17:16]
R/W-0 R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
表8-21. Register 0x14/15/16 Field Descriptions
Bit
Field
CUSTOM PAT [17:0]
Type
Reset
Description
7-0
R/W
00000000 This register is used for two purposes:
•
•
It sets the constant custom pattern starting from MSB
It sets the RAMP pattern increment step size.
00001: Ramp pattern for 18-bit ADC
00100: Ramp pattern for 16-bit ADC
10000: Ramp pattern for 14-bit ADC
7-5
TEST PAT B
R/W
000
Enables test pattern output mode for channel B (NOTE: The test
pattern is set prior to the bit mapper and is based on native
resolution of the ADC starting from the MSB). These work in
either output format.
000: Normal output mode (test pattern output disabled)
010: Ramp pattern: need to set proper increment using
CUSTOM PAT register
011: Constant Pattern using CUSTOM PAT [17:0] in register
0x14/15/16.
others: not used
4-2
TEST PAT A
R/W
000
Enables test pattern output mode for channel A (NOTE: The test
pattern is set prior to the bit mapper and is based on native
resolution of the ADC starting from the MSB). These work in
either output format.
000: Normal output mode (test pattern output disabled)
010: Ramp pattern: need to set proper increment using
CUSTOM PAT register
011: Constant Pattern using CUSTOM PAT [17:0] in register
0x14/15/16.
others: not used
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图8-53. Register 0x19
7
6
0
5
0
4
3
2
0
1
0
0
FCLK SRC
FCLK DIV
R/W-0
0
TOG FCLK
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
表8-22. Register 0x19 Field Descriptions
Bit
Field
Type
Reset
Description
7
FCLK SRC
R/W
0
User has to select if FCLK signal comes from ADC or from DDC
block. Here real decimation is treated same as bypass mode
0: FCLK generated from ADC. FCLK SRC set to 0 for DDC
bypass, real decimation mode and 1/2-w complex decimation
mode.
1: FCLK generated from DDC block. In complex decimation
mode only this bit needs to be set for 2-w and 1-w output
interface mode but NOT for 1/2-w mode.
6-5
4
0
R/W
R/W
0
0
Must write 0
FCLK DIV
This bit needs to be set to 1 for 2-w output mode in bypass/real
decimation mode only .
0: All output interface modes except 2-w decimation bypass and
real decimation mode.
1: 2-w output interface mode for decimation bypass and real
decimation.
3-1
0
0
R/W
R/W
0
0
Must write 0
TOG FCLK
This bit adjusts the FCLK signal appropriately for 1/2-wire mode
where FCLK is stretched to cover channel A and channel B.
This bit ONLY needs to be set in 1/2-wire mode with complex
decimation mode.
0: all other modes.
1: FCLK for 1/2-wire complex decimation mode.
表8-23. Configuration of FCLK SRC and FCLK DIV Register Bits vs Serial Interface
BYPASS/DECIMATION
SERIAL INTERFACE
FCLK SRC
FCLK DIV
TOG FCLK
2-wire
0
0
0
1
1
0
1
0
0
0
0
0
0
0
0
0
0
1
Decimation Bypass/ Real Decimation
Complex Decimation
1-wire
1/2-wire
2-wire
1-wire
1/2-wire
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图8-54. Register 0x1A
7
0
6
0
5
4
3
2
1
0
LVDS SWING HIGH
R/W-0
LVDS SWING LOW
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
表8-24. Register 0x1A Field Descriptions
Bit
7-6
5-3
Field
Type
R/W
R/W
Reset
Description
0
0
Must write 0
LVDS SWING HIGH
000
These bits adjust the SLVDS interface output high side
amplitude in 25mV steps. By using SLVDS SWING HIGH/LOW
the differential amplitude and common mode can be adjusted.
000: 1250 mV
001: 1275 mV
010: 1300 mV
011: 1325 mV
100: 1350 mV
101: 1325 mV
110: 1350 mV
111: 1375 mV
2-0
LVDS SWING LOW
R/W
000
These bits adjust the SLVDS interface output low side amplitude
in 25mV steps. By using SLVDS SWING HIGH/LOW the
differential amplitude and common mode can be adjusted.
000: 575 mV
001: 600 mV
010: 625 mV
011: 650 mV
100: 675 mV
101: 700 mV
110: 725 mV
111: 750 mV
图8-55. Register 0x1B
7
6
5
4
3
2
0
1
0
0
0
MAPPER EN
R/W-0
20B EN
R/W-0
BIT MAPPER RES
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
表8-25. Register 0x1B Field Descriptions
Bit
Field
MAPPER EN
Type
Reset
Description
7
R/W
0
This bit enables changing the resolution of the output (including
output serialization factor) in bypass mode only. This bit is not
needed for 20-bit resolution output.
0: Output bit mapper disabled.
1: Output bit mapper enabled.
6
20B EN
R/W
R/W
0
This bit enables 20-bit output resolution which can be useful for
very high decimation settings so that quantization noise doesn't
impact the ADC performance.
0: 20-bit output resolution disabled.
1: 20-bit output resolution enabled.
5-3
BIT MAPPER RES
000
Sets the output resolution using the bit mapper. MAPPER EN bit
(D6) needs to be enabled when operating in bypass mode..
000: 18 bit
001: 16 bit
010: 14 bit
all others, n/a
2-0
0
R/W
0
Must write 0
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表8-26. Register Settings for Output Bit Mapper vs Operating Mode
BYPASS/
DECIMATION
OUTPUT RESOLUTION
MAPPER EN (D7)
BIT MAPPER RES (D5-D3)
Decimation Bypass
Real Decimation
Resolution Change
1
0
0
000: 18-bit
001: 16-bit
010: 14-bit
Resolution Change (default 18-bit)
Complex Decimation
图8-56. Register 0x1E
7
0
6
0
5
0
4
3
2
1
0
0
LVDS DATA DEL
LVDS DCLK DEL
R/W-0 R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
表8-27. Register 0x1E Field Descriptions
Bit
Field
Type
R/W
R/W
Reset
Description
7-4
3-2
0
0
Must write 0
LVDS DATA DEL
00
These bits adjust the output timing of the SLVDS output data.
00: no delay
01: Data advanced by 50 ps
10: Data delayed by 50 ps
11: Data delayed by 100 ps
1-0
LVDS DCLK DEL
R/W
00
These bits adjust the output timing of the SLVDS DCLK output.
00: no delay
01: DCLK advanced by 50 ps
10: DCLK delayed by 50 ps
11: DCLK delayed by 100 ps
图8-57. Register 0x20/21/22
7
0
6
5
4
3
2
1
0
FCLK PAT [7:0]
FCLK PAT [15:8]
0
0
0
FCLK PAT [19:16]
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
表8-28. Register 0x20/21/22 Field Descriptions
Bit
Field
Type
Reset
Description
7-0
FCLK PAT [19:0]
R/W
0xFFC00
These bits can adjust the duty cycle of the FCLK. In decimation
bypass mode the FCLK pattern gets adjusted automatically for
the different output resolutions. 表8-29 shows the proper FCLK
pattern values for 1-wire and 1/2-wire in real/complex
decimation.
表8-29. FCLK Pattern for different resolution based on interface
DECIMATION
OUTPUT RESOLUTION
2-WIRE
1-WIRE
0xFE000
0xFF000
0xFF800
0xFFC00
1/2-WIRE
14-bit
16-bit
18-bit
20-bit
14-bit
16-bit
18-bit
20-bit
REAL DECIMATION
Use Default
Use Default
COMPLEX
DECIMATION
0xFFFFF
0xFFFFF
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图8-58. Register 0x24
7
0
6
0
5
0
4
3
2
1
0
DDC MUX
DIG BYP
R/W-0
DDC EN
R/W-0
0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
表8-30. Register 0x24 Field Descriptions
Bit
7-5
4-3
Field
Type
R/W
R/W
Reset
Description
0
0
0
Must write 0
DDC MUX
Configures DDC MUX in front of the decimation filter.
00: ADC channel A connected to DDC A;
01: ADC channel A connected to DDC A and DDC B.
others: not used
2
DIG BYP
R/W
0
This bit needs to be set to enable digital features block which
includes decimation and scrambling.
0: Digital feature block bypassed - lowest latency
1: Data path includes digital features
1
0
DDC EN
0
R/W
R/W
0
0
Enables internal decimation filter for both channels
0: DDC disabled.
1: DDC enabled.
Must write 0
To output
interface
DDC
N
N
DECIMATION
DIG BYP
DDC
DDC MUX
To output
interface
图8-59. Register control for digital features
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图8-60. Register 0x25
7
6
5
4
3
2
0
1
0
0
DDC MUX EN
DECIMATION
R/W-0
REAL OUT
R/W-0
MIX PHASE
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
表8-31. Register 0x25 Field Descriptions
Bit
Field
Type
Reset
Description
7
DDC MUX EN
DECIMATION
R/W
0
Enables the digital mux between ADCs and decimation filters.
This bit is required for DDC mux settings in register 0x024 (D4,
D3) to go into effect.
0: DDC mux disabled
1: DDC mux enabled
6-4
R/W
000
Complex decimation setting. This applies to both channels.
000: Bypass mode (no decimation)
001: Decimation by 2
010: Decimation by 4
011: Decimation by 8
100: Decimation by 16
101: Decimation by 32
others: not used
3
REAL OUT
R/W
0
This bit selects real output decimation. This mode applies to
both channels. In this mode, the decimation filter is a low pass
filter and no complex mixing is performed to reduce power
consumption. For maximum power savings the NCO in this case
should be set to 0.
0: Complex decimation
1: Real decimation
2-1
0
0
R/W
R/W
0
0
Must write 0
MIX PHASE
This bit used to invert the NCO phase
0: NCO phase as is.
1: NCO phase inverted.
图8-61. Register 0x26
7
6
5
4
3
2
1
0
MIX GAIN A
MIX RES A
R/W-0
FS/4 MIX A
R/W-0
MIX GAIN B
MIX RES B
R/W-0
FS/4 MIX B
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
表8-32. Register 0x26 Field Descriptions
Bit
Field
Type
Reset
Description
7-6
MIX GAIN A
R/W
00
This bit applies a 0, 3 or 6-dB digital gain to the output of digital
mixer to compensate for the mixing loss for channel A.
00: no digital gain added
01: 3-dB digital gain added
10: 6-dB digital gain added
11: not used
5
4
MIX RES A
FS/4 MIX A
R/W
R/W
0
0
Toggling this bit resets the NCO phase of channel A and loads
the new NCO frequency. This bit does not self reset.
Enables FS/4 mixing for DDC A (complex decimation only).
0: FS/4 mixing disabled.
1: FS/4 mixing enabled.
3-2
MIX GAIN B
R/W
00
This bit applies a 0, 3 or 6-dB digital gain to the output of digital
mixer to compensate for the mixing loss for channel B.
00: no digital gain added
01: 3-dB digital gain added
10: 6-dB digital gain added
11: not used
1
MIX RES B
R/W
0
Toggling this bit resets the NCO phase of channel B and loads
the new NCO frequency. This bit does not self reset.
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表8-32. Register 0x26 Field Descriptions (continued)
Bit
Field
FS/4 MIX B
Type
Reset
Description
0
R/W
0
Enables FS/4 mixing for DDC B (complex decimation only).
0: FS/4 mixing disabled.
1: FS/4 mixing enabled.
图8-62. Register 0x27
7
0
6
0
5
0
4
3
2
1
0
0
0
OP ORDER A
R/W-0
Q-DEL A
R/W-0
FS/4 MIX PH A
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
表8-33. Register 0x27 Field Descriptions
Bit
Field
Type
R/W
R/W
Reset
Description
7-5
4
0
0
0
Must write 0
OP ORDER A
Swaps the I and Q output order for channel A
0: Output order is I[n], Q[n]
1: Output order is swapped: Q[n], I[n]
3
2
Q-DEL A
R/W
R/W
R/W
0
0
0
This delays the Q-sample output of channel A by one.
0: Output order is I[n], Q[n]
1: Q-sample is delayed by 1 sample: I[n], Q[n+1], I[n+1], Q[n+2]
FS/4 MIX PH A
0
Inverts the mixer phase for channel A when using FS/4 mixer
0: Mixer phase is non-inverted
1: Mixer phase is inverted
1-0
Must write 0
图8-63. Register 0x2A/B/C/D
7
6
5
4
3
2
1
0
NCO A [7:0]
NCO A [15:8]
NCO A [23:16]
NCO A [31:24]
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
表8-34. Register 0x2A/2B/2C/2D Field Descriptions
Bit
7-0
Field
Type
Reset
Description
NCO A [31:0]
R/W
0
Sets the 32 bit NCO value for decimation filter channel A. The
NCO value is fNCO× 232/FS
In real decimation mode these registers are automatically set to
0.
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图8-64. Register 0x2E
7
0
6
0
5
0
4
3
2
1
0
0
0
OP ORDER B
R/W-0
Q-DEL B
R/W-0
FS/4 MIX PH B
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
表8-35. Register 0x2E/2F/30 Field Descriptions
Bit
Field
Type
R/W
R/W
Reset
Description
7-5
4
0
0
0
Must write 0
OP ORDER B
Swaps the I and Q output order for channel B
0: Output order is I[n], Q[n]
1: Output order is swapped: Q[n], I[n]
3
2
Q-DEL B
R/W
R/W
R/W
0
0
0
This delays the Q-sample output of channel B by one.
0: Output order is I[n], Q[n]
1: Q-sample is delayed by 1 sample: I[n], Q[n+1], I[n+1], Q[n+2]
FS/4 MIX PH B
0
Inverts the mixer phase for channel B when using FS/4 mixer
0: Mixer phase is non-inverted
1: Mixer phase is inverted
1-0
Must write 0
图8-65. Register 0x31/32/33/34
7
6
5
4
3
2
1
0
NCO B [7:0]
NCO B [15:8]
NCO B [23:16]
NCO B [31:24]
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
表8-36. Register 0x31/32/33/34 Field Descriptions
Bit
7-0
Field
Type
Reset
Description
NCO B [31:0]
R/W
0
Sets the 32 bit NCO value for decimation filter channel B. The
NCO value is fNCO× 232/FS
In real decimation mode these registers are automatically set to
0.
图8-66. Register 0x39..0x60
7
6
5
4
3
2
1
0
OUTPUT BIT MAPPER CHA
R/W-0 R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
表8-37. Register 0x39..0x60 Field Descriptions
Bit
7-0
Field
Type
Reset
Description
OUTPUT BIT MAPPER CHA
R/W
0
These registers are used to reorder the output data bus. See the
节8.3.5.2 on how to program it.
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图8-67. Register 0x61..0x88
7
6
5
4
3
2
1
0
OUTPUT BIT MAPPER CHB
R/W-0 R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
表8-38. Register 0x61..0x88 Field Descriptions
Bit
Field
Type
Reset
Description
7-0
OUTPUT BIT MAPPER CHB
R/W
0
These registers are used to reorder the output data bus. See the
节8.3.5.2 on how to program it.
图8-68. Register 0x8F
7
0
6
0
5
0
4
3
2
0
1
0
0
0
0
FORMAT A
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
表8-39. Register 0x8F Field Descriptions
Bit
Field
Type
R/W
R/W
Reset
Description
7-2
1
0
0
0
Must write 0
FORMAT A
This bit sets the output data format for channel A. Digital bypass
register bit (0x24, D2) needs to be enabled as well.
0: 2s complement
1: Offset binary
0
0
R/W
0
Must write 0
图8-69. Register 0x92
7
0
6
0
5
0
4
3
2
0
1
0
0
0
0
FORMAT B
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
表8-40. Register 0x92 Field Descriptions
Bit
Field
Type
R/W
R/W
Reset
Description
7-2
1
0
0
0
Must write 0
FORMAT B
This bit sets the output data format for channel B. Digital bypass
register bit (0x24, D2) needs to be enabled as well.
0: 2s complement
1: Offset binary
0
0
R/W
0
Must write 0
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9 Application Information Disclaimer
备注
以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
9.1 Typical Application
A spectrum analyzer is a typical frequency domain application for the ADC3564 and its front end circuitry is very
similar to several other systems such as software defined radio (SDR), radar or communications. Some
applications require frequency coverage including DC or near DC so it’s included in this example.
0.6V
10 uF
VREF
10 kꢀ
REFBUF
1.2V REF
NCO
NCO
Glitch Filter
100 pF
33 ꢀ
N
N
Low Pass Filter
10 ꢀ
10 ꢀ
180nH
DCLKIN
AMP
AIN
ADC
33 ꢀ
DCLK
FCLK
Dig I/F
FPGA
180nH
VCM
DA0/1
DB0/1
0.95V
CVCM
Device Clock
CLK
Control
图9-1. Typical configuration for a spectrum analyzer with DC support
9.1.1 Design Requirements
Frequency domain applications cover a wide range of frequencies from low input frequencies at or near DC in
the 1st Nyquist zone to undersampling in higher Nyquist zones. If very low input frequency is supported then the
input has to be DC coupled and the ADC driven by a fully differential amplifier (FDA). If low frequency support is
not needed then AC coupling and use of a balun may be more suitable.
The internal reference is used since DC precision is not needed. However the ADC AC performance is highly
dependent on the quality of the external clock source. If in-band interferers can be present then the ADC SFDR
performance will be a key care about as well. A higher ADC sampling rate is desirable in order to relax the
external anti-aliasing filter –an internal decimation filter can be used to reduce the digital output rate afterwards.
表9-1. Design key care-abouts
FEATURE
DESCRIPTION
Signal Bandwidth
Input Driver
DC to 30 MHz
Single ended to differential signal conversion and DC coupling
External clock with low jitter
Clock Source
When designing the amplifier/filter driving circuit, the ADC input full-scale voltage needs to be taken into
consideration. For example, the ADC3564 input full-scale is 3.2Vpp. When factoring in ~ 1 dB for insertion loss
of the filter, then the amplifier needs to deliver close to 3.6Vpp. The amplifier distortion performance will degrade
with a larger output swing and considering the ADC common mode input voltage the amplifier may not be able to
deliver the full swing. The ADC3564 provides an output common mode voltage of 0.95V and the THS4541 for
example can only swing within 250 mV of its negative supply. A unipolar 3.3 V amplifier power supply will thus
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limit the maximum voltage swing to ~ 2.8Vpp. Hence if a larger output swing is required (factoring in filter
insertion loss) then a negative supply for the amplifier is needed in order to eliminate that limitation. Additionally
input voltage protection diodes may be needed to protect the ADC from over-voltage events.
表9-2. Output voltage swing of THS4541 vs power supply
DEVICE
MIN OUTPUT VOLTAGE
MAX SWING WITH 3.3 V/ 0 V SUPPLY
MAX SWING WITH 3.3 V/ -1.0 V SUPPLY
THS4541
VS- + 250 mV
2.8 Vpp
6.8 Vpp
9.1.2 Detailed Design Procedure
9.1.2.1 Input Signal Path
The THS4541 provides a very good low power option to drive the ADC inputs. 表9-3
provides an overview of the THS4541 with power consumption and usable frequency.
表9-3. Fully Differential Amplifier Options
DEVICE
CURRENT (IQ) PER CHANNEL
USABLE FREQUENCY RANGE
THS4541
10 mA
< 70 MHz
The low pass filter design (topology, filter order) is driven by the application itself. However, when designing the
low pass filter, the optimum load impedance for the amplifier should be taken into consideration as well. Between
the low pass filter and the ADC input the sampling glitch filter needs to added as well as shown in 节8.3.1.2.1. In
this example the DC - 30 MHz glitch filter is selected.
9.1.2.2 Sampling Clock
Applications operating with low input frequencies (such as DC to 30 MHz) typically are less sensitive to
performance degradation due to clock jitter. The internal ADC aperture jitter improves with faster rise and fall
times (i.e. square wave vs sine wave). 表 9-4 provides an overview of the estimated SNR performance of the
ADC3564 based on different amounts of jitter of the external clock source. The SNR is estimated based on
ADC3564 thermal noise of 77 dBFS and input signal at -1dBFS.
表9-4. ADC SNR performance across vs input frequency for different amounts of external clock jitter
INPUT FREQUENCY
TJ,EXT = 100 fs
TJ,EXT = 250 fs
TJ,EXT = 500 fs
TJ,EXT = 1 ps
10 MHz
76.5
76.3
76.2
76.4
76.2
75.9
76.3
75.8
75.1
75.9
20 MHz
74.5
30 MHz
72.8
Termination of the clock input should be considered for long clock traces.
9.1.2.3 Voltage Reference
The ADC3564 is configured to internal reference operation by applying 0.6 V to the REFBUF pin.
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9.1.3 Application Curves
The following FFT plots show the performance of THS4541 driving the ADC3564 operated at 125 MSPS with a
full-scale input at -1 dBFS with input frequencies at 5, 10 and 20 MHz.
SNR = 75.2 dBFS, HD23 = 80 dBc, Non HD23 = 88 dBFS
SNR = 75.2 dBFS, HD23 = 81 dBc, Non HD23 = 91 dBFS
图9-2. Single Tone FFT at FIN = 5 MHz
图9-3. Single Tone FFT at FIN = 10 MHz
SNR = 75.6 dBFS, HD23 = 74 dBc, Non HD23 = 94 dBFS
AIN = -10 dBFS, SNR = 76.9 dBFS, HD23 = 83 dBc, Non
HD23 = 93 dBFS
图9-4. Single Tone FFT at FIN = 20 MHz
图9-5. Single Tone FFT at FIN = 20 MHz
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9.2 Initialization Set Up
After power-up, the internal registers must be initialized to their default values through a hardware reset by
applying a high pulse on the RESET pin, as shown in 图9-6.
1. Apply AVDD and IOVDD (no specific sequence required). After AVDD is applied the internal bandgap
reference will power up and settle out in ~ 2ms.
2. Configure REFBUF pin (pull high or low even if configured via SPI later on) and apply the sampling clock.
3. Apply hardware reset. After hardware reset is released, the default registers are loaded from internal fuses
and the internal power up capacitor calibration is initiated. The calibration takes approximately 200000 clock
cycles.
4. Begin programming using SPI interface.
t2
AVDD
IOVDD
t1
REFBUF
Ext VREF
CLK
t4
t3
RESET
SEN
图9-6. Initialization of serial registers after power up
表9-5. Power-up timing
MIN
TYP
MAX
UNIT
t1
t2
t3
t4
Power-on delay: delay from power up to logic level of REFBUF pin
Delay from REFBUF pin logic level to RESET rising edge
RESET pulse width
2
100
ms
ns
us
1
Delay from RESET disable to SEN active
~ 200000
clock cycles
9.2.1 Register Initialization During Operation
If required, the serial interface registers can be cleared and reset to default settings during operation either:
• through a hardware reset or
• by applying a software reset. When using the serial interface, set the RESET bit (D0 in register address 0x00)
high. This setting initializes the internal registers to the default values and then self-resets the RESET bit low.
In this case, the RESET pin is kept low.
After hardware or software reset the wait time is also ~ 200000 clock cycles before the SPI registers can be
programmed.
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9.3 Power Supply Recommendations
The ADC3564 requires two different power-supplies. The AVDD rail provides power for the internal analog
circuits and the ADC itself while the IOVDD rail powers the digital interface and the internal digital circuits like
decimation filter or output interface mapper. Power sequencing is not required.
The AVDD power supply must be low noise to achieve data sheet performance. In applications operating near
DC, the 1/f noise contribution of the power supply must also be considered. The ADC is designed for good
PSRR which aides with the power supply filter design.
图9-7. Power Supply Rejection Ratio (PSRR) vs Frequency
There are two recommended power-supply architectures:
1. Step down using high-efficiency switching converters, followed by a second stage of regulation using a low
noise LDO to provide switching noise reduction and improved voltage accuracy.
2. Directly step down the final ADC supply voltage using high-efficiency switching converters. This approach
provides the best efficiency, but care must be taken to make sure the switching noise is minimized to prevent
degraded ADC performance.
TI WEBENCH® Power Designer can be used to select and design the individual power-supply elements
needed: see the WEBENCH® Power Designer
Recommended switching regulators for the first stage include the TPS62821, and similar devices.
Recommended low dropout (LDO) linear regulators include the TPS7A4701, TPS7A90, LP5901, and similar
devices.
For the switch regulator only approach, the ripple filter must be designed with a notch frequency that aligns with
the switching ripple frequency of the DC/DC converter. Note the switching frequency reported from WEBENCH®
and design the EMI filter and capacitor combination to have the notch frequency centered as needed. 图9-8 and
图9-9 illustrate the two approaches.
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AVDD and IOVDD supply voltages should not be shared in order to prevent digital switching noise from coupling
into the analog signal chain.
FB
FB
2.1V
1.8V
DC/DC
Regulator
5V-12V
LDO
AVDD
10uF 10uF 0.1uF
47uF
47uF
GND
GND
GND
FB
IOVDD
10uF 10uF 0.1uF
FB = Ferrite bead filter
GND
图9-8. Example: LDO Linear Regulator Approach
EMI FILTER
FB
1.8V
DC/DC
Regulator
5V-12V
AVDD
10uF 10uF 10uF
10uF 10uF 0.1uF
GND
GND
FB
IOVDD
10uF 10uF 0.1uF
GND
Ripple filter notch frequency to match switching frequency of the DC/DC regulator
FB = Ferrite bead filter
图9-9. Example Switcher-Only Approach
9.4 Layout
9.4.1 Layout Guidelines
There are several critical signals which require specific care during board design:
1. Analog input and clock signals
• Traces should be as short as possible and vias should be avoided where possible to minimize impedance
discontinuities.
• Traces should be routed using loosely coupled 100-Ωdifferential traces.
• Differential trace lengths should be matched as close as possible to minimize phase imbalance and HD2
degradation.
2. Digital output interface
• Traces should be routed using tightly coupled 100-Ωdifferential traces.
3. Voltage reference
• The bypass capacitor should be placed as close to the device pins as possible and connected between
VREF and REFGND –on top layer avoiding vias.
• Depending on configuration an additional bypass capacitor between REFBUF and REFGND may be
recommended and should also be placed as close to pins as possible on top layer.
4. Power and ground connections
• Provide low resistance connection paths to all power and ground pins.
• Use power and ground planes instead of traces.
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• Avoid narrow, isolated paths which increase the connection resistance.
• Use a signal/ground/power circuit board stackup to maximize coupling between the ground and power
plane.
9.4.2 Layout Example
The following screen shot shows the top layer of the ADC3564/3664 EVM.
• Signal and clock inputs are routed as differential signals on the top layer avoiding vias.
• SLVDS output interface lanes are routed differential and length matched
• Bypass caps are close to the VREF pin on the top layer avoiding vias.
SLVDS routed tightly
coupled and length matched
Bypass caps on VREF close
to the pins and no vias
Clock routing
without vias
Analog inputs on
top layer (no vias)
图9-10. Layout example: top layer of ADC3564 EVM
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10 Device and Documentation Support
TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device,
generate code, and develop solutions are listed below.
10.1 Device Support
10.2 Documentation Support
10.2.1 Related Documentation
10.3 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
10.4 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
10.5 商标
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
10.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
10.7 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
11 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
ADC3564IRSBR
ADC3564IRSBT
ACTIVE
ACTIVE
WQFN
WQFN
RSB
RSB
40
40
3000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 105
-40 to 105
AZ3564
AZ3564
Samples
Samples
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
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Addendum-Page 2
PACKAGE OUTLINE
RSB0040E
WQFN - 0.8 mm max height
S
C
A
L
E
2
.
7
0
0
PLASTIC QUAD FLATPACK - NO LEAD
5.1
4.9
B
A
PIN 1 INDEX AREA
5.1
4.9
C
0.8 MAX
SEATING PLANE
0.08 C
0.05
0.00
2X 3.6
(0.2) TYP
EXPOSED
11
20
THERMAL PAD
36X 0.4
10
21
2X
41
SYMM
3.6
3.15 0.1
1
30
0.25
0.15
40X
40
31
PIN 1 ID
(OPTIONAL)
0.1
C A B
SYMM
0.5
0.3
0.05
40X
4219096/A 11/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
RSB0040E
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
3.15)
SYMM
40
31
40X (0.6)
40X (0.2)
1
30
36X (0.4)
41
SYMM
(4.8)
(1.325)
(
0.2) TYP
VIA
10
21
(R0.05)
TYP
11
20
(1.325)
(4.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
0.05 MIN
ALL AROUND
0.05 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
EXPOSED
METAL
EXPOSED
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4219096/A 11/2017
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
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EXAMPLE STENCIL DESIGN
RSB0040E
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(0.785)
4X ( 1.37)
40
31
40X (0.6)
1
30
40X (0.2)
36X (0.4)
SYMM
(0.785)
(4.8)
41
(R0.05) TYP
10
21
METAL
TYP
20
11
SYMM
(4.8)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
EXPOSED PAD 41
75% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:20X
4219096/A 11/2017
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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