ADC3683_V01 [TI]
ADC368x 18-bit 0.5 to 65-MSPS Low Noise Ultra-low Power Dual Channel ADC;型号: | ADC3683_V01 |
厂家: | TEXAS INSTRUMENTS |
描述: | ADC368x 18-bit 0.5 to 65-MSPS Low Noise Ultra-low Power Dual Channel ADC |
文件: | 总75页 (文件大小:5011K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
ADC3683
SBAS872 – DECEMBER 2020
ADC368x 18-bit 0.5 to 65-MSPS Low Noise Ultra-low Power Dual Channel ADC
1 Features
3 Description
•
•
•
•
Dual Channel ADC
18-bit 10/25/65 MSPS ADC
Noise Floor: -160 dBFS/Hz
Low Power and Optimized Power Scaling:
50 mW/ch (10 MSPS) to 94 mW/ch (65 MSPS)
Latency: 1-2 clock cycles
18-bit, no missing codes
INL/DNL: ±7/ ±0.7 LSB (typ)
Reference: External or Internal
Input Bandwidth: 900MHz (3-dB)
Industrial Temperature Range: -40 to +105°C
On-chip digital filter (Optional)
– Decimation by 2, 4, 8, 16, 32
– 32-bit NCO
Serial LVDS digital interface (2-, 1- and 1/2-wire)
Small Footprint: 40-QFN (5x5 mm) Package
Spectral Performance (fIN = 5 MHz):
– SNR: 83.8 dBFS
– SFDR: 89 dBc HD2, HD3
– SFDR: 101 dBFS Worst Spur
Spectral Performance (fIN = 20MHz):
– SNR: 82.6 dBFS
– SFDR: 85 dBc HD2, HD3
– SFDR: 97 dBFS Worst Spur
The ADC3681, 82, 83 (ADC368x) is a low noise, ultra-
low power 18-bit 65 MSPS high-speed dual channel
ADC family. Designed for lowest noise performance, it
delivers a noise spectral density of -160 dBFS/Hz
combined with excellent linearity and dynamic range.
The ADC368x offers excellent DC precision together
with IF sampling support which makes it ideally suited
for a wide range of applications. High-speed control
loops benefit from the short latency as low as only 1
clock cycle. The ADC consumes only 94 mW/ch at 65
Msps and its power consumption scales very well with
lower sampling rates.
•
•
•
•
•
•
•
The ADC368x uses a serial LVDS (SLVDS) interface
to output the data which minimizes the number of
digital interconnects. The device supports two-lane,
one-lane and half-lane options. The ADC36xx is a pin
to pin compatible family of ADCs with 16 and 18-bit
resolution and different speed grades. It comes in a
40-pin QFN package (5 x 5mm) and supports the
extended industrial temperature range from -40 to
+105⁰C.
•
•
•
Device Information
•
PART NUMBER
ADC368x
PACKAGE(1)
BODY SIZE (NOM)
VQFN (40)
5.00 x 5.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
2 Applications
Device Comparison
•
•
•
•
•
•
•
•
•
•
•
•
High-Speed Data Acquisition
Industrial Monitoring
Software Defined Radio
Power Quality Analyzer
Source Measurement Unit (SMU)
Communications Infrastructure
Spectrum Analyzer
Control Loops
Instrumentation
Imaging
Spectroscopy
Radar
PART NUMBER
ADC3683
RESOLUTION
SAMPLING RATE
18 BIT
65 MSPS
ADC3682(1)
18 BIT
18 BIT
25 MSPS
ADC3681(1)
10 MSPS
(1) Product Preview.
FFT: Fs = 65 MSPS, Fin = 5 MHz
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION
DATA.
ADC3683
SBAS872 – DECEMBER 2020
www.ti.com
Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 5
6.1 Absolute Maximum Ratings ....................................... 5
6.2 ESD Ratings .............................................................. 5
6.3 Recommended Operating Conditions ........................5
6.4 Thermal Information ...................................................5
6.5 Electrical Characteristics - Power Consumption ........6
6.6 Electrical Characteristics - DC Specifications ............7
6.7 Electrical Characteristics - AC Specifications ............ 9
6.8 Timing Requirements ...............................................12
6.9 Typical Characteristics - ADC3683........................... 14
7 Parameter Measurement Information..........................19
8 Detailed Description......................................................21
8.1 Overview...................................................................21
8.2 Functional Block Diagram.........................................21
8.3 Feature Description...................................................22
8.4 Device Functional Modes..........................................40
8.5 Programming............................................................ 42
8.6 Register Map.............................................................44
9 Application Information Disclaimer.............................59
9.1 Typical Application.................................................... 59
9.2 Initialization Set Up................................................... 62
10 Power Supply Recommendations..............................63
11 Layout...........................................................................65
11.1 Layout Guidelines................................................... 65
11.2 Layout Example...................................................... 65
12 Device and Documentation Support..........................66
12.1 Receiving Notification of Documentation Updates..66
12.2 Support Resources................................................. 66
12.3 Trademarks.............................................................66
12.4 Electrostatic Discharge Caution..............................66
12.5 Glossary..................................................................66
13 Mechanical, Packaging, and Orderable
Information.................................................................... 66
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
DATE
REVISION
NOTES
December 2020
*
Initial release.
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5 Pin Configuration and Functions
40
39
38
37
36
35
34
33
32
31
1
2
30
29
28
27
26
25
24
23
22
21
PDN/SYNC
VREF
IOVDD
FCLKM
FCLKP
3
REFGND
REFBUF
AVDD
CLKP
4
NC
5
IOGND
DCLKINP
DCLKINM
DCLKP
DCLKM
IOVDD
6
7
CLKM
8
VCM
9
RESET
SDIO
GND PAD (backside)
10
11
12
13
14
15
16
17
18
19
20
Figure 5-1. RSB Package, 40-Pin WQFN, Top View
Table 5-1. Pin Descriptions
PIN
I/O
Description
Name
No.
INPUT/REFERENCE
AINP
AINM
BINP
BINM
VCM
VREF
12
13
39
38
8
I
I
Positive analog input, channel A
Negative analog input, channel A
I
Positive analog input, channel B
I
Negative analog input, channel B
O
I
Common-mode voltage output for the analog inputs, 0.95V
External voltage reference input, 1.6V
2
1.2V external voltage reference input for use with internal reference buffer. Internal 100 kΩ
pull-up resistor to AVDD. This pin is also used to configure default operating conditions.
REFBUF
4
3
I
I
REFGND
CLOCK
Reference ground input
CLKP
6
7
I
I
Positive differential sampling clock input for the ADC
Negative differential sampling clock input for the ADC
CLKM
CONFIGURATION
Power down/Synchronization input. This pin can be configured via the SPI interface. Active
high. This pin has an internal 21 kΩ pull-down resistor.
PDN/SYNC
1
I
RESET
SEN
9
I
Hardware reset. Active high. This pin has an internal 21 kΩ pull-down resistor.
Serial interface enable. Active low. This pin has an internal 21 kΩ pull-up resistor to AVDD.
Serial interface clock input. This pin has an internal 21 kΩ pull-down resistor.
Serial interface data input and output. This pin has an internal 21 kΩ pull-down resistor.
Do not connect
16
35
10
27
I
I
SCLK
SDIO
NC
I/O
-
DIGITAL INTERFACE
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Table 5-1. Pin Descriptions (continued)
PIN
I/O
Description
Name
No.
20
19
18
17
31
32
33
34
23
22
28
29
25
24
DA0P
O
O
O
O
O
O
O
O
O
O
O
O
I
Positive differential serial LVDS output for lane 0, channel A
Negative differential serial LVDS output for lane 0, channel A
Positive differential serial LVDS output for lane 1, channel A
Negative differential serial LVDS output for lane 1, channel A
Positive differential serial LVDS output for lane 0, channel B
Negative differential serial LVDS output for lane 0, channel B
Positive differential serial LVDS output for lane 1, channel B
Negative differential serial LVDS output for lane 1, channel B
Positive differential serial LVDS bit clock output.
DA0M
DA1P
DA1M
DB0P
DB0M
DB1P
DB1M
DCLKP
DCLKM
FCLKP
FCLKM
DCLKINP
DCLKINM
POWER SUPPLY
AVDD
Negative differential serial LVDS bit clock output.
Positive differential serial LVDS frame clock output.
Negative differential serial LVDS frame clock output.
Positive differential serial LVDS bit clock input. Internal 100 Ω differential termination.
Negative differential serial LVDS bit clock input. Internal 100 Ω differential termination.
I
5,15,36
I
I
Analog 1.8V power supply
Ground, 0V
11,14,37,40,
PowerPad
GND
IOVDD
IOGND
21,30
26
I
I
1.8V power supply for digital interface
Ground, 0V for digital interface
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
PARAMETER
TEST CONDITIONS
MIN
MAX UNIT
Supply voltage range, AVDD, IOVDD
Supply voltage range, GND, IOGND, REFGND
–0.3
–0.3
–0.3
–0.3
2.1
0.3
V
V
AINP/M, BINP/M,CLKP/M, DCLKINP/M, VREF, REFBUF
PDN/SYNC, RESET, SCLK, SEN, SDIO
2.1
Voltage applied to
input pins
V
2.1
Junction temperature, TJ
Storage temperature, Tstg
105
150
°C
°C
–65
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
6.2 ESD Ratings
VALUE
2500
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1)
Electrostatic
discharge
V(ESD)
V
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2)
1000
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
1.75
1.75
–40
NOM
1.8
MAX UNIT
AVDD(1)
1.85
1.85
V
V
Supply
voltage range
IOVDD(1)
1.8
TA
TJ
Operating free-air temperature
Operating junction temperature
105
°C
°C
105(2)
(1) Measured to GND.
(2) Prolonged use above this junction temperature may increase the device failure-in-time (FIT) rate.
6.4 Thermal Information
ADC368x
RSB (QFN)
40 Pins
30.7
THERMAL METRIC(1)
UNIT
RΘJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RΘJC(top)
RΘJB
16.4
10.5
ΨJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.2
ΨJB
10.5
RΘJC(bot)
2.0
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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6.5 Electrical Characteristics - Power Consumption
Typical values are over the operating free-air temperature range, at TA = 25°C, full temperature range is TMIN = –40°C to
TMAX = 105°C, ADC sampling rate = 65 MSPS, 50% clock duty cycle, AVDD = IOVDD = 1.8 V, external 1.6 V reference, and
–1-dBFS differential input, unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ADC3681: 10 MSPS
IAVDD
IIOVDD
PDIS
Analog supply current
I/O supply current
Power dissipation
External reference
27
28
99
21
35
25
30
27
mA
SLVDS 1-wire
External reference, 1-wire
1-wire, 1/2-swing
2-wire
mW
IIOVDD
I/O supply current
1/2-wire
mA
4x real decimation, 1-wire
4x real decimation, 1/2-wire
ADC3682: 25 MSPS
IAVDD
IIOVDD
PDIS
Analog supply current
External reference
1-wire
31
30
mA
I/O supply current
Power dissipation
External reference, 1-wire
1-wire, 1/2-swing
2-wire
110
23
mW
37
IIOVDD
I/O supply current
1/2-wire
27
mA
4x real decimation, 1-wire
4x real decimation, 1/2-wire
33
29
ADC3683: 65 MSPS
IAVDD
IIOVDD
PDIS
Analog supply current
External reference
63
41
187
30
39
36
37
33
44
40
36
82
47
mA
I/O supply current
Power dissipation
2-wire
External reference, 2-wire
2-wire, 1/2-swing
232
mW
4x real decimation, 1-wire
4x real decimation, 1/2-wire
16x real decimation, 1-wire
16x real decimation, 1/2-wire
4x complex decimation, 1-wire
16x complex decimation, 1-wire
16x complex decimation, 1/2-wire
IIOVDD
I/O supply current
mA
MISCELLANEOUS
Internal reference, additional analog
3
0.3
0.7
5
supply current
External 1.2V reference (REFBUF),
additional analog supply current
IAVDD
mA
Single ended clock input, reduces
analog supply current by
Enabled via SPI
Default mask settings, internal
reference
Power consumption in global power
down mode
PDIS
mW
Default mask settings, external
reference
9
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6.6 Electrical Characteristics - DC Specifications
Typical values are over the operating free-air temperature range, at TA = 25°C, full temperature range is TMIN = –40°C to
TMAX = 105°C, ADC sampling rate = 65 MSPS, 50% clock duty cycle, AVDD = IOVDD = 1.8 V, 1.6 V external reference, and
–1-dBFS differential input, unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DC ACCURACY
No missing codes
PSRR
18
bits
dB
FIN = 1 MHz
50
ADC3681: 10 MSPS
DNL
Differential nonlinearity
FIN = 1 MHz
FIN = 1 MHz
± 0.7
± 7
LSB
LSB
INL
Integral nonlinearity
Offset error
VOS_ERR
VOS_DRIFT
GAINERR
GAINDRIFT
GAINERR
GAINDRIFT
130
TBD
0.83
TBD
TBD
TBD
5
LSB
Offset drift over temperature
Gain error
LSB/ºC
%FSR
ppm/ºC
%FSR
dB
External 1.6V Reference
External 1.6V Reference
Internal Reference
Gain drift over temperature
Gain error
Gain drift over temperature
Internal Reference
Transition Noise
LSB
ADC3682: 25 MSPS
DNL
Differential nonlinearity
FIN = 1 MHz
FIN = 1 MHz
± 0.7
± 7
LSB
LSB
INL
Integral nonlinearity
Offset error
VOS_ERR
VOS_DRIFT
GAINERR
GAINDRIFT
GAINERR
GAINDRIFT
130
TBD
0.83
TBD
TBD
TBD
5
LSB
Offset drift over temperature
Gain error
LSB/ºC
%FSR
ppm/ºC
%FSR
dB
External 1.6V Reference
External 1.6V Reference
Internal Reference
Gain drift over temperature
Gain error
Gain drift over temperature
Internal Reference
Transition Noise
LSB
ADC3683: 65 MSPS
DNL
Differential nonlinearity
FIN = 1 MHz
FIN = 1 MHz
± 0.7
± 7
100
-3.5
0.35
10
± 0.9
± 19
510
LSB
LSB
INL
Integral nonlinearity
Offset error
VOS_ERR
VOS_DRIFT
GAINERR
GAINDRIFT
GAINERR
GAINDRIFT
LSB
Offset drift over temperature
Gain error
LSB/ºC
%FSR
ppm/ºC
%FSR
ppm/ºC
LSB
External 1.6V Reference
External 1.6V Reference
Internal Reference
Gain drift over temperature
Gain error
2.4
108
5
Gain drift over temperature
Internal Reference
Transition Noise
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6.6 Electrical Characteristics - DC Specifications (continued)
Typical values are over the operating free-air temperature range, at TA = 25°C, full temperature range is TMIN = –40°C to
TMAX = 105°C, ADC sampling rate = 65 MSPS, 50% clock duty cycle, AVDD = IOVDD = 1.8 V, 1.6 V external reference, and
–1-dBFS differential input, unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ADC ANALOG INPUT (AINP/M, BINP/M)
FS
Input full scale
Differential
3.2
0.95
8
Vpp
V
VCM
RIN
Input common model voltage
Differential input resistance
Differential input Capacitance
Output common mode voltage
Analog Input Bandwidth (-3dB)
0.9
1.0
FIN = 100 kHz
FIN = 100 kHz
kΩ
pF
CIN
7
VOCM
BW
0.95
900
V
MHz
Internal Voltage Reference
VREF
Internal reference voltage
1.6
8
V
VREF Output Impedance
Reference Input Buffer (REFBUF)
External reference voltage
External voltage reference (VREF)
Ω
1.2
V
VREF
External voltage reference
1.6
0.3
5.3
V
Input Current
mA
kΩ
Input impedance
Clock Input (CLKP/M)
Input clock frequency
0.5
65
MHz
Vpp
V
VID
Differential input voltage
1
3.6
VCM
Input common mode voltage
0.9
Single ended input resistance to
common mode
RIN
CIN
5
kΩ
Single ended input capacitance
1.5
50
pF
%
Clock duty cycle
40
60
Digital Inputs (RESET, PDN, SCLK, SEN, SDIO)
VIH
VIL
IIH
IIL
High level input voltage
Low level input voltage
High level input current
Low level input current
Input capacitance
1.4
V
0.4
V
90
-90
1.5
150
uA
uA
pF
-150
CI
Digital Output (SDOUT)
IOVDD
– 0.1
VOH
VOL
High level output voltage
Low level output voltage
ILOAD = -400 uA
ILOAD = 400 uA
IOVDD
V
V
0.1
SLVDS Interface
Output data rate
per differential SLVDS output pair
DCLKIN
1000
650
1.3
Mbps
VID
Differential input voltage
200
1
350
1.2
mVpp
VCM
VOD
VCM
Input common mode voltage
Differential output voltage
Output common mode voltage
V
V
V
500
700
1.0
850
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6.7 Electrical Characteristics - AC Specifications
Typical values are over the operating free-air temperature range, at TA = 25°C, full temperature range is TMIN = –40°C to
TMAX = 105°C, ADC sampling rate = 65 MSPS, 50% clock duty cycle, AVDD = IOVDD = 1.8 V, 1.6 V external reference, and
–1-dBFS differential input, unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
dBFS/Hz
dBFS
ADC3681 - 10 MSPS:
NSD
SNR
Noise Spectral Density
Signal to noise ratio
fIN = 1.1 MHz, AIN = –20 dBFS
fIN = 1.1 MHz, AIN = –20 dBFS
fIN = 1.1 MHz
–153
86
84.5
84.5
84.0
TBD
TBD
TBD
13.7
13.7
13.7
TBD
TBD
TBD
90
fIN = 4.9 MHz
TBD
TBD
TBD
TBD
TBD
TBD
fIN = 9.9 MHz
dBFS
fIN = 1.1 MHz
Signal to noise and
distortion ratio
SINAD
ENOB
THD
fIN = 4.9 MHz
dBFS
fIN = 9.9 MHz
fIN = 1.1 MHz
Effective number of bits
fIN = 4.9 MHz
bits
dBc
dBc
fIN = 9.9 MHz
fIN = 1.1 MHz
Total Harmonic Distortion
(First five harmonics)
fIN = 4.9 MHz
fIN = 9.9 MHz
fIN = 1.1 MHz
Spur free dynamic range
including second and third
harmonic distortion
SFDR
fIN = 4.9 MHz
90
fIN = 9.9 MHz
90
fIN = 1.1 MHz
100
100
100
Spur free dynamic range
(excluding HD2 and HD3)
Non HD2,3
IMD3
fIN = 4.9 MHz
dBFS
dBc
fIN = 9.9 MHz
Two tone inter-modulation
distortion
f1 = 1 MHz, f2 = 2 MHz, AIN = -7 dBFS/tone
TBD
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6.7 Electrical Characteristics - AC Specifications (continued)
Typical values are over the operating free-air temperature range, at TA = 25°C, full temperature range is TMIN = –40°C to
TMAX = 105°C, ADC sampling rate = 65 MSPS, 50% clock duty cycle, AVDD = IOVDD = 1.8 V, 1.6 V external reference, and
–1-dBFS differential input, unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ADC3682 - 25 MSPS:
NSD
SNR
Noise Spectral Density
Signal to noise ratio
fIN = 1.1 MHz, AIN = –20 dBFS
fIN = 1.1 MHz, AIN = –20 dBFS
fIN = 1.1 MHz
–157
86
dBFS/Hz
84.5
84.5
84.0
83.5
TBD
TBD
TBD
TBD
13.7
13.7
13.7
13.6
TBD
TBD
TBD
TBD
90
fIN = 5 MHz
TBD
TBD
TBD
TBD
TBD
TBD
dBFS
fIN = 10 MHz
fIN = 20 MHz
fIN = 1.1 MHz
fIN = 5 MHz
Signal to noise and
distortion ratio
SINAD
ENOB
THD
dBFS
bits
fIN = 10 MHz
fIN = 20 MHz
fIN = 1.1 MHz
fIN = 5 MHz
Effective number of bits
fIN = 10 MHz
fIN = 20 MHz
fIN = 1.1 MHz
fIN = 5 MHz
Total Harmonic Distortion
(First five harmonics)
dBc
dBc
fIN = 10 MHz
fIN = 20 MHz
fIN = 1.1 MHz
Spur free dynamic range
including second and third
harmonic distortion
fIN = 5 MHz
90
SFDR
fIN = 10 MHz
90
fIN = 20 MHz
88
fIN = 1.1 MHz
100
100
100
95
fIN = 5 MHz
Spur free dynamic range
(excluding HD2 and HD3)
Non HD2,3
IMD3
dBFS
dBc
fIN = 10 MHz
fIN = 20 MHz
f1 = 1 MHz, f2 = 2 MHz, AIN = -7 dBFS/tone
f1 = 10 MHz, f2 = 12 MHz, AIN = -7 dBFS/tone
TBD
TBD
Two tone inter-modulation
distortion
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6.7 Electrical Characteristics - AC Specifications (continued)
Typical values are over the operating free-air temperature range, at TA = 25°C, full temperature range is TMIN = –40°C to
TMAX = 105°C, ADC sampling rate = 65 MSPS, 50% clock duty cycle, AVDD = IOVDD = 1.8 V, 1.6 V external reference, and
–1-dBFS differential input, unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ADC3683 - 65 MSPS:
NSD
SNR
Noise Spectral Density
Signal to noise ratio
fIN = 1.1 MHz, AIN = –20 dBFS
fIN = 1.1 MHz, AIN = –20 dBFS
fIN = 1.1 MHz
–160
84.8
84.2
83.8
83.6
82.6
81.0
77.3
80.0
82.7
82.7
80.2
78.7
75.8
13.7
13.6
13.6
13.4
3.2
dBFS/Hz
fIN = 5 MHz
81.0
fIN = 10 MHz
dBFS
fIN = 20 MHz
fIN = 40 MHz
fIN = 70 MHz
fIN = 1.1 MHz
fIN = 5 MHz
fIN = 10 MHz
Signal to noise and
distortion ratio
SINAD
ENOB
THD
dBFS
fIN = 20 MHz
fIN = 40 MHz
fIN = 70 MHz
fIN = 1.1 MHz
fIN = 5 MHz
fIN = 10 MHz
Effective number of bits
bits
fIN = 20 MHz
fIN = 40 MHz
fIN = 70 MHz
12.5
81
fIN = 1.1 MHz
fIN = 5 MHz
80.5
81.5
90
88
fIN = 10 MHz
89
Total Harmonic Distortion
(First five harmonics)
dBc
fIN = 20 MHz
83
fIN = 40 MHz
82
fIN = 70 MHz
80
fIN = 1.1 MHz
82
fIN = 5 MHz
89
Spur free dynamic range
including second and third
harmonic distortion
fIN = 10 MHz
92
SFDR
dBc
fIN = 20 MHz
85
fIN = 40 MHz
84
fIN = 70 MHz
82
fIN = 1.1 MHz
101
101
100
97
fIN = 5 MHz
fIN = 10 MHz
Spur free dynamic range
(excluding HD2 and HD3)
Non HD2,3
dBFS
dBc
fIN = 20 MHz
fIN = 40 MHz
91
fIN = 70 MHz
88
f1 = 10 MHz, f2 = 12 MHz, AIN = -7 dBFS/tone
f1 = 40 MHz, f2 = 45 MHz, AIN = -7 dBFS/tone
90
Two tone inter-modulation
distortion
IMD3
85
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6.8 Timing Requirements
Typical values are over the operating free-air temperature range, at TA = 25°C, full temperature range is TMIN = –40°C to
TMAX = 105°C, ADC sampling rate = 65 MSPS, 50% clock duty cycle, AVDD = IOVDD = 1.8 V, 1.6 V external reference, and
–1-dBFS differential input, unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN NOM MAX
UNIT
ADC Timing Specifications
tAD
tA
Aperture Delay
Aperture Jitter
Jitter on DCLKIN
0.85
180
ns
fs
Square wave clock with fast edges
tJ
± 50
-TS/2
-TS/2
-TS/4
ps
FS = 10 Msps
FS = 25 Msps
FS = 65 Msps
Sampling
Clock
Period
Signal acquisition period, referenced
to sampling clock falling edge
tACQ
+TS ×
1/5
FS = 10 Msps
FS = 25 Msps
FS = 65 Msps
Sampling
Clock
Period
Signal conversion period, referenced
to sampling clock falling edge
+TS ×
3/8
tCONV
+TS ×
5/8
Bandgap reference enabled, single ended clock
Bandgap reference enabled, differential clock
Bandgap reference disabled, single ended clock
Bandgap reference disabled, differential clock
Bandgap reference enabled, single ended clock
Bandgap reference enabled, differential clock
Bandgap reference disabled, single ended clock
Bandgap reference disabled, differential clock
17.6
us
ms
us
12.9
Time to valid data after coming out of
power down. Internal reference.
2.2
2.2
Wake up
time
15.9
Time to valid data after coming out of
power down.
External 1.6V reference.
12.9
1.7
ms
ps
1.7
tS,SYNC
tH,SYNC
Setup time for SYNC input signal
Hold time for SYNC input signal
500
600
2
Referenced to sampling clock rising edge
SLVDS 2-wire
SLVDS 1-wire
SLVDS 1/2-wire
ADC
clock
cycles
ADC
Latency
Signal input to data output
1
1
Real decimation by 2
21
22
23
Output
clock
cycles
Add
Latency
Complex decimation by 2
Real or complex decimation by 4, 8, 16, 32
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6.8 Timing Requirements (continued)
Typical values are over the operating free-air temperature range, at TA = 25°C, full temperature range is TMIN = –40°C to
TMAX = 105°C, ADC sampling rate = 65 MSPS, 50% clock duty cycle, AVDD = IOVDD = 1.8 V, 1.6 V external reference, and
–1-dBFS differential input, unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN NOM MAX
UNIT
Interface Timing: Serial LVDS Interface
Delay between sampling clock falling edge to
DCLKIN falling edge < 2.5ns.
TDCLK = DCLK period
tCDCLK = Sampling clock falling edge to DCLKIN
falling edge
2 +
3 +
4 +
TDCLK TDCLK TDCLK
ns
+
+
+
tCDCLK tCDCLK tCDCLK
Propagation delay: sampling clock
falling edge to DCLK rising edge
tPD
Delay between sampling clock falling edge to
DCLKIN falling edge >= 2.5ns.
TDCLK = DCLK period
tCDCLK = Sampling clock falling edge to DCLKIN
falling edge
2 +
3 +
4 +
ns
tCDCLK tCDCLK tCDCLK
Fout = 10 MSPS, DA/B0,1 = 90 MBPS
Fout = 25 MSPS, DA/B0,1 = 225 MBPS
Fout = 65 MSPS, DA/B0,1 = 585 MBPS
Fout = 10 MSPS, DA/B0 = 180 MBPS
Fout = 25 MSPS, DA/B0 = 450 MBPS
Fout = 55 MSPS, DA/B0 = 990 MBPS
Fout = 5 MSPS, DA0 = 180 MBPS
Fout = 10 MSPS, DA0 = 360 MBPS
Fout = 25 MSPS, DA0 = 720 MBPS
Fout = 10 MSPS, DA/B0,1 = 90 MBPS
Fout = 25 MSPS, DA/B0,1 = 225 MBPS
Fout = 65 MSPS, DA/B0,1 = 585 MBPS
Fout = 10 MSPS, DA/B0 = 180 MBPS
Fout = 25 MSPS, DA/B0 = 450 MBPS
Fout = 55 MSPS, DA/B0 = 990 MBPS
Fout = 5 MSPS, DA0 = 180 MBPS
Fout = 10 MSPS, DA0 = 360 MBPS
Fout = 25 MSPS, DA0 = 900 MBPS
0
0
0.1
0.1
0.1
0.2
0.1
0.1
0.1
0.1
0.1
DCLK rising edge to output data
delay,
2-wire SLVDS
0
0.1
0
DCLK rising edge to output data
delay,
1-wire SLVDS
tCD
ns
-0.4
0
DCLK rising edge to output data
delay,
1/2-wire SLVDS
0
0
10.5 10.7
Data valid, 2-wire SLVDS
Data valid, 1-wire SLVDS
Data valid, 1/2-wire SLVDS
4.0
1.3
4.7
1.8
0.5
4.7
2.4
0.6
4.1
1.4
4.8
1.9
0.6
4.8
2.5
0.7
tDV
ns
SERIAL PROGRAMMING INTERFACE (SCLK, SEN, SDIO) - Input
fCLK(SCLK) Serial clock frequency
20
MHz
ns
tSU(SEN)
tH(SEN)
tSU(SDIO)
tH(SDIO)
SEN to rising edge of SCLK
SEN from rising edge of SCLK
SDIO to rising edge of SCLK
SDIO from rising edge of SCLK
10
9
ns
17
9
ns
ns
SERIAL PROGRAMMING INTERFACE (SDIO) - Output
t(OZD)
t(ODZ)
t(OD)
SDIO tri-state to driven
3.9
3.4
3.9
10.8
14
ns
ns
ns
SDIO data to tri-state
SDIO valid from falling edge of SCLK
10.8
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6.9 Typical Characteristics - ADC3683
Typical values at TA = 25 °C, ADC sampling rate = 65 MSPS, AIN = –1 dBFS differential input, AVDD = IOVDD =
1.8 V, external 1.6 V voltage reference, unless otherwise noted.
SNR = 84.2 dBFS, SFDR = 81 dBc, Non HD23 = 101 dBFS
SNR = 83.8 dBFS, SFDR = 89 dBc, Non HD23 = 99 dBFS
Figure 6-1. Single Tone FFT at FIN = 1 MHz
Figure 6-2. Single Tone FFT at FIN = 5 MHz
AIN = -20 dBFS, SNR = 84.8 dBFS, SFDR = 81 dBc, Non HD23
= 103 dBFS
SNR = 83.8 dBFS, SFDR = 92 dBc, Non HD23 = 98 dBFS
Figure 6-4. Single Tone FFT at FIN = 10 MHz
Figure 6-3. Single Tone FFT at FIN = 5 MHz
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SNR = 81.1 dBFS, SFDR = 84 dBc, Non HD23 = 95 dBFS
SNR = 77.3 dBFS, SFDR = 86 dBc, Non HD23 = 92 dBFS
Figure 6-5. Single Tone FFT at FIN = 40 MHz
Figure 6-6. Single Tone FFT at FIN = 64 MHz
SNR = 75.1 dBFS, SFDR = 75 dBc, Non HD23 = 93 dBFS
AIN = -7 dBFS/tone, IMD3 = 88 dBc
Figure 6-7. Single Tone FFT at FIN = 100 MHz
Figure 6-8. Two Tone FFT at FIN = 10/12 MHz
AIN = -20 dBFS/tone, IMD3 = 95 dBc
AIN = -7 dBFS/tone, IMD3 = 83 dBc
Figure 6-9. Two Tone FFT at FIN = 10/12 MHz
Figure 6-10. Two Tone FFT at FIN = 40/45 MHz
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Figure 6-11. AC Performance vs Input Frequency
Figure 6-12. ENOB vs Input Frequency
FIN = 5 MHz
FIN = 5 MHz
Figure 6-13. AC Performance vs Input Amplitude
Figure 6-14. AC Performance vs Sampling Rate
spacer
Single ended clock input
Figure 6-15. AC Performance vs Clock Amplitude
Figure 6-16. AC Performance vs Clock Amplitude
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FIN = 5 MHz
FIN = 5 MHz
Figure 6-17. AC Performance vs AVDD
Figure 6-18. AC Performance vs VCM vs
Temperature
FIN = 5 MHz
Figure 6-20. Isolation vs Input Frequency
Figure 6-19. AC Performance vs Clock Duty Cycle
FIN = 5 MHz
FIN = 5 MHz
Figure 6-21. INL vs Code
Figure 6-22. DNL vs Code
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Figure 6-23. DC Offset Histogram
FIN = 1 MHz
Figure 6-24. Pulse Response
FIN = 5 MHz, 2-wire
FIN = 5 MHz, DDC Bypass
Figure 6-26. IIOVDD Current vs Decimation
Figure 6-25. Current vs Sampling Rate
FIN = 5 MHz, Complex Decimation by 32
Figure 6-27. IIOVDD Current vs Output Interface
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7 Parameter Measurement Information
Sample N
Sample N+1
Input Signal
tAD
tPD
Sampling
Clock
tACQ
tConv
tCDCLK
DCLKIN
DCLK
tCD
TDCLK
FCLK
tDV
D
D
D
D
D
D
D
D
DA1/DB1
(MSB)
D9 D7 D5 D3 D1
D8 D6 D4 D2 D0
D9 D7 D5 D3 D1
D8 D6 D4 D2 D0
17 15 13 11
17 15 13 11
D
D
D
D
D
D
D
D
DA0/DB0
(MSB)
16 14 12 10
16 14 12 10
Sample N-1
Sample N-3
Sample N-2
Figure 7-1. Timing diagram: 2-wire SLVDS
Sample N
Sample N+1
Input Signal
tAD
tPD
Sampling
Clock
tACQ
tConv
tCDCLK
DCLKIN
DCLK
FCLK
tCD
TDCLK
tDV
D
D
D
D
D
D
17 16 15 14 13 12 11 10
D
D
D5 D4 D3 D2 D1 D0
D5 D4 D3 D2 D1 D0
D2 D1 D0
D9 D8 D7 D6
DA0
DB0
D D
17 16 15 14 13 12 11 10
D
D
D
D
D
D
D2 D1 D0
D9 D8 D7 D6
Sample N-2
Sample N-1
Figure 7-2. Timing diagram: 1-wire SLVDS
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Sample N
tAD
Sample N+1
Input Signal
tPD
Sampling
Clock
tACQ
tConv
tCDCLK
DCLKIN
DCLK
FCLK
tCD
TDCLK
tDV
Channel A
Channel B
D
0
D
1
D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D
1716 15 1413 12 11 10 9 8 7 6 5 4 3 2 1 0 17 16 1514 13 12 11 10 9 8 7 6 5 4 3 2
DA0
Sample N-2
Sample N-1
Figure 7-3. Timing diagram: 1/2-wire SLVDS
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8 Detailed Description
8.1 Overview
The ADC368x is a low noise, ultra-low power 18-bit high-speed dual channel ADC family supporting sampling
rates up to 65 MSPS. It offers excellent DC precision together with IF sampling support which makes it ideally
suited for a wide range of applications. The ADC368x is equipped with an internal reference option but it also
supports the use of an external, high precision 1.6 V voltage reference or an external 1.2 V reference which is
buffered and gained up internally. Because of the inherent low latency architecture, the digital output result is
available after only one or two clock cycles depending on the digital output interface.
An optional programmable digital down converter enables external anti-alias filter relaxation as well as output
data rate reduction. The digital filter provides a 32-bit programmable NCO and supports both real or complex
decimation.
The ADC368x uses a serial LVDS (SLVDS) interface to output the data which minimizes the number of digital
interconnects. The device supports a two-lane (2-wire), a one-lane (1-wire) and a half-lane (1/2-wire) option. The
ADC368x includes a digital output formatter which supports output resolutions from 14 to 20-bit.
The device features and control options can be set up either through pin configurations or via SPI register writes.
8.2 Functional Block Diagram
REFBUF
1.2V REF
Digital Downconverter
NCO
VREF
Crosspoint
Switch
ADC
18bit
N
AIN
DCLKIN
DCLK
0.95V
VCM
FCLK
Dig I/F
SLVDS
NCO
DA0/1
DB0/1
ADC
18bit
N
BIN
CLK
Control
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8.3 Feature Description
8.3.1 Analog Input
The analog inputs of ADC368x are intended to be driven differentially. Both AC coupling and DC coupling of the
analog inputs is supported. The analog inputs are designed for an input common mode voltage of 0.95 V which
must be provided externally on each input pin. DC-coupled input signals must have a common mode voltage that
meets the device input common mode voltage range.
The equivalent input network diagram is shown in Figure 8-1. All four sampling switches, on-resistance shown in
red are in same position (open or closed) simultaneously.
AVDD
Sampling Switch
0.32 pF
1 ꢀ
125 ꢀ
2 nH
xINP/
xINM
24 ꢀ
1.4 pF
0.15 pF
0.6 pF
GND
0.6 pF
GND
GND
GND
GND
6.4 pF
7 ꢀ
GND
5 ꢀ
0.7 pF
1.6 pF
GND
GND
GND
Figure 8-1. Equivalent input network
8.3.1.1 Analog Input Bandwidth
Figure 8-2 shows the analog full power input bandwidth of the ADC368x with a 50 Ω differential termination. The
-3 dB bandwidth is approximately 900 MHz and the useful input bandwidth with good AC performance is
approximately 120 MHz.
The equivalent differential input resistance RIN and input capacitance CIN vs frequency are shown in Figure 8-3.
0
-1
-2
-3
-4
-5
-6
10
100
Input Frequency (MHz)
1000
ADC3
Figure 8-3. Equivant RIN, CIN vs Input Frequency
Figure 8-2. ADC Analog Input bandwidth response
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8.3.1.2 Analog Front End Design
The ADC368x is an unbuffered ADC and thus a passive kick-back filter is recommended to absorb the glitch
from the sampling operation. Depending on if the input is driven by a balun or a differential amplifier with low
output impedance, a termination network may be needed. Additionally a passive DC bias circuit is needed in AC-
coupled applications which can be combined with the termination network.
8.3.1.2.1 Sampling Glitch Filter Design
The front end sampling glitch filter is designed to optimize the SNR and HD3 performance of the ADC. The filter
performance is dependent on input frequency and therefore the following filter designs are recommended for
different input frequency ranges as shown in Figure 8-4 and Figure 8-5 (assuming a 50 Ω source impedance).
33 ꢀ
10 ꢀ
180nH
100 pF
Termination
33 ꢀ
180nH
10 ꢀ
Figure 8-4. Sampling glitch filter example for input frequencies from DC to 30 MHz
33 ꢀ
10 ꢀ
100pF
120nH
82 pF
Termination
33 ꢀ
10 ꢀ
100pF
120nH
Figure 8-5. Sampling glitch filter example for input frequencies from 30 to 70 MHz
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8.3.1.2.2 Analog Input Termination and DC Bias
Depending on the input drive circuitry, a termination network and/or DC biasing needs to be provided.
8.3.1.2.2.1 AC-Coupling
The ADC368x requires external DC bias using the common mode output voltage (VCM) of the ADC together
with the termination network as shown in Figure 8-6. The termination is located within the glitch filter network.
When using a balun on the input, the termination impedance has to be adjusted to account for the turns ratio of
the transformer. When using an amplifier, the termination impedance can be adjusted to optimize the amplifier
performance.
Glitch Filter
Termination
33 ꢀ
1 uF
10 ꢀ
180nH
25 ꢀ
100 pF
VCM
0.1 …F
25 ꢀ
33 ꢀ
1 uF
VCM
180nH
10 ꢀ
Figure 8-6. AC-Coupling: termination network provides DC bias (glitch filter example for DC - 30 MHz)
8.3.1.2.2.2 DC-Coupling
In DC coupled applications the DC bias needs to be provided from the fully differential amplifier (FDA) using
VCM output of the ADC as shown in Figure 8-7. The glitch filter in this case is located between the anti-alias filter
and the ADC. No termination may be needed if amplifier is located close to the ADC or if the termination is part
of the anti-alias filter.
Glitch Filter
33 ꢀ
10 ꢀ
180nH
100 pF
AAF (Anti
Alias Filter)
33 ꢀ
VCM
180nH
10 ꢀ
Figure 8-7. DC-Coupling: DC bias provided by FDA (glitch filter example for DC - 30 MHz)
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8.3.1.3 Auto-Zero Feature
The ADC368x includes an internal auto-zero front end amplifier circuit which improves the 1/f flicker noise. This
auto-zero feature is enabled by default for the ADC3681/2 and can be enabled using SPI register writes for the
ADC3683 (register 0x11, D0).
0
-20
-80
-90
Auto-zero DIS
Auto-zero EN
Auto-zero DIS
Auto-zero EN
-40
-100
-110
-120
-130
-140
-150
-160
-60
-80
-100
-120
-140
-160
0
2.5
5
7.5
10
12.5
0.01
0.1
1
10
100
1000
Frequency (MHz)
Frequency (kHz)
adc3
adc3
Figure 8-8. FFT at 25 MSPS with input frequency of Figure 8-9. FFT at 25 MSPS with input frequency of
3 MHz (auto-zero feature enable vs disable, 4M
point FFT)
3 MHz (auto-zero feature enable vs disable, 4M
point FFT)
Figure 8-11. FFT at 65 MSPS with input frequency
of 5 MHz (auto-zero feature enabled vs disabled,
4M point FFT)
Figure 8-10. FFT at 65 MSPS with input frequency
of 5 MHz (auto-zero feature enable vs disable, 4M
point FFT)
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8.3.2 Clock Input
In order to maximize the ADC SNR performance, the external sampling clock should be low jitter and differential
signaling with a high slew rate. This is especially important in IF sampling applications (Figure 8-12 and Figure
8-13). For less jitter sensitive applications, the ADC368x provides the option to operate with single ended
signaling which saves additional power consumption.
Figure 8-12. AC Performance vs Clock Amplitude
(Differential Clock Input)
Figure 8-13. AC Performance vs Clock Amplitude
(Single Ended Clock Input)
8.3.2.1 Single Ended vs Differential Clock Input
The ADC368x can be operated using a differential or a single ended clock input where the single ended clock
consumes less power consumption. However clock amplitude impacts the ADC aperture jitter and consequently
the SNR. For maximum SNR performance, a large clock signal with fast slew rates needs to be provided.
•
•
Differential Clock Input: The clock input can be AC coupled externally. The ADC368x provides internal bias.
Single Ended Clock Input: This mode needs to be configured using SPI register (0x0E, D2 and D0) or with
the REFBUF pin. In this mode there is no internal clock biasing and thus the clock input needs to be DC
coupled around a 0.9V center. The unused input needs to be AC coupled to ground.
1.8V
CLKP
CLKP
0.9V
0V
+
-
5kO
VCM
0.9V
5kO
CLKM
CLKM
Figure 8-14. External and internal connection using differential (left) and single ended (right) clock input
8.3.2.2 Signal Acquisition Time Adjust
The ADC368x includes a register (DLL PDN (0x11, D2) which increases the signal acquisition time window for
clock rates below 40 MSPS from 25% to 50% of the clock period. Increasing the sampling time provides a longer
time for the driving amplifier to settle out the signal which can improve the SNR performance of the system. This
register should only be used for the 65 MSPS speed grade (ADC3683) For the 10 and 25 MSPS device speed
grades the sampling time is already set to TS/2. When powering down the DLL, the acquisition time will track the
clock duty cycle (50% is recommended).
Table 8-1. Acquisition time vs DLL PDN setting
SAMPLING CLOCK FS (MSPS)
DLL PDN (0x11, D2)
ACQUISITION TIME (tACQ)
65
0
1
TS / 4
TS / 2
≤ 40
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8.3.3 Voltage Reference
The ADC368x provides three different options for supplying the voltage reference to the ADC. An external 1.6 V
reference can be directly connected to the VREF input; a voltage 1.2 V reference can be connected to the
REFBUF input using the internal gain buffer or the internal 1.2 V reference can be enabled to generate a 1.6 V
reference voltage. For best performance, the reference noise should be filtered by connecting a 10 uF and a 0.1
uF ceramic bypass capacitor to the VREF pin. The internal reference circuitry of the ADC368x is shown in Figure
8-15.
Note
The voltage reference mode can be selected using SPI writes or by using the REFBUF pin (default) as
a control pin (Section 8.5.1). If the REFBUF pin is not used for configuration, the REFBUF pin should
be connected to AVDD (even though the REFBUF pin has a weak internal pullup to AVDD) and the
voltage reference option has to be selected using the SPI interface.
xINP
xINM
0.95V
VCM
VREF
(1.6V)
x1.33
REFBUF
(1.2V)
VREF1.2
REFGND
Figure 8-15. Different voltage reference options for ADC368x
8.3.3.1 Internal voltage reference
The 1.6 V reference for the ADC can be generated internal using the on-chip 1.2V bandgap reference along with
the internal gain buffer. A 10 uF and a 0.1 uF ceramic bypass capacitor (CVREF) should be connected between
the VREF and REFGND pins as close to the pins as possible.
xINP
xINM
0.95V
VCM
VREF
(1.6V)
x1.33
CVREF
REFBUF
(1.6V)
VREF1.2
REFGND
Figure 8-16. Internal reference
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8.3.3.2 External voltage reference (VREF)
For highest accuracy and lowest temperature drift, the VREF input can be directly connected to an external 1.6 V
reference. A 10 uF and a 0.1 uF ceramic bypass capacitor (CVREF) connected between the VREF and REFGND
pins and placed as close to the pins as possible is recommended. The load current from the external reference
is about 1mA.
Note: The internal reference is also used for other functions inside the device, therefore the reference amplifier
should only be powered down in power down state but not during normal operation.
xINP
xINM
0.95V
VCM
VREF
(1.6V)
Reference
1.6V
REFBUF
(1.2V)
x1.33
CVREF
VREF1.2
REFGND
Figure 8-17. External 1.6 V reference
8.3.3.3 External voltage reference with internal buffer (REFBUF)
The ADC368x is equipped with an on-chip reference buffer that also includes gain to generate the 1.6 V
reference voltage from an external 1.2V reference. A 10 uF and a 0.1 uF ceramic bypass capacitor (CVREF
)
between the VREF and REFGND pins and a 10 uF and a 0.1 uF ceramic bypass capacitor between the
REFBUF and REFGND pins are recommended. Both capacitors should be placed as close to the pins as
possible. The load current from the external reference is less than 100uA.
xINP
xINM
0.95V
VCM
VREF
(1.6V)
x1.33
REFBUF
(1.2V)
Reference
1.2V
VREF1.2
CREFBUF
CVREF
REFGND
Figure 8-18. External 1.2V reference using internal reference buffer
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8.3.4 Digital Down Converter
The ADC368x includes an optional on-chip digital down conversion (DDC) decimation filter that can be enabled
via SPI register settings. It supports complex decimation by 2, 4, 8, 16 and 32 using a digital mixer and a 32-bit
numerically controlled oscillator (NCO) as shown in Figure 8-19.
Furthermore it supports a mode with real decimation where the complex mixer is bypassed (NCO should be set
to 0 for lowest power consumption) and the digital filter acts as a low pass filter.
Internally the decimation filter calculations are performed with a 20-bit resolution in order to avoid any SNR
degradation due to quantization noise limitation. The Section 8.3.5.1 truncates to the selected resolution prior to
outputting the data on the digital interface.
NCO
32bit
Filter
I
Q
I
Q
Digital
Interface
N
ADC
SYNC
Figure 8-19. Internal Digital Decimation Filter
8.3.4.1 DDC MUX
The ADC368x contains a MUX in front of the digital decimation filter which allows ADC ChA to be connected to
DDC ChB and vice versa. This feature is enabled and controlled using the SPI interface. Subsequently the
output interface corresponds to the DDC channel A and B.
Digital Downconverter
NCO
DDC MUX
N
ADC
NCO
N
ADC
Figure 8-20. DDC MUX
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8.3.4.2 Digital Filter Operation
The complex decimation operation is illustrated with an example in Figure 8-21. First the input signal (and the
negative image) are frequency shifted by the NCO frequency as shown on the left. Next a digital filter is applied
(centered around 0 Hz) and the output data rate is decimated by 8 complex - in this example the output data rate
FS,OUT = FS/8 with a Nyquist zone of FS/16. During the complex mixing the spectrum (signal and noise) is split
into real and complex parts and thus the amplitude is reduced by 6-dB. In order to compensate this loss, there is
a 6-dB digital gain option in the decimation filter block that can be enabled via SPI write.
Input Signal
(Alias)
Shifted Input
Signal (Alias)
-FIN + FNCO
Shifted Input Signal
Negative Image
Input Signal
Negative Image
Decimation
by 8
FIN + FNCO
0
0
-FS/16
FS/16
FS/2
-FS/2
-FS/2
FS/2
FNCO
NCO Tuning Range
Figure 8-21. Complex decimation illustration
The real decimation operation is illustrated with an example in Figure 8-22. There is no frequency shift
happening and only the real portion of the complex digital filter is exercised. The output data rate is decimated -
a decimation of 8 would result in an output data rate FS,OUT = FS/8 with a Nyquist zone of FS/16.
During the real mixing the spectrum (signal and noise) amplitude is reduced by 3-dB. In order to compensate this
loss, there is a 3-dB digital gain option in the decimation filter block that can be enabled via SPI write.
Input Signal
Decimation by
32
Decimation by
16
Decimation by 2
Decimation by 4
Decimation by 8
FS/2
FS/16
FS/8
FS/4
FS/32
FS/64
Figure 8-22. Real decimation illustration
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8.3.4.3 FS/4 Mixing with Real Output
In this mode, the output after complex decimation gets mixed with FS/4 (FS = output data rate in this case).
Instead of a complex output with the input signal centered around 0 Hz, the output is transmitted as a real output
at twice the data rate and the signal is centered around FS/4 (Fout/4) as illustrated in Figure 8-23.
In this example, complex decimation by 8 is used. The output data is transmitted as a real output with an output
rate of Fout = FS'/4 (FS' = ADC sampling rate). The input signal is now centered around FS/4 (Fout/4) or FS'/16.
FIN
FNCO
- FIN + FNCO
-FIN + FNCO + FS/4
/8
FS/4 mix
Fout/4 mix
Complex
Decimation /8
0
0
FS‘/2
FS/16
FS‘/2
FS/8
0
FS/2
Figure 8-23. FS/4 Mixing with real output
8.3.4.4 Numerically Controlled Oscillator (NCO) and Digital Mixer
The decimation block is equipped with a 32-bit NCO and a digital mixer to fine tune the frequency placement
prior to the digital filtering. The oscillator generates a complex exponential sequence of:
ejωn (default) or e–jωn
(1)
where: frequency (ω) is specified as a signed number by the 32-bit register setting
The complex exponential sequence is multiplied with the real input from the ADC to mix the desired carrier to a
frequency equal to fIN + fNCO. The NCO frequency can be tuned from –FS/2 to +FS/2 and is processed as a
signed, 2s complement number. After programming a new NCO frequency, the MIXER RESTART register bit or
SYNC pin has to be toggled for the new frequency to get active. Additionally the ADC368x provides the option
via SPI to invert the mixer phase.
The NCO frequency setting is set by the 32-bit register value given and calculated as:
NCO frequency = 0 to + FS/2: NCO = fNCO × 232 / FS
NCO frequency = -FS/2 to 0: NCO = (fNCO + FS) × 232 / FS
where:
•
•
•
NCO = NCO register setting (decimal value)
fNCO = Desired NCO frequency (MHz)
FS = ADC sampling rate (MSPS)
The NCO programming is further illustrated with this example:
•
•
•
ADC sampling rate FS = 65 MSPS
Input signal fIN = 10 MHz
Desired output frequency fOUT = 0 MHz
For this example there are actually four ways to program the NCO and achieve the desired output frequency as
shown in Table 8-2.
Table 8-2. NCO value calculations example
Alias or negative image
fIN = –10 MHz
fNCO
NCO Value
660764199
3634203097
660764199
3634203097
Mixer Phase
Frequency translation for fOUT
fNCO = 10 MHz
fNCO = –10 MHz
fNCO = 10 MHz
fNCO = –10 MHz
fOUT = fIN + fNCO = –10 MHz +10 MHz = 0 MHz
fOUT = fIN + fNCO = 10 MHz + (–10 MHz) = 0 MHz
fOUT = fIN – fNCO = 10 MHz – 10 MHz = 0 MHz
fOUT = fIN – fNCO = –10 MHz – (–10 MHz) = 0 MHz
as is
fIN = 10 MHz
fIN = 10 MHz
inverted
fIN = –10 MHz
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8.3.4.5 Decimation Filter
The ADC368x supports complex decimation by 2, 4, 8, 16 and 32 with a stopband rejection of at least 85 dB and
a pass-band bandwidth of ~ 80%. Table 8-3 gives an overview of the pass-band bandwidth of the different
decimation settings with respect to ADC sampling rate FS. In real decimation mode the output bandwidth is half
of the complex bandwidth.
Table 8-3. Decimation Filter Summary and Maximum Available Output Bandwidth
REAL/COMPLEX
DECIMATION
DECIMATION
SETTING N
OUTPUT
BANDWIDTH
OUTPUT RATE
(FS = 65 MSPS)
OUTPUT BANDWIDTH
(FS = 65 MSPS)
OUTPUT RATE
2
4
FS / 2 complex
FS / 4 complex
FS / 8 complex
FS / 16 complex
FS / 32 complex
FS / 2 real
0.8 × FS / 2
0.8 × FS / 4
0.8 × FS / 8
0.8 × FS / 16
0.8 × FS / 32
0.4 × FS / 2
0.4 × FS / 4
0.4 × FS / 8
0.4 × FS / 16
0.4 × FS / 32
32.5 MSPS complex
16.25 MSPS complex
8.125 MSPS complex
4.0625 MSPS complex
2.03125 MSPS complex
32.5 MSPS
26 MHz
13 MHz
Complex
8
6.5 MHz
16
32
2
3.25 MHz
1.625 MHz
13 MHz
4
FS / 4 real
16.25 MSPS
6.5 MHz
Real
8
FS / 8 real
8.125 MSPS
3.25 MHz
1.625 MHz
0.8125 MHz
16
32
FS / 16 real
4.0625 MSPS
FS / 32 real
2.03125 MSPS
The decimation filter responses are normalized to the ADC sampling clock frequency FS and illustrated in Figure
8-25 to Figure 8-34. They are interpreted as follows:
Each figure contains the filter pass-band, transition band(s) and alias or stop-band(s) as shown in Figure 8-24.
The x-axis shows the offset frequency (after the NCO frequency shift) normalized to the ADC sampling rate FS.
For example, in the divide-by-4 complex setup, the output data rate is FS / 4 complex with a Nyquist zone of FS /
8 or 0.125 × FS. The transition band (colored in blue) is centered around 0.125 × FS and the alias transition band
is centered at 0.375 × FS. The stop-bands (colored in red), which alias on top of the pass-band, are centered at
0.25 × FS and 0.5 × FS. The stop-band attenuation is greater than 85 dB.
0
Passband
Transition Band
-20
Alias Band
Attn Spec
Filter
Transition
Bands
-40
-60
Bands that alias on top
of signal band
Pass Band
-80
-100
-120
0
0.1
0.2
0.3
0.4
0.5
Normalized Frequency (Fs)
Figure 8-24. Interpretation of the Decimation Filter Plots
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0
0.1
0.09
0.08
0.07
0.06
0.05
0.04
0.03
0.02
0.01
0
Passband
Passband
Transition Band
Alias Band
Attn Spec
Transition Band
Alias Band
Attn Spec
-20
-40
-60
-0.01
-0.02
-0.03
-0.04
-0.05
-0.06
-0.07
-0.08
-0.09
-0.1
-80
-100
-120
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
0
0.025 0.05 0.075
0.1
0.125 0.15 0.175
0.2
0.225 0.25
Normalized Frequency (Fs)
Normalized Frequency (Fs)
Decb
Decb
Figure 8-25. Decimation by 2 complex frequency
response
Figure 8-26. Decimation by 2 complex passband
ripple response
0
0
Passband
Transition Band
Alias Band
Passband
Transition Band
Alias Band
Attn Spec
-0.01
-0.02
-20
-40
Attn Spec
-0.03
-0.04
-0.05
-0.06
-0.07
-0.08
-0.09
-0.1
-60
-80
-100
-120
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
0
0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1 0.11 0.12
Normalized Frequency (Fs)
Normalized Frequency (Fs)
Decb
Decb
Figure 8-27. Decimation by 4complex frequency
response
Figure 8-28. Decimation by 4 complex passband
ripple response
0
-0.08
Passband
Transition Band
Alias Band
Passband
-0.081
-0.082
-0.083
-0.084
-0.085
-0.086
-0.087
-0.088
-0.089
-0.09
Transition Band
Alias Band
Attn Spec
-20
-40
Attn Spec
-60
-0.091
-0.092
-0.093
-0.094
-0.095
-0.096
-0.097
-0.098
-0.099
-0.1
-80
-100
-120
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
0
0.006 0.012 0.018 0.024 0.03 0.036 0.042 0.048 0.054 0.06
Normalized Frequency (Fs)
Normalized Frequency (Fs)
Decb
Decb
Figure 8-29. Decimation by 8 complex frequency
response
Figure 8-30. Decimation by 8 complex passband
ripple response
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0
-20
-0.1
-0.11
-0.12
-0.13
-0.14
-0.15
-0.16
-0.17
-0.18
-0.19
-0.2
Passband
Passband
Transition Band
Alias Band
Attn Spec
Transition Band
Alias Band
Attn Spec
-40
-60
-80
-100
-120
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
0
0.003 0.006 0.009 0.012 0.015 0.018 0.021 0.024 0.027 0.03
Normalized Frequency (Fs)
Normalized Frequency (Fs)
Decb
Decb
Figure 8-31. Decimation by 16 complex frequency Figure 8-32. Decimation by 16 complex passband
response ripple response
0
-0.2
-0.205
-0.21
Passband
Passband
Transition Band
Alias Band
Attn Spec
Transition Band
Alias Band
Attn Spec
-20
-0.215
-0.22
-40
-60
-0.225
-0.23
-80
-0.235
-0.24
-100
-120
-0.245
-0.25
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
0
0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018 0.02
Normalized Frequency (Fs)
Normalized Frequency (Fs)
Decb
Decb
Figure 8-33. Decimation by 32 complex frequency Figure 8-34. Decimation by 32 complex passband
response ripple response
8.3.4.6 SYNC
The PDN/SYNC pin can be used to synchronize multiple devices using an external SYNC signal. The PDN/
SYNC pin can be configured via SPI (SYNC EN bit) from power down to synchronization functionality and is
latched in by the rising edge of the sampling clock as shown in Figure 8-35.
CLK
tS,SYNC
tH,SYNC
SYNC
Figure 8-35. External SYNC timing diagram
The synchronization signal is only required when using the decimation filter - either using the SPI SYNC register
or the PDN/SYNC pin. It resets internal clock dividers used in the decimation filter and aligns the internal clocks
as well as I and Q data within the same sample. If no SYNC signal is given the internal clock dividers will not be
synchronized, which can lead to a fractional delay across different devices. The SYNC signal also resets the
NCO phase and loads the new NCO frequency (same as the MIXER RESTART bit).
When trying to resynchronize during operation, the SYNC toggle should occur at 64*K clock cycles, where K is
an integer. This ensures phase continuity of the clock divider.
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8.3.4.7 Output Formatting with Decimation
When using decimation, the digital output data is formatted as shown in Figure 8-36 (complex decimation) and
Figure 8-37 (real decimation).The output format is illustrated for 18-bit output resolution.
FCLK
AI
AI
AI
AI
AI
AI
D7
AI
AI
AI
AQ
AQ AQ
AQ
AQ
AQ
D7 D5
AQ
AQ AQ
D3 D1
DA1
DA0
D17 D15 D13 D11 D9
D5 D3
D1 D17 D15 D13 D11 D9
ChA
ChB
AI
AI
AI
AI
AI
AI
D6
AI
D4
AI
D2
AI
AQ
AQ
AQ
AQ
AQ
AQ
D6 D4
AQ
AQ
AQ
D16 D14 D12 D10 D8
D0 D16 D14 D12 D10 D8
D2 D0
Serial LVDS
2-Wire
(9x Serialization)
BI
BI
BI
BI
BI
BI
D7
BI
BI
BI
BQ
BQ
BQ
BQ
BQ
BQ
D7 D5
BQ
BQ
D3
BQ
D1
DB1
D17 D15 D13 D11 D9
D5 D3
D1 D17 D15 D13 D11 D9
BI
BI
BI
BI
BI
BI
D6
BI
D4
BI
D2
BI
BQ
BQ BQ
BQ
BQ
BQ
D6 D4
BQ
BQ
D2 D0
BQ
DB0
D16 D14 D12 D10 D8
D0 D16 D14 D12 D10 D8
DCLK
FCLK
DA0
Serial LVDS
1-Wire
AI <17:0>
AQ <17:0>
(18x Serialization)
DB0
BI <17:0>
BQ <17:0>
DCLK
FCLK
DA0
Serial LVDS
1/2-Wire
AI <17:0>
BI <17:0>
AQ <17:0>
BQ <17:0>
(36x Serialization)
DCLK
Figure 8-36. Output Data Format in Complex Decimation (18-bit Output Resolution)
Table 8-4 illustrates the output interface data rate along with the corresponding DCLK/DCLKIN and FCLK
frequencies based on output resolution (R), number of SLVDS lanes (L) and complex decimation setting (N).
Furthermore the table shows an actual lane rate example for the 2-, 1- and 1/2-wire interface, 18-bit output
resolution and complex decimation by 4.
Table 8-4. Serial LVDS Lane Rate Examples with Complex Decimation and 18-bit Output Resolution
DECIMATION
SETTING
ADC SAMPLING
RATE
OUTPUT
RESOLUTION
# of WIRES
FCLK
DCLKIN, DCLK
DA/B0,1
N
FS
R
L
2
FS / N
[DA/B0,1] / 2
146.25 MHz
292.5 MHz
495 MHz
FS x 2 x R / L / N
292.5 MHz
585 MHz
65 MSPS
55 MSPS
16.25 MHz
13.75 MHz
4
18
1
1/2
990 MHz
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FCLK
DA1
A0
A0
A0
A0
A0
A0
A0
D5
A0
D3
A0
D1
A1
A1
A1
A1
A1
A1
A1
A1
D3
A1
D1
D17 D15 D13 D11 D9 D7
D17 D15 D13 D11 D9
D7 D5
ChA
A0
A0
A0
A0
A0
A0
A0
D4
A0
D2
A0
A1
A1
A1
A1
A1
A1
A1
A1
D2
A1
D0
DA0
DB1
D16 D14 D12 D10 D8 D6
D0 D16 D14 D12 D10 D8
D6 D4
Serial LVDS
2-Wire
(9x Serialization)
B0
B0
B0
B0
B0
B0
D7
B0
B0
B0
B1
B1
B1
B1
B1
B1
D7
B1
B1
B1
D1
D17 D15 D13 D11 D9
D5 D3
D1 D17 D15 D13 D11 D9
D5 D3
ChB
B0
B0
B0
B0
B0
B0
D6
B0
B0
B0
B1
B1
B1
B1
B1
B1
D6
B1
B1
B1
D0
DB0
D16 D14 D12 D10 D8
D4 D2
D0 D16 D14 D12 D10 D8
D4 D2
DCLK
FCLK
DA0
A0 <17:9>
A0 <8:0>
Serial LVDS
1-Wire
(18x Serialization)
DB0
B0 <17:9>
B0 <8:0>
DCLK
FCLK
DA0
Serial LVDS
1/2-Wire
A0 <17:0>
B0 <17:0>
(36x Serialization)
DCLK
Figure 8-37. Output Data Format in Real Decimation (18-bit Output Resolution)
Table 8-5 illustrates the output interface data rate along with the corresponding DCLK/DCLKIN and FCLK
frequencies based on output resolution (R), number of SLVDS lanes (L) and real decimation setting (M).
Furthermore the table shows an actual lane rate example for the 2-, 1- and 1/2-wire interface, 18-bit output
resolution and real decimation by 4.
Table 8-5. Serial LVDS Lane Rate Examples with Real Decimation and 18-bit Output Resolution
DECIMATION
SETTING
ADC SAMPLING
RATE
OUTPUT
RESOLUTION
# of WIRES
FCLK
DCLKIN, DCLK
DA/B0,1
FS / M / 2 (L = 2)
FS / M (L = 1, 1/2)
M
FS
R
L
[DA/B0,1] / 2
FS x R / L / M
2
1
8.125 MHz
73.125 MHz
146.25 MHz
292.5 MHz
146.25 MHz
292.5 MHz
585 MHz
4
65 MSPS
18
16.25 MHz
1/2
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8.3.5 Digital Interface
The serial LVDS interface supports the data output with 2-wire, 1-wire and 1/2-wire operation. The actual data
output rate depends on the output resolution and number of lanes used.
The ADC368x requires an external serial LVDS clock input (DCLKIN), which is used to transmit the data out of
the ADC along with the data clock (DCLK). The phase relationship between DCLKIN and the sampling clock is
irrelevant but both clocks need to be frequency locked. The SLVDS interface is configured using SPI register
writes.
8.3.5.1 Output Formatter
The digital output interface utilizes a flexible output bit mapper (Figure 8-38). The bit mapper takes the 18-bit
output directly from the ADC or from the digital decimation filter block and reformats it to a resolution of 14,16,18
or 20-bit. The output serialization factor gets adjusted accordingly for 2-, 1- and 1/2-wire interface modes. The
maximum SLVDS interface output data rate can not be exceeded independent of output resolution or
serialization factor.
For 14 and 16-bit output resolution the LSBs simply get truncated during the reformatting. With 20-bit output, in
bypass mode two 0s are added in place of the two LSBs while in decimation mode and the digital averaging
mode the full 20-bit output is utilized.
Output Bit
Mapping
14 Bit
16 Bit
18 Bit
20 Bit
NCO
18-Bit
Output
SLVDS
Interface
18-Bit ADC
N
Figure 8-38. Interface output bit mapper
Table 8-6 provides an overview for the resulting serialization factor depending on output resolution and output
modes. Note that the DCLKIN frequency needs to be adjusted accordingly as well. Changing the output
resolution to 16-bit, 2-wire mode for example would result in DCLKIN = FS * 4 instead of * 4.5.
Table 8-6. Serialization factor vs output resolution for different output modes
OUTPUT
RESOLUTION
Interface SERIALIZATION
FCLK
DCLKIN
DCLK
D0/D1
2-Wire
1-Wire
7x
FS/2
FS
FS* 3.5
FS* 7
FS* 3.5
FS* 7
FS* 7
FS* 14
FS* 28
FS* 8
14-bit
14x
28x
8x
1/2-Wire
2-Wire
FS
FS* 14
FS* 4
FS* 14
FS* 4
FS/2
FS
16-bit
18-bit (default)
20-bit
1-Wire
16x
32x
9x
FS* 8
FS* 8
FS* 16
FS* 32
FS* 9
1/2-Wire
2-Wire
FS
FS* 16
FS* 4.5
FS* 9
FS* 16
FS* 4.5
FS* 9
FS/2
FS
1-Wire
18x
36x
10x
20x
40x
FS* 18
FS* 36
FS* 10
FS* 20
FS* 40
1/2-Wire
2-Wire
FS
FS* 18
FS* 5
FS* 18
FS* 5
FS/2
FS
1-Wire
FS* 10
FS* 20
FS* 10
FS* 20
1/2-Wire
FS
The programming sequence to change the output interface and/or resolution from default settings is shown in
Section 8.3.5.2.
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8.3.5.2 Output Interface/Mode Configuration
The following sequence summarizes all the relevant registers for changing the output interface and/or enabling
the decimation filter. Steps 1 and 2 must come first since the E-Fuse load reset the SPI writes, the remaining
steps can come in any order.
Table 8-7. Configuration steps for changing interface or decimation
STEP
FEATURE
ADDRESS
DESCRIPTION
1
0x07
Select the output interface bit mapping depending on resolution and output interface.
Output Resolution
14-bit
2-wire
0x2B
0x4B
0x2B
0x4B
1-wire
1/2-wire
0x8D
16-bit
0x6C
18-bit
20-bit
Load the output interface bit mapping using the E-fuse loader (0x13, D0). Program register 0x13 to
0x01, wait ~ 1ms so that bit mapping is loaded properly followed by 0x13 0x00
2
3
0x13
0x19
Configure the FCLK frequency based on bypass/decimation and number of lanes used.
FCLK SRC
(D7)
FCLK DIV
(D4)
TOG FCLK
(D0)
Bypass/Dec
SLVDS
2-wire
1-wire
0
0
0
1
1
0
1
0
0
0
0
0
0
0
0
0
0
1
Bypass/ Real
Decimation
1/2-wire
2-wire
Output
Interface
Complex
Decimation
1-wire
1/2-wire
4
5
0x1B
Select the output interface resolution using the bit mapper (D5-D3).
Select the FCLK pattern for decimation for proper duty cycle output of the frame clock.
Output Resolution
14-bit
2-wire
1-wire
1/2-wire
0xFE000
0xFF000
0xFF800
0xFFC00
16-bit
Real Decimation
use default
0x20
0x21
0x22
18-bit
20-bit
use default
14-bit
16-bit
Complex
Decimation
0xFFFFF
0xFFFFF
18-bit
20-bit
6
7
0x24
0x25
Enable the decimation filter
Configure the decimation filter
0x2A/B/C/D
0x31/2/3/4
8
Program the NCO frequency for complex decimation (can be skipped for real decimation)
Configure the complex output data stream (set both bits to 0 for real decimation)
Decimation
Filter
SLVDS
2-wire
OP-Order (D4)
Q-Delay (D3)
0x27
0x2E
9
1
0
1
0
1
1
1-wire
1/2-wire
10
0x26
Set the mixer gain and toggle the mixer reset bit to update the NCO frequency.
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8.3.5.2.1 Configuration Example
The following is a step by step programming example to configure the ADC368x to complex decimation by 8 with
1-wire SLVDS and 16-bit output.
1. 0x07 (address) 0x6C (load bit mapper configuration for 16-bit output with 1-wire SLVDS)
2. 0x13 0x01, wait 1 ms, 0x13 0x00 (load e-fuse)
3. 0x19 0x80 (configure FCLK)
4. 0x1B 0x88 (select 16-bit output resolution)
5. 0x20 0xFF, 0x21 0xFF, 0x22 0x0F (configure FCLK pattern)
6. 0x24 0x06 (enable decimation filter)
7. 0x25 0x30 (configure complex decimation by 8)
8. 0x2A/B/C/D and 0x31/32/33/34 (program NCO frequency)
9. 0x27/0x2E 0x08 (configure Q-delay register bit)
10.0x26 0xAA, 0x26 0x88 (set digital mixer gain to 6-dB and toggle the mixer update)
8.3.5.3 Output Data Format
The output data can be configured to two's complement (default) or offset binary formatting using SPI register
writes (register 0x8F and 0x92). Table 8-8 provides an overview for minimum and maximum output codes for the
two formatting options. The actual output resolution is set by the output bit mapper.
Table 8-8. Overview of minimum and maximum output codes vs output resolution for different formatting
Two's Complement (default)
Offset Binary
RESOLUTION (BIT)
14
16
18
20
14
16
18
20
VIN,MAX
0
0x1FFF
0x7FFF
0x1FFFF
0x7FFFF
0x3FFF
0x2000
0xFFFF
0x8000
0x3FFFF
0x20000
0xFFFFF
0x80000
0x0000
0x00000
VIN,MIN
0x2000
0x8000
0x20000
0x80000
0x0000
0x00000
8.3.6 Test Pattern
In order to enable in-circuit testing of the digital interface, the following test patterns are supported and enabled
via SPI register writes (0x14/0x15/0x16). In decimation mode (real and complex), the test patterns replace the
output data of the DDC - however channel A controls the test patterns for both channels.
•
RAMP Pattern: The step size needs to be configured in the CUSTOM PAT register according to the native
resolution of the ADC. When selecting a higher output resolution then the additional LSBs will still be 0 in
RAMP pattern mode.
– 00001: 18-bit output resolution
– 00100: 16-bit output resolution
– 10000: 14-bit output resolution
•
Custom Pattern: Configured in the CUSTOM PAT register
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8.4 Device Functional Modes
8.4.1 Normal Operation
In normal operating mode, the entire ADC full-scale range gets converted to a digital output with 18-bit
resolution.
8.4.2 Power Down Options
A global power down mode can be enabled via SPI as well as using the power down pin (PDN/SYNC). There is
an internal pull-down 21 kΩ resistor on the PDN/SYNC input pin and the pin is active high - so the pin needs to
be pulled high externally to enter global power down mode.
The SPI register map provides the capability to enable/disable individual blocks directly or via PDN pin mask in
order to trade off power consumption vs wake up time as shown in Table 8-9.
REFBUF
1.2V REF
Digital Downconverter
NCO
VREF
AIN
Crosspoint
Switch
N
ADC
NCO
Dig I/F
N
BIN
CLK
ADC
Figure 8-39. Power Down Configurations
Table 8-9. Overview of Power Down Options
PDN
via SPI
Mask for
Global PDN
Feature -
Default
Power
Impact
Wake-up
time
Function/ Register
ADC
Comment
Both ADC channels are included in
Global PDN automatically
Yes
-
Enabled
Enabled
Should only be powered down in power
down state.
Reference gain amplifier
Internal 1.2V reference
Yes
Yes
~ 0.4 mA
~3 us
Internal/external reference selection is
available through SPI and REFBUF pin.
External ref
~ 1-3.5 mA
~3 ms
Yes
Single ended clock input saves ~ 1mA
compared to differential.
Some programmability is available
through the REFBUF pin.
Differential
clock
Clock buffer
Yes
~ 1 mA
varies
n/a
Depending on output interface mode,
unused output drivers can be powered
down for maximum power savings
Output interface drivers
Decimation filter
Yes
Yes
-
-
Enabled
Disabled
n/a
n/a
see electrical
table
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8.4.3 Digital Channel Averaging
The ADC368x includes a digital channel averaging feature which enables improvement of the ADC dynamic
range (see Figure 8-40). The same input signal is given to both ADC inputs externally and the output of the two
ADCs is averaged internally. By averaging, uncorrelated noise (e.g. ADC thermal noise) improves 3-dB while
correlated noise (e.g. jitter in the clock path, reference noise) is unaffected. Therefore the averaging gives close
to 3-dB improvement at low input frequencies but less at high input frequencies where clock jitter dominates the
SNR.
The output from the digital averaging block is given out on the digital outputs of channel A or alternatively can be
routed to the digital decimation filters using the digital mux.
NCO
MUX
N
ADC
AVG
NCO
N
ADC
External
Internal
Figure 8-40. Digital Channel Averaging Diagram
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8.5 Programming
The device is primarily configured and controlled using the serial programming interface (SPI) however it can
operate in a default configuration without requiring the SPI interface. Furthermore the power down function as
well as internal/external reference configuration is possible via pin control (PDN/SYNC and REFBUF pin).
Note
The power down command (via PIN or SPI) only goes in effect with the ADC sampling clock present.
8.5.1 Configuration using PINs only
The ADC voltage reference can be selected using the REFBUF pin. Even though there is an internal 100 kΩ
pull-up resistor to AVDD, the REFBUF pin should be set to a voltage externally and not left floating. When using
a voltage divider to set the REFBUF voltage (R1 and R2 in Figure 8-41), resistor values < 5 kΩ should be used.
AVDD
R1
AVDD
100 k
REFBUF
R2
Figure 8-41. Configuration of external voltage on REFBUF pin
Table 8-10. REFBUF voltage levels control voltage reference selection
REFBUF VOLTAGE
VOLTAGE REFERENCE OPTION
CLOCKING OPTION
> 1.7 V (Default)
1.2 V (1.15-1.25V)
0.5 - 0.7V
External reference
Differential clock input
Differential clock input
Differential clock input
Single ended clock input
External 1.2V input on REFBUF pin using internal gain buffer
Internal reference
< 0.1V
Internal reference
Table 8-11. REFBUF voltage levels control voltage reference selection
REFBUF VOLTAGE
VOLTAGE REFERENCE OPTION
CLOCKING OPTION
> 1.7 V (Default)
1.2 V (1.15-1.25V)
0.5 - 0.7V
External reference
Differential clock input
Differential clock input
Differential clock input
Single ended clock input
External 1.2V input on REFBUF pin using internal gain buffer
Internal reference
< 0.1V
Internal reference
8.5.2 Configuration using the SPI interface
The device has a set of internal registers that can be accessed by the serial interface formed by the SEN (serial
interface enable), SCLK (serial interface clock) and SDIO (serial interface data input/output) pins. Serially shifting
bits into the device is enabled when SEN is low. Serial data input are latched at every SCLK rising edge when
SEN is active (low). The serial data are loaded into the register at every 24th SCLK rising edge when SEN is low.
When the word length exceeds a multiple of 24 bits, the excess bits are ignored. Data can be loaded in multiples
of 24-bit words within a single active SEN pulse. The interface can function with SCLK frequencies from 12 MHz
down to very low speeds (of a few hertz) and also with a non-50% SCLK duty cycle.
8.5.2.1 Register Write
The internal registers can be programmed following these steps:
1. Drive the SEN pin low
2. Set the R/W bit to 0 (bit A15 of the 16-bit address) and bits A[14:12] in address field to 0.
3. Initiate a serial interface cycle by specifying the address of the register (A[11:0]) whose content is written and
4. Write the 8-bit data that are latched in on the SCLK rising edges
Figure 8-42 shows the timing requirements for the serial register write operation.
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Register Address <11:0>
A7 A6 A5 A4
Register Data <7:0>
R/W
0
SDIO
0
0
0
A11 A10
A9
A8
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
tH,SDIO
tSCLK
tS,SDIO
SCLK
SEN
tS,SEN
tH,SEN
RESET
Figure 8-42. Serial Register Write Timing Diagram
8.5.2.2 Register Read
The device includes a mode where the contents of the internal registers can be read back using the SDIO pin.
This readback mode can be useful as a diagnostic check to verify the serial interface communication between
the external controller and the ADC. The procedure to read the contents of the serial registers is as follows:
1. Drive the SEN pin low
2. Set the R/W bit (A15) to 1. This setting disables any further writes to the registers. Set A[14:12] in address
field to 0.
3. Initiate a serial interface cycle specifying the address of the register (A[11:0]) whose content must be read
4. The device launches the contents (D[7:0]) of the selected register on the SDIO pin on SCLK falling edge
5. The external controller can capture the contents on the SCLK rising edge
Register Address <11:0>
Register Data <7:0>
R/W
1
tOZD
A0
tOD
SDIO
0
0
0
A11 A10
A9
A8
A7 A6 A5 A4
A3
A2
A1
D7
D6
D5 D4 D3
D2
D1
D0
SCLK
SEN
tODZ
Figure 8-43. Serial Register Read Timing Diagram
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8.6 Register Map
Table 8-12. Register Map Summary
REGISTER
ADDRESS
REGISTER DATA
A[11:0]
0x00
D7
D6
D5
D4
D3
D2
D1
0
D0
0
0
0
0
0
0
0
RESET
0x07
OP IF MAPPER
0
OP IF EN
0
OP IF SEL
PDN
PDN
GLOBAL
0x08
0x09
0x0D
0x0E
0
0
0
PDN CLKBUF
PDN A
PDN B
REFAMP
PDN
FCLKOUT
PDN
0
0
PDN DA1
PDN DA0
PDN DB1
PDN DB0
0
DCLKOUT
MASK
MASK
REFAMP
MASK BG
DIS
0
0
0
CLKBUF
SYNC PIN
EN
SPI SYNC SPI SYNC EN
REF CTRL
REF SEL
SE CLK EN
0x11
0x13
0x14
0x15
0x16
0x19
0
0
0
0
0
0
0
0
0
0
DLL PDN
0
0
0
AZ EN
E-FUSE LD
CUSTOM PAT [7:0]
CUSTOM PAT [15:8]
TEST PAT A
TEST PAT B
0
CUSTOM PAT [17:16]
FCLK SRC
0
0
0
FCLK DIV
0
0
0
0
0
0
0
0
0
TOG FCLK
LVDS ½
SWING
0x1A
0
0
0x1B
0x1E
0x20
0x21
0x22
0x24
0x25
0x26
MAPPER EN
0
20B EN
0
BIT MAPPER RES
0
0
LVDS DATA DEL
LVDS DCLK DEL
FCLK PAT [7:0]
FCLK PAT [15:8]
0
0
0
0
0
FCLK PAT [19:16]
0
CH AVG EN
DECIMATION
MIX RES A
DDC MUX
DIG BYP
0
DDC EN
0
0
DDC MUX EN
REAL OUT
MIX PHASE
FS/4 MIX B
MIX GAIN A
FS/4 MIX A
MIX GAIN B
MIX RES B
FS/4 MIX PH
A
0x27
0
0
0
0
0
OP ORDER A
Q-DEL A
0
0
0x2A
0x2B
0x2C
0x2D
NCO A [7:0]
NCO A [15:8]
NCO A [23:16]
NCO A [31:24]
FS/4 MIX PH
B
0x2E
0
OP ORDER B
Q-DEL B
0
0
0x31
0x32
0x33
0x34
0x8F
0x92
NCO B [7:0]
NCO B [15:8]
NCO B [23:16]
NCO B [31:24]
0
0
0
0
0
0
0
0
0
0
0
FORMAT A
FORMAT B
0
0
0
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8.6.1 Detailed Register Description
Figure 8-44. Register 0x00
7
0
6
0
5
0
4
3
2
0
1
0
0
0
0
RESET
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
Table 8-13. Register 0x00 Field Descriptions
Bit
Field
0
Type
R/W
R/W
Reset
Description
7-1
0
0
0
Must write 0
RESET
This bit resets all internal registers to the default values and self
clears to 0.
Figure 8-45. Register 0x07
7
6
5
4
3
2
1
0
OP IF MAPPER
R/W-0
0
OP IF EN
R/W-0
OP IF SEL
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
Table 8-14. Register 0x07 Field Descriptions
Bit
Field
Type
Reset
Description
7-5
OP IF MAPPER
R/W
000
Output interface mapper. This register contains the proper
output interface bit mapping for the different interfaces. The
interface bit mapping is internally loaded from e-fuses and also
requires a fuse load command to go into effect (0x13, D0).
Register 0x07 along with the E-Fuse Load (0x13, D0) needs to
be loaded first in the programming sequence since the E-Fuse
load resets the SPI writes.
After initial reset the default output interface variant is loaded
automatically from fuse internally. However when reading back
this register reads 000 until a value is written using SPI.
001: 2-wire, 18 and 14-bit
010: 2-wire, 16-bit
011: 1-wire
100: 0.5-wire
others: not used
4
3
0
R/W
R/W
R/W
0
Must write 0
OP IF EN
OP IF SEL
0
Enables changing the default output interface mode (D2-D0).
2-0
000
Selection of the output interface mode. OP IF EN (D3) needs to
be enabled also.
After initial reset the default output interface is loaded
automatically from fuse internally. However when reading back
this register reads 000 until a value is written using SPI.
011: 2-wire
100: 1-wire
101: 0.5-wire
others: not used
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Figure 8-46. Register 0x08
7
0
6
5
4
3
2
1
0
0
PDN CLKBUF PDN REFAMP
R/W-0 R/W-0
0
PDN A
R/W-0
PDN B
R/W-0
PDN GLOBAL
R/W-0
R/W-0
R/W-0
R/W-0
Table 8-15. Register 0x08 Field Descriptions
Bit
Field
Type
R/W
R/W
Reset
Description
7-6
5
0
0
0
Must write 0
PDN CLKBUF
Powers down sampling clock buffer
0: Clock buffer enabled
1: Clock buffer powered down
4
PDN REFAMP
R/W
0
Powers down internal reference gain amplifier
0: REFAMP enabled
1: REFAMP powered down
3
2
0
R/W
R/W
0
0
Must write 0
PDN B
Powers down ADC channel A
0: ADC channel A enabled
1: ADC channel A powered down
1
0
PDN A
R/W
R/W
0
0
Powers down ADC channel B
0: ADC channel B enabled
1: ADC channel B powered down
PDN GLOBAL
Global power down via SPI
0: Global power disabled
1: Global power down enabled. Power down mask (register
0x0D) determines which internal blocks are powered down.
Figure 8-47. Register 0x09
7
0
6
0
5
4
3
2
1
0
PDN FCLKOUT PDN DCLKOUT
R/W-0 R/W-0
PDN DA1
R/W-0
PDN DA0
R/W-0
PDN DB1
R/W-0
PDN DB0
R/W-0
R/W-0
R/W-0
Table 8-16. Register 0x09 Field Descriptions
Bit
Field
Type
R/W
R/W
Reset
Description
7-6
5
0
0
0
Must write 0
PDN FCLKOUT
Powers down frame clock (FCLK) LVDS output buffer
0: FCLK output buffer enabled
1: FCLK output buffer powered down
4
3
PDN DCLKOUT
PDN DA1
R/W
R/W
0
0
Powers down DCLK LVDS output buffer
0: DCLK output buffer enabled
1: DCLK output buffer powered down
Powers down LVDS output buffer for channel A, lane 1.
NOT powered down automatically in 1-wire and 1/2-wire mode.
0: DA1 LVDS output buffer enabled
1: DA1 LVDS output buffer powered down
2
1
PDN DA0
PDN DB1
R/W
R/W
0
0
Powers down LVDS output buffer for channel A, lane 0.
0: DA0 LVDS output buffer enabled
1: DA0 LVDS output buffer powered down
Powers down LVDS output buffer for channel B, lane 1. NOT
powered down automatically in 1-wire and 1/2-wire mode.
0: DB1 LVDS output buffer enabled
1: DB1 LVDS output buffer powered down
0
PDN DB0
R/W
0
Powers down LVDS output buffer for channel B, lane 0.
NOT powered down automatically in 1/2-wire mode.
0: DB0 LVDS output buffer enabled
1: DB0 LVDS output buffer powered down
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Figure 8-48. Register 0x0D (PDN GLOBAL MASK)
7
0
6
0
5
4
3
2
1
0
0
0
0
MASK CLKBUF MASK REFAMP MASK BG DIS
R/W-0 R/W-0 R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
Table 8-17. Register 0x0D Field Descriptions
Bit
7-4
3
Field
Type
R/W
R/W
Reset
Description
0
0
0
Must write 0
MASK CLKBUF
MASK REFAMP
MASK BG DIS
Global power down mask control for sampling clock input buffer.
0: Clock buffer will get powered down when global power down
is exercised.
1: Clock buffer will NOT get powered down when global power
down is exercised.
2
1
R/W
R/W
0
0
Global power down mask control for reference amplifier.
0: Reference amplifier will get powered down when global power
down is exercised.
1: Reference amplifier will NOT get powered down when global
power down is exercised.
Global power down mask control for internal 1.2V bandgap
voltage reference. Setting this bit reduces power consumption in
global power down mode but increases the wake up time. See
the power down option overview.
0: Internal 1.2V bandgap voltage reference will NOT get
powered down when global power down is exercised.
1: Internal 1.2V bandgap voltage reference will get powered
down when global power down is exercised.
0
0
R/W
0
Must write 0
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Figure 8-49. Register 0x0E
7
6
5
4
3
2
1
0
SYNC PIN EN
R/W-0
SPI SYNC
R/W-0
SPI SYNC EN
R/W-0
0
REF CTL
R/W-0
REF SEL
SE CLK EN
R/W-0
R/W-0
R/W-0
R/W-0
Table 8-18. Register 0x0E Field Descriptions
Bit
Field
SYNC PIN EN
Type
Reset
Description
7
R/W
0
This bit controls the functionality of the SYNC/PDN pin.
0: SYNC/PDN pin exercises global power down mode when pin
is pulled high.
1: SYNC/PDN pin issues the SYNC command when pin is
pulled high.
6
5
SPI SYNC
R/W
R/W
0
0
Toggling this bit issues the SYNC command using the SPI
register write. SYNC using SPI must be enabled as well (D5).
This bit doesn't self reset to 0.
0: Normal operation
1: SYNC command issued.
SPI SYNC EN
This bit enables synchronization using SPI instead of the
SYNC/PDN pin.
0: Synchronization using SPI register bit disabled.
1: Synchronization using SPI register bit enabled.
4
3
0
R/W
R/W
0
0
Must write 0
REF CTL
This bit determines if the REFBUF pin controls the voltage
reference selection or the SPI register (D2-D1).
0: The REFBUF pin selects the voltage reference option.
1: Voltage reference is selected using SPI (D2-D1) and single
ended clock using D0.
2-1
REF SEL
R/W
R/W
00
Selects of the voltage reference option. REF CTRL (D3) must be
set to 1.
00: Internal reference
01: External voltage reference (1.2V) using internal reference
buffer (REFBUF)
10: External voltage reference
11: not used
0
SE CLK EN
0
Selects single ended clock input and powers down the
differential sampling clock input buffer. REF CRTL (D3) must be
set to 1.
0: Differential clock input
1: Single ended clock input
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Figure 8-50. Register 0x11
7
0
6
0
5
0
4
3
2
1
0
0
0
DLL PDN
R/W-0
0
AZ EN
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
Table 8-19. Register 0x11 Field Descriptions
Bit
7-3
2
Field
0
Type
R/W
R/W
Reset
Description
0
0
Must write 0
DLL PDN
This register applies ONLY to the ADC3683. It powers down the
internal DLL, which is used to adjust the sampling time. This
register must only be enabled when operating at sampling rates
below 40 MSPS. When DLL PDN bit is enabled the sampling
time is directly dependent on sampling clock duty cycle (with a
50/50 duty the sampling time is TS/2).
0: Sampling time is TS/ 4
1: Sampling time is TS/2 (only for sampling rates below 40
MSPS).
1
0
0
R/W
R/W
0
Must write 0
AZ EN
0/1
This bit enables the internal auto-zero circuitry. It is enabled by
default for the ADC3681/82 and disabled for the ADC3683.
0: Auto-zero disabled
1: Auto-zero enabled
Figure 8-51. Register 0x13
7
0
6
0
5
0
4
3
2
0
1
0
0
0
E-FUSE LD
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
Table 8-20. Register 0x13 Field Descriptions
Bit
7-1
0
Field
Type
R/W
R/W
Reset
Description
0
0
0
Must write 0
E-FUSE LD
This register bit loads the internal bit mapping for different
interfaces. After setting the interface in register 0x07, this E-
FUSE LD bit needs to be set to 1 and reset to 0 for loading to go
into effect. Register 0x07 along with the E-Fuse Load (0x12, D0)
needs to be loaded first in the programming sequence since the
E-Fuse load resets the SPI writes.
0: E-FUSE LOAD set
1: E-FUSE LOAD reset
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Figure 8-52. Register 0x14/15/16
7
6
5
4
3
2
1
0
CUSTOM PAT [7:0]
CUSTOM PAT [15:8]
TEST PAT B
R/W-0
TEST PAT A
R/W-0
CUSTOM PAT [17:16]
R/W-0 R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
Table 8-21. Register 0x14/15/16 Field Descriptions
Bit
Field
CUSTOM PAT [17:0]
Type
Reset
Description
7-0
R/W
00000000 This register is used for two purposes:
•
•
It sets the constant custom pattern starting from MSB
It sets the RAMP pattern increment step size.
00001: Ramp pattern for 18-bit ADC
00100: Ramp pattern for 16-bit ADC
10000: Ramp pattern for 14-bit ADC
7-5
TEST PAT B
R/W
000
Enables test pattern output mode for channel B (NOTE: The test
pattern is set prior to the bit mapper and is based on native
resolution of the ADC starting from the MSB). These work in
either output format.
000: Normal output mode (test pattern output disabled)
010: Ramp pattern: need to set proper increment using
CUSTOM PAT register
011: Constant Pattern using CUSTOM PAT [17:0] in register
0x14/15/16.
others: not used
4-2
TEST PAT A
R/W
000
Enables test pattern output mode for channel A (NOTE: The test
pattern is set prior to the bit mapper and is based on native
resolution of the ADC starting from the MSB). These work in
either output format.
000: Normal output mode (test pattern output disabled)
010: Ramp pattern: need to set proper increment using
CUSTOM PAT register
011: Constant Pattern using CUSTOM PAT [17:0] in register
0x14/15/16.
others: not used
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Figure 8-53. Register 0x19
7
6
0
5
0
4
3
2
0
1
0
FCLK SRC
R/W-0
FCLK DIV
R/W-0
0
0
TOG FCLK
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
Table 8-22. Register 0x19 Field Descriptions
Bit
Field
FCLK SRC
Type
Reset
Description
7
R/W
0
User has to select if FCLK signal comes from ADC or from DDC
block. Here real decimation is treated same as bypass mode
0: FCLK generated from ADC. FCLK SRC set to 0 for DDC
bypass, real decimation mode and 1/2-w complex decimation
mode.
1: FCLK generated from DDC block. In complex decimation
mode only this bit needs to be set for 2-w and 1-w output
interface mode but NOT for 1/2-w mode.
6-5
4
0
R/W
R/W
0
0
Must write 0
FCLK DIV
This bit needs to be set to 1 for 2-w output mode in bypass/real
decimation mode only .
0: All output interface modes except 2-w decimation bypass and
real decimation mode.
1: 2-w output interface mode for decimation bypass and real
decimation.
3-1
0
0
R/W
R/W
0
0
Must write 0
TOG FCLK
This bit adjusts the FCLK signal appropriately for 1/2-wire mode
where FCLK is stretched to cover channel A and channel B.
This bit ONLY needs to be set in 1/2-wire mode with complex
decimation mode.
0: all other modes.
1: FCLK for 1/2-wire complex decimation mode.
Table 8-23. Configuration of FCLK SRC and FCLK DIV Register Bits vs Serial Interface
BYPASS/DECIMATION
SERIAL INTERFACE
FCLK SRC
FCLK DIV
TOG FCLK
2-wire
0
0
0
1
1
0
1
0
0
0
0
0
0
0
0
0
0
1
Decimation Bypass/ Real Decimation
Complex Decimation
1-wire
1/2-wire
2-wire
1-wire
1/2-wire
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Figure 8-54. Register 0x1A
7
0
6
5
0
4
3
2
0
1
0
0
0
LVDS ½
SWING
0
0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
Table 8-24. Register 0x1A Field Descriptions
Bit
Field
Type
R/W
R/W
Reset
Description
7
6
0
0
0
Must write 0
LVDS ½ SWING
This bit reduces the LVDS output current from 3.5mA to 1.75mA
which reduces power consumption.
5-0
0
R/W
0
Must write 0
Figure 8-55. Register 0x1B
7
6
5
4
3
2
0
1
0
0
0
MAPPER EN
R/W-0
20B EN
R/W-0
BIT MAPPER RES
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
Table 8-25. Register 0x1B Field Descriptions
Bit
Field
MAPPER EN
Type
Reset
Description
7
R/W
0
This bit enables changing the resolution of the output (including
output serialization factor) in bypass mode only. This bit is not
needed for 20-bit resolution output.
0: Output bit mapper disabled.
1: Output bit mapper enabled.
6
20B EN
R/W
R/W
0
This bit enables 20-bit output resolution which can be useful for
very high decimation settings so that quantization noise doesn't
impact the ADC performance.
0: 20-bit output resolution disabled.
1: 20-bit output resolution enabled.
5-3
BIT MAPPER RES
000
Sets the output resolution using the bit mapper. MAPPER EN bit
(D6) needs to be enabled when operating in bypass mode..
000: 18 bit
001: 16 bit
010: 14 bit
all others, n/a
2-0
0
R/W
0
Must write 0
Table 8-26. Register Settings for Output Bit Mapper vs Operating Mode
BYPASS/DECIMATION
Decimation Bypass
Real Decimation
OUTPUT RESOLUTION
MAPPER EN (D7)
BIT MAPPER RES (D5-D3)
Resolution Change
1
0
0
000: 18-bit
001: 16-bit
010: 14-bit
Resolution Change (default 18-bit)
Complex Decimation
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Figure 8-56. Register 0x1E
7
0
6
0
5
0
4
3
2
1
0
0
LVDS DATA DEL
LVDS DCLK DEL
R/W-0 R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
Table 8-27. Register 0x1E Field Descriptions
Bit
7-4
3-2
Field
Type
R/W
R/W
Reset
Description
0
0
Must write 0
LVDS DATA DEL
00
These bits adjust the output timing of the SLVDS output data.
00: no delay
01: Data advanced by 50 ps
10: Data delayed by 50 ps
11: Data delayed by 100 ps
1-0
LVDS DCLK DEL
R/W
00
These bits adjust the output timing of the SLVDS DCLK output.
00: no delay
01: DCLK advanced by 50 ps
10: DCLK delayed by 50 ps
11: DCLK delayed by 100 ps
Figure 8-57. Register 0x20/21/22
7
6
5
4
3
2
1
0
FCLK PAT [7:0]
FCLK PAT [15:8]
0
0
0
0
FCLK PAT [19:16]
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
Table 8-28. Register 0x20/21/22 Field Descriptions
Bit
Field
Type
Reset
Description
7-0
FCLK PAT [19:0]
R/W
0xFFC00
These bits can adjust the duty cycle of the FCLK. In decimation
bypass mode the FCLK pattern gets adjusted automatically for
the different output resolutions. Table 8-29 shows the proper
FCLK pattern values for 1-wire and 1/2-wire in real/complex
decimation.
Table 8-29. FCLK Pattern for different resolution based on interface
DECIMATION
OUTPUT RESOLUTION
2-WIRE
1-WIRE
0xFE000
0xFF000
0xFF800
0xFFC00
1/2-WIRE
14-bit
16-bit
18-bit
20-bit
14-bit
16-bit
18-bit
20-bit
REAL DECIMATION
Use Default
Use Default
COMPLEX
DECIMATION
0xFFFFF
0xFFFFF
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Figure 8-58. Register 0x24
7
0
6
5
4
3
2
1
0
0
0
CH AVG EN
R/W-0
DDC MUX
DIG BYP
R/W-0
DDC EN
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
Table 8-30. Register 0x24 Field Descriptions
Bit
Field
Type
R/W
R/W
Reset
Description
7-6
5
0
0
0
Must write 0
CH AVG EN
Averages the output of ADC channel A and channel B together.
The DDC MUX has to be enabled and set to '11'. The
decimation filter needs to be enabled and set to bypass (fullrate
output) or decimation and DIG BYP set to 1.
0: Channel averaging feature disabled
1: Output of channel A and channel B are averaged: (A+B)/2.
4-3
DDC MUX
R/W
R/W
0
0
Configures DDC MUX in front of the decimation filter.
00: ADC channel A connected to DDC A; ADC Channel B
connected to DDC B
01: ADC channel A connected to DDC A and DDC B.
10: ADC channel B connected to DDC A and DDC B.
11: Output of ADC averaging block (see CH AVG EN) given to
DDC A and DDC B.
2
DIG BYP
This bit needs to be set to enable digital features block which
includes decimation.
0: Digital feature block bypassed - lowest latency
1: Data path includes digital features
1
0
DDC EN
0
R/W
R/W
0
0
Enables internal decimation filter for both channels
0: DDC disabled.
1: DDC enabled.
Must write 0
To output
interface
DDC
N
N
CH
Average
DECIMATION
DIG BYP
DDC
DDC MUX
To output
interface
Figure 8-59. Register control for digital features
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Figure 8-60. Register 0x25
7
6
5
4
3
2
0
1
0
DDC MUX EN
R/W-0
DECIMATION
R/W-0
REAL OUT
R/W-0
0
MIX PHASE
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
Table 8-31. Register 0x25 Field Descriptions
Bit
Field
DDC MUX EN
Type
Reset
Description
7
R/W
0
Enables the digital mux between ADCs and decimation filters.
This bit is required for DDC mux settings in register 0x24 (D4,
D3) to go into effect.
0: DDC mux disabled
1: DDC mux enabled
6-4
DECIMATION
REAL OUT
R/W
R/W
000
Complex decimation setting. This applies to both channels.
000: Bypass mode (no decimation) 100: Decimation by 16
001: Decimation by 2
010: Decimation by 4
011: Decimation by 8
101: Decimation by 32
others: not used
3
0
This bit selects real output decimation. This mode applies to
both channels. In this mode, the decimation filter is a low pass
filter and no complex mixing is performed to reduce power
consumption. For maximum power savings the NCO in this case
should be set to 0.
0: Complex decimation
Must write 0
1: Real decimation
2-1
0
0
R/W
R/W
0
0
MIX PHASE
This bit used to invert the NCO phase
0: NCO phase as is.
1: NCO phase inverted.
Figure 8-61. Register 0x26
7
6
5
4
3
2
1
0
MIX GAIN A
MIX RES A
R/W-0
FS/4 MIX A
R/W-0
MIX GAIN B
MIX RES B
R/W-0
FS/4 MIX B
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
Table 8-32. Register 0x26 Field Descriptions
Bit
Field
Type
Reset
Description
7-6
MIX GAIN A
R/W
00
This bit applies a 0, 3 or 6-dB digital gain to the output of digital
mixer to compensate for the mixing loss for channel A.
00: no digital gain added
01: 3-dB digital gain added (should be enabled with real
decimation)
10: 6-dB digital gain added (should be enabled with complex
decimation)
11: not used
5
4
MIX RES A
FS/4 MIX A
R/W
R/W
0
0
Toggling this bit resets the NCO phase of channel A and loads
the new NCO frequency. This bit does not self reset.
Enables FS/4 mixing for DDC A (complex decimation only).
0: FS/4 mixing disabled.
1: FS/4 mixing enabled.
3-2
MIX GAIN B
R/W
00
This bit applies a 0, 3 or 6-dB digital gain to the output of digital
mixer to compensate for the mixing loss for channel B.
00: no digital gain added
01: 3-dB digital gain added (should be enabled with real
decimation)
10: 6-dB digital gain added (should be enabled with complex
decimation)
11: not used
1
MIX RES B
R/W
0
Toggling this bit resets the NCO phase of channel B and loads
the new NCO frequency. This bit does not self reset.
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Table 8-32. Register 0x26 Field Descriptions (continued)
Bit
Field
Type
Reset
Description
Enables FS/4 mixing for DDC B (complex decimation only).
0: FS/4 mixing disabled. 1: FS/4 mixing enabled.
0
FS/4 MIX B
R/W
0
Figure 8-62. Register 0x27
7
0
6
0
5
0
4
3
2
1
0
0
OP ORDER A
R/W-0
Q-DEL A
R/W-0
FS/4 MIX PH A
R/W-0
0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
Table 8-33. Register 0x27 Field Descriptions
Bit
Field
Type
R/W
R/W
Reset
Description
7-5
4
0
0
0
Must write 0
OP ORDER A
Swaps the I and Q output order for channel A. See Table 8-34
for recommended settings. Only used with complex decimation.
Set to 0 with real decimation.
0: Output order is I[n], Q[n]
1: Output order is swapped: Q[n], I[n]
3
Q-DEL A
R/W
0
This delays the Q-sample output of channel A by one. See Table
8-34 for recommended settings. Only used with complex
decimation. Set to 0 with real decimation.
0: Output order is I[n], Q[n]
1: Q-sample is delayed by 1 sample: I[n], Q[n+1], I[n+1], Q[n+2]
2
FS/4 MIX PH A
0
R/W
R/W
0
0
Inverts the mixer phase for channel A when using FS/4 mixer.
0: Mixer phase is non-inverted
1: Mixer phase is inverted
1-0
Must write 0
Table 8-34. OP-ORDER and Q-DELAY Register Settings for Complex Decimation
SLVDS INTERFACE
OP-ORDER
Q-DELAY
2-wire
1
0
1
0
1
1
1-wire
1/2-wire
Figure 8-63. Register 0x2A/B/C/D
7
6
5
4
3
2
1
0
NCO A [7:0]
NCO A [15:8]
NCO A [23:16]
NCO A [31:24]
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
Table 8-35. Register 0x2A/2B/2C/2D Field Descriptions
Bit
7-0
Field
Type
Reset
Description
NCO A [31:0]
R/W
0
Sets the 32 bit NCO value for decimation filter channel A. The
NCO value is fNCO× 232 / FS.
In real decimation mode these registers are automatically set to
0.
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Figure 8-64. Register 0x2E/2F/30
7
0
6
0
5
0
4
3
2
1
0
0
OP ORDER B
R/W-0
Q-DEL B
R/W-0
FS/4 MIX PH B
R/W-0
0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
Table 8-36. Register 0x2E/2F/30 Field Descriptions
Bit
7-5
4
Field
Type
R/W
R/W
Reset
Description
0
0
0
Must write 0
OP ORDER B
Swaps the I and Q output order for channel B. See Table 8-34
for recommended settings. Only used with complex decimation.
Set to 0 with real decimation.
0: Output order is I[n], Q[n]
1: Output order is swapped: Q[n], I[n]
3
Q-DEL B
R/W
0
This delays the Q-sample output of channel B by one. See Table
8-34 for recommended settings. Only used with complex
decimation. Set to 0 with real decimation.
0: Output order is I[n], Q[n]
1: Q-sample is delayed by 1 sample: I[n], Q[n+1], I[n+1], Q[n+2]
2
FS/4 MIX PH B
0
R/W
R/W
0
0
Inverts the mixer phase for channel B when using FS/4 mixer.
0: Mixer phase is non-inverted
1: Mixer phase is inverted
1-0
Must write 0
Figure 8-65. Register 0x31/32/33/34
7
6
5
4
3
2
1
0
NCO B [7:0]
NCO B [15:8]
NCO B [23:16]
NCO B [31:24]
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
Table 8-37. Register 0x31/32/33/34 Field Descriptions
Bit
Field
Type
Reset
Description
7-0
NCO B [31:0]
R/W
0
Sets the 32 bit NCO value for decimation filter channel B. The
NCO value is fNCO× 232 / FS.
In real decimation mode these registers are automatically set to
0.
Figure 8-66. Register 0x8F
7
0
6
0
5
0
4
3
2
0
1
0
0
0
0
FORMAT A
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
Table 8-38. Register 0x8F Field Descriptions
Bit
7-2
1
Field
Type
R/W
R/W
Reset
Description
0
0
0
Must write 0
FORMAT A
This bit sets the output data format for channel A.
0: 2s complement
1: Offset binary
0
0
R/W
0
Must write 0
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Figure 8-67. Register 0x92
7
0
6
5
0
4
3
2
0
1
0
0
0
0
0
FORMAT B
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
Table 8-39. Register 0x92 Field Descriptions
Bit
Field
Type
R/W
R/W
Reset
Description
7-2
1
0
0
0
Must write 0
FORMAT B
This bit sets the output data format for channel B.
0: 2s complement
1: Offset binary
0
0
R/W
0
Must write 0
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9 Application Information Disclaimer
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Typical Application
A spectrum analyzer is a typical frequency domain application for the ADC368x and its front end circuitry is very
similar to several other systems such as software defined radio (SDR), sonar, radar or communications. Some
applications require frequency coverage including DC or near DC (e.g. sonar) so it’s included in this example.
0.6V
10 uF
VREF
10 kꢀ
REFBUF
1.2V REF
Glitch Filter
33 ꢀ
Low Pass Filter
100 pF
10 ꢀ
10 ꢀ
NCO
180nH
AMP
AIN
ADC
N
33 ꢀ
DCLKIN
180nH
VCM
DCLK
FCLK
0.95V
FPGA
Dig I/F
33 ꢀ
CVCM
DA0/1
DB0/1
Low Pass Filter
NCO
100 pF
10 ꢀ
10 ꢀ
180nH
N
AMP
BIN
CLK
ADC
33 ꢀ
180nH
Glitch Filter
Device Clock
Control
Figure 9-1. Typical configuration for a spectrum analyzer with DC support
9.1.1 Design Requirements
Frequency domain applications cover a wide range of frequencies from low input frequencies at or near DC in
the 1st Nyquist zone to undersampling in higher Nyquist zones. If very low input frequency is supported then the
input has to be DC coupled and the ADC driven by a fully differential amplifier (FDA). If low frequency support is
not needed then AC coupling and use of a balun may be more suitable.
The internal reference is used since DC precision is not needed. However the ADC AC performance is highly
dependent on the quality of the external clock source. If in-band interferers can be present then the ADC SFDR
performance will be a key care about as well. A higher ADC sampling rate is desirable in order to relax the
external anti-aliasing filter – an internal decimation filter can be used to reduce the digital output rate afterwards.
Table 9-1. Design key care-abouts
FEATURE
DESCRIPTION
Signal Bandwidth
Input Driver
DC to 20 MHz
Single ended to differential signal conversion and DC coupling
External clock with low jitter
Clock Source
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When designing the amplifier/filter driving circuit, the ADC input full-scale voltage needs to be taken into
consideration. For example, the ADC368x input full-scale is 3.2 Vpp. When factoring in ~ 1 dB for insertion loss
of the filter, then the amplifier needs to deliver close to 3.6 Vpp. The amplifier distortion performance will degrade
with a larger output swing and considering the ADC common mode input voltage the amplifier may not be able to
deliver the full swing. The ADC368x provides an output common mode voltage of 0.95V and the THS4541 for
example can only swing within 250 mV of its negative supply. A unipolar 3.3 V amplifier power supply will thus
limit the maximum voltage swing to ~ 2.8 Vpp. Hence if a larger output swing is required (factoring in filter
insertion loss) then a negative supply for the amplifier is needed in order to eliminate that limitation. Additionally
input voltage protection diodes may be needed to protect the ADC from over-voltage events.
Table 9-2. Output voltage swing of THS4541 vs power supply
DEVICE
MIN OUTPUT VOLTAGE
MAX SWING WITH 3.3 V/ 0 V SUPPLY
MAX SWING WITH 3.3 V/ -1.0 V SUPPLY
THS4541
VS- + 250 mV
2.8 Vpp
6.8 Vpp
9.1.2 Detailed Design Procedure
9.1.2.1 Input Signal Path
Depending on desired input signal frequency range the THS4551 and THS4541 provide very good low power
options to drive the ADC inputs. Table 9-3 provides a comparison between the THS4551 and THS4541 and the
power consumption vs usable frequency trade off.
Table 9-3. Fully Differential Amplifier Options
DEVICE
THS4561
THS4551
THS4541
CURRENT (IQ) PER CHANNEL
USABLE FREQUENCY RANGE
0.8 mA
1.4 mA
10 mA
< 3 MHz
< 10 MHz
< 70 MHz
The low pass filter design (topology, filter order) is driven by the application itself. However, when designing the
low pass filter, the optimum load impedance for the amplifier should be taken into consideration as well. Between
the low pass filter and the ADC input the sampling glitch filter needs to added as well as shown in Section
8.3.1.2.1. In this example the DC - 30 MHz glitch filter is selected.
9.1.2.2 Sampling Clock
Applications operating with low input frequencies (such as DC to 20 MHz) typically are less sensitive to
performance degradation due to clock jitter. The internal ADC aperture jitter improves with faster rise and fall
times (i.e. square wave vs sine wave). Table 9-4 provides an overview of the estimated SNR performance of the
ADC368x based on different amounts of jitter of the external clock source. The SNR is estimated based on
ADC368x thermal noise of 84.2dBFS and input signal at -1dBFS.
Table 9-4. ADC SNR performance across vs input frequency for different amounts of external clock jitter
INPUT FREQUENCY
TJ,EXT = 100 fs
TJ,EXT = 250 fs
TJ,EXT = 500 fs
TJ,EXT = 1 ps
5 MHz
84.2
84.0
83.6
84.1
83.9
83.0
83.9
83.3
81.3
83.4
10 MHz
81.5
20 MHz
77.8
Termination of the clock input should be considered for long clock traces.
9.1.2.3 Voltage Reference
The ADC368x is configured to internal reference operation by applying 0.6 V to the REFBUF pin.
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9.1.3 Application Curves
The following FFT plots show the performance of THS4541 driving the ADC3683 operated at 65 MSPS with a
full-scale input at -1 dBFS and input frequencies of 5, 10 and 20 MHz.
SNR = 81.5 dBFS, HD23 = 88 dBc, Non HD23 = 95 dBFS
SNR = 80.9 dBFS, HD23 = 91 dBc, Non HD23 = 83 dBFS
Figure 9-2. Single Tone FFT at FIN = 5 MHz
Figure 9-3. Single Tone FFT at FIN = 10 MHz
SNR = 77.6 dBFS, HD23 = 76 dBc, Non HD23 = 93 dBFS
AIN = -10 dBFS, SNR = 81.3 dBFS, HD23 = 87 dBc,
Non HD23 = 90 dBFS
Figure 9-4. Single Tone FFT at FIN = 20 MHz
Figure 9-5. Single Tone FFT at FIN = 20 MHz
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9.2 Initialization Set Up
After power-up, the internal registers must be initialized to their default values through a hardware reset by
applying a high pulse on the RESET pin, as shown in Figure 9-6.
1. Apply AVDD and IOVDD (no specific sequence required). After AVDD is applied the internal bandgap
reference will power up and settle out in ~ 2ms.
2. Configure REFBUF pin (pull high or low even if configured via SPI later on) and apply the sampling clock.
3. Apply hardware reset. After hardware reset is released, the default registers are loaded from internal fuses
and the internal power up capacitor calibration is initiated. The calibration takes approximately 200000 clock
cycles.
4. Begin programming using SPI interface.
AVDD
IOVDD
t1
REFBUF
Ext VREF
CLK
t3
t2
RESET
SEN
Figure 9-6. Initialization of serial registers after power up
Table 9-5. Power-up timing
MIN
TYP
MAX
UNIT
t1
t2
t4
t5
Power-on delay: delay from power up to logic level of REFBUF pin
Delay from REFBUF pin logic level to RESET rising edge
RESET pulse width
2
100
ms
ns
us
1
Delay from RESET disable to SEN active
~ 200000
clock cycles
9.2.1 Register Initialization During Operation
If required, the serial interface registers can be cleared and reset to default settings during operation either:
•
•
through a hardware reset or
by applying a software reset. When using the serial interface, set the RESET bit (D0 in register address 0x00)
high. This setting initializes the internal registers to the default values and then self-resets the RESET bit low.
In this case, the RESET pin is kept low.
After hardware or software reset the wait time is also ~ 200000 clock cycles before the SPI registers can be
programmed.
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10 Power Supply Recommendations
The ADC368x requires two different power-supplies. The AVDD rail provides power for the internal analog
circuits and the ADC itself while the IOVDD rail powers the digital interface and the internal digital circuits like
decimation filter or output interface mapper. Power sequencing is not required.
The AVDD power supply must be low noise in order to achieve data sheet performance. In applications
operating near DC, the 1/f noise contribution of the power supply needs to be considered as well. The ADC is
designed for very good PSRR which aides with the power supply filter design.
55
50
45
40
35
30
0.05 0.1
1
10
Frequency of Signal on AVDD (MHz)
100
D42_
Figure 10-1. Power supply rejection ratio (PSRR) vs frequency
There are two recommended power-supply architectures:
1. 1. Step down using high-efficiency switching converters, followed by a second stage of regulation using a low
noise LDO to provide switching noise reduction and improved voltage accuracy.
2. 2. Directly step down the final ADC supply voltage using high-efficiency switching converters. This approach
provides the best efficiency, but care must be taken to ensure switching noise is minimized to prevent
degraded ADC performance.
TI WEBENCH® Power Designer can be used to select and design the individual power-supply elements
needed: see the WEBENCH® Power Designer
Recommended switching regulators for the first stage include the TPS62821, and similar devices.
Recommended low dropout (LDO) linear regulators include the TPS7A4701, TPS7A90, LP5901, and similar
devices.
For the switch regulator only approach, the ripple filter must be designed with a notch frequency that aligns with
the switching ripple frequency of the DC/DC converter. Note the switching frequency reported from WEBENCH®
and design the EMI filter and capacitor combination to have the notch frequency centered as needed. Figure
10-2 and Figure 10-3 illustrate the two approaches.
AVDD and IOVDD supply voltages should not be shared in order to prevent digital switching noise from coupling
into the analog signal chain.
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FB
FB
2.1V
1.8V
DC/DC
Regulator
5V-12V
LDO
AVDD
10uF 10uF 0.1uF
47uF
47uF
GND
GND
GND
FB
IOVDD
10uF 10uF 0.1uF
FB = Ferrite bead filter
GND
Figure 10-2. Example: LDO Linear Regulator Approach
EMI FILTER
FB
1.8V
DC/DC
Regulator
5V-12V
AVDD
10uF 10uF 10uF
10uF 10uF 0.1uF
GND
GND
FB
IOVDD
10uF 10uF 0.1uF
GND
Ripple filter notch frequency to match switching frequency of the DC/DC regulator
FB = Ferrite bead filter
Figure 10-3. Example Switcher-Only Approach
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11 Layout
11.1 Layout Guidelines
There are several critical signals which require specific care during board design:
1. Analog input and clock signals
•
Traces should be as short as possible and vias should be avoided where possible to minimize impedance
discontinuities.
•
•
Traces should be routed using loosely coupled 100-Ω differential traces.
Differential trace lengths should be matched as close as possible to minimize phase imbalance and HD2
degradation.
2. Digital output interface
Traces should be routed using tightly coupled 100-Ω differential traces.
3. Voltage reference
•
•
The bypass capacitor should be placed as close to the device pins as possible and connected between
VREF and REFGND – on top layer avoiding vias.
•
Depending on configuration an additional bypass capacitor between REFBUF and REFGND may be
recommended and should also be placed as close to pins as possible on top layer.
4. Power and ground connections
•
•
•
•
Provide low resistance connection paths to all power and ground pins.
Use power and ground planes instead of traces.
Avoid narrow, isolated paths which increase the connection resistance.
Use a signal/ground/power circuit board stackup to maximize coupling between the ground and power
plane.
11.2 Layout Example
The following screen shot shows the top layer of the ADC368x EVM.
•
•
•
Signal and clock inputs are routed as differential signals on the top layer avoiding vias.
SLVDS output interface lanes are routed differential and length matched
Bypass caps are close to the VREF pin on the top layer avoiding vias.
SLVDS routed tightly
coupled and length matched
Bypass caps on VREF close
to the pins and no vias
Clock routing
without vias
Analog inputs on
top layer (no vias)
Figure 11-1. Layout example: top layer of ADC368x EVM
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12 Device and Documentation Support
12.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
12.2 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.5 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
ADC3683IRSBR
ADC3683IRSBT
ACTIVE
ACTIVE
WQFN
WQFN
RSB
RSB
40
40
3000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 105
-40 to 105
AZ3683
AZ3683
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
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30-Dec-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
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1-Sep-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
ADC3683IRSBR
WQFN
RSB
40
3000
330.0
12.4
5.3
5.3
1.5
8.0
12.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
1-Sep-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
WQFN RSB 40
SPQ
Length (mm) Width (mm) Height (mm)
350.0 350.0 43.0
ADC3683IRSBR
3000
Pack Materials-Page 2
PACKAGE OUTLINE
RSB0040E
WQFN - 0.8 mm max height
S
C
A
L
E
2
.
7
0
0
PLASTIC QUAD FLATPACK - NO LEAD
5.1
4.9
B
A
PIN 1 INDEX AREA
5.1
4.9
C
0.8 MAX
SEATING PLANE
0.08 C
0.05
0.00
2X 3.6
(0.2) TYP
EXPOSED
11
20
THERMAL PAD
36X 0.4
10
21
2X
41
SYMM
3.6
3.15 0.1
1
30
0.25
0.15
40X
40
31
PIN 1 ID
(OPTIONAL)
0.1
C A B
SYMM
0.5
0.3
0.05
40X
4219096/A 11/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
RSB0040E
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
3.15)
SYMM
40
31
40X (0.6)
40X (0.2)
1
30
36X (0.4)
41
SYMM
(4.8)
(1.325)
(
0.2) TYP
VIA
10
21
(R0.05)
TYP
11
20
(1.325)
(4.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
0.05 MIN
ALL AROUND
0.05 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
EXPOSED
METAL
EXPOSED
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4219096/A 11/2017
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
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EXAMPLE STENCIL DESIGN
RSB0040E
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(0.785)
4X ( 1.37)
40
31
40X (0.6)
1
30
40X (0.2)
36X (0.4)
SYMM
(0.785)
(4.8)
41
(R0.05) TYP
10
21
METAL
TYP
20
11
SYMM
(4.8)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
EXPOSED PAD 41
75% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:20X
4219096/A 11/2017
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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