ADC78H89 [TI]
7 通道、500 KSPS、12 位模数转换器;
| 型号： | ADC78H89 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 7 通道、500 KSPS、12 位模数转换器 转换器 模数转换器 |
| 文件： | 总26页 (文件大小：794K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ADC78H89
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SNAS201D –APRIL 2003–REVISED MARCH 2013
ADC78H89 7-Channel, 500 KSPS, 12-Bit A/D Converter
Check for Samples: ADC78H89
1
FEATURES
DESCRIPTION
The ADC78H89 is
CMOS 12-bit analog-to-digital converter with
conversion throughput of 500 KSPS. The converter is
based on successive-approximation register
architecture with an internal track-and-hold circuit. It
can be configured to accept up to seven input signals
on pins AIN1 through AIN7.
a low-power, seven-channel
23
•
Seven Input Channels
a
•
Variable Power Management
•
•
•
Independent Analog and Digital Supplies
SPI™/QSPI™/MICROWIRE™/DSP Compatible
Packaged in 16-Lead TSSOP
a
The output serial data is straight binary, and is
compatible with several standards, such as SPI™,
QSPI™, MICROWIRE™, and many common DSP
serial interfaces.
APPLICATIONS
•
•
•
•
•
Automotive Navigation
Portable Systems
Medical Instruments
The ADC78H89 may be operated with independent
Mobile Communications
Instrumentation and Control Systems
analog and digital supplies. The analog supply (AVDD
)
can range from +2.7V to +5.25V, and the digital
supply (DVDD) can range from +2.7V to AVDD. Normal
power consumption using a +3V or +5V supply is
1.5 mW and 8.3 mW, respectively. The power-down
feature reduces the power consumption to just
0.3 µW using a +3V supply, or 0.5 µW using a +5V
supply. The ADC78H89 is packaged in a 16-lead
TSSOP package. Operation over the industrial
temperature range of −40°C to +85°C is ensured.
KEY SPECIFICATIONS
•
•
•
•
Conversion Rate: 500 KSPS
DNL: ± 1 LSB (max)
INL: ± 1 LSB (max)
Power Consumption
–
–
3V Supply: 1.5 mW (typ)
5V Supply: 8.3 mW (typ)
Connection Diagram
SCLK
DOUT
DIN
CS
NC
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
AV
DD
DV
DD
GND
ADC78H89
GND
AIN7
AIN6
AIN5
AIN1
AIN2
AIN3
AIN4
9
Figure 1. 16-Lead TSSOP
See PW Package
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
TRI-STATE is a trademark of Texas Instruments.
2
3
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2003–2013, Texas Instruments Incorporated
ADC78H89
SNAS201D –APRIL 2003–REVISED MARCH 2013
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Block Diagram
Pin Descriptions and Equivalent Circuits
Pin No.
ANALOG I/O
5 - 11
Symbol
Equivalent Circuit
Description
AIN1 to AIN7
NC
Analog inputs. These signals can range from 0V to AVDD.
This pin is not connected internally, and can be left floating, or tied to
ground.
2
DIGITAL I/O
Digital clock input. The range of frequencies for this input is 50 kHz
to 8 MHz, with ensured performance at 8 MHz. This clock directly
controls the conversion and readout processes.
16
SCLK
Digital data output. The output samples are clocked out of this pin on
falling edges of the SCLK pin.
15
14
1
DOUT
DIN
Digital data input. The ADC78H89's Control Register is loaded
through this pin on rising edges of the SCLK pin.
Chip select. On the falling edge of CS, a conversion process begins.
Conversions continue as long as CS is held low.
CS
POWER SUPPLY
Positive analog supply pin. This pin should be connected to a quiet
+2.7V to +5.25V source and bypassed to GND with 0.1 µF ceramic
monolithic and 1 µF tantalum capacitors located within 1 cm of the
power pin.
3
AVDD
DVDD
GND
Positive digital supply pin. This pin should be connected to a +2.7V
to AVDD supply, and bypassed to GND with a 0.1 µF ceramic
monolithic capacitor located within 1 cm of the power pin.
13
The ground return for both analog and digital supplies. These pins
are tied directly together internally, so must be connected to the
same potential. If any potential exists across these pins, large
currents will flow through the device.
4, 12
2
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SNAS201D –APRIL 2003–REVISED MARCH 2013
(1) (2)
ABSOLUTE MAXIMUM RATINGS
Analog Supply Voltage AVDD
−0.3V to 6.5V
−0.3V to AVDD + 0.3V, max 6.5V
−0.3V to AVDD +0.3V
±10 mA
Digital Supply Voltage DVDD
Voltage on Any Pin to GND
(3)
Input Current at Any Pin
(3)
Package Input Current
±20 mA
(4)
Power Dissipation at TA = 25°C
See
(5)
ESD Susceptibility
Human Body Model
Machine Model
2500V
250V
(6)
Soldering Temperature, Infrared, 10 seconds
Junction Temperature
260°C
+150°C
Storage Temperature
−65°C to +150°C
(1) Absolute maximum ratings are limiting values which indicate limits beyond which damage to the device may occur. Operating Ratings
indicate conditions for which the device is functional, but do not ensure specific performance limits. For specifications and test
conditions, see the Electrical Characteristics. The specifications apply only for the test conditions listed. Some performance
characteristics may degrade when the device is not operated under the listed test conditions.
(2) All voltages are measured with respect to GND = 0V, unless otherwise specified.
(3) When the input voltage at any pin exceeds the power supplies (that is, VIN < AGND or VIN > VA or VD), the current at that pin should be
limited to 10 mA. The 50 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies
with an input current of 10 mA to five.
(4) The absolute maximum junction temperature (TJmax) for this device is 150°C. The maximum allowable power dissipation is dictated by
TJmax, the junction-to-ambient thermal resistance (θJA), and the ambient temperature (TA), and can be calculated using the formula
PDMAX = (TJmax − TA)/θJA. The values for maximum power dissipation listed above will be reached only when the ADC78H89 is
operated in a severe fault condition (e.g. when input or output pins are driven beyond the power supply voltages, or the power supply
polarity is reversed). Obviously, such conditions should always be avoided.
(5) Human body model is 100 pF capacitor discharged through a 1.5 kΩ resistor. Machine model is 220 pF discharged through ZERO
ohms.
(6) See http://www.ti.com/ for other methods of soldering surface mount devices.
(1) (2)
OPERATING RATINGS
Operating Temperature Range
−40°C ≤ TA ≤ +85°C
+2.7V to +5.25V
+2.7V to AVDD
-0.3V to AVDD
AVDD Supply Voltage
DVDD Supply Voltage
Digital Input Pins Voltage Range
Clock Frequency
50 kHz to 8 MHz
0V to AVDD
Analog Input Voltage
(1) Absolute maximum ratings are limiting values which indicate limits beyond which damage to the device may occur. Operating Ratings
indicate conditions for which the device is functional, but do not ensure specific performance limits. For specifications and test
conditions, see the Electrical Characteristics. The specifications apply only for the test conditions listed. Some performance
characteristics may degrade when the device is not operated under the listed test conditions.
(2) All voltages are measured with respect to GND = 0V, unless otherwise specified.
PACKAGE THERMAL RESISTANCE
Package
θJA
16-lead TSSOP on 4-layer, 2 oz. PCB
96°C / W
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(1)
ADC78H89 CONVERTER ELECTRICAL CHARACTERISTICS
The following specifications apply for AVDD = DVDD = +2.7V to 5.25V, fSCLK = 8 MHz, fSAMPLE = 500 KSPS unless otherwise
noted. Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25°C.
(2)
Symbol
Parameter
Conditions
Typical
Limits
Units
STATIC CONVERTER CHARACTERISTICS
Resolution with No Missing Codes
AVDD = +5.0V, DVDD = +3.3V
AVDD = +5.0V, DVDD = +3.3V
AVDD = +5.0V, DVDD = +3.3V
AVDD = +5.0V, DVDD = +3.3V
AVDD = +5.0V, DVDD = +3.3V
AVDD = +5.0V, DVDD = +3.3V
AVDD = +5.0V, DVDD = +3.3V
12
±1
±1
±2
±2
±3
±3
Bits
INL
Integral Non-Linearity
Differential Non-Linearity
Offset Error
LSB (max)
LSB (max)
LSB (max)
LSB (max)
LSB (max)
LSB (max)
DNL
OE
OEM
GE
Offset Error Match
Gain Error
GEM
Gain Error Match
DYNAMIC CONVERTER CHARACTERISTICS
AVDD = +5.0V, DVDD = +3.0V,
fIN = 40.2 kHz, −0.02 dBFS
SINAD
SNR
Signal-to-Noise Plus Distortion Ratio
Signal-to-Noise Ratio
72.6
72.8
-86
dB
dB
dB
dB
bits
dB
dB
dB
AVDD = +5.0V, DVDD = +3.0V,
fIN = 40.2 kHz, −0.02 dBFS
AVDD = +5.0V, DVDD = +3.0V,
fIN = 40.2 kHz, −0.02 dBFS
THD
Total Harmonic Distortion
AVDD = +5.0V, DVDD = +3.0V,
fIN = 40.2 kHz, −0.02 dBFS
SFDR
ENOB
Spurious-Free Dynamic Range
Effective Number of Bits
88
AVDD = +5.0V, DVDD = +3.0V,
fIN = 40.2 kHz, −0.02 dBFS
11.8
-82
AVDD = +5.0V, DVDD = +3.0V,
fIN = 40.2 kHz
Channel-to-Channel Crosstalk
Intermodulation Distortion, Second Order AVDD = +5.0V, DVDD = +3.0V,
-93
Terms
fa = 40.161 kHz, fb = 41.015 kHz
IMD
Intermodulation Distortion, Third Order
Terms
AVDD = +5.0V, DVDD = +3.0V,
fa = 40.161 kHz, fb = 41.015 kHz
-90
AVDD = +5V
AVDD = +3V
11
8
MHz
MHz
FPBW
-3 dB Full Power Bandwidth
ANALOG INPUT CHARACTERISTICS
0 to
AVDD
VIN
Input Range
V
IDCL
DC Leakage Current
±1
µA (max)
pF
In Track Mode
In Hold Mode
33
3
CINA
Input Capacitance
pF
DIGITAL INPUT CHARACTERISTICS
DVDD = +4.75Vto +5.25V
DVDD = +2.7V to +3.6V
DVDD = +2.7V to +5.25V
VIN = 0V or DVDD
2.4
2.1
0.8
1
V (min)
V (min)
VIH
Input High Voltage
VIL
Input Low Voltage
Input Current
V (max)
µA (max)
pF (max)
IIN
±0.01
2
CIND
Input Capacitance
4
DIGITAL OUTPUT CHARACTERISTICS
ISOURCE = 200 µA,
DVDD = +2.7V to +5.25V
VOH
VOL
Output High Voltage
Output Low Voltage
DVDD −0.5
V (min)
ISINK = 200 µA
0.4
±1
4
V (max)
µA (max)
pF (max)
IOZH, IOZL TRI-STATE Leakage Current
COUT
TRI-STATE Output Capacitance
Output Coding
2
Straight (Natural) Binary
(1) Data sheet min/max specification limits are specified by design, test, or statistical analysis.
(2) Tested limits are specified to AOQL (Average Outgoing Quality Level).
4
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ADC78H89 CONVERTER ELECTRICAL CHARACTERISTICS (1) (continued)
The following specifications apply for AVDD = DVDD = +2.7V to 5.25V, fSCLK = 8 MHz, fSAMPLE = 500 KSPS unless otherwise
noted. Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25°C.
(2)
Symbol
Parameter
Conditions
Typical
Limits
Units
POWER SUPPLY CHARACTERISTICS (CL = 10 pF)(3)
2.7
V (min)
V (max)
AVDD
DVDD
,
Analog and Digital Supply Voltages
AVDD ≥ DVDD
5.25
AVDD = DVDD = +4.75V to +5.25V,
fSAMPLE = 500 KSPS, fIN = 40 kHz
1.65
0.5
0.1
0.1
2.3
2.3
mA (max)
mA (max)
µA
Total Supply Current, Normal Mode
(Operational, CS low)
AVDD = DVDD = +2.7V to +3.6V,
fSAMPLE = 500 KSPS, fIN = 40 kHz
IDD
AVDD = DVDD = +4.75V to +5.25V,
fSAMPLE = 0 KSPS
Total Supply Current, Shutdown (CS
high)
AVDD = DVDD = +2.7V to +3.6V,
fSAMPLE = 0 KSPS
µA
AVDD = DVDD = +4.75V to +5.25V
AVDD = DVDD = +2.7V to +3.6V
AVDD = DVDD = +4.75V to +5.25V
AVDD = DVDD = +2.7V to +3.6V
8.3
1.5
0.5
0.3
12
mW (max)
mW (max)
µW
Power Consumption, Normal Mode
(Operational, CS low)
8.3
PD
Power Consumption, Shutdown (CS
high)
µW
AC ELECTRICAL CHARACTERISTICS
fSCLK
Maximum Clock Frequency
Minimum Clock Frequency
Maximum Sample Rate
Conversion Time
8
MHz (max)
kHz
50
fS
500
13
40
60
3
KSPS (min)
SCLK cycles
% (min)
tCONV
13
50
DC
Duty Cycle
% (max)
tACQ
Track/Hold Acquisition Time
Throughput Time
Full-Scale Step Input
SCLK cycles
SCLK cycles
KSPS (min)
ns
Conversion Time + Acquisition Time
16
500
fRATE
tAD
Throughput Rate
Aperture Delay
4
(3) Except power supply pins.
ADC78H89 TIMING SPECIFICATIONS
The following specifications apply for AVDD = DVDD = +2.7V to 5.25V, fSCLK = 8 MHz, CL = 50 pF, Boldface limits apply for
TA = TMIN to TMAX: all other limits TA = 25°C.
Symbol
Parameter
SCLK High to CS Fall Setup Time
SCLK Low to CS Fall Hold Time
Conditions
(1)
Typical
Limits
Units
t1a
t1b
t2
See
See
10
ns (min)
ns (min)
ns (max)
ns (max)
ns (max)
ns (max)
ns (min)
ns (min)
ns (max)
(1)
10
Delay from CS Until DOUT TRI-STATE™ Disabled
Data Access Time after SCLK Falling Edge
Data Setup Time Prior to SCLK Rising Edge
Data Valid SCLK Hold Time
30
t3
30
10
t4
t5
10
t6
SCLK High Pulse Width
0.4 x tSCLK
0.4 x tSCLK
20
t7
SCLK Low Pulse Width
t8
CS Rising Edge to DOUT High-Impedance
(1) Clock may be in any state (high or low) when CS is asserted, with the restrictions on setup and hold time given by t1a and t1b
.
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Timing Diagrams
Figure 2. ADC78H89 Operational Timing Diagram
Figure 3. Timing Test Circuit
CS
tCONVERT
tACQ
t6
SCLK
1
2
3
4
5
6
7
8
16
t7
t8
t2
t3
DOUT
DIN
Z3
Z2
Z1
Z0
DB11 DB10
DB9
DB8
DB1 DB0
t5
t4
DONTC
DONT DONTC ADD2 ADD1 ADD0
DONTC DONTC
Figure 4. ADC78H89 Serial Timing Diagram
Figure 5. SCLK and CS Timing Parameters
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Specification Definitions
ACQUISITION TIME is the time required to acquire the input voltage. That is, it is time required for the hold
capacitor to charge up to the input voltage.
APERTURE DELAY is the time between the fourth falling SCLK edge of a conversion and the time when the
input signal is acquired or held for conversion.
CONVERSION TIME is the time required, after the input voltage is acquired, for the ADC to convert the input
voltage to a digital word.
CROSSTALK is the coupling of energy from one channel into the other channel, or the amount of signal energy
from one analog input that appears at the measured analog input.
DIFFERENTIAL NON-LINEARITY (DNL) is the measure of the maximum deviation from the ideal step size of 1
LSB.
DUTY CYCLE is the ratio of the time that a repetitive digital waveform is high to the total time of one period. The
specification here refers to the SCLK.
EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE BITS) is another method of specifying Signal-to-Noise
and Distortion or SINAD. ENOB is defined as (SINAD - 1.76) / 6.02 and says that the converter is equivalent to a
perfect ADC of this (ENOB) number of bits.
FULL POWER BANDWIDTH is a measure of the frequency at which the reconstructed output fundamental
drops 3 dB below its low frequency value for a full scale input.
GAIN ERROR is the deviation of the last code transition (111...110) to (111...111) from the ideal (VREF - 1.5
LSB), after adjusting for offset error.
INTEGRAL NON-LINEARITY (INL) is a measure of the deviation of each individual code from a line drawn from
negative full scale (½ LSB below the first code transition) through positive full scale (½ LSB above the last code
transition). The deviation of any given code from this straight line is measured from the center of that code value.
INTERMODULATION DISTORTION (IMD) is the creation of additional spectral components as a result of two
sinusoidal frequencies being applied to the ADC input at the same time. It is defined as the ratio of the power in
the both second order (or all four third order) intermodulation products to the sum of the power in both of the
original frequencies. IMD is usually expressed in dBFS.
MISSING CODES are those output codes that will never appear at the ADC outputs. The ADC78H89 is ensured
not to have any missing codes.
OFFSET ERROR is the deviation of the first code transition (000...000) to (000...001) from the ideal (i.e. GND +
0.5 LSB).
SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in dB, of the rms value of the input signal to the rms
value of the sum of all other spectral components below one-half the sampling frequency, not including
harmonics or d.c.
SIGNAL TO NOISE PLUS DISTORTION (S/N+D or SINAD) Is the ratio, expressed in dB, of the rms value of the
input signal to the rms value of all of the other spectral components below half the clock frequency, including
harmonics but excluding d.c.
SPURIOUS FREE DYNAMIC RANGE (SFDR) is the difference, expressed in dB, between the rms values of the
input signal and the peak spurious signal, where a spurious signal is any signal present in the output spectrum
that is not present at the input.
TOTAL HARMONIC DISTORTION (THD) is the ratio, expressed in dB, expressed in dB or dBc, of the rms total
of the first five harmonic components at the output to the rms level of the input signal frequency as seen at the
output. THD is calculated as
2
Af22 +3+ Af6
THD = 20 • log10
2
Af1
(1)
where Af1 is the RMS power of the input frequency at the output and Af2 through Af6 are the RMS power in the
first 5 harmonic frequencies.
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THROUGHPUT TIME is the minimum time required between the start of two successive conversion. It is the
acquisition time plus the conversion time. In the case of the ADC78H89, this is 16 SCLK periods.
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TYPICAL PERFORMANCE CHARACTERISTICS
TA = +25°C, fSAMPLE = 500 KSPS, fSCLK = 8 MHz, fIN = 40.2 kHz unless otherwise stated.
DNL
DNL
Figure 6.
INL
Figure 7.
INL
Figure 8.
Figure 9.
DNL vs. Supply
INL vs. Supply
Figure 10.
Figure 11.
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
TA = +25°C, fSAMPLE = 500 KSPS, fSCLK = 8 MHz, fIN = 40.2 kHz unless otherwise stated.
SNR vs. Supply
THD vs. Supply
Figure 12.
Figure 13.
ENOB vs. Supply
SNR vs. Input Frequency
Figure 14.
Figure 15.
THD vs. Input Frequency
ENOB vs. Input Frequency
Figure 16.
Figure 17.
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
TA = +25°C, fSAMPLE = 500 KSPS, fSCLK = 8 MHz, fIN = 40.2 kHz unless otherwise stated.
Spectral Response
Spectral Response
Figure 18.
Figure 19.
Power Consumption vs. Throughput
Figure 20.
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APPLICATION INFORMATION
USING THE ADC78H89
An operational timing diagram and a serial interface timing diagram for the ADC78H89 are shown in the Timing
Diagrams section. CS is chip select, which initiates conversions and frames the serial data transfers. SCLK
(serial clock) controls both the conversion process and the timing of serial data. DOUT is the serial data output
pin, where a conversion result is sent as a serial data stream, MSB first. Data to be written to the ADC78H89's
Control Register is placed on DIN, the serial data in pin.
The conversion process and serial data timing are controlled by the SCLK. Each conversion requires 16 SCLK
cycles to complete. Conversions are begun by bringing CS low. Several conversions can be executed
sequentially in a single serial frame, which is defined as the time between falling and rising edges of CS. If CS is
held low continuously, the ADC78H89 will perform conversions continuously.
Each time CS goes low, a conversion process is initiated simultaneously with a load of the Control Register. The
new contents of the Control Register will affect the next conversion. There is thus a one sample delay between
selecting a new input channel and observing the corresponding output.
Basic operation of the ADC78H89 begins with CS going low and initiating a conversion process and data
transfer. At this time the DOUT pin comes out of the high impedance state. The converter enters track mode at
the first falling edge of SCLK after CS is brought low, and begins to acquire the input signal. Acquisition of the
input signal continues during the first three SCLK cycles after the falling edge of CS. This acquisition time is
denoted by tACQ. The converter goes from track to hold mode on the fourth falling edge of SCLK, and the analog
input signal is sampled at this time (see Figure 2).
The ADC78H89 supports idling SCLK either high or low between conversions, when CS is high. The SCLK may
also run continuously while CS is high. Regardless of whether the clock is idled, SCLK is internally gated off
when CS is brought high. If SCLK is in the low state when CS goes high, the subsequent fall of CS will generate
a falling edge of the internal version of SCLK, putting the ADC into the track mode. This is seen as the first falling
edge of SCLK. If SCLK is in the high state when CS goes high, the ADC enters the track mode on the first falling
edge of SCLK after the falling edge of CS (see Figure 2). In both cases, a total of sixteen falling edges are
required to complete the acquisition and conversion process.
Sixteen SCLK cycles are required to read a complete sample from the ADC78H89. Each bit of the sample
(including leading zeros) is valid on subsequent rising edges of SCLK. The ADC78H89 will produce four leading
zeros on DOUT, followed by twelve data bits, most significant first. The final data bit, DB0, will be clocked out on
the 16th SCLK falling edge, and will be valid on the following rising edge. Depending upon the application, the
first edge on SCLK after CS goes low may be either a falling edge or a rising edge. If the first SCLK edge after
CS goes low is a falling edge, all four leading zeros will be valid on the first four rising edges of SCLK. If the first
SCLK edge after CS goes low is a rising edge, the first leading zero may not be set up in time for a
microprocessor or DSP to read it correctly. The remaining data bits are still clocked out on the falling edges of
SCLK, so that they are valid on the rising edges of SCLK.
Control information must be written to the Control Register whenever a conversion is performed. Information is
written to the Control Register on the first eight rising edges of SCLK of each conversion. It is important that the
DIN line is set up with the correct information when reading data from the ADC78H89. The input channel to be
sampled in the next conversion process is determined by writing information to the Control Register in the current
conversion.
On the rising edges of SCLK after CS is brought low, data is loaded through the DIN pin to the Control Register,
MSB first. Since the data on the DIN pin is transferred while the conversion data is being read, 16 serial clocks
are required for each data transfer. The control register only loads the information on the first 8 rising SCLK
edges; DIN is ignored for the last 8 rising edges. Table 1 describes the bit functions, where MSB indicates the
first bit of information in the loaded data. At power-up, the control register defaults to all zeros in the bit locations.
Table 1. Control Register Bits
Bit 7 (MSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
DONTC
DONTC
ADD2
ADD1
ADD0
DONTC
DONTC
DONTC
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Table 2. Control Register Bit Descriptions
Bit #:
Symbol:
DONTC
ADD2
Description
7, 6, 2, 1, 0
Don't care. The value of this bit does not affect the device.
5
4
3
These three bits determine which input channel will be sampled and converted on the next falling edge of CS.
The mapping between codes and channels is shown in Table 3.
ADD1
ADD0
Table 3. Input Channel Selection
ADD2
ADD1
ADD0
Input Channel
AIN1 (Default)
AIN2
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
AIN3
AIN4
AIN5
AIN6
AIN7
GND
ADC78H89 OPERATION
The ADC78H89 is a successive-approximation analog-to-digital converter designed around a charge-
redistribution digital-to-analog converter. Simplified schematics of the ADC78H89 in both track and hold modes
are shown in Figure 21 and Figure 22, respectively. In Figure 21, the ADC78H89 is in track mode: switch SW1
connects the sampling capacitor to one of seven analog input channels through the multiplexer, and SW2
balances the comparator inputs. The ADC78H89 is in this state for the first three SCLK cycles after CS is
brought low.
The user does not need to worry about any kind of power-up delays or dummy conversions with the ADC78H89.
The part is able to acquire input to full resolution in the first conversion immediately following power-up. The first
conversion after power up will be that of the first channel.
Figure 22 shows the ADC78H89 in hold mode: switch SW1 connects the sampling capacitor to ground,
maintaining the sampled voltage, and switch SW2 unbalances the comparator. The control logic then instructs
the charge-redistribution DAC to add or subtract fixed amounts of charge from the sampling capacitor until the
comparator is balanced. When the comparator is balanced, the digital word supplied to the DAC is the digital
representation of the analog input voltage. The ADC78H89 is in this state for the last thirteen SCLK cycles after
CS is brought low.
Figure 21. ADC78H89 in Track Mode
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Figure 22. ADC78H89 in Hold Mode
ADC78H89 TRANSFER FUNCTION
The output format of the ADC89H89 is straight binary. Code transitions occur midway between successive
integer LSB values. The LSB width for the ADC78H89 is AVDD / 4096. The ideal transfer characteristic is shown
in Figure 23.
Figure 23. Ideal Transfer Characteristic
TYPICAL APPLICATION CIRCUIT
A typical application of the ADC78H89 is shown in Figure 24. The split analog and digital supplies are both
provided in this example by the Texas Instruments LP2950 low-dropout voltage regulator, available in a variety of
fixed and adjustable output voltages. The analog supply is bypassed with a capacitor network located close to
the ADC78H89. The digital supply is separated from the analog supply by an isolation resistor and conditioned
with additional bypass capacitors. The ADC78H89 uses the analog supply (AVDD) as its reference voltage, so it
is very important that AVDD be kept as clean as possible. Because of the ADC78H89's low power requirements, it
is also possible to use a precision reference as a power supply to maximize performance. The four-wire interface
is also shown connected to a microprocessor or DSP.
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Figure 24. Typical Application Circuit
ANALOG INPUTS
An equivalent circuit for one of the ADC78H89's input channels is shown in Figure 25. At the start of each
conversion, one of the ADC78H89's seven channels are selected. Diodes D1 and D2 provide ESD protection for
the analog inputs. At no time should an analog input be beyond (AVDD + 300 mV) or (GND - 300 mV), as these
ESD diodes will begin conducting, which could cause erratic operation.
The capacitor C1 in Figure 25 typically has a value of 3 pF, and is mainly the package pin capacitance. Resistor
R1 is the on resistance of the multiplexer and track / hold switch, and is typically 500 ohms. Capacitor C2 is the
ADC78H89 sampling capacitor, and is typically 30 pF. The ADC78H89 will deliver best performance when driven
by a low-impedance source to eliminate distortion caused by the charging of the sampling capacitor.
Figure 25. Equivalent Input Circuit
In applications where dynamic performance is critical, the ADC78H89 might need to be driven with a low output-
impedance amplifier. In addition, when using the ADC78H89 to sample AC signals, a band-pass or low-pass filter
will reduce harmonics and noise, improving dynamic performance.
DIGITAL INPUTS AND OUTPUTS
The ADC78H89's digital inputs (SCLK, CS, and DIN) are limited by and cannot exceed the analog supply voltage
AVDD. The digital input pins are not prone to latch-up; SCLK, CS, and DIN may be asserted before DVDD without
any risk.
POWER SUPPLY CONSIDERATIONS
The ADC78H89 has two supplies, although they could both have the same potential. There are two major power
supply concerns with this product. They are relative power supply levels, including power-on sequencing, and the
effect of digital supply noise on the analog supply.
Power Management
The ADC78H89 is a dual-supply device. These two supplies share ESD resources, and thus care must be
exercised to ensure that the power supplies are applied in the correct sequence. To avoid turning on the ESD
diodes, the digital supply (DVDD) cannot exceed the analog supply (AVDD) by more than 300 mV. The
ADC78H89's analog power supply must, therefore, be applied before (or concurrently with) the digital power
supply.
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The ADC78H89 is fully powered-up whenever CS is low, and fully powered-down whenever CS is high, with one
exception: the ADC78H89 automatically enters power-down mode between the 16th falling edge of a conversion
and the 1st falling edge of the subsequent conversion (see Figure 2).
The ADC78H89 can perform multiple conversions back to back; each conversion requires 16 SCLK cycles. The
ADC78H89 will perform conversions continuously as long as CS is held low.
The user may trade off throughput for power consumption by simply performing fewer conversions per unit time.
The Power Consumption vs. Sample Rate curve in the Typical Performance Curves section shows the typical
power consumption of the ADC78H89 versus throughput. To calculate the power consumption, simply multiply
the fraction of time spent in the normal mode by the normal mode power consumption (8.3 mW with AVDD
=
DVDD = +3.6V, for example), and add the fraction of time spent in shutdown mode multiplied by the shutdown
mode power dissipation (0.3 mW with AVDD = DVDD = +3.6V).
Power Supply Noise Considerations
The charging of any output load capacitance requires current from the digital supply, DVDD. The current pulses
required from the supply to charge the output capacitance will cause voltage variations on the digital supply. If
these variations are large enough, they could cause degrade SNR and SINAD performance of the ADC.
Furthermore, if the analog and digital supplies are tied directly together, the noise on the digital supply will be
coupled directly into the analog supply, causing greater performance degradation than noise on the digital
supply. Furthermore, discharging the output capacitance when the digital output goes from a logic high to a logic
low will dump current into the die substrate, which is resistive. Load discharge currents will cause "ground
bounce" noise in the substrate that will degrade noise performance if that current is large enough. The larger is
the output capacitance, the more current flows through the die substrate and the greater is the noise coupled into
the analog channel, degrading noise performance.
The first solution is to decouple the analog and digital supplies from each other, or use separate supplies for
them, to keep digital noise out of the analog supply. To keep noise out of the digital supply, keep the output load
capacitance as small as practical. If the load capacitance is greater than 25 pF, use a 100 Ω series resistor at
the ADC output, located as close to the ADC output pin as practical. This will limit the charge and discharge
current of the output capacitance and improve noise performance.
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SNAS201D –APRIL 2003–REVISED MARCH 2013
REVISION HISTORY
Changes from Revision C (March 2013) to Revision D
Page
•
Changed layout of National Data Sheet to TI format .......................................................................................................... 16
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
ADC78H89CIMT/NOPB
ADC78H89CIMTX/NOPB
ACTIVE
TSSOP
TSSOP
PW
16
16
92
RoHS & Green
SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 85
-40 to 85
78H89
CIMT
ACTIVE
PW
2500 RoHS & Green
SN
78H89
CIMT
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
ADC78H89CIMTX/NOPB TSSOP
PW
16
2500
330.0
12.4
6.95
5.6
1.6
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
TSSOP PW 16
SPQ
Length (mm) Width (mm) Height (mm)
367.0 367.0 35.0
ADC78H89CIMTX/NOPB
2500
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TUBE
T - Tube
height
L - Tube length
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device
Package Name Package Type
PW TSSOP
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
ADC78H89CIMT/NOPB
16
92
495
8
2514.6
4.06
Pack Materials-Page 3
PACKAGE OUTLINE
PW0016A
TSSOP - 1.2 mm max height
S
C
A
L
E
2
.
5
0
0
SMALL OUTLINE PACKAGE
SEATING
PLANE
C
6.6
6.2
TYP
A
0.1 C
PIN 1 INDEX AREA
14X 0.65
16
1
2X
5.1
4.9
4.55
NOTE 3
8
9
0.30
16X
4.5
4.3
NOTE 4
1.2 MAX
0.19
B
0.1
C A B
(0.15) TYP
SEE DETAIL A
0.25
GAGE PLANE
0.15
0.05
0.75
0.50
A
20
0 -8
DETAIL A
TYPICAL
4220204/A 02/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.
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EXAMPLE BOARD LAYOUT
PW0016A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
SYMM
16X (1.5)
(R0.05) TYP
16
1
16X (0.45)
SYMM
14X (0.65)
8
9
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
15.000
(PREFERRED)
SOLDER MASK DETAILS
4220204/A 02/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
PW0016A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
16X (1.5)
SYMM
(R0.05) TYP
16
1
16X (0.45)
SYMM
14X (0.65)
8
9
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
4220204/A 02/2017
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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Copyright © 2022, Texas Instruments Incorporated
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