ADS1018_14 [TI]
Ultra-Small, Low-Power, SPIâ¢-Compatible, 12-Bit, Analog-to-Digital Converter and Temperature Sensor with Internal Reference;
| 型号： | ADS1018_14 |
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TEXAS INSTRUMENTS |
| 描述： | Ultra-Small, Low-Power, SPIâ¢-Compatible, 12-Bit, Analog-to-Digital Converter and Temperature Sensor with Internal Reference |
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ADS1118
www.ti.com
SBAS457A –OCTOBER 2010–REVISED JULY 2011
Ultra-Small, Low-Power, SPI™-Compatible, 16-Bit
Analog-to-Digital Converter and Temperature Sensor with Internal Reference
Check for Samples: ADS1118
1
FEATURES
DESCRIPTION
The ADS1118 is
a
precision analog-to-digital
23
•
Ultra-Small QFN Package:
converter (ADC) with 16 bits of resolution offered in
an ultra-small, leadless QFN-10 package or an
MSOP-10 package. The ADS1118 is designed with
precision, power, and ease of implementation in
mind. The ADS1118 features an onboard reference
and oscillator. Data are transferred via a serial
peripheral interface (SPI). The ADS1118 operates
from a single power supply ranging from 2V to 5.5V.
2mm × 1,5mm × 0,4mm
Wide Supply Range: 2.0V to 5.5V
Low Current Consumption:
•
•
–
–
Continuous Mode: Only 150μA
Single-Shot Mode: Auto Shutdown
•
Programmable Data Rate:
8SPS to 860SPS
•
•
•
Single-Cycle Settling
Internal Low-Drift Voltage Reference
Internal Temperature Sensor:
The ADS1118 can perform conversions at rates up to
860 samples per second (SPS). An onboard
programmable gain amplifier (PGA) is available on
the ADS1118 that offers input ranges from the supply
to as low as ±256mV. This range allows both large
and small signals to be measured with high
resolution. The ADS1118 also features an input
multiplexer (MUX) that provides two differential or
four single-ended inputs. The ADS1118 can also
function as a high-accuracy temperature sensor. This
temperature sensor can be used for system-level
temperature monitoring or cold junction compensation
for thermocouples.
–
0.5°C Max Error
•
•
•
Internal Oscillator
Internal PGA
Four Single-Ended or Two Differential Inputs
APPLICATIONS
•
Temperature Measurement:
–
–
–
Thermocouple Measurement
Cold Junction Compensation
Thermistor Measurement
The ADS1118 operates either in continuous
conversion mode or
automatically powers down after
a
single-shot mode that
conversion.
a
•
•
Portable Instrumentation
Factory Automation and Process Controls
Single-shot mode significantly reduces current
consumption during idle periods. The ADS1118 is
specified from –40°C to +125°C.
2V
0.1
F
2V
1Mȍ
GND
F
GND
0.1
1
500ȍ
500ȍ
AIN0
VDD
ADS1118
F
Voltage
Reference
AIN1
0.1
F
1Mȍ
SCLK
GND
GND
CS
SPI
Interface
16-bit Ȉǻ
ADC
MUX
PGA
DOUT/DRDY
DIN
2V
1Mȍ
GND
F
0.1
1
500ȍ
500ȍ
AIN2
High Accuracy
Temp Sensor
F
Oscillator
AIN3
GND
GND
0.1
F
1Mȍ
GND
GND
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
3
SPI is a trademark of Motorola.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2010–2011, Texas Instruments Incorporated
ADS1118
SBAS457A –OCTOBER 2010–REVISED JULY 2011
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION
For the most current package and ordering information, see the Package Option Addendum at the end of this
document, or visit the device product folder on www.ti.com.
ABSOLUTE MAXIMUM RATINGS(1)
ADS1118
–0.3 to +5.5
UNIT
V
VDD to GND
Analog input current
100, momentary
10, continuous
–0.3 to VDD + 0.3
–0.3 to +5.5
mA
mA
V
Analog input current
Analog input voltage to GND
DIN, DOUT/DRDY, SCLK, CS voltage to GND
Human body model (HBM)
V
±4000
±1000
V
V
JEDEC standard 22, test method A114-C.01, all pins
ESD ratings
Charged device model (CDM)
JEDEC standard 22, test method C101, all pins
Operating temperature range
Maximum junction temperature
Storage temperature range
–40 to +125
+150
°C
°C
°C
–60 to +150
(1) Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to absolute
maximum conditions for extended periods may affect device reliability.
PRODUCT FAMILY
INPUT CHANNELS
RESOLUTION MAXIMUM SAMPLE
SPECIAL
(Differential/
DEVICE
ADS1118
ADS1018
ADS1115
ADS1114
ADS1113
ADS1015
ADS1014
ADS1013
(Bits)
RATE (SPS)
FEATURES
PGA
Yes
Yes
Yes
Yes
No
INTERFACE
Single-Ended)
16
860
Temperature sensor
Temperature sensor
Comparator
Comparator
None
SPI
SPI
I2C
I2C
I2C
I2C
I2C
I2C
2/4
2/4
2/4
1/1
1/1
2/4
1/1
1/1
12
3300
860
16
16
860
16
860
12
3300
3300
3300
Comparator
Comparator
None
Yes
Yes
No
12
12
2
Copyright © 2010–2011, Texas Instruments Incorporated
ADS1118
www.ti.com
SBAS457A –OCTOBER 2010–REVISED JULY 2011
ELECTRICAL CHARACTERISTICS
Maximum/minimum specifications at –40°C to +125°C, VDD = 3.3V, data rate = 8SPS, and full-scale (FS) = ±2.048V, unless
otherwise noted. Typical values are at +25°C, VDD = 3.3V, data rate = 8SPS, and full-scale (FS) = ±2.048V, unless otherwise
noted.
ADS1118
PARAMETER
ANALOG INPUT
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Full-scale input voltage(1)
VIN = (AINP) – (AINN)
±4.096/PGA
V
V
Analog input voltage
AINP or AINN to GND
GND
VDD
Differential input impedance
See Table 1
FS = ±6.144V(1)
FS = ±4.096V(1), ±2.048V
FS = ±1.024V
8
6
MΩ
MΩ
MΩ
MΩ
Common-mode input impedance
3
FS = ±0.512V, ±0.256V
100
SYSTEM PERFORMANCE
Resolution
No missing codes
All data rates
16
Bits
SPS
%
Data rate (DR)
8, 16, 32, 64, 128, 250, 475, 860
–10 10
See Typical Characteristics
Data rate variation
Output noise
Integral nonlinearity
DR = 8SPS, FS = ±2.048V, best fit(2)
FS = ±2.048V, differential inputs
FS = ±2.048V, single-ended inputs
FS = ±2.048V
1
LSB
LSB
LSB
LSB/°C
LSB/V
%
±0.1
±0.25
0.002
0.2
±2
Offset error
Offset drift
Offset power-supply rejection
Gain error(3)
FS = ±2.048V, with dc supply variation
FS = ±2.048V at +25°C
FS = ±0.256V
0.01
7
0.15
40
ppm/°C
ppm/°C
ppm/°C
ppm/V
%
Gain drift(3)(4)
FS = ±2.048V
FS = ±6.144V(1)
5
5
Gain power-supply rejection
PGA gain match(3)
Gain match
10
Match between any two PGA gains
Match between any two inputs
Match between any two inputs
At dc and FS = ±0.256V
0.01
0.01
0.6
0.1
0.1
%
Offset match
LSB
dB
105
100
90
At dc and FS = ±2.048V
dB
Common-mode rejection
At dc and FS = ±6.144V(1)
fCM = 60Hz, DR = 860SPS
fCM = 50Hz, DR = 860SPS
dB
105
105
dB
dB
TEMPERATURE SENSOR
Temperature sensor range
Temperature sensor resolution
–40
+125
°C
°C/LSB
°C
0.03125
0.2
0°C to +70°C
–40°C to +125°C
vs supply
±0.5
±1
Temperature sensor accuracy
0.4
°C
0.03125
±0.25
°C/V
(1) This parameter expresses the full-scale range of the ADC scaling. In no event should more than the smaller of VDD + 0.3V or 5.5V be
applied to this device.
(2) Best fit INL covers 99% of full-scale.
(3) Includes all errors from onboard PGA and reference.
(4) Not production tested; ensured by characterization.
Copyright © 2010–2011, Texas Instruments Incorporated
3
ADS1118
SBAS457A –OCTOBER 2010–REVISED JULY 2011
www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
Maximum/minimum specifications at –40°C to +125°C, VDD = 3.3V, data rate = 8SPS, and full-scale (FS) = ±2.048V, unless
otherwise noted. Typical values are at +25°C, VDD = 3.3V, data rate = 8SPS, and full-scale (FS) = ±2.048V, unless otherwise
noted.
ADS1118
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DIGITAL INPUT/OUTPUT
Logic level
VIH
0.7VDD
GND
VDD
V
V
V
V
VIL
0.2VDD
VOH
IOH = 1mA
IOL = 1mA
0.8VDD
GND
VOL
0.2VDD
Input leakage
IH
VIH = 5.5V
VIL = GND
±10
±10
μA
μA
IL
POWER-SUPPLY REQUIREMENTS
Power-supply voltage
2
5.5
2
V
Power-down current at +25°C
Power-down current up to +125°C
Operating current at +25°C
Operating current up to +125°C
VDD = 5.0V
0.5
μA
5
μA
Supply current
150
200
300
μA
μA
0.9
0.5
0.3
mW
mW
mW
Power dissipation
VDD = 3.3V
VDD = 2.0V
TEMPERATURE
Storage temperature
Specified temperature
–60
–40
+150
+125
°C
°C
THERMAL INFORMATION
ADS1118
THERMAL METRIC(1)
DGS
10 PINS
186.8
51.5
UNITS
θJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
θJCtop
θJB
Junction-to-board thermal resistance
108.4
2.7
°C/W
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
ψJB
106.5
n/a
θJCbot
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
4
Copyright © 2010–2011, Texas Instruments Incorporated
ADS1118
www.ti.com
SBAS457A –OCTOBER 2010–REVISED JULY 2011
PIN CONFIGURATIONS
RUG PACKAGE
QFN-10
(TOP VIEW)
DGS PACKAGE
MSOP-10
(TOP VIEW)
DIN
10
9
SCLK
1
2
3
4
5
10 DIN
SCLK
1
2
3
4
DOUT/DRDY
9
8
7
6
DOUT/DRDY
VDD
CS
GND
AIN0
AIN1
8
7
VDD
AIN3
AIN2
CS
GND
AIN0
AIN3
6
AIN2
5
AIN1
PIN DESCRIPTIONS
ANALOG/
DIGITAL
INPUT/
PIN #
PIN NAME
SCLK
CS
OUTPUT
DESCRIPTION
1
2
Digital input
Digital input
Analog
Serial clock input
Chip select; active low
Ground
3
GND
4
AIN0
Analog input
Analog input
Analog input
Analog input
Analog
Differential channel 1: positive input or single-ended channel 1 input
Differential channel 1: negative input or single-ended channel 2 input
Differential channel 2: positive input or single-ended channel 3 input
Differential channel 2: negative input or single-ended channel 4 input
Power supply: 2V to 5.5V
5
AIN1
6
AIN2
7
AIN3
8
VDD
9
DOUT/DRDY
DIN
Digital output
Digital input
Serial data out combined with data ready; active low
Serial data input
10
Copyright © 2010–2011, Texas Instruments Incorporated
5
ADS1118
SBAS457A –OCTOBER 2010–REVISED JULY 2011
SPI TIMING CHARACTERISTICS
CS
www.ti.com
tCSH
tSCLK
tCSSC
tSPWH
tSCCS
SCLK
DIN
tDIHD
tSPWL
tSCSC
tDIST
tDOHD
tCSDOD
tCSDOZ
Hi-Z
tDOPD
Hi-Z
DOUT
Figure 1. Serial Interface Timing
TIMING REQUIREMENTS: SERIAL INTERFACE TIMING
At TA = –40°C to +125°C and VDD = 2V to 5.5V, unless otherwise noted.
SYMBOL
tCSSC
DESCRIPTION
MIN
MAX
UNIT
ns
CS low to first SCLK: setup time(1)
SCLK period
100
250
100
100
tSCLK
ns
tSPWH
SCLK pulse width: high
ns
ns
tSPWL
SCLK pulse width: low(2)
28
50
ms
ns
tDIST
tDIHD
Valid DIN to SCLK falling edge: setup time
Valid DIN to SCLK falling edge: hold time
SCLK rising edge to valid new DOUT: propagation delay(3)
SCLK rising edge to DOUT invalid: hold time
CS low to DOUT driven: propagation delay
CS high to DOUT Hi-Z: propagation delay
CS high pulse
50
50
ns
tDOPD
tDOHD
tCSDOD
tCSDOZ
tCSH
ns
0
ns
100
100
200
100
ns
ns
ns
tSCCS
Final SCLK falling edge to CS high
ns
(1) CS can be tied low.
(2) Holding SCLK low longer than 28ms resets the SPI interface.
(3) DOUT load = 20pF || 100kΩ to DGND.
6
Copyright © 2010–2011, Texas Instruments Incorporated
ADS1118
www.ti.com
SBAS457A –OCTOBER 2010–REVISED JULY 2011
TYPICAL CHARACTERISTICS
At TA = +25°C and VDD = 3.3V, unless otherwise noted.
TOTAL ERROR vs INPUT SIGNAL
DATA RATE vs TEMPERATURE
4
3
4
3
VDD = 2V
VDD = 3.3V
VDD = 5V
Includes noise, offset, and gain error.
2
2
1
1
0
0
−1
−2
−3
−4
-1
-2
-3
-4
FS = ±2.048V
Data Rate = 860SPS
Differential Inputs
−60 −40 −20
0
20
40
60
80 100 120 140
-2.048
-1.024
0
1.024
2.048
Temperature (°C)
G028
Input Signal (V)
Figure 2.
Figure 3.
NOISE vs INPUT SIGNAL
NOISE vs SUPPLY VOLTAGE
10
8
35
30
25
20
15
10
5
FS = ±0.512V
FS = ±2.048V
DR = 860SPS
DR = 860SPS
6
4
DR = 128SPS
DR = 8SPS
DR = 128SPS
DR = 8SPS
2
0
0
2.0
−0.5 −0.4 −0.3 −0.2 −0.1
0
0.1 0.2 0.3 0.4 0.5
2.5
3.0
3.5
4.0
4.5
5.0
5.5
Input Voltage (V)
Supply Voltage (V)
G017
G018
Figure 4.
Figure 5.
NOISE vs TEMPERATURE
INL vs SUPPLY VOLTAGE(1)
10
9
8
7
6
5
4
3
2
1
15
12.5
10
FS = ±2.048V
Data Rate = 8SPS
FS = ±0.256V
FS = ±0.512V
FS = ±2.048V
FS = ±6.144V
7.5
5
2.5
0
−40
−20
0
20
40
60
80
100
120
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
Temperature (°C)
Supply Voltage (V)
G019
G010
Figure 6.
Figure 7.
(1) This parameter expresses the full-scale range of the ADC scaling. In no event should more than VDD + 0.3V be applied to this device.
Copyright © 2010–2011, Texas Instruments Incorporated
7
ADS1118
SBAS457A –OCTOBER 2010–REVISED JULY 2011
www.ti.com
TYPICAL CHARACTERISTICS (continued)
At TA = +25°C and VDD = 3.3V, unless otherwise noted.
INL vs INPUT SIGNAL
INL vs INPUT SIGNAL
5
10
8
FS = ±2.048V
VDD = 3.3V
−40°C
+25°C
4
3
2
DR = 8SPS
Best Fit
6
+125°C
4
1
2
0
0
−1
−2
−3
−4
−5
−2
−4
−6
−8
−10
FS = ±0.512V
VDD = 3.3V
DR = 8SPS
Best Fit
−40°C
+25°C
+125°C
−2
−1.5
−1
−0.5
0
0.5
1
1.5
2
−0.5 −0.4 −0.2 −0.1
0
0.1
0.2
0.4
0.5
Input Signal (V)
Input Signal (V)
G011
G012
Figure 8.
Figure 9.
INL vs INPUT SIGNAL
INL vs INPUT SIGNAL
5
4
10
8
FS = ±2.048V
VDD = 5V
DR = 8SPS
Best Fit
−40°C
+25°C
+125°C
3
6
2
4
1
2
0
0
−1
−2
−3
−4
−5
−2
−4
−6
−8
−10
FS = ±0.512V
VDD = 5V
DR = 8SPS
Best Fit
−40°C
+25°C
+125°C
−2
−1.5
−1
−0.5
0
0.5
1
1.5
2
−0.5 −0.4 −0.2 −0.1
0
0.1
0.2
0.4
0.5
Input Signal (V)
Input Signal (V)
G013
G014
Figure 10.
Figure 11.
INL vs TEMPERATURE
INL vs DATA RATE
12
10
8
16
14
12
10
8
FS = ±2.048V
DR = 8SPS
Best Fit
VDD = 2V
VDD = 3.3V
VDD = 5V
FS = ±2.048V
Best Fit
−40°C
+25°C
+125°C
6
6
4
4
2
2
0
0
−60 −40 −20
0
20
40
60
80 100 120 140
8
16
32
64
128
250
475
860
Temperature (°C)
Data Rate (SPS)
G015
G016
Figure 12.
Figure 13.
8
Copyright © 2010–2011, Texas Instruments Incorporated
ADS1118
www.ti.com
SBAS457A –OCTOBER 2010–REVISED JULY 2011
TYPICAL CHARACTERISTICS (continued)
At TA = +25°C and VDD = 3.3V, unless otherwise noted.
SINGLE-ENDED OFFSET vs TEMPERATURE
SINGLE-ENDED OFFSET vs SUPPLY
60
60
40
AIN0 to GND
AIN1 to GND
AIN2 to GND
AIN0 to GND
AIN1 to GND
AIN2 to GND
AIN3 to GND
40
AIN3 to GND
20
20
0
−20
−40
0
−20
−40
−60
FS = ±2.048V
−60
FS = ±2.048V
−40
−20
0
20
40
60
80
100
120
2
2.5
3
3.5
4
4.5
5
Temperature (°C)
Supply Voltage (V)
G004
G005
Figure 14.
Figure 15.
DIFFERENTIAL OFFSET vs TEMPERATURE
DIFFERENTIAL OFFSET vs SUPPLY
40
30
40
30
AIN0 to AIN1
AIN0 to AIN3
AIN1 to AIN3
AIN2 to AIN3
AIN0 to AIN1
AIN0 to AIN3
AIN1 to AIN3
AIN2 to AIN3
20
20
10
10
0
0
−10
−20
−30
−40
−10
−20
−30
−40
FS = ±2.048V
FS = ±2.048V
2.5
−40
−20
0
20
40
60
80
100
120
2
3
3.5
4
4.5
5
Temperature (°C)
Supply Voltage (V)
G006
G007
Figure 16.
Figure 17.
OFFSET DRIFT HISTOGRAM
OFFSET HISTOGRAM
15
10
5
200
150
100
50
Offset Drift from −40°C to +125°C
FS = ±2.048V, MUX = AIN0 to AIN3
30 units from one production lot
540 units from 3 production lots
FS = ±2.048V
0
0
Offset (µV)
Offset Drift (LSB/°C)
G046
G000
Figure 18.
Figure 19.
Copyright © 2010–2011, Texas Instruments Incorporated
9
ADS1118
SBAS457A –OCTOBER 2010–REVISED JULY 2011
www.ti.com
TYPICAL CHARACTERISTICS (continued)
At TA = +25°C and VDD = 3.3V, unless otherwise noted.
GAIN ERROR vs TEMPERATURE
GAIN ERROR vs SUPPLY
0.05
0.04
0.03
0.02
0.01
0
0.15
0.10
0.05
0
FS = ±256mV
FS = ±2.048V
−0.01
−0.02
−0.03
−0.04
−0.05
FS = ±0.256V
FS = ±0.512V
FS = ±1.024V
FS = ±2.048V
FS = ±4.096V
FS = ±6.144V
-0.05
-0.10
-0.15
−40 −20
0
20
40
60
80
100 120 140
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
Temperature (°C)
G008
Supply Voltage (V)
Figure 20.
Figure 21.
TEMPERATURE SENSOR ERROR
vs
GAIN ERROR HISTOGRAM
AMBIENT TEMPERATURE
1
200
150
100
50
Average Temperature Error
Average ± 3 sigma
Average ± 6 sigma
540 units from 3 production lots
FS = ±2.048V
0.8
0.6
0.4
0.2
0
−0.2
−0.4
−0.6
−0.8
−1
0
−40
−20
0
20
40
60
80
100
120
Temperature (°C)
G023
Gain Error (%)
G000
Figure 22.
Figure 23.
TEMPERATURE SENSOR ERROR HISTOGRAM
TEMPERATURE SENSOR ERROR HISTOGRAM
40
35
30
25
20
15
10
5
40
35
30
25
20
15
10
5
Ambient temperature = −40°C
48 units from 3 production lots
Ambient temperature = 0°C
48 units from 3 production lots
0
0
Temperature Error (°C)
Temperature Error (°C)
G040
G040
Figure 24.
Figure 25.
10
Copyright © 2010–2011, Texas Instruments Incorporated
ADS1118
www.ti.com
SBAS457A –OCTOBER 2010–REVISED JULY 2011
TYPICAL CHARACTERISTICS (continued)
At TA = +25°C and VDD = 3.3V, unless otherwise noted.
TEMPERATURE SENSOR ERROR HISTOGRAM
TEMPERATURE SENSOR ERROR HISTOGRAM
40
40
35
30
25
20
15
10
5
Ambient temperature = 25°C
48 units from 3 production lots
Ambient temperature = 70°C
48 units from 3 production lots
35
30
25
20
15
10
5
0
0
Temperature Error (°C)
Temperature Error (°C)
G042
G043
Figure 26.
Figure 27.
TEMPERATURE SENSOR ERROR HISTOGRAM
OPERATING CURRENT vs TEMPERATURE
40
35
30
25
20
15
10
5
300
Ambient temperature = 125°C
48 units from 3 production lots
250
200
150
100
50
VDD = 5V
VDD = 3.3V
VDD = 2V
0
0
-40 -20
0
20
40
60
80
100 120 140
Temperature (°C)
Temperature Error (°C)
G045
Figure 28.
Figure 29.
SHUTDOWN CURRENT vs TEMPERATURE
FREQUENCY RESPONSE
0
5
4.5
4
Data Rate = 8SPS
VDD = 2V
VDD = 3.3V
VDD = 5V
-10
-20
-30
-40
-50
-60
-70
-80
3.5
3
2.5
2
1.5
1
0.5
0
−40 −20
0
20
40
60
80
100 120 140
1
10
100
1k
10k
Temperature (°C)
G003
Input Frequency (Hz)
Figure 30.
Figure 31.
Copyright © 2010–2011, Texas Instruments Incorporated
11
ADS1118
SBAS457A –OCTOBER 2010–REVISED JULY 2011
www.ti.com
OVERVIEW
The ADS1118 is a very small, low-power, 16-bit, delta-sigma (ΔΣ) analog-to-digital converter (ADC). The
ADS1118 is extremely easy to configure and design into a wide variety of applications, and allows precise
measurements to be obtained with very little effort. Both experienced and novice users of data converters find
designing with the ADS1118 family to be intuitive and problem-free.
The ADS1118 consists of a ΔΣ analog-to-digital (A/D) core with adjustable gain, an internal voltage reference, a
clock oscillator, and an SPI. This device is also a highly linear and accurate temperature sensor. All of these
features are intended to reduce required external circuitry and improve performance. Figure 32 shows the
ADS1118 functional block diagram.
VDD
Device
Voltage
Reference
MUX
Gain = 2/3, 1,
2, 4, 8, or 16
CS
AIN0
AIN1
SCLK
16-Bit DS
SPI
Interface
PGA
DIN
ADC
DOUT/DRDY
AIN2
AIN3
Temperature
Sensor
Oscillator
GND
Figure 32. ADS1118 Functional Block Diagram
The ADS1118 A/D core measures a differential signal, VIN, that is the difference of AINP and AINN. The converter
core consists of a differential, switched-capacitor ΔΣ modulator followed by a digital filter. This architecture
results in a very strong attenuation in any common-mode signals. Input signals are compared to the internal
voltage reference. The digital filter receives a high-speed bitstream from the modulator and outputs a code
proportional to the input voltage.
The ADS1118 has two available conversion modes: single-shot mode and continuous conversion mode. In
single-shot mode, the ADC performs one conversion of the input signal upon request and stores the value to an
internal conversion register. The device then enters a low-power shutdown mode. This mode is intended to
provide significant power savings in systems that require only periodic conversions or when there are long idle
periods between conversions. In continuous conversion mode, the ADC automatically begins a conversion of the
input signal as soon as the previous conversion is completed. The rate of continuous conversion is equal to the
programmed data rate. Data can be read at any time and always reflect the most recent completed conversion.
12
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ADS1118
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SBAS457A –OCTOBER 2010–REVISED JULY 2011
MULTIPLEXER
The ADS1118 contains an input multiplexer, as shown in Figure 33. Either four single-ended or two differential
signals can be measured. Additionally, AIN0 and AIN1 may be measured differentially to AIN3. The multiplexer is
configured by three bits in the Config Register. When single-ended signals are measured, the negative input of
the ADC is internally connected to GND by a switch within the multiplexer.
VDD
Device
AIN0
VDD
GND
AINP
AINN
AIN1
VDD
GND
AIN2
VDD
GND
AIN3
GND
GND
Figure 33. ADS1118 MUX
When measuring single-ended inputs, it is important to note that the negative range of the output codes are not
used. These codes are for measuring negative differential signals, such as (AINP – AINN) < 0. Electrostatic
discharge (ESD) diodes to VDD and GND protect the inputs. To prevent the ESD diodes from turning on, the
absolute voltage on any input must stay within the range of Equation 1:
GND – 0.3V < AINx < VDD + 0.3V
(1)
If it is possible that the voltages on the input pins may violate these conditions, external Schottky clamp diodes
and/or series resistors may be required to limit the input current to safe values (see the Absolute Maximum
Ratings table). While the analog inputs can support signals marginally above supply, under no circumstances
should any analog or digital input or output be driven to greater than 5.5V with respect to the GND pin.
Also, overdriving one unused input on the ADS1118 may affect conversions taking place on other input pins. If
overdrive on unused inputs is possible, it is recommended to clamp the signal with external Schottky diodes.
Copyright © 2010–2011, Texas Instruments Incorporated
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ADS1118
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www.ti.com
ANALOG INPUTS
The ADS1118 uses a switched-capacitor input stage where capacitors are continuously charged and then
discharged to measure the voltage between AINP and AINN. The capacitors used are small, and to external
circuitry, the average loading appears resistive. This structure is shown in Figure 34. The resistance is set by the
capacitor values and the rate at which they are switched. Figure 35 shows the on/off setting of the switches
illustrated in Figure 34. During the sampling phase, switches S1 are closed. This event charges CA1 to AINP, CA2
to AINN, and CB to (AINP – AINN). During the discharge phase, S1 is first opened and then S2 is closed. Both CA1
and CA2 then discharge to approximately 0.7V and CB discharges to 0V. This charging draws a very small
transient current from the source driving the ADS1118 analog inputs. The average value of this current can be
used to calculate the effective impedance (Reff), where Reff = VIN/IAVERAGE
.
0.7V
CA1
ZCM
ZDIFF
ZCM
Equivalent
Circuit
AINP
AINN
0.7V
0.7V
AINP
AINN
S1
S1
S2
S2
CB
CA2
f
= 250kHz
CLK
0.7V
Figure 34. Simplified Analog Input Circuit
tSAMPLE
ON
S1
OFF
ON
S2
OFF
Figure 35. S1 and S2 Switch Timing for Figure 34
The common-mode input impedance is measured by applying a common-mode signal to the shorted AINP and
AINN inputs and measuring the average current consumed by each pin. The common-mode input impedance
changes depending on the PGA gain setting, but is approximately 6MΩ for the default PGA gain setting. In
Figure 34, the common-mode input impedance is ZCM
.
The differential input impedance is measured by applying a differential signal to AINP and AINN inputs where one
input is held at 0.7V. The current that flows through the pin connected to 0.7V is the differential current and
scales with the PGA gain setting. In Figure 34, the differential input impedance is ZDIFF. Table 1 describes the
typical differential input impedance.
Table 1. Differential Input Impedance
FS (V)
±6.144V(1)(1)
±4.096V(1)(1)
±2.048V
DIFFERENTIAL INPUT IMPEDANCE
22MΩ
15MΩ
4.9MΩ
2.4MΩ
710kΩ
710kΩ
±1.024V
±0.512V
±0.256V
(1) This parameter expresses the full-scale range of the ADC scaling. In
no event should more than VDD + 0.3V be applied to this device.
14
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ADS1118
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SBAS457A –OCTOBER 2010–REVISED JULY 2011
The typical value of the input impedance cannot be neglected. Unless the input source has a low impedance, the
ADS1118 input impedance may affect the measurement accuracy. For sources with high output impedance,
buffering may be necessary. Note that active buffers introduce noise, and also introduce offset and gain errors.
All of these factors should be considered in high-accuracy applications.
Because the clock oscillator frequency drifts slightly with temperature, the input impedances also drift. For many
applications, this input impedance drift can be ignored, and the values given in Table 1 for typical input
impedance are valid.
FULL-SCALE INPUT
A PGA is implemented before the ΔΣ core of the ADS1118. The PGA can be set to gains of 2/3, 1, 2, 4, 8, and
16. Table 2 shows the corresponding full-scale (FS) ranges. The PGA is configured by three bits in the Config
register. The PGA = 2/3 setting allows input measurement to extend up to the supply voltage when VDD is larger
than 4V. Note, however, in this case (as well as for PGA = 1 and VDD < 4V) that it is not possible to reach a
full-scale output code on the ADC. Analog input voltages may never exceed the analog input voltage limits given
in the Electrical Characteristics table.
Table 2. PGA Gain Full-Scale Range
PGA SETTING
FS (V)
±6.144V(1)(1)
±4.096V(1)
±2.048V
2/3
1
2
4
±1.024V
8
±0.512V
16
±0.256V
(1) This parameter expresses the full-scale range of the ADC scaling. In
no event should more than VDD + 0.3V be applied to this device.
Copyright © 2010–2011, Texas Instruments Incorporated
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ADS1118
SBAS457A –OCTOBER 2010–REVISED JULY 2011
www.ti.com
DATA FORMAT
The ADS1118 provides 16 bits of data in binary twos complement format. The positive full-scale input produces
an output code of 7FFFh and the negative full-scale input produces an output code of 8000h. The output clips at
these codes for signals that exceed full-scale. Table 3 summarizes the ideal output codes for different input
signals. Figure 36 shows code transitions versus input voltage.
Table 3. Input Signal versus Ideal Output Code
INPUT SIGNAL, VIN
(AINP – AINN)
≥ FS (215 – 1)/215
+FS/215
IDEAL OUTPUT CODE(1)
7FFFh
0001h
0
0
–FS/215
FFFFh
8000h
≤ –FS
(1) Excludes the effects of noise, INL, offset, and gain errors.
0x7FFF
0x7FFE
0x0001
0x0000
0xFFFF
0x8001
0x8000
¼
¼
-FS
-FS
0
FS
Input Voltage (AINP - AINN)
215 - 1
215 - 1
FS
215
215
Figure 36. ADS1118 Code Transition Diagram
16
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ADS1118
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SBAS457A –OCTOBER 2010–REVISED JULY 2011
TEMPERATURE SENSOR
The temperature measurement mode of the ADS1118 is configured as a 14-bit result when enabled. Two bytes
must be read to obtain data. The first byte is the most significant byte (MSB), followed by a second byte, the
least significant byte (LSB). The first 14 bits are used to indicate temperature. That is, the 14-bit temperature
result is left-justified within the 16-bit result register and the last two bits always read back as '0'. One 14-bit LSB
equals 0.03125°C. Negative numbers are represented in binary twos complement format.
Table 4. 14-bit Temperature Data Format
TEMPERATURE (°C)
DIGITAL OUTPUT (BINARY)
01 0000 0000 0000
00 1111 1111 1111
00 1100 1000 0000
00 1010 0000 0000
00 1001 0110 0000
00 0110 0100 0000
00 0011 0010 0000
00 0000 0000 1000
00 0000 0000 0000
11 1111 1111 1000
11 1100 1110 0000
11 1001 0010 0000
HEX
1000
0FFF
0C80
0A00
0960
0640
0320
0008
0000
3FF8
3CE0
3920
128
127.96875
100
80
75
50
25
0.25
0
–0.25
–25
–55
Converting from Temperature to Digital Codes
For positive temperatures (for example, +50°C):
Twos complement is not performed on positive numbers. Therefore, simply convert the number to binary
code in a 14-bit left justified format with the MSB = 0 to denote the positive sign.
Example: (+50°C)/(0.03125°C/count) = 1600 = 0640h = 00 0110 0100 0000
For negative temperatures (for example –25°C):
Generate the twos complement of a negative number by complementing the absolute binary number and
adding 1. Then denote the negative sign with the MSB = 1.
Example:(|–25°C|)/(0.03125°C/count) = 800 = 0320h = 00 0011 0010 0000
Twos complement format: 11 1100 1101 1111 + 1 = 11 1100 1110 0000
Converting from Digital Codes to Temperature
To convert from digital codes to temperature, first check whether the MSB is a '0' or a '1'. If the MSB is a '0',
simply multiply the decimal code by 0.03125°C to obtain the result. If the MSB = 1, subtract '1' from the result
and complement all of the bits. Then multiply the result by –0.03125°C.
Example: ADS1118 reads back 0960h: 0960h has an MSB = 0.
(0960h)(0.03125°C) = (2400)(0.03125°C) = +75°C
Example: ADS1118 reads back 3CE0h: 3CE0h has an MSB = 1.
Complement the result: 3CE0h → 0320h
(0320h)(–0.03125°C) = (800)(–0.03125°C) = –25°C
Copyright © 2010–2011, Texas Instruments Incorporated
17
ADS1118
SBAS457A –OCTOBER 2010–REVISED JULY 2011
www.ti.com
ALIASING
As with any data converter, if the input signal contains frequencies greater than half the data rate, aliasing
occurs. To prevent aliasing, the input signal must be bandlimited. Some signals are inherently bandlimited; for
example, the output of a thermocouple has a limited rate of change. Nevertheless, these signals can contain
noise and interference components. These components can fold back into the sampling band in the same way as
with any other signal.
The ADS1118 digital filter provides some attenuation of high-frequency noise, but the digital sinc filter frequency
response cannot completely replace an anti-aliasing filter. For some applications, some external filtering may be
needed; in such instances, a simple RC filter is adequate.
When designing an input filter circuit, be sure to take into account the interaction between the filter network and
the input impedance of the ADS1118.
OPERATING MODES
The ADS1118 operates in one of two modes: continuous conversion or single-shot. In continuous conversion
mode, the ADS1118 continuously performs conversions. Once a conversion has been completed, the ADS1118
places the result in the Conversion Register and immediately begins another conversion. In single-shot mode,
the ADS1118 waits until the OS bit is set high. Once asserted, the bit is set to '0', indicating that a conversion is
currently in progress. Once conversion data are ready, the OS bit reasserts and the device powers down. Writing
a '1' to the OS bit during a conversion has no effect.
RESET AND POWER-UP
When the ADS1118 powers up, a reset is performed. As part of the reset process, the ADS1118 sets all of the
bits in the Config Register to the respective default settings. By default, the ADS1118 enters into a power-down
state at start-up. The device interface and digital are active, but no conversion occurs until the Config Register is
written to. The initial power-down state of the ADS1118 is intended to relieve systems with tight power-supply
requirements from encountering a surge during power-up.
DUTY CYCLING FOR LOW POWER
For many applications, improved performance at low data rates may not be required. For these applications, the
ADS1118 supports duty cycling that can yield significant power savings by periodically requesting high data rate
readings at an effectively lower data rate. For example, an ADS1118 in power-down mode with a data rate set to
860SPS could be operated by a microcontroller that instructs a single-shot conversion every 125ms (8SPS).
Because a conversion at 860SPS only requires about 1.2ms, the ADS1118 enters power-down mode for the
remaining 123.8ms. In this configuration, the ADS1118 consumes about 1/100th the power of the ADS1118
operated in continuous conversion mode. The rate of duty cycling is completely arbitrary and is defined by the
master controller.
SERIAL INTERFACE
The SPI-compatible serial interface consists of either four signals: CS, SCLK, DIN, and DOUT/DRDY; or three
signals, in which case CS may be tied low. The interface is used to read conversion data, read and write
registers, and control the ADS1118 operation.
CHIP SELECT (CS)
The chip select (CS) selects the ADS1118 for SPI communication. This feature is useful when multiple devices
share the serial bus. CS must remain low for the duration of the serial communication. When CS is taken high,
the serial interface is reset, SCLK is ignored, and DOUT/DRDY enters a high-impedance state; as such,
DOUT/DRDY cannot provide indication of data ready. In situations where multiple devices are present and
DOUT/DRDY must be monitored; by periodically lowering CS, the DOUT/DRDY pin either immediately goes high
to indicate that no new data are available, or it immediately goes low, to indicate that new data are present in the
Config Register and are available for transfer. New data can be transferred at anytime without concern of data
corruption. When a transmission starts, the current result is locked into the output shift register and does not
change until the communication is completed. This system avoids any possibility of data corruption.
18
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ADS1118
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SBAS457A –OCTOBER 2010–REVISED JULY 2011
SERIAL CLOCK (SCLK)
The serial clock (SCLK) features a Schmitt-triggered input and is used to clock data on the DIN and
DOUT/DRDY pins into and out of the ADS1118. Even though the input has hysteresis, it is recommended to
keep SCLK as clean as possible to prevent glitches from accidentally shifting the data. If SCLK is held low for
28ms, the serial interface resets and the next SCLK pulse starts a new communication cycle. This timeout
feature can be used to recover communication when a serial interface transmission is interrupted. When the
serial interface is idle, hold SCLK low.
DATA INPUT (DIN)
The data input pin (DIN) is used along with SCLK to send data to the ADS1118 (op code commands and register
data). The device latches data on DIN on the falling edge of SCLK. The ADS1118 never drives the DIN pin.
DATA OUTPUT AND DATA READY (DOUT/DRDY)
The data output and data ready pin (DOUT/DRDY) are used with SCLK to read conversion and register data
from the ADS1118. In Read Data Continuous mode, DOUT/DRDY goes low when conversion data are ready and
goes high 8µs before the data ready signal. Data on DOUT/DRDY are shifted out on the rising edge of SCLK. By
default DOUT/DRDY goes to a high-impedance state when CS is high. Alternatively, the ADS1118 DOUT/DRDY
pin can be configured as a weak pull-up if CS is high. This feature is intended to reduce the risk of DOUT/DRDY
floating near midsupply and causing leakage current in the master. If the ADS1118 does not share the serial bus
with another device, CS may be tied low.
POWER-DOWN MODE
When the PWDN bit in the Config Register is set to '1', the ADS1118 enters a lower power standby state. This
condition is also the default state the ADS1118 enters when power is first supplied. In this mode, the ADS1118
uses no more than 2μA of current. During this time, the device responds to commands, but does not perform any
data conversion. To exit this mode, simply write a '0' to the PWDN bit in the Config Register.
Copyright © 2010–2011, Texas Instruments Incorporated
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ADS1118
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www.ti.com
REGISTERS
The ADS1118 has two registers that are accessible via the SPI port. The Conversion Register contains the result
of the last conversion. The Config Register allows the modification of the ADS1118 operating modes and the
ability to query the status of the device.
Conversion Register
This 16-bit register contains the result of the last conversion in binary twos complement format. Following
power-up, the Conversion Register is cleared to '0', and remains '0' until the first conversion is completed.
The register format is shown in Table 5.
Table 5. Conversion Register (Read-Only)
BIT
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
NAME
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Config Register
The 16-bit register can be used to control the ADS1118 operating mode, input selection, data rate, PGA settings,
and comparator modes. The register format is shown in Table 6.
Table 6. Config Register (Read/Write)
BIT
15
14
13
12
11
10
9
8
NAME
OS
MUX2
MUX1
MUX0
PGA2
PGA1
PGA0
MODE
blank
BIT
7
6
5
4
3
2
1
0
NAME
DR2
DR1
DR0
TS_MODE
PULL_UP_
EN
NOP1
NOP2
CNV_RDY_FL
Default = 8583h.
Bit 15
OS: Operational status/single-shot conversion start
This bit determines the operational status of the device.
This bit can only be written when in power-down mode.
For a write status:
0 : No effect
1 : Begin a single conversion (when in power-down mode)
For a read status:
0 : Device is currently performing a conversion
1 : Device is not currently performing a conversion
Bits[14:12]
Bits[11:9]
Bit 8
MUX[2:0]: Input multiplexer configuration
These bits configure the input multiplexer. No effect when in temperature sensor mode.
000 : AINP = AIN0 and AINN = AIN1 (default)
001 : AINP = AIN0 and AINN = AIN3
010 : AINP = AIN1 and AINN = AIN3
011 : AINP = AIN2 and AINN = AIN3
100 : AINP = AIN0 and AINN = GND
101 : AINP = AIN1 and AINN = GND
110 : AINP = AIN2 and AINN = GND
111 : AINP = AIN3 and AINN = GND
PGA[2:0]: Programmable gain amplifier configuration
These bits configure the programmable gain amplifier. No effect when in temperature sensor mode.
000 : FS = ±6.144V(1)
001 : FS = ±4.096V(1)
010 : FS = ±2.048V (default)
011 : FS = ±1.024V
100 : FS = ±0.512V
101 : FS = ±0.256V
110 : FS = ±0.256V
111 : FS = ±0.256V
MODE: Device operating mode
This bit controls the current operational mode of the ADS1118.
0 : Continuous conversion mode
1 : Power-down single-shot mode (default)
(1) This parameter expresses the full-scale range of the ADC scaling. In no event should more than VDD + 0.3V be applied to this device.
20
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ADS1118
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Bits[7:5]
SBAS457A –OCTOBER 2010–REVISED JULY 2011
DR[2:0]: Data rate
These bits control the data rate setting.
000 : 8SPS
001 : 16SPS
010 : 32SPS
011 : 64SPS
100 : 128SPS (default)
101 : 250SPS
110 : 475SPS
111 : 860SPS
Bit 4
Bit 3
TS_MODE: Temperature sensor mode
This bit configures the ADC to convert temperature or input signals.
0 : ADC mode (default)
1 : Temperature sensor mode
PULL_UP_EN: Pull-up enable
This bit enables a weak pull-up resistor on the DOUT pin when CS is high. When enabled, a 400kΩ resistor
connects the bus line to supply when CS is high. When disabled, the DOUT pin floats when CS is high.
0 : Pull-up resistor disabled on DOUT pin (default)
1 : Pull-up resistor enabled on DOUT pin
Bits[2:0]
NOP: No operation
The NOP bits control whether data are written to the Config Register or not. In order for data to be written to
the Config Register, the NOP bits must be written as '01'. Any other value written to the NOP bits results in a
NOP command. This means that DIN can be held high or low during SCLK pulses without data being written to
the Config Register.
00 : Invalid data, do not update the contents of the Config Register.
01 : Valid data, update the Config Register (default)
10 : Invalid data, do not update the contents of the Config Register.
11: Invalid data, do not update the contents of the Config Register.
Bit 0
CNV_RDY_FL: Conversion ready flag
This bit is active low and indicates when data are ready from the converter. When it is high, a conversion is not
yet ready and is in process. The purpose of the conversion ready flag bit is to return the DOUT pin line to a
high state to prepare for the falling edge from new data.
0 : Data ready, no conversion in progress
1 : Data not ready, conversion in progress (default)
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ADS1118
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DATA RETRIEVAL
Data may be read in one of two modes: Single-Shot and Continuous Conversion mode. The mode is selected by
writing to the OS bit in the Config Register.
Continuous Conversion Mode
In Continuous Conversion mode, the conversion data are read from the device without an op code command.
When DOUT/DRDY asserts low (indicating that new conversion data are ready), the conversion data are read by
shifting the data out on DOUT. The MSB of the data (bit 15) on DOUT/DRDY is clocked out on the first rising
edge of SCLK.
As shown in Figure 37, the data consist of two bytes for the conversion result and an additional two bytes for the
Config Register readback. The data read operation must be completed 16/fCLK cycles before DOUT asserts
again.
CS(1)
1
9
17
25
SCLK
DOUT
Next Data
Ready
Hi-Z
DATA MSB
DATA LSB
CONFIG MSB
CONFIG MSB
CONFIG LSB
CONFIG LSB
CONFIG MSB
CONFIG LSB
DIN
(1) CS may be held low. If CS is low, DOUT/DRDY asserts low indicating new data.
Figure 37. Continuous Conversion Mode Timing
One-Shot Mode
In One-Shot mode, the conversion data are buffered, holding the current data until new conversion data replace
it. The conversion data are read by writing a '1' to the OS bit, followed by shifting the conversion data out.
The data consist of two bytes for the conversion result and two bytes for the Config Register; see Figure 38. In
contrast to the Continuous Conversion mode, DOUT does not assert low in one-shot mode.
CS(1)
1
9
17
25
tUPDATE
SCLK
DOUT
Data
Ready
Next Data
Ready
Hi-Z
DATA MSB
DATA LSB
CONFIG MSB
CONFIG MSB
CONFIG LSB
CONFIG LSB
CONFIG MSB
CONFIG LSB
DIN
(1) CS may be held low. If CS is low, DOUT/DRDY asserts low indicating new data.
Figure 38. One-Shot Mode Timing
22
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ADS1118
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SBAS457A –OCTOBER 2010–REVISED JULY 2011
APPLICATION INFORMATION
The following sections give example circuits and suggestions for using the ADS1118 in various situations.
BASIC CONNECTIONS AND LAYOUT CONSIDERATIONS
For many applications, connecting the ADS1118 is simple. A basic connection diagram for the ADS1118 is
shown in Figure 39. Most microcontroller SPI peripherals can operate with the ADS1118. The interface operates
in SPI mode 1 where CPOL = 0 and CPHA = 1. In SPI mode 1, SCLK idles low and data launch or are changed
only on rising edges of SCLK and data are latched or read by the master and slave on falling edges of SCLK.
Details of the SPI communication protocol employed by the ADS1118 can be found in the SPI Timing
Characteristics section. Although it is not required, it is a good practice to place 49.9Ω resistors in series with all
of the digital pins. This resistance smooths sharp transitions, suppresses overshoot, and offers some overvoltage
protection.
10
Device
VDD
DIN
1
2
3
4
SCLK
9
8
7
6
DOUT/DRDY
VDD
CS
GND
AIN0
AIN3
0.1mF (typ)
AIN2
Microcontroller or
Microprocessor
with SPI Port
AIN1
5
DOUT
DIN
Inputs Selected
from Configuration
Register
CS
SCLK
Figure 39. Typical Connections of the ADS1118
The fully differential voltage input of the ADS1118 is ideal for connection to differential sources with moderately
low source impedance, such as thermocouples and thermistors. Although the ADS1118 can read bipolar
differential signals, it cannot accept negative voltages on either input because every pin on the ADS1118
employs the use of ESD protection diodes. In the event that an input exceeds supply or drops below ground,
these diodes begin to turn on. Therefore, it may be helpful to think of the ADS1118 positive voltage input as
noninverting, and of the negative input as inverting.
When the ADS1118 is converting data, it draws current in short spikes. The 0.1μF bypass capacitor supplies the
momentary bursts of extra current needed from the supply. This bypass capacitor should be placed as close to
the device as possible. For very sensitive systems, or systems in harsh noise environments, avoiding the use of
vias for connecting the bypass capacitor may offer superior bypass and noise immunity.
Copyright © 2010–2011, Texas Instruments Incorporated
23
ADS1118
SBAS457A –OCTOBER 2010–REVISED JULY 2011
www.ti.com
It is recommended to employ best design practices when laying out a printed circuit board (PCB) for both analog
and digital components. This recommendation generally means that the layout should separate analog
components [such as ADCs, op amps, references, digital-to-analog converters (DACs), and analog MUXs] from
digital components [such as microcontrollers, complex programmable logic devices (CPLDs), field-programmable
gate arrays (FPGAs), radio frequency (RF) tranceivers, universal serial bus (USB) tranceivers, and switching
regulators]. An example of good component placement is shown in Figure 40. While Figure 40 provides a good
example of component placement, the best placement for each application is unique to the geometries,
components, and PCB fabrication capabilities being employed. That is, there is no single layout that is perfect for
every design and careful consideration must always be used when designing with any analog components.
Ground fill or
Ground plane
Ground fill or
Ground plane
Supply
Generation
Signal
Conditioning
(RC filters
and
Interface
Tranceiver
ADS1118
Microprocessor
Connector
or Antenna
amplifiers)
Ground fill or
Ground plane
Ground fill or
Ground plane
Figure 40. System Component Placement
The usage of split analog and digital ground planes is not necessary for improved noise performance (although
for thermal isolation it is a worthwhile consideration). However, the use of a solid ground plane or ground fill in
PCB areas with no components is essential for optimum performance. If the system being used employs a split
digital and analog ground plane, it is generally recommended that the ground planes be connected as close to
the ADS1118 as possible. It is also strongly recommended that digital components, especially RF portions, be
kept as far as practically possible from analog circuitry in a given system. Additionally, minimize the distance that
digital control traces run through analog areas and avoid allowing these traces to be near sensitive analog
components. Digital return currents usually flow through a ground path that is as close to the digital path as
possible. If a solid ground connection to a plane is not available, these currents may find paths back to the
source that interfere with analog performance. The implications that layout has on the temperature sensing
functions are much more significant than they are for the ADC functions. Details on layout considerations for the
temperature sensor can be found in the Thermocouple Measurement with Cold Junction Compensation section.
For a detailed layout example, refer to the ADS1118EVM User's Guide (SBAU184).
24
Copyright © 2010–2011, Texas Instruments Incorporated
ADS1118
www.ti.com
SBAS457A –OCTOBER 2010–REVISED JULY 2011
CONNECTING MULTIPLE DEVICES
Connecting multiple ADS1118s to a single bus is simple. Using a dedicated chip-select (CS) for each SPI
enabled device, SCLK, DIN, and DOUT/DRDY can be safely shared. By default, when CS goes high for the
ADS1118, DOUT/DRDY enters a 3-state mode. If the PULL_UP_EN bit is enabled, the DOUT/DRDY pin is
pulled up to the supply of the ADS1118 by a weak 400kΩ resistor. This feature is intended to prevent
DOUT/DRDY from floating near mid-rail and causing excess current leakage on a microcontroller input. The
ADS1118 cannot issue a data ready pulse on DOUT/DRDY when CS is high. In order to evaluate when a new
conversion is ready from the ADS1118 when using multiple devices, the master can periodically drop CS to the
ADS1118. When CS lowers, the DOUT/DRDY pin immediately drives either high or low. If the DOUT/DRDY line
drives low on a low CS, new data are currently available for clocking out at any time. If the DOUT/DRDY line
drives high, no new data are available and the ADS1118 returns the last read conversion result. Valid data can
be retrieved from the ADS1118 at anytime without concern of data corruption. When SCLK rises, the current
result is locked into DOUT/DRDY the output shift register. If a new conversion becomes available during data
transmission, it is not avialable for readback until a new SPI transmission is initiated.
Microcontroller or
Microprocessor
ADS1118
10
DIN
SCLK
DIN
1
2
3
4
SCLK DOUT/DRDY
9
8
7
6
VDD
CS
GND
AIN3
DOUT
CS1
AIN0
AIN2
AIN1
5
CS2
10
ADS1118
DIN
1
2
3
4
SCLK DOUT/DRDY
9
8
7
6
VDD
CS
GND
AIN0
AIN3
AIN2
AIN1
5
NOTE: Power and input connections omitted for clarity.
Figure 41. Connecting Multiple ADS1118s
Copyright © 2010–2011, Texas Instruments Incorporated
25
ADS1118
SBAS457A –OCTOBER 2010–REVISED JULY 2011
www.ti.com
USING GPIO PORTS FOR COMMUNICATION
Most microcontrollers have programmable input/output (I/O) pins that can be set in software to act as inputs or
outputs. If an SPI controller is not available, the ADS1118 can be connected to GPIO pins and the SPI bus
protocol can be simulated. Using GPIO pins to generate the SPI interface only requires that the pins be
configured as push/pull inputs or outputs. Furthermore, if the SCLK line is held low for more than 28ms, the
communication times out. This condition means that the GPIO ports must be capable of providing SCLK pulses
with no more than 28ms between pulses.
SINGLE-ENDED INPUTS
Although the ADS1118 has two differential inputs, the device can easily measure four single-ended signals.
Figure 42 shows a single-ended connection scheme. The ADS1118 is configured for single-ended measurement
by configuring the MUX to measure each channel with respect to ground. Data are then read out of one input
based on the selection in the Config Register. The single-ended signal can range from 0V to supply. The
ADS1118 loses no linearity anywhere within the input range. Negative voltages cannot be applied to this circuit
because the ADS1118 can only accept positive voltages.
The ADS1118 input range is bipolar differential. The single-ended circuit shown in Figure 42 covers only half the
ADS1118 input scale because it does not produce differentially negative inputs; therefore, one bit of resolution is
lost. For optimal noise performance, it is recommended to use differential configurations whenever possible.
Differential configurations maximize the dynamic range of the ADC and provide strong attenuation of
common-mode noise.
VDD
10
Device
DIN
1
2
3
4
SCLK
9
8
7
6
DOUT/DRDY
VDD
CS
GND
AIN0
AIN3
0.1mF (typ)
AIN2
AIN1
5
Inputs Selected
from Configuration
Register
NOTE: Digital pin connections omitted for clarity.
Figure 42. Measuring Single-Ended Inputs
The ADS1118 is also designed to allow AIN3 to serve as a common point for measurements by adjusting the
MUX configuration. AIN0, AIN1, and AIN2 can all be measured with respect to AIN3. In this configuration the
ADS1118 can operate with inputs where AIN3 serves as the common point. This ability improves the usable
range over the single-ended configuration because it allows negative voltages; however, it does not offer
attenuation of common-mode noise.
26
Copyright © 2010–2011, Texas Instruments Incorporated
ADS1118
www.ti.com
SBAS457A –OCTOBER 2010–REVISED JULY 2011
THERMOCOUPLE MEASUREMENT WITH COLD JUNCTION COMPENSATION
For an independent, two-channel thermocouple system, Figure 43 shows the basic connections. This circuit
contains a simple low-pass, anti-aliasing filter, mid-point bias, and open detection. While the digital filter of the
ADS1118 strongly attenuates high-frequency components of noise, it is generally recommended to provide a
first-order passive RC filter to further improve this performance. The differential RC filter formed by the 500Ω
resistors (RDIFFA and RDIFFB) and the 1µF (CDIFF) capacitor offers a cutoff frequency of approximately 320Hz.
Additional filtering can be achieved by increasing the differential capacitor or the resistance values. However,
avoid increasing the filter resistance beyond 1kΩ because the effects of the interaction with ADCs input
impedance begin to affect the linearity and gain error of the ADS1118. Because of the high sampling rates
supported by the ADS1118, simple post digital filtering in a microcontroller can alleviate the requirements of the
analog filter and can also offer the flexibility to implement filter notches at 50Hz or 60Hz. Two 0.1µF (CCMA and
CCMB) capacitors are also added to offer attenuation of high-frequency common-mode noise components.
Because mismatches in the common-mode capacitors cause differential noise, it is recommended that the
differential capacitor be at least an order of magnitude (10x) larger than the common-mode capacitors.
3.3V
0.1
F
GND
3.3V
GND
CCMA = 0.1
F
RPU = 1Mȍ
500ȍ
RDIFFA
AIN0
VDD
Voltage
Reference
CDIFF = 1
FAIN1
RDIFFB
(PGA Gain = 16)
±256mV FS
500ȍ
RPD = 1Mȍ
CCMB = 0.1
F
SCLK
Digital Filter
and
Interface
GND
GND
16-bit
Ȉǻ
CS
MUX
PGA
DOUT/DRDY
DIN
ADC
GND
3.3V
CCMA = 0.1
F
RPU = 1Mȍ
500ȍ
AIN2
RDIFFA
CDIFF = 1
FAIN3
Oscillator
Temp Sensor
RDIFFB
GND
GND
500ȍ
RPD = 1Mȍ
CCMB = 0.1
F
GND
GND
Figure 43. Two-Channel Thermocouple System
Copyright © 2010–2011, Texas Instruments Incorporated
27
ADS1118
SBAS457A –OCTOBER 2010–REVISED JULY 2011
www.ti.com
The two 1MΩ resistors (RPU and RPD) serve two purposes. The first purpose is to offer a common-mode bias
near midsupply. While the ADS1118 does offer the ability to float the common-mode of a signal or connect any of
the inputs to a common point such as ground or supply, it is generally recommended to avoid such situations.
Connecting one of the inputs to a common point decreases performance by converting common-mode noise into
differential signal noise that is not strongly attenuated. The second purpose of the 1MΩ resistors is to offer a
weak pull-up and pull-down for sensor open detection. In the event that a sensor is disconnected, the inputs to
the ADC extend to supply and ground and yield a full-scale readout, indicating a sensor disconnection.
The procedure to actually achieve cold junction compensation is simple and can be done in several ways. One
way is to interleave readings between the thermocouple inputs and the temperature sensor. That is, acquire one
on-chip temperature result for every thermocouple ADC voltage measured. If the cold junction is in a very stable
environment, more periodic cold junction measurements may be sufficient. These operations yield two results for
every thermocouple measurement and cold junction measurement cycle: the thermocouple voltage or VTC and
the on-chip temperature or TCJC. In order to account for the cold junction, the temperature sensor within the
ADS1118 must first be converted to a voltage proportional to the thermocouple currently being used yielding
VCJC. This conversion is generally accomplished by performing a reverse lookup on the table being used for the
thermocouple voltage to temperature conversion. Then, adding the two voltages yields the thermocouple
compensated voltage VActual where VCJC + VTC = VActual. VActual is then converted to temperature using the same
lookup table from before, yielding TActual
.
Thermocouple manufacturers usually supply a lookup table with their thermocouples that offer excellent accuracy
for linearization of a specific type of thermocouple. The granularity on these lookup tables is generally very
precise (at around 1°C for each lookup value). To save microcontroller memory and development time, an
interpolation technique applied to these values can be used. By choosing 16 to 32 equally-spaced values from
the manufacturer's lookup tables over a desired temperature range, using a simple linear approximation of
intervals between is generally very precise.
28
Copyright © 2010–2011, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
25-Jul-2011
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
ADS1118IDGSR
ADS1118IDGST
ACTIVE
ACTIVE
MSOP
MSOP
DGS
DGS
10
10
2500
250
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
ADS1118IRUGR
ADS1118IRUGT
PREVIEW
PREVIEW
X2QFN
X2QFN
RUG
RUG
10
10
TBD
TBD
Call TI
Call TI
Call TI
Call TI
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
22-Jul-2011
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
ADS1118IDGSR
ADS1118IDGST
MSOP
MSOP
DGS
DGS
10
10
2500
250
330.0
180.0
12.4
12.4
5.3
5.3
3.3
3.3
1.3
1.3
8.0
8.0
12.0
12.0
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
22-Jul-2011
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
ADS1118IDGSR
ADS1118IDGST
MSOP
MSOP
DGS
DGS
10
10
2500
250
370.0
195.0
355.0
200.0
55.0
45.0
Pack Materials-Page 2
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