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ADS1120-Q1

ZHCSCV9A –AUGUST 2014–REVISED OCTOBER 2014

ADS1120-Q1 用于小型信号传感器的车用低功耗、低噪声、

16 位模数转换器

1 特性

3 说明

1

•

符合汽车应用要求

具有符合 AEC-Q100 的下列结果：

ADS1120-Q1 是一款精密的 16 位模数转换器

(ADC)，所集成的多种特性能够降低系统成本并减少小

型传感器信号测量应用中的组件数量。这个器件具有

通过灵活的输入复用器 (MUX) 实现的两个差分输入或

四个单端输入，一个低噪声可编程增益放大器

•

–

温度等级 1：-40°C 至 +125°C

人体模型 (HBM) 静电放电 (ESD) 分类等级 2

充电器件模型 (CDM) ESD 分类等级 C4B

(PGA)，两个可编程励磁电流源，一个电压基准，一个

振荡器，一个低侧开关和一个精密温度传感器。

•

低流耗：

占空比模式下低至 120μA（典型值）

•

宽电源电压：2.3V 至 5.5V

此器件能够以高达 2000 次/秒 (SPS) 采样数据速率执

行转换，并且能够在单周期内稳定。针对噪声环境中

的工业应用，当采样频率为 20SPS 时，数字滤波器能

够实现 50Hz 和 60Hz 同步抑制。其内部 PGA 提供高

达 128V/V 的增益。此 PGA 使得 ADS1120-Q1 非常

适用于小传感器信号测量应用，例如电阻式温度检测器

(RTD)、热电偶、热敏电阻和桥式传感器。该器件在

使用 PGA 时支持测量伪差分或全差分信号。此外，

该器件还可配置为绕过内部 PGA，同时仍提供高输入

阻抗和高达 4V/V 的增益，从而实现单端测量。

可编程增益：1V/V 至 128V/V

可编程数据速率：5SPS 至 2kSPS

16 位无噪声分辨率（20SPS 时）

采用单周期稳定数字滤波器，在 20SPS 时

实现 50Hz 和 60Hz 同步抑制

•

两个差分输入或四个单端输入

双匹配可编程电流源：50μA 至 1.5mA

内部 2.048V 基准电压：漂移 5ppm/°C（典型值）

内部 2% 精准振荡器

内部温度传感器：精度 0.5°C（典型值）

SPI™- 兼容接口（模式 1）

在禁用 PGA 后的占空比模式下运行功耗可低至

120µA。通过模式 1 SPI 兼容接口建立与器件之间的

通信。 ADS1120-Q1 采用薄型小外形尺寸 (TSSOP)-

16 封装，额定工作温度范围为 -40°C 至 +125°C。

2 应用

•

温度传感器：

–

热电偶

器件信息⁽¹⁾

电阻式温度检测器 (RTD)：

2 线、3 线或 4 线制类型

部件号

封装

封装尺寸（标称值）

ADS1120-Q1

TSSOP (16)

5.00mm x 4.40mm

•

桥式传感器：

(1) 如需了解所有可用封装，请见数据表末尾的可订购产品附录。

–

压力传感器

应力计

电池电压测量

REFP0

REFN0

AVDD

DVDD

50 ꢀA to

1.5 mA

Internal

Reference

Mux

ADS1120-Q1

AIN0/REFP1

AIN1

CS

Digital Filter

and

SCLK

16-bit

ûꢁꢀADC

Mux

PGA

DIN

SPI

DOUT/DRDY

DRDY

Interface

AIN2

Low Drift

Oscillator

Precision

Temp Sensor

AIN3/REFN1

AVSS

CLK

DGND

1

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

English Data Sheet: SBAS683

ADS1120-Q1

ZHCSCV9A –AUGUST 2014–REVISED OCTOBER 2014

www.ti.com.cn

8.3 Feature Description................................................. 18

8.4 Device Functional Modes........................................ 30

8.5 Programming........................................................... 32

8.6 Register Map........................................................... 37

Application and Implementation ........................ 42

9.1 Application Information............................................ 42

9.2 Typical Application ................................................. 47

1

2

3

4

5

6

特性.......................................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

Pin Configurations and Functions....................... 3

Specifications......................................................... 4

6.1 Absolute Maximum Ratings ...................................... 4

6.2 Handling Ratings....................................................... 4

6.3 Recommended Operating Conditions....................... 5

6.4 Thermal Information.................................................. 5

6.5 Electrical Characteristics........................................... 6

6.6 SPI Timing Requirements ......................................... 8

6.7 SPI Switching Characteristics ................................... 8

6.8 Typical Characteristics.............................................. 9

Parameter Measurement Information ................ 15

7.1 Noise Performance ................................................. 15

Detailed Description ............................................ 17

8.1 Overview ................................................................. 17

8.2 Functional Block Diagram ....................................... 17

9

10 Power-Supply Recommendations ..................... 57

10.1 Power-Supply Sequencing.................................... 57

10.2 Power-Supply Decoupling..................................... 57

11 Layout................................................................... 58

11.1 Layout Guidelines ................................................. 58

11.2 Layout Example .................................................... 59

12 器件和文档支持 ..................................................... 60

12.1 文档支持................................................................ 60

12.2 商标....................................................................... 60

12.3 静电放电警告......................................................... 60

12.4 术语表 ................................................................... 60

13 机械封装和可订购信息 .......................................... 60

7

8

4 修订历史记录

Changes from Original (August 2013) to Revision A

Page

•

已更改产品预览数据表............................................................................................................................................................ 1

2

ADS1120-Q1

www.ti.com.cn

ZHCSCV9A –AUGUST 2014–REVISED OCTOBER 2014

5 Pin Configurations and Functions

PW Package

TSSOP-16

(Top View)

SCLK

CS

1

2

3

4

5

6

7

8

16 DIN

15 DOUT/DRDY

14 DRDY

CLK

DGND

13 DVDD

AVSS

12 AVDD

AIN3/REFN1

AIN2

11 AIN0/REFP1

10 AIN1

REFN0

9

REFP0

Pin Functions

NUMBER

NAME

TYPE

DESCRIPTION

1

SCLK

Digital input

Serial clock input

Chip select, active low.

Connect to DGND if not used.

2

3

CS

Digital input

External clock source pin.

Connect to DGND if not used.

CLK

4

5

DGND

AVSS

Digital

Digital ground

Analog

Negative analog power supply

Analog input 3, negative reference input 1.

6

AIN3/REFN1

Analog input

Internal low-side power switch connected between AIN3/REFN1 and AVSS.

Leave unconnected or tie to AVDD if not used.

Analog input 2.

Leave unconnected or tie to AVDD if not used.

7

8

AIN2

REFN0

Analog input

Negative reference input 0.

Leave unconnected or tie to AVDD if not used.

Positive reference input 0.

Leave unconnected or tie to AVDD if not used.

9

REFP0

Analog input 1.

Leave unconnected or tie to AVDD if not used.

10

11

AIN1

Analog input 0, positive reference input 1.

Leave unconnected or tie to AVDD if not used.

AIN0/REFP1

12

13

AVDD

DVDD

Analog

Digital

Positive analog power supply

Positive digital power supply

Data ready, active low.

Leave unconnected or tie to DVDD using a weak pull-up resistor if not used.

14

DRDY

Digital output

15

16

DOUT/DRDY

DIN

Digital output

Digital input

Serial data output combined with data ready, active low

Serial data input

3

ADS1120-Q1

ZHCSCV9A –AUGUST 2014–REVISED OCTOBER 2014

www.ti.com.cn

6 Specifications

6.1 Absolute Maximum Ratings⁽¹⁾

MIN

–0.3

MAX

UNIT

V

AVDD to AVSS

7

DVDD to DGND

–0.3

7

0.3

V

AVSS to DGND

–2.8

V

Analog input voltage

AVSS – 0.3

DGND – 0.3

–10

AVDD + 0.3

DVDD + 0.3

10

V

Digital input voltage

V

Input current, continuous, any terminal except power supply terminals

Junction temperature, T_J

mA

°C

–40

150

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 Handling Ratings

MIN

–60

MAX

150

UNIT

°C

T_stg

Storage temperature range

Electrostatic discharge

Human body model (HBM), per AEC Q100-002⁽¹⁾

–2000

2000

V

Corner pins

(1, 8, 9, and 16)

V_(ESD)

–750

–500

750

500

V

Charged device model (CDM), per

AEC Q100-011

Other pins

(1) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

4

ADS1120-Q1

www.ti.com.cn

ZHCSCV9A –AUGUST 2014–REVISED OCTOBER 2014

6.3 Recommended Operating Conditions

over operating ambient temperature range (unless otherwise noted)

MIN

NOM

MAX

UNIT

POWER SUPPLY

AVDD to AVSS

Unipolar analog power supply

2.3

–0.1

2.3

5.5

0.1

V

AVSS to DGND

0

2.5

AVDD to DGND

Bipolar analog power supply

2.75

–2.3

5.5

AVSS to DGND

–2.75

2.3

–2.5

Digital power supply

ANALOG INPUTS⁽¹⁾

DVDD to DGND

(2)

V_IN

Differential input voltage

V_IN= V_(AINP)– V_(AINN)

–V_ref/ Gain

AVSS – 0.1

V_ref/ Gain

V

PGA disabled, gain = 1 to 4

PGA enabled, gain = 1 to 128

PGA disabled, gain = 1 to 4

PGA enabled, gain = 1 to 128

AVDD + 0.1

V_(AINx)

Absolute input voltage

See the Low-Noise PGA section

AVSS – 0.1

See the Low-Noise PGA section

AVDD + 0.1

V

V_CM

Common-mode input voltage

VOLTAGE REFERENCE INPUTS⁽³⁾

V_ref

Differential reference input voltage

V_ref= V_(REFPx)– V_(REFNx)

0.75

AVSS – 0.1

2.5

AVDD

V_(REFPx)– 0.75

AVDD + 0.1

V

V_(REFNx)

V_(REFPx)

Absolute negative reference voltage

Absolute positive reference voltage

V_(REFNx)+ 0.75

EXTERNAL CLOCK SOURCE

f_(CLK)

External clock frequency

Duty cycle

0.5

4.096

4.5

MHz

40%

60%

DIGITAL INPUTS

Input voltage

TEMPERATURE RANGE

T_AOperating ambient temperature

DGND

DVDD

V

–40

125

°C

(1) AIN_Pand AIN_Ndenote the positive and negative inputs of the PGA. AINx denotes one of the four available analog inputs.

PGA disabled means the low-noise PGA is powered down and bypassed. Gains of 1, 2, and 4 are still possible in this case.

See the Bypassing the PGA section for more information.

(2) Excluding the effects of offset and gain error.

Limited to ±[(AVDD – AVSS) – 0.4 V] / Gain, when the PGA is enabled.

(3) REFPx and REFNx denote one of the two available differential reference input pairs.

6.4 Thermal Information

TSSOP (PW)

THERMAL METRIC⁽¹⁾

UNIT

16 PINS

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

99.5

35.2

44.3

2.4

R_θJC(top)

R_θJB

°C/W

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

ψ_JB

43.8

n/a

R_θJC(bot)

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

5

ADS1120-Q1

ZHCSCV9A –AUGUST 2014–REVISED OCTOBER 2014

www.ti.com.cn

6.5 Electrical Characteristics

Minimum and maximum specifications apply from T_A= –40°C to +125°C. Typical specifications are at T_A= 25°C.

All specifications are at AVDD = 3.3 V, AVSS = 0 V, DVDD = 3.3 V, PGA enabled, DR = 20 SPS, and external V_ref= 2.5 V

(unless otherwise noted).⁽¹⁾

PARAMETER

ANALOG INPUTS

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Absolute input current

Differential input current

See the Typical Characteristics

SYSTEM PERFORMANCE

Resolution (no missing codes)

Data rate

16

Bits

SPS

Normal mode

20, 45, 90, 175, 330, 600, 1000

DR

Duty-cycle mode

Turbo mode

5, 11.25, 22.5, 44, 82.5, 150, 250

40, 90, 180, 350, 660, 1200, 2000

Noise (input-referred)

Integral nonlinearity

See the Noise Performance section

Gain = 1, V_CM= 0.5 AVDD, best fit⁽²⁾

8

20

ppm

INL

V_IO

Gain = 2 to 128, V_CM= 0.5 AVDD, best fit

PGA disabled, gain = 1 to 4,

differential inputs

±4

µV

Input offset voltage

Gain = 1 to 128, differential inputs

PGA disabled, gain = 1 to 4

Gain = 1 to 128

±4

0.25

µV

µV/°C

Offset drift

Gain error

Gain drift

0.25

PGA disabled, gain = 1 to 4

Gain = 1 to 128, T_A= 25°C

PGA disabled, gain = 1 to 4

Gain = 1 to 128⁽²⁾

±0.015%

–0.1%

±0.015%

0.1%

5

1

ppm/°C

50 Hz ±3%, DR = 20 SPS, external CLK,

50/60 bit = 10

105

90

dB

60 Hz ±3%, DR = 20 SPS, external CLK,

50/60 bit = 11

NMRR Normal-mode rejection ratio⁽²⁾

CMRR Common-mode rejection ratio

50 Hz or 60 Hz ±3%, DR = 20 SPS,

external CLK, 50/60 bit = 01

At dc, gain = 1

90

80

90

105

115

105

115

dB

f_(CM)= 50 Hz, DR = 2000 SPS⁽²⁾

f_(CM)= 60 Hz, DR = 2000 SPS⁽²⁾

AVDD at dc, V_CM= 0.5 AVDD, gain = 1

DVDD at dc, V_CM= 0.5 AVDD, gain = 1⁽²⁾

PSRR

Power-supply rejection ratio

INTERNAL VOLTAGE REFERENCE

Initial accuracy

T_A= 25°C

2.045

2.048

5

2.051

40

V

Reference drift⁽²⁾

ppm/°C

ppm

Long-term drift

1000 hours

110

VOLTAGE REFERENCE INPUTS

Reference input current

INTERNAL OSCILLATOR

Internal oscillator accuracy

REFP0 = V_ref, REFN0 = AVSS

Normal mode

±10

nA

–2%

±1%

2%

(1) PGA disabled means the low-noise PGA is powered down and bypassed. Gains of 1, 2, and 4 are still possible in this case.

See the Bypassing the PGA section for more information.

(2) Minimum and maximum values are ensured by design and characterization data.

6

ADS1120-Q1

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ZHCSCV9A –AUGUST 2014–REVISED OCTOBER 2014

Electrical Characteristics (continued)

Minimum and maximum specifications apply from T_A= –40°C to +125°C. Typical specifications are at T_A= 25°C.

All specifications are at AVDD = 3.3 V, AVSS = 0 V, DVDD = 3.3 V, PGA enabled, DR = 20 SPS, and external V_ref= 2.5 V

(unless otherwise noted).⁽¹⁾

PARAMETER

EXCITATION CURRENT SOURCES (IDACs)

Current settings

TEST CONDITIONS

MIN

TYP

MAX

UNIT

50, 100, 250, 500, 1000, 1500

µA

V

Compliance voltage

All current settings

AVDD – 0.9

6%

Accuracy

All current settings, each IDAC

Between IDACs

–6%

±1%

±0.3%

50

Current match

Temperature drift

Each IDAC

ppm/°C

Temperature drift matching

TEMPERATURE SENSOR

Between IDACs

10

Conversion resolution

Temperature resolution

T_A= 0°C to +75°C

14

0.03125

±0.25

Bits

°C

Temperature sensor resolution

°C

T_A= –40°C to +125°C

±0.5

°C

Temperature sensor accuracy

Temperature sensor accuracy vs analog

supply voltage

0.0625

3.5

0.25

30

°C/V

LOW-SIDE POWER SWITCH

R_ON

On-resistance

Ω

Current through switch

mA

DIGITAL INPUT/OUTPUT

V_IH

V_IL

V_OH

V_OL

I_H

High-level input voltage

0.7 DVDD

DGND

DVDD

V

Low-level input voltage

High-level output voltage

Low-level output voltage

Input leakage, high

0.3 DVDD

I_OH= 3 mA

I_OL= 3 mA

V_IH= 5.5 V

V_IL= DGND

0.8 DVDD

V

0.2 DVDD

V

–10

10

µA

I_L

Input leakage, low

POWER-SUPPLY

Power-down mode

0.1

65

3

µA

Duty-cycle mode, PGA disabled

Normal mode, PGA disabled

Normal mode, gain = 1 to 16

Normal mode, gain = 32

Normal mode, gain = 64, 128

Turbo mode, gain = 1 to 16

Power-down mode

240

340

425

510

540

0.3

55

µA

I_AVDD

Analog supply current⁽³⁾

490

µA

5

µA

Duty-cycle mode

µA

I_DVDD

Digital supply current⁽³⁾

Power dissipation⁽³⁾

Normal mode

75

110

µA

Turbo mode

95

µA

Duty-cycle mode, PGA disabled

Normal mode, gain = 1 to 16

Turbo mode, gain = 1 to 16

0.4

1.4

2.1

mW

P_D

(3) Internal voltage reference selected, internal oscillator enabled, both IDACs turned off.

7

ADS1120-Q1

ZHCSCV9A –AUGUST 2014–REVISED OCTOBER 2014

www.ti.com.cn

6.6 SPI Timing Requirements

over operating ambient temperature range, DVDD = 2.3 V to 5.5 V (unless otherwise noted)

MIN

50

MAX

UNIT

ns

t_d(CSSC)

t_d(SCCS)

t_w(CSH)

t_c(SC)

Delay time, CS falling edge to first SCLK rising edge

Delay time, final SCLK falling edge to CS rising edge

Pulse duration, CS high

SCLK period⁽¹⁾

Pulse duration, SCLK high⁽¹⁾

25

ns

50

ns

150

60

ns

t_w(SCH)

t_w(SCL)

t_su(DI)

ns

Pulse duration, SCLK low⁽¹⁾

60

ns

Setup time, DIN valid before SCLK falling edge

Hold time, DIN valid after SCLK falling edge

50

ns

t_h(DI)

25

ns

(1) If a complete command is not sent within 13955 · t_(MOD)(normal mode, duty-cycle mode) or 27910 · t_(MOD)(turbo mode), the serial

interface resets and the next SCLK pulse starts a new communication cycle.

t_(MOD)= 1 / f_(MOD). Modulator frequency (f_(MOD)) is 256 kHz in normal and duty-cycle mode and 512 kHz in turbo mode, when using the

internal oscillator or an external 4.096-MHz clock.

t_w(CSH)

CS

tt_d(CSSC)

t

tt_c(SC)

t

t_w(SCH)

tt_d(SCCS)t

SCLK

t_su(DI)

t_h(DI)

t_w(SCL)

DIN

NOTE: Single-byte communication is shown. Actual communication may be multiple bytes.

Figure 1. Serial Interface Timing Requirements

6.7 SPI Switching Characteristics

over operating ambient temperature range, DVDD = 2.3 V to 5.5 V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Propagation delay time,

CS falling edge to DOUT driven

t_p(CSDO)

t_p(SCDO)

t_p(CSDOZ)

DOUT load = 20 pF || 10 kΩ to DGND

50

ns

Propagation delay time,

SCLK rising edge to valid new DOUT

DOUT load = 20 pF || 10 kΩ to DGND

0

50

ns

Propagation delay time,

CS rising edge to DOUT high impedance

CS

SCLK

t_p(CSDO)

t_p(SCDO)

t_p(CSDOZ)

Hi-Z

DOUT/DRDY

NOTE: Single-byte communication is shown. Actual communication may be multiple bytes.

Figure 2. Serial Interface Switching Characteristics

8

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ZHCSCV9A –AUGUST 2014–REVISED OCTOBER 2014

6.8 Typical Characteristics

At T_A= 25°C, AVDD = 3.3 V, AVSS = 0 V, and PGA enabled using external V_ref= 2.5 V (unless otherwise noted).

40

30

20

10

0

40

30

20

10

0

Gain = 1

Gain = 128

PGA Disabled

Gain = 128

PGA Disabled

±10

0

20

40

60

80

100

120

0

20

40

60

80

100

120

±40

±20

±40

±20

C017

C018

Temperature (C)

AVDD = 3.3 V

AVDD = 5.0 V

Figure 3. Input-Referred Offset Voltage vs Temperature

Figure 4. Input-Referred Offset Voltage vs Temperature

500

Gain = 1

Gain = 128

400

PGA Disabled

300

200

100

0

300

200

100

0

20

40

60

80

100

120

0

20

40

60

80

100

120

±40

±20

±40

±20

C019

C020

Temperature (C)

AVDD = 3.3 V

AVDD = 5.0 V

Figure 5. Gain Error vs Temperature

Figure 6. Gain Error vs Temperature

15

10

5

15

10

5

Gain = 1

Gain = 32

PGA Disabled

Gain = 1

Gain = 32

PGA Disabled

0

±5

±10

±15

±5

±10

±15

0

25

50

75

100

0

25

50

75

100

±100 ±75

±50

±25

±100 ±75

±50

±25

C025

C029

V_IN(% of FS)

AVDD = 3.3 V, external 2.5-V reference, normal mode

AVDD = 5.0 V, external 2.5-V reference, normal mode

Figure 7. Integral Nonlinearity vs

Differential Input Signal

Figure 8. Integral Nonlinearity vs

Differential Input Signal

9

ADS1120-Q1

ZHCSCV9A –AUGUST 2014–REVISED OCTOBER 2014

www.ti.com.cn

Typical Characteristics (continued)

At T_A= 25°C, AVDD = 3.3 V, AVSS = 0 V, and PGA enabled using external V_ref= 2.5 V (unless otherwise noted).

20

Gain = 1

Gain = 32

15

PGA Disabled

10

5

0

±5

±10

±15

±20

±10

±15

±20

0

25

50

75

100

0

25

50

75

100

±100 ±75

±50

±25

±100 ±75

±50

±25

C043

C044

V_IN(% of FS)

AVDD = 3.3 V, internal reference, normal mode

AVDD = 5.0 V, internal reference, normal mode

Figure 9. Integral Nonlinearity vs

Differential Input Signal

Figure 10. Integral Nonlinearity vs

Differential Input Signal

1000

2.051

2.050

2.049

2.048

2.047

2.046

2.045

AVDD = 3.3 V

AVDD = 5.0 V

800

600

400

200

0

20

40

60

80

100

120

±40

±20

Initial Reference Voltage (V)

C042

C021

Temperature (C)

T_A= 25°C, data from 5490 devices

Figure 12. Internal Reference Voltage vs Temperature

Figure 11. Internal Reference Voltage Histogram

0

1.00

0.75

Gain = 1

±20

Gain = 128

0.50

±40

±60

±80

0.25

0.00

±0.25

±0.50

±0.75

±1.00

±100

±120

±140

±160

0

20

40

60

80

100

120

0.1

1

10

100

1000

±40

±20

C002

C016

Temperature (C)

Frequency (kHz)

DVDD = 3.3 V, normal mode

Figure 13. Internal Oscillator Accuracy vs Temperature

Figure 14. AVDD Power-Supply Rejection Ratio vs

Frequency

10

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ZHCSCV9A –AUGUST 2014–REVISED OCTOBER 2014

Typical Characteristics (continued)

At T_A= 25°C, AVDD = 3.3 V, AVSS = 0 V, and PGA enabled using external V_ref= 2.5 V (unless otherwise noted).

15

10

5

15

10

5

AIN0

AIN1

AIN2

AIN3

AIN0

AIN1

AIN2

AIN3

0

±5

±10

±15

±5

±10

±15

0.5

1.0

1.5

2.0

2.5

3.0

0.5

1.0

1.5

2.0

2.5

3.0

C030

C031

Absolute Input Voltage V_(AINx)(V)

AVDD = 3.3 V, PGA enabled, T_A= –40°C

AVDD = 3.3 V, PGA enabled, T_A= 25°C

Figure 15. Absolute Input Current vs

Absolute Input Voltage

Figure 16. Absolute Input Current vs

Absolute Input Voltage

20

10

100

50

AIN0

AIN1

AIN2

AIN3

AIN0

AIN1

AIN2

AIN3

0

±10

±20

±30

±40

±50

±100

±150

±200

±250

0.5

1.0

1.5

2.0

2.5

3.0

0.5

1.0

1.5

2.0

2.5

3.0

C032

C033

Absolute Input Voltage V_(AINx)(V)

AVDD = 3.3 V, PGA enabled, T_A= 85°C

AVDD = 3.3 V, PGA enabled, T_A= 125°C

Figure 17. Absolute Input Current vs

Absolute Input Voltage

Figure 18. Absolute Input Current vs

Absolute Input Voltage

40

20

40

20

Ta = ±40C

Ta = 25°C

Ta = 85°C

Ta = 125°C

Ta = ±40C

Ta = 25°C

Ta = 85°C

Ta = 125°C

0

±20

±40

±60

±20

±40

±60

0.0

0.5

1.0

1.5

2.0

0.0

0.5

1.0

1.5

2.0

±2.0 ±1.5 ±1.0 ±0.5

C038

C039

Differential Input Voltage V_IN(V)

AVDD = 3.3 V, PGA enabled, AIN_P= AIN0, AIN_N= AIN1

AVDD = 3.3 V, PGA enabled, AIN_P= AIN3, AIN_N= AIN2

Figure 19. Differential Input Current vs

Differential Input Voltage

Figure 20. Differential Input Current vs

Differential Input Voltage

11

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www.ti.com.cn

Typical Characteristics (continued)

At T_A= 25°C, AVDD = 3.3 V, AVSS = 0 V, and PGA enabled using external V_ref= 2.5 V (unless otherwise noted).

15

10

5

15

10

5

AIN0

AIN1

AIN2

AIN3

AIN0

AIN1

AIN2

AIN3

0

±5

±10

±15

±5

±10

±15

0.5

1.0

1.5

2.0

2.5

3.0

0.5

1.0

1.5

2.0

2.5

3.0

C034

C035

Absolute Input Voltage V_(AINx)(V)

AVDD = 3.3 V, PGA disabled, T_A= –40°C

AVDD = 3.3 V, PGA disabled, T_A= 25°C

Figure 21. Absolute Input Current vs

Absolute Input Voltage

Figure 22. Absolute Input Current vs

Absolute Input Voltage

20

10

100

50

AIN0

AIN1

AIN2

AIN3

AIN0

AIN1

AIN2

AIN3

0

±10

±20

±30

±40

±50

±100

±150

±200

±250

0.5

1.0

1.5

2.0

2.5

3.0

0.5

1.0

1.5

2.0

2.5

3.0

C036

C037

Absolute Input Voltage V_(AINx)(V)

AVDD = 3.3 V, PGA disabled, T_A= 85°C

AVDD = 3.3 V, PGA disabled, T_A= 125°C

Figure 23. Absolute Input Current vs

Absolute Input Voltage

Figure 24. Absolute Input Current vs

Absolute Input Voltage

40

20

40

20

Ta = ±40C

Ta = 25°C

Ta = 85°C

Ta = 125°C

Ta = ±40C

Ta = 25°C

Ta = 85°C

Ta = 125°C

0

±20

±40

±60

±20

±40

±60

0.0

0.5

1.0

1.5

2.0

0.0

0.5

1.0

1.5

2.0

±2.0 ±1.5 ±1.0 ±0.5

C040

C041

Differential Input Voltage V_IN(V)

AVDD = 3.3 V, PGA disabled, AIN_P= AIN0, AIN_N= AIN1

AVDD = 3.3 V, PGA disabled, AIN_P= AIN3, AIN_N= AIN2

Figure 25. Differential Input Current vs

Differential Input Voltage

Figure 26. Differential Input Current vs

Differential Input Voltage

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Typical Characteristics (continued)

At T_A= 25°C, AVDD = 3.3 V, AVSS = 0 V, and PGA enabled using external V_ref= 2.5 V (unless otherwise noted).

6

IDAC = 1000 µA

IDAC = 500 µA

IDAC = 100 µA

4

2

0

±2

±4

±6

±2

±4

±6

0

20

40

60

80

100

120

0.5

0.6

0.7

0.8

0.9

1.0

±40

±20

C005

C006

Temperature (C)

Compliance Voltage (V)

Figure 27. IDAC Accuracy vs Compliance Voltage

Figure 28. IDAC Accuracy vs Temperature

600

500

400

300

200

100

0

1.00

IDAC = 1000 µA

IDAC = 500 µA

IDAC = 100 µA

0.75

0.50

0.25

0.00

±0.25

±0.50

±0.75

±1.00

Gain = 64, 128

Gain = 1 to 16

PGA Disabled

0

20

40

60

80

100

120

0

20

40

60

80

100

120

±40

±20

±40

±20

C007

C011

Temperature (C)

AVDD = 3.3 V, internal reference, normal mode

Figure 29. IDAC Matching vs Temperature

Figure 30. I_AVDDvs Temperature

1000

800

600

400

200

0

150

125

100

75

50

25

0

Gain = 64, 128

Gain = 1 to 16

PGA Disabled

Gain = 1 to 16

PGA Disabled

0

20

40

60

80

100

120

0

20

40

60

80

100

120

±40

±20

±40

±20

C012

C013

Temperature (C)

AVDD = 3.3 V, internal reference, turbo mode

AVDD = 3.3 V, internal reference, duty-cycle mode

Figure 31. I_AVDDvs Temperature

Figure 32. I_AVDDvs Temperature

13

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www.ti.com.cn

Typical Characteristics (continued)

At T_A= 25°C, AVDD = 3.3 V, AVSS = 0 V, and PGA enabled using external V_ref= 2.5 V (unless otherwise noted).

120

100

80

60

40

20

0

600

500

400

300

200

100

0

Gain = 64, 128

Gain = 1 to 16

PGA Disabled

Turbo Mode

Normal Mode

Duty-Cycle Mode

2.5

3.0

3.5

4.0

4.5

5.0

5.5

2.5

3.0

3.5

4.0

4.5

5.0

5.5

C004

C010

AVDD (V)

DVDD (V)

Normal mode, internal reference

Figure 33. I_AVDDvs AVDD

Figure 34. I_DVDDvs DVDD

120

100

80

60

40

20

0

1.00

0.75

Mean + 61

Mean

Mean - 61

0.50

0.25

0.00

±0.25

±0.50

±0.75

±1.00

Turbo Mode

Normal Mode

Duty-Cycle Mode

0

20

40

60

80

100

120

0

20

40

60

80

100

120

±40

±20

±40

±20

C014

C015

Temperature (C)

DVDD = 3.3 V

Figure 35. I_DVDDvs Temperature

Figure 36. Internal Temperature Sensor Accuracy vs

Temperature

6

5

4

3

2

1

0

AVDD = 2.3 V

AVDD = 3.3 V

AVDD = 5.0 V

0

20

40

60

80

100

120

±40

±20

C001

Temperature (C)

Figure 37. Low-Side Power Switch R_ONvs Temperature

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ZHCSCV9A –AUGUST 2014–REVISED OCTOBER 2014

7 Parameter Measurement Information

7.1 Noise Performance

Delta-sigma (ΔΣ) analog-to-digital converters (ADCs) are based on the principle of oversampling. The input

signal of a ΔΣ ADC is sampled at a high frequency (modulator frequency) and subsequently filtered and

decimated in the digital domain to yield a conversion result at the respective output data rate. The ratio between

modulator frequency and output data rate is called oversampling ratio (OSR). By increasing the OSR, and thus

reducing the output data rate, the noise performance of the ADC can be optimized. In other words, the input-

referred noise drops when reducing the output data rate because more samples of the internal modulator are

averaged to yield one conversion result. Increasing the gain also reduces the input-referred noise, which is

particularly useful when measuring low-level signals.

Table 1 to Table 4 summarize the device noise performance. Data are representative of typical noise

performance at T_A= 25°C using the internal 2.048-V reference. Data shown are the result of averaging readings

from a single device over a time period of approximately 0.75 seconds and are measured with the inputs

internally shorted together. Table 1 and Table 3 list the input-referred noise in units of μV_RMSfor the conditions

shown. Note that µV_PPvalues are shown in parenthesis. Table 2 and Table 4 list the corresponding data in

effective number of bits (ENOB) calculated from μV_RMSvalues using Equation 1. Note that noise-free bits

calculated from peak-to-peak noise values are shown in parenthesis.

The input-referred noise (Table 1 and Table 3) only changes marginally when using an external low-noise

reference, such as the REF5020A-Q1. To calculate ENOB numbers and noise-free bits when using a reference

voltage other than 2.048 V, use Equation 1 to Equation 3:

ENOB = ln (Full-Scale Range / V_RMS-Noise) / ln(2)

Noise-Free Bits = ln (Full-Scale Range / V_PP-Noise) / ln(2)

Full-Scale Range = 2 · V_ref/ Gain

(1)

(2)

(3)

Table 1. Noise in μV_RMS(μV_PP

)

at AVDD = 3.3 V, AVSS = 0 V, and Internal Reference = 2.048 V

DATA

RATE

(SPS)

GAIN (PGA ENABLED)

1

2

4

8

16

32

64

128

20

45

62.50 (62.50)

62.50 (63.72)

31.25 (31.25)

31.25 (34.06)

15.63 (15.63)

15.63 (17.76)

15.63 (26.25)

15.63 (39.43)

7.81 (7.81)

7.81 (11.20)

7.81 (14.13)

7.81 (19.26)

7.81 (31.52)

7.81 (37.02)

3.91 (3.91)

3.91 (5.13)

3.91 (7.52)

3.91 (12.77)

3.91 (18.08)

3.91 (18.89)

1.95 (1.95)

1.95 (2.14)

1.95 (3.09)

1.95 (4.66)

1.95 (6.87)

1.95 (10.71)

1.95 (12.00)

0.98 (0.98)

0.98 (1.22)

0.98 (2.14)

0.98 (2.69)

0.98 (4.76)

1.03 (6.52)

1.13 (7.60)

0.49 (0.49)

0.49 (0.51)

0.49 (0.85)

0.49 (1.60)

0.49 (1.99)

0.55 (3.34)

0.70 (4.01)

0.82 (5.81)

90

175

330

600

1000

2000

62.50 (106.93) 31.25 (50.78)

62.50 (151.61) 31.25 (72.27)

62.50 (227.29) 31.25 (122.68) 15.63 (58.53)

62.50 (265.14) 31.25 (127.32) 15.63 (65.43)

Table 2. ENOB from RMS Noise (Noise-free Bits from Peak-to-Peak Noise)

at AVDD = 3.3 V, AVSS = 0 V, and Internal Reference = 2.048 V

DATA

RATE

(SPS)

GAIN (PGA ENABLED)

1

2

4

8

16

32

64

128

20

45

16 (16)

16 (15.49)

16 (15.20)

16 (14.29)

16 (13.97)

15.83 (13.23)

90

16 (16)

16 (15.87)

16 (15.34)

16 (14.74)

16 (14.18)

16 (13.54)

16 (13.38)

16 (15.67)

16 (14.87)

16 (14.54)

16 (13.72)

175

330

600

1000

2000

16 (15.97)

16 (15.23)

16 (14.72)

16 (14.14)

16 (13.92)

16 (15.88)

16 (15.30)

16 (14.79)

16 (14.03)

16 (13.97)

16 (15.82)

16 (15.25)

16 (14.66)

16 (14.09)

16 (13.93)

16 (15.48)

16 (15.15)

16 (14.70)

16 (13.99)

16 (13.76)

16 (15.61)

16 (15.05)

16 (14.29)

16 (13.79)

16 (13.73)

15.92 (13.26) 15.49 (12.96)

15.79 (13.04) 15.25 (12.43)

15

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Table 3. Noise in μV_RMS(μV_PP) with PGA Disabled

at AVDD = 3.3 V, AVSS = 0 V, and Internal Reference = 2.048 V

GAIN (PGA DISABLED)

DATA RATE

(SPS)

1

2

4

20

45

62.50 (62.50)

62.50 (65.92)

62.50 (94.24)

62.50 (138.67)

62.50 (260.50)

62.50 (250.98)

31.25 (31.25)

31.25 (35.40)

31.25 (50.17)

31.25 (78.13)

31.25 (120.97)

31.25 (131.35)

15.63 (15.63)

15.63 (18.92)

15.63 (28.75)

15.63 (39.79)

15.63 (63.72)

15.63 (68.18)

90

175

330

600

1000

2000

Table 4. ENOB from RMS Noise (Noise-free Bits from Peak-to-Peak Noise) with PGA Disabled

at AVDD = 3.3 V, AVSS = 0 V, and Internal Reference = 2.048 V

GAIN (PGA DISABLED)

DATA RATE

(SPS)

20

1

2

4

16 (16)

45

16 (16)

90

16 (16)

175

330

600

1000

2000

16 (15.92)

16 (15.41)

16 (14.85)

16 (13.94)

16 (13.99)

16 (15.82)

16 (15.32)

16 (14.68)

16 (14.05)

16 (13.93)

16 (15.72)

16 (15.12)

16 (14.65)

16 (13.97)

16 (13.87)

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8 Detailed Description

8.1 Overview

The ADS1120-Q1 is a small, low-power, 16-bit, ΔΣ ADC that offers many integrated features to reduce system

cost and component count in applications measuring small sensor signals.

In addition to the ΔΣ ADC core and single-cycle settling digital filter, the device offers a low-noise, high input

impedance, programmable gain amplifier (PGA), an internal voltage reference, and a clock oscillator. The device

also integrates a highly linear and accurate temperature sensor as well as two matched programmable current

sources (IDACs) for sensor excitation. All of these features are intended to reduce the required external circuitry

in typical sensor applications and improve overall system performance. An additional low-side power switch

eases the design of low-power bridge sensor applications. The device is fully configured through four registers

and controlled by six commands through a mode 1 SPI-compatible interface. The Functional Block Diagram

section shows the device functional block diagram.

The ADS1120-Q1 ADC measures a differential signal, V_IN, which is the difference in voltage between nodes AIN_P

and AIN_N. The converter core consists of a differential, switched-capacitor, ΔΣ modulator followed by a digital

filter. The digital filter receives a high-speed bitstream from the modulator and outputs a code proportional to the

input voltage. This architecture results in a very strong attenuation of any common-mode signal.

The device has two available conversion modes: single-shot and continuous conversion mode. In single-shot

mode, the ADC performs one conversion of the input signal upon request and stores the value in an internal data

buffer. The device then enters a low-power state to save power. Single-shot mode is intended to provide

significant power savings in systems that require only periodic conversions, or when there are long idle periods

between conversions. In continuous conversion mode, the ADC automatically begins a conversion of the input

signal as soon as the previous conversion is completed. New data are available at the programmed data rate.

Data can be read at any time without concern of data corruption and always reflect the most recently completed

conversion.

8.2 Functional Block Diagram

REFP0

REFN0

AVDD

DVDD

50 ꢀA to

1.5 mA

Internal

Reference

Device

AIN0/REFP1

AIN1

Mux

CS

AIN_P

AIN_N

Digital Filter

and

SPI

Interface

SCLK

16-bit

ûꢁꢀADC

Mux

PGA

DIN

DOUT/DRDY

DRDY

AIN2

Low Drift

Oscillator

Precision

Temp Sensor

AIN3/REFN1

AVSS

CLK

DGND

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www.ti.com.cn

8.3 Feature Description

8.3.1 Multiplexer

The device contains a very flexible input multiplexer, as shown in Figure 38. Either four single-ended signals, two

differential signals, or a combination of two single-ended signals and one differential signal can be measured.

The multiplexer is configured by four bits (MUX[3:0]) in the configuration register. When single-ended signals are

measured, the negative ADC input (AIN_N) is internally connected to AVSS by a switch within the multiplexer. For

system-monitoring purposes, the analog supply (AVDD – AVSS) / 4 or the currently-selected external reference

voltage (V_(REFPx)– V_(REFNx)) / 4 can be selected as inputs to the ADC. The multiplexer also offers the possibility to

route any of the two programmable current sources to any analog input (AINx) or to any dedicated reference pin

(REFP0, REFN0).

System Monitors

(V_(REFPx)± V_(REFNx)) / 4

(AVDD ± AVSS) / 4

AVDD

IDAC1

AVDD

IDAC2

(AVDD + AVSS) / 2

AVDD

AVSS

AIN0/REFP1

AIN1

AVDD

Burnout Current Source (10 µA)

AIN2

AIN_P

PGA

To ADC

AIN_N

AIN3/REFN1

REFP0

Burnout Current Source (10 µA)

AVSS

REFN0

Figure 38. Analog Input Multiplexer

Electrostatic discharge (ESD) diodes to AVDD and AVSS protect the inputs. To prevent the ESD diodes from

turning on, the absolute voltage on any input must stay within the range provided by Equation 4:

AVSS – 0.3 V < V_(AINx)< AVDD + 0.3 V

(4)

If the voltages on the input pins have any potential to violate these conditions, external Schottky clamp diodes or

series resistors may be required to limit the input current to safe values (see the Absolute Maximum Ratings

table). Overdriving an unused input on the device may affect conversions taking place on other input pins. If any

overdrive on unused inputs is possible, TI recommends clamping the signal with external Schottky diodes.

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ZHCSCV9A –AUGUST 2014–REVISED OCTOBER 2014

Feature Description (continued)

8.3.2 Low-Noise PGA

The device features a low-noise, low-drift, high input impedance, programmable gain amplifier (PGA). The PGA

can be set to gains of 1, 2, 4, 8, 16, 32, 64, or 128. Three bits (GAIN[2:0]) in the configuration register are used

to configure the gain. A simplified diagram of the PGA is shown in Figure 39. The PGA consists of two chopper-

stabilized amplifiers (A1 and A2) and a resistor feedback network that sets the PGA gain. The PGA input is

equipped with an electromagnetic interference (EMI) filter.

200 O

+

-

AIN_P

25 pF

A1

R_F

OUT_P

OUT_N

V_OUT= Gain·V_IN

V_IN

R_G

R_F

-

A2

200 O

+

AIN_N

25 pF

Figure 39. Simplified PGA Diagram

V_INdenotes the differential input voltage V_IN= (V_(AINP)– V_(AINN)). The gain of the PGA can be calculated with

Equation 5:

Gain = 1 + 2 · R_F/ R_G

(5)

Gain is changed inside the device using a variable resistor, R_G. The differential full-scale input voltage range

(FSR) of the PGA is defined by the gain setting and the reference voltage used, as shown in Equation 6:

FSR = ±V_ref/ Gain

(6)

Table 5 shows the corresponding full-scale ranges when using the internal 2.048-V reference.

Table 5. PGA Full-Scale Range

GAIN SETTING

FSR

1

2

±2.048 V

±1.024 V

±0.512 V

±0.256 V

±0.128 V

±0.064 V

±0.032 V

±0.016 V

4

8

16

32

64

128

19

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8.3.2.1 PGA Common-Mode Voltage Requirements

To stay within the linear operating range of the PGA, the input signals must meet certain requirements that are

discussed in this section.

The outputs of both amplifiers (A1 and A2) in Figure 39 can not swing closer to the supplies (AVSS and AVDD)

than 200 mV. If the outputs OUT_Pand OUT_Nare driven to within 200 mV of the supply rails, the amplifiers

saturate and consequently become nonlinear. To prevent this nonlinear operating condition the output voltages

must meet Equation 7:

AVSS + 0.2 V ≤ V_(OUTN), V_(OUTP)≤ AVDD – 0.2 V

(7)

Translating the requirements of Equation 7 into requirements referred to the PGA inputs (AIN_Pand AIN_N) is

beneficial because there is no direct access to the outputs of the PGA. The PGA employs a symmetrical design,

therefore the common-mode voltage at the output of the PGA can be assumed to be the same as the common-

mode voltage of the input signal, as shown in Figure 40.

+

AIN_P

A1

-

½ V_IN

R_F

OUT_P

½ Gain·V_IN

V_CM= ½ (V_(AINP)+ V_(AINN)

)

R_G

½ Gain·V_IN

OUT_N

R_F

½ V_IN

-

A2

+

AIN_N

Figure 40. PGA Common-Mode Voltage

The common-mode voltage is calculated using Equation 8:

V_CM= ½ (V_(AINP)+ V_(AINN)) = ½ (V_(OUTP)+ V_(OUTN)

)

(8)

The voltages at the PGA inputs (AIN_Pand AIN_N) can be expressed as Equation 9 and Equation 10:

V_(AINP)= V_CM+ ½ V_IN

V_(AINN)= V_CM– ½ V_IN

(9)

(10)

The output voltages (V_(OUTP)and V_(OUTN)) can then be calculated as Equation 11 and Equation 12:

V_(OUTP)= V_CM+ ½ Gain · V_IN

V_(OUTN)= V_CM– ½ Gain · V_IN

(11)

(12)

The requirements for the output voltages of amplifiers A1 and A2 (Equation 7) can now be translated into

requirements for the input common-mode voltage range using Equation 11 and Equation 12, which are given in

Equation 13 and Equation 14:

V

_{CM (MIN)}≥ AVSS + 0.2 V + ½ Gain · V_{IN (MAX)}

_{CM (MAX)}≤ AVDD – 0.2 V – ½ Gain · V_{IN (MAX)}

(13)

(14)

V

In order to calculate the minimum and maximum common-mode voltage limits, the maximum differential input

voltage (V_{IN (MAX)}) that occurs in the application must be used. V_{IN (MAX)}can be less than the maximum possible

FS value.

In addition to Equation 13, the minimum V_CMmust also meet Equation 15 because of the specific design

implementation of the PGA.

V_{CM (MIN)}≥ AVSS + ¼ (AVDD – AVSS)

(15)

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Figure 41 and Figure 42 show a graphical representation of the common-mode voltage limits for AVDD = 3.3 V

and AVSS = 0 V, with gain = 1 and gain = 16, respectively.

3.30

2.75

2.20

1.65

1.10

0.55

0.00

3.30

2.75

2.20

1.65

1.10

0.55

0.00

AVDD / 4

0.0

0.5

1.0

1.5

2.0

2.5

3.0

0.00

0.03

0.06

0.09

0.12

0.15

0.18

C009

C008

V_IN(V)

AVDD = 3.3 V

Figure 41. Common-Mode Voltage Limits (Gain = 1)

Figure 42. Common-Mode Voltage Limits (Gain = 16)

The following discussion explains how to apply Equation 13 through Equation 15 to a hypothetical application.

The setup for this example is AVDD = 3.3 V, AVSS = 0 V, and gain = 16, using an external reference,

V_ref= 2.5 V. The maximum possible differential input voltage V_IN= (V_(AINP)– V_(AINN)) that can be applied is then

limited to the full-scale range of FSR = ±2.5 V / 16 = ±0.156 V. Consequently, Equation 13 through Equation 15

yield an allowed V_CMrange of 1.45 V ≤ V_CM≤ 1.85 V.

If the sensor signal connected to the inputs in this hypothetical application does not make use of the entire full-

scale range but is limited to V_{IN (MAX)}= ±0.1 V, for example, then this reduced input signal amplitude relaxes the

V_CMrestriction to 1.0 V ≤ V_CM≤ 2.3 V.

In the case of a fully-differential sensor signal, each input (AIN_P, AIN_N) can swing up to ±50 mV around the

common-mode voltage (V_(AINP)+ V_(AINN)) / 2, which must remain between the limits of 1.0 V and 2.3 V. The

output of a symmetrical wheatstone bridge is an example of a fully-differential signal. Figure 43 shows a situation

where the common-mode voltage of the input signal is at the lowest limit. V_(OUTN)is exactly at 0.2 V in this case.

Any further decrease in common-mode voltage (V_CM) or increase in differential input voltage (V_IN) drives V_(OUTN)

below 0.2 V and saturates amplifier A2.

+

-

V_(AINP)= 1.05 V

A1

50 mV

R_F

V_(OUTP)= 1.8 V

800 mV

V_CM= 1.0 V

R_F/7.5

800 mV

R_F

V_(OUTN)= 0.2 V

50 mV

-

A2

+

V_(AINN)= 0.95 V

Figure 43. Example where V_CMis at Lowest Limit

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In contrast, the signal of an RTD is of a pseudo-differential nature (if implemented as shown in the RTD

Measurement section), where the negative input is held at a constant voltage other than 0 V and only the voltage

on the positive input changes. When a pseudo-differential signal must be measured, the negative input in this

example must be biased at a voltage between 0.95 V and 2.25 V. The positive input can then swing up to

V_{IN (MAX)}= 100 mV above the negative input. Note that in this case the common-mode voltage changes at the

same time the voltage on the positive input changes. That is, while the input signal swings between 0 V ≤ V_IN

≤

V_{IN (MAX)}, the common-mode voltage swings between V_(AINN)≤ V_CM≤ V_(AINN)+ ½ V_{IN (MAX)}. Satisfying the

common-mode voltage requirements for the maximum input voltage V_{IN (MAX)}ensures the requirements are met

throughout the entire signal range.

Figure 44 and Figure 45 show examples of both fully-differential and pseudo-differential signals, respectively.

AIN_P

AIN_N

V_CM

100 mV

V_CM

1.0 V

0 V

100 mV

1.0 V

0 V

AIN_N

Figure 44. Fully-Differential Input Signal

Figure 45. Pseudo-Differential Input Signal

NOTE

Remember, common-mode voltage requirements with PGA enabled (Equation 13 to

Equation 15) are as follows:

•

V

_{CM (MIN)}≥ AVSS + ¼ (AVDD – AVSS)

_{CM (MIN)}≥ AVSS + 0.2 V + ½ Gain · V_{IN (MAX)}

_{CM (MAX)}≤ AVDD – 0.2 V – ½ Gain · V_{IN (MAX)}

8.3.2.2 Bypassing the PGA

At gains of 1, 2, and 4, the device can be configured to disable and bypass the low-noise PGA. Disabling the

PGA lowers the overall power consumption and also removes the restrictions of Equation 13 through

Equation 15 for the common-mode input voltage range, V_CM. The usable absolute and common-mode input

voltage range is (AVSS – 0.1 V ≤ V_(AINx), V_CM≤ AVDD + 0.1 V) when the PGA is disabled. In order to measure

single-ended signals that are referenced to AVSS (AIN_P= V_IN, AIN_N= AVSS), the PGA must be bypassed.

The PGA is disabled by setting the PGA_BYPASS bit in the configuration register. When the PGA is disabled,

the device uses a buffered switched-capacitor stage to obtain gains 1, 2, and 4. An internal buffer in front of the

switched-capacitor stage ensures that the effect on the input loading resulting from the capacitor charging and

discharging is minimal. Refer to Figure 21 to Figure 26 for the typical values of absolute input currents (current

flowing into or out of each input) and differential input currents (difference in absolute current between positive

and negative input) when the PGA is disabled.

For signal sources with high output impedance, external buffering may still be necessary. Note that active buffers

introduce noise and also introduce offset and gain errors. Consider all of these factors in high-accuracy

applications.

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8.3.3 Modulator

A ΔΣ modulator is used in the ADS1120-Q1 to convert the analog input voltage into a pulse code modulated

(PCM) data stream. The modulator runs at a modulator clock frequency of f_(MOD)= f_(CLK)/ 16 in normal and duty-

cycle mode and f_(MOD)= f_(CLK)/ 8 in turbo mode, where f_(CLK)is either provided by the internal oscillator or the

external clock source. Table 6 shows the modulator frequency for each operating mode using either the internal

oscillator or an external clock of 4.096 MHz.

Table 6. Modulator Clock Frequency for Different

Operating Modes⁽¹⁾

OPERATING MODE

Duty-cycle mode

Normal mode

f_(MOD)

256 kHz

512 kHz

Turbo mode

(1) Using the internal oscillator or an external 4.096-MHz clock.

8.3.4 Digital Filter

The device uses a linear-phase finite impulse response (FIR) digital filter that performs both filtering and

decimation of the digital data stream coming from the modulator. The digital filter is automatically adjusted for the

different data rates and always settles within a single cycle. At data rates of 5 SPS and 20 SPS, the filter can be

configured to reject 50-Hz or 60-Hz line frequencies or to simultaneously reject 50 Hz and 60 Hz. Two bits

(50/60[1:0]) in the configuration register are used to configure the filter accordingly. The frequency responses of

the digital filter are shown in Figure 46 to Figure 59 for different output data rates using the internal oscillator or

an external 4.096-MHz clock.

The filter notches and output data rate scale proportionally with the clock frequency. For example, a notch that

appears at 20 Hz when using a 4.096-MHz clock appears at 10 Hz if a 2.048-MHz clock is used. Note that the

internal oscillator can vary over temperature as specified in the Electrical Characteristics table. The data rate or

conversion time, respectively, and filter notches consequently vary by the same amount. Consider using an

external precision clock source if a digital filter notch at a specific frequency with a tighter tolerance is required.

0

±40

0

±40

±80

±120

±160

±200

±120

±160

±200

0

20

40

60

80 100 120 140 160 180 200

46

48

50

52

54

56

58

60

62

64

Frequency (Hz)

C049

C050

Simultaneous 50-Hz and 60-Hz Rejection, 50/60[1:0] = 01

Figure 46. Filter Response

(DR = 20 SPS)

Figure 47. Detailed View of Filter Response

(DR = 20 SPS)

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0

±40

0

±40

±80

±120

±160

±200

±120

±160

±200

0

20

40

60

80 100 120 140 160 180 200

46

56

0

47

48

49

50

51

52

53

54

Frequency (Hz)

C045

C046

50-Hz Rejection Only, 50/60[1:0] = 10

Figure 48. Filter Response

(DR = 20 SPS)

Figure 49. Detailed View of Filter Response

(DR = 20 SPS)

0

±40

0

±40

±80

±120

±160

±200

±120

±160

±200

20

40

60

80 100 120 140 160 180 200

57

58

59

60

61

62

63

64

Frequency (Hz)

C047

C048

60-Hz Rejection Only, 50/60[1:0] = 11

Figure 50. Filter Response

(DR = 20 SPS)

Figure 51. Detailed View of Filter Response

(DR = 20 SPS)

0

±20

±40

±60

±80

0

±20

±40

±60

±80

20

40

60

80 100 120 140 160 180 200

20

40

60

80 100 120 140 160 180 200

C051

C052

Frequency (Hz)

50/60[1:0] = 00

Figure 52. Filter Response

(DR = 20 SPS)

Figure 53. Filter Response

(DR = 45 SPS)

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0

±20

±40

±60

±80

±20

±40

±60

±80

0

100 200 300 400 500 600 700 800 900 1000

0

100 200 300 400 500 600 700 800 900 1000

C054

C053

Frequency (Hz)

Figure 54. Filter Response

(DR = 90 SPS)

Figure 55. Filter Response

(DR = 175 SPS)

0

±20

±40

±60

0

±20

±40

±60

±80

0

200 400 600 800 1000 1200 1400 1600 1800 2000

500 1000 1500 2000 2500 3000 3500 4000

C055

C056

Frequency (Hz)

Figure 56. Filter Response

(DR = 330 SPS)

Figure 57. Filter Response

(DR = 600 SPS)

0

±20

±40

±60

0

±20

±40

±60

±80

0

1

2

3

4

5

6

7

8

9

10

1

2

3

4

5

6

7

8

9

10

C057

C058

Frequency (kHz)

Figure 58. Filter Response

(DR = 1 kSPS)

Figure 59. Filter Response

(DR = 2 kSPS)

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8.3.5 Output Data Rate

Table 7 shows the actual conversion times for each data rate setting. The values provided are in terms of t_(CLK)

cycles using an external clock with a clock frequency of f_(CLK)= 4.096 MHz. The data rates scale proportionally in

case an external clock with a frequency other than 4.096 MHz is used.

Continuous conversion mode data rates are timed from one DRDY falling edge to the next DRDY falling edge.

The first conversion starts 210 · t_(CLK)(normal mode, duty-cycle mode) or 114 · t_(CLK)(turbo mode) after the last

SCLK falling edge of the START/SYNC command.

Single-shot mode data rates are timed from the last SCLK falling edge of the START/SYNC command to the

DRDY falling edge and rounded to the next t_(CLK). In case the internal oscillator is used, an additional oscillator

wake-up time of up to 50 µs (normal mode, duty-cycle mode) or 25 µs (turbo mode) must be added in single-shot

mode. The internal oscillator starts to power up at the first SCLK rising edge of the START/SYNC command. If

an SCLK frequency higher than 160 kHz (normal mode, duty-cycle mode) or 320 kHz (turbo mode) is used, the

oscillator may not be fully powered up at the end of the START/SYNC command. The ADC then waits until the

internal oscillator is fully powered up before starting a conversion.

Single-shot conversion times in duty-cycle mode are the same as in normal mode. See the Duty-Cycle Mode

section for more details on duty-cycle mode operation.

Table 7. Conversion Times

ACTUAL CONVERSION TIME (t_(CLK)

)

NOMINAL DATA RATE

(SPS)

–3-dB BANDWIDTH

(Hz)

CONTINUOUS CONVERSION MODE

SINGLE-SHOT MODE

Normal Mode

20

13.1

20.0

204768

91120

46128

23664

12464

6896

204850

91218

46226

23762

12562

6994

45

90

39.6

175

77.8

330

150.1

279.0

483.8

600

1000

4144

4242

Duty-Cycle Mode

5

13.1

20.0

823120

364560

184592

94736

49936

27664

16656

n/a

11.25

22.5

39.6

44

77.8

82.5

150.1

279.0

483.8

150

250

Turbo Mode

40

26.2

39.9

102384

45560

23064

11832

6232

102434

45618

23122

11890

6290

90

180

79.2

350

155.6

300.3

558.1

967.6

660

1200

2000

3448

3506

2072

2130

Note that even though the conversion time at the 20-SPS setting is not exactly 1 / 20 Hz = 50 ms, this

discrepancy does not affect the 50-Hz or 60-Hz rejection. To achieve the 50-Hz and 60-Hz rejection specified in

the Electrical Characteristics, the external clock frequency must be 4.096 MHz. When using the internal

oscillator, the conversion time and filter notches vary by the amount specified in the Electrical Characteristics

table for oscillator accuracy.

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8.3.6 Voltage Reference

The device offers an integrated low-drift, 2.048-V reference. For applications that require a different reference

voltage value or a ratiometric measurement approach, the device offers two differential reference input pairs

(REFP0, REFN0 and REFP1, REFN1). In addition, the analog supply (AVDD) can be used as a reference.

The reference source is selected by two bits (VREF[1:0]) in the configuration register. By default, the internal

reference is selected. The internal voltage reference requires less than 25 µs to fully settle after power-up, when

coming out of power-down mode, or when switching from an external reference source to the internal reference.

The differential reference inputs allow freedom in the reference common-mode voltage. REFP0 and REFN0 are

dedicated reference inputs whereas REFP1 and REFN1 are shared with inputs AIN0 and AIN3, respectively. All

reference inputs are internally buffered to increase input impedance. Therefore, additional reference buffers are

usually not required when using an external reference. When used in ratiometric applications, the reference

inputs do not load the external circuitry. Note that the analog supply current increases by approximately 75 µA

when using an external reference because the reference buffers are enabled. In most cases the conversion

result is directly proportional to the stability of the reference source. Any noise and drift of the source is reflected

in the conversion result.

8.3.7 Clock Source

The device system clock can either be provided by the internal low-drift oscillator or by an external clock source

on the CLK input. Connect the CLK pin to DGND before power-up or reset to activate the internal oscillator.

Connecting an external clock to the CLK pin at any time deactivates the internal oscillator after two rising edges

on the CLK pin are detected. The device then operates on the external clock. After the ADS1120-Q1 switches to

the external clock, the device can only be switched back to the internal oscillator by cycling the power supplies or

by sending a RESET command.

8.3.8 Excitation Current Sources

The device provides two matched programmable excitation current sources (IDACs) for RTD applications. The

output current of the current sources can be programmed to 50 μA, 100 μA, 250 μA, 500 μA,

1000 μA, or 1500 μA using the respective bits (IDAC[2:0]) in the configuration register. Each current source can

be connected to any of the analog inputs (AINx) as well as to any of the dedicated reference inputs (REFP0 and

REFN0). Both current sources can also be connected to the same pin. Routing of the IDACs is configured by bits

(I1MUX[2:0], I2MUX[2:0]) in the configuration register. Care must be taken not to exceed the compliance voltage

of the IDACs. In other words, limit the voltage on the pin where the IDAC is routed to ≤ (AVDD – 0.9 V),

otherwise the specified accuracy of the IDAC current is not met. For three-wire RTD applications, the matched

current sources can be used to cancel errors caused by sensor lead resistance (see the 3-Wire RTD

Measurement section for more details).

The IDACs require up to 200 µs to start up after the IDAC current is programmed to the respective value using

bits IDAC[2:0]. If configuration registers 2 and 3 are not written during the same WREG command, TI

recommends to first set the IDAC current to the respective value using bits IDAC[2:0] and thereafter select the

routing for each IDAC (I1MUX[2:0], I2MUX[2:0]).

In single-shot mode, the IDACs remain active between any two conversions if the IDAC[2:0] bits are set to a

value other than 000. However, the IDACs are powered down whenever the POWERDOWN command is issued.

8.3.9 Low-Side Power Switch

A low-side power switch with low on-resistance connected between the analog input AIN3/REFN1 and AVSS is

integrated in the device as well. This power switch can be used to reduce system power consumption in bridge

sensor applications by powering down the bridge circuit between conversions. When the respective bit (PSW) in

the configuration register is set, the switch automatically closes when the START/SYNC command is sent and

opens when the POWERDOWN command is issued. Note that the switch stays closed between conversions in

single-shot mode in case the PSW bit is set to 1. The switch can be opened at any time by setting the PSW bit to

0. By default, the switch is always open.

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8.3.10 Sensor Detection

To help detect a possible sensor malfunction, the device provides internal 10-µA, burn-out current sources.

When enabled by setting the respective bit (BCS) in the configuration register, one current source sources

current to the positive analog input (AIN_P) currently selected while the other current source sinks current form the

selected negative analog input (AIN_N).

In case of an open circuit in the sensor, these burn-out current sources pull the positive input towards AVDD and

the negative input towards AVSS, resulting in a full-scale reading. A full-scale reading may also indicate that the

sensor is overloaded or that the reference voltage is absent. A near-zero reading may indicate a shorted sensor.

Note that the absolute value of the burn-out current sources typically varies by ±10% and the internal multiplexer

adds a small series resistance. Therefore, distinguishing a shorted sensor condition from a normal reading can

be difficult, especially if an RC filter is used at the inputs. In other words, even if the sensor is shorted, the

voltage drop across the external filter resistance and the residual resistance of the multiplexer causes the output

to read a value higher than zero.

Keep in mind that ADC readings of a functional sensor may be corrupted when the burn-out current sources are

enabled. TI recommends disabling the burn-out current sources when preforming the precision measurement,

and only enabling them to test for sensor fault conditions.

8.3.11 System Monitor

The device provides some means for monitoring the analog power supply and the external voltage reference. To

select a monitoring voltage, the internal multiplexer (MUX[3:0]) must be configured accordingly in the

configuration register. The device automatically bypasses the PGA and sets the gain to 1, irrespective of the

configuration register settings while the monitoring feature is used. Note that the system monitor function only

provides a coarse result and is not meant to be a precision measurement.

When measuring the analog power supply (MUX[3:0] = 1101), the resulting conversion is approximately (AVDD –

AVSS) / 4. The device uses the internal 2.048-V reference for the measurement regardless of what reference

source is selected in the configuration register (VREF[1:0]).

When monitoring one of the two possible external reference voltage sources (MUX[3:0] = 1100), the result is

approximately (V_(REFPx)– V_(REFNx)) / 4. REFPx and REFNx denote the external reference input pair selected in

the configuration register (VREF[1:0]). The device automatically uses the internal reference for the measurement.

8.3.12 Offset Calibration

The internal multiplexer offers the option to short both PGA inputs (AIN_Pand AIN_N) to mid-supply (AVDD +

AVSS) / 2. This option can be used to measure and calibrate the device offset voltage by storing the result of the

shorted input voltage reading in a microcontroller and consequently subtracting the result from each following

reading. TI recommends taking multiple readings with the inputs shorted and averaging the result to reduce the

effect of noise.

8.3.13 Power Supplies

The device requires two power supplies: analog (AVDD, AVSS) and digital (DVDD, DGND). The analog power

supply can be bipolar (for example, AVDD = 2.5 V, AVSS = –2.5 V) or unipolar (for example, AVDD = 3.3 V,

AVSS = 0 V) and is independent of the digital power supply. The digital supply sets the digital I/O levels. The

power supplies can be sequenced in any order but in no case can any analog or digital inputs exceed the

respective analog or digital power-supply voltage limits.

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8.3.14 Temperature Sensor

The ADS1120-Q1 offers an integrated precision temperature sensor. The temperature sensor mode is enabled

by setting bit TS = 1 in the configuration register. When in temperature sensor mode, the settings of configuration

register 0 have no effect and the device uses the internal reference for measurement, regardless of the selected

voltage reference source. Temperature data are represented as a 14-bit result that is left-justified within the 16-

bit conversion result. Data are output starting with the most significant byte (MSB). When reading the two data

bytes, the first 14 bits are used to indicate the temperature measurement result. One 14-bit LSB equals

0.03125°C. Negative numbers are represented in binary twos complement format, as shown in Table 8.

Table 8. 14-Bit Temperature Data Format

DIGITAL OUTPUT

TEMPERATURE (°C)

BINARY

HEX

1000

0FFF

0C80

0960

0640

0320

0008

0001

0000

3FF8

3CE0

3920

128

127.96875

100

01 0000 0000 0000

00 1111 1111 1111

00 1100 1000 0000

00 1001 0110 0000

00 0110 0100 0000

00 0011 0010 0000

00 0000 0000 1000

00 0000 0000 0001

00 0000 0000 0000

11 1111 1111 1000

11 1100 1110 0000

11 1001 0010 0000

75

50

25

0.25

0.03125

0

–0.25

–25

–55

8.3.14.1 Converting from Temperature to Digital Codes

8.3.14.1.1 For Positive Temperatures (for Example, 50°C):

Twos complement is not performed on positive numbers. Therefore, simply convert the number to binary code in

a 14-bit, left-justified format with the MSB = 0 to denote the positive sign.

Example: 50°C / (0.03125°C per count) = 1600 = 0640h = 00 0110 0100 0000

8.3.14.1.2 For Negative Temperatures (for Example, –25°C):

Generate the twos complement of a negative number by complementing the absolute binary number and adding

1. Then, denote the negative sign with the MSB = 1.

Example: |–25°C| / (0.03125°C per count) = 800 = 0320h = 00 0011 0010 0000

Twos complement format: 11 1100 1101 1111 + 1 = 11 1100 1110 0000

8.3.14.2 Converting from Digital Codes to Temperature

To convert from digital codes to temperature, first check whether the MSB is a 0 or a 1. If the MSB is a 0, simply

multiply the decimal code by 0.03125°C to obtain the result. If the MSB = 1, subtract 1 from the result and

complement all bits. Then, multiply the result by –0.03125°C.

Example: The device reads back 0960h: 0960h has an MSB = 0.

0960h · 0.03125°C = 2400 · 0.03125°C = 75°C

Example: The device reads back 3CE0h: 3CE0h has an MSB = 1.

Complement the result: 3CE0h → 0320h

0320h · 0.03125°C = 800 · 0.03125°C = –25°C

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8.4 Device Functional Modes

8.4.1 Power-Up and Reset

When the device powers up, a reset is performed. The reset process takes approximately 50 µs. After this

power-up reset time, all internal circuitry (including the voltage reference) are stable and communication with the

device is possible. As part of the reset process, the device sets all bits in the configuration registers to the

respective default settings. By default, the device is set to single-shot mode. After power-up, the device performs

a single conversion using the default register settings and then enters a low-power state. When the conversion is

complete, the DRDY pin transitions from high to low. The high-to-low transition of the DRDY pin can be used to

signal that the ADS1120-Q1 is operational and ready to use. The power-up behavior is intended to prevent

systems with tight power-supply requirements from encountering a current surge during power-up.

8.4.2 Conversion Modes

The device can be operated in one of two conversion modes that can be selected by the CM bit in the

configuration register. These conversion modes are single-shot and continuous conversion mode.

8.4.2.1 Single-Shot Mode

In single-shot mode, the device only performs a conversion when a START/SYNC command is issued. The

device consequently performs one single conversion and returns to a low-power state afterwards. The internal

oscillator and all analog circuitry (except for the excitation current sources) are turned off while the device waits

in this low-power state until the next conversion is started. In addition, every write access to any configuration

register also starts a new conversion. Writing to any configuration register while a conversion is ongoing

functions as a new START/SYNC command that stops the current conversion and restarts a single new

conversion. Each conversion is fully settled (assuming the analog input signal settles to its final value before the

conversion starts) because the device digital filter settles within a single cycle.

8.4.2.2 Continuous Conversion Mode

In continuous conversion mode, the device continuously performs conversions. When a conversion completes,

the device places the result in the output buffer and immediately begins another conversion.

In order to start continuous conversion mode, the CM bit must be set to 1 followed by a START/SYNC command.

The first conversion starts 210 · t_(CLK)(normal mode, duty-cycle mode) or 114 · t_(CLK)(turbo mode) after the last

SCLK falling edge of the START/SYNC command. Writing to any configuration register during an ongoing

conversion restarts the current conversion. TI recommends always sending a START/SYNC command

immediately after the CM bit is set to 1.

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Device Functional Modes (continued)

8.4.3 Operating Modes

In addition to the different conversion modes, the device can also be operated in different operating modes that

can be selected to trade-off power consumption, noise performance, and output data rate. These modes are:

normal mode, duty-cycle mode, turbo mode, and power-down mode.

8.4.3.1 Normal Mode

Normal mode is the default mode of operation after power-up. In this mode, the internal modulator of the ΔΣ ADC

runs at a modulator clock frequency of f_(MOD)= f_(CLK)/ 16, where the system clock (f_(CLK)) is either provided by the

internal oscillator or the external clock source. The modulator frequency is 256 kHz when using the internal

oscillator. Normal mode offers output data rate options ranging from 20 SPS to 1 kSPS with the internal

oscillator. The data rate is selected by the DR[2:0] bits in the configuration register. In case an external clock

source with a clock frequency other than 4.096 MHz is used, the data rates scale accordingly. For example,

using an external clock with f_(CLK)= 2.048 MHz yields data rates ranging from 10 SPS to 500 SPS.

8.4.3.2 Duty-Cycle Mode

The noise performance of a ΔΣ ADC generally improves when lowering the output data rate because more

samples of the internal modulator can be averaged to yield one conversion result. In applications where power

consumption is critical, the improved noise performance at low data rates may not be required. For these

applications, the device supports an automatic duty-cycle mode that can yield significant power savings by

periodically entering a low-power state between conversions. In principle, the device runs in normal mode with a

duty cycle of 25%. This functionality means the device performs one conversion in the same manner as when

running in normal mode but then automatically enters a low power-state for three consecutive conversion cycles.

The noise performance in duty-cycle mode is therefore comparable to the noise performance in normal mode at

four times the data rate. Data rates in duty-cycle mode range from 5 SPS to 250 SPS with the internal oscillator.

8.4.3.3 Turbo Mode

Applications that require higher data rates up to 2 kSPS can operate the device in turbo mode. In this mode, the

internal modulator runs at a higher frequency of f_(MOD)= f_(CLK)/ 8. f_(MOD)equals 512 kHz when the internal

oscillator or an external 4.096-MHz clock is used. Note that the device power consumption increases because

the modulator runs at a higher frequency. Running the ADS1120-Q1 in turbo mode at a comparable output data

rate as in normal mode yields better noise performance. For example, the input-referred noise at 90 SPS in turbo

mode is lower than the input-referred noise at 90 SPS in normal mode.

8.4.3.4 Power-Down Mode

When the POWERDOWN command is issued, the device enters power-down mode after completing the current

conversion. In this mode, all analog circuitry (including the voltage reference and both IDACs) are powered

down, the low-side power switch is opened, and the device typically only uses 400 nA of current. While in power-

down mode, the device holds the configuration register settings and responds to commands, but does not

perform any data conversions.

Issuing a START/SYNC command wakes up the device and either starts a single conversion or starts continuous

conversion mode, depending on the conversion mode selected by the CM bit. Note that writing to any

configuration register wakes up the device as well, but only starts a single conversion regardless of the selected

conversion mode (CM).

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8.5 Programming

8.5.1 Serial Interface

The SPI-compatible serial interface of the device is used to read conversion data, read and write the device

configuration registers, and control device operation. Only SPI mode 1 (CPOL = 0, CPHA = 1) is supported. The

interface consists of five control lines (CS, SCLK, DIN, DOUT/DRDY, and DRDY) but can be used with only four

or even three control signals as well. The dedicated data-ready signal (DRDY) can be configured to be shared

with DOUT/DRDY. If the serial bus is not shared with any other device, CS can be tied low permanently so that

only signals SCLK, DIN, and DOUT/DRDY are required to communicate with the device.

8.5.1.1 Chip Select (CS)

Chip select (CS) is an active-low input that selects the device for SPI communication. This feature is useful when

multiple devices share the same serial bus. CS must remain low for the duration of the serial communication.

When CS is taken high, the serial interface is reset, SCLK is ignored, and DOUT/DRDY enters a high-impedance

state; as such, DOUT/DRDY cannot indicate when data are ready. In situations where multiple devices are

present on the bus, the dedicated DRDY pin can provide an uninterrupted monitor of the conversion status. If the

serial bus is not shared with another peripheral, CS can be tied low.

8.5.1.2 Serial Clock (SCLK)

The serial clock (SCLK) features a Schmitt-triggered input and is used to clock data into and out of the device on

the DIN and DOUT/DRDY pins, respectively. Even though the input has hysteresis, TI recommends keeping the

SCLK signal as clean as possible to prevent glitches from accidentally shifting the data. When the serial interface

is idle, hold SCLK low.

8.5.1.3 Data Ready (DRDY)

DRDY indicates when a new conversion result is ready for retrieval. When DRDY falls low, new conversion data

are ready. DRDY transitions back high on the next SCLK rising edge. When no data are read during continuous

conversion mode, DRDY remains low but pulses high for a duration of 2 · t_(MOD)prior to the next DRDY falling

edge. The DRDY pin is always actively driven, even when CS is high.

8.5.1.4 Data Input (DIN)

The data input pin (DIN) is used along with SCLK to send data (commands and register data) to the device. The

device latches data on DIN on the SCLK falling edge. The device never drives the DIN pin.

8.5.1.5 Data Output and Data Ready (DOUT/DRDY)

DOUT/DRDY serves a dual-purpose function. This pin is used with SCLK to read conversion and register data

from the device. Data on DOUT/DRDY are shifted out on the SCLK rising edge. DOUT/DRDY goes to a high-

impedance state when CS is high.

In addition, the DOUT/DRDY pin can also be configured as a data-ready indicator by setting the DRDYM bit high

in the configuration register. DOUT/DRDY then transitions low at the same time that the DRDY pin goes low to

indicate new conversion data are available. Both signals can be used to detect if new data are ready. However,

because DOUT/DRDY is disabled when CS is high, the recommended method of monitoring the end of a

conversion when multiple devices are present on the SPI bus is to use the dedicated DRDY pin.

8.5.1.6 SPI Timeout

The ADS1120-Q1 offers an SPI timeout feature that can be used to recover communication when a serial

interface transmission is interrupted. This feature is especially useful in applications where CS is permanently

tied low and not used to frame a communication sequence. Whenever a complete command is not sent within

13955 · t_(MOD)(normal mode, duty-cycle mode) or 27910 · t_(MOD)(turbo mode), the serial interface resets and the

next SCLK pulse starts a new communication cycle.

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Programming (continued)

8.5.2 Data Format

The device provides 16 bits of data in binary twos complement format. The size of one code (LSB) is calculated

using Equation 16.

1 LSB = (2 · V_ref/ Gain) / 2¹⁶= FS / 2¹⁵

(16)

A positive full-scale input [V_IN≥ (+FS – 1 LSB) = (V_ref/ Gain – 1 LSB)] produces an output code of 7FFFh and a

negative full-scale input (V_IN≤ –FS = –V_ref/ Gain) produces an output code of 8000h. The output clips at these

codes for signals that exceed full-scale.

Table 9 summarizes the ideal output codes for different input signals.

Table 9. Ideal Output Code versus Input Signal

INPUT SIGNAL

V_IN= (V_(AINP)– V_(AINN)

)

IDEAL OUTPUT CODE⁽¹⁾

≥ +FS (2¹⁵– 1) / 2¹⁵

7FFFh

0001h

0000h

FFFFh

8000h

+FS / 2¹⁵

0

–FS / 2¹⁵

≤ –FS

(1) Excludes the effects of noise, INL, offset, and gain errors.

Mapping of the analog input signal to the output codes is shown in Figure 60.

0x7FFF

0x7FFE

0x0001

0x0000

0xFFFF

0x8001

0x8000

¼

-FS

0

FS

Input Voltage (V_IN

)

2¹⁵- 1

FS

2¹⁵

Figure 60. Code Transition Diagram

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8.5.3 Commands

The device offers six different commands to control device operation, as shown in Table 10. Four commands are

stand-alone instructions (RESET, START/SYNC, POWERDOWN, and RDATA). The commands to read (RREG)

and write (WREG) configuration register data from and to the device require additional information as part of the

instruction.

Table 10. Command Definitions

COMMAND

DESCRIPTION

COMMAND BYTE⁽¹⁾

0000 011x

RESET

Reset the device

START/SYNC

POWERDOWN

RDATA

Start or restart conversions

Enter power-down mode

Read data by command

0000 100x

0000 001x

0001 xxxx

RREG

Read nn registers starting at address rr

Write nn registers starting at address rr

0010 rrnn

WREG

0100 rrnn

(1) Operands: rr = configuration register (00 to 11), nn = number of bytes – 1 (00 to 11), and x = don't care.

8.5.3.1 RESET (0000 011x)

Resets the device to the default values. Wait at least (50 µs + 32 · t_(CLK)) after the RESET command is sent

before sending any other command.

8.5.3.2 START/SYNC (0000 100x)

In single-shot mode, the START/SYNC command is used to start a single conversion, or (when sent during an

ongoing conversion) to reset the digital filter, and then restarts a single new conversion. When the device is set

to continuous conversion mode, the START/SYNC command must be issued one time to start converting

continuously. Sending the START/SYNC command while converting in continuous conversion mode resets the

digital filter and restarts continuous conversions.

8.5.3.3 POWERDOWN (0000 001x)

The POWERDOWN command places the device into power-down mode. This command shuts down all internal

analog components, opens the low-side switch, turns off both IDACs, but holds all register values. In case the

POWERDOWN command is issued while a conversion is ongoing, the conversion completes before the

ADS1120-Q1 enters power-down mode. As soon as a START/SYNC command is issued, all analog components

return to their previous states.

8.5.3.4 RDATA (0001 xxxx)

The RDATA command loads the output shift register with the most recent conversion result. This command can

be used when DOUT/DRDY or DRDY are not monitored to indicate that a new conversion result is available. If a

conversion finishes in the middle of the RDATA command byte, the state of the DRDY pin at the end of the read

operation signals whether the old or the new result is loaded. If the old result is loaded, DRDY stays low,

indicating that the new result is not read out. The new conversion result loads when DRDY is high.

8.5.3.5 RREG (0010 rrnn)

The RREG command reads the number of bytes specified by nn (number of bytes to be read – 1) from the

device configuration register, starting at register address rr. The command is completed after nn + 1 bytes are

clocked out after the RREG command byte. For example, the command to read three bytes (nn = 10) starting at

configuration register 1 (rr = 01) is 0010 0110.

8.5.3.6 WREG (0100 rrnn)

The WREG command writes the number of bytes specified by nn (number of bytes to be written – 1) to the

device configuration register, starting at register address rr. The command is completed after nn + 1 bytes are

clocked in after the WREG command byte. For example, the command to write two bytes (nn = 01) starting at

configuration register 0 (rr = 00) is 0100 0001. The configuration registers are updated on the last SCLK falling

edge.

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8.5.4 Reading Data

Output pins DRDY and DOUT/DRDY (if the DRDYM bit is set high in the configuration register) transition low

when new data are ready for retrieval. The conversion data are written to an internal data buffer. Data can be

read directly from this buffer on DOUT/DRDY when DRDY falls low without concern of data corruption. An

RDATA command does not have to be sent. Data are shifted out on the SCLK rising edges, MSB first, and

consist of two bytes of data.

Figure 61 to Figure 63 show the timing diagrams for reading conversion data in continuous conversion mode and

single-shot mode when not using the RDATA command.

CS

1

9

SCLK

DOUT/DRDY

DRDY

Hi-Z

DATA MSB

DATA LSB

Next Data Ready

2· t_(MOD)

DIN

Figure 61. Continuous Conversion Mode (DRDYM = 0)

CS

SCLK

1

9

DOUT/DRDY

DRDY

DATA MSB

DATA LSB

Next Data Ready

2· t_(MOD)

DIN

Figure 62. Continuous Conversion Mode (DRDYM = 1)

CS

SCLK

1

9

DOUT/DRDY

DRDY

DATA MSB

DATA LSB

Next Data Ready

DIN

START/SYNC

Figure 63. Single-Shot Mode (DRDYM = 0)

Data can also by read at any time without synchronizing to the DRDY signal using the RDATA command. When

an RDATA command is issued, the conversion result currently stored in the data buffer is shifted out on

DOUT/DRDY on the following SCLK rising edges. Data can be read continuously with the RDATA command as

an alternative to monitoring DRDY or DOUT/DRDY. The DRDY pin can be polled after the LSB is clocked out to

determine if a new conversion result was loaded. If a new conversion completes during the read operation but

data from the previous conversion are read, then DRDY is low. Otherwise, if the most recent result is read,

DRDY is high. Figure 64 and Figure 65 illustrate the behavior for both cases.

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CS

1

9

SCLK

Hi-Z

DOUT/DRDY

DATA MSB

DATA LSB

DRDY

Next Data Ready

DIN

RDATA

Figure 64. State of DRDY when a New Conversion Finishes During an RDATA Command

CS

SCLK

1

9

Hi-Z

DOUT/DRDY

DRDY

DATA MSB

DATA LSB

Next Data Ready

DIN

RDATA

Figure 65. State of DRDY when the Most Recent Conversion Result is Read During an RDATA Command

8.5.5 Sending Commands

The device serial interface is capable of full-duplex operation while reading conversion data when not using the

RDATA command. Full-duplex operation means commands are decoded at the same time that conversion data

are read. Commands can be sent on any 8-bit data boundary during a data read operation. When a RREG or

RDATA command is recognized, the current data read operation is aborted and the conversion data are

corrupted, unless the command is sent while the last byte of the conversion result is retrieved. The device starts

to output the requested data on DOUT/DRDY at the first SCLK rising edge after the command byte. To read data

without interruption, keep DIN low while clocking out data.

A WREG command can be sent without corrupting an ongoing read operation. Figure 66 shows an example for

sending a WREG command to write two configuration registers while reading conversion data in continuous

conversion mode. After the command is clocked in (after the 32nd SCLK falling edge), the device resets the

digital filter and starts converting with the new register settings. The WREG command can be sent on any of the

8-bit boundaries.

CS

1

9

17

25

SCLK

DOUT/DRDY

DRDY

Hi-Z

DATA MSB

DATA LSB

WREG

Next Data Ready

2· t_(MOD)

DIN

REG_DATA

Figure 66. Example of Reading Data while Simultaneously Sending a WREG Command

Note that the serial interface does not decode commands while an RDATA or RREG command is executed. That

is, all 16 bits of the conversion result must be read after the RDATA command is issued and all requested

registers must be read after a RREG command is sent before a new command can be issued.

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8.5.6 Interfacing with Multiple Devices

When connecting multiple ADS1120-Q1 devices to a single SPI bus, SCLK, DIN, and DOUT/DRDY can be safely

shared by using a dedicated chip-select (CS) line for each SPI-enabled device. When CS transitions high for the

respective device, DOUT/DRDY enters a 3-state mode. Therefore, DOUT/DRDY cannot be used to indicate

when new data are available if CS is high, regardless of the DRDYM bit setting in the configuration register. Only

the dedicated DRDY pin indicates that new data are available, because the DRDY pin is actively driven even

when CS is high.

In some cases the DRDY pin cannot be interfaced to the microcontroller. This scenario can occur if there are

insufficient GPIO channels available on the microcontroller or if the serial interface must be galvanically isolated

and thus the amount of channels must be limited. Therefore, in order to evaluate when a new conversion of one

of the devices is ready, the microcontroller can periodically drop CS to the respective device and poll the state of

the DOUT/DRDY pin. When CS goes low, the DOUT/DRDY pin immediately drives either high or low, provided

that the DRDYM bit is configured to 1. If the DOUT/DRDY line drives low, when CS is taken low, new data are

currently available. If the DOUT/DRDY line drives high, no new data are available. This procedure requires that

DOUT/DRDY is high after reading each conversion result and before taking CS high. To make sure DOUT/DRDY

is taken high, send 16 additional SCLKs with DIN held low after each data read operation. DOUT/DRDY reads

low during the first eight SCLKs after the conversion result is read, and reads high during the following eight

SCLKs, as shown in Figure 67. Alternatively, valid data can be retrieved from the device at any time without

concern of data corruption by using the RDATA command.

CS

1

9

17

25

SCLK

DOUT/DRDY

DRDY

Hi-Z

DATA MSB

DATA LSB

Next Data Ready

DIN

Figure 67. Example of Taking DOUT/DRDY High After Reading a Conversion Result

8.6 Register Map

8.6.1 Configuration Registers

The device has four 8-bit configuration registers that are accessible through the serial interface using the RREG

and WREG commands. The configuration registers control how the device operates and can be changed at any

time without causing data corruption. After power-up or reset, all registers are set to the default values (which are

all 0). All registers retain their values during power-down mode. Table 11 shows the register map of the

configuration registers.

Table 11. Configuration Register Map

REGISTER

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

(Hex)

00h

MUX[3:0]

GAIN[2:0]

PGA_BYPAS

S

01h

02h

03h

DR[2:0]

VREF[1:0]

I1MUX[2:0]

MODE[1:0]

CM

TS

BCS

50/60[1:0]

PSW

IDAC[2:0]

DRDYM

I2MUX[2:0]

RESERVED

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8.6.1.1 Configuration Register 0 (offset = 00h) [reset = 00h]

Figure 68. Configuration Register 0

7

6

5

4

3

2

1

0

MUX[3:0]

R/W-0h

GAIN[2:0]

R/W-0h

PGA_BYPASS

R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 12. Configuration Register 0 Field Descriptions

Bit

Field

Type

Reset

Description

Input multiplexer configuration

These bits configure the input multiplexer.

For settings where AIN_N= AVSS, the PGA must be disabled (PGA_BYPASS = 1)

and only gains 1, 2, and 4 can be used.

0000 : AIN_P= AIN0, AIN_N= AIN1 (default)

0001 : AIN_P= AIN0, AIN_N= AIN2

0010 : AIN_P= AIN0, AIN_N= AIN3

0011 : AIN_P= AIN1, AIN_N= AIN2

0100 : AIN_P= AIN1, AIN_N= AIN3

0101 : AIN_P= AIN2, AIN_N= AIN3

0110 : AIN_P= AIN1, AIN_N= AIN0

7:4

MUX[3:0]

R/W

0h

0111 : AIN_P= AIN3, AIN_N= AIN2

1000 : AIN_P= AIN0, AIN_N= AVSS

1001 : AIN_P= AIN1, AIN_N= AVSS

1010 : AIN_P= AIN2, AIN_N= AVSS

1011 : AIN_P= AIN3, AIN_N= AVSS

1100 : (V_(REFPx)– V_(REFNx)) / 4 monitor (PGA bypassed)

1101 : (AVDD – AVSS) / 4 monitor (PGA bypassed)

1110 : AIN_Pand AIN_Nshorted to (AVDD + AVSS) / 2

1111 : Not used

Gain configuration

These bits configure the device gain.

Gains 1, 2, and 4 can be used without the PGA. In this case, gain is obtained by

a switched-capacitor structure.

000 : Gain = 1 (default)

001 : Gain = 2

010 : Gain = 4

3:1

GAIN[2:0]

R/W

0h

011 : Gain = 8

100 : Gain = 16

101 : Gain = 32

110 : Gain = 64

111 : Gain = 128

Disables and bypasses the internal low-noise PGA

Disabling the PGA reduces overall power consumption and allows the common-

mode voltage range (V_CM) to span from AVSS – 0.1 V to AVDD + 0.1 V.

The PGA can only be disabled for gains 1, 2, and 4.

The PGA is always enabled for gain settings 8 to 128, regardless of the

PGA_BYPASS setting.

0

PGA_BYPASS

R/W

0h

0 : PGA enabled (default)

1 : PGA disabled and bypassed

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8.6.1.2 Configuration Register 1 (offset = 01h) [reset = 00h]

Figure 69. Configuration Register 1

7

6

5

4

3

2

1

0

DR[2:0]

R/W-0h

MODE[1:0]

R/W-0h

CM

TS

BCS

R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 13. Configuration Register 1 Field Descriptions

Bit

Field

Type

Reset

Description

Data rate

7:5

DR[2:0]

R/W

0h

These bits control the data rate setting depending on the selected operating

mode. Table 14 lists the bit settings for normal, duty-cycle, and turbo mode.

Operating mode

These bits control the operating mode the device operates in.

00 : Normal mode (256-kHz modulator clock, default)

01 : Duty-cycle mode (internal duty cycle of 1:4)

10 : Turbo mode (512-kHz modulator clock)

11 : Not used

4:3

2

MODE[1:0]

R/W

0h

Conversion mode

This bit sets the conversion mode for the device.

CM

0 : Single-shot mode (default)

1 : Continuous conversion mode

Temperature sensor mode

This bit enables the internal temperature sensor and puts the device in

temperature sensor mode.

The settings of configuration register 0 have no effect and the device uses the

internal reference for measurement when temperature sensor mode is enabled.

1

0

TS

R/W

0h

0 : Disables temperature sensor (default)

1 : Enables temperature sensor

Burn-out current sources

This bit controls the 10-µA, burn-out current sources.

The burn-out current sources can be used to detect sensor faults such as wire

breaks and shorted sensors.

BCS

0 : Current sources off (default)

1 : Current sources on

Table 14. DR Bit Settings⁽¹⁾

NORMAL MODE

000 = 20 SPS

001 = 45 SPS

010 = 90 SPS

011 = 175 SPS

100 = 330 SPS

101 = 600 SPS

110 = 1000 SPS

111 = Not used

DUTY-CYCLE MODE

000 = 5 SPS

TURBO MODE

000 = 40 SPS

001 = 90 SPS

010 = 180 SPS

011 = 350 SPS

100 = 660 SPS

101 = 1200 SPS

110 = 2000 SPS

111 = Not used

001 = 11.25 SPS

010 = 22.5 SPS

011 = 44 SPS

100 = 82.5 SPS

101 = 150 SPS

110 = 250 SPS

111 = Not used

(1) Data rates provided are calculated using the internal oscillator or an external 4.096-MHz clock. The data rates scale proportionally with

the external clock frequency when an external clock other than 4.096 MHz is used.

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8.6.1.3 Configuration Register 2 (offset = 02h) [reset = 00h]

Figure 70. Configuration Register 2

7

6

5

4

3

2

1

0

VREF[1:0]

R/W-0h

50/60[1:0]

R/W-0h

PSW

R/W-0h

IDAC[2:0]

R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 15. Configuration Register 2 Field Descriptions

Bit

Field

Type

Reset

Description

Voltage reference selection

These bits select the voltage reference source that is used for the conversion.

00 : Internal 2.048-V reference selected (default)

7:6

VREF[1:0]

R/W

0h

01 : External reference selected using dedicated REFP0 and REFN0 inputs

10 : External reference selected using AIN0/REFP1 and AIN3/REFN1 inputs

11 : Analog supply (AVDD – AVSS) used as reference

FIR filter configuration

These bits configure the filter coefficients for the internal FIR filter.

These bits only affect the 20-SPS setting in normal mode and 5-SPS setting in

duty-cycle mode.

5:4

50/60[1:0]

R/W

0h

00 : No 50-Hz or 60-Hz rejection (default)

01 : Simultaneous 50-Hz and 60-Hz rejection

10 : 50-Hz rejection only

11 : 60-Hz rejection only

Low-side power switch configuration

This bit configures the behavior of the low-side switch connected between

AIN3/REFN1 and AVSS.

3

PSW

0 : Switch is always open (default)

1 : Switch automatically closes when the START/SYNC command is sent and

opens when the POWERDOWN command is issued

IDAC current setting

These bits set the current for both IDAC1 and IDAC2 excitation current sources.

000 : Off (default)

001 : Not used

010 : 50 µA

011 : 100 µA

100 : 250 µA

101 : 500 µA

110 : 1000 µA

111 : 1500 µA

2:0

IDAC[2:0]

R/W

0h

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8.6.1.4 Configuration Register 3 (offset = 03h) [reset = 00h]

Figure 71. Configuration Register 3

7

6

5

4

3

2

1

0

I1MUX[2:0]

R/W-0h

I2MUX[2:0]

R/W-0h

DRDYM

R/W-0h

RESERVED

R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 16. Configuration Register 3 Field Descriptions

Bit

Field

Type

Reset

Description

IDAC1 routing configuration

These bits select the channel where IDAC1 is routed to.

000 : IDAC1 disabled (default)

001 : IDAC1 connected to AIN0/REFP1

010 : IDAC1 connected to AIN1

011 : IDAC1 connected to AIN2

100 : IDAC1 connected to AIN3/REFN1

101 : IDAC1 connected to REFP0

110 : IDAC1 connected to REFN0

111 : Not used

7:5

I1MUX[2:0]

R/W

0h

IDAC2 routing configuration

These bits select the channel where IDAC2 is routed to.

000 : IDAC2 disabled (default)

001 : IDAC2 connected to AIN0/REFP1

010 : IDAC2 connected to AIN1

011 : IDAC2 connected to AIN2

100 : IDAC2 connected to AIN3/REFN1

101 : IDAC2 connected to REFP0

110 : IDAC2 connected to REFN0

111 : Not used

4:2

I2MUX[2:0]

R/W

0h

DRDY mode

This bit controls the behavior of the DOUT/DRDY pin when new data are ready.

1

0

DRDYM

R/W

0h

0 : Only the dedicated DRDY pin is used to indicate when data are ready (default)

1 : Data ready is indicated simultaneously on DOUT/DRDY and DRDY

Reserved

Always write 0

RESERVED

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9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

9.1 Application Information

The ADS1120-Q1 is a precision, 16-bit, ΔΣ ADC that offers many integrated features to ease the measurement

of the most common sensor types including various types of temperature and bridge sensors. Primary

considerations when designing an application with the ADS1120-Q1 include analog input filtering, establishing an

appropriate external reference for ratiometric measurements, and setting the common-mode input voltage for the

internal PGA. Connecting and configuring the serial interface appropriately is another concern. These

considerations are discussed in the following sections.

9.1.1 Serial Interface Connections

The principle serial interface connections for the ADS1120-Q1 are shown in Figure 72.

Microcontroller with SPI Interface

0.1 PF

3.3 V

1

2

3

4

5

6

7

8

SCLK

CS

DIN 16

DOUT/DRDY 15

DRDY 14

3.3 V

CLK

DGND

AVSS

DVDD 13

Device

AVDD 12

3.3 V

0.1 PF

AIN3/REFN1 AIN0/REFP1 11

0.1 PF

AIN2

AIN1 10

REFP0

REFN0

9

Figure 72. Serial Interface Connections

Most microcontroller SPI peripherals can operate with the ADS1120-Q1. The interface operates in SPI mode 1

where CPOL = 0 and CPHA = 1. In SPI mode 1, SCLK idles low and data are launched or changed only on

SCLK rising edges; data are latched or read by the master and slave on SCLK falling edges. Details of the SPI

communication protocol employed by the device can be found in the SPI Timing Requirements section.

TI recommends placing 47-Ω resistors in series with all digital input and output pins (CS, SCLK, DIN,

DOUT/DRDY, and DRDY). This resistance smooths sharp transitions, suppresses overshoot, and offers some

overvoltage protection. Care must be taken to meet all SPI timing requirements because the additional resistors

interact with the bus capacitances present on the digital signal lines.

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Application Information (continued)

9.1.2 Analog Input Filtering

Analog input filtering serves two purposes: first, to limit the effect of aliasing during the sampling process and

second, to reduce external noise from being a part of the measurement.

As with any sampled system, aliasing can occur if proper antialias filtering is not in place. Aliasing occurs when

frequency components are present in the input signal that are higher than half the sampling frequency of the

ADC (also known as the Nyquist frequency). These frequency components are folded back and show up in the

actual frequency band of interest below half the sampling frequency. Note that inside a ΔΣ ADC, the input signal

is sampled at the modulator frequency f_(MOD)and not at the output data rate. The filter response of the digital filter

repeats at multiples of the sampling frequency (f_(MOD)), as shown in Figure 73. Signals or noise up to a frequency

where the filter response repeats are attenuated to a certain amount by the digital filter depending on the filter

architecture. Any frequency components present in the input signal around the modulator frequency or multiples

thereof are not attenuated and alias back into the band of interest, unless attenuated by an external analog filter.

Magnitude

Sensor

Signal

Unwanted

Signals

Unwanted

Signals

Output

Data Rate

f_(MOD)/2

f_(MOD)

Frequency

Magnitude

Digital Filter

Aliasing of

Unwanted Signals

Output

Data Rate

f_(MOD)/2

f_(MOD)

Magnitude

External

Antialiasing Filter

Roll-Off

Output

f_(MOD)/2

f_(MOD)

Data Rate

Figure 73. Effect of Aliasing

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Application Information (continued)

Many sensor signals are inherently bandlimited; for example, the output of a thermocouple has a limited rate of

change. In this case the sensor signal does not alias back into the pass-band when using a ΔΣ ADC. However,

any noise pick-up along the sensor wiring or the application circuitry can potentially alias into the pass-band.

Power line-cycle frequency and harmonics are one common noise source. External noise can also be generated

from electromagnetic interference (EMI) or radio frequency interference (RFI) sources, such as nearby motors

and cellular phones. Another noise source typically exists on the printed circuit board (PCB) itself in the form of

clocks and other digital signals. Analog input filtering helps remove unwanted signals from affecting the

measurement result.

A first-order resistor-capacitor (RC) filter is (in most cases) sufficient to either totally eliminate aliasing, or to

reduce the effect of aliasing to a level within the noise floor of the sensor. Ideally, any signal beyond f_(MOD)/ 2 is

attenuated to a level below the noise floor of the ADC. The digital filter of the ADS1120-Q1 attenuates signals to

a certain degree, as illustrated in the filter response plots in the Digital Filter section. In addition, noise

components are usually smaller in magnitude than the actual sensor signal. Therefore, using a first-order RC

filter with a cutoff frequency set at the output data rate or 10x higher is generally a good starting point for a

system design.

Internal to the device, prior to the PGA inputs, is an EMI filter as shown in Figure 39. The cutoff frequency of this

filter is approximately 31.8 MHz, which helps reject high-frequency interferences.

9.1.3 External Reference and Ratiometric Measurements

The full-scale range of the ADS1120-Q1 is defined by the reference voltage and the PGA gain (FSR = ±V_ref

/

Gain). An external reference can be used instead of the integrated 2.048-V reference to adapt the FSR to the

specific system needs. An external reference must be used if V_IN> 2.048 V. For example, an external 5-V

reference and an AVDD = 5 V are required in order to measure a single-ended signal that can swing between

0 V and 5 V.

The reference inputs of the device also allow the implementation of ratiometric measurements. In a ratiometric

measurement the same excitation source that is used to excite the sensor is also used to establish the reference

for the ADC. As an example, a simple form of a ratiometric measurement uses the same current source to excite

both the resistive sensor element (such as an RTD) and another resistive reference element that is in series with

the element being measured. The voltage that develops across the reference element is used as the reference

source for the ADC. Because current noise and drift are common to both the sensor measurement and the

reference, these components cancel out in the ADC transfer function. The output code is only a ratio of the

sensor element and the value of the reference resistor. The value of the excitation current source itself is not part

of the ADC transfer function.

9.1.4 Establishing a Proper Common-Mode Input Voltage

The ADS1120-Q1 can be used to measure various types of input signal configurations: single-ended, pseudo-

differential, and fully-differential signals (which can be either unipolar or bipolar). However, configuring the device

properly for the respective signal type is important.

Signals where the negative analog input is fixed and referenced to analog ground (V_(AINN)= 0 V) are commonly

called single-ended signals. The common-mode voltage of a single-ended signal consequently varies between

0 V and V_IN/ 2. If the PGA is disabled and bypassed, the common-mode input voltage of the ADS1120-Q1 can

be as low as 100 mV below AVSS and as large as 100 mV above AVDD. Therefore, the PGA_BYPASS bit must

be set in order to measure single-ended signals when a unipolar analog supply is used (AVSS = 0 V). Gains of

1, 2, and 4 are still possible in this configuration. Measuring a 0-mA to 20-mA or 4-mA to 20-mA signal across a

load resistor of 100 Ω referenced to GND is a typical example. The ADS1120-Q1 can directly measure the signal

across the load resistor using a unipolar supply, the internal 2.048-V reference, and gain = 1 when the PGA is

bypassed.

If gains larger than 4 are needed to measure a single-ended signal, the PGA must be enabled. In this case, a

bipolar supply is required for the ADS1120-Q1 to meet the common-mode voltage requirement of the PGA.

Signals where the negative analog input (AIN_N) is fixed at a voltage other the 0 V are referred to as pseudo-

differential signals. The common-mode voltage of a pseudo-differential signal varies between V_(AINN)and V_(AINN)

+

V_IN/ 2.

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Application Information (continued)

Fully-differential signals in contrast are defined as signals having a constant common-mode voltage where the

positive and negative analog inputs swing 180° out-of-phase but have the same amplitude.

The ADS1120-Q1 can measure pseudo-differential and fully-differential signals both with the PGA enabled or

bypassed. However, the PGA must be enabled in order to use gains greater than 4. The common-mode voltage

of the input signal must meet the input-common mode voltage restrictions of the PGA (as explained in the PGA

Common-Mode Voltage Requirements section) when the PGA is enabled. Setting the common-mode voltage at

or near (AVSS + AVDD) / 2 in most cases satisfies the PGA common-mode voltage requirements.

Signals where both the positive and negative inputs are always ≥ 0 V are called unipolar signals. These signals

can in general be measured with the ADS1120-Q1 using a unipolar analog supply (AVSS = 0 V). As mentioned

previously, the PGA must be bypassed in order to measure single-ended, unipolar signals when using a unipolar

supply.

A signal is called bipolar when either the positive or negative input can swing below 0 V. A bipolar analog supply

(such as AVDD = 2.5 V, AVSS = –2.5 V) is required in order to measure bipolar signals with the ADS1120-Q1. A

typical application task is measuring a single-ended, bipolar ±10 V signal where AIN_Nis fixed at 0 V while AIN_P

swings between –10 V and 10 V. The ADS1120-Q1 cannot directly measure this signal because the 10 V

exceeds the analog power-supply limits. However, one possible solution is to use a bipolar analog supply (AVDD

= 2.5 V, AVSS = –2.5 V), gain = 1, and a resistor divider in front of the ADS1120-Q1. The resistor divider must

divide the voltage down to ≤ ±2.048 V to be able to measure it using the internal 2.048-V reference.

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Application Information (continued)

9.1.5 Pseudo Code Example

The following list shows a pseudo code sequence with the required steps to set up the device and the

microcontroller that interfaces to the ADC in order to take subsequent readings from the ADS1120-Q1 in

continuous conversion mode. The dedicated DRDY pin is used to indicate availability of new conversion data.

The default configuration register settings are changed to gain = 16, continuous conversion mode, and

simultaneous 50-Hz and 60-Hz rejection.

Power-up;

Delay to allow power supplies to settle and power-up reset to complete; minimum of 50 µs;

Configure the SPI interface of the microcontroller to SPI mode 1 (CPOL = 0, CPHA = 1);

If the CS pin is not tied low permanently, configure the microcontroller GPIO connected to CS as an output;

Configure the microcontroller GPIO connected to the DRDY pin as a falling edge triggered interrupt input;

Set CS to the device low;

Delay for a minimum of t_d(CSSC)

Send the RESET command (06h) to make sure the device is properly reset after power-up;

Delay for a minimum of 50 µs + 32 · t_(CLK)

;

Write the respective register configuration with the WREG command (43h, 08h, 04h, 10h, and 00h);

As an optional sanity check, read back all configuration registers with the RREG command (23h);

Send the START/SYNC command (08h) to start converting in continuous conversion mode;

Delay for a minimum of t_d(SCCS)

;

Clear CS to high (resets the serial interface);

Loop

{

Wait for DRDY to transition low;

Take CS low;

Delay for a minimum of t_d(CSSC)

;

Send 16 SCLK rising edges to read out conversion data on DOUT/DRDY;

Delay for for a minimum of t_d(SCCS)

;

Clear CS to high;

}

Take CS low;

Delay for a minimum of t_d(CSSC)

Send the POWERDOWN command (02h) to stop conversions and put the device in power-down mode;

;

Delay for a minimum of t_d(SCCS)

Clear CS to high;

;

TI recommends running an offset calibration before performing any measurements or when changing the gain of

the PGA. The internal offset of the device can, for example, be measured by shorting the inputs to mid-supply

(MUX[3:1] = 1110). The microcontroller then takes multiple readings from the device with the inputs shorted and

stores the average value in the microcontroller memory. When measuring the sensor signal, the microcontroller

then subtracts the stored offset value from each device reading to obtain an offset compensated result. Note that

the offset can be either positive or negative in value.

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9.2 Typical Application

9.2.1 K-Type Thermocouple Measurement (–200°C to +1250°C)

Figure 74 shows the basic connections of a thermocouple measurement system when using the internal high-

precision temperature sensor for cold-junction compensation. Apart from the thermocouple itself, the only

external circuitry required are two biasing resistors, a simple low-pass, antialiasing filter, and the power-supply

decoupling capacitors.

3.3 V

0.1 PF

3.3 V

R_B2

REFP0

REFN0

50 ꢀA to

1.5 mA

AVDD

DVDD

C_CM2

R_F2

Internal

Reference

Mux

AIN0

AIN1

Device

C_DIF

R_F1

CS

Digital Filter

and

SCLK

16-bit

ûꢁꢀADC

Thermocouple

Mux

PGA

DIN

R_B1

C_CM1

SPI

DOUT/DRDY

DRDY

Interface

AIN2

AIN3

Low Drift

Oscillator

Precision

Temp Sensor

AVSS

CLK

DGND

Figure 74. Thermocouple Measurement

9.2.1.1 Design Requirements

Table 17. Design Requirements

DESIGN PARAMETER

VALUE

Supply voltage

Reference voltage

3.3 V

Internal 2.048-V reference

≥10 readings per second

K

Update rate

Thermocouple type

Temperature measurement range

Measurement accuracy at T_A= 25°C⁽¹⁾

–200°C to +1250°C

±0.5°C

(1) Not accounting for error of the thermocouple and cold-junction temperature measurement;

offset calibration at T_(TC)= T_(CJ)= 25°C; no gain calibration.

9.2.1.2 Detailed Design Procedure

The biasing resistors R_B1and R_B2are used to set the common-mode voltage of the thermocouple to within the

specified common-mode voltage range of the PGA (in this example, to mid-supply AVDD / 2). If the application

requires the thermocouple to be biased to GND, either a bipolar supply (for example, AVDD = 2.5 V and AVSS =

–2.5 V) must be used for the device to meet the common-mode voltage requirement of the PGA, or the PGA

must be bypassed. When choosing the values of the biasing resistors, care must be taken so that the biasing

current does not degrade measurement accuracy. The biasing current flows through the thermocouple and can

cause self-heating and additional voltage drops across the thermocouple leads. Typical values for the biasing

resistors range from 1 MΩ to 50 MΩ.

In addition to biasing the thermocouple, R_B1and R_B2are also useful for detecting an open thermocouple lead.

When one of the thermocouple leads fails open, the biasing resistors pull the analog inputs (AIN0 and AIN1) to

AVDD and AVSS, respectively. The ADC consequently reads a full-scale value, which is outside the normal

measurement range of the thermocouple voltage, to indicate this failure condition.

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Although the device digital filter attenuates high-frequency components of noise, TI recommends providing a first-

order, passive RC filter at the inputs to further improve performance. The differential RC filter formed by R_F1, R_F2,

and the differential capacitor C_DIFoffers a cutoff frequency that is calculated using Equation 17.

f_C= 1 / [2π · (R_F1+ R_F2) · C_DIF

]

(17)

Two common-mode filter capacitors (C_M1and C_M2) are also added to offer attenuation of high-frequency,

common-mode noise components. TI recommends that the differential capacitor C_DIFbe at least an order of

magnitude (10x) larger than the common-mode capacitors (C_M1and C_M2) because mismatches in the common-

mode capacitors can convert common-mode noise into differential noise.

The filter resistors R_F1and R_F2also serve as current-limiting resistors. These resistors limit the current into the

analog inputs (AIN0 and AIN1) of the device to safe levels if an overvoltage on the inputs occur. Care must be

taken when choosing the filter resistor values because the input currents flowing into and out of the device cause

a voltage drop across the resistors. This voltage drop shows up as an additional offset error at the ADC inputs.

TI recommends limiting the filter resistor values to below 1 kΩ.

The filter component values used in this design are: R_F1= R_F2= 1 kΩ, C_DIF= 100 nF, and C_CM1= C_CM2= 10 nF.

The highest measurement resolution is achieved when matching the largest potential input signal to the FSR of

the ADC by choosing the highest possible gain. From the design requirement, the maximum thermocouple

voltage occurs at T_(TC)= 1250°C and is V_(TC)= 50.644 mV as defined in the tables published by the National

Institute of Standards and Technology (NIST) using a cold-junction temperature of T_(CJ)= 0°C. A thermocouple

produces an output voltage that is proportional to the temperature difference between the thermocouple tip and

the cold junction. If the cold junction is at a temperature below 0°C, the thermocouple produces a voltage larger

than 50.644 mV. The isothermal block area is constrained by the operating temperature range of the device.

Therefore, the isothermal block temperature is limited to –40°C. A K-type thermocouple at T_(TC)= 1250°C

produces an output voltage of V_(TC)= 50.644 mV – (–1.527 mV) = 52.171 mV when referenced to a cold-junction

temperature of T_(CJ)= –40°C. The maximum gain that can be applied when using the internal 2.048-V reference

is then calculated as (2.048 V / 52.171 mV) = 39.3. The next smaller PGA gain setting the device offers is 32.

The device integrates a high-precision temperature sensor that can be used to measure the temperature of the

cold junction. To measure the internal temperature of the ADS1120-Q1, the device must be set to internal

temperature sensor mode by setting the TS bit to 1 in the configuration register. For best performance, careful

board layout is critical to achieve good thermal conductivity between the cold junction and the device package.

However, the device does not perform automatic cold-junction compensation of the thermocouple. This

compensation must be done in the microcontroller that interfaces to the device. The microcontroller requests one

or multiple readings of the thermocouple voltage from the device and then sets the device to internal temperature

sensor mode (TS = 1) to acquire the temperature of the cold junction. An algorithm similar to the following must

be implemented on the microcontroller to compensate for the cold-junction temperature:

1. Measure the thermocouple voltage, V_(TC), between AIN0 and AIN1.

2. Measure the temperature of the cold junction, T_(CJ), using the temperature sensor mode of the ADS1120-Q1.

3. Convert the cold-junction temperature into an equivalent thermoelectric voltage, V_(CJ), using the tables or

equations provided by NIST.

4. Add V_(TC)and V_(CJ)and translate the summation back into a thermocouple temperature using the NIST tables

or equations again.

In some applications, the integrated temperature sensor of the ADS1120-Q1 cannot be used (for example, if the

accuracy is not high enough or if the device cannot be placed close enough to the cold junction). The additional

analog input channels of the device can be used in this case to measure the cold-junction temperature with a

thermistor, RTD, or an analog temperature sensor.

The device is capable of 16-bit, noise-free resolution using a gain of 32, the internal 2.048-V reference, and a

data rate of 20 SPS (see Table 1 and Table 2). Accordingly the device is able to resolve signals as small as one

LSB. The LSB size is calculated using Equation 18:

1 LSB = (2 · V_ref/ Gain) / 2¹⁶= (2 · 2.048 V / 32) / 2¹⁶= 1.953 µV

(18)

To get an approximation of the achievable temperature resolution per ADC code, the LSB size is divided by the

average sensitivity of a K-type thermocouple (41 µV/°C), as shown in Equation 19.

Temperature Resolution per Code = 1.953 µV / 41 µV/°C = 0.05°C

(19)

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The register settings for this design are shown in Table 18.

Table 18. Register Settings

REGISTER

00h

SETTING

0Ah

DESCRIPTION

AIN_P= AIN0, AIN_N= AIN1, gain = 32, PGA enabled

DR = 20 SPS, normal mode, continuous conversion mode

Internal voltage reference, simultaneous 50-Hz and 60-Hz rejection

No IDACs used

01h

04h

02h

10h

03h

00h

9.2.1.3 Application Curves

Figure 75 and Figure 76 show the measurement results. The measurements are taken at T_A= T_(CJ)= 25°C. A

system offset calibration is performed at T_(TC)= 25°C, which translates to a V_(TC)= 0 V when T_(CJ)= 25°C. No

gain calibration is implemented. The data in Figure 75 are taken using a precision voltage source as the input

signal instead of a thermocouple. The respective temperature measurement error in Figure 76 is calculated from

the data in Figure 75 using the NIST tables.

The design meets the required temperature measurement accuracy given in Table 17. Note that the

measurement error shown in Figure 76 does not include the error of the thermocouple itself and the

measurement error of the cold-junction temperature. Those two error sources are in general larger than 0.2°C

and therefore, in many cases, dominate the overall system measurement accuracy.

0.01

0.005

0

0.2

0.1

0

-0.005

-0.1

-0.01

-0.2

-10

0

10

20

30

40

50

-200

0

200

400

600

800

1000

1200

Thermocouple Voltage (mV)

Temperature (°C)

D002

D001

Figure 75. Voltage Measurement Error vs V_(TC)

Figure 76. Temperature Measurement Error vs T_(TC)

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9.2.2 3-Wire RTD Measurement (–200°C to +850°C)

The ADS1120-Q1 integrates all necessary features (such as dual-matched programmable current sources,

buffered reference inputs, and a PGA) to ease the implementation of ratiometric 2-, 3-, and 4-wire RTD

measurements. Figure 77 shows a typical implementation of a ratiometric 3-wire RTD measurement using the

excitation current sources integrated in the device to excite the RTD as well as to implement automatic RTD

lead-resistance compensation.

R_REF

I_IDAC1+ I_IDAC2

3.3 V

R_F3

C_DIF2

R_F4

C_CM3

C_CM4

0.1 PF

50 ꢀA to

1.5 mA

R_LEAD3

R_LEAD2

AVDD

DVDD

REFP0

REFN0

C_CM2

C_DIF1

C_CM1

R_F2

Internal

Reference

Mux

AIN0

AIN1

Device

3-wire RTD

R_LEAD1

R_F1

CS

Digital Filter

and

SPI

Interface

SCLK

16-bit

ûꢁꢀADC

Mux

PGA

DIN

AIN2

DOUT/DRDY

DRDY

(IDAC1)

AIN3

Low Drift

Oscillator

Precision

Temp Sensor

(IDAC2)

AVSS

CLK

DGND

Figure 77. 3-Wire RTD Measurement

9.2.2.1 Design Requirements

Table 19. Design Requirements

DESIGN PARAMETER

VALUE

Supply voltage

Update rate

3.3 V

20 readings per second

3-wire Pt100

15 Ω

RTD type

Maximum RTD lead resistance

RTD excitation current

500 µA

Temperature measurement range

Measurement accuracy at T_A= 25°C⁽¹⁾

–200°C to +850°C

±0.2°C

(1) Not accounting for error of RTD;

offset calibration is performed with R_RTD= 100 Ω; no gain calibration.

9.2.2.2 Detailed Design Procedure

The circuit in Figure 77 employs a ratiometric measurement approach. In other words, the sensor signal (that is,

the voltage across the RTD in this case) and the reference voltage for the ADC are derived from the same

excitation source. Therefore, errors resulting from temperature drift or noise of the excitation source cancel out

because these errors are common to both the sensor signal and the reference.

In order to implement a ratiometric 3-wire RTD measurement using the device, IDAC1 is routed to one of the

leads of the RTD and IDAC2 is routed to the second RTD lead. Both currents have the same value, which is

programmable by the IDAC[2:0] bits in the configuration register. The design of the device ensures that both

IDAC values are closely matched, even across temperature. The sum of both currents flows through a precision,

low-drift reference resistor, R_REF. The voltage, V_ref, generated across the reference resistor (as shown in

Equation 20) is used as the ADC reference voltage. Equation 20 reduces to Equation 21 because I_IDAC1= I_IDAC2

.

V_ref= (I_IDAC1+ I_IDAC2) · R_REF

V_ref= 2 · I_IDAC1· R_REF

(20)

(21)

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To simplify the following discussion, the individual lead resistance values of the RTD (R_LEADx) are set to zero.

Only IDAC1 excites the RTD to produce a voltage (V_RTD) proportional to the temperature-dependable RTD value

and the IDAC1 value, as shown in Equation 22.

V_RTD= R_{RTD (at temperature)}· I_IDAC1

(22)

The device internally amplifies the voltage across the RTD using the PGA and compares the resulting voltage

against the reference voltage to produce a digital output code proportional to Equation 23 through Equation 25:

Code ∝ V_RTD· Gain / V_ref

(23)

(24)

(25)

Code ∝ (R_{RTD (at temperature)}· I_IDAC1· Gain) / (2 · I_IDAC1· R_REF

)

Code ∝ (R_{RTD (at temperature)}· Gain) / (2 · R_REF

)

As can be seen from Equation 25, the output code only depends on the value of the RTD, the PGA gain, and the

reference resistor (R_REF), but not on the IDAC1 value. The absolute accuracy and temperature drift of the

excitation current therefore does not matter. However, because the value of the reference resistor directly affects

the measurement result, choosing a reference resistor with a very low temperature coefficient is important to limit

errors introduced by the temperature drift of R_REF

.

The second IDAC2 is used to compensate for errors introduced by the voltage drop across the lead resistance of

the RTD. All three leads of a 3-wire RTD typically have the same length and, thus, the same lead resistance.

Also, IDAC1 and IDAC2 have the same value. Taking the lead resistance into account, the differential voltage

(V_IN) across the ADC inputs, AIN0 and AIN1, is calculated using Equation 26:

V_IN= I_IDAC1· (R_RTD+ R_LEAD1) – I_IDAC2· R_LEAD2

(26)

When R_LEAD1= R_LEAD2and I_IDAC1= I_IDAC2, Equation 26 reduces to Equation 27:

V_IN= I_IDAC1· R_RTD

(27)

In other words, the measurement error resulting from the voltage drop across the RTD lead resistance is

compensated, as long as the lead resistance values and the IDAC values are well matched.

A first-order differential and common-mode RC filter (R_F1, R_F2, C_DIF1, C_CM1, and C_CM2) is placed on the ADC

inputs, as well as on the reference inputs (R_F3, R_F4, C_DIF2, C_CM3, and C_CM4). The same guidelines for designing

the input filter apply as described in the Thermocouple Measurement section. For best performance, TI

recommends matching the corner frequencies of the input and reference filter. More detailed information on

matching the input and reference filter can be found in application report RTD Ratiometric Measurements and

Filtering Using the ADS1148 and ADS1248 (SBAA201).

The reference resistor R_REFnot only serves to generate the reference voltage for the device, but also sets the

common-mode voltage of the RTD to within the specified common-mode voltage range of the PGA.

When designing the circuit, care must also be taken to meet the compliance voltage requirement of the IDACs.

The IDACs require that the maximum voltage drop developed across the current path to AVSS be equal or less

than AVDD – 0.9 V in order to operate accurately. This requirement means that Equation 28 must be met at all

times.

AVSS + I_IDAC1· (R_LEAD1+ R_RTD) + (I_IDAC1+ I_IDAC2) · (R_LEAD3+ R_REF) ≤ AVDD – 0.9 V

(28)

The device also offers the possibility to route the IDACs to the same inputs used for measurement. If the filter

resistor values R_F1and R_F2are small enough and well matched, IDAC1 can be routed to AIN1 and IDAC2 to

AIN0 in Figure 77. In this manner, even two 3-wire RTDs sharing the same reference resistor can be measured

with a single device.

This design example discusses the implementation of a 3-wire Pt100 measurement to be used to measure

temperatures ranging from –200°C to +850°C as stated in Table 19. The excitation current for the Pt100 is

chosen as I_IDAC1= 500 µA, which means a combined current of 1 mA is flowing through the reference resistor,

R_REF. As mentioned previously, besides creating the reference voltage for the ADS1120-Q1, the voltage across

R_REFalso sets the common-mode voltage for the RTD measurement. In general, choose the largest reference

voltage possible while still maintaining the compliance voltage of the IDACs as well as meeting the common-

mode voltage requirement of the PGA. TI recommends setting the common-mode voltage at or near half the

analog supply (in this case 3.3 V / 2 = 1.65 V), which in most cases satisfies the common-mode voltage

requirements of the PGA. The value for R_REFis then calculated by Equation 29:

R_REF= V_ref/ (I_IDAC1+ I_IDAC2) = 1.65 V / 1 mA = 1.65 kΩ

(29)

51

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ZHCSCV9A –AUGUST 2014–REVISED OCTOBER 2014

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The stability of R_REFis critical to achieve good measurement accuracy over temperature and time. Choosing a

reference resistor with a temperature coefficient of ±10 ppm/°C or better is advisable. If a 1.65 kΩ value is not

readily available, another value near 1.65 kΩ (such as 1.62 kΩ or 1.69 kΩ) can certainly be used as well.

As a last step, the PGA gain must be selected in order to match the maximum input signal to the FSR of the

ADC. The resistance of a Pt100 increases with temperature. Therefore, the maximum voltage to be measured

(V_{IN (MAX)}) occurs at the positive temperature extreme. At 850°C, a Pt100 has an equivalent resistance of

approximately 391 Ω as per the NIST tables. The voltage across the Pt100 equates to Equation 30:

V_{IN (MAX)}= V_{RTD (at 850°C)}= R_{RTD (at 850°C)}· I_IDAC1= 391 Ω · 500 µA = 195.5 mV

(30)

The maximum gain that can be applied when using a 1.65-V reference is then calculated as (1.65 V / 195.5 mV)

= 8.4. The next smaller PGA gain setting available in the ADS1120-Q1 is 8. At a gain of 8, the ADS1120-Q1

offers a FSR value as described in Equation 31:

FSR = ±V_ref/ Gain = ±1.65 V / 8 = ±206.25 mV

(31)

This range allows for margin with respect to initial accuracy and drift of the IDACs and reference resistor.

After selecting the values for the IDACs, R_REF, and PGA gain, make sure to double check that the settings meet

the common-mode voltage requirements of the PGA and the compliance voltage of the IDACs. To determine the

true common-mode voltage at the ADC inputs (AIN0 and AIN1) the lead resistance must be taken into account

as well.

The smallest common-mode voltage occurs at the lowest measurement temperature (–200°C) with R_LEADx= 0 Ω

and is calculated using Equation 32 and Equation 33.

V_{CM (MIN)}= V_ref+ (I_IDAC1+ I_IDAC2) · R_LEAD3+ I_IDAC2· R_LEAD2+ ½ I_IDAC1· R_{RTD (at –200°C)}

(32)

(33)

V_{CM (MIN)}= 1.65 V + ½ 500 µA · 18.52 Ω = 1.655 V

Actually, assuming V_{CM (MIN)}= V_refis a sufficient approximation.

V_{CM (MIN)}must meet two requirements: Equation 15 requires V_{CM (MIN)}to be larger than AVDD / 4 = 3.3 V / 4 =

0.825 V and Equation 13 requires V_{CM (MIN)}to meet Equation 34:

V_{CM (MIN)}≥ AVSS + 0.2 V + ½ Gain · V_{IN (MAX)}= 0 V + 0.2 V + ( ½ · 8 · 195.5 mV) = 982 mV

(34)

Both restrictions are satisfied in this design with a V_{CM (MIN)}= 1.65 V.

The largest common-mode voltage occurs at the highest measurement temperature (850°C) and is calculated

using Equation 35 and Equation 36.

V_{CM (MAX)}= V_ref+ (I_IDAC1+ I_IDAC2) · R_LEAD3+ I_IDAC2· R_LEAD2+ ½ I_IDAC1· R_{RTD (at 850°C)}

(35)

(36)

V_{CM (MAX)}= 1.65 V + 1 mA · 15 Ω + 500 µA · 15 Ω + ½ 500 µA · 391 Ω = 1.77 V

V_{CM (MAX)}does meet the requirement given by Equation 14, which in this design equates to Equation 37:

V_{CM (MAX)}≤ AVDD – 0.2 V – ½ Gain · V_{IN (MAX)}= 3.3 V – 0.2 V – ( ½ · 8 · 195.5 mV) = 2.318 V

(37)

Finally, the maximum voltage that can occur on input AIN1 must be calculated to determine if the compliance

voltage (AVDD – 0.9 V = 3.3 V – 0.9 V = 2.4 V) of IDAC1 is met. Note that the voltage on input AIN0 is smaller

than the one on input AIN1. Equation 38 and Equation 39 show that the voltage on AIN1 is less than 2.4 V, even

when taking the worst-case lead resistance into account.

V_{AIN1 (MAX)}= V_ref+ (I_IDAC1+ I_IDAC2) · R_LEAD3+ I_IDAC1· (R_{RTD (at 850°C)}+ R_LEAD1

)

(38)

(39)

V_{AIN1 (MAX)}= 1.65 V + 1 mA · 15 Ω + 500 µA · (391 Ω + 15 Ω) = 1.868 V

The register settings for this design are shown in Table 20.

Table 20. Register Settings

REGISTER

00h

SETTING

66h

DESCRIPTION

AIN_P= AIN1, AIN_N= AIN0, gain = 8, PGA enabled

01h

04h

DR = 20 SPS, normal mode, continuous conversion mode

External reference (REFP0, REFN0), simultaneous 50-Hz and 60-Hz

rejection, IDAC = 500 µA

02h

03h

55h

70h

IDAC1 = AIN2, IDAC2 = AIN3

52

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9.2.2.2.1 Design Variations for 2-Wire and 4-Wire RTD Measurements

Implementing a 2- or 4-wire RTD measurement is very similar to the 3-wire RTD measurement illustrated in

Figure 77, except that only one IDAC is required.

Figure 78 shows a typical circuit implementation of a 2-wire RTD measurement. The main difference compared

to a 3-wire RTD measurement is with respect to the lead resistance compensation. The voltage drop across the

lead resistors, R_LEAD1and R_LEAD2, in this configuration is directly part of the measurement (as shown in

Equation 40) because there is no means to compensate the lead resistance by use of the second current source.

Any compensation must be done by calibration.

V_IN= I_IDAC1· (R_LEAD1+ R_RTD+ R_LEAD2

)

(40)

R_REF

I_IDAC1

3.3 V

R_F3

R_F4

C_CM3

C_DIF2

C_CM4

0.1 PF

50 ꢀA to

1.5 mA

AVDD

DVDD

REFP0

REFN0

C_CM2

C_DIF1

C_CM1

R_LEAD2

R_F2

Internal

Reference

Mux

AIN0

Device

2-wire RTD

R_LEAD1

R_F1

AIN1

AIN2

CS

Digital Filter

and

SPI

Interface

SCLK

16-bit

ûꢁꢀADC

Mux

PGA

DIN

DOUT/DRDY

DRDY

AIN3

Low Drift

Oscillator

Precision

Temp Sensor

(IDAC1)

AVSS

CLK

DGND

Figure 78. 2-Wire RTD Measurement

Figure 79 shows a typical circuit implementation of a 4-wire RTD measurement. Similar to the 2-wire RTD

measurement, only one IDAC is required for exciting and measuring a 4-wire RTD in a ratiometric manner. The

main benefit of using a 4-wire RTD is that the ADC inputs are connected to the RTD in the form of a Kelvin

connection. Apart from the input leakage currents of the ADC, there is no current flow through the lead resistors

R_LEAD2and R_LEAD3and therefore no voltage drop is created across them. The voltage at the ADC inputs

consequently equals the voltage across the RTD and the lead resistance is of no concern.

R_REF

I_IDAC1

3.3 V

R_F3

C_DIF2

R_F4

C_CM3

C_CM4

0.1 PF

50 ꢀA to

1.5 mA

R_LEAD4

R_LEAD3

AVDD

DVDD

REFP0

REFN0

C_CM2

C_DIF1

C_CM1

R_F2

Internal

Reference

Mux

AIN0

AIN1

AIN2

Device

4-wire RTD

R_LEAD2

R_F1

CS

Digital Filter

and

SPI

Interface

SCLK

16-bit

ûꢁꢀADC

Mux

PGA

DIN

R_LEAD1

DOUT/DRDY

DRDY

AIN3

Low Drift

Oscillator

Precision

Temp Sensor

(IDAC1)

AVSS

CLK

DGND

Figure 79. 4-Wire RTD Measurement

53

ADS1120-Q1

ZHCSCV9A –AUGUST 2014–REVISED OCTOBER 2014

www.ti.com.cn

Note that because only one IDAC is used and flows through the reference resistor, R_REF, the transfer function of

a 2- and 4-wire RTD measurement differs compared to the one of a 3-wire RTD measurement by a factor of 2,

as shown in Equation 41.

Code ∝ (R_{RTD (at Temperature)}· Gain) / R_REF

(41)

In addition, the common-mode and reference voltage is reduced compared to the 3-wire RTD configuration.

Therefore, some further modifications may be required in case the 3-wire RTD design is used to measure 2- and

4-wire RTDs as well. If the decreased common-mode voltage does not meet the V_{CM (MIN)}requirements of the

PGA anymore, either increase the value of R_REFby switching in a larger resistor or, alternatively, increase the

excitation current while decreasing the gain at the same time.

9.2.2.3 Application Curves

Figure 80 and Figure 81 show the measurement results. The measurements are taken at T_A= 25°C. A system

offset calibration is performed using a reference resistor of 100 Ω. No gain calibration is implemented. The data

in Figure 80 are taken using precision resistors instead of a 3-wire Pt100. The respective temperature

measurement error in Figure 81 is calculated from the data in Figure 80 using the NIST tables.

The design meets the required temperature measurement accuracy given in Table 19. Note that the

measurement error shown in Figure 81 does not include the error of the RTD itself.

0.1

0.05

0

0.2

0.1

0

-0.05

-0.1

-0.2

0

50

100

150

200

250

300

350

400

-200

0

200

400

600

800

1000

RTD Value (:)

Temperature (°C)

D003

D004

Figure 80. Resistance Measurement Error vs R_RTD

Figure 81. Temperature Measurement Error vs T_(RTD)

54

ADS1120-Q1

www.ti.com.cn

ZHCSCV9A –AUGUST 2014–REVISED OCTOBER 2014

9.2.3 Bridge Measurement

The device offers several features to ease the implementation of ratiometric bridge measurements (such as a

PGA with gains up to 128, buffered, differential reference inputs, and a low-side power switch).

5.0 V

3.3 V

0.1 PF

REFP0

REFN0

50 ꢀA to

1.5 mA

AVDD

DVDD

5.0 V

Internal

Reference

Mux

REFP1

AIN1

Device

C_CM2

C_DIF1

C_CM1

R_F2

CS

Digital Filter

and

SPI

Interface

SCLK

16-bit

ûꢁꢀADC

C_DIF2

Mux

PGA

DIN

R_F1

AIN2

DOUT/DRDY

DRDY

REFN1

Low Drift

Oscillator

Precision

Temp Sensor

AVSS

CLK

DGND

Figure 82. Bridge Measurement

9.2.3.1 Design Requirements

Table 21. Design Requirements

DESIGN PARAMETER

VALUE

Analog supply voltage

Digital supply voltage

Load cell type

5.0 V

3.3 V

4-wire load cell

2 mV/V

5 V

Load cell sensitivity

Excitation voltage

Noise-free counts

8000

9.2.3.2 Detailed Design Procedure

To implement a ratiometric bridge measurement, the bridge excitation voltage is simultaneously used as the

reference voltage for the ADC; see Figure 82. With this configuration, any drift in excitation voltage also shows

up on the reference voltage, consequently canceling out drift error. Either of the two device reference input pairs

can be connected to the bridge excitation voltage. However, only the negative reference input (REFN1) can be

internally routed to a low-side power switch. By connecting the low side of the bridge to REFN1, the device can

automatically power-down the bridge by opening the low-side power switch. When the PSW bit in the

configuration register is set to 1, the device opens the switch every time a POWERDOWN command is issued

and closes the switch again when a START/SYNC command is sent.

The PGA offers gains up to 128, which helps amplify the small differential bridge output signal to make optimal

use of the ADC full-scale range. Using a symmetrical bridge with the excitation voltage equal to the supply

voltage of the device ensures that the output signal of the bridge meets the common-mode voltage requirement

of the PGA.

Note that the maximum input voltage of ADS1120-Q1 is limited to V_{IN (MAX)}= ±[(AVDD – AVSS) – 0.4 V] / Gain,

which means the entire full-scale range, FSR = ±(AVDD – AVSS) / Gain, cannot be used in this configuration.

This limitation is a result of the output drive capability of the PGA amplifiers (A1 and A2); see Figure 39. The

output of each amplifier must stay 200 mV away from the rails (AVDD and AVSS), otherwise the PGA becomes

nonlinear. Consequently, the maximum output swing of the PGA is limited to V_OUT= ±[(AVDD – AVSS) – 0.4 V].

55

ADS1120-Q1

ZHCSCV9A –AUGUST 2014–REVISED OCTOBER 2014

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Using a 2-mV/V load cell with a 5-V excitation yields a maximum differential output voltage of V_{IN (MAX)}= ±10 mV,

which meets Equation 42 when using a gain of 128.

V_{IN (MAX)}≤ ±[(AVDD – AVSS) – 0.4 V] / Gain = ±(5 V – 0.4 V) / 128 = ±36 mV

(42)

A first-order differential and common-mode RC filter (R_F1, R_F2, C_DIF1, C_CM1, and C_CM2) is placed on the ADC

inputs. The reference has an additional capacitor C_DIF2to limit reference noise. Care must be taken to maintain a

limited amount of filtering or the measurement will no longer be ratiometric.

The device is capable of 16-bit, noise-free resolution using a gain of 128 at 20 SPS for the specified reference

voltage. Accordingly the device is able to resolve signals as small as one LSB. The LSB size is calculated using

Equation 43:

1 LSB = (2 · V_ref/ Gain) / 2¹⁶= (2 · 5.0 V / 128) / 2¹⁶= 1.192 µV

(43)

To find the total number of counts available for the bridge measurement, the maximum output voltage is divided

by the LSB value. Dividing 10 mV by 1.192 µV equates to 8389 total counts available, which meets the design

parameter of 8000 counts.

The register settings for this design are shown in Table 22.

Table 22. Register Settings

REGISTER

00h

SETTING

3Eh

DESCRIPTION

AIN_P= AIN1, AIN_N= AIN2, gain = 128, PGA enabled

DR = 20 SPS, normal mode, continuous conversion mode

01h

04h

External reference (REFP1, REFN1), simultaneous 50-Hz and 60-Hz

rejection, PSW = 1

02h

03h

98h

00h

No IDACs used

56

ADS1120-Q1

www.ti.com.cn

ZHCSCV9A –AUGUST 2014–REVISED OCTOBER 2014

10 Power-Supply Recommendations

The device requires two power supplies: analog (AVDD, AVSS) and digital (DVDD, DGND). The analog power

supply can be bipolar (for example, AVDD = 2.5 V, AVSS = –2.5 V) or unipolar (for example, AVDD = 3.3 V,

AVSS = 0 V) and is independent of the digital power supply. The digital supply sets the digital I/O levels.

10.1 Power-Supply Sequencing

The power supplies can be sequenced in any order but in no case must any analog or digital inputs exceed the

respective analog or digital power-supply voltage limits. Wait approximately 50 µs after all power supplies are

stabilized before communicating with the device to allow the power-up reset process to complete.

10.2 Power-Supply Decoupling

Good power-supply decoupling is important to achieve optimum performance. AVDD, AVSS (when using a

bipolar supply) and DVDD must be decoupled with at least a 0.1-µF capacitor, as shown in Figure 83 and

Figure 84. Place the bypass capacitors as close to the power-supply pins of the device as possible using low-

impedance connections. TI recommends using multi-layer ceramic chip capacitors (MLCCs) that offer low

equivalent series resistance (ESR) and inductance (ESL) characteristics for power-supply decoupling purposes.

For very sensitive systems, or for systems in harsh noise environments, avoiding the use of vias for connecting

the capacitors to the device pins may offer superior noise immunity. The use of multiple vias in parallel lowers

the overall inductance and is beneficial for connections to ground planes. TI recommends connecting analog and

digital ground together as close to the device as possible.

1

2

3

4

5

6

7

8

SCLK

CS

DIN 16

DOUT/DRDY 15

DRDY 14

1

2

3

4

5

6

7

8

SCLK

CS

DIN 16

DOUT/DRDY 15

DRDY 14

3.3 V

CLK

DGND

AVSS

DVDD 13

DGND

AVSS

DVDD 13

Device

AVDD 12

3.3 V

-2.5 V

AVDD 12

2.5 V

0.1 PF

AIN3/REFN1 AIN0/REFP1 11

0.1 PF

AIN2

AIN1 10

REFP0

AIN2

AIN1 10

REFP0

REFN0

9

REFN0

9

Figure 83. Unipolar Analog Power Supply

Figure 84. Bipolar Analog Power Supply

57

ADS1120-Q1

ZHCSCV9A –AUGUST 2014–REVISED OCTOBER 2014

www.ti.com.cn

11 Layout

11.1 Layout Guidelines

TI recommends employing best design practices when laying out a printed circuit board (PCB) for both analog

and digital components. This recommendation generally means that the layout separates analog components

[such as ADCs, amplifiers, references, digital-to-analog converters (DACs), and analog MUXs] from digital

components [such as microcontrollers, complex programmable logic devices (CPLDs), field-programmable gate

arrays (FPGAs), radio frequency (RF) transceivers, universal serial bus (USB) transceivers, and switching

regulators]. An example of good component placement is shown in Figure 85. Although Figure 85 provides a

good example of component placement, the best placement for each application is unique to the geometries,

components, and PCB fabrication capabilities employed. That is, there is no single layout that is perfect for every

design and careful consideration must always be used when designing with any analog component.

Ground fill or

Ground plane

Ground fill or

Ground plane

Supply

Generation

Signal

Conditioning

(RC filters

and

Interface

Tranceiver

Device

Microcontroller

Connector

or Antenna

amplifiers)

Ground fill or

Ground plane

Ground fill or

Ground plane

Figure 85. System Component Placement

The use of split analog and digital ground planes is not necessary for improved noise performance (although for

thermal isolation this option is a worthwhile consideration). However, the use of a solid ground plane or ground

fill in PCB areas with no components is essential for optimum performance. If the system being used employs a

split digital and analog ground plane, TI generally recommends that the ground planes be connected together as

close to the device as possible. A two-layer board is possible using common grounds for both analog and digital

grounds. Additional layers can be added to simplify PCB trace routing. Ground fill may also reduce EMI and RFI

issues.

TI also strongly recommends that digital components, especially RF portions, be kept as far as practically

possible from analog circuitry in a given system. Additionally, minimize the distance that digital control traces run

through analog areas and avoid placing these traces near sensitive analog components. Digital return currents

usually flow through a ground path that is as close to the digital path as possible. If a solid ground connection to

a plane is not available, these currents may find paths back to the source that interfere with analog performance.

The implications that layout has on the temperature-sensing functions are much more significant than for ADC

functions.

Supply pins must be bypassed to ground with a low-ESR ceramic capacitor. The optimum placement of the

bypass capacitors is as close as possible to the supply pins. If AVSS is connected to a negative supply, then

connect an additional bypass capacitor from AVSS to AGND as well. The ground-side connections of the bypass

capacitors must be low-impedance connections for optimum performance. The supply current flows through the

bypass capacitor terminal first and then to the supply pin to make the bypassing most effective.

Analog inputs with differential connections must have a capacitor placed differentially across the inputs. Best

input combinations for differential measurements are AIN0, AIN1 and AIN2, AIN3. The differential capacitors

must be of high quality. The best ceramic chip capacitors are C0G (NPO), which have stable properties and low

noise characteristics. Thermally isolate a copper region around the thermocouple input connections to create a

thermally-stable cold junction. Obtaining acceptable performance with alternate layout schemes is possible as

long as the above guidelines are followed.

58

ADS1120-Q1

www.ti.com.cn

ZHCSCV9A –AUGUST 2014–REVISED OCTOBER 2014

11.2 Layout Example

Vias connect to either the bottom layer or

an internal plane. The bottom layer or

internal plane are dedicated GND planes

(GND = DGND = AVSS).

AIN1

AIN2

AIN3

AIN0

9: REFP0

8: REFN0

10: AIN1

11: AIN0

7: AIN2

6: AIN3

5: AVSS

4: DGND

3: CLK

12: AVDD

13: DVDD

14: DRDY

15: DOUT

16: DIN

AVDD

DVDD

2: CS

1: SCLK

Figure 86. Layout Example

59

ADS1120-Q1

ZHCSCV9A –AUGUST 2014–REVISED OCTOBER 2014

www.ti.com.cn

12 器件和文档支持

12.1 文档支持

12.1.1 相关文档ꢀ

REF5020A-Q1 数据表，SBOS456

《采用 ADS1148 和 ADS1248 进行 RTD 比率测量和滤波》应用报告，SBAA201

12.2 商标

SPI is a trademark of Motorola, Inc.

All other trademarks are the property of their respective owners.

12.3 静电放电警告

ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可

能会损坏集成电路。

ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可

能会导致器件与其发布的规格不相符。

12.4 术语表

SLYZ022 — TI 术语表。

这份术语表列出并解释术语、首字母缩略词和定义。

13 机械封装和可订购信息

以下页中包括机械封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知且不对

本文档进行修订的情况下发生改变。欲获得该数据表的浏览器版本，请查阅左侧的导航栏。

60

PACKAGE MATERIALS INFORMATION

www.ti.com

16-Feb-2022

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

ADS1120QPWRQ1

TSSOP

PW

16

2000

330.0

12.4

6.9

5.6

1.6

8.0

12.0

Q1

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

16-Feb-2022

*All dimensions are nominal

Device

Package Type Package Drawing Pins

TSSOP PW 16

SPQ

Length (mm) Width (mm) Height (mm)

367.0 367.0 35.0

ADS1120QPWRQ1

2000

Pack Materials-Page 2

PACKAGE OUTLINE

PW0016A

TSSOP - 1.2 mm max height

S

C

A

L

E

2

.

5

0

SMALL OUTLINE PACKAGE

SEATING

PLANE

C

6.6

6.2

TYP

A

0.1 C

PIN 1 INDEX AREA

14X 0.65

16

1

2X

5.1

4.9

4.55

NOTE 3

8

9

0.30

16X

4.5

4.3

NOTE 4

1.2 MAX

0.19

B

0.1

C A B

(0.15) TYP

SEE DETAIL A

0.25

GAGE PLANE

0.15

0.05

0.75

0.50

A

20

0 -8

DETAIL A

TYPICAL

4220204/A 02/2017

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.15 mm per side.

4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.

5. Reference JEDEC registration MO-153.

www.ti.com

EXAMPLE BOARD LAYOUT

PW0016A

TSSOP - 1.2 mm max height

SMALL OUTLINE PACKAGE

SYMM

16X (1.5)

(R0.05) TYP

16

1

16X (0.45)

SYMM

14X (0.65)

8

9

(5.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE: 10X

METAL UNDER

SOLDER MASK

OPENING

SOLDER MASK

OPENING

METAL

EXPOSED METAL

0.05 MAX

ALL AROUND

0.05 MIN

ALL AROUND

NON-SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

15.000

(PREFERRED)

SOLDER MASK DETAILS

4220204/A 02/2017

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com

EXAMPLE STENCIL DESIGN

PW0016A

TSSOP - 1.2 mm max height

SMALL OUTLINE PACKAGE

16X (1.5)

SYMM

(R0.05) TYP

16

1

16X (0.45)

SYMM

14X (0.65)

8

9

(5.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE: 10X

4220204/A 02/2017

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

9. Board assembly site may have different recommendations for stencil design.

www.ti.com

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型号：	ADS1120-Q1
厂家：	TEXAS INSTRUMENTS
描述：	适用于小信号传感器且具有 PGA 和基准电压的汽车类、16 位、2kSPS、4 通道、低功耗 Δ-Σ ADC 传感器
文件：	总67页 (文件大小：3046K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ADS1120-Q1 [TI]

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