ADS1191_14_技术文档

ADS1191

ADS1192

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SBAS566 –DECEMBER 2011

Low-Power, 2-Channel, 16-Bit Analog Front-End for Biopotential Measurements

Check for Samples: ADS1191, ADS1192

The ADS1191/2 incorporate all of the features that

1

FEATURES

are commonly required in portable, low-power

medical electrocardiogram (ECG), sports, and fitness

applications.

23

•

Two Low-Noise PGAs and

Two High-Resolution ADCs (ADS1192)

•

Low Power: 335 μW/channel

With its high levels of integration and exceptional

performance, the ADS1191/2 family enables the

creation of scalable medical instrumentation systems

at significantly reduced size, power, and overall cost.

Input-Referred Noise: 24 μV_PP

(150-Hz BW, G = 6)

•

Input Bias Current: 1 nA

Data Rate: 125 SPS to 8 kSPS

CMRR: –95 dB

The ADS1191/2 have a flexible input multiplexer per

channel that can be independently connected to the

internally-generated signals for test, temperature, and

lead-off detection. Additionally, any configuration of

input channels can be selected for derivation of the

right leg drive (RLD) output signal. The ADS1191/2

operate at data rates up to 8 kSPS. Lead-off

detection can be implemented internal to the device,

using the device internal excitation current

sink/source.

Programmable Gain: 1, 2, 3, 4, 6, 8, or 12

Supplies: Unipolar or Bipolar

–

Analog: 2.7 V to 5.25 V

Digital: 1.7 V to 3.6 V

•

Built-In Right Leg Drive Amplifier, Lead-Off

Detection, Test Signals

•

Built-In Oscillator and Reference

The devices are packaged in a 5-mm × 5-mm, 32-pin

thin quad flat pack (TQFP). Operating temperature is

specified from –40°C to +85°C.

Flexible Power-Down, Standby Mode

SPI™-Compatible Serial Interface

REF

Operating Temperature Range: –40°C to +85°C

Test Signals and

Monitors

Reference

APPLICATIONS

SPI

•

Medical Instrumentation (ECG) including:

–

Patient monitoring; Holter, event, stress,

and vital signs including ECG, AED,

telemedicine

ADC1

ADC2

A1

A2

Oscillator

MUX

Control

–

Sports and fitness (heart rate, respiration,

and ECG)

To Channel

DESCRIPTION

The ADS1191/2 are

a family of multichannel,

simultaneous sampling, 16-bit, delta-sigma (ΔΣ)

analog-to-digital converters (ADCs) with a built-in

programmable gain amplifier (PGA), internal

reference, and an onboard oscillator.

RLD

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2

3

SPI is a trademark of Motorola.

All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

ADS1191

ADS1192

SBAS566 –DECEMBER 2011

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This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

FAMILY AND ORDERING INFORMATION⁽¹⁾

MAXIMUM

SAMPLE RATE

(kSPS)

OPERATING

TEMPERATURE

RANGE

PACKAGE

OPTION

NUMBER OF

CHANNELS

ADC

RESOLUTION

RESPIRATION

CIRCUITRY

PRODUCT

ADS1191IPBS

ADS1192IPBS

ADS1291IPBS

ADS1292IPBS

ADS1292RIPBS

TQFP

1

2

1

2

16

24

8

–40°C to +85°C

No

Yes

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the

device product folder at www.ti.com.

ABSOLUTE MAXIMUM RATINGS⁽¹⁾

Over operating free-air temperature range, unless otherwise noted.

ADS1191, ADS1192

UNIT

V

AVDD to AVSS

–0.3 to +7

DVDD to DGND

–0.3 to +7

V

AGND to DGND

–0.3 to +0.3

V

Analog input to AVSS

Digital input to DVDD

Input current to any pin except supply pins⁽²⁾

AVSS – 0.3 to AVDD + 0.3

V

DVSS – 0.3 to DVDD + 0.3

V

±10

±100

mA

°C

Momentary

Input current

Continuous

±10

Operating temperature range Industrial-grade devices only

Storage temperature range

–40 to +85

–60 to +150

+150

Maximum junction temperature (T_J)

Human body model (HBM)

JEDEC standard 22, test method A114-C.01, all pins

±1000

±500

V

ESD ratings

Charged device model (CDM)

JEDEC standard 22, test method C101, all pins

(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may

degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond

those specified is not implied.

(2) Input terminals are diode-clamped to the power-supply rails. Input signals that can swing beyond the supply rails must be current limited

to 10 mA or less.

2

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ELECTRICAL CHARACTERISTICS

Minimum and maximum specifications apply from –40°C to +85°C. Typical specifications are at +25°C. All specifications at

DVDD = 1.8 V, AVDD – AVSS = 3 V⁽¹⁾, V_REF= 2.42 V, external f_CLK= 512 kHz, data rate = 500 SPS, C_FILTER= 4.7 nF⁽²⁾, and

gain = 6, unless otherwise noted.

ADS1191, ADS1192

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

ANALOG INPUTS

Full-scale differential input voltage

(AINP – AINN)

±V_REF/GAIN

V

See the Input Common-Mode Range

subsection of the PGA Settings and

Input Range section

Input common-mode range

Input capacitance

20

pF

nA

MΩ

Input = 1.5 V

±1

Input bias current

Input = 1.5 V, T_A= –40°C to +85°C

±2

No lead-off

1000

Current source lead-off detection (nA range),

AVSS + 0.3 V < AIN < AVDD – 0.3 V

500

100

MΩ

DC input impedance

Current source lead-off detection (µA range),

AVSS + 0.6 V < AIN < AVDD – 0.6 V

PGA PERFORMANCE

Gain settings

1, 2, 3, 4, 6, 8, 12

8.5

With a 4.7-nF capacitor on PGA output

(see PGA Settings and Input Range section

for details)

BW

Bandwidth

kHz

ADC PERFORMANCE

Resolution

16

125

Bits

DR

Data rate

8000

25

SPS

CHANNEL PERFORMANCE (DC Performance)

Gain = 6⁽³⁾, 10 seconds of data

24.6

μV_PP

Gain = 6, 256 points, 0.5 seconds of data

Input-referred noise

Gain settings other than 6, data rate other

than 500 SPS

See Noise Measurements section

INL

Integral nonlinearity

Input-referred offset error

Input-referred offset error drift

Offset error with calibration

Gain error

Full-scale with gain = 6, best fit

±1

±100

2

LSB

μV

μV/°C

μV

15

Excluding voltage reference error

Excluding voltage reference drift

±0.5

5

% of FS

ppm/°C

% of FS

Gain drift

Gain match between channels

1

CHANNEL PERFORMANCE (AC performance)

CMRR

PSRR

Common-mode rejection ratio

Power-supply rejection ratio

Crosstalk

f_CM= 50 Hz, 60 Hz⁽⁴⁾

f_PS= 50 Hz, 60 Hz

f_IN= 50 Hz, 60 Hz

–95

dB

90

–120

96

SNR

THD

Signal-to-noise ratio

f_IN= 10 Hz input, gain = 6

10 Hz, –0.5 dBFs

Total harmonic distortion

–100

(1) Performance is applicable for 5-V operation as well. Production testing for limits is performed at 3 V.

(2) C_FILTERis the capacitor accross the PGA outputs; see the PGA Settings and Input Range section for details.

(3) Noise data measured in a 10-second interval. Test not performed in production. Input-referred noise is calculated with input shorted

(without electrode resistance) over a 10-second interval.

(4) CMRR is measured with a common-mode signal of AVSS + 0.3 V to AVDD – 0.3 V. The values indicated are the minimum of the eight

channels.

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ELECTRICAL CHARACTERISTICS (continued)

Minimum and maximum specifications apply from –40°C to +85°C. Typical specifications are at +25°C. All specifications at

DVDD = 1.8 V, AVDD – AVSS = 3 V⁽¹⁾, V_REF= 2.42 V, external f_CLK= 512 kHz, data rate = 500 SPS, C_FILTER= 4.7 nF⁽²⁾, and

gain = 6, unless otherwise noted.

ADS1191, ADS1192

PARAMETER

RIGHT LEG DRIVE (RLD) AMPLIFIER

Integrated noise

TEST CONDITIONS

MIN

TYP

MAX

UNIT

BW = 150 Hz

1.4

100

0.07

–85

μV_RMS

kHz

V/μs

dB

GBP

SR

Gain bandwidth product

Slew rate

50 kΩ || 10 pF load, gain = 1

f_IN= 100 Hz, gain = 1

THD

CMIR

Total harmonic distortion

Common-mode input range

Common-mode resistor matching

Short-circuit current

AVSS + 0.3

AVDD – 0.3

V

Internal 200-kΩ resistor matching

0.1

1.1

5

%

I_SC

mA

μA

Quiescent power consumption

RLD amplifier

LEAD-OFF DETECT

Frequency

See Register Map section for settings

ILEAD_OFF [1:0] = 00

0, f_DR/4

kHz

nA

μA

%

6

22

ILEAD_OFF [1:0] = 01

Current

ILEAD_OFF [1:0] = 10

6

ILEAD_OFF [1:0] = 11

22

Current accuracy

Comparator threshold accuracy

EXTERNAL REFERENCE

±20

±30

mV

AVDD = 3 V, V_REF= (VREFP – VREFN)

AVDD = 5 V, V_REF= (VREFP – VREFN)

2

2.5

4

VDD – 0.3

V

Reference input voltage

VREFN

VREFP

Negative input

Positive input

AVSS

V

AVSS + 2.5

120

V

Input impedance

kΩ

INTERNAL REFERENCE

CONFIG2.VREF_4V = 0

CONFIG2.VREF_4V = 1

Available for external use

2.42

4.033

100

V

Output voltage

Output current drive

µA

V_REFaccuracy

±0.5

45

%

Internal reference drift

ppm/°C

Settled to 0.2% with 10-µF capacitor on

VREFP pin

Start-up time

100

20

ms

Quiescent current consumption

µA

4

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SBAS566 –DECEMBER 2011

ELECTRICAL CHARACTERISTICS (continued)

Minimum and maximum specifications apply from –40°C to +85°C. Typical specifications are at +25°C. All specifications at

DVDD = 1.8 V, AVDD – AVSS = 3 V⁽¹⁾, V_REF= 2.42 V, external f_CLK= 512 kHz, data rate = 500 SPS, C_FILTER= 4.7 nF⁽²⁾, and

gain = 6, unless otherwise noted.

ADS1191, ADS1192

PARAMETER

SYSTEM MONITORS

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Analog supply reading error

Digital supply reading error

2

%

From power supply ramp after power-on-reset

to DRDY low

32

ms

Device wake up

From power-down mode to DRDY low

From STANDBY mode to DRDY low

1% accuracy with 1-µF capacitor

T_A= +25°C

10

ms

VCAP1 settling time

0.5

145

490

s

Voltage

mV

μV/°C

Temperature sensor

reading

Coefficient

TEST SIGNAL

Signal frequency

Signal voltage

Accuracy

See Register Map section for settings

At dc and 1 Hz

Hz

mV

%

±1

±2

CLOCK

Nominal frequency

T_A= +25°C

512

kHz

%

Internal oscillator clock frequency

±0.5

±1.5

–40°C ≤ T_A≤ +85°C

%

Internal oscillator start-up time

32

30

μs

Internal oscillator power consumption

μW

kHz

MHz

CLKSEL pin = 0, CLK_DIV = 0

CLKSEL pin = 0, CLK_DIV = 1

485

512

562.5

2.25

External clock input frequency

1.94

2.048

DIGITAL INPUT/OUTPUT (DVDD = 1.8 V to 3.6 V)

V_IH(DVDD =

1.8 V to 3.6 V)

0.8 DVDD

–0.1

DVDD + 0.1

0.2 DVDD

V

V_IL(DVDD =

1.8 V to 3.6 V)

Logic level

V_IH(DVDD =

1.7 V to 1.8 V)

DVDD – 0.2

V_IL(DVDD =

1.7 V to 1.8 V)

0.2

V

Input current (I_IN

)

0 V < V_DigitalInput< DVDD

–10

+10

μA

POWER-SUPPLY REQUIREMENTS (RLD Amplifiers Turned Off)

AVDD

DVDD

Analog supply

Digital supply

AVDD – DVDD

AVDD – AVSS

2.7

1.7

3

5.25

3.6

V

1.8

–2.1

3.6

SUPPLY CURRENT

AVDD – AVSS = 3 V

AVDD – AVSS = 5 V

DVDD = 3.3 V

205

250

75

µA

I_AVDD

Normal mode

I_DVDD

DVDD = 1.8 V

32

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ELECTRICAL CHARACTERISTICS (continued)

Minimum and maximum specifications apply from –40°C to +85°C. Typical specifications are at +25°C. All specifications at

DVDD = 1.8 V, AVDD – AVSS = 3 V⁽¹⁾, V_REF= 2.42 V, external f_CLK= 512 kHz, data rate = 500 SPS, C_FILTER= 4.7 nF⁽²⁾, and

gain = 6, unless otherwise noted.

ADS1191, ADS1192

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

740

UNIT

POWER DISSIPATION (Analog Supply = 3 V, RLD Turned Off)

Normal mode

ADS1192/2R

670

160

450

160

350

µW

Standby mode

Normal mode

Standby mode

Normal mode

Quiescent power

dissipation

495

ADS1191

Quiescent power

dissipation, per

channel

ADS1192

ADS1191

Normal mode

400

µW

POWER DISSIPATION (Analog Supply = 5 V, RLD Turned Off)

Normal mode

ADS1192

1300

340

950

340

670

µW

Standby mode

Quiescent power

dissipation

Normal mode

ADS1191

Standby mode

Quiescent power

dissipation, per

channel

ADS1192

ADS1191

Normal mode

860

µW

POWER DISSIPATION IN POWER-DOWN MODE

DVDD = 1.8 V

Analog supply = 3 V

1

4

µW

DVDD = 3.3 V

DVDD = 1.8 V

Analog supply = 5 V

5

DVDD = 3.3 V

10

TEMPERATURE

Specified temperature range

Operating temperature range

Storage temperature range

–40

–60

+85

°C

+150

THERMAL INFORMATION

ADS1191,

ADS1192

THERMAL METRIC⁽¹⁾

UNITS

PBS (TQFP)

32 PINS

68.4

θ_JA

Junction-to-ambient thermal resistance

θ_JCtop

θ_JB

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

25.9

30.5

°C/W

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

0.5

ψ_JB

24.3

θ_JCbot

N/A

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

6

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PARAMETER MEASUREMENT INFORMATION

NOISE MEASUREMENTS

The ADS1191/2 noise performance can be optimized by adjusting the data rate and PGA setting. As the

averaging is increased by reducing the data rate, the noise drops correspondingly. Increasing the PGA value

reduces the input-referred noise, which is particularly useful when measuring low-level biopotential signals.

Table 1 and Table 2 summarize the noise performance of the ADS1191/2. The data are representative of typical

noise performance at T_A= +25°C. The data shown are the result of averaging the readings from multiple devices

and are measured with the inputs shorted together.

Table 1 and Table 2 show measurements taken with an internal reference. The data are also representative of

the ADS1191/2 noise performance when using a low-noise external reference such as the REF5025.

Table 1. Input-Referred Noise (μV_PP) 3-V Analog Supply and 2.42-V Reference⁽¹⁾

PGA GAIN

DR BITS OF

CONFIG1

REGISTER

OUTPUT

DATA RATE

(SPS)

x1

x2

μV_PP

73.9

x3

μV_PP

49.2

x4

x6

x8

x12

μV_PP

12.3

18.5

67.5

325.0

–3-dB BANDWIDTH

(Hz)

μV_PP

36.9

55.4

202.5

975.0

μV_PP

24.6

36.9

135.0

650.0

μV_PP

18.5

27.7

101.3

487.5

000

001

010

011

100

101

110

125

250

32.75

65.5

131

147.1

147.7

221.5

810.0

3900.0

73.9

49.2

500

73.9

49.2

1000

2000

4000

8000

262

73.9

49.2

524

110.8

405.0

1950.0

73.8

1048

2096

270.0

1300.0

(1) At least 1000 consecutive readings were used to calculate the peak-to-peak noise values in this table.

Table 2. Input-Referred Noise (μV_PP) 5-V Analog Supply and 4.033-V Reference⁽¹⁾

PGA GAIN

DR BITS OF

CONFIG1

REGISTER

OUTPUT

DATA RATE

(SPS)

x1

x2

x3

μV_PP

82.0

x4

μV_PP

61.5

x6

μV_PP

41.0

x8

x12

μV_PP

20.5

30.8

102.5

566.7

–3-dB BANDWIDTH

(Hz)

μV_PP

30.8

46.2

153.8

850.0

000

001

010

011

100

101

110

125

250

32.75

65.5

131

246.1

369.2

1230.0

6800.0

123.1

184.6

615.0

3400.0

82.0

61.5

41.0

500

82.0

61.5

41.0

1000

2000

4000

8000

262

82.0

61.5

41.0

524

123.1

410.0

2266.7

92.3

61.5

1048

2096

307.5

1700.0

205.0

1133.3

(1) At least 1000 consecutive readings were used to calculate the peak-to-peak noise values in this table.

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TIMING CHARACTERISTICS

t_CLK

CLK

t_CSSC

t_CSH

t_SDECODE

t_SPWL

CS

t_SCCS

t_SCLK

t_SPWH

SCLK

1

2

3

8

1

2

3

8

t_DIHD

t_DIST

t_DOPD

DIN

t_CSDOZ

Hi-Z

t_CSDOD

Hi-Z

DOUT

NOTE: SPI settings are CPOL = 0 and CPHA = 1.

Figure 1. Serial Interface Timing

Timing Requirements For Figure 1⁽¹⁾

2.7 V ≤ DVDD ≤ 3.6 V 1.6 V ≤ DVDD ≤ 2.7 V

PARAMETER

DESCRIPTION

Master clock period (CLK_DIV bit of LOFF_STAT register = 0)

Master clock period (CLK_DIV bit of LOFF_STAT register = 1)

CS low to first SCLK, setup time

SCLK period

MIN

TBD

414

6

TYP

MAX

TBD

514

MIN

TBD

514

17

TYP

MAX UNIT

TBD

465

ns

t_CLK

t_CSSC

ns

t_SCLK

50

66.6

25

ns

t_{SPWH, L}

t_DIST

SCLK pulse width, high and low

15

ns

DIN valid to SCLK falling edge: setup time

Valid DIN after SCLK falling edge: hold time

SCLK rising edge to DOUT valid: setup time

CS high pulse

10

ns

t_DIHD

10

11

ns

t_DOPD

t_CSH

t_CSDOD

t_SCCS

t_SDECODE

t_CSDOZ

12

10

22

20

ns

2

10

4

2

20

4

t_CLKs

ns

CS low to DOUT driven

Eighth SCLK falling edge to CS high

Command decode time

t_CLKs

ns

4

CS high to DOUT Hi-Z

(1) Specified at T_A= –40°C to +85°C, unless otherwise noted. Load on D_OUT= 20 pF || 100 kΩ.

8

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PIN CONFIGURATIONS

PBS PACKAGE

TQFP-32

(TOP VIEW)

PGA1N

PGA1P

IN1N

1

2

3

4

5

6

7

8

24 DGND

23 DVDD

22

DRDY

21 DOUT

20

IN1P

IN2N

SCLK

19 DIN

18

IN2P

PGA2N

PGA2P

CS

17 CLK

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PIN ASSIGNMENTS

NAME

AVDD

TERMINAL

FUNCTION

DESCRIPTION

12

13

18

17

14

24

19

21

22

23

26

25

3

Supply

Analog supply

AVSS

Analog ground

CS

Digital input

Supply

Chip select

CLK

Master clock input

CLKSEL

DGND

Master clock select

Digital ground

DIN

Digital input

Digital output

Supply

SPI data in

DOUT

SPI data out

DRDY

Data ready; active low

Digital power supply

DVDD

GPIO1/RCLK1

GPIO2/RCLK2

IN1N⁽¹⁾

IN1P⁽¹⁾

Digital input/output

Analog input

Analog output

Digital input

Analog input

Analog input/output

Digital input

—

GPIO1

GPIO2

Differential analog negative input 1

Differential analog positive input 1

Differential analog negative input 2

Differential analog positive input 2

Differential analog negative output 1

Differential analog positive output 1

Differential analog negative output 2

Differential analog positive output 2

Power-down/System reset; active low

Right leg drive input to MUX/RLD reference

Right leg drive inverting input

Right leg drive output

4

IN2N⁽¹⁾

IN2P⁽¹⁾

5

6

PGA1N

PGA1P

PGA2N

PGA2P

PWDN/RESET

RLDIN/RLDREF

RLDINV

RLDOUT

IN3N⁽¹⁾

IN3P⁽¹⁾

1

2

7

8

15

29

28

30

32

31

20

16

11

27

10

9

Differential analog negative input 3

Differential analog positive input 3

SPI clock

SCLK

START

VCAP1

VCAP2

VREFN

VREFP

Start conversion

Analog bypass capacitor

Negative reference voltage

Positive reference voltage

—

Analog input

Analog input/output

(1) Excludes effects of noise, linearity, offset, and gain error.

10

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TYPICAL CHARACTERISTICS

All plots at T_A= +25°C, AVDD = 3 V, AVSS = 0 V, DVDD = 1.8 V, internal VREFP = 2.42 V, VREFN = AVSS,

external clock = 512 kHz, data rate = 500 SPS, and gain = 6, unless otherwise noted.

INTERNAL REFERENCE vs TEMPERATURE

CMRR vs FREQUENCY

2.424

2.422

2.42

130

120

110

100

90

Data Rate = 8 kSPS

AIN = AVDD − 0.3 V to AVSS + 0.3 V

Gain = 1

Gain = 2

Gain = 3

Gain = 4

Gain = 6

Gain = 8

Gain = 12

2.418

2.416

−40

−15

10

35

60

85

10

100

1k

Temperature (°C)

Frequency (Hz)

G003

G004

Figure 2.

Figure 3.

LEAKAGE CURRENT vs INPUT VOLTAGE

LEAKAGE CURRENT vs TEMPERATURE

0.2

0.1

0

1

0.8

0.6

0.4

0.2

0

0.5

1

1.5

2

2.5

3

−40

−15

10

35

60

85

Input Signal (V)

Temperature (°C)

G004

G006

Figure 4.

Figure 5.

PSRR vs FREQUENCY

THD vs FREQUENCY

120

110

100

90

110

Data Rate = 8 kSPS, −0.5 dBFS

100

90

80

70

60

Gain = 1

Gain = 2

Gain = 3

Gain = 4

Gain = 6

Gain = 8

Gain = 12

80

70

Gain = 1

Gain = 2

Gain = 3

Gain = 4

Gain = 6

Gain = 8

Gain = 12

60

50

10

100

1k

10

100

1k

Frequency (Hz)

G007

G006

Figure 6.

Figure 7.

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TYPICAL CHARACTERISTICS (continued)

All plots at T_A= +25°C, AVDD = 3 V, AVSS = 0 V, DVDD = 1.8 V, internal VREFP = 2.42 V, VREFN = AVSS,

external clock = 512 kHz, data rate = 500 SPS, and gain = 6, unless otherwise noted.

THD FFT PLOT

FFT PLOT

(60-Hz Signal)

0

−20

0

−20

PGA Gain = 1

Input = 10Hz, −0.5 dBFS

THD = −96 dB

PGA Gain = 1

Input = 10Hz, −0.5 dBFS

THD = −97 dB

−40

SNR = 92 dB

SNR =76 dB

Data Rate =500 SPS

Data Rate = 8 kSPS

−60

−80

−100

−120

−140

−160

−100

−120

−140

−160

0

50

100

150

200

250

0

1000

2000

3000

4000

Frequency (Hz)

G011

G008

Figure 8.

Figure 9.

TEST SIGNAL AMPLITUDE ACCURACY

LEAD-OFF COMPARATOR THRESHOLD ACCURACY

60

40

20

0

140

Data from 96 devices, Two lots

Data from 96 devices, Two Lots

120

100

80

60

40

20

0

Threshold Error (mV)

Error (%)

G014

G015

Figure 10.

Figure 11.

LEAD-OFF CURRENT SOURCE ACCURACY DISTRIBUTION

120

Data from 125 devices, Two lots

Current Setting = 24 nA

100

80

60

40

20

0

Error in Current Magnitude (nA)

G016

Figure 12.

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OVERVIEW

The ADS1191/2 are low-power, multichannel, simultaneously-sampling, 16-bit delta-sigma (ΔΣ) analog-to-digital

converters (ADCs) with integrated programmable gain amplifiers (PGAs). These devices integrate various

ECG-specific functions that make them well-suited for scalable electrocardiogram (ECG), sports, and fitness

applications. The devices can also be used in high-performance, multichannel data acquisition systems by

powering down the ECG-specific circuitry.

The ADS1191/2 have a highly programmable multiplexer that allows for temperature, supply, input short, and

RLD measurements. Additionally, the multiplexer allows any of the input electrodes to be programmed as the

patient reference drive. The PGA gain can be chosen from one of seven settings (1, 2, 3, 4, 6, 8, and 12). The

ADCs in the device offer data rates from 125 SPS to 8 kSPS. Communication to the device is accomplished

using an SPI-compatible interface. The device provides two general-purpose I/O (GPIO) pins for general use.

Multiple devices can be synchronized using the START pin.

The internal reference can be programmed to either 2.42 V or 4.033 V. The internal oscillator generates a

512-kHz clock. The versatile right leg drive (RLD) block allows the user to choose the average of any

combination of electrodes to generate the patient drive signal. Lead-off detection can be accomplished either by

using an external pull-up/pull-down resistor or the device internal current source/sink. An internal ac lead-off

detection feature is also available. A detailed diagram of the ADS1191/2 is shown in Figure 13.

AVDD

VCAP1

PGA1P PGA1N VREFP VCAP2 VREFN

DVDD

Power-Supply Signal

Temperature Sensor Input

Test Signal

Reference

DRDY

Lead-Off Excitation Source

CS

SCLK

DIN

DOUT

SPI

IN1P

CLKSEL

CLK

EMI

Filter

PGA1

ADC1

IN1N

IN2P

Oscillator

Control

GPIO1/

RCLK

EMI

Filter

MUX

IN2N

GPIO2/

RCLK

RESP

PGA2

ADC2

PWDN/

RESET

V

START

(AVDD + AVSS)/2

RLD

Amplifier

AVSS

DGND

RLDIN/

RLDREF

RLD

OUT

RLD

INV

PGA2N PGA2P

Figure 13. Functional Block Diagram

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THEORY OF OPERATION

This section contains details of the ADS1191/2 internal functional elements. The analog blocks are discussed

first followed by the digital interface. Blocks implementing ECG-specific functions are covered in the end.

Throughout this document, f_CLKdenotes the frequency of the signal at the CLK pin, t_CLKdenotes the period of the

signal at the CLK pin, f_DRdenotes the output data rate, t_DRdenotes the time period of the output data, and f_MOD

denotes the frequency at which the modulator samples the input.

EMI FILTER

An RC filter at the input acts as an EMI filter on channels 1 and 2. The –3-dB filter bandwidth is approximately

3 MHz.

INPUT MULTIPLEXER

The ADS1191/2 input multiplexers are very flexible and provide many configurable signal switching options.

Refer to Figure 14 for a diagram of the ADS1191/2 multiplexer. Note that IN3P, IN3N, and RLDIN are common to

both channels. VINP and VINN are separate for each of the three pins. This flexibility allows for significant device

and sub-system diagnostics, calibration, and configuration. Selection of switch settings for each channel is made

by writing the appropriate values to the CH1SET or CH2SET register (see the CH1SET and CH2SET Registers

in the Register Map section for details.) More details of the ECG-specific features of the multiplexer are

discussed in the Input Multiplexer subsection of the ECG-Specifc Functions.

Device Noise Measurements

Setting CHnSET[3:0] = 0001 sets the common-mode voltage of (VREFP + VREFN)/2 to both inputs of the

channel. This setting can be used to test the inherent noise of the device in the user system.

Test Signals (TestP and TestN)

Setting CHnSET[2:0] = 101 provides internally-generated test signals for use in sub-system verification at

power-up. This functionality allows the entire signal chain to be tested out. Although the test signals are similar to

the CAL signals described in the IEC60601-2-51 specification, this feature is not intended for use in compliance

testing.

Control of the test signals is accomplished through register settings (see the CONFIG2: Configuration Register 2

subsection in the Register Map section for details). TEST_AMP controls the signal amplitude and TEST_FREQ

controls switching at the required frequency.

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INT_TEST

Device

MUX1[3:0] = 0101

MUX1[3:0] = 0100

MUX1[3:0] = 0011

TESTP

TEMPP

MVDDP

From LOFFP

MUX1[3:0] = 0000

IN2P

To PGA2_INP

MUX1[3:0] = 0110 or

MUX1[3:0] = 1000

MUX1[3:0] = 0001

MUX1[3:0] = 0010

VREFP + VREFN

2

EMI

Filter

MUX1[3:0] = 0111 or

MUX1[3:0] = 1000

MUX1[3:0] = 0001

MUX1[3:0] = 0000

IN2N

To PGA2_INN

From LOFFN

RLD_REF

MUX1[3:0] = 0010

MUX1[3:0] = 0011

MUX1[3:0] = 0100

MUX1[3:0] = 1001

MVDDN

TEMPN

INT_TEST

MUX1[3:0] = 0101

TESTM

TESTP

RLDIN/

RLDREF

INT_TEST

MUX1[3:0] = 0101

MUX1[3:0] = 0100

MUX1[3:0] = 0011

TEMPP

MVDDP

From LOFFP

MUX1[3:0] = 0000

IN1P

To PGA1_INP

MUX1[3:0] = 0111 or

MUX1[3:0] = 1000

MUX1[3:0] = 0001

MUX1[3:0] = 0010

VREFP + VREFN

2

EMI

Filter

MUX1[3:0] = 0110 or

MUX1[3:0] = 1000

MUX1[3:0] = 0001

MUX1[3:0] = 1001

MUX1[3:0] = 0000

IN1N

To PGA1_INN

From LOFFN

RLD_REF

MUX1[3:0] = 0010

MUX1[3:0] = 0011

MUX1[3:0] = 0100

MVDDN

MUX1[3:0] = 1001

TEMPN

RESP

MOD

INT_TEST

MUX1[3:0] = 0101

TESTM

RESP_MODP/IN3P

RESP_MODN/IN3N

NOTE: MVDD monitor voltage supply depends on channel number; see the Supply Measurements (MVDDP, MVDDN) section.

Figure 14. Input Multiplexer Block for Both Channels

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Auxiliary Differential Input (IN3N, IN3P)

The IN3N and IN3P signals can be used as a third multiplexed differential input channel. These inputs can be

multiplexed to either of the ADC channels.

Temperature Sensor (TempP, TempN)

The ADS1191/2 contain an on-chip temperature sensor. This sensor uses two internal diodes with one diode

having a current density 16x that of the other, as shown in Figure 15. The difference in current densities of the

diodes yields a difference in voltage that is proportional to absolute temperature.

As a result of the low thermal resistance of the package to the printed circuit board (PCB), the internal device

temperature tracks the PCB temperature closely. Note that self-heating of the ADS1191/2 causes a higher

reading than the temperature of the surrounding PCB.

The scale factor of Equation 1 converts the temperature reading to °C. Before using this equation, the

temperature reading code must first be scaled to μV.

Temperature Reading (mV) - 168,000 mV

Temperature (°C) =

+ 25°C

394 mV/°C

(1)

Temperature Sensor Monitor

AVDD

1x

2x

To MUX TempP

To MUX TempN

8x

1x

AVSS

Figure 15. Measurement of the Temperature Sensor in the Input

Supply Measurements (MVDDP, MVDDN)

Setting CHnSET[2:0] = 011 sets the channel inputs to different supply voltages of the device. For channel 1

(MVDDP – MVDDN) is [0.5(AVDD + AVSS)]; for channel 2 (MVDDP – MVDDN) is DVDD/4. Note that to avoid

saturating the PGA while measuring power supplies, the gain must be set to '1'.

Lead-Off Excitation Signals (LoffP, LoffN)

The lead-off excitation signals are fed into the multiplexer before the switches. The comparators that detect the

lead-off condition are also connected to the multiplexer block before the switches. For a detailed description of

the lead-off block, refer to the Lead-Off Detection subsection in the ECG-Specific Functions section.

Auxiliary Single-Ended Input

The RLDIN pin is primarily used for routing the right leg drive signal to any of the electrodes in case the right leg

drive electrode falls off. However, the RLDIN pin can be used as a multiple single-ended input channel. The

signal at the RLDIN pin can be measured with respect to the voltage at the RLD_REF pin using either channel.

This measurement is done by setting the channel multiplexer setting MUXn[3:0] to '0010' in the CH1SET and

CH2SET registers.

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ANALOG INPUT

The analog input to the ADS1191/2 is fully differential. Assuming PGA = 1, the differential input (INP – INN) can

span between –V_REFto +V_REF. Refer to Table 4 for an explanation of the correlation between the analog input

and the digital codes. There are two general methods of driving the analog input of the ADS1191/2: single-ended

or differential, as shown in Figure 16 and Figure 17. Note that INP and INN are 180°C out-of-phase in the

differential input method. When the input is single-ended, the INN input is held at the common-mode voltage,

preferably at mid-supply. The INP input swings around the same common voltage and the peak-to-peak

amplitude is the (common-mode + 1/2 V_REF) and the (common-mode – 1/2 V_REF). When the input is differential,

the common-mode is given by (INP + INN)/2. Both the INP and INN inputs swing from (common-mode + 1/2

V_REFto common-mode – 1/2 V_REF). For optimal performance, it is recommended that the ADS1191/2 be used in

a differential configuration.

-1/2 V_REFto

V_REF

Device

+1/2 V_REF

Peak-to-Peak

Device

Common

Voltage

Common

Voltage

V_REF

Peak-to-Peak

Single-Ended Input

Differential Input

Figure 16. Methods of Driving the ADS1191/2: Single-Ended or Differential

CM + 1/2 V_REF

+1/2 V_REF

INP

CM Voltage

-1/2 V_REF

INN = CM Voltage

CM - 1/2 V_REF

t

Single-Ended Inputs

INP

INN

+V_REF

CM + 1/2 V_REF

CM Voltage

CM - 1/2 V_REF

-V_REF

t

Differential Inputs

(INP) + (INN)

, Common-Mode Voltage (Single-Ended Mode) = INN.

Common-Mode Voltage (Differential Mode) =

2

Input Range (Differential Mode) = (AINP - AINN) = 2 V_REF

.

Figure 17. Using the ADS1191/2 in the Single-Ended and Differential Input Modes

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PGA SETTINGS AND INPUT RANGE

The PGA is a differential input/differential output amplifier, as shown in Figure 18. It has seven gain settings (1,

2, 3, 4, 6, 8, and 12) that can be set by writing to the CHnSET register (see the CH1SET and CH2SET Registers

in the Register Map section for details). The ADS1191/2 have CMOS inputs and hence have negligible current

noise.

From MuxP

R_S= 2 kW

PGA1P

PgaP

C_P1

R₂

150 kW

R₁

C_FILTER

4.7 nF

60 kW

(for Gain = 6)

R₂

150 kW

R_S= 2 kW

PgaN

PGA1N

C_P2

From MuxN

Figure 18. PGA Implementation

The resistor string of the PGA that implements the gain has 360 kΩ of resistance for a gain of 6. This resistance

provides a current path across the outputs of the PGA in the presence of a differential input signal. This current

is in addition to the quiescent current specified for the device in the presence of a differential signal at the input.

The output of PGA is filtered by an RC filter before it goes to the ADC. The filter is formed by an internal resistor

R_S= 2 kΩ and an external capacitor C_FILTER(4.7 nF, typical). This filter acts as an anti-aliasing filter with

the –3-dB bandwidth of 8.4 kHz. The internal R_Sresistor is accurate to 15% so actual bandwidth will vary. This

RC filter also suppresses the glitch at the output of PGA caused by ADC sampling. The minimum value of C_EXT

that can be used is 4 nF. A larger value C_FILTERcapacitor can be used for increased attenution at higher

frequencies for anti-aliasing purposes. The tradeoff is that a larger capacitor value gives degraded THD

performance. See Figure 19 for a plot showing the THD versus C_FILTERvalue.

−85

−90

−95

−100

−105

5

10

15

20

25

C_FILTER(nF)

G025

Figure 19. THD versus C_FILTERValue

Special care must be taken in PCB layout to minimize the parasitic capacitance C_P1/C_P2. The absolute value of

these capacitances must be less than 20 pF. Ideally, C_FILTERshould be placed right at the pins to minimize these

capacitors. Mismatch between these capacitors will lead to CMRR degradation. Assuming everything else is

perfectly matched, the 60 Hz CMRR as a function of this mismatch is given by Equation 2.

Gain

CMRR = 20log

2p ´ 2e3 ´ DC ´ 60

P

(2)

where ΔC_P= C_P1– C_P2

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For example, a mismatch of 20 pF with a gain of 6 limits the CMRR to 112 dB. If ΔC_Pis small, then the CMRR is

limited by the PGA itself and is as specified in the Electrical Characteristics table. The PGA are chopped

internally at either 8, 32, or 64 kSPS. The digital decimation filter filters out the chopping ripple in the normal path

so the chopping ripple is not a concern. First-order filtering is provided by the RC filter at the PGA output.

Additional filtering may be needed to suppress the chopping ripple. If the PGA output is routed to other circuitry,

a 20-kΩ series resistance must be added in the path near the C_FILTERcapacitor. The routing should be matched

to maintain the CMRR performance.

Input Common-Mode Range

The usable input common-mode range of the front end depends on various parameters, including the maximum

differential input signal, supply voltage, PGA gain, etc. This range is described in Equation 3:

Gain V_{MAX_DIFF}

AVDD - 0.4 -

> CM > AVSS + 0.4 +

2

where:

V_{MAX_DIFF}= maximum differential signal at the input of the PGA

CM = common-mode range

(3)

For example:

If V_DD= 3 V, gain = 6, and V_{MAX_DIFF}= 350 mV

Then 1.25 V < CM < 1.75 V

Input Differential Dynamic Range

The differential (INP – INN) signal range depends on the analog supply and reference used in the system. This

range is shown in Equation 4.

V_REF

±V_REF2 V_REF

=

Max (INP - INN) <

;

Full-Scale Range =

Gain

(4)

The 3-V supply, with a reference of 2.42 V and a gain of 6 for ECGs, is optimized for power with a differential

input signal of approximately 300 mV. For higher dynamic range, a 5-V supply with a reference of 4 V (set by the

VREF_4V bit of the CONFIG3 register) can be used to increase the differential dynamic range.

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ADC ΔΣ Modulator

Each channel of the ADS1191/2 has a 16-bit ΔΣ ADC. This converter uses a second-order modulator optimized

for low-power applications. The modulator samples the input signal at the rate of f_MOD= f_CLK/4 or f_CLK/16, as

determined by the CLK_DIV bit. In both cases, the sampling clock has a typical value of 128 kHz. As in the case

of any ΔΣ modulator, the noise of the ADS1191/2 is shaped until f_MOD/2, as shown in Figure 20. The on-chip

digital decimation filters explained in the next section can be used to filter out the noise at higher frequencies.

These on-chip decimation filters also provide antialias filtering. This feature of the ΔΣ converters drastically

reduces the complexity of the analog antialiasing filters that are typically needed with nyquist ADCs.

0

−10

−20

−30

−40

−50

−60

−70

−80

−90

−100

−110

−120

−130

−140

−150

−160

0.001

0.01

0.1

1

Normalized Frequency (f_IN/f_MOD

)

G001

Figure 20. Power Spectral Density (PSD) of a ΔΣ Modulator (4-Bit Quantizer)

DIGITAL DECIMATION FILTER

The digital filter receives the modulator output and decimates the data stream. By adjusting the amount of

filtering, tradeoffs can be made between resolution and data rate: filter more for higher resolution, filter less for

higher data rates. Higher data rates are typically used in ECG applications for implement software pace detection

and ac lead-off detection.

The digital filter on each channel consists of a third-order sinc filter. The decimation ratio on the sinc filters can

be adjusted by the DR bits in the CONFIG1 register (see the Register Map section for details). This setting is a

global setting that affects all channels and, therefore, in a device all channels operate at the same data rate.

Sinc Filter Stage (sinx/x)

The sinc filter is a variable decimation rate, third-order, low-pass filter. Data are supplied to this section of the

filter from the modulator at the rate of f_MOD. The sinc filter attenuates the high-frequency noise of the modulator,

then decimates the data stream into parallel data. The decimation rate affects the overall data rate of the

converter.

Equation 5 shows the scaled Z-domain transfer function of the sinc filter.

3

1 - Z^{- N}

½H(z)½ =

1 - Z^{- 1}

(5)

The frequency domain transfer function of the sinc filter is shown in Equation 6.

3

Npf

sin

f_MOD

H(f)½ =

pf

N ´ sin

f_MOD

where:

N = decimation ratio

(6)

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The sinc filter has notches (or zeroes) that occur at the output data rate and multiples thereof. At these

frequencies, the filter has infinite attenuation. Figure 21 shows the frequency response of the sinc filter and

Figure 22 shows the roll-off of the sinc filter. With a step change at input, the filter takes 3 t_DRto settle. After a

rising edge of the START signal, the filter takes t_SETTLEtime to give the first data output. The settling time of the

filters at various data rates are discussed in the START subsection of the SPI Interface section. Figure 23 and

Figure 24 show the filter transfer function until f_MOD/2 and f_MOD/16, respectively, at different data rates. Figure 25

shows the transfer function extended until 4 f_MOD. It can be seen that the passband of the ADS1191/2 repeats

itself at every f_MOD. The input R-C anti-aliasing filters in the system should be chosen such that any interference

in frequencies around multiples of f_MODare attenuated sufficiently.

0

-0.5

-1

-20

-40

-60

-1.5

-2

-80

-100

-120

-140

-2.5

-3

0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5

0

0.05

0.1

0.15

0.2

0.25

0.3

0.35

Normalized Frequency (f_IN/f_DR

)

Normalized Frequency (f_IN/f_DR

)

Figure 21. THD vs Frequency

Figure 22. INL vs PGA Gain

0

-20

0

DR[0:2] = 000

DR[0:2] = 110

-20

-40

DR[0:2] = 110

-40

-60

-80

-100

-120

-140

-100

-120

-140

0

0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5

Normalized Frequency (f_IN/f_MOD

0

0.01

0.02

0.03

0.04

0.05

0.06

0.07

)

Normalized Frequency (f_IN/f_MOD

)

Figure 23. Transfer Function of On-Chip

Decimation Filters Until f_MOD/2

10

Figure 24. Transfer Function of On-Chip

Decimation Filters Until f_MOD/16

DR[0:2] = 110

DR[0:2] = 000

-10

-30

-50

-70

-90

-110

-130

0

0.5

1

1.5

2

2.5

3

3.5

4

Normalized Frequency (f_IN/f_MOD

)

Figure 25. Transfer Function of On-Chip Decimation Filters

Until 4f_MODfor DR[0:2] = 000 and DR[0:2] = 110

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REFERENCE

Figure 26 shows a simplified block diagram of the internal reference of the ADS1191/2. The reference voltage is

generated with respect to AVSS. The VREFN pin must always be connected to AVSS.

1 mF

VCAP1

(1)

R₁

2.42 V or

4.033 V

Bandgap

VREFP

(1)

R₃

10 mF

0.1 mF

(1)

R₂

VREFN

AVSS

To ADC Reference Inputs

(1) For V_REF= 2.42 V: R₁= 100 kΩ, R₂= 200 kΩ, and R₃= 200 kΩ. For V_REF= 4.033 V: R₁= 84 kΩ, R₂= 120 kΩ, and R₃= 280 kΩ.

Figure 26. Internal Reference

The external band-limiting capacitors determine the amount of reference noise contribution. For high-end ECG

systems, the capacitor values should be chosen such that the bandwidth is limited to less than 10 Hz, so that the

reference noise does not dominate the system noise. When using a 3-V analog supply, the internal reference

must be set to 2.42 V. In case of a 5-V analog supply, the internal reference can be set to 4.033 V by setting the

VREF_4V bit in the CONFIG2 register.

Alternatively, the internal reference buffer can be powered down and VREFP can be applied externally. Figure 27

shows a typical external reference drive circuitry. Power-down is controlled by the PD_REFBUF bit in the

CONFIG3 register. This power-down is also used to share internal references when two devices are cascaded.

By default, the device wakes up in external reference mode.

100 kW

10 pF

+5 V

0.1 mF

100 W

To VREFP Pin

OPA211

100 W

22 mF

10 mF

0.1 mF

+5 V

VIN

REF5025

TRIM

OUT

100 mF

22 mF

Figure 27. External Reference Driver

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CLOCK

The ADS1191/2 provide two different methods for device clocking: internal and external. Internal clocking is

ideally suited for low-power, battery-powered systems. The internal oscillator is trimmed for accuracy at room

temperature. Over the specified temperature range the accuracy varies; see the Electrical Characteristics. Clock

selection is controlled by the CLKSEL pin and the CLK_EN register bit.

The CLKSEL pin selects either the internal or external clock. The CLK_EN bit in the CONFIG1 register enables

and disables the oscillator clock to be output in the CLK pin. A truth table for these two pins is shown in Table 3.

The CLK_EN bit is useful when multiple devices are used in a daisy-chain configuration. It is recommended that

during power-down the external clock be shut down to save power.

Table 3. CLKSEL Pin and CLK_EN Bit

CONFIG1.CLK_EN

CLKSEL PIN

BIT

CLOCK SOURCE

External clock

CLK PIN STATUS

Input: external clock

3-state

0

1

X

0

Internal clock oscillator

1

Output: internal clock oscillator

The ADS1191/2 have the option to choose between two different external clock frequencies (512 kHz or

2.048 MHz). This frequency is selected by setting the CLK_DIV bit (bit 6) in the LOFF_STAT register. The

modulator must be clocked at 128 kHz, regardless of the external clock frequency. Figure 28 shows the

relationship between the external clock (f_CLK) and the modulator clock (f_MOD). The default mode of operation is

f_CLK= 512 kHz. The higher frequency option has only been provided to allow the SPI to run at a higher speed.

SCLK can be only twice the speed of f_CLKduring a register read and/or write.

Frequency

Divider

f

CLK

Divide-By-4

f

MOD

Frequency

Divider

Divide-By-16

CLK_DIV

(Bit 6 of LOFF_STAT

Register)

Figure 28. Relationship Between External Clock (f_CLK) and Modulator Clock (f_MOD

)

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DATA FORMAT

The ADS1191/2 outputs 16 bits of data per channel in binary twos complement format, MSB first. The LSB has a

weight of V_REF/(2¹⁵– 1). A positive full-scale input produces an output code of 7FFFh and the negative full-scale

input produces an output code of 8000h. The output clips at these codes for signals exceeding full-scale. Table 4

summarizes the ideal output codes for different input signals. All 16 bits toggle when the analog input is at

positive or negative full-scale.

Table 4. Ideal Output Code versus Input Signal

INPUT SIGNAL, V_IN

(AINP – AINN)

IDEAL OUTPUT CODE⁽¹⁾

≥ V_REF

7FFFh

0001h

0000h

FFFFh

8000h

+V_REF/(2¹⁵– 1)

0

–V_REF/(2¹⁵– 1)

≤ –V_REF(2¹⁵/2¹⁵– 1)

(1) Excludes effects of noise, linearity, offset, and gain error.

SPI INTERFACE

The SPI-compatible serial interface consists of four signals: CS, SCLK, DIN, and DOUT. The interface reads

conversion data, reads and writes registers, and controls the ADS1191/2 operation. The DRDY output is used as

a status signal to indicate when data are ready. DRDY goes low when new data are available.

Chip Select (CS)

Chip select (CS) selects the ADS1191/2 for SPI communication. CS must remain low for the entire duration of

the serial communication. After the serial communication is finished, always wait four or more t_CLKcycles before

taking CS high. When CS is taken high, the serial interface is reset, SCLK and DIN are ignored, and DOUT

enters a high-impedance state. DRDY asserts when data conversion is complete, regardless of whether CS is

high or low.

Serial Clock (SCLK)

SCLK is the serial peripheral interface (SPI) serial clock. It is used to shift in commands and shift out data from

the device. The serial clock (SCLK) features a Schmitt-triggered input and clocks data on the DIN and DOUT

pins into and out of the ADS1191/2. Even though the input has hysteresis, it is recommended to keep SCLK as

clean as possible to prevent glitches from accidentally forcing a clock event. The absolute maximum limit for

SCLK is specified in the Serial Interface Timing table. When shifting in commands with SCLK, make sure that the

entire set of SCLKs is issued to the device. Failure to do so could result in the device serial interface being

placed into an unknown state, requiring CS to be taken high to recover.

For a single device, the minimum speed needed for the SCLK depends on the number of channels, number of

bits of resolution, and output data rate. (For multiple cascaded devices, see the Cascade Mode subsection of the

Multiple Device Configuration section.)

t_SCLK< (t_DR– 4 t_CLK)/(N_BITSN_CHANNELS+ 24)

(7)

For example, if the ADS1191/2 is used in a 500-SPS mode (two channels, 16-bit resolution), the minimum SCLK

speed is approximately 36 kHz.

Data retrieval can be done either by putting the device in RDATAC mode or by issuing a RDATA command for

data on demand. The above SCLK rate limitation applies to RDATAC. For the RDATA command, the limitation

applies if data must be read in between two consecutive DRDY signals. The above calculation assumes that

there are no other commands issued in between data captures. SCLK can only be twice the speed of f_CLKduring

register reads and writes. For faster SPI interface, use f_CLK= 2.048 MHz and set the CLK_DIV register bit (in the

LOFF_STAT register) to '1'.

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Data Input (DIN)

The data input pin (DIN) is used along with SCLK to communicate with the ADS1191/2 (opcode commands and

register data). The device latches data on DIN on the falling edge of SCLK.

Data Output (DOUT)

The data output pin (DOUT) is used with SCLK to read conversion and register data from the ADS1191/2. Data

on DOUT are shifted out on the rising edge of SCLK. DOUT goes to a high-impedance state when CS is high. In

read data continuous mode (see the SPI Command Definitions section for more details), the DOUT output line

also indicates when new data are available. This feature can be used to minimize the number of connections

between the device and the system controller.

Figure 29 shows the data output protocol for ADS1192.

DRDY

CS

SCLK

DOUT

DIN

STAT

CH1

CH2

16-Bit

Figure 29. SPI Bus Data Output for the ADS1192 (Two Channels)

Data Retrieval

Data retrieval can be accomplished in one of two methods. The read data continuous command (see the

RDATAC: Read Data Continuous section) can be used to set the device in a mode to read the data continuously

without sending opcodes. The read data command (see the RDATA: Read Data section) can be used to read

just one data output from the device (see the SPI Command Definitions section for more details). The conversion

data are read by shifting the data out on DOUT. The MSB of the data on DOUT is clocked out on the first SCLK

rising edge. DRDY returns to high on the first SCLK falling edge. DIN should remain low for the entire read

operation.

The number of bits in the data output depends on the number of channels and the number of bits per channel.

For the ADS1191/2, the number of data outputs is (16 status bits + 16 bits × 2 channels) = 48 bits. The format of

the 16 status bits is (1100 + LOFF_STAT[4:0] + GPIO[1:0] + 5 zeros). The data format for each channel data are

twos complement and MSB first. When channels are powered down using the user register setting, the

corresponding channel output is set to '0'. However, the sequence of channel outputs remains the same.

The ADS1191/2 also provide a multiple readback feature. The data can be read out multiple times by simply

giving more SCLKs, in which case the MSB data byte repeats after reading the last byte.

Data Ready (DRDY)

DRDY is an output. When it transitions low, new conversion data are ready. The CS signal has no effect on the

data ready signal. The behavior of DRDY is determined by whether the device is in RDATAC mode or the

RDATA command is being used to read data on demand. (See the RDATAC: Read Data Continuous and

RDATA: Read Data subsections of the SPI Command Definitions section for further details).

When reading data with the RDATA command, the read operation can overlap the occurrence of the next DRDY

without data corruption.

The START pin or the START command is used to place the device either in normal data capture mode or pulse

data capture mode.

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Figure 30 shows the relationship between DRDY, DOUT, and SCLK during data retrieval (in case of an

ADS1191/2 with a selected data rate that gives 16-bit resolution). DOUT is latched out at the rising edge of

SCLK. DRDY is pulled high at the falling edge of SCLK. Note that DRDY goes high on the first falling edge SCLK

regardless of the status of the CS signal and regardless of whether data are being retrieved from the device or a

command is being sent through the DIN pin.

DRDY

DOUT

SCLK

Bit 55

Bit 54

Bit 53

Figure 30. DRDY with Data Retrieval (CS = 0)

GPIO

The ADS1191/2 have a total of two general-purpose digital I/O (GPIO) pins available in the normal mode of

operation. The digital I/O pins are individually configurable as either inputs or as outputs through the GPIOC bits

register. The GPIOD bits in the GPIO register control the level of the pins. When reading the GPIOD bits, the

data returned are the logic level of the pins, whether they are programmed as inputs or outputs. When the GPIO

pin is configured as an input, a write to the corresponding GPIOD bit has no effect. When configured as an

output, a write to the GPIOD bit sets the output value.

If configured as inputs, these pins must be driven (do not float). The GPIO pins are set as inputs after power-on

or after a reset. Figure 31 shows the GPIO port structure. The pins should be shorted to DGND with a series

resistor if not used.

GPIO Data (read)

GPIO Pin

GPIO Data (write)

GPIO Control

Figure 31. GPIO Port Pin

Power-Down/Reset (PWDN/RESET)

The PWDN/RESET pins are shared. If PWDN/RESET is held low for longer than 2⁹t_MODs, the device is powered

down. The implementation is such that the device is always reset when PWDN/RESET makes a transition from

high to low. If the device is powered down it is reset first and then if 2¹⁰clock elapses it is powered down. Hence,

when powering up the device from a power-down state, all registers must be rewritten.

There are two methods to reset the ADS1191/2: pull the PWDN/RESET pin low, or send the RESET opcode

command. When using the PWDN/RESET pin, take it low to force a reset. Make sure to follow the minimum

pulse width timing specifications before taking the PWDN/RESET pin back high. The RESET command takes

effect on the eighth SCLK falling edge of the opcode command. On reset it takes 18 t_CLKcycles to complete

initialization of the configuration registers to the default states and start the conversion cycle. Note that an

internal RESET is automatically issued to the digital filter whenever the CONFIG1 register is set to a new value

with a WREG command.

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START

The START pin must be set high or the START command sent to begin conversions. When START is low or if

the START command has not been sent, the device does not issue a DRDY signal (conversions are halted).

When using the START opcode to control conversion, hold the START pin low. The ADS1191/2 feature two

modes to control conversion: continuous mode and single-shot mode. The mode is selected by SINGLE_SHOT

(bit 7 of the CONFIG1 register). In multiple device configurations the START pin is used to synchronize devices

(see the Multiple Device Configuration subsection of the SPI Interface section for more details).

Settling Time

The settling time (t_SETTLE) is the time it takes for the converter to output fully settled data when the START signal

is pulled high. Once START is pulled high, DRDY is also pulled high. The next falling edge of DRDY indicates

that data are ready. Figure 32 shows the timing diagram and Table 5 shows the settling time for different data

rates. The settling time depends on f_CLKand the decimation ratio (controlled by the DR[2:0] bits in the CONFIG1

register). Table 4 shows the settling time as a function of t_CLK. Note that when START is held high and there is a

step change in the input signal, it takes 3 t_DRfor the filter to settle to the new value. Settled data are available on

the fourth DRDY pulse. Settling time number uncertainty is one t_MODcycle. Therefore, it is recommended to add

one t_MODcycle delay before issuing SCLK to retrieve data.

t_SETTLE

START Pin

or

START Opcode

DIN

t_DR

4/f_CLK

DRDY

(1) Settling time uncertainty is one t_MODcycle.

Figure 32. Settling Time

Table 5. Settling Time for Different Data Rates

DR[2:0]

000

SETTLING TIME⁽¹⁾

UNIT⁽²⁾

t_MOD

—

4100

2052

1028

516

260

132

68

001

010

011

100

101

110

111

—

(1) Settling time uncertainty is one t_MODcycle.

(2) t_MOD= 4 t_CLKfor CLK_DIV = 0 and t_MOD= 16 t_CLKfor CLK_DIV = 1.

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Continuous Mode

Conversions begin when the START pin is taken high or when the START opcode command is sent. As seen in

Figure 33, the DRDY output goes high when conversions are started and goes low when data are ready.

Conversions continue indefinitely until the START pin is taken low or the STOP opcode command is transmitted.

When the START pin is pulled low or the stop command is issued, the conversion in progress is allowed to

complete. Figure 34 and Table 6 show the required timing of DRDY to the START pin and the START/STOP

opcode commands when controlling conversions in this mode. To keep the converter running continuously, the

START pin can be permanently tied high. Note that when switching from pulse mode to continuous mode, the

START signal is pulsed or a STOP command must be issued followed by a START command. This conversion

mode is ideal for applications that require a fixed continuous stream of conversions results.

START Pin

or

START⁽¹⁾

Opcode

STOP⁽¹⁾

Opcode

DIN

t_DR

t_SETTLE

DRDY

(1) START and STOP opcode commands take effect on the seventh SCLK falling edge at the end of the opcode

transmission.

Figure 33. Continuous Conversion Mode

t_SDSU

DRDY and DOUT

t_DSHD

START Pin

or

STOP⁽¹⁾

STOP Opcode

(1) START and STOP commands take effect on the seventh SCLK falling edge at the end of the opcode transmission.

Figure 34. START to DRDY Timing

Table 6. Timing Characteristics for Figure 34⁽¹⁾

SYMBOL

DESCRIPTION

MIN

UNIT

START pin low or STOP opcode to DRDY setup time

to halt further conversions

t_SDSU

8

t_MOD

START pin low or STOP opcode to complete current

conversion

t_DSHD

8

t_MOD

(1) START and STOP commands take effect on the seventh SCLK falling edge at the end of the opcode transmission.

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Single-Shot Mode

The single-shot mode is enabled by setting the SINGLE_SHOT bit in the CONFIG1 register to '1'. In single-shot

mode, the ADS1191/2 perform a single conversion when the START pin is taken high or when the START

opcode command is sent. As seen in Figure 34, when a conversion is complete, DRDY goes low and further

conversions are stopped. Regardless of whether the conversion data are read or not, DRDY remains low. To

begin a new conversion, take the START pin low and then back high, or transmit the START opcode again.

When switching from continuous mode to pulse mode, make sure the START signal is pulsed or issue a STOP

command followed by a START command.

This conversion mode is provided for applications that require non-standard or non-continuous data rates.

Issuing a START command or toggling the START pin high resets the digital filter, effectively dropping the data

rate by a factor of four. Note that this mode leaves the system more susceptible to aliasing effects, requiring

more complex analog anti-aliasing filters at the inputs. Loading on the host processor increases because it must

toggle the START pin or send a START command to initiate a new conversion cycle.

START

t_SETTLE

4/f_CLK

Data Updating

DRDY

Figure 35. DRDY with No Data Retrieval in Single-Shot Mode

MULTIPLE DEVICE CONFIGURATION

The ADS1191/2 are designed to provide configuration flexibility when multiple devices are used in a system. The

serial interface typically needs four signals: DIN, DOUT, SCLK, and CS. With one additional chip select signal

per device, multiple devices can be connected together. The number of signals needed to interface n devices is

3 + n.

The right leg drive amplifiers can be daisy-chained as explained in the RLD Configuration with Multiple Devices

subsection of the ECG-Specific Functions section. To use the internal oscillator in a daisy-chain configuration,

one of the devices must be set as the master for the clock source with the internal oscillator enabled (CLKSEL

pin = 1) and the internal oscillator clock brought out of the device by setting the CLK_EN register bit to '1'. This

master device clock is used as the external clock source for the other devices.

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When using multiple devices, the devices can be synchronized with the START signal. The delay from START to

the DRDY signal is fixed for a fixed data rate (see the START subsection of the SPI Interface section for more

details on the settling times). Figure 36 shows the behavior of two devices when synchronized with the START

signal.

Device₁

START

CLK

START₁

CLK

DRDY₁

DRDY

Device₂

START₂

CLK

DRDY₂

DRDY

CLK

Note 1

START

DRDY₁

DRDY₂

Note 2

(1) Start pulse must be at least one t_MODcycle wide.

(2) Settling time number uncertainty is one t_MODcycle.

Figure 36. Synchronizing Multiple Converters

Standard Mode

Figure 37 shows a configuration with two devices cascaded together. One of the devices is an ADS1192

(two-channel) and the other is an ADS1192 (two-channel). Together, they create a system with four channels.

DOUT, SCLK, and DIN are shared. Each device has its own chip select. When a device is not selected by the

corresponding CS being driven to logic 1, the DOUT of this device is high-impedance. This structure allows the

other device to take control of the DOUT bus.

START⁽¹⁾

START

DRDY

CS

INT

CLK

GPO0

GPO1

SCLK

MOSI

MISO

SCLK

DIN

Device 2

DOUT

Host Processor

START

CLK

DRDY

CS

SCLK

DIN

Device 1

DOUT

Figure 37. Multiple Device Configurations

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SPI COMMAND DEFINITIONS

The ADS1191/2 provide flexible configuration control. The opcode commands, summarized in Table 7, control

and configure the operation of the ADS1191/2. The opcode commands are stand-alone, except for the register

read and register write operations that require a second command byte plus data. CS can be taken high or held

low between opcode commands but must stay low for the entire command operation (especially for multi-byte

commands). System opcode commands and the RDATA command are decoded by the ADS1191/2 on the

seventh falling edge of SCLK. The register read/write opcodes are decoded on the eighth SCLK falling edge. Be

sure to follow SPI timing requirements when pulling CS high after issuing a command.

Table 7. Command Definitions

COMMAND

System Commands

WAKEUP

DESCRIPTION

FIRST BYTE

SECOND BYTE

Wake-up from standby mode

Enter standby mode

0000 0010 (02h)

0000 0100 (04h)

0000 0110 (06h)

0000 1000 (08h)

0000 1010 (0Ah)

0001 1010 (1Ah)

STANDBY

RESET

Reset the device

START

Start/restart (synchronize) conversions

Stop conversion

STOP

OFFSETCAL

Channel offset calibration

Data Read Commands

Enable Read Data Continuous mode.

RDATAC

0001 0000 (10h)

This mode is the default mode at power-up.⁽¹⁾

SDATAC

RDATA

Stop Read Data Continuously mode

0001 0001 (11h)

0001 0010 (12h)

Read data by command; supports multiple read back.

Register Read Commands

RREG

WREG

Read n nnnn registers starting at address r rrrr

Write n nnnn registers starting at address r rrrr

001r rrrr (2xh)⁽²⁾

010r rrrr (4xh)⁽²⁾

000n nnnn⁽²⁾

(1) When in RDATAC mode, the RREG command is ignored.

(2) n nnnn = number of registers to be read/written – 1. For example, to read/write three registers, set n nnnn = 0 (0010). r rrrr = starting

register address for read/write opcodes.

WAKEUP: Exit STANDBY Mode

This opcode exits the low-power standby mode; see the STANDBY: Enter STANDBY Mode subsection of the

SPI Command Definitions section. Time is required when exiting standby mode (see the Electrical

Characteristics for details). There are no restrictions on the SCLK rate for this command and it can be

issued any time. Any following command must be sent after 4 t_CLKcycles.

STANDBY: Enter STANDBY Mode

This opcode command enters the low-power standby mode. All parts of the circuit are shut down except for the

reference section. The standby mode power consumption is specified in the Electrical Characteristics. There are

no restrictions on the SCLK rate for this command and it can be issued any time. Do not send any other

command other than the wakeup command after the device enters the standby mode.

RESET: Reset Registers to Default Values

This command resets the digital filter cycle and returns all register settings to the default values. See the Reset

(RESET) subsection of the SPI Interface section for more details. There are no restrictions on the SCLK rate

for this command and it can be issued any time. It takes 9 f_MODcycles to execute the RESET command.

Avoid sending any commands during this time.

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START: Start Conversions

This opcode starts data conversions. Tie the START pin low to control conversions by command. If conversions

are in progress this command has no effect. The STOP opcode command is used to stop conversions. If the

START command is immediately followed by a STOP command then have a gap of 4 t_CLKcycles between them.

When the START opcode is sent to the device, keep the START pin low until the STOP command is issued.

(See the START subsection of the SPI Interface section for more details.) There are no restrictions on the

SCLK rate for this command and it can be issued any time.

STOP: Stop Conversions

This opcode stops conversions. Tie the START pin low to control conversions by command. When the STOP

command is sent, the conversion in progress completes and further conversions are stopped. If conversions are

already stopped, this command has no effect. There are no restrictions on the SCLK rate for this command and it

can be issued any time.

OFFSETCAL: Channel Offset Calibration

This command is used to cancel the channel offset. The CALIB_ON bit in the MISC2 register must be set to '1'

before issuing this command. OFFSETCAL must be executed every time there is a change in the PGA gain

settings.

RDATAC: Read Data Continuous

This opcode enables the output of conversion data on each DRDY without the need to issue subsequent read

data opcodes. This mode places the conversion data in the output register and may be shifted out directly. The

read data continuous mode is the default mode of the device and the device defaults in this mode on power-up.

RDATAC mode is cancelled by the Stop Read Data Continuous command. If the device is in RDATAC mode, an

SDATAC command must be issued before any other commands can be sent to the device. There is no

restriction on the SCLK rate for this command. However, the subsequent data retrieval SCLKs or the SDATAC

opcode command should wait at least 4 t_CLKcycles. The timing for RDATAC is shown in Figure 38. As Figure 38

shows, there is a keep out zone of 4 t_CLKcycles around the DRDY pulse where this command cannot be issued

in. If no data are retrieved from the device, DOUT and DRDY behave similarly in this mode. To retrieve data from

the device after the RDATAC command is issued, make sure either the START pin is high or the START

command is issued. Figure 38 shows the recommended way to use the RDATAC command. RDATAC is ideally

suited for applications such as data loggers or recorders where registers are set once and do not need to be

re-configured.

START

DRDY

(1)

t_UPDATE

CS

SCLK

RDATAC Opcode

DIN

Hi-Z

Status Register + 2-Channel Data

DOUT

Next Data

(1) t_UPDATE= 4 * t_CLK. Do not read data during this time.

Figure 38. RDATAC Usage

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SDATAC: Stop Read Data Continuous

This opcode cancels the Read Data Continuous mode. There is no restriction on the SCLK rate for this

command, but the following command must wait for 4 t_CLKcycles.

RDATA: Read Data

Issue this command after DRDY goes low to read the conversion result (in Stop Read Data Continuous mode).

There is no restriction on the SCLK rate for this command, and there is no wait time needed for the subsequent

commands or data retrieval SCLKs. To retrieve data from the device after the RDATA command is issued, make

sure either the START pin is high or the START command is issued. When reading data with the RDATA

command, the read operation can overlap the occurrence of the next DRDY without data corruption. Figure 39

shows the recommended way to use the RDATA command. RDATA is best suited for ECG- and EEG-type

systems where register setting must be read or changed often between conversion cycles.

START

DRDY

CS

SCLK

RDATA Opcode

DIN

Hi-Z

Status Register+ 8-Channel Data (216 Bits)

DOUT

Figure 39. RDATA Usage

Sending Multi-Byte Commands

The ADS1191/2 serial interface decodes commands in bytes and requires 4 t_CLKcycles to decode and execute.

Therefore, when sending multi-byte commands, a 4 t_CLKperiod must separate the end of one byte (or opcode)

and the next.

Assume CLK is 512 kHz, then t_SDECODE(4 t_CLK) is 7.8125 µs. When SCLK is 16 MHz, one byte can be

transferred in 500 ns. This byte transfer time does not meet the t_SDECODEspecification; therefore, a delay must be

inserted so the end of the second byte arrives 7.3125 µs later. If SCLK is 1 MHz, one byte is transferred in 8 µs.

Because this transfer time exceeds the t_SDECODEspecification, the processor can send subsequent bytes without

delay. In this later scenario, the serial port can be programmed to cease single-byte transfer per cycle to multiple

bytes.

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RREG: Read From Register

This opcode reads register data. The Register Read command is a two-byte opcode followed by the output of the

register data. The first byte contains the command opcode and the register address. The second byte of the

opcode specifies the number of registers to read – 1.

First opcode byte: 001r rrrr, where r rrrr is the starting register address.

Second opcode byte: 000n nnnn, where n nnnn is the number of registers to read – 1.

The 17th SCLK rising edge of the operation clocks out the MSB of the first register, as shown in Figure 40. When

the device is in read data continuous mode it is necessary to issue a SDATAC command before the RREG

command can be issued. The RREG command can be issued any time. However, because this command is a

multi-byte command, there are restrictions on the SCLK rate depending on the way the SCLKs are issued. See

the Serial Clock (SCLK) subsection of the SPI Interface section for more details. Note that CS must be low for

the entire command.

CS

1

9

17

25

SCLK

DIN

OPCODE 1

OPCODE 2

REG DATA

REG DATA + 1

DOUT

Figure 40. RREG Command Example: Read Two Registers Starting from Register 00h (ID Register)

(OPCODE 1 = 0010 0000, OPCODE 2 = 0000 0001)

WREG: Write to Register

This opcode writes register data. The Register Write command is a two-byte opcode followed by the input of the

register data. The first byte contains the command opcode and the register address.

The second byte of the opcode specifies the number of registers to write – 1.

First opcode byte: 010r rrrr, where r rrrr is the starting register address.

Second opcode byte: 000n nnnn, where n nnnn is the number of registers to write – 1.

After the opcode bytes, the register data follows (in MSB-first format), as shown in Figure 41. The WREG

command can be issued any time. However, because this command is a multi-byte command, there are

restrictions on the SCLK rate depending on the way the SCLKs are issued. See the Serial Clock (SCLK)

subsection of the SPI Interface section for more details. Note that CS must be low for the entire command.

CS

1

9

17

25

SCLK

DIN

OPCODE 1

OPCODE 2

REG DATA 1

REG DATA 2

DOUT

Figure 41. WREG Command Example: Write Two Registers Starting from 00h (ID Register)

(OPCODE 1 = 0100 0000, OPCODE 2 = 0000 0001)

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REGISTER MAP

Table 8 describes the various ADS1191/2 registers.

Table 8. Register Assignments

RESET

VALUE

(Hex)

ADDRESS

REGISTER

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

Device Settings (Read-Only Registers)

00h ID

Global Settings Across Channels

XX

02

REV_ID7

REV_ID6

REV_ID5

1

0

REV_ID1

REV_ID0

SINGLE_

SHOT

01h

CONFIG1

0

DR2

DR1

DR0

PDB_LOFF_

COMP

02h

03h

CONFIG2

LOFF

80

10

1

PDB_REFBUF

COMP_TH0

VREF_4V

1

CLK_EN

0

INT_TEST

0

TEST_FREQ

FLEAD_OFF

COMP_TH2

COMP_TH1

ILEAD_OFF1

ILEAD_OFF0

Channel-Specific Settings

04h

05h

CH1SET

CH2SET

00

PD1

PD2

GAIN1_2

GAIN2_2

GAIN1_1

GAIN2_1

GAIN1_0

GAIN2_0

MUX1_3

MUX2_3

MUX1_2

MUX2_2

MUX1_1

MUX2_1

MUX1_0

MUX2_0

RLD_LOFF_

SENS

06h

07h

08h

RLD_SENS

LOFF_SENS

LOFF_STAT

00

0

PDB_RLD

FLIP2

0

RLD2N

LOFF2N

RLD2P

LOFF2P

RLD1N

LOFF1N

RLD1P

LOFF1P

FLIP1

RLD_STAT

(read only)

CLK_DIV

IN2N_OFF

IN2P_OFF

IN1N_OFF

IN1P_OFF

GPIO and Other Registers

09h

0Ah

0Bh

MISC1

MISC2

GPIO

00

02

0C

0

1

0

CALIB_ON

0

RLDREF_INT

GPIOD2

GPIOC2

GPIOC1

GPIOD1

User Register Description

ID: ID Control Register (Factory-Programmed, Read-Only)

Address = 00h

BIT 7

BIT 6

BIT 5

BIT 4

1

BIT 3

0

BIT 2

0

BIT 1

REV_ID1

BIT 0

REV_ID7

REV_ID6

REV_ID5

REV_ID0

The ID Control Register is programmed during device manufacture to indicate device characteristics.

Bits[7:5]

REV_ID[7:5]: Revision identification

000 = Reserved

001 = Reserved

010 = ADS1x9x device

011 = ADS1292R device

100 = Reserved

101 = Reserved

110 = Reserved

111 = Reserved

Bit 4

Reads high

Bits[3:2]

Bits[1:0]

Reads low

REV_ID[1:0]: Revision identification

00 = ADS1191

01 = ADS1192

10 = ADS1291

11 = ADS1292/2R

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CONFIG1: Configuration Register 1

Address = 01h

BIT 7

BIT 6

0

BIT 5

0

BIT 4

0

BIT 3

0

BIT 2

DR2

BIT 1

DR1

BIT 0

DR0

SINGLE_SHOT

Configuration Register 1 configures each ADC channel sample rate.

Bit 7

SINGLE_SHOT: Single-shot conversion

This bit sets the conversion mode

0 = Continuous conversion mode (default)

1 = Single-shot mode

Bits[6:3]

Bits[2:0]

Must be set to '0'

DR[2:0]: Channel oversampling ratio

These bits determine the oversampling ratio of both channel 1 and channel 2.

BIT

000

001

010

011

100

101

110

111

OVERSAMPLING RATIO

f_MOD/1024

f_MOD/512

DATA RATE⁽¹⁾

125 SPS

250 SPS

f_MOD/256

500 SPS (default)

1 kSPS

f_MOD/128

f_MOD/64

2 kSPS

f_MOD/32

4 kSPS

f_MOD/16

8 kSPS

Do not use

(1) f_CLK= 512 kHz and CLK_DIV = 0 or f_CLK= 2.048 MHz and CLK_DIV = 1.

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CONFIG2: Configuration Register 2

Address = 02h

BIT 7

1

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

0

BIT 1

INT_TEST

BIT 0

PDB_LOFF_

COMP

PDB_REFBUF

VREF_4V

CLK_EN

TEST_FREQ

Configuration Register 2 configures the test signal, clock, reference, and LOFF buffer.

Bit 7

Bit 6

Must be set to '1'

PDB_LOFF_COMP: Lead-off comparator power-down

This bit powers down the lead-off comparators.

0 = Lead-off comparators disabled (default)

1 = Lead-off comparators enabled

Bit 5

Bit 4

Bit 3

PDB_REFBUF: Reference buffer power-down

This bit powers down the internal reference buffer so that the external reference can be used.

0 = Reference buffer is powered down (default)

1 = Reference buffer is enabled

VREF_4V: Enables 4-V reference

This bit chooses between 2.42-V and 4.033-V reference.

0 = 2.42-V reference (default)

1 = 4.033-V reference

CLK_EN: CLK connection

This bit determines if the internal oscillator signal is connected to the CLK pin when an internal oscillator is used.

0 = Oscillator clock output disabled (default)

1 = Oscillator clock output enabled

Bit 2

Bit 1

Must be set to '0'

INT_TEST: Test signal selection

This bit determines whether the test signal is turned on or off.

0 = Off (default)

1 = On; amplitude = ±(VREFP – VREFN)/2420

Bit 0

TEST_FREQ: Test signal frequency.

This bit determines the test signal frequency.

0 = At dc (default)

1 = Square wave at 1 Hz

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LOFF: Lead-Off Control Register

Address = 03h

BIT 7

BIT 6

BIT 5

BIT 4

1

BIT 3

BIT 2

BIT 1

0

BIT 0

COMP_TH2

COMP_TH1

COMP_TH0

ILEAD_OFF1

ILEAD_OFF0

FLEAD_OFF

The Lead-Off Control Register configures the Lead-Off detection operation.

Bits[7:5]

COMP_TH[2:0]: Lead-off comparator threshold

These bits determine the lead-off comparator threshold. See the Lead-Off Detection subsection of the ECG-Specific

Functions section for a detailed description.

Comparator positive side

000 = 95% (default)

001 = 92.5%

010 = 90%

011 = 87.5%

100 = 85%

101 = 80%

110 = 75%

111 = 70%

Comparator negative side

000 = 5% (default)

001 = 7.5%

010 = 10%

011 = 12.5%

100 = 15%

101 = 20%

110 = 25%

111 = 30%

Bit 4

Must be set to '1'

Bits[3:2]

ILEAD_OFF[1:0]: Lead-off current magnitude

These bits determine the magnitude of current for the current lead-off mode.

00 = 6 nA (default)

01 = 22 nA

10 = 6 µA

11 = 22 µA

Bit 1

Bit 0

Must be set to '0'

FLEAD_OFF: Lead-off frequency

This bit selects ac or dc lead-off.

0 = At dc lead-off detect (default)

1 = At ac lead-off detect at f_DR/4 (500 Hz for an 2-kHz output rate)

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CH1SET: Channel 1 Settings

Address = 04h

BIT 7

PD1

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

MUX1_1

BIT 0

GAIN1_2

GAIN1_1

GAIN1_0

MUX1_3

MUX1_2

MUX1_0

The CH1SET Control Register configures the power mode, PGA gain, and multiplexer settings channels. See the

Input Multiplexer section for details.

Bit 7

PD1: Channel 1 power-down

0 = Normal operation (default)

1 = Channel 1 power-down

Bits[6:4]

GAIN1[2:0]: Channel 1 PGA gain setting

These bits determine the PGA gain setting for channel 1.

000 = 6 (default)

001 = 1

010 = 2

011 = 3

100 = 4

101 = 8

110 = 12

111 = Not available

Bits[3:0]

MUX1[3:0]: Channel 1 input selection

These bits determine the channel 1 input selection.

0000 = Normal electrode input (default)

0001 = Input shorted (for offset measurements)

0010 = RLD_MEASURE

0011 = MVDD for supply measurement

0100 = Temperature sensor

0101 = Test signal

0110 = RLD_DRP (positive input is connected to RLDIN)

0111 = RLD_DRM (negative input is connected to RLDIN)

1000 = RLD_DRPM (both positive and negative inputs are connected to RLDIN)

1001 = Route IN3P and IN3N to channel 1 inputs

1010 = Reserved

1011 = Reserved

1100 = Reserved

1101 = Reserved

1110 = Reserved

1111 = Reserved

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CH2SET: Channel 2 Settings

Address = 05h

BIT 7

PD2

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

GAIN2_2

GAIN2_1

GAIN2_0

MUX2_3

MUX2_2

MUX2_1

MUX2_0

The CH2SET Control Register configures the power mode, PGA gain, and multiplexer settings channels. See the

Input Multiplexer section for details.

Bit 7

PD2: Channel 2 power-down

0 = Normal operation (default)

1 = Channel 2 power-down

Bits[6:4]

GAIN2[2:0]: Channel 2 PGA gain setting

These bits determine the PGA gain setting for channel 2.

000 = 6 (default)

001 = 1

010 = 2

011 = 3

100 = 4

101 = 8

110 = 12

Bits[3:0]

MUX2[3:0]: Channel 2 input selection

These bits determine the channel 2 input selection.

0000 = Normal electrode input (default)

0001 = Input shorted (for offset measurements)

0010 = RLD_MEASURE

0011 = VDD/2 for supply measurement

0100 = Temperature sensor

0101 = Test signal

0110 = RLD_DRP (positive electrode is the driver)

0111 = RLD_DRM (negative electrode is the driver)

1000 = Reserved

1001 = Route IN3P and IN3N to channel 2 inputs

1010 = Reserved

1011 = Reserved

1100 = Reserved

1101 = Reserved

1110 = Reserved

1111 = Reserved

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RLD_SENS: Right Leg Drive Sense Selection

Address = 06h

BIT 7

0

BIT 6

0

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

RLD1N

BIT 0

RLD_LOFF_

SENS

PDB_RLD

RLD2N

RLD2P

RLD1P

This register controls the selection of the positive and negative signals from each channel for right leg drive

derivation. See the Right Leg Drive (RLD DC Bias Circuit) subsection of the ECG-Specific Functions section for

details.

Bits[7:6]

Bit 5

Must be set to '0'

PDB_RLD: RLD buffer power

This bit determines the RLD buffer power state.

0 = RLD buffer is powered down (default)

1 = RLD buffer is enabled

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

RLD_LOFF_SENSE: RLD lead-off sense function

This bit enables the RLD lead-off sense function.

0 = RLD lead-off sense is disabled (default)

1 = RLD lead-off sense is enabled

RLD2N: Channel 2 RLD negative inputs

This bit controls the selection of negative inputs from channel 2 for right leg drive derivation.

0 = Not connected (default)

1 = RLD connected to IN2N

RLD2P: Channel 2 RLD positive inputs

This bit controls the selection of positive inputs from channel 2 for right leg drive derivation.

0 = Not connected (default)

1 = RLD connected to IN2P

RLD1N: Channel 1 RLD negative inputs

This bit controls the selection of negative inputs from channel 1 for right leg drive derivation.

0 = Not connected (default)

1 = RLD connected to IN1N

RLD1P: Channel 1 RLD positive inputs

This bit controls the selection of positive inputs from channel 1 for right leg drive derivation.

0 = Not connected (default)

1 = RLD connected to IN1P

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LOFF_SENS: Lead-Off Sense Selection

Address = 07h

BIT 7

0

BIT 6

0

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

FLIP2

FLIP1

LOFF2N

LOFF2P

LOFF1N

LOFF1P

This register selects the positive and negative side from each channel for lead-off detection. See the Lead-Off

Detection subsection of the ECG-Specific Functions section for details. Note that the LOFF_STAT register bits

should be ignored if the corresponding LOFF_SENS bits are set to '1'.

Bits[7:6]

Bit 5

Must be set to '0'

FLIP2: Current direction selection

This bit controls the direction of the current used for lead-off derivation for channel 2.

0 = Disabled (default)

1 = Enabled

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

FLIP1: Current direction selection

This bit controls the direction of the current used for lead-off derivation for channel 1.

0 = Disabled (default)

1 = Enabled

LOFF2N: Channel 2 lead-off detection negative inputs

This bit controls the selection of negative input from channel 2 for lead-off detection.

0 = Disabled (default)

1 = Enabled

LOFF2P: Channel 2 lead-off detection positive inputs

This bit controls the selection of positive input from channel 2 for lead-off detection.

0 = Disabled (default)

1 = Enabled

LOFF1N: Channel 1 lead-off detection negative inputs

This bit controls the selection of negative input from channel 1 for lead-off detection.

0 = Disabled (default)

1 = Enabled

LOFF1P: Channel 1 lead-off detection positive inputs

This bit controls the selection of positive input from channel 1 for lead-off detection.

0 = Disabled (default)

1 = Enabled

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LOFF_STAT: Lead-Off Status

Address = 08h

BIT 7

0

BIT 6

BIT 5

0

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

RLD_STAT

(read only)

IN2N_OFF

(read only)

IN2P_OFF

(read only)

IN1N_OFF

(read only)

IN1P_OFF

(read only)

CLK_DIV

This register stores the status of whether the positive or negative electrode on each channel is on or off. See the

Lead-Off Detection subsection of the ECG-Specific Functions section for details. Ignore the LOFF_STAT values

if the corresponding LOFF_SENS bits are not set to '1'.

'0' is lead-on (default) and '1' is lead-off. When the LOFF_SENS bits[3:0] are '0', the LOFF_STAT bits should be

ignored.

Bit 7

Bit 6

Must be set to '0'

CLK_DIV: Clock divider selection

This bit sets the divider ratio between f_CLKand f_MOD. Two external clock values are supported: 512 kHz and 2.048 MHz.

This bit must be set so that f_MOD= 128 kHz.

0 = f_CLK/4 (default, when f_CLK= 512 kHz)

1 = f_CLK/16 (when f_CLK= 2.048 MHz)

Bit 5

Bit 4

Must be set to '0'

RLD_STAT: RLD lead-off status

This bit determines the status of RLD.

0 = RLD is connected (default)

1 = RLD is not connected

Bit 3

Bit 2

Bit 1

Bit 0

IN2N_OFF: Channel 2 negative electrode status

This bit determines if the channel 2 negative electrode is connected or not.

0 = Connected (default)

1 = Not connected

IN2P_OFF: Channel 2 positive electrode status

This bit determines if the channel 2 positive electrode is connected or not.

0 = Connected (default)

1 = Not connected

IN1N_OFF: Channel 1 negative electrode status

This bit determines if the channel 1 negative electrode is connected or not.

0 = Connected (default)

1 = Not connected

IN1P_OFF: Channel 1 positive electrode status

This bit determines if the channel 1 positive electrode is connected or not.

0 = Connected (default)

1 = Not connected

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MISC1: Miscellaneous Control Register 1

Address = 09h

BIT 7

0

BIT 6

0

BIT 5

0

BIT 4

0

BIT 3

0

BIT 2

0

BIT 1

1

BIT 0

0

This register controls the miscellaneous functionality. For the ADS1191 and ADS1192 devices, 02h must be

written to the MISC1 register.

Bits[7:2]

Bit 6

Must be set to '0'

Must be set to '1'

Must be set to '0'

Bit 0

MISC2: Miscellaneous Control Register 2

Address = 0Ah

BIT 7

BIT 6

0

BIT 5

0

BIT 4

0

BIT 3

0

BIT 2

0

BIT 1

BIT 0

0

CALIB_ON

RLDREF_INT

This register controls the calibration functionality.

Bit 7

CALIB_ON: Calibration on

This bit is used to enable offset calibration.

0 = Off (default)

1 = On

Bits[6:2]

Bit 1

Must be '0'

RLDREF_INT: RLDREF signal

This bit determines the RLDREF signal source.

0 = RLDREF is external (default)

1 = RLDREF is fed internally

Bit 0

Must be set to '0'

GPIO: General-Purpose I/O Register

Address = 0Bh

BIT 7

0

BIT 6

0

BIT 5

0

BIT 4

0

BIT 3

BIT 2

BIT 1

BIT 0

GPIOC2

GPIOC1

GPIOD2

GPIOD1

This register controls the GPIO pins.

Bits[7:4]

Bits[3:2]

Must be '0'

GPIOC[2:1]: GPIO 1 and 2 control

These bits determine if the corresponding GPIOD pin is an input or output.

0 = Output

1 = Input (default)

Bits[1:0]

GPIOD[2:1]: GPIO 1 and 2 data

These bits are used to read and write data to the GPIO ports.

When reading the register, the data returned correspond to the state of the GPIO external pins, whether they are

programmed as inputs or as outputs. As outputs, a write to the GPIOD sets the output value. As inputs, a write to the

GPIOD has no effect.

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ECG-SPECIFIC FUNCTIONS

INPUT MULTIPLEXER (REROUTING THE RIGHT LEG DRIVE SIGNAL)

The input multiplexer has ECG-specific functions for the right leg drive signal. The RLD signal is available at the

RLDOUT pin once the appropriate channels are selected for the RLD derivation, feedback elements are installed

external to the chip, and the loop is closed. This signal can be fed after filtering or fed directly into the RLDIN pin

as shown in Figure 42. This RLDIN signal can be multiplexed into any one of the input electrodes by setting the

MUX bits of the appropriate channel set registers to '0110' for P-side or '0111' for N-side. Figure 42 shows the

RLD signal generated from channel 1 and routed to the N-side of channel 2. This feature can be used to

dynamically change the electrode that is used as the reference signal to drive the patient body. Note that the

corresponding channel cannot be used and can be powered down.

RLD1P = 1

IN1P

EMI

Filter

PGA1

PGA2

RLD1N = 1

MUX1[3:0] = 0000

IN1N

IN2P

RLD2P = 0

RLD2N = 0

EMI

Filter

MUX1[3:0] = 0111

IN2N

RLDREF_INT = 1

(AVDD + AVSS)

MUX

2

RLDREF_INT = 0

RLD_AMP

Device

RLDIN/RLDREF

RLDOUT

RLDINV

(1)

1 M

Filter or

Feedthrough

1.5 nF⁽¹⁾

(1) Typical values for example only.

Figure 42. Example of RLDOUT Signal Configured to be Routed to IN2N

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Input Multiplexer (Measuring the Right Leg Drive Signal)

Also, the RLDOUT signal can be routed to a channel (that is not used for the calculation of RLD) for

measurement. Figure 43 shows the register settings to route the RLDIN signal to channel 2. The measurement is

done with respect to the voltage on the RLDREF pin. If RLDREF is chosen to be internal, it would be at (AVDD +

AVSS)/2. This feature is useful for debugging purposes during product development.

RLD1P = 1

IN1P

EMI

Filter

PGA1

PGA2

RLD1N = 1

MUX1[3:0] = 0000

IN1N

IN2P

RLD2P = 0

RLD2N = 0

EMI

Filter

MUX1[3:0] = 0010

IN2N

RLDREF_INT = 1

(AVDD + AVSS)

2

MUX

MUX1[3:0] = 0010

RLDREF_INT = 0

RLD_AMP

Device

RLDIN/RLDREF

RLDOUT

RLDINV

(1)

1 M

Filter or

Feedthrough

1.5 nF⁽¹⁾

(1) Typical values for example only.

Figure 43. RLDOUT Signal Configured to be Read Back by Channel 2

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LEAD-OFF DETECTION

Patient electrode impedances are known to decay over time. It is necessary to continuously monitor these

electrode connections to verify a suitable connection is present. The ADS1191/2 lead-off detection functional

block provides significant flexibility to the user to choose from various lead-off detection strategies. Though called

lead-off detection, this is in fact an electrode-off detection.

The basic principle is to inject an excitation signal and measure the response to find out if the electrode is off. As

shown in the lead-off detection functional block diagram in Figure 44, this circuit provides two different methods

of determining the state of the patient electrode. The methods differ in the frequency content of the excitation

signal. Lead-off can be selectively done on a per channel basis using the LOFF_SENS register. Also, the internal

excitation circuitry can be disabled and just the sensing circuitry can be enabled.

Skin,

Patient

Patient Electrode Contact Protection

Model

Resistor

47 nF

51 k

IN1P_OFF/

IN2P_OFF

30 k

V_INP

V_INN

EMI

Filter

PGA

To ADC

51 k

LOFF1P/

LOFF2P

LOFF1N/

LOFF2N

47 nF

IN1N_OFF/

IN2N_OFF

47 nF

51 k

4-Bit

DAC

AVDD AVSS

COMP_TH[2:0]

30 k

RLD OUT

NOTE: The R_Pvalue must be selected in order to be below the maximum allowable current flow into a patient (in accordance with the

relevant specification the latest revision of IEC 60601).

Figure 44. Lead-Off Detection

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DC Lead-Off

In this method, the lead-off excitation is with a dc signal. The dc excitation signal can be chosen from either an

external pull-up/pull-down resistor or a current source/sink, as shown in Figure 45. One side of the channel is

pulled to supply and the other side is pulled to ground. The internal current source and current sink can be

swapped by setting thebits in the LOFF_FLIP register. In case of current source/sink, the magnitude of the

current can be set by using the ILEAD_OFF[1:0] bits in the LOFF register. The current source/sink gives larger

input impedance compared to the 10-MΩ pull-up/pull-down resistor.

AVDD

Device

10 MW

INP

INN

INP

INN

PGA

10 MW

a) External Pull-Up/Pull-Down Resistors

b) Input Current Source

Figure 45. DC Lead-Off Excitation Options

Sensing of the response can be done either by looking at the digital output code from the device or by monitoring

the input voltages with an on-chip comparator. If either of the electrodes is off, the pull-up resistors and/or the

pull-down resistors saturate the channel. By looking at the output code it can be determined that either the P-side

or the N-side is off. To pinpoint which one is off, the comparators must be used. The input voltage is also

monitored using a comparator and a 4-bit digital-to-analog converter (DAC) whose levels are set by the

COMP_TH[2:0] bits in the LOFF register. The output of the comparators are stored in the LOFF_STAT register.

These two registers are available as a part of the output data stream. (See the Data Output Protocol (DOUT)

subsection of the SPI Interface section.) If dc lead-off is not used, the lead-off comparators can be powered

down by setting the PD_LOFF_COMP bit in the CONFIG2 register.

An example procedure to turn on dc lead-off is given in the Lead-Off subsection of the Quick-Start Guide section.

AC Lead-Off

In this method, an out-of-band ac signal is used for excitation. The ac signal is generated by alternatively

providing an internal current source and current sink at the input with a fixed frequency. The excitation frequency

is a function of the output data rate and is f_DR/4. This out-of-band excitation signal is passed through the channel

and measured at the output.

Sensing of the ac signal is done by passing the signal through the channel to digitize it and measure at the

output. The ac excitation signals are introduced at a frequency that is above the band of interest, generating an

out-of-band differential signal that can be filtered out separately and processed. By measuring the magnitude of

the excitation signal at the output spectrum, the lead-off status can be calculated. Therefore, the ac lead-off

detection can be accomplished simultaneously with the ECG signal acquisition.

48

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RLD Lead-Off

The ADS1191/2 provide two modes for determining whether the RLD is correctly connected:

•

RLD lead-off detection during normal operation

RLD lead-off detection during power-up

The following sections provide details of the two modes of operation.

RLD Lead-Off Detection During Normal Operation

During normal operation, the ADS1191/2 RLD lead-off at power-up function cannot be used because it is

necessary to power off the RLD amplifier.

RLD Lead-Off Detection At Power-Up

This feature is included in the ADS1191/2 for use in determining whether the right leg electrode is suitably

connected. At power-up, the ADS1191/2 provides a procedure to determine the RLD electrode connection status

using a current sink, as shown in Figure 46. The reference level of the comparator is set to determine the

acceptable RLD impedance threshold.

Skin,

Patient

Patient Electrode Contact Protection

Model

47 nF

Resistor

To ADC input (through V_REF

connection to any of the channels).

RLD_STAT

30 k

51 k

RLD_LOFF_SENS

AVSS

NOTE: The R_Pvalue must be selected in order to be below the maximum allowable current flow into a patient (in accordance with the

relevant specification the latest revision of IEC 60601).

Figure 46. RLD Lead-Off Detection at Power-Up

When the RLD amplifier is powered on, the current source has no function. Only the comparator can be used to

sense the voltage at the output of the RLD amplifier. The comparator thresholds are set by the same LOFF[7:5]

bits used to set the thresholds for other negative inputs.

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Right Leg Drive (RLD DC Bias Circuit)

The right leg drive (RLD) circuitry is used as a means to counter the common-mode interference in an ECG

system as a result of power lines and other sources, including fluorescent lights. The RLD circuit senses the

common-mode of a selected set of electrodes and creates a negative feedback loop by driving the body with an

inverted common-mode signal. The negative feedback loop restricts the common-mode movement to a narrow

range, depending on the loop gain. Stabilizing the entire loop is specific to the individual user system based on

the various poles in the loop. The ADS1191/2 integrates the muxes to select the channel and an operational

amplifier. All the amplifier terminals are available at the pins, allowing the user to choose the components for the

feedback loop. The circuit shown in Figure 47 shows the overall functional connectivity for the RLD bias circuit.

From

MUX1P

RLD1P

400 k

PGA1P

From

MUX2P

150 k

RLD2P

400 k

PGA2P

PGA2N

60 k

150 k

60 k

400 k

PGA1N

From

RLD1N

MUX1N

400 k

From

MUX2N

RLD2N

RLDINV

(1)

C_EXT

1.5 nF

R_EXT

1 M

RLD

Amp

(AVDD + AVSS)

2

RLDOUT

RLDREF_INT

RLDIN/RLDREF

RLDREF_INT

To MUX

(1) Typical values.

Figure 47. RLD Channel Selection

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The reference voltage for the right leg drive can be chosen to be internally generated (AVDD + AVSS)/2 or it can

be provided externally with a resistive divider. The selection of an internal versus external reference voltage for

the RLD loop is defined by writing the appropriate value to the RLDREF_INT bit in the MISC2 register.

If the RLD function is not used, the amplifier can be powered down using the PDB_RLD bit. This bit is also used

in daisy-chain mode to power-down all but one of the RLD amplifiers.

The functionality of the RLDIN pin is explained in the Input Multiplexer section. An example procedure to use the

RLD amplifier is shown in the Right Leg Drive subsection of the Quick-Start Guide section.

RLD Configuration with Multiple Devices

Figure 48 shows multiple devices connected to an RLD.

(AVDD+AVSS)

2

(AVDD+AVSS)

2

(AVDD+AVSS)

2

Device N

VA2

Device 2

VA2

Device 1

VA2

VA1

Power-Down

RLDIN/

RLDREF

RLDIN/

RLDREF

R_EXT

C_EXT

RLD

OUT

RLD

OUT

RLDIN/

RLDREF

RLDINV

RLD

OUT

Figure 48. RLD Connection for Multiple Devices

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QUICK-START GUIDE

PCB LAYOUT

Power Supplies and Grounding

The ADS1191/2 have two supplies: AVDD and DVDD. AVDD should be as quiet as possible. AVDD provides the

supply to the charge pump block and has transients at f_CLK. It is important to eliminate noise from AVDD that is

non-synchronous with the ADS1191/2 operation. Each supply of the ADS1191/2 should be bypassed with 10-μF

and a 0.1-μF solid ceramic capacitors. It is recommended that placement of the digital circuits (DSP,

microcontrollers, FPGAs, etc.) in the system is done such that the return currents on those devices do not cross

the analog return path of the ADS1191/2. The ADS1191/2 can be powered from unipolar or bipolar supplies.

The capacitors used for decoupling can be of the surface-mount, low-cost, low-profile multi-layer ceramic type. In

most cases the VCAP1 capacitor can also be a multi-layer ceramic, but in systems where the board is subjected

to high or low frequency vibration, it is recommend that a non-ferroelectric capacitor such as a tantalum or class

1 capacitor (for example, C0G or NPO) be installed. EIA class 2 and class 3 dielectrics (such as X7R, X5R, X8R,

etc.) are ferroelectric. The piezoelectric property of these capacitors can appear as electrical noise coming from

the capacitor. When using internal reference, noise on the VCAP1 node results in performance degradation.

Connecting the Device to Unipolar (+3 V/+1.8 V) Supplies

Figure 49 illustrates the ADS1191/2 connected to a unipolar supply. In this example, the analog supply (AVDD) is

referenced to analog ground (AVSS) and the digital supply (DVDD) is referenced to digital ground (DGND).

+3 V

+1.8 V

0.1 mF

1 mF

0.1 mF

AVDD

DVDD

VREFP

VREFN

0.1 mF

10 mF

PGA1N

4.7 nF

VCAP1

VCAP2

PGA1P

Device

PGA2N

PGA2P

4.7 nF

1 mF

AVSS DGND

NOTE: Place the capacitors for supply, reference, VCAP1, and VCAP2 as close to the package as possible.

Figure 49. Single-Supply Operation

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Connecting the Device to Bipolar (±1.5 V/1.8 V) Supplies

Figure 50 illustrates the ADS1191/2 connected to a bipolar supply. In this example, the analog supplies connect

to the device analog supply (AVDD). This supply is referenced to the device analog return (AVSS), and the

digital supply (DVDD) is referenced to the device digital ground return (DGND).

+1.5 V

+1.8 V

1 mF

0.1 mF

1 mF

AVDD

DVDD

VREFP

0.1 mF

10 mF

VREFN

PGA1N

PGA1P

4.7 nF

-1.5 V

VCAP1

VCAP2

Device

PGA2N

PGA2P

4.7 nF

AVSS DGND

1 mF

0.1 mF

-1.5 V

NOTE: Place the capacitors for supply, reference, VCAP1, and VCAP2 as close to the package as possible.

Figure 50. Bipolar Supply Operation

Shielding Analog Signal Paths

As with any precision circuit, careful PCB layout ensures the best performance. It is essential to make short,

direct interconnections and avoid stray wiring capacitance—particularly at the analog input pins and AVSS.

These analog input pins are high-impedance and extremely sensitive to extraneous noise. The AVSS pin should

be treated as a sensitive analog signal and connected directly to the supply ground with proper shielding.

Leakage currents between the PCB traces can exceed the input bias current of the ADS1191/2 if shielding is not

implemented. Digital signals should be kept as far as possible from the analog input signals on the PCB.

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POWER-UP SEQUENCING

Before device power-up, all digital and analog inputs must be low. At the time of power-up, all of these signals

should remain low until the power supplies have stabilized, as shown in Figure 51. At this time, begin supplying

the master clock signal to the CLK pin. Wait for time t_POR, then transmit a RESET pulse. After releasing RESET,

the configuration register must be programmed, see the CONFIG1: Configuration Register 1 subsection of the

Register Map section for details. The power-up sequence timing is shown in Table 9.

t_POR

Power Supplies

t_RST

RESET

Start Using the Device

18 t_CLK

Figure 51. Power-Up Timing Diagram

Table 9. Power-Up Sequence Timing

SYMBOL

t_POR

DESCRIPTION

Wait after power-up until reset

Reset low width

MIN

2¹¹

1

TYP

MAX

UNIT

t_MOD

t_RST

SETTING THE DEVICE FOR BASIC DATA CAPTURE

The following section outlines the procedure to configure the device in a basic state and capture data. This

procedure is intended to put the device in a data sheet condition to check if the device is working properly in the

user's system. It is recommended that this procedure be followed initially to get familiar with the device settings.

Once this procedure has been verified, the device can be configured as needed. For details on the timings for

commands refer to the appropriate sections in the data sheet. Also, some sample programming codes are added

for the ECG-specific functions.

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// Follow Power-Up Sequencing

Analog/Digital Power-Up

Set CLKSEL Pin = 0 and

Provide External Clock

f_CLK= 512 kHz

Yes

External

Clock

No

Set CLKSEL Pin = 1

and Wait for Oscillator

to Wake Up

// If START is Tied High, After This Step

// DRDY Toggles at f_MOD/256

Set PWDN/RESET = 1

Wait for 1 s for

// Delay for Power-On Reset and Oscillator Start-Up

Power-On Reset

// Activate DUT

Issue Reset Pulse,

Wait for 18 t_CLKs

//CS can be Either Tied Permanently Low

// Or Selectively Pulled Low Before Sending

// Commands or Reading/Sending Data From/To Device

// Device Wakes Up in RDATAC Mode, so Send

// SDATAC Command so Registers can be Written

SDATAC

Send SDATAC

Command

No

Set PDB_REFBUF = 1

and Wait for Internal

Reference To Settle

// If Using Internal Reference, Send This Command

-- WREG CONFIG2 A0h

External Reference

Yes

// DRATE = 500 SPS

Write Certain Registers,

Including Input Short

WREG CONFIG1 02h

// Set All Channels to Input Short

WREG CHnSET 01h

// Activate Conversion

Set START = 1

RDATAC

// After This Point DRDY Should Toggle at

// f_CLK/256

// Put the Device Back in RDATAC Mode

RDATAC

Capture Data and

Check Noise

// Look for DRDY and Issue 16 + 2 16 SCLKs

// Activate a (1 mV V_REF/2.4) Square-Wave Test Signal

// On All Channels

SDATAC

WREG CONFIG2 A3h

WREG CHnSET 05h

RDATAC

Set Test Signals

Capture Data and

Test Signals

// Look for DRDY and Issue 16 + 2 16 SCLKs

Figure 52. Initial Flow at Power-Up

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Lead-Off

Sample code to set dc lead-off with current source/sink resistors on all channels

WREG LOFF 10h // Comparator threshold at 95% and 5%, current source/sink resistor // DC lead-off

WREG CONFIG2 E0h // Turn-on dc lead-off comparators

WREG LOFF_SENS 0Fh // Turn on both P- and Nside of all channels for lead-off sensing

Observe the status bits of the output data stream to monitor lead-off status.

Right Leg Drive

Sample code to choose RLD as an average of the first three channels.

WREG RLD_SENSP 07h // Select channel 1—3 P-side for RLD sensing

WREG RLD_SENSN 07h // Select channel 1—3 N-side for RLD sensing

WREG CONFIG3 b’x1xx 1100 // Turn on RLD amplifier, set internal RLDREF voltage

Sample code to route the RLD_OUT signal through channel 4 N-side and measure RLD with channel 5. Make

sure the external side to the chip RLDOUT is connected to RLDIN.

WREG CONFIG3 b’xxx1 1100 // Turn on RLD amplifier, set internal RLDREF voltage, set RLD measurement bit

WREG CH4SET b’1xxx 0111 // Route RLDIN to channel 4 N-side

WREG CH5SET b’1xxx 0010 // Route RLDIN to be measured at channel 5 w.r.t RLDREF

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PACKAGE MATERIALS INFORMATION

www.ti.com

14-Jul-2012

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

ADS1191IPBSR

ADS1192IPBSR

TQFP

PBS

32

1000

330.0

16.4

7.2

1.5

12.0

16.0

Q2

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

14-Jul-2012

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

ADS1191IPBSR

ADS1192IPBSR

TQFP

PBS

32

1000

367.0

38.0

Pack Materials-Page 2

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型号：	ADS1191_14
厂家：	TEXAS INSTRUMENTS
描述：	Low-Power, 2-Channel, 16-Bit Analog Front-End for Biopotential Measurements
文件：	总61页 (文件大小：1520K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ADS1191_14 [TI]

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