ADS1205_15 [TI]
Two 1-Bit, 10MHz,2nd-Order Delta-sigma Modulators;型号: | ADS1205_15 |
厂家: | TEXAS INSTRUMENTS |
描述: | Two 1-Bit, 10MHz,2nd-Order Delta-sigma Modulators |
文件: | 总22页 (文件大小:298K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
ꢛ ꢓꢖ ꢃꢍ ꢉꢜ
SBAS312A − JANUARY 2005 − REVISED APRIL 2005
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢆ
ꢇ
ꢈ
ꢆ
ꢃ
ꢉ
ꢊ
ꢋ
ꢌ
ꢈ
ꢍ
ꢎ
ꢏ
ꢄ
ꢐ
ꢑ
ꢏ
ꢒ
ꢑ
ꢓ
ꢒ
ꢔ
ꢇ
ꢕ
ꢄ
ꢖ
ꢗ
ꢘ
ꢕ
ꢊ
ꢂ
ꢏ
ꢙ
ꢔ
ꢕ
ꢇ
ꢂ
ꢑ
ꢚ
FEATURES
DESCRIPTION
D
D
D
D
D
D
D
D
D
D
16-Bit Resolution
The ADS1205 is a two-channel, high-performance,
delta-sigma (∆Σ) modulator with more than 98dB dynamic
range, operating from a single +5V supply. The differential
inputs are ideal for direct connection to transducers in an
industrial environment. With the appropriate digital filter
and modulator rate, the device can be used to achieve
16-bit analog-to-digital (A/D) conversion with no missing
codes. Effective resolution of 14 bits can be obtained with
a digital filter bandwidth of 40kHz at a modulator rate of
10MHz. The ADS1205 is designed for use in
high-resolution measurement applications including
current measurements, smart transmitters, industrial
process control, and resolvers. It is available in a QFN-24
(4x4) package.
14-Bit Linearity
2.5V Input Range at 2.5V
Internal Reference Voltage: 2%
Gain Error: 0.5%
Two Independent Delta-Sigma Modulators
Two Input Reference Buffers
On-Chip 20MHz Oscillator
Selectable Internal or External Clock
Operating Temperature Range:
−40°C to +85°C
QFN-24 (4x4) Package
D
AVDD
BVDD
APPLICATIONS
D
D
D
D
D
Motor Control
OUT A
OUT B
CH A+
2nd−Order
Current Measurement
Industrial Process Control
Instrumentation
Resolver
Output
Interface
Circuit
∆Σ
Modulator
−
CH A
CLKOUT
REFIN A
CH B+
2nd−Order
∆Σ
Modulator
−
CH B
Divider
REFIN B
CLKIN
Clock
Select
CLKSEL
Out EN
Reference
Voltage
2.5V
RC
Oscillator
20MHz
REFOUT
AGND
BGND
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
ꢝꢞ ꢐ ꢓꢟ ꢠ ꢀꢡ ꢐꢢ ꢓ ꢛꢀꢛ ꢆꢎ ꢣꢂ ꢑ ꢘꢕ ꢇꢆꢂꢎ ꢆꢚ ꢤꢙ ꢑ ꢑ ꢒꢎꢇ ꢕꢚ ꢂꢣ ꢥꢙꢦ ꢔꢆꢤ ꢕꢇꢆ ꢂꢎ ꢏꢕ ꢇꢒꢧ ꢝꢑ ꢂꢏꢙ ꢤꢇꢚ
ꢤ ꢂꢎ ꢣꢂꢑ ꢘ ꢇꢂ ꢚ ꢥꢒ ꢤ ꢆ ꢣꢆ ꢤ ꢕ ꢇꢆ ꢂꢎꢚ ꢥ ꢒꢑ ꢇꢨꢒ ꢇꢒ ꢑ ꢘꢚ ꢂꢣ ꢀꢒꢩ ꢕꢚ ꢡꢎꢚ ꢇꢑ ꢙꢘ ꢒꢎꢇ ꢚ ꢚꢇ ꢕꢎꢏ ꢕꢑ ꢏ ꢁ ꢕꢑ ꢑ ꢕ ꢎꢇꢪꢧ
ꢝꢑ ꢂ ꢏꢙꢤ ꢇ ꢆꢂ ꢎ ꢥꢑ ꢂ ꢤ ꢒ ꢚ ꢚ ꢆꢎ ꢗ ꢏꢂ ꢒ ꢚ ꢎꢂꢇ ꢎꢒ ꢤꢒ ꢚꢚ ꢕꢑ ꢆꢔ ꢪ ꢆꢎꢤ ꢔꢙꢏ ꢒ ꢇꢒ ꢚꢇꢆ ꢎꢗ ꢂꢣ ꢕꢔ ꢔ ꢥꢕ ꢑ ꢕꢘ ꢒꢇꢒ ꢑ ꢚꢧ
Copyright 2005, Texas Instruments Incorporated
www.ti.com
ꢛ
ꢓ
ꢖ
ꢃ
ꢍ
ꢉ
ꢜ
www.ti.com
SBAS312A − JANUARY 2005 − REVISED APRIL 2005
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate
precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to
damage because very small parametric changes could cause the device not to meet its published specifications.
Package/Ordering Information
For the most current package and ordering information, see the Package Option Addendum at the end of this document,
or see the TI web site at www.ti.com.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted
(1)
ADS1205
−0.3 to 6
−0.3 to 6
UNIT
V
Supply voltage, AGND to AV
Supply voltage, BGND to BV
DD
DD
V
Analog input voltage with respect to AGND
Reference input voltage with respect to AGND
Digital input voltage with respect to BGND
Ground voltage difference, AGND to BGND
AGND − 0.3 to AV
AGND − 0.3 to AV
+ 0.3
+ 0.3
+ 0.3
V
DD
DD
V
BGND − 0.3 to BV
V
DD
0.3
−0.3 to 6
10
V
Voltage differences, BV
DD
to AGND
V
Input current to any pin except supply
mA
Power dissipation
See Dissipation Rating table
−40 to +150
Operating virtual junction temperature range, T
°C
°C
°C
J
Operating free-air temperature range, T
−40 to +85
A
Storage temperature range, T
STG
−65 to +150
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and
functionaloperation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
DISSIPATION RATINGS
PACKAGE
T
≤ 25°C
DERATING FACTOR
(1)
T
= 70°C
T = 85°C
A
POWER RATING
A
A
POWER RATING
ABOVE T = 25°C
POWER RATING
A
QFN-24 (4x4)
2193mW
21.929mW/°C
1206mW
877.2mW
(1)
This is the inverse of the traditional junction-to-ambient thermal resistance (R
informational purposes only.
). Thermal resistances are not production tested and are for
qJA
RECOMMENDED OPERATING CONDITIONS
PARAMETER
MIN
4.5
2.7
4.5
0.5
NOM
MAX
5.5
UNIT
V
Supply voltage, AGND to AV
Supply voltage, BGND to BV
Reference input voltage
5
DD
Low-Voltage Levels
5V Logic Levels
3.6
V
DD
5
5.5
V
2.5
2.5
2.6
V
Operating common-mode signal
Analog inputs
−IN
V
+IN − (−IN)
0.8 × REFIN
V
(1)
External clock
16
20
24
MHz
°C
Operating junction temperature range, T
−40
105
J
(1)
With reduced accuracy, clock can go from 1MHz up to 33MHz; see Typical Characteristics.
2
ꢛ ꢓꢖ ꢃꢍ ꢉꢜ
www.ti.com
SBAS312A − JANUARY 2005 − REVISED APRIL 2005
ELECTRICAL CHARACTERISTICS
Over recommended operating free-air temperature range at −40°C to +85°C, AV
= 5V, BV = 3V, CH x+ = 0.5V to 4.5V, CH x− = 2.5V,
DD
DD
3
REFIN = REFOUT = internal +2.5V, CLKIN = 20MHz, and 16-bit Sinc filter with decimation by 256, unless otherwise noted.
ADS1205I
(1)
TYP
MIN
MAX
UNITS
PARAMETER
Resolution
TEST CONDITIONS
16
Bits
DC Accuracy
−1.4
3
LSB
(2)
Integral linearity error
INL
−0.002
0.005 % FSR
LSB
0.009 % FSR
6
Integral linearity match
Differential nonlinearity
(3)
DNL
1
3
2
8
LSB
mV
(4)
Input offset error
V
OS
−1.2
0.1
Input offset error match
Input offset error drift
mV
TCV
OS
1.1
µV/°C
(4)
Gain error
G
Referenced to V
−0.01
0.09
1.3
0.5 % FSR
0.5 % FSR
ppm/°C
ERR
REF
Gain error match
TCG
ERR
Gain error drift
PSRR
Power-supply rejection ratio
4.75V < AV
DD
< 5.25V
78
dB
Analog Input
FSR
Full-scale differential range
Specified differential range
Maximum operating input range
Input capacitance
(CH x+) − (CH x−); CH x− = 2.5V
(CH x+) − (CH x−); CH x− = 2.5V
2.5
2
V
V
(3)
0
AV
V
DD
Common-mode
CLK turned off
3
pF
nA
kΩ
pF
dB
dB
MHz
Input leakage current
1
Differential input resistance
Differential input capacitance
100
2.5
108
117
50
At DC
CMRR
BW
Common-mode rejection ratio
Bandwidth
V
IN
=
1.25V at 40kHz
PP
FS sine wave, −3dB
Sampling Dynamics
Internal clock frequency
CLKSEL = 1
CLKSEL = 0
8
1
9.8
20
12
24
MHz
MHz
(5)
CLKIN
AC Accuracy
THD
External clock frequency
Total harmonic distortion
V
IN
V
IN
V
IN
V
IN
V
IN
=
=
=
=
=
2V
PP
2V
PP
2V
PP
2V
PP
2V
PP
at 5kHz
at 5kHz
at 5kHz
at 5kHz
at 50kHz
−96.6
98
−88
dB
dB
dB
dB
dB
Bits
SFDR
Spurious-free dynamic range
Signal-to-noise ratio
92
86
85
SNR
88.9
88.2
100
SINAD
Signal-to-noise + distortion
(3)
Channel-to-channel isolation
Effective number of bits
ENOB
(1)
14
14.5
All typical values are at T = +25°C.
A
(2)
Integral nonlinearity is defined as the maximum deviation of the line through the end points of the specified input range of the transfer curve
for CH x+ = −2V to +2V at 2.5V, expressed either as the number of LSBs or as a percent of measured input range (4V).
Ensured by design.
(3)
(4)
(5)
(6)
(7)
Maximum values, including temperature drift, are ensured over the full specified temperature range.
With reduced accuracy, the clock frequency can go from 1MHz to 33MHz.
Applicable for 5.0V nominal supply: BV
Applicable for 3.0V nominal supply: BV
(min) = 4.5V and BV
(min) = 2.7V and BV
(max) = 5.5V.
(max) = 3.6V.
DD
DD
DD
DD
3
ꢛꢓ ꢖꢃ ꢍ ꢉ ꢜ
www.ti.com
SBAS312A − JANUARY 2005 − REVISED APRIL 2005
ELECTRICAL CHARACTERISTICS (continued)
Over recommended operating free-air temperature range at −40°C to +85°C, AV
= 5V, BV
DD
= 3V, CH x+ = 0.5V to 4.5V, CH x− = 2.5V,
DD
3
REFIN = REFOUT = internal +2.5V, CLKIN = 20MHz, and 16-bit Sinc filter with decimation by 256, unless otherwise noted.
ADS1205I
(1)
TYP
MIN
MAX
UNITS
PARAMETER
TEST CONDITIONS
−40°C to +85°C
f = 0.1Hz to 10Hz, C = 10µF
Voltage Reference Output
V
Reference voltage output
2.450
2.5
20
2.550
V
ppm/°C
µVrms
µVrms
dB
REFOUT
dV
/dT Output voltage temperature drift
REFOUT
10
L
Output voltage noise
f =10Hz to 10kHz, C = 10µF
12
L
PSRR
Power-supply rejection ratio
Output current
60
I
I
10
µA
OUT
SC
Short-circuit current
Turn-on settling time
0.5
100
mA
to 0.1% at C = 0
µs
L
Voltage Reference Input
V
IN
Reference voltage input
Reference input resistance
Reference input capacitance
Reference input current
0.5
2.5
100
5
2.6
1
V
MΩ
pF
µA
(6)
Digital Inputs
Logic family
CMOS with Schmitt Trigger
0.7×BV BV +0.3
V
IH
V
IL
High-level input voltage
Low-level input voltage
Input current
V
V
DD DD
−0.3
0.3×BV
DD
50
I
V = BV
I DD
or GND
nA
pF
IN
C
Input capacitance
5
I
(6)
Digital Outputs
Logic family
CMOS
V
V
High-level output voltage
Low-level output voltage
Output capacitance
Load capacitance
Data format
BV
BV
= 4.5V, I
= 4.5V, I
= −100µA
= +100µA
4.44
V
V
OH
OL
DD
DD
OH
OL
0.5
30
C
5
pF
pF
O
L
C
Bit Stream
(1)
(2)
All typical values are at T = +25°C.
A
Integral nonlinearity is defined as the maximum deviation of the line through the end points of the specified input range of the transfer curve
for CH x+ = −2V to +2V at 2.5V, expressed either as the number of LSBs or as a percent of measured input range (4V).
Ensured by design.
Maximum values, including temperature drift, are ensured over the full specified temperature range.
With reduced accuracy, the clock frequency can go from 1MHz to 33MHz.
(3)
(4)
(5)
(6)
(7)
Applicable for 5.0V nominal supply: BV
Applicable for 3.0V nominal supply: BV
(min) = 4.5V and BV
(min) = 2.7V and BV
(max) = 5.5V.
(max) = 3.6V.
DD
DD
DD
DD
4
ꢛ ꢓꢖ ꢃꢍ ꢉꢜ
www.ti.com
SBAS312A − JANUARY 2005 − REVISED APRIL 2005
ELECTRICAL CHARACTERISTICS (continued)
Over recommended operating free-air temperature range at −40°C to +85°C, AV
= 5V, BV = 3V, CH x+ = 0.5V to 4.5V, CH x− = 2.5V,
DD
DD
3
REFIN = REFOUT = internal +2.5V, CLKIN = 20MHz, and 16-bit Sinc filter with decimation by 256, unless otherwise noted.
ADS1205I
(1)
TYP
MIN
MAX
UNITS
PARAMETER
Digital Inputs
TEST CONDITIONS
(7)
Logic family
LVCMOS
V
V
High-level input voltage
Low-level input voltage
Input current
BV
BV
= 3.6V
2
BV +0.3
DD
V
V
IH
IL
DD
DD
= 2.7V
or GND
−0.3
0.8
I
IN
V = BV
I DD
50
nA
pF
C
Input capacitance
5
I
(7)
Digital Outputs
Logic family
LVCMOS
V
V
High-level output voltage
Low-level output voltage
Output capacitance
Load capacitance
Data format
BV
BV
= 2.7V, I
= 2.7V, I
= −100µA
= +100µA
BV −0.2
DD
V
V
OH
DD
DD
OH
OL
0.2
30
OL
C
C
5
pF
pF
O
L
Bit Stream
Power Supply
AV
Analog supply voltage
4.5
2.7
4.5
5.5
3.6
5.5
16
V
DD
Low-voltage levels
5V logic levels
CLKSEL = 1
V
BV
DD
Buffer I/O supply voltage
V
11.8
11.4
mA
mA
mA
mA
mW
mW
AI
DD
Analog operating supply current
Buffer I/O operating supply current
Power dissipation
CLKSEL = 0
15.5
2
BV
BV
= 3V, CLKOUT = 10MHz
= 5V, CLKOUT = 10MHz
DD
BI
DD
2
DD
CLKSEL = 0
CLKSEL = 1
57
59
77.5
80
(1)
(2)
All typical values are at T = +25°C.
A
Integral nonlinearity is defined as the maximum deviation of the line through the end points of the specified input range of the transfer curve
for CH x+ = −2V to +2V at 2.5V, expressed either as the number of LSBs or as a percent of measured input range (4V).
Ensured by design.
Maximum values, including temperature drift, are ensured over the full specified temperature range.
With reduced accuracy, the clock frequency can go from 1MHz to 33MHz.
(3)
(4)
(5)
(6)
(7)
Applicable for 5.0V nominal supply: BV
Applicable for 3.0V nominal supply: BV
(min) = 4.5V and BV
(min) = 2.7V and BV
(max) = 5.5V.
(max) = 3.6V.
DD
DD
DD
DD
EQUIVALENT INPUT CIRCUIT
BVDD
AVDD
C(SAMPLE)
1pF
RON
Ω
650
AIN
DIN
Diode Turn−On Voltage: 0.35V
AGND
Equivalent Analog Input Circuit
BGND
Equivalent Digital Input Circuit
5
ꢛꢓ ꢖꢃ ꢍ ꢉ ꢜ
www.ti.com
SBAS312A − JANUARY 2005 − REVISED APRIL 2005
PIN ASSIGNMENTS
RGE PACKAGE
QFN−24
(TOP VIEW)
1
2
3
4
5
6
18 REFIN A
17
16 AVDD
REFIN B
AGND
AVDD
AGND
ADS1205
15
14
13
AVDD
AVDD
REFOUT
AGND
AGND
CLKSEL
Terminal Functions
TERMINAL
NAME
NO.
I/O
DESCRIPTION
REFIN B
AGND
1
I
Reference voltage input of channel B: pin for external reference voltage
Analog ground
2, 5, 13, 17
AV
DD
3, 4, 15, 16
Analog power supply; nominal 5V
CLKSEL
CLKIN
6
7
I
I
Clock select between internal clock (CLKSEL = 1) or external clock (CLKSEL = 0)
External clock input
BV
DD
8
Digital interface power supply; from 2.7V to 5.5V
Interface ground
BGND
9
CLKOUT
OUT B
10
11
O
O
System clock output
Bit stream from channel B modulator
OUT A
12
14
18
O
O
I
Bit stream from channel A modulator
REFOUT
REFIN A
Reference voltage output: output pin of the internal reference source; nominal 2.5V
Reference voltage input of channel A: pin for external reference voltage
NC
19, 24
20
No connection; this pin is left unconnected
Analog input of channel A: noninverting input
Analog input of channel A: inverting input
Analog input of channel B: inverting input
Analog input of channel B: noninverting input
CH A+
CH A−
CH B−
CH B+
I
I
I
I
21
22
23
6
ꢛ ꢓꢖ ꢃꢍ ꢉꢜ
www.ti.com
SBAS312A − JANUARY 2005 − REVISED APRIL 2005
PARAMETER MEASUREMENT INFORMATION
tC1
CLKIN
tW1
tD1
tD2
tC2
CLKOUT
OUT x
tW2
tD3
tD4
Figure 1. ADS1205 Timing Diagram
(1)
TIMING REQUIREMENTS
over recommended operating free-air temperature range at −40°C to +85°C, AV
= 5V, and BV
DD
= 2.7 to 5V, unless otherwise noted.
MIN MAX UNIT
DD
PARAMETER
(2)
t
t
t
CLKIN period: (CLKSEL = 0)
41.6
1000
− 10
125
ns
ns
ns
ns
ns
ns
ns
ns
ns
C1
W1
C2
CLKIN high time: (CLKSEL = 0)
10
83
t
C1
CLKOUT period using internal oscillator (CLKSEL = 1)
CLKOUT period using external clock (CLKSEL = 0)
CLKOUT high time
2 × t
C1
t
t
t
t
t
(t /2) − 5 (t /2) + 5
C2 C2
W2
D1
D2
D3
D4
CLKOUT rising edge delay after CLKIN rising edge: (CLKOUT = 0)
CLKOUT falling edge delay after CLKIN rising edge: (CLKOUT = 0)
Data valid delay after rising edge of CLKOUT (CLKSEL = 1)
Data valid delay after rising edge of CLKOUT (CLKSEL = 0)
0
0
10
10
(t /4) − 8 (t /4) + 8
C2 C2
t
− 3
t
+ 7
W1
W1
(1)
(2)
All input signals are specified with t = t = 5ns (10% to 90% of BV ) and timed from a voltage level of (V + V )/2. See Figure 1.
DD IL IH
R
F
With reduced accuracy, the minimum clock period can go down to 30ns.
7
ꢛꢓ ꢖꢃ ꢍ ꢉ ꢜ
www.ti.com
SBAS312A − JANUARY 2005 − REVISED APRIL 2005
TYPICAL CHARACTERISTICS
3
AV
= 5V, BV
= 3V, CH x+ = 0.5V to 4.5V, CH x− = 2.5V, REFIN = REFOUT = internal +2.5V, CLKIN = 20MHz, and 16-bit Sinc filter with
decimation by 256, unless otherwise noted.
DD
DD
INTEGRAL NONLINEARITY vs INPUT SIGNAL
INTEGRAL NONLINEARITY vs INPUT SIGNAL
(CLKIN = 32MHz)
(CLKIN = 20MHz)
1.7
1.2
0.00259
0.00183
0.00107
0.00031
−0.00046
−0.00122
−0.00198
−0.00275
1.7
1.2
0.00259
0.00183
0.00107
0.00031
−0.00046
−0.00122
−0.00198
−0.00275
0.70
0.20
−0.3
−0.8
−1.3
−1.8
0.70
0.20
−0.3
−0.8
−1.3
−1.8
+25_C
+85_C
+25_C
+85_C
−40_C
−40_C
−2.5 −2.0 −1.5 −1.0 −0.5
0
0.5 1.0 1.5 2.0 2.5
−2.5 −2.0 −1.5 −1.0 −0.5
0
0.5 1.0 1.5 2.0 2.5
Differential Input Voltage (V)
Differential Input Voltage (V)
Figure 2
Figure 3
INTEGRAL LINEARITY MATCH OF CHANNELS
vs INPUT SIGNAL
INTEGRAL LINEARITY vs TEMPERATURE
0
0
0.4
0.3
0.2
0.1
0
0.00061
0.00046
0.00031
0.00015
0
−0.2
−0.00031
CLKIN = 20MHz
CLKIN = 32MHz
−
−
0.00061
0.4
−0.6
−0.8
−1.0
−1.2
−0.00092
−0.00122
−0.00153
−0.00183
−0.1
−0.2
−0.00015
−0.00031
CLKIN = 32MHz
0.3
0.00046
−
−
−
1.4
−
0.00214
CLKIN = 20MHz
−0.4
−2.5 −2.0 −1.5 −1.0 −0.5
−0.00061
−1.6
−40
−0.00244
100
0
0.5 1.0 1.5 2.0 2.5
−20
0
20
40
60
80
Differential Input Voltage (V)
Temperature (_C)
Figure 4
Figure 5
OFFSET vs TEMPERATURE
OFFSET MATCH vs TEMPERATURE
−
1.0
0.15
0.14
0.13
0.12
0.11
0.10
0.09
0.08
0.07
0.06
0.05
−
−
−
−
−
−
1.05
1.10
1.15
1.20
1.25
1.30
CLKIN = 32MHz
CLKIN = 20MHz
CLKIN = 32MHz
CLKIN = 20MHz
−
−
−
−
20
40
20
0
20
40
60
80
100
40
0
20
40
60
80
100
_
_
Temperature ( C)
Temperature ( C)
Figure 6
Figure 7
8
ꢛ ꢓꢖ ꢃꢍ ꢉꢜ
www.ti.com
SBAS312A − JANUARY 2005 − REVISED APRIL 2005
TYPICAL CHARACTERISTICS (continued)
3
AV
= 5V, BV
= 3V, CH x+ = 0.5V to 4.5V, CH x− = 2.5V, REFIN = REFOUT = internal +2.5V, CLKIN = 20MHz, and 16-bit Sinc filter with
decimation by 256, unless otherwise noted.
DD
DD
OFFSET vs POWER SUPPLY
REFERENCE VOLTAGE vs TEMPERATURE
−
−
−
−
−
0.8
1.0
1.2
1.4
1.6
2.510
2.508
2.506
2.504
2.502
2.500
2.498
2.496
2.494
2.492
2.490
CLKIN = 32MHz
CLKIN = 20MHz
−
−
20
4.50
4.75
5.00
5.25
5.50
40
0
20
40
60
80
100
_
Power Supply (V)
Temperature ( C)
Figure 8
Figure 9
GAIN vs TEMPERATURE
GAIN MATCH vs TEMPERATURE
0.125
0.120
0.115
0.110
0.105
0.100
0.095
0.090
0.085
0.080
0.075
0.25
0.20
0.15
0.10
0.05
0
CLKIN = 20MHz
CLKIN = 20MHz
CLKIN = 32MHz
−
0.05
0.10
0.15
0.20
0.25
CLKIN = 32MHz
−
−
−
−
−
−
−
−
20
40
20
0
20
40
60
80
100
40
0
20
40
60
80
100
_
_
Temperature ( C)
Temperature ( C)
Figure 10
Figure 11
SIGNAL−TO−NOISE RATIO
vs TEMPERATURE
SIGNAL−TO−NOISE + DISTORTION
vs TEMPERATURE
89.0
88.9
88.8
88.7
88.6
88.5
88.4
88.3
88.2
88.1
88.0
89.2
89.0
88.8
88.6
88.4
88.2
88.0
87.8
87.6
CLKIN = 20MHz
CLKIN = 32MHz
CLKIN = 20MHz
CLKIN = 32MHz
4VPP
5kHz
4VPP
5kHz
−
−
−
−
20
40
20
0
20
40
60
80
100
40
0
20
40
60
80
100
_
_
Temperature ( C)
Temperature ( C)
Figure 12
Figure 13
9
ꢛꢓ ꢖꢃ ꢍ ꢉ ꢜ
www.ti.com
SBAS312A − JANUARY 2005 − REVISED APRIL 2005
TYPICAL CHARACTERISTICS (continued)
3
AV
= 5V, BV
= 3V, CH x+ = 0.5V to 4.5V, CH x− = 2.5V, REFIN = REFOUT = internal +2.5V, CLKIN = 20MHz, and 16-bit Sinc filter with
decimation by 256, unless otherwise noted.
DD
DD
SPURIOUS FREE DYNAMIC RANGE AND
TOTAL HARMONIC DISTORTION vs TEMPERATURE
(CLKIN = 20MHz)
SPURIOUS FREE DYNAMIC RANGE AND
TOTAL HARMONIC DISTORTION vs TEMPERATURE
(CLKIN = 32MHz)
105
103
101
99
−105
−103
105
103
101
99
−105
−103
−101
−99
SFDR
THD
101
−
−
99
SFDR
THD
97
−97
−95
97
−97
95
95
95
−
93
−
91
−
93
93
−
−
93
91
91
91
89
−89
−87
89
−89
−87
−85
4VPP
5kHz
4VPP
5kHz
87
87
85
−40
85
−
100
85
−40
−20
0
20
40
60
80
−20
0
20
40
60
80
100
Temperature ( C)
_
Temperature (_C)
Figure 14
Figure 15
SIGNAL−TO−NOISE AND DISTORTION AND
SIGNAL−TO−NOISE AND DISTORTION AND
SIGNAL−TO−NOISE RATIO vs INPUT FREQUENCY
(CLKIN = 20MHz)
SIGNAL−TO−NOISE RATIO vs INPUT FREQUENCY
(CLKIN = 32MHz)
100
100
98
96
94
92
90
88
86
84
82
80
95
90
85
80
SNR
SNR
SINAD
SINAD
OSR = 256
Sinc3 Filter
OSR = 256
Sinc3 Filter
100
1k
100k
100
1k
10k
100k
Input Frequency (kHz)
Figure 16
Input Frequency (kHz)
Figure 17
SPURIOUS FREE DYNAMIC RANGE AND
SPURIOUS FREE DYNAMIC RANGE AND
TOTAL HARMONIC DISTORTION vs INPUT FREQUENCY
(CLKIN = 20MHz)
TOTAL HARMONIC DISTORTION vs INPUT FREQUENCY
(CLKIN = 32MHz)
120
110
100
90
−120
−110
−100
−90
120
−120
−110
−100
110
100
90
SFDR
THD
SFDR
THD
−
90
OSR = 256
Sinc3 Filter
OSR = 256
Sinc3 Filter
80
−80
100k
80
−80
100k
100
1k
10k
100
1k
10k
Input Frequency (Hz)
Input Frequency (Hz)
Figure 18
Figure 19
10
ꢛ ꢓꢖ ꢃꢍ ꢉꢜ
www.ti.com
SBAS312A − JANUARY 2005 − REVISED APRIL 2005
TYPICAL CHARACTERISTICS (continued)
3
AV
= 5V, BV
= 3V, CH x+ = 0.5V to 4.5V, CH x− = 2.5V, REFIN = REFOUT = internal +2.5V, CLKIN = 20MHz, and 16-bit Sinc filter with
decimation by 256, unless otherwise noted.
DD
DD
FREQUENCY SPECTRUM
(4096 point FFT fIN = 1kHz, 4VPP
FREQUENCY SPECTRUM
(4096 point FFT fIN = 5kHz, 4VPP)
)
0
20
40
60
80
0
20
40
60
80
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
100
120
140
160
100
120
140
160
0
2
4
6
8
10
12
14
16
18 19
0
2
4
6
8
10
12
14
16
18 19
Frequency (kHz)
Frequency (kHz)
Figure 20
Figure 21
EFFECTIVE NUMBER OF BITS
vs DECIMATION RATIO
POWER−SUPPLY CURRENT
vs TEMPERATURE
16
15
14
13
12
11
10
9
16
14
12
10
8
98
86
74
62
50
38
26
14
Sinc3 Filter
Sinc2 Filter
CLKSEL = 0, CLKIN = 32MHz
CLKSEL = 0, CLKIN = 20MHz
6
CLKSEL = 1
4
8
2
−
−
20
10
100
1k
40
0
20
40
60
80
100
_
Decimation Ratio (OSR)
Temperature ( C)
Figure 22
Figure 23
COMMON−MODE REJECTION RATIO
vs FREQUENCY
POWER−SUPPLY REJECTION RATIO
vs FREQUENCY
130
120
110
100
90
100
90
80
70
60
100
1k
10k
100k
1M
100
1k
10k
Input Frequency (kHz)
Frequency of Power Supply (kHz)
Figure 24
Figure 25
11
ꢛꢓ ꢖꢃ ꢍ ꢉ ꢜ
www.ti.com
SBAS312A − JANUARY 2005 − REVISED APRIL 2005
TYPICAL CHARACTERISTICS (continued)
3
AV
= 5V, BV
= 3V, CH x+ = 0.5V to 4.5V, CH x− = 2.5V, REFIN = REFOUT = internal +2.5V, CLKIN = 20MHz, and 16-bit Sinc filter with
decimation by 256, unless otherwise noted.
DD
DD
CLOCK FREQUENCY vs TEMPERATURE
CLOCK FREQUENCY vs POWER SUPPLY
11.0
10.8
10.6
10.4
10.2
10.0
9.8
10.2
10.1
10.0
9.9
9.8
9.7
9.6
9.6
9.5
9.4
9.4
9.2
9.3
9.0
9.2
−
−
20
40
0
20
40
60
80
100
4.5
4.75
5
5.25
5.5
_
Temperature ( C)
Power Supply (V)
Figure 26
Figure 27
12
ꢛ ꢓꢖ ꢃꢍ ꢉꢜ
www.ti.com
SBAS312A − JANUARY 2005 − REVISED APRIL 2005
An application-specific integrated circuit (ASIC) or
field-programmable gate array (FPGA) could be used to
implement the digital filter. Figure 28 and Figure 29 show
typical application circuits with the ADS1205 connected to
an FPGA or ASIC.
GENERAL DESCRIPTION
The ADS1205 is a two-channel, 2nd-order, CMOS device
with two delta-sigma modulators, designed for medium- to
high-resolution A/D signal conversions from DC to 39kHz
(filter response −3dB) if an oversampling ratio (OSR) of 64
is chosen. The output of the converter (OUTX) provides a
stream of digital ones and zeros. The time average of this
serial output is proportional to the analog input voltage.
The overall performance (that is, speed and accuracy)
depends on the selection of an appropriate OSR and filter
type. A higher OSR produces greater output accuracy
while operating at a lower refresh rate. Alternatively, a
lower OSR produces lower output accuracy, but operates
at a higher refresh rate. This system allows flexibility with
the digital filter design and is capable of A/D conversion
results that have a dynamic range exceeding 98dB with an
OSR = 256.
The modulator shifts the quantization noise to high
frequencies. A low-pass digital filter should be used at the
output of the delta-sigma modulator. The filter serves two
functions. First, it filters out high-frequency noise. Second,
the filter converts the 1-bit data stream at a high sampling
rate into a higher-bit data word at a lower rate (decimation).
Ω
2 k
AVDD
BVDD
+5V
5kΩ
5V
Ω
27
OUT A
OUT B
µ
0.1 F
CH A+
OPA2350
2nd−Order
Output
Interface
Circuit
0.1nF
∆Σ
Modulator
CH A−
Ω
Ω
2k
5k
FPGA
or
ASIC
REFIN A
CLKOUT
+3V
Ω
2k
CH B+
2nd−Order
BVDD
∆Σ
Modulator
−
CH B
µ
F
0.1
+5V
BGND
Ω
5k
5V
27Ω
REFIN B
µ
0.1 F
OPA2350
Divider
0.1nF
5kΩ
2kΩ
+3V
CLKIN
Clock
Select
CLKSEL
+5V
AVDD
AVDD
AVDD
AVDD
+5V
µ
F
Out EN
0.1
0.1µF
RC
Oscillator
20MHz
+5V
Reference
Voltage
2.5V
+5V
µ
0.1
0.1µF
F
REFOUT
AGND AGND AGND AGND
µ
0.1
F
+5V
OPA336
µ
0.1
F
Figure 28. Single-Ended Connection Diagram for the ADS1205 Delta-Sigma Modulator
13
ꢛꢓ ꢖꢃ ꢍ ꢉ ꢜ
www.ti.com
SBAS312A − JANUARY 2005 − REVISED APRIL 2005
AVDD
BVDD
+5V
Ω
Ω
27
OUT A
OUT B
CH A+
OPA4354
R1
2nd−Order
Output
Interface
Circuit
IN+
∆Σ
Modulator
CH A−
0.1nF
R2
FPGA
or
ASIC
REFIN A
CLKOUT
+5V
+3V
CH B+
2nd−Order
BVDD
27
∆Σ
Modulator
OPA4354
−
CH B
µ
F
0.1
R1
−
IN
BGND
REFIN B
R2
Divider
+5V
+3V
Ω
Ω
27
CLKIN
Clock
Select
OPA4354
R1
CLKSEL
IN+
0.1nF
+5V
R2
AVDD
AVDD
AVDD
AVDD
+5V
0.1
µ
Out EN
F
+5V
RC
Oscillator
20MHz
+5V
0.1µF
27
OPA4354
R1
Reference
Voltage
2.5V
+5V
µ
0.1
0.1µF
F
−
IN
REFOUT
R2
AGND AGND AGND AGND
0.1µF
+5V
OPA336
µ
0.1 F
Figure 29. Differential Connection Diagram for the ADS1205 Delta-Sigma Modulator
14
ꢛ ꢓꢖ ꢃꢍ ꢉꢜ
www.ti.com
SBAS312A − JANUARY 2005 − REVISED APRIL 2005
restrictions on the analog input signals, CH x+ and CH x−.
If the input voltage exceeds the range (GND – 0.3V) to
(VDD + 0.3V), the input current must be limited to 10mA
because the input protection diodes on the front end of the
converter will begin to turn on. In addition, the linearity and
the noise performance of the device are ensured only
when the differential analog voltage resides within 2V
(with VREF as a midpoint); however, the FSR input voltage
is 2.5V.
THEORY OF OPERATION
The differential analog input of the ADS1205 is
implemented with a switched-capacitor circuit. This circuit
implements a 2nd-order modulator stage, which digitizes
the analog input signal into a 1-bit output stream. The clock
source can be internal as well as external. Different
frequencies for this clock allow for a variety of solutions
and signal bandwidths. Every analog input signal is
continuously sampled by the modulator and compared to
a reference voltage that is applied to the REFINx pin. A
digital stream, which accurately represents the analog
input voltage over time, appears at the output of the
corresponding converter.
Modulator
The ADS1205 can be operated in two modes. When
CKLSEL = 1, the two modulators operate using the internal
clock, which is fixed at 20MHz. When CKLSEL = 0, the
modulators operate using an external clock. In both modes,
the clock is divided by two internally and functions as the
modulator clock. The frequency of the external clock can vary
from 1MHz to 33MHz to adjust for the clock requirements of
the application.
ANALOG INPUT STAGE
Analog Input
The topology of the analog inputs of ADS1205 is based on
a fully differential switched-capacitor architecture. This
input stage provides the mechanism to achieve low
system noise, high common-mode rejection (108dB), and
excellent power-supply rejection.
The modulator topology is fundamentally a 2nd-order,
switched-capacitor, delta-sigma modulator, such as the one
conceptualized in Figure 31. The analog input voltage and
the output of the 1-bit digital-to-analog converter (DAC) are
differentiated, providing analog voltages at X2 and X3. The
voltages at X2 and X3 are presented to their individual
integrators. The output of these integrators progresses in a
negative or positive direction. When the value of the signal
at X4 equals the comparator reference voltage, the output of
the comparator switches from negative to positive, or positive
to negative, depending on its original state. When the output
value of the comparator switches from high to low or vice
versa, the 1-bit DAC responds on the next clock pulse by
changing its analog output voltage at X6, causing the
integrators to progress in the opposite direction. The
feedback of the modulator to the front end of the integrators
forces the value of the integrator output to track the average
of the input.
The input impedance of the analog input is dependent on
the modulator clock frequency (fCLK), which is also the
sampling frequency of the modulator. Figure 30 shows the
basic input structure of one channel of the ADS1205. The
relationship between the input impedance of the ADS1205
and the modulator clock frequency is:
100kW
MODń10MHz
ZIN
+
f
(1)
The input impedance becomes a consideration in designs
where the source impedance of the input signal is high.
This high impedance may cause degradation in gain,
linearity, and THD. The importance of this effect depends
on the desired system performance. There are two
Ω
650
High
Impedance
AIN+
Ω
> 1G
1.2pF
1.2pF
0.4pF
0.4pF
VCM
Switching Frequency = CLK
Ω
650
High
Impedance
−
AIN
Ω
> 1G
Figure 30. Input Impedance of the ADS1205
15
ꢛꢓ ꢖꢃ ꢍ ꢉ ꢜ
www.ti.com
SBAS312A − JANUARY 2005 − REVISED APRIL 2005
fCLK
X2
X3
X4
X(t)
Integrator 1
Integrator 2
DATA
fS
VREF
Comparator
X6
D/A Converter
Figure 31. Block Diagram of the 2nd-Order Modulator
and an ASIC or FPGA (each with an implemented filter),
the two standard signals per modulator (CLKOUT and
OUTx) are provided from the modulator. The output clock
signal is equal for both modulators. If CLKSEL = 1, CLKIN
must always be set either high or low.
DIGITAL OUTPUT
A differential input signal of 0V will ideally produce a
stream of ones and zeros that are high 50% of the time and
low 50% of the time. A differential input of +2V produces
a stream of ones and zeros that are high 80% of the time.
A differential input of –2V produces a stream of ones and
zeros that are high 20% of the time. The input voltage
versus the output modulator signal is shown in Figure 32.
MODES OF OPERATION
The system clock of the ADS1205 is 20MHz by default.
The system clock can be provided either from the internal
20MHz RC oscillator or from an external clock source. For
this purpose, the CLKIN pin is provided; it is controlled by
the mode setting, CLKSEL.
DIGITAL INTERFACE
INTRODUCTION
The analog signal connected to the input of the
delta-sigma modulator is converted using the clock signal
applied to the modulator. The result of the conversion, or
modulation, is generated and sent to the OUTx pin from the
delta-sigma modulator. In most applications where a direct
connection is realized between the delta-sigma modulator
The system clock is divided by two for the modulator clock.
Therefore, the default clock frequency of the modulator is
10MHz. With a possible external clock range of 1MHz to
33MHz, the modulator operates between 500kHz and
16.5MHz.
Modulator Output
+FS (Analog Input)
−
FS (Analog Input)
Analog Input
Figure 32. Analog Input vs Modulator Output of the ADS1205
16
ꢛ ꢓꢖ ꢃꢍ ꢉꢜ
www.ti.com
SBAS312A − JANUARY 2005 − REVISED APRIL 2005
FILTER USAGE
0
10
20
30
40
50
60
70
80
OSR = 32
fDATA = 10MHz/32 = 312.5kHz
The modulator generates only a bitstream, which does
not output a digital word like an A/D converter. In order
to output a digital word equivalent to the analog input
voltage, the bitstream must be processed by a digital
filter.
−
−
−
−
−
−
−
−
−
3dB: 81.9kHz
A very simple filter, built with minimal effort and
hardware, is the Sinc filter:
3
3
1 * z−OSR
H(z) + ǒ 1 * z−1
Ǔ
(2)
0
200
400
600
800 1000 1200 1400 1600
This filter provides the best output performance at the
lowest hardware size (for example, a count of digital
gates). For oversampling ratios in the range of 16 to
256, this is a good choice. All the characterizations in
Frequency (kHz)
3
Figure 33. Frequency Response of Sinc Filter
3
the data sheet are also done using a Sinc filter with an
oversampling ratio of OSR = 256 and an output word
length of 16 bits.
30k
OSR = 32
FSR = 32768
ENOB = 9.9 Bits
3
In a Sinc filter response (shown in Figure 33 and
25k
Figure 34), the location of the first notch occurs at the
frequency of output data rate f
Settling Time =
20k
×
µ
1/fDATA = 9.6 s
3
= f
/OSR. The
DATA
CLK
–3dB point is located at half the Nyquist frequency or
/4. For some applications, it may be necessary to
use another filter type for better frequency response.
15k
10k
5k
f
DATA
This performance can be improved, for example, by a
cascaded filter structure. The first decimation stage can
3
be a Sinc filter with a low OSR and the second stage
0
a high-order filter.
0
5
10
15
20
25
30
35
40
Number of Output Clocks
For more information, see application note SBAA094,
Combining the ADS1202 with an FPGA Digital Filter for
Current Measurement in Motor Control Applications,
available for download at www.ti.com.
3
Figure 34. Pulse Response of Sinc Filter
(f = 10MHz)
MOD
17
ꢛꢓ ꢖꢃ ꢍ ꢉ ꢜ
www.ti.com
SBAS312A − JANUARY 2005 − REVISED APRIL 2005
3
The effective number of bits (ENOB) can be used to
compare the performance of ADCs and delta-sigma
modulators. Figure 35 shows the ENOB of the
ADS1205 with different filter types. In this data sheet,
the ENOB is calculated from the SNR:
filter types other than Sinc might be a better choice. A
2
simple example is a Sinc filter. The Sincfast is a
2
modified Sinc filter:
2
1 * z−OSR
ǒ
−2 OSRǓ
H(z) + ǒ 1 * z−1
Ǔ
1 ) z
(4)
SNR = 1.76dB + 6.02dB × ENOB
(3)
Figure 36 compares the settling time of different filter
types operating with a 10MHz modulator clock.
16
Sinc3
14
12
10
8
10
Sinc3
9
8
Sinc2
Sincfast
7
Sinc2
6
6
Sinc
Sincfast
5
4
Sinc
4
2
3
2
1
0
0
1
10
100
1000
OSR
0
2
4
6
8
10
Figure 35. Measured ENOB vs OSR
µ
Settling Time ( s)
In motor control applications, a very fast response time
for overcurrent detection is required. There is a
constraint between 1µs and 5µs with 3 bits to 7 bits
resolution. The time for full settling is dependent on the
Figure 36. Measured ENOB vs Settling Time
3
filter order. Therefore, the full settling of the Sinc filter
For more information, see application note SBAA094,
Combining the ADS1202 with an FPGA Digital Filter for
Current Measurement in Motor Control Applications,
available for download at www.ti.com.
2
needs three data clocks and the Sinc filter needs two
data clocks. The data clock is equal to the modulator
clock divided by the OSR. For overcurrent protection,
18
ꢛ ꢓꢖ ꢃꢍ ꢉꢜ
www.ti.com
SBAS312A − JANUARY 2005 − REVISED APRIL 2005
For multiple converters, connect the two ground planes as
close as possible to one central location for all of the
converters. In some cases, experimentation may be
required to find the best point to connect the two planes
together.
LAYOUT CONSIDERATIONS
POWER SUPPLIES
An applied external digital filter rejects high-frequency
noise. PSRR and CMRR improve at higher frequencies
because the digital filter suppresses high-frequency noise.
However, the suppression of the filter is not infinite, so
high-frequency noise still influences the conversion result.
DECOUPLING
Good decoupling practices must be used for the ADS1205
and for all components in the design. All decoupling
capacitors, specifically the 0.1µF ceramic capacitors,
must be placed as close as possible to the pin being
decoupled. A 1µF and 10µF capacitor, in parallel with the
0.1µF ceramic capacitor, can be used to decouple AVDD
to AGND as well as BVDD to BGND. At least one 0.1µF
ceramic capacitor must be used to decouple every AVDD
to AGND and BVDD to BGND, as well as for the digital
supply on each digital component.
Inputs to the ADS1205, such as CH x+, CH x−, and CLKIN,
should not be present before the power supply is on.
Violating this condition could cause latch-up. If these
signals are present before the supply is on, series resistors
should be used to limit the input current to a maximum of
10mA. Experimentation may be the best way to determine
the appropriate connection between the ADS1205 and
different power supplies.
The digital supply sets the I/O voltage for the interface and
can be set within a range of 2.7V to 5.5V.
GROUNDING
Analog and digital sections of the design must be carefully
and cleanly partitioned. Each section should have its own
ground plane with no overlap between them. Do not join
the ground planes; instead, connect the two with a
moderate signal trace underneath the converter. However,
for different applications with DSPs and switching power
supplies, this process might be different.
In cases where both the analog and digital I/O supplies
share the same supply source, an RC filter of 10Ω and
0.1µF can be used to help reduce the noise in the analog
supply.
19
PACKAGE OPTION ADDENDUM
www.ti.com
21-Jun-2005
PACKAGING INFORMATION
Orderable Device
ADS1205IRGER
ADS1205IRGERG4
ADS1205IRGET
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
QFN
RGE
24
24
24
24
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
QFN
QFN
QFN
RGE
RGE
RGE
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
ADS1205IRGETG4
250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
orders and should verify that such information is current and complete. All products are sold subject to TI’s terms
and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for
their products and applications using TI components. To minimize the risks associated with customer products
and applications, customers should provide adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,
copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process
in which TI products or services are used. Information published by TI regarding third-party products or services
does not constitute a license from TI to use such products or services or a warranty or endorsement thereof.
Use of such information may require a license from a third party under the patents or other intellectual property
of the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of information in TI data books or data sheets is permissible only if reproduction is without
alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction
of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for
such altered documentation.
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that
product or service voids all express and any implied warranties for the associated TI product or service and
is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.
Following are URLs where you can obtain information on other Texas Instruments products and application
solutions:
Products
Applications
Audio
Amplifiers
amplifier.ti.com
www.ti.com/audio
Data Converters
dataconverter.ti.com
Automotive
www.ti.com/automotive
DSP
dsp.ti.com
Broadband
Digital Control
Military
www.ti.com/broadband
www.ti.com/digitalcontrol
www.ti.com/military
Interface
Logic
interface.ti.com
logic.ti.com
Power Mgmt
Microcontrollers
power.ti.com
Optical Networking
Security
www.ti.com/opticalnetwork
www.ti.com/security
www.ti.com/telephony
www.ti.com/video
microcontroller.ti.com
Telephony
Video & Imaging
Wireless
www.ti.com/wireless
Mailing Address:
Texas Instruments
Post Office Box 655303 Dallas, Texas 75265
Copyright 2005, Texas Instruments Incorporated
相关型号:
©2020 ICPDF网 联系我们和版权申明