ADS1210 [TI]
24-Bit ANALOG-TO-DIGITAL CONVERTER;
| 型号： | ADS1210 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 24-Bit ANALOG-TO-DIGITAL CONVERTER |
| 文件： | 总50页 (文件大小：1568K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
A
D
S
1
2
1
0
ADS1210
ADS1211
A
D
S
1
2
1
1
A
D
S
1
1
2
1
0
ADS1211
A
D
S
1
2
1
SBAS034B – JANUARY 1996 – REVISED SEPTEMBER 2005
24-Bit ANALOG-TO-DIGITAL CONVERTER
DESCRIPTION
FEATURES
● DELTA-SIGMA A/D CONVERTER
The ADS1210 and ADS1211 are precision, wide dynamic
range, delta-sigma Analog-to-Digital (A/D) converters with
24-bit resolution operating from a single +5V supply. The
differential inputs are ideal for direct connection to transduc-
ers or low-level voltage signals. The delta-sigma architec-
ture is used for wide dynamic range and to ensure 22 bits
of no-missing-code performance. An effective resolution of
23 bits is achieved through the use of a very low-noise input
amplifier at conversion rates up to 10Hz. Effective resolu-
tions of 20 bits can be maintained up to a sample rate of
1kHz through the use of the unique Turbo modulator mode
of operation. The dynamic range of the converters is further
increased by providing a low-noise programmable gain
amplifier with a gain range of 1 to 16 in binary steps.
● 23 BITS EFFECTIVE RESOLUTION AT 10Hz
AND 20 BITS AT 1000Hz
● DIFFERENTIAL INPUTS
● PROGRAMMABLE GAIN AMPLIFIER
● FLEXIBLE SPI™-COMPATIBLE SSI
INTERFACE WITH 2-WIRE MODE
● PROGRAMMABLE CUT-OFF FREQUENCY
UP TO 15.6kHz
● INTERNAL/EXTERNAL REFERENCE
● ON-CHIP SELF-CALIBRATION
● ADS1211 INCLUDES 4-CHANNEL MUX
The ADS1210 and ADS1211 are designed for high resolution
measurement applications in smart transmitters, industrial
process control, weigh scales, chromatography, and portable
instrumentation. Both converters include a flexible synchro-
nous serial interface that is SPI-compatible and also offers a
two-wire control mode for low cost isolation.
APPLICATIONS
● INDUSTRIAL PROCESS CONTROL
● INSTRUMENTATION
● BLOOD ANALYSIS
● SMART TRANSMITTERS
● PORTABLE INSTRUMENTS
● WEIGH SCALES
The ADS1210 is a single-channel converter and is offered in
both 18-pin DIP and 18-lead SOIC packages. The ADS1211
includes a 4-channel input multiplexer and is available in 24-
pin DIP, 24-lead SOIC, and 28-lead SSOP packages.
● PRESSURE TRANSDUCERS
AGND AVDD REFOUT
REFIN
VBIAS
XIN
XOUT
+2.5V
Reference
+3.3V Bias
Generator
Clock Generator
DGND
DVDD
AIN1P
A
IN1N
IN2P
IN2N
IN3P
IN3N
AIN4P
IN4N
Micro Controller
A
AIN
P
Second-Order
∆∑
Modulator
A
Instruction Register
Command Register
Data Output Register
Offset Register
Third-Order
Digital Filter
PGA
A
MUX
AINN
A
Full-Scale Register
A
SCLK
SDIO
Modulator Control
Serial Interface
SDOUT
ADS1211 Only
ADS1210/11
DSYNC
CS
MODE DRDY
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright © 1996-2005, Texas Instruments Incorporated
www.ti.com
SPECIFICATIONS
All specifications TMIN to TMAX, AVDD = DVDD = +5V, fXIN = 10MHz, programmable gain amplifier setting of 1, Turbo Mode Rate of 1, REFOUT disabled,VBIAS disabled,
and external 2.5V reference, unless otherwise specified.
ADS1210U, P/ADS1211U, P, E
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
ANALOG INPUT
Input Voltage Range(1)
0
–10
+5
+10
V
V
MΩ
(2)
With VBIAS
Input Impedance
Programmable Gain Amplifier
Input Capacitance
G = Gain, TMR = Turbo Mode Rate
User Programmable: 1, 2, 4, 8, or 16
4/(G • TMR)(3)
1
16
8
5
pF
pA
nA
Input Leakage Current
At +25°C
At TMIN to TMAX
50
1
SYSTEMS PERFORMANCE
Resolution
No Missing Codes
Integral Linearity
24
Bits
Bits
%FSR
%FSR
fDATA = 60Hz
fDATA = 60Hz
fDATA = 1000Hz, TMR of 16
22
±0.0015
±0.0015
Unipolar Offset Error(4)
Unipolar Offset Drift(6)
Gain Error(4)
See Note 5
1
µV/°C
See Note 5
Gain Error Drift(6)
1
115
115
µV/°C
dB
dB
dB
dB
Common-Mode Rejection(9)
At DC, +25°C
100
90
160
160
100
100
At DC, TMIN to TMAX
50Hz, fDATA = 50Hz(7)
60Hz, fDATA = 60Hz(7)
50Hz, fDATA = 50Hz(7)
60Hz, fDATA = 60Hz(7)
Normal-Mode Rejection
dB
dB
Output Noise
See Typical Performance Curves
Power Supply Rejection
DC, 50Hz, and 60Hz
65
dB
VOLTAGE REFERENCE
Internal Reference (REFOUT
Drift
Noise
Load Current
Output Impedance
)
2.4
2.5
25
50
2.6
1
V
ppm/°C
µVp-p
mA
Source or Sink
2
Ω
External Reference (REFIN
Load Current
VBIAS Output
Drift
Load Current
)
2.0
3.0
2.5
3.45
V
µA
V
Using Internal Reference
Source or Sink
3.15
3.3
50
ppm/°C
10mA
DIGITAL INPUT/OUTPUT
Logic Family
TTL Compatible CMOS
Logic Level: (all except XIN
)
VIH
VIL
VOH
IIH = +5µA
IIL = +5µA
IOH = 2 TTL Loads
IOL = 2 TTL Loads
2.0
–0.3
2.4
DVDD +0.3
0.8
V
V
V
V
V
VOL
XIN Input Levels: VIH
VIL
XIN Frequency Range (fXIN
Output Data Rate (fDATA
0.4
DVDD +0.3
0.8
10
15,625
781
3.5
–0.3
0.5
2.4
0.12
V
)
MHz
Hz
Hz
)
User Programmable
fXIN = 500kHz
Data Format
User Programmable
Two’s Complement
or Offset Binary
SYSTEM CALIBRATION
Offset and Full-Scale Limits
VFS – | VOS
VFS = Full-Scale Differential Voltage(8) 0.7 • (2 • REFIN)/G
VOS = Offset Differential Voltage(8)
|
1.3 • (2 • REFIN)/G
ADS1210, ADS1211
2
SBAS034B
www.ti.com
SPECIFICATIONS (CONT)
All specifications TMIN to TMAX, AVDD = DVDD = +5V, fXIN = 10MHz, programmable gain amplifier setting of 1, Turbo Mode Rate of 1, REFOUT disabled,VBIAS disabled,
and external 2.5V reference, unless otherwise specified.
ADS1210U, P/ADS1211U, P, E
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
POWER SUPPLY REQUIREMENTS
Power Supply Voltage
Power Supply Current:
Analog Current
4.75
5.25
V
2
3.5
mA
mA
Digital Current
Additional Analog Current with
REFOUT Enabled
1.6
1
mA
mA
VBIAS Enabled
No Load
Power Dissipation
26
37
17
27
11
40
60
mW
mW
mW
mW
mW
TMR of 16
fXIN = 2.5MHz
fXIN = 2.5MHz, TMR of 16
Sleep Mode
TEMPERATURE RANGE
Specified
Storage
–40
–60
+85
+125
°C
°C
NOTES: (1) In order to achieve the converter’s full-scale range, the input must be fully differential (AINN = 2 • REFIN – AINP). If the input is single-ended (AINN or
INP is fixed), then the full-scale range is one-half that of the differential range. (2) This range is set with external resistors and VBIAS (as described in the text).
A
Other ranges are possible. (3) Input impedance is higher with lower fXIN. (4) Applies after calibration. (5) After system calibration, these errors will be of the order
of the effective resolution of the converter. Refer to the Typical Performance Curves which apply to the desired mode of operation. (6) Recalibration can remove
these errors. (7) The specification also applies at fDATA /i, where i is 2, 3, 4, etc. (8) Voltages at the analog inputs must remain within AGND to AVDD. (9) The common-
mode rejection test is performed with a 100mV differential input.
ABSOLUTE MAXIMUM RATINGS
ELECTROSTATIC
DISCHARGE SENSITIVITY
Analog Input: Current ................................................ ±100mA, Momentary
±10mA, Continuous
Voltage ................................... AGND –0.3V to AVDD +0.3V
AVDD to DVDD ...........................................................................–0.3V to 6V
This integrated circuit can be damaged by ESD. Texas
AVDD to AGND .........................................................................–0.3V to 6V
DVDD to DGND .........................................................................–0.3V to 6V
AGND to DGND ................................................................................ ±0.3V
REFIN Voltage to AGND............................................ –0.3V to AVDD +0.3V
Digital Input Voltage to DGND .................................. –0.3V to DVDD +0.3V
Digital Output Voltage to DGND ............................... –0.3V to DVDD +0.3V
Lead Temperature (soldering, 10s) .............................................. +300°C
Power Dissipation (Any package) .................................................. 500mW
Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper han-
dling and installation procedures can cause damage.
ESD damage can range from subtle performance degrada-
tion to complete device failure. Precision integrated circuits
may be more susceptible to damage because very small
parametric changes could cause the device not to meet its
published specifications.
PACKAGE/ORDERING INFORMATION
For the most current package and ordering information,
see the Package Option Addendum located at the end of
this data sheet.
ADS1210, ADS1211
3
SBAS034B
www.ti.com
ADS1210 SIMPLIFIED BLOCK DIAGRAM
AGND AVDD
16
REF OUT
17
REF IN
18
VBIAS
4
XIN
XOUT
8
3
7
+2.5V
Reference
+3.3V Bias
Generator
Clock Generator
9
DGND
10 DVDD
Micro Controller
1
2
AIN
P
Second-Order
∆Σ
Modulator
Instruction Register
Command Register
Data Output Register
Offset Register
Third-Order
Digital Filter
PGA
A
INN
Full-Scale Register
11
SCLK
12
Modulator Control
Serial Interface
SDIO
13
SDOUT
6
5
15
14
DSYNC
CS
MODE DRDY
ADS1210 PIN CONFIGURATION
ADS1210 PIN DEFINITIONS
PIN NO
NAME
DESCRIPTION
TOP VIEW
DIP/SOIC
1
2
AIN
P
N
Noninverting Input.
Inverting Input.
AIN
3
AGND
VBIAS
CS
Analog Ground.
4
Bias Voltage Output, +3.3V nominal.
Chip Select Input.
A
INP
1
2
3
4
5
6
7
8
9
18 REFIN
5
AINN
17 REFOUT
16 AVDD
6
DSYNC
XIN
Control Input to Synchronize Serial Output Data.
System Clock Input.
7
AGND
VBIAS
CS
8
XOUT
System Clock Output (for Crystal or Resonator).
Digital Ground.
15 MODE
14 DRDY
13 SDOUT
12 SDIO
11 SCLK
10 DVDD
9
DGND
DVDD
SCLK
SDIO
ADS1210
10
11
12
Digital Supply, +5V nominal.
Clock Input/Output for serial data transfer.
DSYNC
XIN
Serial Data Input (can also function as Serial Data
Output).
Serial Data Output.
13
14
15
16
17
18
SDOUT
DRDY
MODE
AVDD
XOUT
Data Ready.
SCLK Control Input (Master = 1, Slave = 0).
Analog Supply, +5V nominal.
Reference Output, +2.5V nominal.
Reference Input.
DGND
REFOUT
REFIN
ADS1210, ADS1211
4
SBAS034B
www.ti.com
ADS1211 SIMPLIFIED BLOCK DIAGRAM
AGND AVDD
REFOUT
20
REFIN
21
VBIAS
7
XIN
10
XOUT
11
6
19
+2.5V
Reference
+3.3V Bias
Generator
Clock Generator
12 DGND
13 DVDD
4
A
IN1P
5
AIN1N
AIN2P
AIN2N
AIN3P
AIN3N
AIN4P
AIN4N
Micro Controller
2
Second-Order
∆∑
Modulator
Instruction Register
Command Register
Data Output Register
Offset Register
3
Third-Order
Digital Filter
MUX
PGA
24
1
Full-Scale Register
22
23
14
SCLK
15
Modulator Control
Serial Interface
SDIO
16
SDOUT
9
8
18
17
DSYNC
CS
MODE DRDY
ADS1211P AND ADS1211U PIN CONFIGURATION
ADS1211P AND ADS1211U PIN DEFINITIONS
PIN NO
NAME
AIN3N
AIN2P
AIN2N
AIN1P
AIN1N
AGND
VBIAS
DESCRIPTION
TOP VIEW
DIP/SOIC
1
2
Inverting Input Channel 3.
Noninverting Input Channel 2.
Inverting Input Channel 2.
Noninverting Input Channel 1.
Inverting Input Channel 1.
Analog Ground.
3
4
A
IN3N
IN2P
IN2N
IN1P
IN1N
1
2
3
4
5
6
7
8
9
24 AIN3P
5
A
23
22
A
IN4N
IN4P
6
7
Bias Voltage Output, +3.3V nominal.
Chip Select Input.
A
A
8
CS
A
21 REFIN
20 REFOUT
19 AVDD
9
DSYNC
XIN
Control Input to Synchronize Serial Output Data.
System Clock Input.
10
11
12
13
14
15
A
XOUT
System Clock Output (for Crystal or Resonator).
Digital Ground.
DGND
DVDD
SCLK
SDIO
AGND
VBIAS
Digital Supply, +5V nominal.
ADS1211P
ADS1211U
18 MODE
17 DRDY
16 SDOUT
15 SDIO
14 SCLK
13 DVDD
Clock Input/Output for serial data transfer.
Serial Data Input (can also function as Serial Data
Output).
CS
16
17
18
19
20
21
22
23
24
SDOUT
DRDY
MODE
AVDD
Serial Data Output.
DSYNC
Data Ready.
XIN 10
XOUT 11
SCLK Control Input (Master = 1, Slave = 0).
Analog Supply, +5V nominal.
Reference Output: +2.5V nominal.
Reference Input.
REFOUT
REFIN
AIN4P
DGND 12
Noninverting Input Channel 4.
Inverting Input Channel 4.
Noninverting Input Channel 3.
AIN4N
AIN3P
ADS1210, ADS1211
5
SBAS034B
www.ti.com
ADS1211E PIN CONFIGURATION
ADS1211E PIN DEFINITIONS
PIN NO
NAME
IN3N
DESCRIPTION
TOP VIEW
SSOP
1
2
A
Inverting Input Channel 3.
Noninverting Input Channel 2.
Inverting Input Channel 2.
Noninverting Input Channel 1.
Inverting Input Channel 1.
Analog Ground.
AIN2P
AIN2N
AIN1P
AIN1N
AGND
VBIAS
NIC
3
4
A
IN3N
IN2P
IN2N
IN1P
IN1N
1
2
3
4
5
6
7
8
9
28 AIN3P
5
A
27
26
A
A
IN4N
IN4P
6
7
Bias Voltage Output, +3.3V nominal.
Not Internally Connected.
Not Internally Connected.
Chip Select Input.
A
8
9
NIC
A
25 REFIN
24 REFOUT
23 AVDD
22 MODE
21 NIC
10
11
12
13
14
15
16
17
CS
A
DSYNC
XIN
Control Input to Synchronize Serial Output Data.
System Clock Input.
AGND
VBIAS
NIC
XOUT
System Clock Output (for Crystal or Resonator).
Digital Ground.
DGND
DVDD
SCLK
SDIO
ADS1211E
Digital Supply, +5V nominal.
Clock Input/Output for serial data transfer.
Serial Data Input (can also function as Serial Data
Output).
NIC
20 NIC
CS 10
DSYNC 11
XIN 12
19 DRDY
18 SDOUT
17 SDIO
16 SCLK
15 DVDD
18
19
20
21
22
23
24
25
26
27
28
SDOUT
DRDY
NIC
Serial Data Output.
Data Ready.
Not Internally Connected.
Not Internally Connected.
SCLK Control Input (Master = 1, Slave = 0).
Analog Supply, +5V nominal.
Reference Output: +2.5V nominal.
Reference Input.
NIC
MODE
AVDD
XOUT 13
REFOUT
REFIN
AIN4P
DGND 14
Noninverting Input Channel 4.
Inverting Input Channel 4.
Noninverting Input Channel 3.
A
IN4N
AIN3P
ADS1210, ADS1211
6
SBAS034B
www.ti.com
TYPICAL PERFORMANCE CURVES
At TA = +25°C, AVDD = DVDD = +5V, fXIN = 10MHz, programmable gain amplifier setting of 1, Turbo Mode Rate of one, REFOUT disabled, VBIAS disabled, and external
2.5V reference, unless otherwise noted.
EFFECTIVE RESOLUTION vs DATA RATE
(1MHz Clock)
EFFECTIVE RESOLUTION vs DATA RATE
(2.5MHz Clock)
24
22
20
18
16
14
12
24
22
20
18
16
14
12
Turbo 16
Turbo 16
Turbo 8
Turbo 8
Turbo 1
Turbo 1
Turbo 2
Turbo 2
Turbo 4
Turbo 4
1
10
100
1k
1k
1k
1
10
100
1k
Data Rate (Hz)
Data Rate (Hz)
EFFECTIVE RESOLUTION vs DATA RATE
(5MHz Clock)
EFFECTIVE RESOLUTION vs DATA RATE
(10MHz Clock)
24
22
20
18
16
14
12
24
22
20
18
16
14
12
Turbo 16
Turbo 16
Turbo 8
Turbo 8
Turbo 1
Turbo 1
Turbo 2
Turbo 2
Turbo 4
Turbo 4
10
100
10
100
Data Rate (Hz)
1k
Data Rate (Hz)
RMS NOISE vs INPUT VOLTAGE LEVEL
(60Hz Data Rate)
EFFECTIVE RESOLUTION vs DATA RATE
2.5
2.0
1.5
1.0
0.5
24
22
20
18
16
14
12
10
PGA 1
PGA 2
PGA 4
PGA 16
PGA 8
100
Data Rate (Hz)
–5.0 –4.0 –3.0 –2.0 –1.0
0
1.0 2.0 3.0 4.0 5.0
10
Analog Input Differential Voltage (V)
ADS1210, ADS1211
7
SBAS034B
www.ti.com
TYPICAL PERFORMANCE CURVES (CONT)
At TA = +25°C, AVDD = DVDD = +5V, fXIN = 10MHz, programmable gain amplifier setting of 1, Turbo Mode Rate of 1, REFOUT disabled, VBIAS disabled, and external
2.5V reference, unless otherwise noted.
POWER DISSIPATION vs TURBO MODE RATE
(REFOUT Enabled)
POWER DISSIPATION vs TURBO MODE RATE
(External Reference; REFOUT
)
50.0
40.0
30.0
20.0
40.0
30.0
20.0
10.0
10MHz
10MHz
5MHz
5MHz
2.5MHz
2.5MHz
1MHz
1MHz
1
2
4
8
16
1
2
4
8
16
Turbo Mode Rate
Turbo Mode Rate
PSRR vs FREQUENCY
CMRR vs FREQUENCY
85.0
80.0
75.0
70.0
65.0
120.0
115.0
110.0
0.1
1
10
100
1k
10k
100k
0.1
1
10
100
1k
Frequency (Hz)
Frequency (Hz)
LINEARITY vs TEMPERATURE
(60Hz Data Rate)
8
6
–40°C
–5°C
+25°C
+55°C
+85°C
4
2
0
–2
–4
–6
–5
–4
–3
–2 –1
0
1
2
3
4
5
Analog Input Differential Voltage (V)
ADS1210, ADS1211
8
SBAS034B
www.ti.com
THEORY OF OPERATION
The ADS1210 and ADS1211 are precision, high dynamic
range, self-calibrating, 24-bit, delta-sigma A/D converters
capable of achieving very high resolution digital results.
Each contains a programmable gain amplifier (PGA); a
second-order delta-sigma modulator; a programmable digi-
tal filter; a microcontroller including the Instruction, Com-
mand and Calibration registers; a serial interface; a clock
generator circuit; and an internal 2.5V reference. The
ADS1211 includes a 4-channel input multiplexer.
The output data rate of the ADS1210/11 can be varied from
a few hertz to as much as 15,625kHz, trading off lower
resolution results for higher data rates. In addition, the data
rate determines the first null of the digital filter and sets the
–3dB point of the input bandwidth (see the Digital Filter
section). Changing the data rate of the ADS1210/11 does not
result in a change in the sampling rate of the input capacitor.
The data rate effectively sets the number of samples which
are used by the digital filter to obtain each conversion result.
A lower data rate results in higher resolution, lower input
bandwidth, and different notch frequencies than a higher
data rate. It does not result in any change in input impedance
or modulator frequency, or any appreciable change in power
consumption.
In order to provide low system noise, common-mode rejec-
tion of 115dB and excellent power supply rejection, the
design topology is based on a fully differential switched
capacitor architecture. Turbo Mode, a unique feature of the
ADS1210/11, can be used to boost the sampling rate of the
input capacitor, which is normally 19.5kHz with a 10MHz
clock. By programming the Command Register, the sam-
pling rate can be increased to 39kHz, 78kHz, 156kHz, or
312kHz. Each increase in sample rate results in an increase
in performance when maintaining the same output data rate.
The ADS1210/11 also includes complete on-board calibra-
tion that can correct for internal offset and gain errors or
limited external system errors. Internal calibration can be
run when needed, or automatically and continuously in the
background. System calibration can be run as needed and the
appropriate input voltages must be provided to the ADS1210/
11. For this reason, there is no continuous System Calibra-
tion Mode. The calibration registers are fully readable and
writable. This feature allows for switching between various
configurations—different data rates, Turbo Mode Rates, and
gain settings—without re-calibrating.
The programmable gain amplifier (PGA) of the ADS1210/
11 can be set to a gain of 1, 2, 4, 8 or 16—substantially
increasing the dynamic range of the converter and simplify-
ing the interface to the more common transducers (see Table
I). This gain is implemented by increasing the number of
samples taken by the input capacitor from 19.5kHz for a
gain of 1 to 312kHz for a gain of 16. Since the Turbo Mode
and PGA functions are both implemented by varying the
sampling frequency of the input capacitor, the combination
of PGA gain and Turbo Mode Rate is limited to 16 (see
Table II). For example, when using a Turbo Mode Rate of
8 (156kHz at 10MHz), the maximum PGA gain setting is 2.
The various settings, rates, modes, and registers of the
ADS1210/11 are read or written via a synchronous serial
interface. This interface can operate in either a self-clocked
mode (Master Mode) or an externally clocked mode (Slave
Mode). In the Master Mode, the serial clock (SCLK) fre-
quency is one-half of the ADS1210/11 XIN clock frequency.
This is an important consideration for many systems and
may determine the maximum ADS1210/11 clock that can be
used.
ANALOG
INPUT(1)
ANALOG INPUT
UTILIZING VBIAS
(1,2)
FULL-
EXAMPLE
VOLTAGE
RANGE(3)
(V)
FULL-
SCALE
RANGE
(V)
EXAMPLE
The high resolution and flexibility of the ADS1210/11 allow
these converters to fill a wide variety of A/D conversion
tasks. In order to ensure that a particular configuration will
meet the design goals, there are several important items
which must be considered. These include (but are certainly
not limited to) the needed resolution, required linearity,
desired input bandwidth, power consumption goal, and sen-
sor output voltage.
SCALE
RANGE
(V)
VOLTAGE
RANGE(3)
(V)
GAIN
SETTING
1
2
4
8
16
10
5
2.5
1.25
0.625
0 to 5
40
20
10
5
±10
±5
±2.5
±1.25
±0.625
1.25 to 3.75
1.88 to 3.13
2.19 to 2.81
2.34 to 2.66
2.5
NOTE: (1) With a 2.5V reference, such as the internal reference. (2) This
example utilizes the circuit in Figure 12. Other input ranges are possible. (3)
The ADS1210/11 allows common-mode voltage as long as the absolute
The remainder of this data sheet discusses the operation of
the ADS1210/11 in detail. In order to allow for easier
comparison of different configurations, “effective resolu-
tion” is used as the figure of merit for most tables and
graphs. For example, Table III shows a comparison between
data rate (and –3dB input bandwidth) versus PGA setting at
a Turbo Mode Rate of 1 and a clock rate of 10MHz. See the
Definition of Terms section for a definition of effective
resolution.
input voltage on AINP or AINN does not go below AGND or above AVDD
.
TABLE I. Full-Scale Range vs PGA Setting.
TURBO MODE RATE
AVAILABLE PGA SETTINGS
1
2
4
1, 2, 4, 8, 16
1, 2, 4, 8
1, 2, 4
1, 2
8
16
1
TABLE II. Available PGA Settings vs Turbo Mode Rate.
ADS1210, ADS1211
9
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For example, when the converter is configured with a 2.5V
reference and placed in a gain setting of 2, the typical input
voltage range is 1.25V to 3.75V. However, an input range of
0V to 2.5V or 2.5V to 5V would also cover the converter’s
full-scale range.
DATA
RATE FREQUENCY
(HZ)
-3DB
EFFECTIVE RESOLUTION (BITS RMS)
(HZ)
G = 1
G = 2
G = 4
G = 8
G = 16
10
25
30
50
60
100
250
500
1000
2.62
6.55
7.86
13.1
15.7
26.2
65.5
131
21.5
20.5
20.5
20.0
19.5
18.0
15.0
12.5
10.0
21.0
20.5
20.5
20.0
19.5
18.0
15.0
12.5
10.5
21.0
20.5
20.5
20.0
19.5
18.0
15.0
12.5
10.0
21.0
20.0
20.0
19.5
19.0
18.0
15.0
12.5
10.0
20.0
19.5
19.5
19.0
19.0
18.0
15.0
12.5
10.0
Voltage Span—This is simply the magnitude of the typical
analog input voltage range. For example, when the converter
is configured with a 2.5V reference and placed in a gain
setting of 2, the input voltage span is 2.5V.
262
Least Significant Bit (LSB) Weight—This is the theoreti-
cal amount of voltage that the differential voltage at the
analog input would have to change in order to observe a
change in the output data of one least significant bit. It is
computed as follows:
TABLE III. Effective Resolution vs Data Rate and Gain
Setting. (Turbo Mode Rate of 1 and a 10MHz
clock.)
Full−Scale Range
LSB Weight =
DEFINITION OF TERMS
2N
An attempt has been made to be consistent with the termi-
nology used in this data sheet. In that regard, the definition
of each term is given as follows:
where N is the number of bits in the digital output.
Effective Resolution—The effective resolution of the
ADS1210/11 in a particular configuration can be expressed
in two different units: bits rms (referenced to output) and
microvolts rms (referenced to input). Computed directly
from the converter’s output data, each is a statistical calcu-
lation based on a given number of results. Knowing one, the
other can be computed as follows:
Analog Input Differential Voltage—For an analog signal
that is fully differential, the voltage range can be compared
to that of an instrumentation amplifier. For example, if both
analog inputs of the ADS1210 are at 2.5V, then the differ-
ential voltage is 0V. If one is at 0V and the other at 5V, then
the differential voltage magnitude is 5V. But, this is the case
regardless of which input is at 0V and which is at 5V, while
the digital output result is quite different.
10V
The analog input differential voltage is given by the follow-
ing equation: AINP – AINN. Thus, a positive digital output is
produced whenever the analog input differential voltage is
positive, while a negative digital output is produced when-
ever the differential is negative.
PGA
ER in Vrms
20 • log
− 1.76
ER in bits rms =
6.02
For example, when the converter is configured with a 2.5V
reference and placed in a gain setting of 2, the positive full-
scale output is produced when the analog input differential
is 2.5V. The negative full-scale output is produced when the
differential is –2.5V. In each case, the actual input voltages
must remain within the AGND to AVDD range (see Table I).
10V
PGA
ER in Vrms =
6.02 • ER in bits rms + 1.76
20
10
Actual Analog Input Voltage—The voltage at any one
analog input relative to AGND.
The 10V figure in each calculation represents the full-scale
range of the ADS1210/11 in a gain setting of 1. This means
that both units are absolute expressions of resolution—the
performance in different configurations can be directly com-
pared regardless of the units. Comparing the resolution of
different gain settings expressed in bits rms requires ac-
counting for the PGA setting.
Full-Scale Range (FSR)—As with most A/D converters,
the full-scale range of the ADS1210/11 is defined as the
“input” which produces the positive full-scale digital output
minus the “input” which produces the negative full-scale
digital output.
Main Controller—A generic term for the external
microcontroller, microprocessor, or digital signal processor
which is controlling the operation of the ADS1210/11 and
receiving the output data.
For example, when the converter is configured with a 2.5V
reference and is placed in a gain setting of 2, the full-scale
range is: [2.5V (positive full scale) minus –2.5V (negative
full scale)] = 5V.
Typical Analog Input Voltage Range—This term de-
scribes the actual voltage range of the analog inputs which
will cover the converter’s full-scale range, assuming that
each input has a common-mode voltage that is greater than
REFIN/PGA and smaller than (AVDD – REFIN/PGA).
ADS1210, ADS1211
10
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fXIN—The frequency of the crystal oscillator or CMOS
compatible input signal at the XIN input of the ADS1210/11.
NORMALIZED DIGITAL FILTER RESPONSE
0
–20
fMOD—The frequency or speed at which the modulator of the
ADS1210/11 is running, given by the following equation:
–40
–60
f
XIN • Turbo Mode
fMOD
=
–80
512
–100
–120
–140
–160
fSAMP—The frequency or switching speed of the input
sampling capacitor. The value is given by the following
equation:
f
XIN • Turbo Mode • Gain Setting
fSAMP
=
0
1
2
3
4
5
6
512
Frequency (Hz)
fDATA, tDATA—The frequency of the digital output data
produced by the ADS1210/11 or the inverse of this (the
period), respectively, fDATA is also referred to as the data rate.
FIGURE 1. Normalized Digital Filter Response.
FILTER RESPONSE
0
–20
–40
fXIN • Turbo Mode
1
fDATA
=
, tDATA =
–60
512 • Decimation Ratio + 1
fDATA
(
)
–80
–100
–120
–140
–160
Conversion Cycle—The term “conversion cycle” usually
refers to a discrete A/D conversion operation, such as that
performed by a successive approximation converter. As
used here, a conversion cycle refers to the tDATA time period.
However, each digital output is actually based on the modu-
lator results from the last three tDATA time periods.
0
50
100
150
200
250
300
Frequency (Hz)
FILTER RESPONSE
–40
–60
–80
–100
–120
–140
–160
DIGITAL FILTER
45
46
47
48
49
50
51
52
53
54
55
The digital filter of the ADS1210/11 computes the output
result based on the most recent results from the delta-sigma
modulator. The number of modulator results that are used
depend on the decimation ratio set in the Command Regis-
ter. At the most basic level, the digital filter can be thought
of as simply averaging the modulator results and presenting
this average as the digital output.
Frequency (Hz)
FIGURE 2. Digital Filter Response at a Data Rate of 50Hz.
FILTER RESPONSE
0
–20
–40
–60
–80
–100
–120
–140
–160
While the decimation ratio determines the number of modu-
lator results to use, the modulator runs faster at higher Turbo
Modes. These two items, together with the ADS1210/11
clock frequency, determine the output data rate:
0
50
100
150
200
250
300
Frequency (Hz)
FILTER RESPONSE
–40
–60
fXIN • Turbo Mode
–80
fDATA
=
–100
–120
–140
–160
512 • Decimation Ratio + 1
(
)
Also, since the conversion result is essentially an average,
the data rate determines where the resulting notches are in
the digital filter. For example, if the output data rate is 1kHz,
then a 1kHz input frequency will average to zero during the
1ms conversion cycle. Likewise, a 2kHz input frequency
will average to zero, etc.
55
56
57
58
59
60
61
62
63
64
65
Frequency (Hz)
FIGURE 3. Digital Filter Response at a Data Rate of 60Hz.
If the effective resolution at a 50Hz or 60Hz data rate is not
adequate for the particular application, then power line fre-
quencies could still be rejected by operating the ADS1210/11
at 25/30Hz, 16.7/20Hz, 12.5/15Hz, etc. If a higher data rate
is needed, then power line frequencies must either be rejected
before conversion (with an analog notch filter) or after
conversion (with a digital notch filter running on the main
controller).
In this manner, the data rate can be used to set specific notch
frequencies in the digital filter response (see Figure 1 for the
normalized response of the digital filter). For example, if the
rejection of power line frequencies is desired, then the data
rate can simply be set to the power line frequency. Figures
2 and 3 show the digital filter response for a data rate of
50Hz and 60Hz, respectively.
ADS1210, ADS1211
11
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Filter Equation
the effective resolution of the output data at a given data rate,
but there is also an increase in power dissipation. For Turbo
Mode Rates 2 and 4, the increase is slight. For rates 8 and
16, the increase is more substantial. See the Typical Perfor-
mance Curves for more information.
The digital filter is described by the following transfer
function:
3
π • f • N
sin
fMOD
In a Turbo Mode Rate of 16, the ADS1210/11 can offer 20
bits of effective resolution at a 1kHz data rate. A comparison
of effective resolution versus Turbo Mode Rates and output
data rates is shown in Table IV while Table V shows the
corresponding noise level in µVrms.
| H (f) | =
π • f
N • sin
fMOD
where N is the Decimation Ratio.
This filter has a (sin(x)/x)3 response and is referred to a sinc3
filter. For the ADS1210/11, this type of filter allows the data
rate to be changed over a very wide range (nearly four orders
of magnitude). However, the –3dB point of the filter is 0.262
times the data rate. And, as can be seen in Figures 1 and 2,
the rejection in the stopband (frequencies higher than the
first notch frequency) may only be –40dB.
EFFECTIVE RESOLUTION (BITS RMS)
DATA
RATE
(HZ)
TURBO
MODE
RATE 1
TURBO
MODE
TURBO
MODE
TURBO
MODE
TURBO
MODE
RATE 16
RATE 2
RATE 4
RATE 8
10
20
40
50
60
21.5
21.0
20.0
20.0
19.5
18.0
10.0
22.0
22.0
21.5
21.5
21.0
20.0
12.5
22.5
22.0
22.0
21.5
21.5
21.0
15.0
22.5
22.5
22.0
22.0
21.5
17.5
23.0
23.0
23.0
22.5
20.0
These factors must be considered in the overall system
design. For example, with a 50Hz data rate, a significant
signal at 75Hz may alias back into the passband at 25Hz.
The analog front end can be designed to provide the needed
attenuation to prevent aliasing, or the system may simply
provide this inherently. Another possibility is increasing the
data rate and then post filtering with a digital filter on the
main controller.
100
1000
TABLEIV. EffectiveResolutionvsDataRateandTurboMode
Rate. (Gain setting of 1 and 10MHz clock.)
NOISE LEVEL (µVrms)
DATA
RATE
(Hz)
TURBO
MODE
RATE 1
TURBO
MODE
TURBO
MODE
TURBO
MODE
TURBO
MODE
RATE 16
RATE 2
RATE 4
RATE 8
Filter Settling
10
20
40
50
60
2.9
4.3
6.9
1.7
2.1
3.0
3.2
3.9
1.3
1.7
2.3
2.4
2.6
1.3
1.6
1.8
1.9
2.7
The number of modulator results used to compute each
conversion result is three times the Decimation Ratio. This
means that any step change (or any channel change for the
ADS1211) will require at least three conversions to fully
settle. However, if the change occurs asynchronously, then at
least four conversions are required to ensure complete set-
tling. For example, on the ADS1211, the fourth conversion
result after a channel change will be valid (see Figure 4).
1.0
1.0
1.0
1.4
7.8
8.1
10.5
26.9
6909.7
100
1000
6.9
1354.5
3.5
238.4
46.6
TABLE V. Noise Level vs Data Rate and Turbo Mode Rate.
(Gain setting of 1 and 10MHz clock.)
The Turbo Mode feature allows trade-offs to be made
between the ADS1210/11 XIN clock frequency, power dissi-
pation, and effective resolution. If a 5MHz clock is available
but a 10MHz clock is needed to achieve the desired perfor-
mance, a Turbo Mode Rate of 2X will result in the same
effective resolution. Table VI provides a comparison of
effective resolution at various clock frequencies, data rates,
and Turbo Mode Rates.
Significant Analog Input Change
or
ADS1211 Channel Change
Data
not
Valid
Data
not
Valid
Data
not
Valid
Valid
Data
Valid
Data
Valid
Data
Valid
Data
DRDY
Serial
I/O
DATA
RATE
(Hz)
XIN CLOCK
FREQUENCY
(MHz)
TURBO
MODE
RATE
EFFECTIVE
RESOLUTION
(Bits rms)
tDATA
60
60
60
60
60
100
100
100
100
100
10
5
2.5
1.25
0.625
10
5
2.5
1.25
0.625
1
2
4
8
16
1
2
4
8
16
19.5
19.5
19.5
19.5
19.5
18.0
18.0
18.0
18.0
18.0
FIGURE 4. Asynchronous ADS1210/11 Analog Input Volt-
age Step or ADS1211 Channel Change to Fully
Settled Output Data.
TURBO MODE
The ADS1210/11 offers a unique Turbo Mode feature which
can be used to increase the modulator sampling rate by 2, 4,
8, or 16 times normal. With the increase of modulator
sampling frequency, there can be a substantial increase in
TABLE VI. Effective Resolution vs Data Rate, Clock
Frequency, and Turbo Mode Rate. (Gain set-
ting of 1.)
ADS1210, ADS1211
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The Turbo Mode Rate (TMR) is programmed via the Sam-
pling Frequency bits of the Command Register. Due to the
increase in input capacitor sampling frequency, higher Turbo
Mode settings result in lower analog input impedance;
CALIBRATION
The ADS1210/11 offers several different types of calibra-
tion, and the particular calibration desired is programmed
via the Command Register. In the case of Background
Calibration, the calibration will repeat at regular intervals
indefinitely. For all others, the calibration is performed once
and then normal operation is resumed.
AIN Impedance (Ω) = (10MHz/fXIN)•4.3E6/(G•TMR)
where G is the gain setting. Because the modulator rate also
changes in direct relation to the Turbo Mode setting, higher
values result in a lower impedance for the REFIN input:
Each type of calibration is covered in detail in its respective
section. In general, calibration is recommended immediately
after power-on and whenever there is a “significant” change
in the operating environment. The amount of change which
should cause a re-calibration is dependent on the applica-
tion, effective resolution, etc. Where high accuracy is impor-
tant, re-calibration should be done on changes in tempera-
ture and power supply. In all cases, re-calibration should be
done when the gain, Turbo Mode, or data rate is changed.
REFIN Impedance (Ω) = (10MHz/fXIN)•1E6/TMR
The Turbo Mode Rate can be set to 1, 2, 4, 8, or 16. Consult
the graphs shown in the Typical Performance Curves for full
details on the performance of the ADS1210/11 operating in
different Turbo Mode Rates. Keep in mind that higher Turbo
Mode Rates result in fewer available gain settings as shown
in Table II.
After a calibration has been accomplished, the Offset Cali-
bration Register and the Full-Scale Calibration Register
contain the results of the calibration. The data in these
registers are accurate to the effective resolution of the
ADS1210/11’s mode of operation during the calibration.
Thus, these values will show a variation (or noise) equiva-
lent to a regular conversion result.
PROGRAMMABLE GAIN AMPLIFIER
The programmable gain amplifier gain setting is programmed
via the PGA Gain bits of the Command Register. Changes
in the gain setting (G) of the programmable gain amplifier
results in an increase in the input capacitor sampling fre-
quency. Thus, higher gain settings result in a lower analog
input impedance:
For those cases where this error must be reduced, it is
tempting to consider running the calibration at a slower data
rate and then increasing the converter’s data rate after the
calibration is complete. Unfortunately, this will not work as
expected. The reason is that the results calculated at the
slower data rate would not be valid for the higher data rate.
Instead, the calibration should be done repeatedly. After
each calibration, the results can be read and stored. After the
desired number of calibrations, the main controller can
compute an average and write this value into the calibration
registers. The resulting error in the calibration values will be
reduced by the square root of the number of calibrations
which were averaged.
AIN Impedance (Ω) = (10MHz/fXIN)•4.3E6/(G•TMR)
where TMR is the Turbo Mode Rate. Because the modulator
speed does not depend on the gain setting, the input imped-
ance seen at REFIN does not change.
The PGA can be set to gains of 1, 2, 4, 8, or 16. These gain
settings with their resulting full-scale range and typical
voltage range are shown in Table I. Keep in mind that higher
Turbo Mode Rates result in fewer available gain settings as
shown in Table II.
SOFTWARE GAIN
The calibration registers can also be used to provide system
offset and gain corrections separate from those computed by
the ADS1210/11. For example, these might be burned into
E2PROM during final product testing. On power-on, the
main controller would load these values into the calibration
registers. A further possibility is a look-up table based on the
current temperature.
The excellent performance, flexibility, and low cost of the
ADS1210/11 allow the converter to be considered for de-
signs which would not normally need a 24-bit ADC. For
example, many designs utilize a 12-bit converter and a high-
gain INA or PGA for digitizing low amplitude signals. For
some of these cases, the ADS1210/11 by itself may be a
solution, even though the maximum gain is limited to 16.
Note that the values in the calibration registers will vary from
configuration to configuration and from part to part. There is
no method of reliably computing what a particular calibration
register should be to correct for a given amount of system
error. It is possible to present the ADS1210/11 with a known
amount of error, perform a calibration, read the desired
calibration register, change the error value, perform another
calibration, read the new value and use these values to
interpolate an intermediate value.
To get around the gain limitation, the digital result can
simply be shifted up by “n” bits in the main controller—
resulting in a gain of “n” times G, where G is the gain
setting. While this type of manipulation of the output data
is obvious, it is easy to miss how much the gain can be
increased in this manner on a 24-bit converter.
For example, shifting the result up by three bits when the
ADS1210/11 is set to a gain of 16 results in an effective gain
of 128. At lower data rates, the converter can easily provide
more than 12 bits of resolution. Even higher gains are
possible. The limitation is a combination of the needed data
rate, desired noise performance, and desired linearity.
ADS1210, ADS1211
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Normal
Mode
Normal
Mode
Self-Calibration
Mode
Offset
Calibration on
Internal Offset(2)
Full-Scale
Calibration on
Internal Full-Scale
Analog
Input
Conversion
Valid
Data
Valid
Data
Valid
Data
Valid
Data
DRDY
SC(1)
Serial
I/O
tDATA
NOTES: (1) SC = Self-Calibration instruction. (2) In Slave Mode, this function requires 4 cycles.
FIGURE 5. Self-Calibration Timing.
Mode bits are reset to 000 (Normal Mode). A single conver-
sion is done with DRDY HIGH. After this conversion, the
DRDY signal goes LOW indicating resumption of normal
operation.
Self-Calibration
A self-calibration is performed after the bits 001 have been
written to the Command Register Operation Mode bits
(MD2 through MD0). This initiates the following sequence
at the start of the next conversion cycle (see Figure 5). The
DRDY signal will not go LOW but will remain HIGH and
will continue to remain HIGH throughout the calibration
sequence. The inputs to the sampling capacitor are discon-
nected from the converter’s analog inputs and are shorted
together. An offset calibration is performed over the next
three conversion periods (four in Slave Mode). Then, the
input to the sampling capacitor is connected across REFIN,
and a full-scale calibration is performed over the next three
conversions.
Normal operation returns within a single conversion cycle
because it is assumed that the input voltage at the converter’s
input is not removed immediately after the offset calibration
is performed. In this case, the digital filter already contains
a valid result.
For full system calibration, offset calibration must be per-
formed first and then full-scale calibration. In addition, the
offset calibration error will be the rms sum of the conversion
error and the noise on the system offset voltage. See the
System Calibration Limits section for information regarding
the limits on the magnitude of the system offset voltage.
After this, the Operation Mode bits are reset to 000 (normal
mode) and the input capacitor is reconnected to the input.
Conversions proceed as usual over the next three cycles in
order to fill the digital filter. DRDY remains HIGH during
this time. On the start of the fourth cycle, DRDY goes LOW
indicating valid data and resumption of normal operation.
System Full-Scale Calibration
A system full-scale calibration is performed after the bits
011 have been written to the Command Register Operation
Mode bits (MD2 through MD0). This initiates the following
sequence (see Figure 7). At the start of the next conversion
cycle, the DRDY signal will not go LOW but will remain
HIGH and will continue to remain HIGH throughout the
calibration sequence. The full-scale calibration will be per-
formed on the differential input voltage (2 • REFIN/G)
present at the converter’s input over the next three conver-
sion periods (four in Slave Mode). When this is done, the
Operation Mode bits are reset to 000 (Normal Mode). A
single conversion is done with DRDY HIGH. After this
conversion, the DRDY signal goes LOW indicating resump-
tion of normal operation.
System Offset Calibration
A system offset calibration is performed after the bits 010
have been written to the Command Register Operation
Mode bits (MD2 through MD0). This initiates the following
sequence (see Figure 6). At the start of the next conversion
cycle, the DRDY signal will not go LOW but will remain
HIGH and will continue to remain HIGH throughout the
calibration sequence. The offset calibration will be per-
formed on the differential input voltage present at the
converter’s input over the next three conversion periods
(four in Slave Mode). When this is done, the Operation
Normal
Mode
System Full-Scale
Calibration Mode
Normal
Mode
Normal
Mode
System Offset
Calibration Mode
Normal
Mode
Full-Scale
Calibration on
System Full-Scale(2)
Analog
Input
Conversion
Possibly Possibly
Valid
Data
Valid
Data
Valid
Data
Valid
Data
Offset
Calibration on
System Offset(2)
Analog
Input
Conversion
Possibly Possibly
Valid
Data
Valid
Data
Valid
Data
Valid
Data
DRDY
SFSC(1)
DRDY
SOC(1)
Serial
I/O
Serial
I/O
tDATA
tDATA
NOTES: (1) SFSC = System Full-Scale Calibration instruction.
(2) In Slave Mode, this function requires 4 cycles.
NOTES: (1) SOC = System Offset Calibration instruction.
(2) In Slave Mode, this function requires 4 cycles.
FIGURE 7. System Full-Scale Calibration Timing.
FIGURE 6. System Offset Calibration Timing.
ADS1210, ADS1211
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Normal operation returns within a single conversion cycle
because it is assumed that the input voltage at the converter’s
input is not removed immediately after the full-scale calibra-
tion is performed. In this case, the digital filter already
contains a valid result.
input. Conversions proceed as usual over the next three
cycles in order to fill the digital filter. DRDY remains
HIGH during this time. On the next cycle, the DRDY signal
goes LOW indicating valid data and resumption of normal
operation.
For full system calibration, offset calibration must be per-
formed first and then full-scale calibration. The calibration
error will be a sum of the rms noise on the conversion result
and the input signal noise. See the System Calibration Limits
section for information regarding the limits on the magni-
tude of the system full-scale voltage.
The system offset calibration range of the ADS1210/11
is limited and is listed in the Specifications Table. For
more information on how to use these specifications, see
the System Calibration Limits section. To calculate VOS
use 2 • REFIN /GAIN for VFS.
,
Background Calibration
Pseudo System Calibration
The Background Calibration Mode is entered after the bits
101 have been written to the Command Register Operation
Mode bits (MD2 through MD0). This initiates the following
continuous sequence (see Figure 9). At the start of the next
conversion cycle, the DRDY signal will not go LOW but
will remain HIGH. The inputs to the sampling capacitor are
disconnected from the converter’s analog input and shorted
together. An offset calibration is performed over the next
three conversion periods (in Slave Mode, the very first offset
calibration requires four periods and all subsequent offset
calibrations require three periods). Then, the input capacitor
is reconnected to the input. Conversions proceed as usual
over the next three cycles in order to fill the digital filter.
DRDY remains HIGH during this time. On the next cycle,
the DRDY signal goes LOW indicating valid data.
The Pseudo System Calibration is performed after the bits
100 have been written to the Command Register Operation
Mode bits (MD2 through MD0). This initiates the following
sequence (see Figure 8). At the start of the next conversion
cycle, the DRDY signal will not go LOW but will remain
HIGH and will continue to remain HIGH throughout the
calibration sequence. The offset calibration will be performed
on the differential input voltage present at the converter’s
input over the next three conversion periods (four in Slave
Mode). Then, the input to the sampling capacitor is discon-
nected from the converter’s analog input and connected
across REFIN. A gain calibration is performed over the next
three conversions.
After this, the Operation Mode bits are reset to 000 (normal
mode) and the input capacitor is then reconnected to the
Normal
Mode
Normal
Mode
Pseudo System
Calibration Mode
Offset
Calibration on
System Offset(2)
Full-Scale
Calibration on
Internal Full-Scale
Analog
Input
Conversion
Valid
Data
Valid
Data
Valid
Data
Valid
Data
DRDY
PSC(1)
Serial
I/O
tDATA
NOTES: (1) PSC = Pseudo System Calibration instruction. (2) In Slave Mode, this function requires 4 cycles.
FIGURE 8. Pseudo System Calibration Timing.
Normal
Mode
Background Calibration
Mode
Offset
Calibration on
Internal Offset(2)
Analog
Input
Conversion
Full-Scale
Calibration on
Internal Full-Scale
Analog
Input
Conversion
Cycle Repeats
with Offset
Calibration
Valid
Data
Valid
Data
DRDY
BC(1)
Serial
I/O
tDATA
NOTES: (1) BC = Background Calibration instruction. (2) In Slave Mode, the very first offset
calibration will require 4 cycles. All subsequent offset calibrations will require 3 cycles.
FIGURE 9. Background Calibration Timing.
ADS1210, ADS1211
15
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Also, during this cycle, the sampling capacitor is discon-
nected from the converter’s analog input and is connected
across REFIN. A gain calibration is initiated and proceeds
over the next three conversions. After this, the input capaci-
tor is once again connected to the analog input. Conversions
proceed as usual over the next three cycles in order to fill the
digital filter. DRDY remains HIGH during this time. On the
next cycle, the DRDY signal goes LOW indicating valid
data, the input to the sampling capacitor is shorted, and an
offset calibration is initiated. At this point, the Background
Calibration sequence repeats.
This will be an important consideration in many systems
which use a 2.5V or greater reference, as the input range is
constrained by the expected power supply variations. In
addition, the expected full-scale voltage will impact the
allowable offset voltage (and vice-versa) as the combination
of the two must remain within the power supply and ground
potentials, regardless of the results obtained via the range
calculation shown previously.
There are only two solutions to this constraint: either the
system design must ensure that the full-scale and offset
voltage variations will remain within the power supply and
ground potentials, or the part must be used in a gain of 2 or
greater.
In essence, the Background Calibration Mode performs
continuous self-calibration where the offset and gain cali-
brations are interleaved with regular conversions. Thus, the
data rate is reduced by a factor of 6. The advantage is that
the converter is continuously adjusting to environmental
changes such as ambient or component temperature (due to
airflow variations).
SLEEP MODE
The Sleep Mode is entered after the bits 110 have been
written to the Command Register Operation Mode bits
(MD2 through MD0). This mode is exited by entering a new
mode into the MD2-MD0 bits.
The ADS1210/11 will remain in the Background Calibra-
tion Mode indefinitely. To move to any other mode, the
Command Register Operation Mode bits (MD2 through
MD0) must be set to the appropriate values.
The Sleep Mode causes the analog section and a good deal
of the digital section to power down. For full analog power
down, the VBIAS generator and the internal reference must
also be powered down by setting the BIAS and REFO bits
in the Command Register accordingly. The power dissipa-
tion shown in the Specifications Table is with the internal
reference and the VBIAS generator disabled.
System Calibration Offset and Full-Scale
Calibration Limits
The System Offset and Full-Scale Calibration range of the
ADS1210/11 is limited and is listed in the Specifications
Table. The range is specified as:
To initiate serial communication with the converter while it
is in Sleep Mode, one of the following procedures must be
used: If CS is being used, simply taking CS LOW will
enable serial communication to proceed normally. If CS is
not being used (tied LOW) and the ADS1210/11 is in the
Master Mode, then a falling edge must be produced on the
SDIO line. If SDIO is LOW, the SDIO line must be taken
HIGH for 2 • tXIN periods (minimum) and then taken LOW.
Alternatively, SDIO can be forced HIGH after putting the
ADS1210/11 to “sleep” and then taken LOW when the
Sleep Mode is to be exited. Finally, if CS is not being used
(tied LOW) and the ADS1210/11 is in the Slave Mode, then
simply sending a normal Instruction Register command will
re-establish communication.
(VFS – | VOS |) < 1.3 • (2 • REFIN)/GAIN
(VFS – | VOS |) > 0.7 • (2 • REFIN)/GAIN
where VFS is the system full-scale voltage and | VOS | is the
absolute value of the system offset voltage. In the following
discussion, keep in mind that these voltages are differential
voltages.
For example, with the internal reference (2.5V) and a gain of
two, the previous equations become (after some manipulation):
VFS – 3.25 < VOS < VFS – 1.75
If VFS is perfect at 2.5V (positive full-scale), then VOS must
be greater than –0.75V and less than 0.75V. Thus, when offset
calibration is performed, the positive input can be no more
than 0.75V below or above the negative input. If this range is
exceeded, the ADS1210/11 may not calibrate properly.
Once serial communication is resumed, the Sleep Mode is
exited by changing the MD2-MD0 bits to any other mode.
When a new mode (other than Sleep) has been entered, the
ADS1210/11 will execute a very brief internal power-up
sequence of the analog and digital circuitry. Once this has
been done, one normal conversion cycle is performed before
the new mode is actually entered. At the end of this conversion
cycle, the new mode takes effect and the converter will
respond accordingly. The DRDY signal will remain HIGH
through the first conversion cycle. It will also remain HIGH
through the second, even if the new mode is the Normal Mode.
This calculation method works for all gains other than one.
For a gain of one and the internal reference (2.5V), the
equation becomes:
VFS – 6.5 < VOS < VFS – 3.5
With a 5V positive full-scale input, VOS must be greater than
–1.5V and less than 1.5V. Since the offset represents a
common-mode voltage and the input voltage range in a gain
of one is 0V to 5V, a common-mode voltage will cause the
actual input voltage to possibly go below 0V or above 5V.
The specifications also show that for the specifications to be
valid, the input voltage must not go below AGND by more
than 30mV or above AVDD by more than 30mV.
If the VBIAS generator and/or the internal reference have
been disabled, then they must be manually re-enabled via the
appropriate bits in the Command Register. In addition, the
internal reference will have to charge the external bypass
capacitor(s) and possibly other circuitry. There may also be
ADS1210, ADS1211
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considerations associated with VBIAS and the settling of
external circuitry. All of these must be taken into account
when determining the amount of time required to resume
normal operation. The timing diagram shown in Figure 10
does not take into account the settling of external circuitry.
the analog signal must reside within this range, the linearity
of the ADS1210/11 is only ensured when the actual analog
input voltage resides within a range defined by AGND –
30mV and AVDD +30mV. This is due to leakage paths
which occur within the part when AGND and AVDD are
exceeded.
For this reason, the 0V to 5V input range (gain of 1 with a 2.5V
reference) must be used with caution. Should AVDD be 4.75V,
the analog input signal would swing outside of the tested
specifications of the device. Designs utilizing this mode of
operation should consider limiting the span to a slightly smaller
range. Common-mode voltages are also a significant concern
in this mode and must be carefully analyzed.
Change to Normal Mode Occurs Here
Sleep Mode
One
Normal
(Other
Modes
Data
Not
Valid
Data(1)
Valid
Data(1)
Conversion Start Here)
Valid
DRDY
Serial
I/O
An input voltage range of 0.75V to 4.25V is the smallest
span that is allowed if a full system calibration will be
performed (see the Calibration section for more details).
This also assumes an offset error of zero. A better choice
would be 0.5V to 4.5V (a full-scale range of 9V). This span
would allow some offset error, gain error, power supply
drift, and common-mode voltage while still providing full
system calibration over reasonable variation in each of these
parameters.
tDATA
NOTE: (1) Assuming that the external circuitry has
been stable for the previous three tDATA periods.
FIGURE 10. Sleep Mode to Normal Mode Timing.
ANALOG OPERATION
ANALOG INPUT
The actual input voltage exceeding AGND or AVDD should not
be a concern in higher gain settings as the input voltage range
will reside well within 0V to 5V. This is true unless the
common-mode voltage is large enough to place positive full-
scale or negative full-scale outside of the AGND to AVDD range.
The input impedance of the analog input changes with
ADS1210/11 clock frequency (fXIN), gain (G), and Turbo
Mode Rate (TMR). The relationship is:
AIN Impedance (Ω) = (10MHz/fXIN)•4.3E6/(G•TMR)
REFERENCE INPUT
Figure 11 shows the basic input structure of the ADS1210.
The ADS1211 includes an input multiplexer, but this has
little impact on the analysis of the input structure. The
impedance is directly related to the sampling frequency of
the input capacitor. The XIN clock rate sets the basic sam-
pling rate in a gain of 1 and Turbo Mode Rate of 1. Higher
gains and higher Turbo Mode Rates result in an increase of
the sampling rate, while slower clock (XIN) frequencies
result in a decrease.
The input impedance of the REFIN input changes with clock
frequency (fXIN) and Turbo Mode Rate (TMR). The relationship
is:
REFIN Impedance (Ω) = (10MHz/fXIN)•1E6/TMR
Unlike the analog input, the reference input impedance has
a negligible dependency on the PGA gain setting.
The reference input voltage can vary between 2V and 3V. A
nominal voltage of 2.5V appears at REFOUT, and this can be
directly connected to REFIN. Higher reference voltages will
cause the full-scale range to increase while the internal
circuit noise of the converter remains approximately the
same. This will increase the LSB weight but not the internal
noise, resulting in increased signal-to-noise ratio and effec-
tive resolution. Likewise, lower reference voltages will de-
crease the signal-to-noise ratio and effective resolution.
RSW
(8kΩ typical)
High
Impedance
> 1GΩ
AIN
CINT
8pF Typical
Switching Frequency
= fSAMP
VCM
FIGURE 11. Analog Input Structure.
REFERENCE OUTPUT
The ADS1210/11 contains an internal +2.5V reference.
Tolerances, drift, noise, and other specifications for this
reference are given in the Specification Table. Note that it is
not designed to sink or to source more than 1mA of current.
In addition, loading the reference with a dynamic or variable
load is not recommended. This can result in small changes
in reference voltage as the load changes. Finally, for designs
approaching or exceeding 20 bits of effective resolution, a
low-noise external reference is recommended as the internal
reference may not provide adequate performance.
This input impedance can become a major point of consid-
eration in some designs. If the source impedance of the input
signal is significant or if there is passive filtering prior to the
ADS1210/11, then a significant portion of the signal can be
lost across this external impedance. How significant this
effect is depends on the desired system performance.
There are two restrictions on the analog input signal to the
ADS1210/11. Under no conditions should the current into
or out of the analog inputs exceed 10mA. In addition, while
ADS1210, ADS1211
17
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R1
3kΩ
AIN
P
REFIN
REFOUT
AVDD
±10V
±10V
1.0µF
AINN
R2
3kΩ
R3
1kΩ
R4
1kΩ
AGND
AGND
VBIAS
CS
AVDD
MODE
DRDY
SDOUT
SDIO
ADS1210
DVDD
DGND
GND
C1
12pF
DSYNC
XIN
XTAL
XOUT
DGND
SCLK
DVDD
C2
12pF
DVDD
DGND
DGND
FIGURE 12. ±10V Input Configuration Using VBIAS
.
The circuitry which generates the +2.5V reference can be
disabled via the Command Register and will result in a lower
power dissipation. The reference circuitry consumes a little over
1.6mA of current with no external load. When the ADS1210/11
is in its default state, the internal reference is enabled.
be present. When enabled, the VBIAS circuitry consumes
approximately 1mA with no external load.
On power-up, external signals may be present before VBIAS
is enabled. This can create a situation in which a negative
voltage is applied to the analog inputs (–2.5V for the circuit
shown in Figure 12), reverse biasing the negative input
protection diode. This situation should not be a problem as
long as the resistors R1 and R2 limit the current being
sourced by each analog input to under 10mA (a potential of
0V at the analog input pin should be used in the calculation).
VBIAS
The VBIAS output voltage is dependent on the reference input
(REFIN) voltage and is approximately 1.33 times as great.
This output is used to bias input signals such that bipolar
signals with spans of greater than 5V can be scaled to match
the input range of the ADS1210/11. Figure 12 shows a
connection diagram which will allow the ADS1210/11 to
accept a ±10V input signal (40V full-scale range).
DIGITAL OPERATION
SYSTEM CONFIGURATION
This method of scaling and offsetting the ±20V differential
input signal will be a concern for those requiring minimum
power dissipation. VBIAS will supply 1.68mA for every chan-
nel connected as shown. For the ADS1211, the current draw
is within the specifications for VBIAS, but, at 12mW, the
power dissipation is significant. If this is a concern, resistors
R1 and R2 can be set to 9kΩ and R3 and R4 to 3kΩ. This will
reduce power dissipation by one-third. In addition, these
resistors can also be set to values which will provide any
arbitrary input range. In all cases, the maximum current into
or out of VBIAS should not exceed its specification of 10mA.
The Micro Controller (MC) consists of an ALU and a
register bank. The MC has two states: power-on reset and
convert. In the power-on reset state, the MC resets all the
registers to their default state, sets up the modulator to a
stable state, and performs self-calibration at a 850Hz data
rate. After this, it enters the convert mode, which is the
normal mode of operation for the ADS1210/11.
The ADS1210/11 has 5 internal registers, as shown in Table
VII. Two of these, the Instruction Register and the Com-
mand Register, control the operation of the converter. The
Data Output Register (DOR) contains the result from the
most recent conversion. The Offset and Full-Scale Calibra-
tion Registers (OCR and FCR) contain data used for correct-
ing the internal conversion result before it is placed into the
DOR. The data in these two registers may be the result of a
calibration routine, or they may be values which have been
written directly via the serial interface.
Note that the connection diagram shown in Figure 12 causes
a constant amount of current to be sourced by VBIAS. This
will be very important in higher resolution designs as the
voltage at VBIAS will not change with loading, as the load is
constant. However, if the input signal is single-ended and one
side of the input is grounded, the load will not be constant and
VBIAS will change slightly with the input signal. Also, in all
cases, note that noise on VBIAS introduces a common-mode
error signal which is rejected by the converter.
INSR
DOR
CMR
OCR
FCR
Instruction Register
Data Output Register
Command Register
8 Bits
24 Bits
32 Bits
24 Bits
24 Bits
Offset Calibration Register
Full-Scale Calibration Register
The 3k resistors should not be used as part of an anti-alias
filter with a capacitor across the inputs. The ADS1210
samples charge from the capacitor which has the effect of
introducing an offset in the measurement. This might be
acceptable for relative differential measurements.
TABLE VII. ADS1210/11 Registers.
Communication with the ADS1210/11 is controlled via the
Instruction Register (INSR). Under normal operation, the INSR
is written as the first part of each serial communication. The
instruction that is sent determines what type of communication
will occur next. It is not possible to read the INSR.
The circuitry to generate VBIAS is disabled when the
ADS1210/11 is in its default state, and it must be enabled,
via the Command Register, in order for the VBIAS voltage to
ADS1210, ADS1211
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The Command Register (CMR) controls all of the ADS1210/
11’s options and operating modes. These include the PGA
gain setting, the Turbo Mode Rate, the output data rate
(decimation ratio), etc. The CMR is the only 32-bit register
within the ADS1210/11. It, and all the remaining registers,
may be read from or written to.
Each serial communication starts with the 8-bits of the INSR
being sent to the ADS1210/11. This directs the remainder of
the communication cycle, which consists of n bytes being
read from or written to the ADS1210/11. The read/write bit,
the number of bytes n, and the starting register address are
defined, as shown in Table VIII. When the n bytes have been
transferred, the INSR is complete. A new communication
cycle is initiated by sending a new INSR (under restrictions
outlined in the Interfacing section).
Instruction Register (INSR)
The INSR is an 8-bit register which commands the serial
interface either to read or to write “n” bytes beginning at the
specified register location. Table VIII shows the format for
the INSR.
Command Register (CMR)
The CMR controls all of the functionality of the ADS1210/
11. The new configuration takes effect on the negative
transition of SCLK for the last bit in each byte of data being
written to the command register. The organization of the
CMR is shown in Table X.
MSB
LSB
R/W
MB1
MB0
0
A3
A2
A1
A0
TABLE VIII. Instruction Register.
Most Significant Bit
Byte 3
R/W (Read/Write) Bit—For a write operation to occur, this
bit of the INSR must be 0. For a read, this bit must be 1, as
follows:
DSYNC(1)
DRDY
BIAS REFO
DF
U/B
BD
MSB
SDL
0 Off 1 On 0 Two’s 0 Biplr 0 MSByte 0 MSB 0 SDIO
0
Defaults
NOTE: (1) DSYNC is Write only, DRDY is Read only.
R/W
0
1
Write
Read
Byte 2
MD2
MD1
MD0
G2
G1
G0
CH1
CH0
000 Normal Mode
000 Gain 1
00 Channel 1
Defaults
Defaults
Defaults
MB1, MB0 (Multiple Bytes) Bits—These two bits are used
to control the word length (number of bytes) of the read or
write operation, as follows:
Byte 1
SF2
SF1
SF0
DR12 DR11 DR10 DR9 DR8
00000
000 Turbo Mode Rate of 1
MB1
MB0
Byte 0
Least Significant Bit
DR2 DR1 DR0
0
0
1
1
0
1
0
1
1 Byte
2 Bytes
3 Bytes
4 Bytes
DR7
DR6
DR5
DR4
DR3
(00000) 0001 0110 (22) Data Rate of 849Hz
TABLE X. Organization of the Command Register and
Default Status.
A3-A0 (Address) Bits—These four bits select the begin-
ning register location which will be read from or written to,
as shown in Table IX. Each subsequent byte will be read
from or written to the next higher location. (If the BD bit in
the Command Register is set, each subsequent byte will be
read from the next lower location. This bit does not affect the
write operation.) If the next location is not defined in Table
IX, then the results are unknown. Reading or writing contin-
ues until the number of bytes specified by MB1 and MB0
have been transferred.
BIAS (Bias Voltage) Bit—The BIAS bit controls the VBIAS
output state—either on (1.33 • REFIN) or off (disabled), as
follows:
BIAS
VBIAS GENERATOR
VBIAS STATUS
0
1
Off
On
Disabled
1.33•REFIN
Default
The VBIAS circuitry consumes approximately 1mA of steady
state current with no external load. See the VBIAS section for
full details. When the internal reference (REFOUT) is con-
nected to the reference input (REFIN), VBIAS is 3.3V, nominal.
A3
A2
A1
A0
REGISTER BYTE
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
1
1
1
1
0
0
0
1
1
1
0
0
1
0
0
1
1
0
0
1
0
0
1
0
1
0
0
1
0
1
0
1
0
0
1
0
Data Output Register Byte 2 (MSB)
Data Output Register Byte 1
Data Output Register Byte 0 (LSB)
Command Register Byte 3 (MSB)
Command Register Byte 2
REFO (Reference Output) Bit—The REFO bit controls
the internal reference (REFOUT) state, either on (2.5V) or off
(disabled), as follows:
Command Register Byte 1
Command Register Byte 0 (LSB)
Offset Cal Register Byte 2 (MSB)
Offset Cal Register Byte 1
Offset Cal Register Byte 0 (LSB)
Full-Scale Cal Register Byte 2 (MSB)
Full-Scale Cal Register Byte 1
Full-Scale Cal Register Byte 0 (LSB)
REFO
INTERNAL REFERENCE
REFOUT STATUS
0
1
Off
On
High Impedance
2.5V
Default
The internal reference circuitry consumes approximately
1.6mA of steady state current with no external load. See the
Reference Output section for full details on the internal
reference.
Note: MSB = Most Significant Byte, LSB = Least Significant Byte
TABLE IX. A3-A0 Addressing.
ADS1210, ADS1211
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DF (Data Format) Bit—The DF bit controls the format of
the output data, either Two’s Complement or Offset Binary,
as follows:
SDL (Serial Data Line) Bit—The SDL bit controls which
pin on the ADS1210/11 will be used as the serial data output
pin, either SDIO or SDOUT, as follows:
SDL
SERIAL DATA OUTPUT PIN
DF
FORMAT
ANALOG INPUT DIGITAL OUTPUT
0
1
SDIO
SDOUT
Default
0
Two’s
Complement
+Full-Scale
Zero
–Full-Scale
7FFFFFH
000000H
800000H
Default
1
Offset Binary
+Full-Scale
Zero
–Full-scale
FFFFFFH
800000H
000000H
If SDL is LOW, then SDIO will be used for both input and
output of serial data—see the Timing section for more
details on how the SDIO pin transitions between these two
states. In addition, SDOUT will remain in a tri-state condi-
tion at all times.
These two formats are the same for all bits except the most
significant, which is simply inverted in one format vs the
other. This bit only applies to the Data Output Register—it
has no effect on the other registers.
Important Note: Since the default condition is SDL LOW,
SDIO has the potential of becoming an output once every
data output cycle if the ADS1210/11 is in the Master Mode.
This will occur until the Command Register can be written
and the SDL bit set HIGH. See the Interfacing section for
more information.
U/B (Unipolar) Bit—The U/B bit controls the limits im-
posed on the output data, as follows:
U/B
MODE
LIMITS
0
1
Bipolar
Unipolar
None
Default
DRDY (Data Ready) Bit—The DRDY bit is a read-only bit
which reflects the state of the ADS1210/11’s DRDY output
pin, as follows:
Zero to +Full-Scale only
The particular mode has no effect on the actual full-scale
range of the ADS1210/11, data format, or data format vs
input voltage. In the bipolar mode, the ADS1210/11 oper-
ates normally. In the unipolar mode, the conversion result is
limited to positive values only (zero included).
DRDY
MEANING
0
1
Data Ready
Data Not Ready
DSYNC (Data Synchronization) Bit—The DSYNC bit is
a write-only bit which occupies the same location as DRDY.
When a ‘one’ is written to this location, the effect on the
ADS1210/11 is the same as if the DSYNC input pin had
been taken LOW and returned HIGH. That is, the modulator
count for the current conversion cycle will be reset to zero.
This bit only controls what is placed in the Data Output
Register. It has no effect on internal data. When cleared, the
very next conversion will produce a valid bipolar result.
BD (Byte Order) Bit—The BD bit controls the order in
which bytes of data are read, either most significant byte
first or least significant byte, as follows:
DSYNC
MEANING
BD
BYTE ACCESS ORDER
0
1
No Change in Modulator Count
Modulator Count Reset to Zero
0
Most Significant
Default
to Least Significant Byte
The DSYNC bit is provided in order to reduce the number of
interface signals that are needed between the ADS1210/11
and the main controller. Consult “Making Use of DSYNC”
in the Serial Interface section for more information.
1
Least Significant
to Most Significant Byte
Note that when BD is clear and a multi-byte read is initiated,
A3-A0 of the Instruction Register is the address of the most
significant byte and subsequent bytes reside at higher ad-
dresses. If BD is set, then A3-A0 is the address of the least
significant byte and subsequent bytes reside at lower ad-
dresses. The BD bit only affects read operations; it has no
effect on write operations.
MD2-MD0 (Operating Mode) Bits—The MD2-MD0 bits
initiate or enable the various calibration sequences, as follows:
MD2
MD1
MD0
OPERATING MODE
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Normal Mode
Self-Calibration
MSB (Bit Order) Bit—The MSB bit controls the order in
which bits within a byte of data are read, either most
significant bit first or least significant bit, as follows:
System Offset Calibration
System Full-Scale Calibration
Pseudo System Calibration
Background Calibration
Sleep
MSB
BIT ORDER
Reserved
0
1
Most Significant Bit First
Least Significant Bit First
Default
The Normal Mode, Background Calibration Mode, and
Sleep Mode are permanent modes and the ADS1210/11 will
remain in these modes indefinitely. All other modes are
temporary and will revert to Normal Mode once the appro-
priate actions are complete. See the Calibration and Sleep
Mode sections for more information.
The MSB bit only affects read operations; it has no effect on
write operations.
ADS1210, ADS1211
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DATA
DECI-
RATE MATION
(HZ)
RATIO
DR12
DR11
DR10
DR9
DR8
DR7
DR6
DR5
DR4
DR3
DR2
DR1
DR0
1000
500
250
100
60
19
38
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
1
0
1
1
1
0
0
1
1
1
0
1
0
0
1
0
0
0
0
0
1
1
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
0
1
1
0
1
1
0
0
1
1
0
1
0
1
0
0
1
0
1
0
1
0
0
0
77
194
325
390
976
1952
50
20
10
Table XI. Decimation Ratios vs Data Rates (Turbo Mode rate of 1 and 10MHz clock).
The input capacitor sampling frequency and modulator rate
can be calculated from the following equations:
G2-G0 (PGA Control) Bits—The G2-G0 bits control the
gain setting of the PGA, as follows:
fSAMP = G • TMR • fXIN/512
fMOD = TMR • fXIN/512
GAIN
SETTING
AVAILABLE TURBO
MODE RATES
G2
G1
G0
0
0
0
0
1
0
0
1
1
0
0
1
0
1
0
1
2
4
8
16
1, 2, 4, 8, 16
1, 2, 4, 8
1, 2, 4
1, 2
Default
where G is the gain setting and TMR is the Turbo Mode
Rate. The sampling frequency of the input capacitor directly
relates to the analog input impedance. The modulator rate
relates to the power consumption of the ADS1210/11 and
the output data rate. See the Turbo Mode, Analog Input, and
Reference Input sections for more details.
1
The gain is partially implemented by increasing the input
capacitor sampling frequency, which is given by the follow-
ing equation:
DR12-DR0 (Decimation Ratio) Bits—The DR12-DR0 bits
control the decimation ratio of the ADS1210/11. In essence,
these bits set the number of modulator results which are used in
the digital filter to compute each individual conversion result.
Since the modulator rate depends on both the ADS1210/11
clock frequency and the Turbo Mode Rate, the actual output
data rate is given by the following equation:
fSAMP = G • TMR • fXIN/512
where G is the gain setting and TMR is the Turbo Mode
Rate. The product of G and TMR cannot exceed 16. The
sampling frequency of the input capacitor directly relates to
the analog input impedance. See the Programmable Gain
Amplifier and Analog Input sections for more details.
fDATA = fXIN • TMR/(512 • (Decimation Ratio + 1))
CH1-CH0 (Channel Selection) Bits—The CH1 and CH0 bits
control the input multiplexer on the ADS1211, as follows:
where TMR is the Turbo Mode Rate. Table XI shows
various data rates and corresponding decimation ratios (with
a 10MHz clock). Valid decimation ratios are from 19 to
8000. Outside of this range, the digital filter will compute
results incorrectly due to inadequate or too much data.
CH1
CH0
ACTIVE INPUT
0
0
1
1
0
1
0
1
Channel 1
Channel 2
Channel 3
Channel 4
Default
Data Output Register (DOR)
The DOR is a 24-bit register which contains the most recent
conversion result (see Table XII). This register is updated
with a new result just prior to DRDY going LOW. If the
contents of the DOR are not read within a period of time
defined by 1/fDATA –12•(1/fXIN), then a new conversion
result will overwrite the old. (DRDY is forced HIGH prior
to the DOR update, unless a read is in progress).
(For the ADS1210, CH1 and CH0 must always be zero.) The
channel change takes effect when the last bit of byte 2 has
been written to the Command Register. Output data will not
be valid for the next three conversions despite the DRDY
signal indicating that data is ready. On the fourth time that
DRDY goes LOW after a channel change has been written
to the Command Register, valid data will be present in the
Data Output Register (see Figure 4).
Most Significant Bit
Byte 2
DOR23
DOR15
DOR7
DOR22 DOR21 DOR20 DOR19 DOR18 DOR17 DOR16
Byte 1
SF2-SF0 (Turbo Mode Rate) Bits—The SF2-SF0 bits
control the input capacitor sampling frequency and modula-
tor rate, as follows:
DOR14 DOR13 DOR12 DOR11 DOR10
Byte 0 Least Significant Bit
DOR4 DOR3 DOR2 DOR1 DOR0
DOR9
DOR8
DOR6
DOR5
TURBO
MODE
RATE
AVAILABLE
PGA
SETTINGS
TABLE XII. Data Output Register.
SF2
SF1
SF0
0
0
0
0
1
0
0
1
1
0
0
1
0
1
0
1
2
4
8
16
1, 2, 4, 8, 16
1, 2, 4, 8
1, 2, 4
1, 2
Default
The contents of the DOR can be in Two’s Complement or
Offset Binary format. This is controlled by the DF bit of the
Command Register. In addition, the contents can be limited to
unipolar data only with the U/B bit of the Command Register.
1
ADS1210, ADS1211
21
SBAS034B
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Offset Calibration Register (OCR)
The actual FCR value will change from part-to-part and
with configuration, temperature, and power supply. Thus,
the actual FCR value for any arbitrary situation cannot be
accurately predicted. That is, a given system full-scale error
cannot be corrected simply by measuring the error exter-
nally, computing a correction factor, and writing that value
to the FCR. In addition, be aware that the contents of the
FCR are not used to directly correct the conversion result.
Rather, the correction is a function of the FCR value. This
function is linear and two known points can be used as a
basis for interpolating intermediate values for the FCR.
Consult the Calibration section for more details. The con-
tents of the FCR are in unsigned binary format. This is not
affected by the DF bit in the Command Register.
The OCR is a 24-bit register which contains the offset
correction factor that is applied to the conversion result before
it is placed in the Data Output Register (see Table XIII). In
most applications, the contents of this register will be the
result of either a self-calibration or a system calibration.
The OCR is both readable and writeable via the serial
interface. For applications requiring a more accurate offset
calibration, multiple calibrations can be performed, each
resulting OCR value read, the results averaged, and a more
precise offset calibration value written back to the OCR.
The actual OCR value will change from part-to-part and
with configuration, temperature, and power supply. Thus,
the actual OCR value for any arbitrary situation cannot be
accurately predicted. That is, a given system offset could not
be corrected simply by measuring the error externally, com-
puting a correction factor, and writing that value to the OCR.
In addition, be aware that the contents of the OCR are not
used to directly correct the conversion result. Rather, the
correction is a function of the OCR value. This function is
linear and two known points can be used as a basis for
interpolating intermediate values for the OCR. Consult the
Calibration section for more details.
TIMING
Table XV and Figures 13 through 21 define the basic digital
timing characteristics of the ADS1210/11. Figure 13 and the
associated timing symbols apply to the XIN input signal.
Figures 14 through 20 and associated timing symbols apply
to the serial interface signals (SCLK, SDIO, SDOUT, and
CS) and their relationship to DRDY. The serial interface is
discussed in detail in the Serial Interface section. Figure 21
and the associated timing symbols apply to the maximum
DRDY rise and fall times.
Most Significant Bit
Byte 2
OCR23
OCR15
OCR7
OCR22 OCR21 OCR20 OCR19 OCR18 OCR17 OCR16
Byte 1
tXIN
OCR14 OCR13 OCR12 OCR11 OCR10
Byte 0 Least Significant Bit
OCR4 OCR2 OCR1 OCR0
OCR9
OCR8
t2
t3
OCR6
OCR5
OCR3
XIN
TABLE XIII. Offset Calibration Register.
The contents of the OCR are in Two’s Complement format.
This is not affected by the DF bit in the Command Register.
FIGURE 13. XIN Clock Timing.
t4
Full-Scale Calibration Register (FCR)
t5
t6
t8
The FCR is a 24-bit register which contains the full-scale
correction factor that is applied to the conversion result before
it is placed in the Data Output Register (see Table XIV). In
most applications, the contents of this register will be the
result of either a self-calibration or a system calibration.
SCLK
(Internal)
t7
t9
SDIO
(as input)
SDOUT
(or SDlO
as output)
Most Significant Bit
Byte 2
FSR23
FSR15
FSR7
FSR22
FSR14
FSR6
FSR21
FSR13
FSR5
FSR20 FSR19 FSR18
Byte 1
FSR17 FSR16
FIGURE 14. Serial Input/Output Timing, Master Mode.
FSR12 FSR11 FSR10
FSR9
FSR8
Byte 0
FSR4
Least Significant Bit
FSR2 FSR1 FSR0
FSR3
t10
t11
t12
t14
TABLE XIV. Full-Scale Calibration Register.
SCLK
(External)
t13
t15
The FCR is both readable and writable via the serial inter-
face. For applications requiring a more accurate full-scale
calibration, multiple calibrations can be performed, each
resulting FCR value read, the results averaged, and a more
precise calibration value written back to the FCR.
SDIO
(as input)
SDOUT
(or SDlO
as output)
FIGURE 15. Serial Input/Output Timing, Slave Mode.
ADS1210, ADS1211
22
SBAS034B
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SYMBOL
DESCRIPTION
MIN
NOM
MAX
UNITS
fXIN
tXIN
t2
XIN Clock Frequency
XIN Clock Period
0.5
10
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
100
2000
XIN Clock High
0.4 • tXIN
0.4 • tXIN
t3
XIN Clock LOW
t4
Internal Serial Clock HIGH
tXIN
tXIN
t5
Internal Serial Clock LOW
t6
Data In Valid to Internal SCLK Falling Edge (Setup)
Internal SCLK Falling Edge to Data In Not Valid (Hold)
Data Out Valid to Internal SCLK Falling Edge (Setup)
Internal SCLK Falling Edge to Data Out Not Valid (Hold)
External Serial Clock HIGH
40
20
t7
t8
tXIN –25
tXIN
t9
t10
t11
t12
t13
t14
t15
t16
2.5 • tXIN
2.5 • tXIN
40
External Serial Clock LOW
Data In Valid to External SCLK Falling Edge (Setup)
External SCLK Falling Edge to Data In Not Valid (Hold)
Data Out Valid to External SCLK Falling Edge (Setup)
External SCLK Falling Edge to Data Out Not Valid (Hold)
20
tXIN –40
1.5 • tXIN
Falling Edge of DRDY to First SCLK Rising Edge
(Master Mode, CS Tied LOW)
6 • tXIN
5 • tXIN
3 • tXIN
t17
t18
t19
t20
t21
Falling Edge of Last SCLK for INSR to Rising Edge of First
SCLK for Register Data (Master Mode)
ns
ns
Falling Edge of Last SCLK for Register Data to Rising Edge
of DRDY (Master Mode)
Falling Edge of Last SCLK for INSR to Rising Edge of First
SCLK for Register Data (Slave Mode)
5.5 • tXIN
4 • tXIN
ns
ns
Falling Edge of Last SCLK for Register Data to Rising Edge
of DRDY (Slave Mode)
5 • tXIN
ns
Falling Edge of DRDY to Falling Edge of CS (Master and
Slave Mode)
0.5 • tXIN
ns
t22
t23
Falling Edge of CS to Rising Edge of SCLK (Master Mode)
5 • tXIN
6 • tXIN
ns
ns
Rising Edge of DRDY to Rising Edge of CS (Master and
Slave Mode)
10
t24
t25
Falling Edge of CS to Rising Edge of SCLK (Slave Mode)
5.5 • tXIN
3 • tXIN
2 • tXIN
ns
ns
Falling Edge of Last SCLK for INSR to SDIO Tri-state
(Master Mode)
2 • tXIN
2 • tXIN
t26
t27
SDIO as Output to Rising Edge of First SCLK for Register
Data (Master and Slave Modes)
ns
ns
Falling Edge of Last SCLK for INSR to SDIO Tri-state
(Slave Mode)
4 • tXIN
t28
t29
SDIO Tri-state Time (Master and Slave Modes)
tXIN
tXIN
ns
ns
Falling Edge of Last SCLK for Register Data to SDIO Tri-State
(Master Mode)
t30
Falling Edge of Last SCLK for Register Data to SDIO
Tri-state (Slave Mode)
3 • tXIN
ns
t31
t32
t33
t34
DRDY Fall Time
DRDY Rise Time
30
30
ns
ns
ns
ns
Minimum DSYNC LOW Time
10.5 • tXIN
DSYNC Valid HIGH to Falling Edge of XIN (for Exact
Synchronization of Multiple Converters only)
10
t35
t36
t37
t38
Falling Edge of XIN to DSYNC Not Valid LOW (for Exact
Synchronization of Multiple Converters only)
10
ns
ns
ns
ns
Falling Edge of Last SCLK for Register Data to Rising Edge
of First SCLK of next INSR (Slave Mode, CS Tied LOW)
20.5 • tXIN
10.5 • tXIN
5.5 • tXIN
Rising Edge of CS to Falling Edge of CS (Slave Mode,
Using CS)
Falling Edge of DRDY to First SCLK
Rising Edge (Slave Mode, CS Tied LOW)
TABLE XV. Digital Timing Characteristics.
ADS1210, ADS1211
23
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t16
DRDY
SCLK
SDIO
t18
t17
IN7
IN7
IN7
IN1
IN1
IN1
IN0
INM
IN1
IN0
Write Register Data
SDIO
IN0
OUTM
OUT1 OUT0
Read Register Data using SDIO
SDIO
IN0
SDOUT
OUTM
OUT1 OUT0
Read Register Data using SDOUT
FIGURE 16. Serial Interface Timing (CS LOW), Master Mode.
t38
DRDY
t20
t19
SCLK
t36
SDIO
SDIO
IN7
IN7
IN1
IN1
IN0
INM
IN1
IN0
IN7
IN7
Write Register Data
IN0
OUTM
OUT1 OUT0
Read Register Data using SDIO
SDIO
IN7
IN1
IN0
IN7
SDOUT
OUTM
OUT1 OUT0
Read Register Data using SDOUT
FIGURE 17. Serial Interface Timing (CS LOW), Slave Mode.
DRDY
t18
t21
CS
t22
t17
t23
SCLK
IN7
IN7
IN7
IN1
IN1
IN0
INM
IN1
IN0
SDIO
SDIO
Write Register Data
IN0
OUTM
OUT1 OUT0
Read Register Data using SDIO
IN1 IN0
SDIO
OUTM
Read Register Data using SDOUT
OUT1 OUT0
SDOUT
DRDY
t16
t18
CS
SCLK
OUTM
Continuous Read of Data Output Register using SDIO
OUTM OUT1 OUT0
Continuous Read of Data Output Register using SDOUT
OUT1 OUT0
SDIO
SDOUT
FIGURE 18. Serial Interface Timing (Using CS), Master Mode.
ADS1210, ADS1211
24
SBAS034B
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DRDY
t20
t21
t37
CS
t24
t24
t19
t23
SCLK
IN7
IN7
IN7
IN1
IN1
IN0
INM
IN1
IN0
IN7
SDIO
SDIO
Write Register Data
IN0
OUTM
OUT1 OUT0
IN7
IN7
Read Register Data Using SDIO
IN1 IN0
SDIO
OUTM
Read Register Data Using SDOUT
OUT1 OUT0
SDOUT
DRDY
t16
t20
CS
SCLK
OUTM
Continuous Read of Data Output Register using SDIO
OUTM OUT1 OUT0
Continuous Read of Data Output Register using SDOUT
OUT1 OUT0
SDIO
SDOUT
FIGURE 19. Serial Interface Timing (Using CS), Slave Mode.
t23
t18
t16
DRDY
t21
CS(1)
t26
t25
t17
t22
SCLK
Master
t29
Mode
OUT M
OUT0
t20
IN7
IN6
IN5
IN2
IN1
IN0
IN0
t27
SDIO
SCLK
t24
t26
Slave
Mode
t30
IN7
OUT MSB
OUT0
SDIO
t28
t38
t19
SDIO is an input
SDIO is an output
NOTE: (1) CS is optional.
FIGURE 20. SDIO Input to Output Transition Timing.
t32
t31
DRDY
FIGURE 21. DRDY Rise and Fall Time.
ADS1210, ADS1211
25
SBAS034B
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SERIAL INTERFACE
Synchronizing Multiple Converters
A negative going pulse on DSYNC can be used to synchro-
nize multiple ADS1210/11s. This assumes that each
ADS1210/11 is driven from the same master clock and is set
to the same Decimation Ratio and Turbo Mode Rate. The
effect that this signal has on data output timing in general is
discussed in the Serial Interface section.
The ADS1210/11 includes a flexible serial interface which
can be connected to microcontrollers and digital signal
processors in a variety of ways. Along with this flexibility,
there is also a good deal of complexity. This section de-
scribes the trade-offs between the different types of interfac-
ing methods in a top-down approach—starting with the
overall flow and control of serial data, moving to specific
interface examples, and then providing information on vari-
ous issues related to the serial interface.
The concern here is what happens if the DSYNC input is
completely asynchronous to this master clock. If the DSYNC
input rises at a critical point in relation to the master clock
input, then some ADS1210/11s may start-up one XIN clock
cycle before the others. Thus, the output data will be syn-
chronized, but only to within one XIN clock cycle.
Multiple Instructions
The general timing diagrams which appear throughout this
data sheet show serial communication to and from the
ADS1210/11 occurring during the DRDY LOW period (see
Figures 4 through 10 and Figure 36). This communication
represents one instruction that is executed by the ADS1210/
11, resulting in a single read or write of register data.
For many applications, this will be more than adequate. In
these cases, the timing symbols which relate the DSYNC
signal to the XIN signal can be ignored. For other multiple-
converter applications, this one XIN clock cycle difference
could be a problem. These types of applications would
include using the DRDY and/or the SCLK output from one
ADS1210/11 as the “master” signal for all converters.
However, more than one instruction can be executed by the
ADS1210/11 during any given conversion period (see Fig-
ure 24). Note that DRDY remains HIGH during the subse-
quent instructions. There are several important restrictions
on how and when multiple instructions can be issued during
any one conversion period.
To ensure exact synchronization to the same XIN edge, the
timing relationship between the DSYNC and XIN signals,
as shown in Figure 22, must be observed. Figure 23 shows
a simple circuit which can be used to clock multiple
ADS1210/11s from one ADS1210/11, as well as to ensure
that an asynchronous DSYNC signal will exactly synchro-
nize all the converters.
Internal
Update of DOR
12 • tXIN
DRDY
t34
Serial
I/O
XIN
t35
FIGURE 24. Timing of Data Output Register Update.
t33
DSYNC
The first restriction is that the converter must be in the Slave
Mode. There is no provision for multiple instructions when
the ADS1210/11 is operating in the Master Mode. The
second is that some instructions will produce invalid results
if started at the end of one conversion period and carried into
the start of the next conversion period.
FIGURE 22. DSYNC to XIN Timing for Synchronizing
Mutliple ADS1210/11s.
1/2 74AHC74
Asynchronous
DSYNC
Strobe
D
Q
CLK
Q
1/6 74AHC04
C1
12pF
DSYNC
XIN
SDOUT
DSYNC
XIN
SDOUT
SDIO
DSYNC
XIN
SDOUT
SDIO
SDIO
SCLK
DVDD
XTAL
XOUT
XOUT
SCLK
DVDD
XOUT
SCLK
DVDD
DGND
DGND
DGND
C2
DGND
12pF
ADS1210/11
ADS1210/11
ADS1210/11
FIGURE 23. Exactly Synchronizing Multiple ADS1210/11s to an Asynchronous DSYNC Signal.
ADS1210, ADS1211
26
SBAS034B
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For example, Figure 24 shows that just prior to the DRDY
signal going LOW, the internal Data Output Register (DOR)
is updated. This update involves the Offset Calibration
Register (OCR) and the Full-Scale Register (FSR). If the
OCR or FSR are being written, their final value may not be
correct, and the result placed into the DOR will certainly not
be valid. Problems can also arise if certain bits of the
Command Register are being changed.
initiated, the update is blocked. The old output data will
remain in the DOR and the new data will be lost. The old
data will remain valid until the read operation has com-
pleted. In general, multiple instructions may be issued, but
the last one in any conversion period should be complete
within 12 • XIN clock periods of the next DRDY LOW
time. In this usage, “complete” refers to the point where
DRDY rises in Figures 17 and 19 (in the Timing Section).
Consult Figures 25 and 26 for the flow of serial data
during any one conversion period.
Note that reading the Data Output Register is an excep-
tion. If the DOR is being read when the internal update is
Start
Reading
ADS1210/11
drives DRDY LOW
Start
Writing
ADS1210/11
drives DRDY LOW
CS
CS
state
state
HIGH
HIGH
LOW
LOW
CS
Continuous
Read
Mode?
state
HIGH
Yes
LOW
No
ADS1210/11
generates 8 serial clock
cycles and receives
Instruction Register
data via SDIO
ADS1210/11
generates 8
serial clock cycles
and receives
Instruction Register
data via SDIO
ADS1210/11
generates n
serial clock cycles
and receives
specified
Use
SDIO for
output?
Yes
register data
via SDIO
No
SDIO input to
output transition
SDOUT becomes
active from tri-state
ADS1210/11
drives DRDY HIGH
ADS1210/11 generates n
serial clock cycles
ADS1210/11 generates n
serial clock cycles
End
and transmits specified
register data via SDIO
and transmits specified
register data via SDOUT
SDOUT returns to
tri-state condition
SDIO transitions to
tri-state condition
ADS1210/11
drives DRDY HIGH
End
FIGURE 25. Flowchart for Writing and Reading Register Data, Master Mode.
ADS1210, ADS1211
27
SBAS034B
www.ti.com
Start
Reading
From Read
Flowchart
ADS1210/11
drives DRDY LOW
Start
Writing
To Write
Flowchart
ADS1210/11
drives DRDY LOW
CS taken HIGH
for 10.5 tXIN periods
minimum (see text
if CS tied LOW).
CS
state
HIGH
CS taken HIGH
for 10.5 tXIN periods
minimum (see text
if CS tied LOW).
LOW
CS
state
CS
state
Continuous
Read
Mode?
HIGH
HIGH
Yes
LOW
CS
state
LOW
No
External device
HIGH
generates 8
serial clock cycles
and transmits
instruction register
data via SDIO
External device generates
8 serial clock cycles
LOW
and transmits
instruction register
data via SDIO
External device
generates n
serial clock cycles
and transmits
specified
register data
via SDIO
Use
SDIO for
output?
Yes
No
SDIO input to
output transition
SDOUT becomes
active
ADS1210/11
drives DRDY HIGH
External device generates
n serial clock cycles
and transmits
External device generates
n serial clock cycles
and receives
Yes
No
Is Next
Instruction
a Read?
More
Instructions?
specified register
data via SDOUT
specified register
data via SDIO
See text
for restrictions
No
Yes
SDOUT returns to
tri-state condition
SDIO transitions to
tri-state condition
End
To Read
Flowchart
ADS1210/11
drives DRDY HIGH
No
Is Next
Instruction
a Write?
Yes
More
Instructions?
See text
for restrictions
Yes
No
End
To Write
Flowchart
FIGURE 26. Flowchart for Writing and Reading Register Data, Slave Mode.
ADS1210, ADS1211
28
SBAS034B
www.ti.com
Using CS and Continuous Read Mode
The recommended solution to this problem is to actively pull
SDIO LOW. If SDIO is LOW when the ADS1210/11 enters
the instruction byte, then the resulting instruction is a write
of one byte of data to the Data Output Register, which results
in no internal operation.
The serial interface may make use of the CS signal, or this
input may simply be tied LOW. There are several issues
associated with choosing to do one or the other.
The CS signal does not directly control the tri-state condition
of the SDOUT or SDIO output. These signals are normally
in the tri-state condition. They only become active when
serial data is being transmitted from the ADS1210/11. If the
ADS1210/11 is in the middle of a serial transfer and SDOUT
or SDIO is an output, taking CS HIGH will not tri-state the
output signal.
If the SDIO signal cannot be actively pulled LOW, then
another possibility is to time the initialization of the
controller’s serial port such that it becomes active between
adjacent DRDY LOW periods. The default configuration for
the ADS1210/11 produces a data rate of 814Hz—a conver-
sion period of 1.2ms. This time should be more than ad-
equate for most microcontrollers and DSPs to monitor DRDY
and initialize the serial port at the appropriate time.
If there are multiple serial peripherals utilizing the same
serial I/O lines and communication may occur with any
peripheral at any time, then the CS signal must be used. The
ADS1210/11 may be in the Master Mode or the Slave Mode.
In the Master Mode, the CS signal is used to hold-off serial
communication with a “ready” (DRDY LOW) ADS1210/11
until the main controller can accommodate the communica-
tion. In the Slave Mode, the CS signal is used to enable
communication with the ADS1210/11.
Master Mode
The Master Mode is active when the MODE input is HIGH.
All serial clock cycles will be produced by the ADS1210/11
in this mode, and the SCLK pin is configured as an output.
The frequency of the serial clock will be one-half of the XIN
frequency. Multiple instructions cannot be issued during a
single conversion period in this mode—only one instruction
per conversion cycle is possible.
The CS input has another use. If the CS state is left LOW
after a read of the Data Output Register has been performed,
then the next time that DRDY goes LOW, the ADS1210/11
Instruction Register will not be entered. Instead, the Instruc-
tion Register contents will be re-used, and the new contents
of the Data Output Register, or some part thereof, will be
transmitted. This will occur as long as CS is LOW and not
toggled.
The Master Mode will be difficult for some microcontrollers,
particularly when the XIN input frequency is greater than a
few MHz, as the serial clock may exceed the microcontroller’s
maximum serial clock frequency. For the majority of digital
signal processors, this will be much less of a concern. In
addition, if SDIO is being used as an input and an output,
then the transition time from input to output may be a
concern. This will be true for both microcontrollers and
DSPs. See Figure 20 in the Timing section.
This mode of operation is called the Continuous Read Mode
and is shown in the read flowcharts of Figures 25 and 26. It
is also shown in the Timing Diagrams of Figures 18 and 19
in the Timing section. Note that once CS has been taken
HIGH, the Continuous Read Mode will be enabled (but not
entered) and can never be disabled. The mode is actually
entered and exited as described above.
Note that if CS is tied LOW, there are special considerations
regarding SDIO as outlined previously in this section. Also
note that if CS is being used to control the flow of data from
the ADS1210/11 and it remains HIGH for one or more
conversion periods, the ADS1210/11 will operate properly.
However, the result in the Data Output Register will be lost
when it is overwritten by each new result. Just prior to this
update, DRDY will be forced HIGH and will return LOW
after the update.
Power-On Conditions for SDIO
Even if the SDIO connection will be used only for input,
there is one important item to consider regarding SDIO. This
only applies when the ADS1210/11 is in the Master Mode
and CS will be tied LOW. At power-up, the serial I/O lines
of most microcontrollers and digital signal processors will be
in a tri-state condition, or they will be configured as inputs.
When power is applied to the ADS1210/11, it will begin
operating as defined by the default condition of the Com-
mand Register (see Table X in the System Configuration
section). This condition defines SDIO as the data output pin.
Slave Mode
Most systems will use the ADS1210/11 in the Slave Mode.
This mode allows multiple instructions to be issued per
conversion period as well as allowing the main controller to
set the serial clock frequency and pace the serial data
transfer. The ADS1210/11 is in the Slave Mode when the
MODE input is LOW.
Since the ADS1210/11 is in the Master Mode and CS is tied
LOW, the serial clock will run whenever DRDY is LOW and
an instruction will be entered and executed. If the SDIO line
is HIGH, as it might be with an active pull-up, then the
instruction is a read operation and SDIO will become an
output every DRDY LOW period—for 32 serial clock cycles.
When the serial port on the main controller is enabled, signal
contention could result.
There are several important items regarding the serial clock
for this mode of operation. The maximum serial clock
frequency cannot exceed the ADS1210/11 XIN frequency
divided by 5 (see Figure 15 in the Timing section).
When using SDIO as the serial output, the falling edge of the
last serial clock cycle of the instruction byte will cause the
SDIO pin to begin its transition from input to output.
Between three and four XIN cycles after this falling edge, the
SDIO pin will become an output. This transition may be too
fast for some microcontrollers and digital signal processors.
ADS1210, ADS1211
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If a serial communication does not occur during any conver-
sion period, the ADS1210/11 will continue to operate prop-
erly. However, the results in the Data Output Register will
be lost when they are overwritten by the new result at the
start of the next conversion period. Just prior to this update,
DRDY will be forced HIGH and will return LOW after the
update.
nication to and from the ADS1210/11 should not occur for at
least 25ms after power is stable.)
If this requirement cannot be met or if the circuit has
brown-out considerations, the timing diagram of Figure 27
can be used to reset the ADS1210/11. This timing applies
only when the ADS1210/11 is in the Slave Mode and
accomplishes the reset by controlling the duty cycle of the
SCLK input. In general, a reset is required after power-up,
after a brown-out has been detected, or when a watchdog
timer event has occured.
Making Use of DSYNC
The DSYNC input pin and the DSYNC write bit in the
Command Register reset the current modulator count to
zero. This causes the current conversion cycle to proceed as
normal, but all modulator outputs from the last data output
to the point where DSYNC is asserted are discarded. Note
that the previous two data outputs are still present in the
ADS1210/11 internal memory. Both will be used to com-
pute the next conversion result, and the most recent one will
be used to compute the result two conversions later. DSYNC
does not reset the internal data to zero.
If the ADS1210/11 is in the Master Mode, a reset of the
device is not possible. If the power supply does not meet the
minimum ramp rate requirement, or brown-out is of concern,
low on-resistance MOSFETs or equivalent should be used to
control power to the ADS1210/11. When powered down, the
device should be left unpowered for at least 300ms before
power is reapplied. An alternate method would be to control
the MODE pin and temporarily place the ADS1210/11 in the
Slave Mode while a reset is initiated as shown in Figure 27.
There are two main uses of DSYNC. In the first case,
DSYNC allows for synchronization of multiple converters.
In regards to the DSYNC input pin, this case was discussed
under “Synchronizing Multiple Converters” in the Timing
section. In regards to the DSYNC bit, it will be difficult to
set all of the converter’s DSYNC bits at the same time
unless all of the converters are in the Slave Mode and the
same instruction can be sent to all of the converters at the
same time.
Two-Wire Interface
For a two-wire interface, the Master Mode of operation may
be preferable. In this mode, serial communication occurs
only when data is ready, informing the main controller as to
the status of the ADS1210/11. The disadvantages are that the
ADS1210/11 must have a dedicated serial port on the main
controller, only one instruction can be issued per data ready
period, and the serial clock may define the maximum clock
frequency of the converter.
The second use of DSYNC is to reset the modulator count
to zero in order to obtain valid data as quickly as possible.
For example, if the input channel is changed on the ADS1211,
the current conversion cycle will be a mix of the old channel
and the new channels. Thus, four conversions are needed in
order to ensure valid data. However, if the channel is
changed and then DSYNC is used to reset the modulator
count, the modulator data at the end of the current conver-
sion cycle will be entirely from the new channel. After two
additional conversion cycles, the output data will be com-
pletely valid. Note that the conversion cycle in which
DSYNC is used will be slightly longer than normal. Its
length will depend on when DSYNC was set.
In the Slave Mode, the main controller must read and write
to the ADS1210/11 “blindly.” Writes to the internal regis-
ters, such as the Command Register or Offset Calibration
Register, might occur during an update of the Data Output
Register. This can result in invalid data in the DOR. A two-
wire interface can be used if the main controller can read
and/or write to the converter, either much slower or much
faster that the data rate. For example, if much faster, the
main controller can use the DRDY bit to determine when
data is becoming valid (polling it multiple times during one
conversion cycle). Thus, the controller obtains some idea of
when to write to the internal register. If much slower, then
reads of the DOR might always return valid data (multiple
conversions have occurred since the last read of the DOR or
since any write of the internal registers).
Reset, Power-On Reset, and Brown-Out
The ADS1210/11 contains an internal power-on reset circuit.
If the power supply ramp rate is greater than 50mV/ms, this
circuit will be adequate to ensure that the device powers up
correctly. (Due to oscillator settling considerations, commu-
t1: > 256 • tXIN
Reset Occurs
at Falling Edge
< 400 • tXIN
t2: > 5 • tXIN
t2
t2
t3: > 512 • tXIN
< 900 • tXIN
SCLK
t1
t3
t4
t4: ≥ 1024 • tXIN
< 1200 • tXIN
FIGURE 27. Resetting the ADS1210/11 (Slave Mode only).
ADS1210, ADS1211
30
SBAS034B
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Three-Wire Interface
Figure 29 shows a different type of three-wire interface with
a 8xC51 microprocessor. Here, the Master Mode is used.
The interface signals consist of SDOUT, SDIO, and SCLK.
Figure 28 shows a three-wire interface with a 8xC32 micro-
processor. Note that the Slave Mode is being selected and
the SDIO pin is being used for input and output.
P1.0
8xC32
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
RESET
RXD
TXD
INT0
INT1
AVDD
AIN
P
N
REFIN
REFOUT
AVDD
1.0µF
AGND
AIN
AGND
VBIAS
CS
MODE
DRDY
SDOUT
SDIO
AGND
DGND
ADS1210
DVDD
DSYNC
XIN
XOUT
DGND
SCLK
R1
10kΩ
DVDD
DVDD
T0
T1
WR
RD
X2
DGND
C1
27pF
XTAL
X1
Q
Q
D
Q
Q
D
VSS
C2
27pF
CLK
CLK
1/2 74HC74
1/2 74HC74
FIGURE 28. Three-Wire Interface with a 8xC32 Microprocessor.
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
VCC
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
8xC51
AVDD
AIN
P
N
REFIN
REFOUT
AVDD
1.0µF
DVDD
AIN
AGND
VBIAS
CS
AGND
MODE
DRDY
SDOUT
SDIO
AGND
DVDD
ADS1210
C1
12pF
DSYNC
XIN
XTAL
XOUT
DGND
SCLK
R1
10kΩ
DVDD
C2
12pF
DGND
DGND
FIGURE 29. Three-Wire Interface with a 8xC51 Microprocessor.
ADS1210, ADS1211
31
SBAS034B
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Four-Wire Interface
Figure 30 shows a four-wire interface with a 8xC32 micro-
processor. Again, the Slave Mode is being used.
Note that the XIN input can also be controlled. It is possible
with some microcontrollers and digital signal processors to
produce a continuous serial clock, which could be connected
to the XIN input. The frequency of the clock is often settable
over some range. Thus, the power dissipation of the
ADS1210/11 could be dynamically varied by changing both
the Turbo Mode and XIN input, trading off conversion speed
and resolution for power consumption.
Multi-Wire Interface
Figures 31 and 32 show multi-wire interfaces with a 8xC51
or 68HC11 microprocessor. In these interfaces, the mode of
the ADS1210/11 is actually controlled dynamically. This
could be extremely useful when the ADS1210/11 is to be
used in a wide variety of ways. For example, it might be
desirable to have the ADS1210/11 produce data at a steady
rate and to have the converter operating in the Continuous
Read Mode. But for system calibration, the Slave Mode
might be preferred because multiple instructions can be
issued per conversion period.
I/O Recovery
If serial communication stops during an instruction or data
transfer for longer than 4 • tDATA, the ADS1210/11 will reset
its serial interface. This will not affect the internal registers.
The main controller must not continue the transfer after this
event, but must restart the transfer from the beginning.
Note that the MODE input should not be changed in the
middle of a serial transfer. This could result in misoperation
of the device. A Master/Slave Mode change will not affect
the output data.
This feature is very useful if the main controller can be reset
at any point. After reset, simply wait 8 • tDATA before
starting serial communication.
P1.0
8xC32
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
RESET
RXD
TXD
INT0
INT1
AVDD
AIN
P
REFIN
REFOUT
AVDD
1.0µF
AGND
A
INN
AGND
VBIAS
CS
MODE
DRDY
SDOUT
SDIO
AGND
DGND
DVDD
ADS1210
DSYNC
XIN
XOUT
DGND
SCLK
R1
10kΩ
DVDD
DVDD
WR
C1
27pF
RD
DGND
X2
X1
Q
Q
D
Q
Q
D
VSS
XTAL
C2
27pF
CLK
CLK
1/2 74HC74
1/2 74HC74
FIGURE 30. Four-Wire Interface with a 8xC32 Microprocessor.
AVDD
A
INP
REFIN
REFOUT
AVDD
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
VCC
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
8xC51
1.0µF
AGND
AIN
N
AGND
VBIAS
CS
MODE
DRDY
SDOUT
SDIO
AGND
ADS1210
C1
12pF
DSYNC
XIN
XTAL
XOUT
DGND
SCLK
R1
10kΩ
R2
10kΩ
DVDD
DVDD
C2
12pF
DGND
DGND
FIGURE 31. Full Interface with a 8xC51 Microprocessor.
ADS1210, ADS1211
32
SBAS034B
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PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
PE0
PE1
PE2
XIRQ
RESET
PC7
AVDD
AIN
P
PC6
REFIN
REFOUT
AVDD
1.0µF
AGND
AINN
PC5
68HC11
AGND
VBIAS
CS
PC4
PC3
PC2
PC1
PC0
XTAL
MODE
DRDY
SDOUT
SDIO
AGND
R1
10kΩ
ADS1210
DSYNC
XIN
C1
12pF
XOUT
DGND
SCLK
XTAL
R2
10kΩ
DVDD
DVDD
C2
DGND
12pF
FIGURE 32. Full Interface with a 68HC11 Microprocessor.
VDD2
DRDY
DGND
AVDD
VDD1
1.0µF
A
INP
INN
REFIN
REFOUT
AVDD
SDOUT
A
AGND
VDD1
VDD2
DGND
VDD1
GND
VDD2
AGND
VBIAS
CS
MODE
DRDY
SDOUT
SDIO
AGND
VDD1
GND
ADS1210
SDIN
C1
R1
100Ω
DSYNC
XIN
12pF
DGND
XTAL
XOUT
SCLK
C2
12pF
DGND
DVDD
DGND
DGND
VDD1
SCLK
VDD2
DGND
GND
FIGURE 33. Isolated Four-Wire Interface.
In addition, the digital outputs of the ADS1210/11 can, in
some cases, drive opto-isolators directly. Figures 34 and 35
show the voltage of the SDOUT pin versus source or sink
current under worst-case conditions. Worst-case conditions
for source current occur when the analog input differential
Isolation
The serial interface of the ADS1210/11 provides for simple
isolation methods. An example of an isolated four-wire
interface is shown in Figure 33. The ISO150 is used to
transmit the digital signals over the isolation barrier.
ADS1210, ADS1211
33
SBAS034B
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SOURCE CURRENT
30
25
20
15
10
5
A
IN3N
AIN2P
IN2N
AIN1P
IN1N
A
IN3P
AIN4N
IN4P
+5V
R1
49.9kΩ
A
A
–40°C
25°C
85°C
REFIN
REFOUT
AVDD
REF1004
+2.5V
A
1.0µF
+5V
AGND
VBIAS
CS
AVDD
+5V
ADS1211U, P
MODE
DRDY
SDOUT
SDIO
+5V
+5V
VOH
C1
12pF
DSYNC
XIN
VOH
0V
P1
XTAL
2kΩ
XOUT
DGND
SCLK
C2
12pF
DVDD
+5V
DGND
0
0
1
2
3
4
5
DGND
V
OH (V)
FIGURE 34. Source Current vs VOH for SDOUT Under Worst-Case Conditions.
SINK CURRENT
30
A
A
A
A
A
IN3N
A
IN3P
IN4N
IN4P
+5V
IN2P
IN2N
IN1P
IN1N
A
25°C
R1
49.9kΩ
–40°C
25
20
15
10
5
A
REFIN
REFOUT
AVDD
85°C
REF1004
+2.5V
1.0µF
0V
AGND
VBIAS
CS
AVDD
+5V
ADS1211U, P
MODE
DRDY
SDOUT
SDIO
+5V
C1
+5V
DSYNC
XIN
VOL
12pF
VOL
0V
P1
2kΩ
XTAL
XOUT
DGND
SCLK
C2
DVDD
+5V
0
DGND
12pF
0
1
2
3
4
5
DGND
V
OL (V)
FIGURE 35. Sink Current vs VOL for SDOUT Under Worst-Case Conditions.
voltage is 5V and the output format is Offset Binary
(FFFFFFH). For sink current, the worst-case condition oc-
curs when the analog input differential voltage is 0V and the
output format is Two’s Complement (000000H).
Note that an asynchronous DSYNC input may cause mul-
tiple converters to be different from one another by one XIN
clock cycle. This should not be a concern for most applica-
tions. However, the Timing section contains information on
exactly synchronizing multiple converters to the same XIN
clock cycle.
Note that SDOUT is tri-stated for the majority of the
conversion period and the opto-isolator connection must
take this into account.
tDATA
Synchronization of Multiple Converters
DRDY A
The DSYNC input is used to synchronize the output data of
multiple ADS1210/11s. Synchronization involves configur-
ing each ADS1210/11 to the same Decimation Ratio and
Turbo Mode setting, and providing a common signal to the
XIN inputs. Then, the DSYNC signal is pulsed LOW (see
Figure 22 in the Timing section). This results in an internal
reset of the modulator count for the current conversion.
Thus, all the converters start counting from zero at the same
time, producing a DRDY LOW signal at approximately the
same point (see Figure 36).
tDATA
DRDY B
tDATA
DRDY C
DSYNC
tDATA
FIGURE 36. Effect of Synchronization on Output Data
Timing.
ADS1210, ADS1211
34
SBAS034B
www.ti.com
LAYOUT
POWER SUPPLIES
For a single converter system, AGND and DGND of the
ADS1210/11 should be connected together, underneath the
converter. Do not join the ground planes, but connect the
two with a moderate signal trace. For multiple converters,
connect the two ground planes at one location as central to
all of the converters as possible. In some cases, experimen-
tation may be required to find the best point to connect the
two planes together. The printed circuit board can be de-
signed to provide different analog/digital ground connec-
tions via short jumpers. The initial prototype can be used to
establish which connection works best.
The ADS1210/11 requires the digital supply (DVDD) to be
no greater than the analog supply (AVDD) +0.3V. In the
majority of systems, this means that the analog supply must
come up first, followed by the digital supply. Failure to
observe this condition could cause permanent damage to the
ADS1210/11.
Inputs to the ADS1210/11, such as SDIO, AIN, or REFIN,
should not be present before the analog and digital supplies
are on. Violating this condition could cause latch-up. If these
signals are present before the supplies are on, series resistors
should be used to limit the input current (see the Analog
Input and VBIAS sections of this data sheet for more details
concerning these inputs).
DECOUPLING
Good decoupling practices should be used for the ADS1210/
11 and for all components in the design. All decoupling
capacitors, but specifically the 0.1µF ceramic capacitors,
should be placed as close as possible to the pin being
decoupled. A 1µF to 10µF capacitor, in parallel with a 0.1µF
ceramic capacitor, should be used to decouple AVDD to
AGND. At a minimum, a 0.1µF ceramic capacitor should be
used to decouple DVDD to DGND, as well as for the digital
supply on each digital component.
The best scheme is to power the analog section of the design
and AVDD of the ADS1210/11 from one +5V supply and the
digital section (and DVDD) from a separate +5V supply. The
analog supply should come up first. This will ensure that AIN
and REFIN do not exceed AVDD and that the digital inputs
are present only after AVDD has been established, and that
they do not exceed DVDD
.
The analog supply should be well-regulated and low-noise. For
designs requiring very high resolution from the ADS1210/11,
power supply rejection will be a concern. See the PSRR vs
Frequency curve in the Typical Performance Curves section of
this data sheet for more information.
SYSTEM CONSIDERATIONS
The recommendations for power supplies and grounding
will change depending on the requirements and specific
design of the overall system. Achieving 20 bits or more of
effective resolution is a great deal more difficult than achiev-
ing 12 bits. In general, a system can be broken up into four
different stages:
The requirements for the digital supply are not as strict.
However, high frequency noise on DVDD can capacitively
couple into the analog portion of the ADS1210/11. This
noise can originate from switching power supplies, very fast
microprocessors or digital signal processors.
Analog Processing
Analog Portion of the ADS1210/11
Digital Portion of the ADS1210/11
Digital Processing
For either supply, high frequency noise will generally be
rejected by the digital filter except at interger multiplies of
fMOD. Just below and above these frequencies, noise will
alias back into the passband of the digital filter, affecting the
conversion result.
For the simplest system consisting of minimal analog signal
processing (basic filtering and gain), a self-contained micro-
controller, and one clock source, high-resolution could be
achieved by powering all components by a common power
supply. In addition, all components could share a common
ground plane. Thus, there would be no distinctions between
“analog” and “digital” power and ground. The layout should
still include a power plane, a ground plane, and careful
decoupling.
If one supply must be used to power the ADS1210/11, the
AVDD supply should be used to power DVDD. This connec-
tion can be made via a 10Ω resistor which, along with the
decoupling capacitors, will provide some filtering between
DVDD and AVDD. In some systems, a direct connection can
be made. Experimentation may be the best way to determine
the appropriate connection between AVDD and DVDD
.
In a more extreme case, the design could include: multiple
ADS1210/11s; extensive analog signal processing; one or
more microcontrollers, digital signal processors, or micro-
processors; many different clock sources; and interconnec-
tions to various other systems. High resolution will be very
difficult to achieve for this design. The approach would be
to break the system into as many different parts as possible.
For example, each ADS1210/11 may have its own “analog”
processing front end, its own analog power and ground
(possibly shared with the analog front end), and its own
“digital” power and ground. The converter’s “digital” power
and ground would be separate from the power and ground
for the system’s processors, RAM, ROM, and “glue” logic.
GROUNDING
The analog and digital sections of the design should be care-
fully and cleanly partitioned. Each section should have its own
ground plane with no overlap between them. AGND should be
connected to the analog ground plane as well as all other analog
grounds. DGND should be connected to the digital ground
plane and all digital signals referenced to this plane.
The ADS1210/11 pinout is such that the converter is cleanly
separated into an analog and digital portion. This should allow
simple layout of the analog and digital sections of the design.
ADS1210, ADS1211
35
SBAS034B
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APPLICATIONS
The ADS1210/11 can be used in a broad range of data
acquisition tasks. The following application diagrams show
the ADS1210 and/or ADS1211 being used for bridge trans-
ducer measurements, temperature measurement, and 4-20mA
receiver applications.
1/2 OPA1013
AVDD
AGND
A
INP
REFIN
REFOUT
AVDD
3kΩ
AIN
N
1.0µF
AGND
AGND
VBIAS
CS
MODE
DRDY
SDOUT
SDIO
AGND
AGND
DVDD
XTAL
ADS1210
C1
DSYNC
XIN
12pF
XOUT
DGND
SCLK
DVDD
DVDD
C2
DGND
12pF
DGND
FIGURE 37. Bridge Transducer Interface with Voltage Excitation.
R1
6kΩ
+In
3
5
10kΩ
1
8
RG
A
INP
REFIN
INA118
6
1.0µF
AGND
AIN
N
REFOUT
AVDD
2
–In
AGND
VBIAS
CS
AVDD
MODE
DRDY
SDOUT
SDIO
AGND
DVDD
ADS1210
8
6
5
7
DGND
C1
12pF
DSYNC
XIN
REF200
100µA
100µA
I
O
XTAL
XOUT
DGND
SCLK
DVDD
A
B
C
DVDD
C2
12pF
DGND
1
2
3
4
DGND
AGND
FIGURE 38. Bridge Transducer Interface with Current Excitation.
ADS1210, ADS1211
36
SBAS034B
www.ti.com
REF200
100µA
A
100µA
B
3
+In
RG
7
5
1
8
AIN
P
REFIN
REFOUT
AVDD
INA118
6
1.0µF
AGND
R1
R2
AINN
100Ω
100Ω
4
2
–In
AGND
VBIAS
CS
AVDD
MODE
DRDY
SDOUT
SDIO
AGND
AGND
DVDD
XTAL
R3
14kΩ
ADS1210
C1
12pF
DGND
DSYNC
XIN
AGND
XOUT
DGND
SCLK
DVDD
DVDD
C2
12pF
DGND
DGND
FIGURE 39. PT100 Interface.
+15V
+In
4–20mA
15
3
CT
14
A
INP
REFIN
RCV420
2
1
1.0µF
13
–In
AIN
N
REFOUT
AVDD
5
AGND
VBIAS
CS
AVDD
AGND
MODE
DRDY
SDOUT
SDIO
AGND
–15V
DVDD
ADS1210
C1
12pF
DGND
DSYNC
XIN
XTAL
XOUT
DGND
SCLK
DVDD
DVDD
C2
12pF
DGND
DGND
FIGURE 40. Complete 4-20mA Receiver.
3
+In
RG
–In
7
5
1
8
INA128
6
AINP
REFIN
1.0µF
AGND
4
2
A
INN
REFOUT
AVDD
R1
10kΩ
AGND
VBIAS
CS
+5V
AGND
Termination
MODE
DRDY
SDOUT
SDIO
AGND
DVDD
ADS1210
C1
12pF
DGND
DSYNC
XIN
XTAL
XOUT
SCLK
DVDD
DGND
DVDD
C2
12pF
DGND
DGND
FIGURE 41. Single Supply, High-Accuracy Thermocouple.
ADS1210, ADS1211
37
SBAS034B
www.ti.com
3
+In
RG
–In
7
5
1
8
AIN
P
REFIN
REFOUT
AVDD
INA128
6
1.0µF
AGND
AINN
4
2
AGND
VBIAS
CS
+5V
AGND
DVDD
R1
10kΩ
MODE
DRDY
SDOUT
SDIO
–5V
ADS1210
C1
DGND
DSYNC
XIN
12pF
AGND
XTAL
XOUT
DGND
SCLK
DVDD
DVDD
C2
12pF
DGND
DGND
FIGURE 42. Dual Supply, High-Accuracy Thermocouple.
3
+In
RG
–In
7
A
A
A
A
IN3N
IN2P
IN2N
IN1P
AIN3P
AGND
5
1
8
A
IN4N
IN4P
REFIN
INA118
4
6
A
2
AGND
R1
10kΩ
1.0µF
AGND
AGND
AIN1N
AGND
VBIAS
CS
REFOUT
AVDD
+5V
ADS1211U, P
AGND
MODE
DRDY
SDOUT
SDIO
1N4148
R2
13kΩ
AGND
DVDD
DGND
C1
12pF
DSYNC
XIN
XTAL
XOUT
SCLK
DVDD
DGND
DVDD
C2
12pF
DGND
DGND
FIGURE 43. Single Supply, High-Accuracy Thermocouple Interface with Cold Junction Compensation.
ADS1210, ADS1211
38
SBAS034B
www.ti.com
3
+In
RG
–In
7
AIN3N
AIN3P
IN4N
IN4P
5
1
8
AIN2P
AIN2N
AIN1P
AIN1N
A
INA118
6
A
4
2
AGND
R1
REFIN
REFOUT
AVDD
1.0µF
AGND
10kΩ
–5V
AGND
+5V
AGND
VBIAS
CS
ADS1211U, P
AGND
MODE
DRDY
SDOUT
SDIO
1N4148
R2
13kΩ
AGND
DVDD
DGND
C1
12pF
DSYNC
XIN
XTAL
XOUT
DGND
SCLK
DVDD
DVDD
C2
12pF
DGND
DGND
FIGURE 44. Dual Supply, High-Accuracy Thermocouple Interface with Cold Junction Compensation.
R1
6kΩ
–In
+In
A
INP
REFIN
REFOUT
AVDD
10kΩ
1.0µF
AGND
AIN
N
AGND
VBIAS
CS
AVDD
MODE
DRDY
SDOUT
SDIO
AVDD
6
AGND
DVDD
ADS1210
8
5
7
C1
12pF
DSYNC
XIN
REF200
100µA
100µA
I
O
XTAL
XOUT
DGND
SCLK
A
B
C
DVDD
DVDD
C2
12pF
DGND
1
2
3
4
DGND
AGND
FIGURE 45. Low-Cost Bridge Transducer Interface with Current Excitation.
ADS1210, ADS1211
39
SBAS034B
www.ti.com
TOPIC INDEX
TOPIC
PAGE
TOPIC
PAGE
FEATURES ..................................................................................... 1
APPLICATIONS ............................................................................. 1
DESCRIPTION ............................................................................... 1
SPECIFICATIONS .......................................................................... 2
ABSOLUTE MAXIMUM RATINGS ............................................................. 3
ELECTROSTATIC DISCHARGE SENSITIVITY ........................................ 3
PACKAGE INFORMATION ........................................................................ 3
ORDERING INFORMATION ...................................................................... 3
ADS1210 SIMPLIFIED BLOCK DIAGRAM ................................................ 4
ADS1210 PIN CONFIGURATION .............................................................. 4
ADS1210 PIN DEFINITIONS ..................................................................... 4
ADS1211 SIMPLIFIED BLOCK DIAGRAM ................................................ 5
ADS1211P and ADS1211U PIN CONFIGURATION ................................. 5
ADS1211P and ADS1211U PIN DEFINITIONS ........................................ 5
ADS1211E PIN CONFIGURATION ........................................................... 6
ADS1211E PIN DEFINITIONS ................................................................... 6
TYPICAL PERFORMANCE CURVES ........................................... 7
THEORY OF OPERATION ............................................................ 9
DEFINITION OF TERMS ......................................................................... 10
DIGITAL FILTER ...................................................................................... 11
Filter Equation ....................................................................................... 12
Filter Settling.......................................................................................... 12
TURBO MODE ......................................................................................... 12
PROGRAMMABLE GAIN AMPLIFIER ..................................................... 13
SOFTWARE GAIN ................................................................................... 13
CALIBRATION .......................................................................................... 13
Self-Calibration ...................................................................................... 14
System Offset Calibration ..................................................................... 14
System Full-Scale Calibration ............................................................... 14
Pseudo System Calibration ................................................................... 15
Background Calibration ......................................................................... 15
System Calibration Offset and Full-Scale Calibration Limits ................ 16
SLEEP MODE .......................................................................................... 16
ANALOG OPERATION .................................................................17
ANALOG INPUT ....................................................................................... 17
REFERENCE INPUT ................................................................................ 17
REFERENCE OUTPUT ............................................................................ 17
VBIAS ..................................................................................................................................................... 18
DIGITAL OPERATION ..................................................................18
SYSTEM CONFIGURATION .................................................................... 18
Instruction Register (INSR) ................................................................... 19
Command Register (CMR) .................................................................... 19
Data Output Register (DOR) ................................................................. 21
Offset Calibration Register (OCR) ........................................................ 22
Full-Scale Calibration Register (FCR)................................................... 22
TIMING ..................................................................................................... 22
Synchronizing Multiple Converters ........................................................ 26
SERIAL INTERFACE ............................................................................... 26
Multiple Instructions ............................................................................... 26
Using CS and Continuous Read Mode ................................................ 29
Power-On Conditions for SDIO ............................................................. 29
Master Mode.......................................................................................... 29
Slave Mode............................................................................................ 29
Making Use of DSYNC ......................................................................... 30
Reset, Power-On Reset, and Brown-Out ............................................. 30
Two-Wire Interface ................................................................................ 30
Three-Wire Interface.............................................................................. 30
Four-Wire Interface................................................................................ 30
Multi-Wire Interface ............................................................................... 32
I/O Recovery.......................................................................................... 32
Isolation ................................................................................................. 33
Synchronization of Multiple Converters ................................................ 34
LAYOUT ........................................................................................35
POWER SUPPLIES ................................................................................. 35
GROUNDING............................................................................................ 35
DECOUPLING .......................................................................................... 35
SYSTEM CONSIDERATIONS ................................................................. 35
APPLICATIONS ............................................................................36
ADS1210, ADS1211
40
SBAS034B
www.ti.com
FIGURE INDEX
TABLE INDEX
FIGURE TITLE
PAGE
TABLE
TITLE
PAGE
Figure 1
Figure 2
Figure 3
Figure 4
Normalized Digital Filter Response ......................................... 11
Digital Filter Response at a Data Rate of 50Hz ..................... 11
Digital Filter Response at a Data Rate of 60Hz ..................... 11
Table I
Full-Scale Range vs PGA Setting ............................................. 9
Available PGA Settings vs Turbo Mode Rate .......................... 9
Effective Resolution vs Data Rate and Gain Setting ............. 10
Effective Resolution cs Data Rate and Turbo Mode Rate ..... 12
Noise Level vs Data Rate and Turbo Mode Rate .................. 12
Table II
Table III
Table IV
Table V
Table VI
Asynchronous ADS1210/11 Analog Input Voltage Step or
ADS1211 Channel Change to Fully Settled Output Data ...... 12
Self-Calibration Timing ............................................................ 14
Figure 5
Figure 6
Figure 7
Figure 8
Figure 9
Effective Resolution vs Data Rate, Clock Frequency, and
System Offset Calibration Timing ........................................... 14
System Full-Scale Calibration ................................................. 14
Pseudo System Calibration Timing ......................................... 15
Background Calibration ........................................................... 15
Turbo Mode Rate .................................................................... 12
Table VII ADS1210/11 Registers ............................................................ 18
Table VIII Instruction Register .................................................................. 19
Table IX
Table X
Table XI
A3-A0 Addressing .................................................................... 19
Organization of the Command Register and Default Status .. 19
Decimation Ratios vs Data Rates ........................................... 21
Figure 10 Sleep Mode to Normal Mode Timing ...................................... 17
Figure 11 Analog Input Structure............................................................. 17
Figure 12 ±10V Input Configuration Using VBIAS .................................................... 18
Figure 13 XIN Clock Timing ...................................................................... 22
Figure 14 Serial Input/Output Timing, Master Mode ............................... 22
Figure 15 Serial Input/Output Timing, Slave Mode ................................. 22
Figure 16 Serial Interface Timing (CS LOW), Master Mode................... 24
Figure 17 Serial Interface Timing (CS LOW), Slave Mode..................... 24
Figure 18 Serial Interface Timing (Using CS), Master Mode.................. 24
Figure 19 Serial Interface Timing (Using CS), Slave Mode.................... 25
Figure 20 SDIO Input to Output Transition Timing ................................. 25
Figure 21 DRDY Rise and Fall Time....................................................... 25
Table XII Data Output Register............................................................... 21
Table XIII Offset Calibration Register ...................................................... 22
Table XIV Full-Scale Calibration Register ................................................ 22
Table XV Digital Timing Characteristics .................................................. 23
Figure 22 DSYNC to XIN Timing for Synchronizing Multiple
ADS1210/11s ........................................................................... 26
Figure 23 Exactly Synchronizing Multiple ADS1210/11s
to Asynchronous DSYNC Signal ............................................. 26
Figure 24 Timing of Data Output Register Update ................................. 26
Figure 25 Flowchart for Writing and Reading Register Data, Master Mode 27
Figure 26 Flowchart for Writing and Reading Register Data, Slave Mode .. 28
Figure 27 Resetting the ADS1210/11 (Slave Mode Only) ...................... 30
Figure 28 Three-Wire Interface with an 8xC32 Microprocessor ............. 31
Figure 29 Three-Wire Interface with an 8xC51 Microprocessor ............. 31
Figure 30 Four-Wire Interface with an 8xC32 Microprocessor ............... 32
Figure 31 Full Interface with an 8xC51 Microprocessor ......................... 32
Figure 32 Full Interface with a 68HC11 Microprocessor ........................ 33
Figure 33 Isolated Four-Wire Interface .................................................... 33
Figure 34 Source Current vs VOH for SDOUT Under
Worst-Case Conditions ............................................................ 34
Figure 35 Sink Current vs VOL for SDOUT Under
Worst-Case Conditions ............................................................ 34
Figure 36 Effect of Synchronization on Output Data Timing .................. 34
Figure 37 Bridge Transducer Interface with Voltage Excitation .............. 36
Figure 38 Bridge Transducer Interface with Current Excitation .............. 36
Figure 39 PT100 Interface ....................................................................... 37
Figure 40 Complete 4-20mA Receiver .................................................... 37
Figure 41 Single Supply, High-Accuracy Thermocouple ......................... 37
Figure 42 Dual Supply, High-Accuracy Thermocouple ........................... 38
Figure 43 Single Supply, High-Accuracy Thermocouple Interface
with Cold Junction Compensation ........................................... 38
Figure 44 Dual Supply, High-Accuracy Thermocouple Interface
with Cold Junction Compensation ........................................... 39
Figure 45 Low-Cost Bridge Transducer Interface with Current Excitation ..... 39
ADS1210, ADS1211
41
SBAS034B
www.ti.com
PACKAGE OPTION ADDENDUM
www.ti.com
10-Jun-2014
PACKAGING INFORMATION
Orderable Device
ADS1210P
Status Package Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
NRND
PDIP
PDIP
SOP
N
18
18
18
18
18
18
28
28
28
28
24
24
24
24
24
20
Green (RoHS
& no Sb/Br)
Call TI
N / A for Pkg Type
ADS1210P
ADS1210PG4
ADS1210U
NRND
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
NRND
N
20
40
Green (RoHS
& no Sb/Br)
Call TI
N / A for Pkg Type
ADS1210P
DTC
DTC
DTC
DTC
DB
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
N / A for Pkg Type
-40 to 85
ADS
1210U
ADS1210U/1K
ADS1210U/1KG4
ADS1210UG4
ADS1211E
SOP
1000
1000
40
Green (RoHS
& no Sb/Br)
ADS
1210U
SOP
Green (RoHS
& no Sb/Br)
-40 to 85
-40 to 85
ADS
1210U
SOP
Green (RoHS
& no Sb/Br)
ADS
1210U
SSOP
SSOP
SSOP
SSOP
PDIP
PDIP
SOIC
SOIC
SOIC
50
Green (RoHS
& no Sb/Br)
ADS1211E
ADS1211E
ADS1211E
ADS1211E
ADS1211P
ADS1211P
ADS1211U
ADS1211U
ADS1211U
ADS1211E/1K
ADS1211E/1KG4
ADS1211EG4
ADS1211P
DB
1000
1000
50
Green (RoHS
& no Sb/Br)
DB
Green (RoHS
& no Sb/Br)
DB
Green (RoHS
& no Sb/Br)
NT
15
Green (RoHS
& no Sb/Br)
ADS1211PG4
ADS1211U
NRND
NT
15
Green (RoHS
& no Sb/Br)
N / A for Pkg Type
ACTIVE
ACTIVE
ACTIVE
DW
DW
DW
25
Green (RoHS
& no Sb/Br)
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 85
-40 to 85
-40 to 85
ADS1211U/1K
ADS1211UG4
1000
25
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Jun-2014
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Jul-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
ADS1210U/1K
ADS1211E/1K
ADS1211U/1K
SOP
SSOP
SOIC
DTC
DB
18
28
24
1000
1000
1000
330.0
330.0
330.0
24.4
16.4
24.4
10.9
8.1
12.0
10.4
2.7
2.5
2.7
12.0
12.0
12.0
24.0
16.0
24.0
Q1
Q1
Q1
DW
10.75 15.7
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Jul-2013
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
ADS1210U/1K
ADS1211E/1K
ADS1211U/1K
SOP
SSOP
SOIC
DTC
DB
18
28
24
1000
1000
1000
367.0
367.0
367.0
367.0
367.0
367.0
45.0
38.0
45.0
DW
Pack Materials-Page 2
MECHANICAL DATA
MPDS095 – APRIL 2001
DTC (R-PDSO-G18)
PLASTIC SMALL-OUTLINE
C
0.4625 (11,75)
0.4469 (11,35)
–A–
18
0°–8°
10
0.050 (1,27)
0.016 (0,40)
D
–B–
0.2992 (7,60)
0.2914 (7,40)
0.419 (10,65)
0.394 (10,00)
M
M
0.010 (0,25)
B
Index
1
9
Area
E
E
0.0118 (0,30)
0.004 (0,10)
0.029 (0,75)
0.010 (0,25)
0.050 (1,27)
x 45°
0.1043 (2,65)
0.0926 (2,35)
Base
Plane
–C–
Seating
Plane
0.0125 (0,32)
0.0091 (0,23)
0.020 (0,51)
0.013 (0,33)
0.010 (0,25) C A
0.004 (0,10)
M
M
S
B
4202498/A 03/01
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body length dimension does not include mold flash,
protrusions or gate burrs. Mold flash, protrusions and
gate burrs shall not exceed 0.006 (0,15) per side.
D. Body width dimension does not include inter-lead
flash or protrusions. Inter-lead flash and protrusions
shall not exceed 0.010 (0,25) per side.
E. The chamfer on the body is optional. If it is not
present, a visual index feature must be located within
the cross-hatched area.
F. Falls within JEDEC MS-013-AB.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
M
0,15
15
0,25
0,09
5,60
5,00
8,20
7,40
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
0,10
2,00 MAX
0,05 MIN
PINS **
14
16
20
24
28
30
38
DIM
6,50
5,90
6,50
5,90
7,50
8,50
7,90
10,50
9,90
10,50 12,90
A MAX
A MIN
6,90
9,90
12,30
4040065 /E 12/01
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
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changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
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TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
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Applications
Audio
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相关型号：
ADS1210U/1K
ADC, Delta-Sigma, 24-Bit, 1 Func, 4 Channel, Serial Access, PDSO18, GREEN, PLASTIC, SOP-18
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