ADS1231_14 [TI]
24-Bit Analog-to-Digital Converter for Bridge Sensors;
| 型号： | ADS1231_14 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 24-Bit Analog-to-Digital Converter for Bridge Sensors |
| 文件： | 总22页 (文件大小：477K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ADS1231
www.ti.com
SBAS414C –JULY 2009–REVISED DECEMBER 2010
24-Bit Analog-to-Digital Converter
for Bridge Sensors
1
FEATURES
DESCRIPTION
2
•
•
•
•
•
•
•
Complete Front-End for Bridge Sensors
Internal Amplifier, Gain of 128
Internal Oscillator
The ADS1231 is a precision, 24-bit analog-to-digital
converter (ADC). With an onboard low-noise
amplifier, onboard oscillator, precision third-order
24-bit delta-sigma (ΔΣ) modulator, and bridge power
switch, the ADS1231 provides a complete front-end
solution for bridge sensor applications including
weigh scales, strain gauges, and load cells.
Low-Side Power Switch for Bridge Sensor
Low Noise: 35nVrms
Selectable Data Rates: 10SPS or 80SPS
The low-noise amplifier has a gain of 128, supporting
a full-scale differential input of ±19.5mV. The ΔΣ ADC
has 24-bit resolution and is comprised of a third-order
modulator and fourth-order digital filter. Two data
rates are supported: 10SPS (with both 50Hz and
60Hz rejection) and 80SPS. The ADS1231 can be
put in a low-power standby mode or shut off
completely in power-down mode.
Simultaneous 50Hz and 60Hz Rejection at
10SPS
•
•
Input EMI Filter
External Voltage Reference up to 5V for
Ratiometric Measurements
•
•
•
•
•
Simple, Pin-Driven Control
Two-Wire Serial Digital Interface
Supply Range: 3V to 5.3V
Package: SOIC-16
The ADS1231 is controlled by dedicated pins; there
are no digital registers to program. Data are output
over an easily-isolated serial interface that connects
directly to the MSP430 and other microcontrollers.
Temperature Range: –40°C to +85°C
The ADS1231 is available in an SO-16 package and
is specified from –40°C to +85°C.
APPLICATIONS
•
•
•
•
Weigh Scales
Strain Gauges
Load Cells
Industrial Process Control
CAP CAP VREFP
VREFN DVDD
AVDD
PDWN
AINP
AINN
DRDY/DOUT
SCLK
24-Bit
EMI
G = 128
DS ADC
Filter
SPEED
Internal
Oscillator
SW
GND
CLKIN
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2009–2010, Texas Instruments Incorporated
ADS1231
SBAS414C –JULY 2009–REVISED DECEMBER 2010
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION
For the most current package and ordering information, see the Package Option Addendum at the end of this
document, or visit the device product folder at www.ti.com.
ABSOLUTE MAXIMUM RATINGS(1)
Over operating free-air temperature range, unless otherwise noted.
ADS1231
–0.3 to +6
UNIT
V
AVDD to GND
DVDD to GND
–0.3 to +6
V
100, momentary
10, continuous
–0.3 to AVDD + 0.3
–0.3 to DVDD + 0.3
mA
mA
V
Input current
Analog input voltage to GND
Digital input voltage to GND
V
Human body model (HBM)
JEDEC standard 22, test method A114-C.01, all pins
±2000
±500
V
V
ESD(2)
Charged device model (CDM)
JEDEC standard 22, test method C101, all pins
Maximum junction temperature
Operating temperature range
Storage temperature range
+150
°C
°C
°C
–40 to +85
–60 to +150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) CAUTION: ESD sensitive device. Precaution should be used when handling the device in order to prevent permanent damage.
THERMAL INFORMATION
ADS1231
THERMAL METRIC(1)
SOIC (D)
16 PINS
79.5
UNITS
qJA
Junction-to-ambient thermal resistance
qJCtop
qJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
37.5
37.1
°C/W
yJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
5.6
yJB
36.7
qJCbot
n/a
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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ADS1231
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SBAS414C –JULY 2009–REVISED DECEMBER 2010
ELECTRICAL CHARACTERISTICS
Minimum/maximum limit specifications apply from –40°C to +85°C. Typical specifications at +25°C.
All specifications at AVDD = DVDD = VREFP = +5V, VCM = 2.5V and VREFN = GND, unless otherwise noted.
ADS1231
PARAMETER
ANALOG INPUTS
CONDITIONS
MIN
TYP
MAX
UNIT
±0.5VREF/128
±19.5
V
Full-scale input voltage (AINP – AINN)
VREF = AVDD = 5V
VREF = AVDD = 3V
mV
mV
V
±11.7
Common-mode input range
Differential input current
GND + 1.5
AVDD – 1.5
±2
nA
LOW-SIDE POWER SWITCH
AVDD = 5V, ISW = 30mA
AVDD = 3V, ISW = 30mA
3.5
4
5
7
Ω
Ω
On-resistance (RON
)
Current through switch
SYSTEM PERFORMANCE
Resolution
30
mA
No missing codes
Internal oscillator, SPEED = high
Internal oscillator, SPEED = low
External oscillator, SPEED = high
External oscillator, SPEED = low
Full settling
24
Bits
SPS
80
10
SPS
Data rate
fCLK/61, 440
SPS
fCLK/491, 520
SPS
Digital filter settling time
Integral nonlinearity (INL)
Input offset error
Input offset drift
Gain error
4
±8
10
±20
1
Conversions
ppm
Differential input, end-point fit
mV
nV/°C
%
Gain drift
±2
ppm/°C
fIN = 50Hz or 60Hz ±1Hz, fDATA = 10SPS,
internal oscillator
80
90
100
110
dB
dB
Normal-mode rejection(1)
Common-mode rejection
fIN = 50Hz or 60Hz ±1Hz, fDATA = 10SPS,
external oscillator(2)
At dc
110
35
dB
fDATA = 10SPS, AVDD = VREF = 5V
fDATA = 80SPS, AVDD = VREF = 5V
fDATA = 10SPS, AVDD = VREF = 5V
fDATA = 80SPS, AVDD = VREF = 5V
At dc
nV, rms
nV, rms
nV, P-P
nV, P-P
dB
102
232
622
100
Noise
Power-supply rejection
90
VOLTAGE REFERENCE INPUT
Voltage reference input (VREF
)
VREF = VREFP – VREFN
1.5
AVDD
10
AVDD + 0.1
VREFP – 1.5
AVDD + 0.1
V
V
Negative reference input (VREFN)
Positive reference input (VREFP)
Voltage reference input current
DIGITAL INPUT/OUTPUT (DVDD = 3V to 5.3V)
VIH
AGND – 0.1
VREFN + 1.5
V
nA
0.8 DVDD
GND
DVDD + 0.1
0.2 DVDD
V
V
VIL
Logic levels
VOH
IOH = 500mA
IOL = 500mA
DVDD – 0.4
V
VOL
0.2 DVDD
V
Input leakage
0 < VDIGITAL INPUT < DVDD
±10
5
mA
MHz
Serial clock input frequency (fSCLK
)
(1) Specification is assured by the combination of design and final test.
(2) External oscillator = 4.9152MHz.
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SBAS414C –JULY 2009–REVISED DECEMBER 2010
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ELECTRICAL CHARACTERISTICS (continued)
Minimum/maximum limit specifications apply from –40°C to +85°C. Typical specifications at +25°C.
All specifications at AVDD = DVDD = VREFP = +5V, VCM = 2.5V and VREFN = GND, unless otherwise noted.
ADS1231
PARAMETER
POWER SUPPLY
CONDITIONS
MIN
TYP
MAX
UNIT
Power-supply voltage (AVDD, DVDD)
3
5.3
V
mA
mA
mA
mA
mA
mA
mA
mA
mA
mW
mW
Normal mode, AVDD = 3V
Normal mode, AVDD = 5V
Standby mode
900
900
0.1
0.1
60
Analog supply current
Power-down
Normal mode, DVDD = 3V
Normal mode, DVDD = 5V
Standby mode, SCLK = high, DVDD = 3V
Standby mode, SCLK = high, DVDD = 5V
Power-down
95
Digital supply current
45
65
0.2
2.9
5
Normal mode, AVDD = DVDD = 3V
Normal mode, AVDD = DVDD = 5V
Power dissipation, total
TEMPERATURE
Operating temperature range
Specified temperature range
–40
–40
+85
+85
°C
°C
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ADS1231
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SBAS414C –JULY 2009–REVISED DECEMBER 2010
PIN CONFIGURATION
D PACKAGE
SO-16
(TOP VIEW)
DVDD
GND
1
2
3
4
5
6
7
8
16 DRDY/DOUT
15 SCLK
14 PDWN
13 AVDD
12 PSW
11 GND
CLKIN
SPEED
CAP
CAP
AINP
10 VREFP
AINN
9
VREFN
PIN DESCRIPTIONS
ANALOG/DIGITAL
INPUT/OUTPUT
NAME
DVDD
GND
TERMINAL
DESCRIPTION
1
2
3
Digital
Supply
Digital power supply
Ground for digital and analog supplies
CLKIN
Digital input
External clock input: typically 4.9152MHz. Tie low to activate internal oscillator.
Data rate select:
SPEED
DATA RATE
10SPS
SPEED
4
Digital input
0
1
80SPS
CAP
5
6
Analog
Analog
Gain amplifier bypass capacitor connection
Gain amplifier bypass capacitor connection
Positive analog input
CAP
AINP
7
Analog input
Analog input
Analog input
Analog input
Supply
AINN
VREFN
VREFP
GND
8
Negative analog input
9
Negative reference input
10
11
12
13
14
Positive reference input
Ground for digital and analog supplies
Low-side power switch
PSW
Analog
AVDD
PDWN
Supply
Analog power supply
Digital input
Power-down: holding this pin low powers down the entire converter and resets the ADC.
Serial clock: clock out data on the rising edge. Also used to initiate Standby mode. See the Standby
Mode section for more details.
SCLK
15
16
Digital input
Dual-purpose output:
Data ready: indicates valid data by going low.
Data output: outputs data, MSB first, on the first rising edge of SCLK.
DRDY/DOUT
Digital output
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ADS1231
SBAS414C –JULY 2009–REVISED DECEMBER 2010
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NOISE PERFORMANCE
The ADS1231 offers outstanding noise performance. Table 1 summarizes the typical noise performance with
inputs shorted externally for different data rates and voltage reference values.
The RMS and Peak-to-Peak noise are referred to the input. The effective number of bits (ENOB) is defined as:
ENOB = ln (FSR/RMS noise)/ln(2)
The Noise-Free Bits are defined as:
Noise-Free Bits = ln (FSR/Peak-to-Peak Noise)/ln(2)
Where:
FSR (Full-Scale Range) = VREF/Gain.
Table 1. Noise Performance
AVDD and VREF
(V)
RMS NOISE(1)
(nV)
PEAK-TO-PEAK NOISE(1)
(nV)
ENOB
(RMS)
DATA RATE
NOISE-FREE BITS
5
3
5
3
35.2
33.5
231.9
199.2
622.1
549.6
20.1
19.4
18.5
18.2
17.4
16.8
15.9
15.4
10
102.1
80.3
80
(1) Noise specifications are based on direct measurement of 1024 consecutive samples.
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ADS1231
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SBAS414C –JULY 2009–REVISED DECEMBER 2010
TYPICAL CHARACTERISTICS
At TA = +25°C, AVDD = DVDD = REFP = 5V, REFN = AGND, and VCM = 2.5V unless otherwise noted.
NOISE vs TIME
NOISE vs TIME
300
250
200
150
100
50
300
250
200
150
100
50
Data Rate = 10SPS
Data Rate = 80SPS
0
0
−50
−100
−150
−200
−250
−300
−50
−100
−150
−200
−250
−300
0
200
400
600
800
1000
0
200
400
600
800
1000
Time (Reading Number)
Time (Reading Number)
Figure 1.
Figure 2.
NOISE HISTOGRAM
NOISE HISTOGRAM
500
450
400
350
300
250
200
150
100
50
250
225
200
175
150
125
100
75
Data Rate = 10SPS
Data Rate = 80SPS
50
25
0
0
−40−35−30−25−20−15−10 −5
0
5
10 15 20 25 30 35 40
−40−35−30−25−20−15−10 −5
0
5 10 15 20 25 30 35 40
24−bit LSBs
24−bit LSBs
Figure 3.
Figure 4.
NOISE vs SIGNAL
NOISE vs SIGNAL
150
125
100
75
150
125
100
75
Data Rate = 10SPS
Data Rate = 80SPS
50
50
25
25
0
−20
0
−20
−15
−10
−5
0
5
10
15
20
−15
−10
−5
0
5
10
15
20
Input Voltage (mV)
Input Voltage (mV)
Figure 5.
Figure 6.
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ADS1231
SBAS414C –JULY 2009–REVISED DECEMBER 2010
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TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, AVDD = DVDD = REFP = 5V, REFN = AGND, and VCM = 2.5V unless otherwise noted.
OFFSET DRIFT vs TEMPERATURE
GAIN ERROR vs TEMPERATURE
2000
1500
1000
500
0.02
0.015
0.01
0.005
0
0
-500
-1000
-1500
-2000
-0.005
-0.01
-0.015
-0.02
-40 -27.5 -15 -2.5 10 22.5 35 47.5 60 72.5 85
Temperature (°C)
-40 -27.5 -15 -2.5 10 22.5 35 47.5 60 72.5 85
Temperature (°C)
Figure 7.
Figure 8.
INL vs INPUT SIGNAL
DATA RATE vs TEMPERATURE
3
2
10.2
10.15
10.1
10.05
10
-20°C
-40°C
+25°C
+70°C
Data Rate = 10SPS
1
0
-1
-2
-3
-4
-5
-6
-7
9.95
9.9
9.85
-20
-15
-10
-5
0
5
10
15
20
9.8
−40 −27.5 −15 −2.5 10 22.5 35 47.5 60 72.5 85
Temperature (°C)
VIN (mV)
Figure 9.
Figure 10.
ANALOG CURRENT vs TEMPERATURE
DIGITAL CURRENT vs TEMPERATURE
1200
1000
800
600
400
200
0
120
115
110
105
100
95
90
85
80
-40 -27.5 -15 -2.5 10 22.5 35 47.5 60 72.5 85
Temperature (°C)
-40 -27.5 -15 -2.5 10 22.5 35 47.5 60 72.5 85
Temperature (°C)
Figure 11.
Figure 12.
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ADS1231
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SBAS414C –JULY 2009–REVISED DECEMBER 2010
OVERVIEW
The ADS1231 is a precision, 24-bit ADC that includes
low-noise PGA, internal oscillator, third-order
CAP
a
delta-sigma (ΔΣ) modulator, and fourth-order digital
filter. The ADS1231 provides a complete front-end
solution for bridge sensor applications such as weigh
scales, strain gauges, and pressure sensors.
EMI
RINT
AINP
Filter
A1
R
F1
Gain = 1
Data can be output at 10SPS for excellent 50Hz and
60Hz rejection, or at 80SPS when higher speeds are
needed. The ADS1231 is easy to configure, and all
digital control is accomplished through dedicated
pins; there are no registers to program. A simple
two-wire serial interface retrieves the data.
R1
A3
ADC
RF2
RINT
A2
EMI
AINN
Filter
ANALOG INPUTS (AINP, AINN)
The input signal to be measured is applied to the
input pins AINP and AINN. The ADS1231 accepts
differential input signals, but can also measure
unipolar signals.
CAP
Figure 13. Simplified Diagram of the Amplifier
External Capacitor
LOW-NOISE AMPLIFIER
The ADS1231 features a low-drift, low-noise amplifier
that provides a complete front-end solution for bridge
sensors. A simplified diagram of the amplifier is
shown in Figure 13. It consists of two
chopper-stabilized amplifiers (A1 and A2) and three
accurately matched resistors (R1, RF1, and RF2) that
construct a differential front-end stage with a gain of
128, followed by gain stage A3 (Gain = 1). The inputs
are equipped with an EMI filter, as shown in
Figure 13. The cutoff frequency of the EMI filter is
20MHz. By using AVDD as the reference input, the
bipolar input ranges from –19.5mV to +19.5mV. The
inputs of the ADS1231 are protected with internal
diodes connected to the power-supply rails. These
diodes clamp the applied signal to prevent it from
damaging the input circuitry.
An external capacitor (CEXT) across the two ADS1231
CAP pins combines with the internal resistor RINT
(on-chip) to create
a
low-pass filter. The
recommended value for CEXT is 0.1mF which provides
a corner frequency of 720Hz. This low-pass filter
serves two purposes. First, the input signal is
bandlimited to prevent aliasing by the ADC and to
filter out the high-frequency noise. Second, it
attenuates the chopping residue from the amplifier to
improve temperature drift performance. NPO or C0G
capacitors
are
recommended.
For
optimal
performance, place the external capacitor very close
to the CAP pins.
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VOLTAGE REFERENCE INPUTS
(VREFP, VREFN)
LOW-SIDE POWER SWITCH (SW)
The ADS1231 incorporates an internal switch for use
with an external bridge sensor, as shown in
Figure 15. The switch can be used in a return path for
the bridge power. By opening the switch, power
dissipation in the bridge is eliminated.
The voltage reference used by the modulator is
generated from the voltage difference between
VREFP and VREFN: VREF = VREFP – VREFN. The
reference inputs use a structure similar to that of the
analog inputs. In order to increase the reference input
impedance, switching buffer circuitry is used to
reduce the input equivalent capacitance. The
reference drift and noise impact ADC performance. In
order to achieve best results, pay close attention to
The switch is controlled by the ADS1231 conversion
status. During normal conversions, the switch is
closed (the SW pin is connected to GND). During
standby or power-down modes, the switch is opened
(the SW pin is high impedance). When using the
switch, it is recommended that the negative reference
input (VREFN) be connected directly to the bridge
ground terminal, as shown in Figure 15 for best
performance.
the reference noise and drift specifications.
A
simplified diagram of the circuitry on the reference
inputs is shown in Figure 14. The switches and
capacitors can be modeled approximately using an
effective impedance of:
ZEFF = 500MW
+VDD
VREFP
VREFN
ADS1231
VREFP
Bridge
AVDD
AVDD
AINP
Sensor
ESD
Protection
AINN
CBUF
ZEFF = 500MW
VREFN
SW
GND
Figure 14. Simplified Reference Input Circuitry
ESD diodes protect the reference inputs. To prevent
these diodes from turning on, make sure the voltages
on the reference pins do not go below GND by more
than 100mV, and likewise, do not exceed AVDD by
100mV:
Figure 15. Low-Side Power Switch
CLOCK SOURCE
GND – 100mV < (VREFP or VREFN) < AVDD +
100mV
The ADS1231 uses an internal oscillator. No external
clock circuitry is required.
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SBAS414C –JULY 2009–REVISED DECEMBER 2010
FREQUENCY RESPONSE
0
Data Rate = 10SPS
The ADS1231 uses a sinc4 digital filter with the
frequency response. The frequency response repeats
at multiples of the modulator sampling frequency of
76.8kHz. The overall response is that of a low-pass
filter with a –3dB cutoff frequency of 3.32Hz with the
SPEED pin tied low (10SPS data rate) and 11.64Hz
with the SPEED pin tied high (80SPS data rate).
-50
-100
-150
To help see the response at lower frequencies,
Figure 16(a) illustrates the nominal response out to
100Hz, when the data rate = 10SPS. Notice that
signals at multiples of 10Hz are rejected, and
therefore simultaneous rejection of 50Hz and 60Hz is
achieved.
0
10
20
30
40
50
60
70
80
90 100
Frequency (Hz)
(a)
The benefit of using a sinc4 filter is that every
frequency notch has four zeros on the same location.
This response, combined with the low drift internal
oscillator, provides an excellent normal-mode
rejection of line-cycle interference.
-50
-100
-150
Data Rate = 10SPS
Figure 16(b) zooms in on the 50Hz and 60Hz notches
with the SPEED pin tied low (10SPS data rate).
46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
Frequency (Hz)
(b)
Figure 16. Nominal Frequency Response Out To
100Hz
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Table 2. Data Rate Settings
SETTLING TIME
SPEED PIN
DATA RATE
10SPS
Fast changes in the input signal require time to settle.
For example, an external multiplexer in front of the
ADS1231 can generate abrupt changes in input
voltage by simply switching the multiplexer input
channels. These sorts of changes in the input require
four data conversion cycles to settle. When
continuously converting, five readings may be
necessary in order to settle the data. If the change in
input occurs in the middle of the first conversion, four
more full conversions of the fully-settled input are
required to obtain fully-settled data. Discard the first
0
1
80SPS
DATA FORMAT
The ADS1231 outputs 24 bits of data in binary twos
complement format. The least significant bit (LSB)
has a weight of (0.5VREF/128)(223 – 1). The positive
full-scale input produces an output code of 7FFFFFh
and the negative full-scale input produces an output
code of 800000h. The output clips at these codes for
signals exceeding full-scale. Table 3 summarizes the
ideal output codes for different input signals.
four
readings
because
they
contain
only
partially-settled data. Figure 17 illustrates the settling
time for the ADS1231.
Table 3. Ideal Output Code vs Input Signal
DATA RATE
INPUT SIGNAL VIN
The ADS1231 data rate is set by the SPEED pin, as
shown in Table 2. When SPEED is low, the data rate
is nominally 10SPS. This data rate provides the
lowest noise, and also has excellent rejection of both
50Hz and 60Hz line-cycle interference. For
applications requiring fast data rates, setting SPEED
high selects a data rate of nominally 80SPS.
(AINP – AINN)
≥ +0.5VREF/128
(+0.5VREF/128)/(223 – 1)
0
IDEAL OUTPUT
7FFFFFh
000001h
000000h
(–0.5VREF/128)/(223 – 1)
≤ –0.5VREF/128
FFFFFFh
800000h
1. Excludes effects of noise, INL, offset, and gain
errors.
Abrupt Change in External VIN
VIN
1st Conversion;
2nd Conversion;
VIN settled, but
3rd Conversion;
VIN settled, but
4th Conversion;
VIN settled, but
Conversion
including
VIN settled, but
Start of
Conversion
digital filter
unsettled.
digital filter
unsettled.
digital filter
unsettled.
digital filter
unsettled.
unsettled VIN
.
DRDY/DOUT
Conversion
Time
Figure 17. Settling Time in Continuous Conversion Mode
12
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ADS1231
www.ti.com
SBAS414C –JULY 2009–REVISED DECEMBER 2010
DATA READY/DATA OUTPUT (DRDY/DOUT)
DATA RETRIEVAL
This digital output pin serves two purposes. First, it
indicates when new data are ready by going low.
Afterwards, on the first rising edge of SCLK, the
DRDY/DOUT pin changes function and begins
outputting the conversion data, most significant bit
(MSB) first. Data are shifted out on each subsequent
SCLK rising edge. After all 24 bits have been
retrieved, the pin can be forced high with an
additional SCLK. It then stays high until new data are
ready. This configuration is useful when polling on the
status of DRDY/DOUT to determine when to begin
data retrieval.
The ADS1231 continuously converts the analog input
signal. To retrieve data, wait until DRDY/DOUT goes
low, as shown in Figure 18. After DRDY/DOUT goes
low, begin shifting out the data by applying SCLKs.
Data are shifted out MSB first. It is not required to
shift out all 24 bits of data, but the data must be
retrieved before new data are updated (within tCONV
)
or else the data will be overwritten. Avoid data
retrieval during the update period (tUPDATE). If only 24
SCLKs have been applied, DRDY/DOUT remains at
the state of the last bit shifted out until it is taken high
(see tUPDATE), indicating that new data are being
updated. To avoid having DRDY/DOUT remain in the
state of the last bit, the 25th SCLK can be applied to
force DRDY/DOUT high, as shown in Figure 19. This
technique is useful when a host controlling the device
is polling DRDY/DOUT to determine when data are
ready.
SERIAL CLOCK INPUT (SCLK)
This digital input shifts serial data out with each rising
edge. This input has built-in hysteresis, but care
should still be taken to ensure a clean signal. Glitches
or slow-rising signals can cause unwanted additional
shifting. For this reason, it is best to make sure the
rise and fall times of SCLK are both less than 50ns.
Data
Data Ready
New Data Ready
MSB
23
LSB
0
DRDY/DOUT
22
21
tPD
tHT
tDS
tSCLK
tUPDATE
1
24
SCLK
tSCLK
tCONV
Figure 18. 24-Bit Data Retrieval Timing
SYMBOL
tDS
DESCRIPTION
MIN
TYP
MAX
UNITS
ns
DRDY/DOUT low to first SCLK rising edge
SCLK positive or negative pulse width
0
tSCLK
100
ns
(1)
tPD
SCLK rising edge to new data bit valid: propagation delay
SCLK rising edge to old data bit valid: hold time
Data updating: no readback allowed
50
ns
(1)
tHT
20
ns
tUPDATE
90
ms
SPEED = 1
Conversion time (1/data rate)
SPEED = 0
12.5
100
ms
ms
tCONV
(1) Minimum required from simulation.
Copyright © 2009–2010, Texas Instruments Incorporated
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ADS1231
SBAS414C –JULY 2009–REVISED DECEMBER 2010
www.ti.com
STANDBY MODE
When tSTANDBY has passed with SCLK held high,
Standby mode activates. DRDY/DOUT stays high
when Standby mode begins. SCLK must remain high
to stay in Standby mode. To exit Standby mode
(wakeup), set SCLK low. The first data after exiting
Standby mode are valid.
Standby
mode
dramatically
reduces
power
consumption by shutting down most of the circuitry.
To enter Standby mode, simply hold SCLK high after
DRDY/DOUT goes low; see Figure 20. Standby mode
can be initiated at any time during readback; it is not
necessary to retrieve all 24 bits of data beforehand.
Data
Data Ready
New Data Ready
DRDY/DOUT
SCLK
23
22
21
0
1
24
25
25th SCLK to Force DRDY/DOUT High
Figure 19. Data Retrieval with DRDY/DOUT Forced High Afterwards
Data Ready
Standby Mode
DRDY/DOUT
SCLK
23
22
21
0
23
Start Conversion
1
24
tDSS
tSTANDBY
tS_RDY
Figure 20. Standby Mode Timing (Can be used for single conversions)
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNITS
SCLK high after DRDY/DOUT
goes low to activate Standby
mode
SPEED = 1
SPEED = 0
12.44
ms
(1)
tDSS
99.94
ms
SPEED = 1
SPEED = 0
SPEED = 1
SPEED = 0
12.5
100
ms
ms
ms
ms
tSTANDBY
Standby mode activation time
52.6
Data ready after exiting Standby
mode
(1)
tS_RDY
401.8
(1) Based on an ideal internal oscillator.
14
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Copyright © 2009–2010, Texas Instruments Incorporated
ADS1231
www.ti.com
SBAS414C –JULY 2009–REVISED DECEMBER 2010
POWER-DOWN MODE
AVDD
DVDD
Power-Down mode shuts down the entire ADC
circuitry and reduces the total power consumption
close to zero. To enter Power-Down mode, simply
hold the PDWN pin low. Power-Down mode also
resets the entire circuitry. Power-Down mode can be
initiated at any time during readback; it is not
necessary to retrieve all 24 bits of data beforehand.
Figure 22 shows the wake-up timing from
Power-Down mode.
PDWN
³ 10ms
Figure 21. Power-Up Timing Sequence
Start
Conversion
Data Ready
Power-Down Mode
tPDWN
CLK Source
Wakeup
PDWN
DRDY/DOUT
SCLK
tTS_RDY
tWAKEUP
Figure 22. Wake-Up Timing from Power-Down Mode
SYMBOL
DESCRIPTION
MIN
TYP
UNITS
ms
(1)(2)
tWAKEUP
Wake-up time after Power-Down mode
PDWN pulse width
7.95
(1)
tPDWN
26
ms
(1) Based on an ideal internal oscillator.
(2) Typical required from simulation.
Copyright © 2009–2010, Texas Instruments Incorporated
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ADS1231
SBAS414C –JULY 2009–REVISED DECEMBER 2010
www.ti.com
APPLICATION EXAMPLE
Weigh Scale System
Figure 23 shows a typical ADS1231 application as part of a weigh scale system.
3V to 5.3V
3V
1mF(1)
1mF(1)
12
1
VDD
MSP430x4xx
GND
AVDD
DVDD
10
VREFP
5
CAP
16
15
0.1mF(2)
DRDY/DOUT
SCLK
Load
Cell
6
CAP
14
13
-
+
PDWN
ADS1231
7
8
SPEED
AINP
AINN
9
9
VREFN
SW
GND
2, 3, 11
(1) Place a 0.1mF or higher capacitor as close as possible on both AVDD and DVDD.
(2) Place capacitor very close to the ADS1231 CAP pins for optimal performance.
Figure 23. Weigh Scale Example
16
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Copyright © 2009–2010, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
10-Jan-2011
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
ADS1231ID
ACTIVE
ACTIVE
SOIC
SOIC
D
D
16
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
Request Free Samples
ADS1231IDR
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
Purchase Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
7-Jan-2011
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
ADS1231IDR
SOIC
D
16
2500
330.0
16.4
6.5
10.3
2.1
8.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
7-Jan-2011
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SOIC 16
SPQ
Length (mm) Width (mm) Height (mm)
333.2 345.9 28.6
ADS1231IDR
D
2500
Pack Materials-Page 2
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