ADS1245IDGST [TI]
Low-Power, 24-Bit Analog-to-Digital Converter`;
| 型号： | ADS1245IDGST |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Low-Power, 24-Bit Analog-to-Digital Converter` 光电二极管 转换器 |
| 文件： | 总22页 (文件大小：829K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ADS1245
SBAS287A − JUNE 2003 − REVISED SEPTEMBER 2003
Low-Power, 24-Bit
Analog-to-Digital Converter
FD EATURES
DESCRIPTION
The ADS1245 is a 24-bit, delta-sigma analog-to-digital
converter (ADC). It offers excellent performance and very
low power in an MSOP-10 package and is well suited for
demanding high-resolution measurements, especially in
portable and other space- and power-constrained
systems.
20-Bit Effective Resolution
D
D
D
D
D
D
D
D
D
D
D
D
D
D
High-Impedance Buffered Input
2.5V Differential Input Range
Pin-Compatible with ADS1244
0.0006% INL (typ), 0.0015% INL (max)
Simple Two-Wire Serial Interface
Simultaneous 50Hz and 60Hz Rejection
Single Conversions with Sleep Mode
Single-Cycle Settling
The buffered input presents an impedance of 3GΩ, mini-
mizing measurement errors when using high-impedance
sources. The ADS1245 is compatible with ADS1244 and
offers a direct upgrade path for designs requiring higher in-
put impedance.
A third-order delta-sigma (∆Σ) modulator and digital filter
form the basis of the ADC. The analog modulator has a
2.5V differential input range. The digital filter rejects both
50Hz and 60Hz signals, completely settles in one cycle,
and outputs data at 15 samples per second (SPS).
Self-Calibration
Well Suited for Multi-Channel Systems
Easily Connects to the MSP430
Current Consumption: 158µA
Analog Supply: 2.5V to 5.25V
Digital Supply: 1.8V to 3.6V
A simple, two-wire serial interface provides all the
necessary control. Data retrieval, self-calibration, and
Sleep mode are handled with a few simple waveforms.
When only single conversions are needed, the ADS1245
can be shut down (Sleep mode) while idle between
measurements to dramatically reduce the overall power
dissipation. Multiple ADS1245s can be connected
together to create a synchronously sampling multichannel
measurement system. The ADS1245 is designed to easily
connect to microcontrollers, such as the MSP430.
AD PPLICATIONS
Hand-Held Instrumentation
D
D
D
Portable Medical Equipment
Industrial Process Control
Test and Measurement Systems
The ADS1245 supports 2.5V to 5.25V analog supplies and
1.8V to 3.6V digital supplies. Power is typically less than
470µW in normal operation and less than 1µW during
Sleep mode.
VREFP VREFN
AVDD
DVDD
CLK
DRDY/DOUT
SCLK
AINP
3rd−Order
Modulator
Digital
Filter
Serial
Interface
Buffer
AINN
GND
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
ꢀꢁ ꢂ ꢃꢄ ꢅ ꢆꢇ ꢂꢈ ꢃ ꢉꢆꢉ ꢊꢋ ꢌꢍ ꢎ ꢏꢐ ꢑꢊꢍꢋ ꢊꢒ ꢓꢔ ꢎ ꢎ ꢕꢋꢑ ꢐꢒ ꢍꢌ ꢖꢔꢗ ꢘꢊꢓ ꢐꢑꢊ ꢍꢋ ꢙꢐ ꢑꢕꢚ ꢀꢎ ꢍꢙꢔ ꢓꢑꢒ
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ꢀꢎ ꢍ ꢙꢔꢓ ꢑ ꢊꢍ ꢋ ꢖꢎ ꢍ ꢓ ꢕ ꢒ ꢒ ꢊꢋ ꢟ ꢙꢍ ꢕ ꢒ ꢋꢍꢑ ꢋꢕ ꢓꢕ ꢒꢒ ꢐꢎ ꢊꢘ ꢞ ꢊꢋꢓ ꢘꢔꢙ ꢕ ꢑꢕ ꢒꢑꢊ ꢋꢟ ꢍꢌ ꢐꢘ ꢘ ꢖꢐ ꢎ ꢐꢏ ꢕꢑꢕ ꢎ ꢒꢚ
Copyright 2003, Texas Instruments Incorporated
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SBAS287A − JUNE 2003 − REVISED SEPTEMBER 2003
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ORDERING INFORMATION
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
DESIGNATOR
PACKAGE
MARKING
ORDERING
NUMBER
TRANSPORT
MEDIA, QUANTITY
PRODUCT
PACKAGE−LEAD
(1)
ADS1245IDGST
ADS1245IDGSR
Tape and Reel, 250
Tape and Reel, 2500
ADS1245
MSOP-10
DGS
−40°C to +85°C
BHI
(1)
For the most current specifications and package information, refer to our web site at www.ti.com.
PIN ASSIGNMENTS
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted
(1)
ADS1245
−0.3 to +6
UNIT
DGS PACKAGE
MSOP
(TOP VIEW)
AVDD to GND
V
V
DVDD to GND
−0.3 to +3.6
Input Current
100, momentary
10, continuous
−0.5 to AVDD + 0.5
−0.3 to DVDD + 0.3
−0.3 to DVDD + 0.3
+150
mA
mA
V
ADS1245
Input Current
CLK
GND
VREFP
VREFN
AINN
1
2
3
4
5
10
9
Analog Input Voltage to GND
Analog Input Voltage to GND
Digital Output Voltage to GND
Maximum Junction Temperature
Operating Temperature Range
Storage Temperature Range
Lead Temperature (soldering, 10s)
SCLK
V
V
8
DRDY/DOUT
DVDD
°C
°C
°C
°C
7
−40 to +85
AINP
6
AVDD
−60 to +150
+300
(1)
Stresses above these ratings may cause permanent damage.
Exposure to absolute maximum conditions for extended periods
may degrade device reliability. These are stress ratings only, and
functional operation of the device at these or any other conditions
beyond those specified is not implied.
Terminal Functions
TERMINAL
This integrated circuit can be damaged by ESD. Texas
Instruments recommends that all integrated circuits be
handledwith appropriate precautions. Failure to observe
NAME
NO.
DESCRIPTION
GND
1
2
3
4
5
6
7
8
Analog and digital ground
Positive reference input
Negative reference input
Negative analog input
Positive analog input
proper handling and installation procedures can cause damage.
VREFP
VREFN
AINN
ESD damage can range from subtle performance degradation to
complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could
cause the device not to meet its published specifications.
AINP
AVDD
Analog power supply, 2.5V to 5.25V
Digital power supply, 1.8V to 3.6V
DVDD
DRDY/DOUT
Dual-purpose output:
Data ready: indicates valid data by going low.
Data output: outputs data, MSB first, on the
first rising edge of SCLK.
SCLK
CLK
9
Serial clock input: clocks out data on the
rising edge. Used to initiate calibration and
Sleep mode (see text for more details).
10 System clock input: typically 2.4576MHz
2
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ELECTRICAL CHARACTERISTICS
All specifications at T = −40°C to +85°C, AVDD = +5V, DVDD = +3V, f
= 2.4576MHz, and V
= +1.25V, unless otherwise noted.
A
CLK
REF
PARAMETER
Analog Input
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Full-scale input voltage range
Absolute input range
Differential input impedance
System Performance
Resolution
AINP − AINN
AINP, AINN with respect to GND
= 2.4576MHz
2V
REF
V
V
GND + 0.1
24
AVDD − 1.25
f
3
GΩ
CLK
No missing codes
= 2.4576MHz
Bits
(1)
Data rate
f
15
0.0006
1
SPS
CLK
Differential input signal, end point fit
(2)
Integral nonlinearity (INL)
Offset error
0.0015
14
%FSR
ppm of FSR
(3)
Offset error drift
(4)
Gain error
0.01
0.005
0.5
ppm of FSR/°C
0.1
%
ppm/°C
dB
(3)
Gain error drift
At DC
90
100
100
60
100
(5)
f
f
f
f
= 50 1Hz, f
= 2.4576MHz
= 2.4576MHz
dB
Common-mode rejection
CM
CM
SIG
SIG
CLK
= 60 1Hz, f
(6)
dB
CLK
= 50 1Hz, f
= 2.4576MHz
CLK
= 2.4576MHz
dB
Normal-mode rejection
Input referred noise
= 60 1Hz, f
70
dB
CLK
ppm of FSR,
RMS
2
Analog power-supply rejection
Digital power-supply rejection
Voltage Reference Input
At DC, ∆AVDD = 5%
At DC, ∆AVDD = 5%
100
100
dB
dB
(7)
Reference input voltage (V
)
V
≡ VREFP − VREFN
0.5
1.25
1
AVDD
V
V
REF
REF
Negative reference input (VREFN)
Positive reference input (VREFP)
Voltage reference impedance
Digital Input/Output
GND − 0.1
VREFP − 0.5
AVDD + 0.1
VREFN + 0.5
V
f
= 2.4576MHz
MΩ
CLK
V
V
V
V
(CLK, SCLK)
(CLK, SCLK)
0.8 DVDD
GND
5.25
0.2 DVDD
DVDD
DVDD + 0.4
10
V
V
IH
IL
Logic levels
(DRDY, DOUT)
(DRDY, DOUT)
I
I
= 1mA
= 1mA
DVDD − 0.4
GND
V
OH
OH
V
OL
OL
Input leakage (CLK, SCLK)
0 < (CLK, SCLK) < DVDD
µA
MHz
%
CLK frequency (f
CLK duty cycle
Power Supply
AVDD
)
6
CLK
30
70
2.7
1.8
5.25
3.6
1
V
V
DVDD
Sleep mode
0.1
152
158
0.1
1.6
5
µA
µA
µA
µA
µA
µA
mW
AVDD = 3V
AVDD current
DVDD current
AVDD = 5V
250
Sleep mode, CLK stopped
Sleep mode, 2.4576MHZ CLK running
DVDD = 3V
5
10
Total power dissipation
AVDD = DVDD = 3V
0.47
(1)
(2)
(3)
(4)
SPS = samples per second.
FSR = full-scale range = 4V
REF
Recalibration can reduce these errors to the level of the noise.
.
Achieving specified gain error performance requires that calibration be performed with reference voltage input between (GND + 0.1V) and
(AVDD − 1.25V). See Voltage Reference Inputs section.
(5)
(6)
(7)
f
f
is the frequency of the common-mode input.
is the frequency of the input signal.
CM
SIG
It will not be possible to reach the digital output full-scale code when V > 2V
.
IN REF
3
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TYPICAL CHARACTERISTICS
At T = +25°C, AVDD = +5V, DVDD = +3V, f
CLK
= 2.4576MHz, and V = +1.25V, unless otherwise specified.
REF
A
ANALOG CURRENT vs TEMPERATURE
DIGITAL CURRENT vs TEMPERATURE
12
10
8
220
210
200
190
180
170
160
150
140
130
120
110
100
DVDD = +3V, fCLK = 4.9152MHz
AVDD = +5V, fCLK = 4.9152MHz
6
4
AVDD = +3V, fCLK = 2.4576MHz
2
DVDD = +1.8V, fCLK = 2.4576MHz
15 35 55 75 95
0
−
−
−
5
−
−
−
45
25
45
25
5
15
35
55
75
95
_
_
Temperature ( C)
Temperature ( C)
Figure 1
Figure 2
ANALOG CURRENT vs ANALOG SUPPLY
DIGITAL CURRENT vs DIGITAL SUPPLY
164
162
160
158
156
154
152
150
148
16
14
12
10
8
fCLK = 4.9152MHz
fCLK = 4.9152Hz
6
4
fCLK = 2.4576MHz
fCLK = 2.4576MHz
2
0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
−
45
−
−
5
25
15
35
55
75
95
Analog Supply (V)
Digital Supply (V)
Figure 3
Figure 4
INTEGRAL NONLINEARITY vs ANALOG SUPPLY
VREF = 1.25; fOSC = 2.4576MHz
VCM = 2.4 or ((AVDD− 1.8)/2 + 0.3), whichever is smaller
INTEGRAL NONLINEARITY vs VIN
30
25
20
15
10
5
12.5
10.0
7.5
5.0
2.5
0
_
T = +25 C
_
T = −40 C
_
T = +85 C
−
−
−
2.5
5.0
7.5
_
T = +25 C
−
_
T = 40 C
−
−
10.0
_
T = +85 C
0
12.5
2.5
3.0
3.5
4.0
4.5
5.0
5.5
−
−
−
0.5
2.5
1.5
0.5
1.5
2.5
AVDD
(V)
VIN (V)
Figure 5
Figure 6
4
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TYPICAL CHARACTERISTICS
At T = +25°C, AVDD = +5V, DVDD = +3V, f
CLK
= 2.4576MHz, and V = +1.25V, unless otherwise specified.
REF
A
OFFSET vs TEMPERATURE
GAIN vs TEMPERATURE
5
4
3
2
1
0
1.00006
1.00005
1.00004
1.00003
1.00002
1.00001
1.00000
0.99999
0.99998
0.99997
0.99996
0.99995
0.99994
−
1
2
3
4
5
−
−
−
−
−
−
−
5
45
25
15
35
55
75
95
−
−
−
5
45
25
15
35
55
75
95
_
Temperature ( C)
_
Temperature ( C)
Figure 7
Figure 8
NOISE vs TEMPERATURE
NOISE vs INPUT SIGNAL
3.0
2.5
2.0
1.5
1.0
0.5
3.2
3.0
2.8
2.6
2.4
2.2
2.0
1.8
1.6
1.4
1.2
0
−
−
−
−
−
−
5
45
25
15
35
55
75
95
2.5
1.5
0.5
0.5
1.5
2.5
_
VIN (V)
Temperature ( C)
Figure 9
Figure 10
COMMON−MODE REJECTION RATIO
vs FREQUENCY
HISTOGRAM OF OUTPUT DATA
900
160
140
120
100
80
800
700
600
500
400
300
200
100
0
60
40
20
0
1
10
100
1k
10k
100k
ppm of FSR
Frequency (Hz)
Figure 11
Figure 12
5
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TYPICAL CHARACTERISTICS
At T = +25°C, AVDD = +5V, DVDD = +3V, f
CLK
= 2.4576MHz, and V = +1.25V, unless otherwise specified.
REF
A
DIGITAL POWER−SUPPLY REJECTION RATIO
vs FREQUENCY
ANALOG POWER−SUPPLY REJECTION RATIO
vs FREQUENCY
140
120
100
80
140
120
100
80
60
60
40
40
20
20
0
0
1
10
100
1k
10k
100k
1
10
100
1k
10k
100k
Frequency (Hz)
Frequency (Hz)
Figure 13
Figure 14
6
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The ADS1245 accepts differential input signals, but can
also measure unipolar signals. Note that the analog inputs
(listed in the Electrical Characteristics table as Absolute
Input Range) must remain between GND + 0.1V to
AVDD − 1.25V. Exceeding this range will degrade linearity
and result in performance outside specified limits.
OVERVIEW
The ADS1245 is an ADC comprised of a 3rd-order modulator
followed by a digital filter. The modulator measures the
differential input signal VIN = (AINP – AINN) against the
differential reference VREF = (VREFP – VREFN). Figure 15
shows a conceptual diagram. The differential reference is
scaled internally so that the full-scale input range is 2VREF
.
The digital filter receives the modulator signal and provides
a low-noise digital output. The filter also sets the frequency
response of the converter and provides 50Hz and 60Hz
rejection while settling in a single conversion cycle. A
two-wire serial interface indicates conversion completion and
provides the user with the output data.
VOLTAGE REFERENCE INPUTS
(VREFP, VREFN)
The voltage reference used by the modulator is generated
from the voltage difference between VREFP and VREFN:
VREF = VREFP – VREFN. A simplified diagram of the
circuitry on the reference inputs is shown in Figure 17. The
switches and capacitors can be modeled with an effective
impedance equal to:
VREFP VREFN
tSAMPLE
ǒ Ǔ
ń25pF + 1MW for fCLK + 2.4576MHz
2
Σ
CLK
VREF
2
2VREF
VREFP
VREFN
Digital
Filter and
Serial
AINP
AINN
X1
X1
V
DRDY/DOUT
SCLK
IN
Modulator
Σ
Interface
AVDD
AVDD
ESD
Protection
S1
S1
Figure 15. Conceptual Diagram of the ADS1245
ANALOG INPUTS (AINP, AINN)
25pF
The input signal to be measured is applied to the input pins
AINP and AINN. The ADS1245 features a low-drift
chopper-stabilized buffer to achieve very high input
impedance. The input impedance can be modeled by
resistors, as shown in Figure 16. The impedance scales
inversely with fCLK frequency. For example, if the frequency
of fCLK is reduced by a factor of two, the impedances ZeffA
and ZeffB will double.
S2
tSAMPLE = 128/fCLK
ON
OFF
ON
S1
S2
OFF
AVDD/2
Ω
ZeffA = 280G
Figure 17. Simplified Reference Input Circuitry
AINP
AINN
Ω
ZeffB = 3.46G
The ADS1245 is specified for operation with VREF = 1.25V,
resulting in a full−scale input value of 2.5V. However, the
buffered analog inputs can accept voltages within the
range of 0.10V to 3.75V, resulting in a maximum VIN of
3.65V. Input voltages can be accurately measured over
this entire range if a voltage reference of 1.825V is pro-
vided. In any case, digital output codes will clip to the full
scale value if the absolute input voltage range exceeds
Ω
ZeffA = 280G
fCLK = 2.4576MHz.
AVDD/2
Figure 16. Effective Analog Input Impedances
2VREF
.
7
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To achieve optimal gain error performance, the reference
input should be maintained within the range GND + 0.1V
to AVDD − 1.25V when performing a self-calibration. A
calibration based on a reference input outside this voltage
range will result in gain errors exceeding specified values,
but not more than 0.5%. Errors due to drift will remain
within specified limits regardless of the calibration
procedure.
subsequent SCLK rising edge. After all 24 bits have been
retrieved, the pin can be forced high with an additional
SCLK. It will then stay high until new data is ready. This is
useful when polling on the status of DRDY/DOUT to
determine when to begin data retrieval.
SERIAL CLOCK INPUT (SCLK)
This digital input shifts serial data out with each rising
edge. As with CLK, this input may be driven with 5V logic
regardless of the DVDD or AVDD voltage. There is
hysteresis built into this input, but care should still be taken
to ensure a clean signal. Glitches or slow-rising signals
can cause unwanted additional shifting. For this reason, it
is best to make sure the rise-and-fall times of SCLK are
less than 50ns.
For best performance, bypass the voltage reference inputs
with a 0.1µF capacitor between VREFP and VREFN.
Place the capacitor as close as possible to the pins.
ESD diodes protect the inputs. To keep these diodes from
turning on, make sure the voltages on the input pins do not
go below GND by more than 100mV, and likewise do not
exceed AVDD by 100mV.
CLOCK INPUT (CLK)
FREQUENCY RESPONSE
This digital input supplies the system clock to the
ADS1245. The recommended CLK frequency is
2.4576MHz. This places the notches of the digital filter at
50Hz and 60Hz and sets the data rate at 15SPS. The CLK
frequency can be increased to speed up the data rate, but
the frequency notches will move proportionally in
frequency. CLK must be left running during normal
operation. It can be turned off during Sleep Mode to save
power, but this is not required. The CLK input can be driven
with 5V logic, regardless of the DVDD or AVDD voltage.
Minimize the overshoot and undershoot on CLK for the
best analog performance. A small resistor in series with
CLK (10Ω to 100Ω) can often help. CLK can be generated
from a number of sources including stand-alone crystal
oscillators and microcontrollers. The MSP430, an ultra low
power microcontroller, is especially well-suited for this
task. Using the MSP430 FLL clock generator available on
the 4xx family, it is easy to produce a 2.4576MHz clock
from a 32.768kHz crystal.
The ADS1245 frequency response for fCLK = 2.4576MHz
is shown in Figure 18. The frequency response repeats at
multiples of 19.2kHz. The overall response is that of a
low-pass filter with a –3dB cutoff frequency of 13.7Hz. As
can be seen, the ADS1245 does a good job attenuating out
to 19kHz. For the best resolution, limit the input bandwidth
to below this value to keep higher frequency noise from
affecting performance. Often, a simple RC filter on the
ADS1245 analog inputs is all that is needed.
0
−
−
−
−
20
40
60
80
−
−
−
100
120
140
DATA READY/DATA OUTPUT (DRDY/DOUT)
The digital output pin on the ADS1245 serves two
purposes. It indicates when new data is ready by going
low. Afterwards, on the first rising edge of SCLK, the
DRDY/DOUT pin changes function and begins outputting
the conversion data, MSB first. Data is shifted out on each
0
9.6
19.2
Frequency (kHz)
Figure 18. Frequency Response
8
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To help see the response at lower frequencies, Figure 19
illustrates the response out to 180Hz. Notice that both
50Hz and 60Hz signals are rejected. This feature is very
useful for eliminating power line cycle interference during
measurements. Figure 20 shows the ADS1245 response
around these frequencies.
The ADS1245 data rate and frequency response scale
directly with CLK frequency. For example, if fCLK
increases from 2.4576MHz to 4.9152MHz, the data rate
increases from 15sps to 30sps while the notches in the
response at 50Hz and 60Hz move out to 100Hz and
120Hz.
SETTLING TIME
0
The ADS1245 has single-cycle settling. That is, the output
data is fully settled after a single conversion—there is no
need to wait for additional conversions before retrieving
the data when there is a change on the analog inputs.
−
−
−
−
20
40
60
80
fCLK = 2.4576MHz
In order to realize single-cycle settling, synchronize
changes on the analog inputs to the conversion beginning,
which is indicated by the falling edge of DRDY/DOUT. For
example, when using a multiplexer in front of the
ADS1245, change the multiplexer inputs when
DRDY/DOUT goes low. Increasing the time between the
conversion beginning and the change on the analog inputs
(tDELAY) results in a settling error in the conversion data, as
shown in Figure 21. The settling error versus delay time is
shown in Figure 22. If the input change is delayed to the
point where the settling error is too high, simply ignore the
first data result and wait for the second conversion, which
will be fully settled.
−
−
−
−
−
100
120
140
160
180
Frequency (Hz)
Figure 19. Frequency Response to 180Hz
10.000000
1.000000
0.100000
−
−
−
−
−
−
40
50
60
70
80
90
fCLK = 2.4576MHz
fCLK = 2.4576MHz
0.010000
0.001000
0.000100
0.000010
0.000001
−
100
−
110
120
−
0
2
4
6
8
10
12
14
16
45
50
55
Frequency (Hz)
60
65
Delay Time, tDELAY (ms)
Figure 20. Frequency Response Near
50Hz and 60Hz
Figure 21. Settling Error vs Delay Time
9
ꢉꢃ ꢠꢡ ꢢ ꢣ ꢤ
SBAS287A − JUNE 2003 − REVISED SEPTEMBER 2003
www.ti.com
Begin New Conversion,
Previous Conversion Data
New Conversion Complete
Complete Previous Conversion
DRDY/DOUT
tDELAY
VIN
Figure 22. Analog Input Change Timing
ready for retrieval. The time required before the first data
is ready (t6) depends on how fast AVDD and DVDD ramp
to their final value (t1). For most ramp rates, t1 + t2 ≈ 350ms
(fCLK = 2.4576MHz). If the system environment is not stable
during power-up (the temperature is varying or the supply
voltages are moving around), it is recommended that a
self-calibration be issued after everything is stable.
POWER−UP
Self-calibration is performed at power-up to minimize offset
and gain errors. In order for the self-calibration at power-up to
work properly, make sure that both AVDD and DVDD increase
monotonically and are settled by t1, as shown in Figure 23.
SCLK must be held low during this time. Once calibration
is complete, DRDY/DOUT goes low, indicating data is
AVDD and DVDD
DRDY/DOUT
Data ready after power−up calibration.
SCLK
t1
t2
SYMBOL DESCRIPTION
MIN MAX UNITS
(1)
(1)
t1
t2
AVDD and DVDD settling time.
100 ms
Wait time for calibration and first data
conversion.
ms
316
NOTE: (1) Values given for fCLK = 2.4576MHz. For different CLK frequencies,
scale proportional to CLK period.
Figure 23. Power-Up Timing
10
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ꢉ ꢃꢠ ꢡꢢ ꢣꢤ
SBAS287A − JUNE 2003 − REVISED SEPTEMBER 2003
DATA FORMAT
DATA RETRIEVAL
The ADS1245 outputs 24 bits of data in Binary Two’s
Complement format. The least significant bit (LSB) has a
weight of (2VREF)/(223 − 1). A positive full-scale input
produces an output code of 7FFFFFh and the negative
full-scale input produces an output code of 8000000h. The
output clips at these codes for signals exceeding
full-scale. Table 1 summarizes the ideal output codes for
different input signals.
The ADS1245 continuously converts the analog input
signal. To retrieve data, wait until DRDY/DOUT goes low,
as shown in Figure 24. After this occurs, begin shifting out
the data by applying SCLKs. Data is shifted out most
significant bit (MSB) first. It is not required to shift out all the
24 bits of data, but the data must be retrieved before the
new data is updated (see t3) or else it will be overwritten.
Avoid data retrieval during the update period.
DRDY/DOUT remains at the state of the last bit shifted out
until it is taken high (see t7), indicating that new data is
being updated.
Table 1. Ideal Output Code vs Input Signal
INPUT SIGNAL VIN (AINP − AINN) IDEAL OUTPUT CODE(1)
To avoid having DRDY/DOUT remain in the state of the
last bit, shift a 25th SCLK to force DRDY/DOUT high; see
Figure 25. This technique is useful when a host controlling
the ADS1245 is polling DRDY/DOUT to determine when
data is ready.
7FFFFF
≥ +2VREF
H
000001
H
) 2VREF
(223) * 1
0
000000
H
FFFFFF
H
* 2VREF
(223) * 1
800000
H
223
ǒ Ǔ
v * 2VREF
(223) * 1
NOTE: (1) Excludes effects of noise, INL, offset, and gain errors.
Data
Data is ready.
MSB
New data is ready.
LSB
0
DRDY/DOUT
SCLK
23
22
21
t5
t6
t3
t4
t7
1
24
t4
t8
SYMBOL
DESCRIPTION
MIN
MAX UNITS
t3
t4
0
ns
ns
ns
DRDY/DOUT low to first SCLK rising edge.
SCLK positive or negative pulse width.
100
(1)
t5
SCLK rising edge to new data bit valid;
propagation delay.
50
ns
0
t6
t7
SCLK rising edge to old data bit valid: hold time.
Data updating, no read back allowed.
Conversion time (1/data rate).
µs
152
152
(2)
t8
ms
66.667 66.667
NOTES: (1) Load on DRDY/DOUT = 20pF||100kΩ.
(2) Values given for fCLK = 2.4576MHz. For different CLK frequencies, scale
proportional to CLK period. For example, for fCLK = 4.9152MHz, t8→33.333ms.
Figure 24. Data Retrieval Timing
11
ꢉꢃ ꢠꢡ ꢢ ꢣ ꢤ
SBAS287A − JUNE 2003 − REVISED SEPTEMBER 2003
www.ti.com
Data
Data is ready.
New data is ready.
DRDY/DOUT
23
22
21
0
1
24
25
SCLK
25th SCLK to force DRDY/DOUT
high
Figure 25. Data Retrieval with DRDY/DOUT Forced High Afterwards
When the calibration is complete, DRDY/DOUT will go
low, indicating that new data is ready. There is no need to
alter the analog input signal applied to the ADS1245 during
calibration; the inputs pins are disconnected within the
ADC and the appropriate signals are automatically applied
internally. The first conversion after a calibration is fully
settled and valid for use. The time required for a calibration
depends on two independent signals: the falling edge of
SCLK and an internal clock derived from CLK. Variations
in the internal calibration values will change the time
required for calibration (t9) within the range given by the
MIN/MAX specs. t12 and t13 described in the next section
are likewise affected.
SELF-CALIBRATION
The user can initiate self-calibration at any time, though in
many applications the ADS1245 drift performance is good
enough that the self-calibration performing automatically
at power-up is all that is needed. To initiate a
self-calibration, apply at least two additional SCLKs after
retrieving 24 bits of data. Figure 26 shows the timing
pattern. The 25th SCLK will send DRDY/DOUT high. The
falling edge of the 26th SCLK will begin the calibration
cycle. Additional SCLK pulses may be sent after the 26th
SCLK, but minimizing activity on SCLK during calibration
provides best results.
Data ready after calibration
DRDY/DOUT
SCLK
23
22
21
0
23
Cal begins
26
1
24
25
t9
SYMBOL DESCRIPTION
(1)
MIN MAX UNITS
209 210
t9
First data ready after calibration.
ms
NOTE: (1) Values given for fCLK = 2.4576MHz. For different CLK frequencies,
scale proportional to CLK period.
Figure 26. Self-Calibration Timing
12
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ꢉ ꢃꢠ ꢡꢢ ꢣꢤ
SBAS287A − JUNE 2003 − REVISED SEPTEMBER 2003
Sleep Mode with Self-Calibration
SLEEP MODE
Self-calibration can be set to run immediately after exiting
Sleep mode. This is useful when the ADS1245 is put in
Sleep mode for long periods of time and self-calibration is
desired afterwards to compensate for temperature or
supply voltage changes.
Sleep mode dramatically reduces power consumption
(typically < 1µW with CLK stopped) by shutting down all of
the active circuitry. To enter Sleep mode, simply hold
SCLK high after DRDY/DOUT goes low, as shown in
Figure 27. Sleep Mode can be initiated at any time during
read-back; it is not necessary to retrieve all 24 bits of data
beforehand. Once t11 has passed with SCLK held high,
Sleep mode will activate. DRDY/DOUT stays high once
Sleep mode begins. SCLK must remain high to stay in
Sleep mode. To exit Sleep mode (wakeup), set SCLK low.
The first data after exiting Sleep Mode is valid. It is not
necessary to stop CLK during Sleep mode, but doing so
will further reduce the digital supply current.
To force a self-calibration with Sleep mode, shift 25 bits out
before taking SCLK high to enter Sleep mode.
Self-calibration begins after wakeup. Figure 28 shows the
appropriate timing. Note the extra time needed after
wakeup for calibration before data is ready. The first data
after Sleep mode with self-calibration is fully settled and
can be used.
Data ready after wakeup
Sleep Mode
DRDY/DOUT
SCLK
23
22
21
0
23
Wakeup
1
24
t10
t11
t12
SYMBOL
DESCRIPTION
MIN
0
MAX UNITS
SCLK HIGH after DRDY/DOUT goes low to activate Sleep
Mode.
63.7
ms
(1)
t10
(1)
t11
ms
66.5
66.5
72
Sleep Mode activation time.
Data ready after wakeup.
(1)
t12
ms
71
NOTES: (1) Values given for fCLK = 2.4576MHz. For different CLK frequencies, scale proportional to
CLK period.
Figure 27. Sleep-Mode Timing; Can Be Used for SIngle Conversions
Data ready after wakeup and calibration
23
Sleep Mode
DRDY/DOUT
SCLK
23
22
21
0
Wakeup and begin cal.
1
24
25
t11
t13
SYMBOL
DESCRIPTION
Data ready after wakeup and calibration.
MIN MAX UNITS
(1)
ms
210 211
t13
NOTE: (1) Values given for fCLK = 2.4576MHz. For different CLK frequencies, scale
proportional to CLK period.
Figure 28. Sleep-Mode with Self-Calibration on Wakeup Timing; Can Be Used for SIngle Conversions
13
ꢉꢃ ꢠꢡ ꢢ ꢣ ꢤ
SBAS287A − JUNE 2003 − REVISED SEPTEMBER 2003
www.ti.com
SINGLE CONVERSIONS
to +5V logic
SN74LVCC3245A
When only single conversions are needed, Sleep mode
can be used to start and stop the ADS1245. To make a
single conversion, first enter the Sleep Mode holding
SCLK high. Now, when ready to start the conversion, take
SCLK low. The ADS1245 will wake up and begin the
conversion. Wait for DRDY/DOUT to go low, and then
retrieve the data. Afterwards, take SCLK high to stop the
ADS1245 from converting and re−enter Sleep mode.
Continue to hold SCLK high until ready to start the next
conversion. Operating in this fashion greatly reduces
power consumption since the ADS1245 is shut down while
idle between conversions. Self−calibrations can be
performed prior to the start of the single conversions by
using the waveform shown in Figure 28.
+5V
µ
µ
0.1 F
0.1 F
R
1
from
from
+
+
+5V logic +5V logic
10
9
8
7
6
CLK
SCLK DRDY/DOUT DVDD
AVDD
ADS1245
GND
1
VREFP
2
VREFN
3
AINN
4
AINP
5
SINGLE-SUPPLY OPERATION
It is possible to operate the ADS1245 with a single supply.
For a 3V supply, simply connect AVDD and DVDD
together. Figure 29 shows an example of the ADS1245
running on a single 5V supply. An external resistor, R1, is
used to drop 5V supply down to a desired voltage level of
DVDD. For example, if the desired DVDD supply voltage
is 3V and AVDD is 5V, the value of R1 should be:
Figure 29. Example of the ADS1244 Running on a
Single 5V Supply
MULTI-CHANNEL SYSTEMS
ń
R1 + (5V * 3V) 5mA [ 400kW
Multiple ADS1245s can be operated in parallel to measure
multiple input signals. Figure 30 shows an example of a
two-channel system. For simplicity, the supplies and
reference circuitry were not included. The same CLK
signal should be applied to all devices. To be able to
synchronize the ADS1245s, connect the same SCLK
signal to all devices as well. When ready to synchronize,
place all the devices in Sleep mode. Afterwards, a wakeup
command will synchronize all the ADS1245s; that is, they
will sample the input signals simultaneously
(1)
where 5mA is a typical digital current consumption when
DVDD = 3V (refer to the typical characteristic Digital
Current vs Digital Supply). A buffer on DRDY/DOUT can
provide level−shifting if required.
DVDD can be set to a desired voltage by choosing a proper
value of R1, but keep in mind that DVDD must be set
between 1.8V and 3.6V. Note that the maximum logic high
output of DRDY/DOUT is equal to DVDD, but both CLK
and SCLK inputs can be driven with 5V logic regardless of
the DVDD or AVDD voltage. Use 0.1mF capacitors to
bypass both AVDD and DVDD.
The DRDY/DOUT outputs will go low at approximately the
same time after synchronization. The falling edges,
indicating that new data is ready, will vary with respect to
each other no more than timing specification t14. This
variation is due to possible differences in the ADS1245
internal calibration settings. To account for this when using
multiple devices, either wait for t14 to pass after seeing one
device DRDY/DOUT go low, or wait until all DRDY/DOUTs
have gone low before retrieving data.
14
www.ti.com
ꢉ ꢃꢠ ꢡꢢ ꢣꢤ
SBAS287A − JUNE 2003 − REVISED SEPTEMBER 2003
ADS1245
1
2
3
4
5
GND
CLK 10
VREFP
VREFN
AINN
SCLK
9
8
7
6
OUT1
DRDY/DOUT
DVDD
IN1
AINP
AVDD
ADS1245
1
2
3
4
5
GND
CLK 10
VREFP
VREFN
AINN
SCLK
9
8
7
6
OUT2
DRDY/DOUT
DVDD
IN2
AINP
AVDD
CLK and SCLK
Sources
OUT1
t14
OUT2
SYMBOL
MAX UNITS
MIN
DESCRIPTION
Difference between DRDY/
DOUTs going low in
t14
500 µs
multichannel systems.
Figure 30. Example of Using Multiple ADS1245s in Parallel
15
ꢉꢃ ꢠꢡ ꢢ ꢣ ꢤ
SBAS287A − JUNE 2003 − REVISED SEPTEMBER 2003
www.ti.com
SUMMARY OF SERIAL INTERFACE WAVEFORMS
DRDY/DOUT
23
22
21
0
MSB
LSB
SCLK
1
24
a. Data Retrieval
DRDY/DOUT
SCLK
23
22
21
0
1
24
25
b. Data Retrieval with DRDY/DOUT Forced High Afterwards
Data ready after calibration
D
RDY/DOUT
23
22
21
0
Begin calibration
25 26
SCLK
1
24
c. Self-Calibration
Data ready
Sleep Mode
23
22
21
0
DRDY/DOUT
SCLK
Wakeup and
start conversion
1
24
d. Sleep Mode/Single Conversions
Data ready after
wakeup and calibration
Sleep Mode
DRDY/DOUT
SCLK
23
22
21
0
Wakeup and
begin cal.
1
24
25
e. Sleep Mode/Single Conversions with Self-Calibration on Wakeup
Figure 31. Summary of Serial Interface Waveforms
16
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
PACKAGING INFORMATION
Orderable Device
ADS1245IDGST
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 85
Top-Side Markings
Samples
Drawing
Qty
(1)
(2)
(3)
(4)
ACTIVE
VSSOP
VSSOP
DGS
10
10
250
Green (RoHS CU NIPDAUAG Level-2-260C-1 YEAR
& no Sb/Br)
BHI
BHI
ADS1245IDGSTG4
ACTIVE
DGS
250
Green (RoHS CU NIPDAUAG Level-2-260C-1 YEAR
& no Sb/Br)
-40 to 85
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Jan-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
ADS1245IDGST
VSSOP
DGS
10
250
180.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Jan-2013
*All dimensions are nominal
Device
Package Type Package Drawing Pins
VSSOP DGS 10
SPQ
Length (mm) Width (mm) Height (mm)
210.0 185.0 35.0
ADS1245IDGST
250
Pack Materials-Page 2
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