ADS1246_14_技术文档

ADS1246

ADS1247

ADS1248

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SBAS426D –AUGUST 2008–REVISED MARCH 2010

24-Bit Analog-to-Digital Converters for Temperature Sensors

Check for Samples: ADS1246, ADS1247, ADS1248

1

FEATURES

DESCRIPTION

23

•

24 Bits, No Missing Codes

The ADS1246, ADS1247, and ADS1248 are

highly-integrated, precision, 24-bit analog-to-digital

converters (ADCs). The ADS1246/7/8 feature an

onboard, low-noise, programmable gain amplifier

(PGA), a precision delta-sigma (ΔΣ) ADC with a

single-cycle settling digital filter, and an internal

oscillator. The ADS1247 and ADS1248 also provide a

built-in, very low drift voltage reference with 10mA

output capacity, and two matched programmable

current digital-to-analog converters (DACs). The

ADS1246/7/8 provide a complete front-end solution

for temperature sensor applications including thermal

couples, thermistors, and RTDs.

•

Data Output Rates Up to 2kSPS

•

Single-Cycle Settling for All Data Rates

Simultaneous 50/60Hz Rejection at 20SPS

4 Differential/7 Single-Ended Inputs (ADS1248)

2 Differential/3 Single-Ended Inputs (ADS1247)

Low-Noise PGA: 48nV at PGA = 128

Matched Current Source DACs

Very Low Drift Internal Voltage Reference:

10ppm/°C (max)

•

Sensor Burnout Detection

An input multiplexer supports four differential inputs

for the ADS1248, two for the ADS1247, and one for

the ADS1246. In addition, the multiplexer has a

4/8 General-Purpose I/Os (ADS1247/8)

Internal Temperature Sensor

sensor

thermocouples,

burnout

detect,

system

voltage

monitoring,

bias

for

and

Power Supply and V_REFMonitoring

(ADS1247/8)

general-purpose digital I/Os (ADS1247 and

ADS1248). The onboard, low-noise PGA provides

selectable gains of 1 to 128. The ΔΣ modulator and

adjustable digital filter settle in only one cycle, for fast

channel cycling when using the input multiplexer, and

support data rates up to 2kSPS. For data rates of

20SPS or less, both 50Hz and 60Hz interference are

rejected by the filter.

•

Self and System Calibration

SPI™-Compatible Serial Interface

Analog Supply Unipolar (+2.7V to

+5.25V)/Bipolar (±2.5V) Operation

•

Digital Supply: +2.7V to +5.25V

Operating Temperature –40°C to +125°C

The ADS1246 is offered in a small TSSOP-16

package, the ADS1247 is available in a TSSOP-20

package, and the ADS1248 in a TSSOP-28 package.

All three devices are rated over the extended

specified temperature range of –40°C to +105°C.

APPLICATIONS

•

Temperature Measurement

–

RTDs, Thermocouples, and Thermistors

•

Pressure Measurement

Industrial Process Control

ADS1248 Only

REFP0/ REFN0/

AVDD

REFP REFN

DVDD

AVDD

GPIO0 GPIO1 REFP1 REFN1 VREFOUT VREFCOM

DVDD

Burnout

Detect

Burnout

Detect

ADS1247

ADS1248

ADS1246

Voltage

VREF Mux

V_BIAS

Reference

GPIO

SCLK

AIN0/IEXC

AIN1/IEXC

System

Monitor

DIN

Serial

Interface

and

Serial

Interface

and

DRDY

DOUT/DRDY

CS

DRDY

DOUT/DRDY

CS

AIN2/IEXC/GPIO2

AIN3/IEXC/GPIO3

3rd Order

DS

Adjustable

Digital

Filter

3rd Order

DS

Adjustable

Digital

Filter

AIN0

AIN1

Input

Mux

Input

Mux

PGA

Modulator

AIN4/IEXC/GPIO4

AIN5/IEXC/GPIO5

Control

START

RESET

START

RESET

Dual

Current

DACs

AIN6/IEXC/GPIO6

AIN7/IEXC/GPIO7

Internal Oscillator

ADS1248 Only

Burnout

Detect

Burnout

Detect

AVSS

CLK

DGND

AVSS IEXC1 IEXC2

CLK

DGND

ADS1248 Only

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2

3

SPI is a trademark of Motorola, Inc.

All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

ADS1246

ADS1247

ADS1248

SBAS426D –AUGUST 2008–REVISED MARCH 2010

www.ti.com

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

PACKAGE/ORDERING INFORMATION⁽¹⁾

DUAL SENSOR

EXCITATION CURRENT

SOURCES

PACKAGE-

LEAD

PRODUCT

NUMBER OF INPUTS

VOLTAGE REFERENCE

1 Differential

or

1 Single-Ended

ADS1246

External

NO

YES

TSSOP-16

TSSOP-20

TSSOP-28

2 Differential

or

3 Single-Ended

ADS1247

ADS1248

Internal or External

4 Differential

or

7 Single-Ended

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this data sheet, or see the TI

website at www.ti.com

ABSOLUTE MAXIMUM RATINGS⁽¹⁾

Over operating free-air temperature range (unless otherwise noted).

ADS1246, ADS1247, ADS1248

PARAMETER

MIN

–0.3

–2.8

–0.3

MAX

+5.5

+0.3

+5.5

UNIT

V

AVDD to AVSS

AVSS to DGND

DVDD to DGND

V

100, momentary

10, continuous

mA

V

Input current

Analog input voltage to AVSS

Digital input voltage to DGND

Maximum junction temperature

Operating temperature range

Storage temperature range

AVSS – 0.3

–0.3

AVDD + 0.3

DVDD + 0.3

+150

V

°C

–40

–60

+125

+150

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated is not implied. Exposure to

absolute-maximum-rated conditions for extended periods may affect device reliability.

2

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SBAS426D –AUGUST 2008–REVISED MARCH 2010

THERMAL INFORMATION

ADS1246,

ADS1247,

ADS1248

THERMAL METRIC⁽¹⁾

UNITS

TSSOP (IPW)

28

q_JA

Junction-to-ambient thermal resistance⁽²⁾

Junction-to-case(top) thermal resistance

54.6

11.3

(3)

q_JC(top)

q_JB

(4)

Junction-to-board thermal resistance

13.0

°C/W

0.5

(5)

y_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

(6)

(7)

y_JB

12.7

n/a

q_JC(bottom)

Junction-to-case(bottom) thermal resistance

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, High-K board, as

specified in JESD51-7, in an environment described in JESD51-2a.

(3) The junction-to-case(top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-standard

test exists, but a close description can be found in the ANSI SEMI standard G30-88.

(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB

temperature, as described in JESD51-8.

(5) The junction-to-top characterization parameter, y_JT, estimates the junction temperature of a device in a real system and is extracted

from the simulation data for obtaining q_JA, using a procedure described in JESD51-2a (sections 6 and 7).

(6) The junction-to-board characterization parameter, y_JBestimates the junction temperature of a device in a real system and is extracted

from the simulation data for obtaining q_JA, using a procedure described in JESD51-2a (sections 6 and 7).

(7) The junction-to-case(bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific

JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

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SBAS426D –AUGUST 2008–REVISED MARCH 2010

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ELECTRICAL CHARACTERISTICS

Minimum/maximum specifications apply from –40°C to +105°C. Typical specifications are at +25°C. All specifications at

AVDD = +5V, DVDD = +3.3V, AVSS = 0V, V_REF= +2.048V, and oscillator frequency = 4.096MHz, unless otherwise noted.

ADS1246, ADS1247, ADS1248

PARAMETER

ANALOG INPUTS

CONDITIONS

MIN

TYP

MAX

UNIT

Full-scale input voltage

(V_IN= ADCINP – ADCINN)

±V_REF/PGA

2.7/PGA

V

(V_IN)(Gain)

2

(V_IN)(Gain)

2

AVSS + 0.1V +

AVDD - 0.1V -

Common-mode input range

V

Differential input current

Absolute input current

PGA gain settings

Burnout current source

Bias voltage

100

See Table 11

pA

1, 2, 4, 8, 16, 32, 64, 128

0.5, 2, or 10

mA

V

(AVDD + AVSS)/2

400

Bias voltage output impedance

SYSTEM PERFORMANCE

Resolution

Ω

No missing codes

24

Bits

SPS

ppm

mV

Data rate

5, 10, 20, 40, 80, 160, 320, 640, 1000, 2000

Integral nonlinearity (INL)

Offset error

Differential input, end point fit, PGA = 1

After calibration⁽¹⁾

6

15

–15

Offset drift

See Figure 11 to Figure 14

nV/°C

T = +25°C, all PGAs,

data rate = 40, 80, or 160SPS

Gain error

–0.02

±0.005

0.02

%

Gain drift

See Figure 19 to Figure 22

Single-cycle settling

See Table 5 to Table 8

See Table 13

ppm/°C

ADC conversion time

Noise

Normal-mode rejection

At dc, PGA = 1

At dc, PGA = 32

80

90

dB

Common-mode rejection

Power-supply rejection

125

AVDD/DVDD at dc, PGA = 32,

data rate = 80SPS

100

135

dB

VOLTAGE REFERENCE INPUT

Voltage reference input

0.5

(AVDD – AVSS) – 1

V

(V_REF= V_REFP– V_REFN

)

Negative reference input (REFN)

Positive reference input (REFP)

Reference input current

ON-CHIP VOLTAGE REFERENCE

Output voltage

AVSS – 0.1

REFN + 0.5

REFP – 0.5

AVDD + 0.1

V

30

nA

2.038

2.048

2.058

±10

V

Output current⁽²⁾

mA

Load regulation

50

mV/mA

ppm/°C

ms

T_A= +25°C to +105°C

T_A= –40°C to +105°C

2

6

10

15

Drift⁽³⁾

Startup time

See Table 14

(1) Offset calibration on the order of noise.

(2) Do not exceed this loading on the internal voltage reference.

(3) Specified by the combination of design and final production test.

4

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SBAS426D –AUGUST 2008–REVISED MARCH 2010

ELECTRICAL CHARACTERISTICS (continued)

Minimum/maximum specifications apply from –40°C to +105°C. Typical specifications are at +25°C. All specifications at

AVDD = +5V, DVDD = +3.3V, AVSS = 0V, V_REF= +2.048V, and oscillator frequency = 4.096MHz, unless otherwise noted.

ADS1246, ADS1247, ADS1248

PARAMETER

CURRENT SOURCES (IDACS)

Output current

CONDITIONS

MIN

TYP

MAX

UNIT

50, 100, 250, 500, 750, 1000, 1500

AVDD – 0.7

mA

Voltage compliance

Initial error

All currents

V

All currents, each IDAC

All currents, between IDACs

Each IDAC

–6

±1.0

±0.15

100

6

% of FS

ppm/°C

Initial mismatch

Temperature drift

Temperature drift matching

SYSTEM MONITORS

Between IDACs

10

Voltage

T_A= +25°C

118

405

mV

Temperature

sensor reading

Drift

mV/°C

GENERAL-PURPOSE INPUT/OUTPUT (GPIO)

V_IH

0.7AVDD

AVSS

AVDD

V

V_IL

0.3AVDD

Logic levels

V_OH

V_OL

I_OH= 1mA

I_OL= 1mA

0.8AVDD

0.2 AVDD

DIGITAL INPUT/OUTPUT (other than GPIO)

V_IH

0.7DVDD

DGND

DVDD

V

V_IL

0.3DVDD

Logic levels

V_OH

V_OL

I_OH= 1mA

0.8DVDD

DGND

V

I_OL= 1mA

0.2 DVDD

±10

V

Input leakage

DGND < V_IN< DVDD

mA

MHz

%

Frequency

Duty cycle

1

25

4.5

Clock input

(CLK)

75

Internal oscillator frequency

3.89

4.096

4.3

MHz

POWER SUPPLY

DVDD

2.7

–2.5

5.25

0

V

AVSS

AVDD

AVSS + 2.7

AVSS + 5.25

Normal mode, DVDD = 5V,

data rate = 20SPS, internal oscillator

230

mA

DVDD current

AVDD current

Normal mode, DVDD = 3.3V,

data rate = 20SPS, internal oscillator

210

0.2

mA

µA

Sleep mode

Converting, AVDD = 5V,

data rate = 20SPS, external reference

225

Converting, AVDD = 3.3V,

data rate = 20SPS, external reference

200

0.1

µA

mA

Sleep mode

Additional current with internal reference

enabled

180

AVDD = DVDD = 5V,

data rate = 20SPS, internal oscillator,

external reference

2.3

1.4

mW

Power dissipation

AVDD = DVDD = 3.3V,

data rate = 20SPS, internal oscillator,

external reference

TEMPERATURE RANGE

Specified

–40

–60

+105

+125

+150

°C

Operating

Storage

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PIN CONFIGURATIONS

PW PACKAGE

TSSOP-28

(TOP VIEW)

DVDD

1

2

3

4

5

6

7

8

9

28 SCLK

DGND

CLK

27 DIN

26 DOUT/DRDY

25 DRDY

RESET

REFP0/GPIO0

REFN0/GPIO1

REFP1

24 CS

23 START

22 AVDD

ADS1248

REFN1

21 AVSS

VREFOUT

20 IEXC1

VREFCOM 10

AIN0/IEXC 11

19 IEXC2

18 AIN3/IEXC/GPIO3

17 AIN2/IEXC/GPIO2

16 AIN7/IEXC/GPIO7

15 AIN6/IEXC/GPIO6

AIN1/IEXC 12

AIN4/IEXC/GPIO4 13

AIN5/IEXC/GPIO5 14

6

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ADS1248 (TSSOP-28) PIN DESCRIPTIONS

NAME

PIN NO.

FUNCTION

DESCRIPTION

DVDD

DGND

CLK

1

2

3

4

Digital

Digital power supply

Digital ground

Digital

Digital input

External clock input. Tie this pin to DGND to activate the internal oscillator.

Chip reset (active low). Returns all register values to reset values.

RESET

Analog input

Digital in/out

REFP0/GPIO0

REFN0/GPIO1

5

6

Positive external reference input 0, or general-purpose digital input/output pin 0

Negative external reference 0 input, or general-purpose digital input/output pin 1

Analog input

Digital in/out

REFP1

7

8

9

Analog input

Analog output

Positive external reference 1 input

Negative external reference 1 input

Positive internal reference voltage output

REFN1

VREFOUT

Negative internal reference voltage output. Connect this pin to AVSS when using a unipolar

supply, or to the midvoltage of the power supply when using a bipolar supply.

VREFCOM

10

Analog output

AIN0/IEXC

AIN1/IEXC

11

12

Analog input

Analog input 0, optional excitation current output

Analog input 1, optional excitation current output

Analog input

Digital in/out

AIN4/IEXC/GPIO4

AIN5/IEXC/GPIO5

AIN6/IEXC/GPIO6

AIN7/IEXC/GPIO7

AIN2/IEXC/GPIO2

AIN3/IEXC/GPIO3

13

14

15

16

17

18

Analog input 4, optional excitation current output, or general-purpose digital input/output pin 4

Analog input 5, optional excitation current output, or general-purpose digital input/output pin 5

Analog input 6, optional excitation current output, or general-purpose digital input/output pin 6

Analog input 7, optional excitation current output, or general-purpose digital input/output pin 7

Analog input 2, optional excitation current output, or general-purpose digital input/output pin 2

Analog input 3, optional excitation current output, or general-purpose digital input/output pin 3

Analog input

Digital in/out

Analog input

Digital in/out

Analog input

Digital in/out

Analog input

Digital in/out

Analog input

Digital in/out

IOUT2

IOUT1

AVSS

AVDD

START

CS

19

20

21

22

23

24

25

Analog output

Analog

Excitation current output 2

Excitation current output 1

Negative analog power supply

Positive analog power supply

Conversion start. See text for complete description.

Chip select (active low)

Analog

Digital input

Digital output

DRDY

Data ready (active low)

Serial Data Out Output, or

Data Out combined with Data Ready (active low when DRDY function enabled)

DOUT/DRDY

26

Digital output

DIN

27

28

Digital input

Serial data input

Serial clock input

SCLK

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PW PACKAGE

TSSOP-20

(TOP VIEW)

DVDD

1

2

3

4

5

6

7

8

9

20 SCLK

19 DIN

DGND

CLK

18 DOUT/DRDY

17 DRDY

16 CS

RESET

REFP0/GPIO0

REFN0/GPIO1

VREFOUT

VREFCOM

AIN0/IEXC

ADS1247

15 START

14

AVDD

13 AVSS

12 AIN3/IEXC/GPIO3

11 AIN2/IEXC/GPIO2

AIN1/IEXC 10

ADS1247 (TSSOP-20) PIN DESCRIPTIONS

NAME

PIN NO.

FUNCTION

DESCRIPTION

DVDD

DGND

CLK

1

2

3

4

Digital

Digital power supply

Digital

Digital ground

Digital input

External clock input. Tie this pin to DGND to activate the internal oscillator.

Chip reset (active low). Returns all register values to reset values.

RESET

Analog input

Digital in/out

REFP0/GPIO0

5

Positive external reference input, or general-purpose digital input/output pin 0

Analog input

Digital in/out

REFN0/GPIO1

VREFOUT

6

7

8

Negative external reference input, or general-purpose digital input/output pin 1

Positive internal reference voltage output

Analog output

Negative internal reference voltage output. Connect this pin to AVSS when using a unipolar

supply, or to the midvoltage of the power supply when using a bipolar supply.

VREFCOM

AIN0/IEXC

AIN1/IEXC

9

Analog input

Analog input 0, optional excitation current output

Analog input 1, optional excitation current output

10

Analog input

Digital in/out

AIN2/IEXC/GPIO2

AIN3/IEXC/GPIO3

11

12

Analog input 2, optional excitation current output, or general-purpose digital input/output pin 2

Analog input

Digital in/out

Analog input 3, with or without excitation current output, or general-purpose digital input/output

pin 3

AVSS

AVDD

START

CS

13

14

15

16

17

Analog

Negative analog power supply

Positive analog power supply

Conversion start. See text for description of use.

Chip select (active low)

Digital input

Digital output

DRDY

Data ready (active low)

Serial data out output, or

Data out combined with Data Ready (active low when DRDY function enabled)

DOUT/DRDY

18

Digital output

DIN

19

20

Digital input

Serial data input

Serial clock input

SCLK

8

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PW PACKAGE

TSSOP-16

(TOP VIEW)

DVDD

DGND

CLK

1

2

3

4

5

6

7

8

16 SCLK

15 DIN

14 DOUT/DRDY

13

RESET

REFP

REFN

AINP

DRDY

ADS1246

12 CS

11 START

10

9

AVDD

AVSS

AINN

ADS1246 (TSSOP-16) PIN DESCRIPTIONS

NAME

PIN NO.

FUNCTION

DESCRIPTION

DVDD

DGND

CLK

1

2

Digital

Digital power supply

Digital

Digital ground

3

Digital input

Analog input

Analog

External clock input. Tie this pin to DGND to activate the internal oscillator.

Chip reset (active low). Returns all register values to reset values.

Positive external reference input

Negative external reference input

Positive analog input

RESET

REFP

REFN

AINP

4

5

6

7

AINN

AVSS

AVDD

START

CS

8

Negative analog input

9

Negative analog power supply

10

11

12

13

Analog

Positive analog power supply

Digital input

Digital output

Conversion start. See text for description of use.

Chip select (active low)

DRDY

Data ready (active low)

Serial data out output, or

Data out combined with Data Ready (active low when DRDY function enabled)

DOUT/DRDY

14

Digital output

DIN

15

16

Digital input

Serial data input

Serial clock input

SCLK

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TIMING DIAGRAMS

CS

t_SPWH

t_SCCS

t_CSSC

t_SCLK

SCLK

t_DISTt_DIHD

t_SPWL

DIN

DIN[0]

DIN[7]

DIN[6]

DIN[5]

DIN[4]

DIN[1]

DIN[0]

t_DOPD

t_DOHD

DOUT/DRDY⁽¹⁾

DOUT[7]

DOUT[6]

DOUT[5]

DOUT[4]

DOUT[1]

DOUT[0]

t_CSDO

Figure 1. Serial Interface Timing

(1)

Table 1. Timing Characteristics for Figure 1

SYMBOL

DESCRIPTION

MIN

10

7

MAX

UNIT

t_CSSC

t_SCCS

t_DIST

CS low to first SCLK high (set up time)

SCLK low to CS high (hold time)

DIN set up time

ns

(2)

t_OSC

5

ns

t_DIHD

t_DOPD

t_DOHD

DIN hold time

5

SCLK rising edge to new data valid

DOUT hold time

30

0

500

t_SCLK

SCLK period

64

0.75

10

Conversions

t_SCLK

t_SPWH

t_SPWL

t_CSDO

SCLK pulse width high

0.25

SCLK pulse width low

t_SCLK

CS high to DOUT high impedance

ns

(1) DRDY MODE bit = 0.

(2) t_OSC= 1/f_CLK. The default clock frequency f_CLK= 4.096MHz.

t_DTS

t_PWH

DRDY

t_STD

1

2

3

4

5

6

7

8

SCLK⁽³⁾

Figure 2. SPI Interface Timing to Allow Conversion Result Loading^{(3) (4)}

Table 2. Timing Characteristics for Figure 2

SYMBOL

DESCRIPTION

MIN

3

MAX

UNIT

t_OSC

ns

t_PWH

t_STD

t_DTS

DRDY pulse width high

SCLK low prior to DRDY low

5

DRDY falling edge to SCLK rising edge

30

(3) This timing diagram is applicable only when the CS pin is low. SCLK need not be low during t_STDwhen CS is high.

(4) SCLK should only be sent in multiples of eight during partial retrieval of output data.

10

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t_START

START

Figure 3. Minimum START Pulse Width

Table 3. Timing Characteristics for Figure 3

SYMBOL

t_START

DESCRIPTION

MIN

MAX

UNIT

START pulse width high

3

t_OSC

t_RESET

RESET

CS

SCLK

t_RHSC

Figure 4. Reset Pulse Width and SPI Communication After Reset

Table 4. Timing Characteristics for Figure 4

SYMBOL

t _RESET

t_RHSC

DESCRIPTION

MIN

MAX

UNIT

t_OSC

ms

RESET pulse width low

RESET high to SPI communication start

4

0.6⁽¹⁾

(1) Applicable only when f_OSC= 4.096MHz and scales proportionately with f_OSCfrequency.

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NOISE PERFORMANCE

The ADS1246/7/8 noise performance can be optimized by adjusting the data rate and PGA setting. As the

averaging is increased by reducing the data rate, the noise drops correspondingly. Increasing the PGA value

reduces the input-referred noise, particularly useful when measuring low-level signals. Table 5 to Table 10

summarize noise performance of the ADS1246/7/8. The data are representative of typical noise performance at

T = +25°C. The data shown are the result of averaging the readings from multiple devices and were measured

with the inputs shorted together. A minimum of 128 consecutive readings were used to calculate the RMS and

peak-to-peak noise for each reading.

Table 5, Table 7, and Table 9 list the input-referred noise in units of mV_RMSand mV_PPfor the conditions shown.

Table 6, Table 8, and Table 10 list the corresponding data in units of ENOB (effective number of bits) where:

ENOB = ln(Full-Scale Range/Noise)/ln(2)

(1)

Table 7 to Table 10 use the internal reference available on the ADS1247 and ADS1248. The data though are

also representative of the ADS1246 noise performance when using a low-noise external reference such as the

REF5020.

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Table 5. Noise in mV_RMSand (mV_PP

)

at AVDD = 5V, AVSS = 0V, and External Reference = 2.5V

DATA

RATE

(SPS)

PGA SETTING

1

2

4

8

16

32

64

128

5

10

1.10 (4.99)

1.53 (8.82)

2.32 (13.37)

2.72 (17.35)

3.56 (22.67)

5.26 (42.03)

9.39 (74.91)

13.21 (119.66)

0.68 (3.80)

0.82 (3.71)

1.23 (6.69)

1.33 (7.65)

1.87 (12.30)

2.52 (17.57)

4.68 (39.48)

6.93 (59.31)

0.37 (1.90)

0.50 (2.69)

0.71 (3.83)

0.68 (3.83)

0.81 (5.27)

1.32 (9.22)

2.69 (18.95)

3.59 (28.55)

0.19 (0.98)

0.27 (1.33)

0.34 (1.90)

0.38 (2.21)

0.50 (3.49)

0.67 (5.25)

1.24 (9.94)

1.53 (10.68)

0.10 (0.44)

0.15 (0.67)

0.18 (1.01)

0.22 (1.13)

0.30 (1.99)

0.41 (2.89)

0.68 (5.25)

0.95 (8.70)

2.02 (23.14)

2.19 (24.14)

0.07 (0.31)

0.08 (0.50)

0.12 (0.71)

0.14 (0.77)

0.19 (1.24)

0.26 (1.91)

0.45 (3.08)

0.63 (4.94)

1.15 (12.29)

1.36 (12.32)

0.05 (0.27)

0.06 (0.36)

0.10 (0.51)

0.15 (0.78)

0.19 (1.16)

0.27 (1.74)

0.38 (2.71)

0.53 (3.74)

0.77 (7.42)

1.08 (8.03)

0.05 (0.21)

0.07 (0.34)

0.09 (0.54)

0.14 (0.76)

0.18 (1.04)

0.26 (1.74)

0.36 (2.46)

0.50 (3.55)

0.64 (4.98)

1.00 (6.93)

20

40

80

160

320

640

1000

2000

32.34 (443.91) 16.11 (185.67) 11.54 (92.23) 4.65 (37.55)

32.29 (372.54) 15.99 (182.27) 8.02 (91.73) 4.08 (45.89)

Table 6. Effective Number of Bits From RMS Noise and (Peak-to-Peak Noise)

at AVDD = 5V, AVSS = 0V, and External Reference = 2.5V

DATA

RATE

(SPS)

PGA SETTING

1

2

4

8

16

32

64

128

5

10

21.8 (19.6)

21.4 (18.8)

20.8 (18.2)

20.5 (17.8)

20.1 (17.5)

19.6 (16.6)

18.7 (15.7)

18.2 (15.1)

17.0 (13.2)

17.0 (13.4)

21.5 (19.0)

21.3 (19.1)

20.7 (18.2)

20.6 (18.0)

20.1 (17.3)

19.6 (16.8)

18.7 (15.7)

18.2 (15.1)

17.0 (13.4)

17.0 (13.5)

21.4 (19.0)

21.0 (18.5)

20.5 (18.0)

20.3 (17.6)

19.6 (16.8)

18.5 (15.7)

18.1 (15.1)

16.4 (13.4)

17.0 (13.4)

21.4 (19.0)

20.8 (18.6)

20.5 (18.0)

20.4 (17.8)

20.0 (17.2)

19.5 (16.6)

18.7 (15.7)

18.4 (15.5)

16.7 (13.7)

16.9 (13.4)

21.3 (19.2)

20.7 (18.6)

20.4 (18.0)

20.2 (17.8)

19.7 (17.0)

19.3 (16.4)

18.5 (15.6)

18.0 (14.8)

17.0 (13.4)

16.8 (13.4)

20.9 (18.7)

20.6 (18.0)

20.0 (17.5)

19.8 (17.4)

19.4 (16.7)

18.9 (16.0)

18.1 (15.3)

17.6 (14.7)

16.8 (13.3)

16.5 (13.3)

20.2 (17.8)

19.9 (17.5)

19.3 (16.9)

18.7 (16.3)

18.4 (15.7)

17.9 (15.2)

17.4 (14.5)

16.9 (14.1)

16.4 (13.1)

15.9 (13.0)

19.4 (17.2)

18.9 (16.5)

18.4 (15.9)

17.8 (15.4)

17.5 (14.9)

16.9 (14.2)

16.5 (13.7)

16.0 (13.1)

15.6 (12.6)

15.0 (12.2)

20

40

80

160

320

640

1000

2000

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Table 7. Noise in mV_RMSand (mV_PP

)

at AVDD = 5V, AVSS = 0V, and Internal Reference = 2.048V

DATA

RATE

(SPS)

PGA SETTING

1

2

4

8

16

32

64

128

5

10

1.35 (7.78)

1.80 (10.82)

2.62 (14.32)

2.64 (16.29)

3.69 (23.62)

5.70 (35.74)

9.67 (67.44)

13.66 (93.06)

0.70 (4.17)

0.88 (5.26)

1.22 (7.05)

1.34 (7.75)

1.82 (10.81)

2.63 (16.90)

4.95 (35.30)

7.04 (45.20)

0.35 (2.03)

0.50 (2.75)

0.66 (3.88)

0.69 (4.06)

0.89 (5.48)

1.34 (8.82)

2.59 (17.52)

3.63 (18.73)

7.58 (61.30)

8.07 (67.13)

0.17 (0.95)

0.24 (1.47)

0.35 (2.05)

0.35 (2.07)

0.51 (2.68)

0.68 (4.24)

1.29 (8.86)

1.84 (12.97)

3.98 (33.04)

4.06 (36.16)

0.10 (0.53)

0.13 (0.80)

0.19 (1.09)

0.21 (1.15)

0.30 (1.69)

0.40 (2.65)

0.72 (4.35)

1.02 (6.51)

2.08 (16.82)

2.29 (19.22)

0.06 (0.32)

0.09 (0.49)

0.12 (0.66)

0.15 (0.85)

0.21 (1.32)

0.30 (1.92)

0.49 (3.03)

0.68 (4.20)

1.16 (9.08)

1.38 (9.87)

0.05 (0.31)

0.07 (0.39)

0.10 (0.61)

0.14 (0.81)

0.20 (1.09)

0.28 (1.88)

0.40 (2.44)

0.58 (3.69)

0.83 (5.42)

1.06 (6.93)

0.05 (0.29)

0.07 (0.40)

0.10 (0.55)

0.13 (0.75)

0.18 (0.98)

0.26 (1.57)

0.37 (2.34)

0.53 (3.50)

0.68 (4.65)

1.00 (6.48)

20

40

80

160

320

640

1000

2000

31.18 (284.59) 16.00 (129.77)

31.42 (273.39) 15.45 (130.68)

Table 8. Effective Number of Bits From RMS Noise and (Peak-to-Peak Noise)

at AVDD = 5V, AVSS = 0V, and Internal Reference = 2.048V

DATA

RATE

(SPS)

PGA SETTING

1

2

4

8

16

32

64

128

5

10

21.5 (19.0)

21.1 (18.5)

20.6 (18.1)

20.6 (17.9)

20.1 (17.4)

19.5 (16.8)

18.7 (15.9)

18.2 (15.4)

17.0 (13.8)

17.0 (13.9)

21.5 (18.9)

21.1 (18.6)

20.7 (18.1)

20.5 (18.0)

20.1 (17.5)

19.6 (16.9)

18.7 (15.8)

18.1 (15.5)

17.0 (13.9)

21.5 (18.9)

21.0 (18.5)

20.6 (18.0)

20.5 (17.9)

20.1 (17.5)

19.5 (16.8)

18.6 (15.8)

18.1 (15.7)

17.0 (14.0)

17.0 (13.9)

21.5 (19.0)

21.0 (18.4)

20.5 (17.9)

20.0 (17.5)

19.5 (16.9)

18.6 (15.8)

18.1 (15.3)

17.0 (13.9)

16.9 (13.8)

21.3 (18.9)

20.9 (18.3)

20.4 (17.8)

20.2 (17.8)

19.7 (17.2)

19.3 (16.6)

18.4 (15.8)

17.9 (15.3)

16.9 (13.9)

16.8 (13.7)

21.0 (18.6)

20.5 (18.0)

20.1 (17.6)

19.7 (17.2)

19.2 (16.6)

18.7 (16.0)

18.0 (15.4)

17.5 (14.9)

16.8 (13.8)

16.5 (13.7)

20.2 (17.7)

19.8 (17.3)

19.2 (16.7)

18.8 (16.3)

18.3 (15.8)

17.8 (15.1)

17.3 (14.7)

16.8 (14.1)

16.2 (13.5)

15.9 (13.2)

19.2 (16.8)

18.7 (16.3)

18.3 (15.8)

17.9 (15.4)

17.5 (15.0)

16.9 (14.3)

16.4 (13.7)

15.9 (13.2)

15.5 (12.7)

15.0 (12.3)

20

40

80

160

320

640

1000

2000

14

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Table 9. Noise in mV_RMSand (mV_PP

)

at AVDD = 3V, AVSS = 0V, and Internal Reference = 2.048V

DATA

RATE

(SPS)

PGA SETTING

1

2

4

8

16

32

64

128

5

10

2.50 (14.24)

3.09 (16.85)

4.55 (24.74)

5.06 (34.59)

6.63 (43.46)

9.75 (68.28)

19.22 (140.06)

1.32 (6.92)

1.69 (9.32)

2.19 (12.82)

2.39 (14.49)

3.28 (20.22)

4.89 (32.19)

9.80 (82.24)

0.67 (3.48)

0.82 (4.68)

1.07 (5.94)

1.27 (7.75)

1.79 (10.64)

2.36 (17.74)

4.81 (32.74)

0.32 (1.68)

0.42 (2.41)

0.55 (3.38)

0.66 (4.01)

0.89 (5.48)

1.26 (9.87)

2.47 (18.59)

3.40 (25.93)

0.17 (0.90)

0.23 (1.18)

0.28 (1.66)

0.36 (2.18)

0.47 (2.95)

0.65 (4.77)

1.27 (9.45)

1.76 (12.49)

2.66 (22.78)

2.92 (23.06)

0.09 (0.51)

0.11 (0.63)

0.16 (1.00)

0.21 (1.16)

0.29 (1.63)

0.40 (2.60)

0.71 (5.83)

1.02 (7.49)

1.45 (11.01)

1.68 (11.71)

0.08 (0.42)

0.11 (0.66)

0.15 (0.92)

0.21 (1.27)

0.28 (1.64)

0.40 (2.70)

0.50 (3.36)

0.71 (4.81)

0.93 (6.74)

1.19 (8.23)

0.07 (0.39)

0.10 (0.55)

0.14 (0.87)

0.15 (0.84)

0.21 (1.24)

0.30 (2.12)

0.43 (2.86)

0.60 (4.06)

0.74 (4.86)

1.05 (6.97)

20

40

80

160

320

640

1000

2000

27.07 (192.96) 13.54 (100.26) 6.88 (49.07)

40.83 (388.28) 20.39 (185.96) 10.39 (89.38) 5.09 (43.28)

42.06 (322.85) 21.15 (166.75) 10.66 (92.68) 5.61 (44.08)

Table 10. Effective Number of Bits From RMS and (Peak-to-Peak Noise)

at AVDD = 3V, AVSS = 0V, and Internal Reference = 2.048V

DATA

RATE

(SPS)

PGA SETTING

1

2

4

8

16

32

64

128

5

10

20.6 (18.1)

20.3 (17.9)

19.8 (17.3)

19.6 (16.9)

19.2 (16.5)

18.7 (15.9)

17.7 (14.8)

17.2 (14.4)

16.6 (13.4)

16.6 (13.6)

20.6 (18.2)

20.2 (17.7)

19.8 (17.3)

19.7 (17.1)

19.3 (16.6)

18.7 (16.0)

17.7 (14.6)

17.2 (14.3)

16.6 (13.4)

16.6 (13.6)

20.5 (18.2)

20.3 (17.7)

19.9 (17.4)

19.6 (17.0)

19.1 (16.6)

18.7 (15.8)

17.7 (14.9)

17.2 (14.3)

16.6 (13.5)

16.6 (13.4)

20.6 (18.2)

20.2 (17.7)

19.8 (17.2)

19.6 (17.0)

19.1 (16.5)

18.6 (15.7)

17.7 (14.7)

17.2 (14.3)

16.6 (13.5)

16.5 (13.5)

20.5 (18.1)

20.1 (17.7)

19.8 (17.2)

19.5 (16.8)

19.0 (16.4)

18.6 (15.7)

17.6 (14.7)

17.1 (14.3)

16.6 (13.5)

16.4 (13.4)

20.4 (17.9)

20.1 (17.6)

19.6 (17.0)

19.2 (16.8)

18.7 (16.3)

18.3 (15.6)

17.5 (14.4)

16.9 (14.1)

16.4 (13.5)

16.2 (13.4)

19.6 (17.2)

19.1 (16.6)

18.7 (16.1)

18.2 (15.6)

17.8 (15.3)

17.3 (14.5)

17.0 (14.2)

16.5 (13.7)

16.1 (13.2)

15.7 (12.9)

18.8 (16.3)

18.3 (15.8)

17.8 (15.2)

17.7 (15.2)

17.2 (14.7)

16.7 (13.9)

16.2 (13.4)

15.7 (12.9)

15.4 (12.7)

14.9 (12.2)

20

40

80

160

320

640

1000

2000

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TYPICAL CHARACTERISTICS

At T_A= +25°C, AVDD = 5V, V_REF= 2.5V, and AVSS = 0V, unless otherwise noted.

NOISE HISTOGRAM PLOT

1800

1600

1400

1200

1000

800

1800

1600

1400

1200

1000

800

AVDD = 5V

PGA = 1

AVDD = 5V

PGA = 32

Data Rate = 20SPS

12k Samples

s = 13

Data Rate = 20SPS

12k Samples

s = 19

600

400

200

0

(LSB)

Figure 5.

NOISE HISTOGRAM PLOT

Figure 6.

NOISE HISTOGRAM PLOT

1600

1400

1200

1000

800

600

400

200

0

1400

1200

1000

800

600

400

200

0

AVDD = 3.3V

PGA = 1

AVDD = 3.3V

PGA = 32

Data Rate = 20SPS

12k Samples

s = 18.5

Data Rate = 20SPS

12k Samples

s = 22

(LSB)

Figure 7.

Figure 8.

RMS NOISE vs INPUT SIGNAL

0.30

0.25

0.20

0.15

0.10

0.05

0

0.30

0.25

0.20

0.15

0.10

0.05

0

AVDD = 5V

PGA = 32

Data Rate = 5SPS

AVDD = 3.3V

PGA = 32

Data Rate = 5SPS

-100 -80 -60 -40 -20

20

40

60

80

100

-100 -80 -60 -40 -20

20

40

60

80

100

V_IN(% of FSR)

Figure 9.

Figure 10.

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TYPICAL CHARACTERISTICS (continued)

At T_A= +25°C, AVDD = 5V, V_REF= 2.5V, and AVSS = 0V, unless otherwise noted.

OFFSET vs TEMPERATURE

4

3

8

6

AVDD = 5V

Data Rate = 160SPS

AVDD = 5V

Data Rate = 20SPS

4

2

PGA = 32

1

PGA = 128

PGA = 32

0

PGA = 128

-2

-4

-6

-8

-1

-2

-3

PGA = 1

100

-40

-20

0

20

40

60

80

100

120

-40

-20

0

20

40

60

80

120

Temperature (°C)

Figure 11.

Figure 12.

OFFSET vs TEMPERATURE

8

15

10

5

AVDD = 5V

Data Rate = 640SPS

AVDD = 5V

Data Rate = 2kSPS

6

4

2

PGA = 32

0

-2

-4

-6

-8

-10

-12

-14

PGA = 32

0

PGA = 128

-5

-10

-15

PGA = 128

PGA = 1

-40

0

20

40

60

80

100

120

-40

-20

0

20

40

60

80

100

120

Temperature (°C)

Figure 13.

Figure 14.

OFFSET vs TEMPERATURE

4

3

5

4

AVDD = 3.3V

Data Rate = 160SPS

AVDD = 3.3V

Data Rate = 20SPS

PGA = 1

3

2

PGA = 32

1

0

-1

-2

-3

-4

-5

-6

PGA = 128

0

-1

-2

-3

PGA = 1

PGA = 32

PGA = 128

-40

0

20

40

60

80

100

120

-40

-20

0

20

40

60

80

100

120

Temperature (°C)

Figure 15.

Figure 16.

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TYPICAL CHARACTERISTICS (continued)

At T_A= +25°C, AVDD = 5V, V_REF= 2.5V, and AVSS = 0V, unless otherwise noted.

OFFSET vs TEMPERATURE

10

8

6

AVDD = 3.3V

Data Rate = 640SPS

AVDD = 3.3V

Data Rate = 2kSPS

6

PGA = 1

4

PGA = 128

PGA = 32

2

0

PGA = 32

-2

-4

-6

-8

-2

-4

-6

PGA = 128

-40

-20

0

20

40

60

80

100

120

-40

-20

0

20

40

60

80

100

120

Temperature (°C)

Figure 17.

Figure 18.

GAIN vs TEMPERATURE

0.05

0.04

0.03

0.02

0.01

0

0.03

0.02

0.01

0

AVDD = 5V

Data Rate = 160SPS

PGA = 1

PGA = 32

-0.01

-0.02

-0.03

-0.04

-0.01

-0.02

-0.03

-0.04

-0.05

PGA = 32

PGA = 128

AVDD = 5V

Data Rate = 20SPS

-40

-20

0

20

40

60

80

100

120

-40

-20

0

20

40

60

80

100

120

Temperature (°C)

Figure 19.

Figure 20.

GAIN vs TEMPERATURE

0.03

0.02

0.01

0

0.02

0.01

0

AVDD = 5V

Data Rate = 2kSPS

Data Rate = 640SPS

PGA = 1

PGA = 128

PGA = 32

-0.01

-0.02

-0.03

-0.04

PGA = 128

PGA = 32

-0.01

-0.02

-0.03

-0.04

-40

-20

0

20

40

60

80

100

120

-40

-20

0

20

40

60

80

100

120

Temperature (°C)

Figure 21.

Figure 22.

18

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TYPICAL CHARACTERISTICS (continued)

At T_A= +25°C, AVDD = 5V, V_REF= 2.5V, and AVSS = 0V, unless otherwise noted.

GAIN vs TEMPERATURE

0.04

0.03

0.02

0.01

0

0.04

0.03

0.02

0.01

0

AVDD = 3.3V

Data Rate = 20SPS

AVDD = 3.3V

Data Rate = 160SPS

PGA = 128

PGA = 32

PGA = 1

-0.01

-0.02

-0.03

-0.04

-0.01

-0.02

-0.03

-0.04

PGA = 32

PGA = 128

-40

-20

0

20

40

60

80

100

120

-40

-20

0

20

40

60

80

100

120

Temperature (°C)

Figure 23.

Figure 24.

GAIN vs TEMPERATURE

0.05

0.04

0.03

0.02

0.01

0

0.05

0.04

0.03

0.02

0.01

0

AVDD = 3.3V

Data Rate = 640SPS

AVDD = 3.3V

Data Rate = 2kSPS

PGA = 128

PGA = 32

PGA = 1

-0.01

-0.02

-0.03

-0.04

-0.05

-0.01

-0.02

-0.03

-0.04

-0.05

PGA = 1

PGA = 32

-40

-20

0

20

40

60

80

100

120

-40

-20

0

20

40

60

80

100

120

Temperature (°C)

Figure 25.

Figure 26.

ANALOG CURRENT vs DATA RATE

DIGITAL CURRENT vs DATA RATE

600

550

500

450

400

350

300

250

200

150

100

290

270

250

230

210

190

170

AVDD = 5V

DVDD = 5V

AVDD = 3.3V

DVDD = 3.3V

5

10

20

40

80 160 320 640 1000 2000

5

10

20

40

80 160 320 640 1000 2000

Data Rate (SPS)

Figure 27.

Figure 28.

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TYPICAL CHARACTERISTICS (continued)

At T_A= +25°C, AVDD = 5V, V_REF= 2.5V, and AVSS = 0V, unless otherwise noted.

ANALOG CURRENT vs TEMPERATURE

DIGITAL CURRENT vs TEMPERATURE

800

700

600

500

400

300

200

100

0

330

310

290

270

250

230

210

190

DVDD = 5V

AVDD = 5V

2kSPS

320/640/1kSPS

40/80/160SPS

320/640/1kSPS

5/10/20SPS

40/80/160SPS

5/10/20SPS

-40

-20

0

20

40

60

80

100

120

-40

-20

0

20

40

60

80

100

120

Temperature (°C)

Figure 29.

Figure 30.

ANALOG CURRENT vs TEMPERATURE

DIGITAL CURRENT vs TEMPERATURE

700

600

500

400

300

200

100

0

310

290

270

250

230

210

190

2kSPS

AVDD = 3.3V

DVDD = 3.3V

2kSPS

320/640/1kSPS

40/80/160SPS

320/640/1kSPS

5/10/20SPS

40/80/160SPS

5/10/20SPS

-20

-40

-20

0

20

40

60

80

100

120

-40

0

20

40

60

80

100

120

Temperature (°C)

Figure 31.

Figure 32.

INTEGRAL NONLINEARITY vs INPUT SIGNAL

8

6

8

6

PGA = 32

Data Rate = 20SPS

PGA = 1

Data Rate = 20SPS

4

-40°C

-10°C

2

-10°C

-40°C

0

-2

-4

-6

-8

-10

-2

-4

-6

-8

+25°C

+105°C

-100

-50

0

50

100

-100

-50

0

50

100

V_IN(% of FSR)

Figure 33.

Figure 34.

20

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TYPICAL CHARACTERISTICS (continued)

At T_A= +25°C, AVDD = 5V, V_REF= 2.5V, and AVSS = 0V, unless otherwise noted.

INTEGRAL NONLINEARITY vs INPUT SIGNAL

8

6

8

6

+105°C

-40°C

-10°C

PGA = 128

Data Rate = 20SPS

4

+25°C

-40°C

-10°C

2

0

-2

-4

-6

-8

-2

-4

-6

-8

+25°C

+105°C

PGA = 1

Data Rate = 2kSPS

-100

-50

0

50

100

-100

-50

0

50

100

V_IN(% of FSR)

Figure 35.

Figure 36.

DATA RATE ERROR vs TEMPERATURE

(Using Internal Oscillator)

CMRR vs TEMPERATURE

130

125

120

115

110

105

100

95

3.0

2.5

2.0

PGA = 32

1.5

1.0

DVDD = 5V

0.5

PGA = 128

0

DVDD = 3.3V

-0.5

-1.0

-1.5

-2.0

-2.5

-3.0

PGA = 1

90

85

80

-40

-20

0

20

40

60

80

100

120

-40

-20

0

20

40

60

80

100

120

Temperature (°C)

Figure 37.

Figure 38.

INTERNAL V_REFvs TEMPERATURE

IDAC LINE REGULATION

2.050

2.049

2.048

2.047

2.046

1.002

1.001

1.000

0.999

0.998

0.997

0.996

0.995

0.994

0.993

0.992

0.991

14 Units

50mA

100mA

500mA

250mA

750mA

IDAC Current Settings

1mA

1.5mA

3.5

-40

-20

0

20

40

60

80

100

120

2.0

2.5

3.0

4.0

AVDD (V)

4.5

5.0

5.5

6.0

Temperature (°C)

Figure 39.

Figure 40.

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TYPICAL CHARACTERISTICS (continued)

At T_A= +25°C, AVDD = 5V, V_REF= 2.5V, and AVSS = 0V, unless otherwise noted.

IDAC DRIFT

POWER-SUPPLY REJECTION vs GAIN

0.004

0.003

0.002

0.001

0

8

7

6

5

4

3

2

1

0

1.5mA Setting, 10 Units

2000SPS

320/640/1000SPS

-0.001

-0.002

-0.003

-0.004

40/80/160SPS

5/10/20SPS

-40

-20

0

20

40

60

80

100

120

1

2

4

8

16

32

64

128

Temperature (°C)

Gain

Figure 41.

Figure 42.

INTERNAL V_REFINITIAL ACCURACY HISTOGRAM

IDAC INITIAL ACCURACY HISTOGRAM

700

200

180

160

140

120

100

80

2280 Units

600

500

400

300

200

100

0

60

40

20

0

Initial Accuracy (V)

Initial Accuracy (%)

Figure 43.

Figure 44.

IDAC MISMATCH HISTOGRAM

350

300

250

200

150

100

50

2280 Units

0

Initial Accuracy (%)

Figure 45.

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GENERAL DESCRIPTION

OVERVIEW

The ADS1247 and ADS1248 also include a flexible

input multiplexer with system monitoring capability

and general-purpose I/O settings, a very low-drift

voltage reference, and two matched current sources

for sensor excitation. Figure 46 and Figure 47 show

the various functions incorporated in each device.

The ADS1246, ADS1247 and ADS1248 are highly

integrated 24-bit data converters. They include a

low-noise, high-impedance programmable gain

amplifier (PGA), a delta-sigma (ΔΣ) ADC with an

adjustable single-cycle settling digital filter, internal

oscillator, and a simple but flexible SPI-compatible

serial interface.

REFP REFN

DVDD

AVDD

Burnout

Detect

ADS1246

V_BIAS

SCLK

DIN

Serial

DRDY

Interface

3rd Order

DS

Adjustable

Digital

Filter

AIN0

AIN1

Input

Mux

PGA

DOUT/DRDY

CS

and

Modulator

Control

START

RESET

Internal Oscillator

Burnout

Detect

AVSS

CLK

DGND

Figure 46. ADS1246 Diagram

ADS1248 Only

REFP0/ REFN0/

GPIO0 GPIO1 REFP1 REFN1 VREFOUT VREFCOM

DVDD

AVDD

Burnout

Detect

ADS1247

ADS1248

Voltage

VREF Mux

V_BIAS

Reference

GPIO

SCLK

AIN0/IEXC

AIN1/IEXC

System

Monitor

DIN

Serial

Interface

and

DRDY

DOUT/DRDY

CS

AIN2/IEXC/GPIO2

AIN3/IEXC/GPIO3

3rd Order

DS

Adjustable

Digital

Filter

Input

Mux

PGA

Modulator

AIN4/IEXC/GPIO4

AIN5/IEXC/GPIO5

Control

START

RESET

Dual

Current

DACs

AIN6/IEXC/GPIO6

AIN7/IEXC/GPIO7

Internal Oscillator

ADS1248 Only

Burnout

Detect

AVSS IEXC1 IEXC2

CLK

DGND

ADS1248 Only

Figure 47. ADS1247, ADS1248 Diagram

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ADC INPUT AND MULTIPLEXER

Any analog input pin can be selected as the positive

input or negative input through the MUX0 register.

The ADS1246/7/8 have a true fully differential mode,

meaning that the input signal range can be from

The ADS1246/7/8 ADC measures the input signal

through the onboard PGA. All analog inputs are

connected to the internal AIN_Por AIN_Nanalog inputs

through the analog multiplexer. A block diagram of

the analog input multiplexer is shown in Figure 48.

–2.5V to +2.5V (when AVDD

AVSS = –2.5V).

=

2.5V and

Through the input multiplexer, the ambient

temperature (internal temperature sensor), AVDD,

DVDD, and external reference can all be selected for

measurement. Refer to the System Monitor section

for details.

The input multiplexer connects to eight (ADS1248),

four (ADS1247), or two (ADS1246) analog inputs that

can be configured as single-ended inputs, differential

inputs, or in a combination of single-ended and

differential inputs. The multiplexer also allows the

on-chip excitation current and/or bias voltage to be

selected to a specific channel.

On the ADS1247 and ADS1248, the analog inputs

can also be configured as general-purpose

inputs/outputs (GPIOs). See the General-Purpose

Digital I/O section for more details.

AVDD

IDAC2 IDAC1

System Monitors

AVSS

AVDD

VBIAS

AVDD

AIN0

AIN1

Temperature

Diode

VREFP

VREFN

ADS1247/48 Only

VREFP1/4

VREFN1/4

AVSS

AVDD

VBIAS

VREFP0/4

VREFN0/4

AIN2

AVDD

AVDD/4

AVSS/4

AIN3

DVDD/4

DGND/4

ADS1248 Only

AVSS

AVDD

VBIAS

AIN4

AIN5

AVDD

Burnout Current Source

(0.5mA, 2mA, 10mA)

AIN_P

AIN_N

To

PGA

AVSS

AVDD

VBIAS

ADC

AIN6

AIN7

Burnout Current Source

(0.5mA, 2mA, 10mA)

AVSS

Figure 48. Analog Input Multiplexer Circuit

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ESD diodes protect the ADC inputs. To prevent these

diodes from turning on, make sure the voltages on

the input pins do not go below AVSS by more than

100mV, and do not exceed AVDD by more than

100mV, as shown in Equation 2. Note that the same

caution is true if the inputs are configured to be

GPIOs.

VOLTAGE REFERENCE INPUT

The voltage reference for the ADS1246/7/8 is the

differential voltage between REFP and REFN:

V_REF= V_REFP– V_REFN

In the case of the ADS1246, these pins are dedicated

inputs. For the ADS1247 and ADS1248, there is a

multiplexer that selects the reference inputs, as

shown in Figure 49. The reference input uses a buffer

to increase the input impedance.

AVSS – 100mV < (AINX) < AVDD + 100mV

(2)

Settling Time for Channel Multiplexing

The ADS1246/7/8 is a true single-cycle settling ΔΣ

converter. The first data available after the start of a

conversion are fully settled and valid for use. The

time required to settle is roughly equal to the inverse

of the data rate. The exact time depends on the

specific data rate and the operation that resulted in

the start of a conversion; see Table 20 for specific

values.

As with the analog inputs, REFP0 and REFN0 can be

configured as digital I/Os on the ADS1247/8.

ADS1248 Only

REFP1 REFN1 REFP0 REFN0

VREFOUT VREFCOM

ANALOG INPUT IMPEDANCE

Internal

Voltage

Reference Multiplexer

The ADS1246/7/8 inputs are buffered through a

high-impedance PGA before they reach the ΔΣ

modulator. For the majority of applications, the input

current leakage is minimal and can be neglected.

However, because the PGA is chopper-stabilized for

noise and offset performance, the input impedance is

best described as small absolute input current. The

absolute current leakage for selected channels is

approximately proportional to the selected modulator

clock. Table 11 shows the typical values for these

currents with a differential voltage coefficient and the

corresponding input impedances over data rate.

Reference

REFP

REFN

ADC

Figure 49. Reference Input Multiplexer

The reference input circuit has ESD diodes to protect

the inputs. To prevent the diodes from turning on,

make sure the voltage on the reference input pin is

not less than AVSS – 100mV, and does not exceed

AVDD + 100mV, as shown in Equation 3:

AVSS – 100mV < (V_REFPor V_REFN) < AVDD + 100mV

(3)

Table 11. Typical Values for Analog Input Current Over Data Rate⁽¹⁾

CONDITION

ABSOLUTE INPUT CURRENT

EFFECTIVE INPUT IMPEDANCE

DR = 5SPS, 10SPS, 20SPS

DR = 40SPS, 80SPS, 160SPS

DR = 320SPS, 640SPS, 1kSPS

DR = 2kSPS

± (0.5nA + 0.1nA/V)

± (2nA + 0.5nA/V)

± (4nA + 1nA/V)

± (8nA + 2nA/V)

5000MΩ

1200MΩ

600MΩ

300MΩ

(1) Input current with V_CM= 2.5V. T_A= +25°C, AVDD = 5V, and AVSS = 0V.

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LOW-NOISE PGA

MODULATOR

The ADS1246/7/8 feature a low-drift, low-noise, high

input impedance programmable gain amplifier (PGA).

The PGA can be set to gain of 1, 2, 4, 8, 16, 32, 64,

or 128 by register SYS0. A simplified diagram of the

PGA is shown in Figure 50.

A third-order modulator is used in the ADS1246/7/8.

The modulator converts the analog input voltage into

a pulse code modulated (PCM) data stream. To save

power, the modulator clock runs from 32kHz up to

512kHz for different data rates, as shown in Table 12.

The PGA consists of two chopper-stabilized

amplifiers (A1 and A2) and a resistor feedback

network that sets the gain of the PGA. The PGA input

is equipped with an electromagnetic interference

(EMI) filter, as shown in Figure 50. Note that as with

any PGA, it is necessary to ensure that the input

voltage stays within the specified common-mode

input range specified in the Electrical Characteristics.

The common-mode input (V_CMI) must be within the

range shown in Equation 4:

Table 12. Modulator Clock Frequency for Different

Data Rates

DATA RATE

(SPS)

f_MOD

(kHz)

5, 10, 20

40, 80, 160

320, 640, 1000

2000

32

128

256

512

(V_IN)(Gain)

AVSS + 0.1V +

£ V_CMI

£

) (

AVDD - 0.1V -

DIGITAL FILTER

(

)

2

(4)

The ADS1246/7/8 use linear-phase finite impulse

response (FIR) digital filters that can be adjusted for

different output data rates. The digital filter always

settles in a single cycle.

454W

AIN_P

7.5pF

A1

Table 13 shows the exact data rates when an

external oscillator equal to 4.096MHz is used. Also

shown is the signal –3dB bandwidth, and the 50Hz

and 60Hz attenuation. For good 50Hz or 60Hz

rejection, use a data rate of 20SPS or slower.

R

7.5pF

C

R

ADC

The frequency responses of the digital filter are

shown in Figure 51 to Figure 61. Figure 54 shows a

detailed view of the filter frequency response from

48Hz to 62Hz for a 20SPS data rate. All filter plots

are generated with 4.096MHz external clock.

7.5pF

A2

454W

AIN_N

7.5pF

Figure 50. Simplified Diagram of the PGA

Table 13. Digital Filter Specifications⁽¹⁾

ATTENUATION

NOMINAL

ACTUAL

–3dB

DATA RATE DATA RATE

BANDWIDTH

2.26Hz

4.76Hz

14.8Hz

9.03Hz

19.8Hz

118Hz

f_IN= 50Hz ±0.3Hz

–106dB

f_IN= 60Hz ±0.3Hz

f_IN= 50Hz ±1Hz

–81dB

f_IN= 60Hz ±1Hz

–69dB

5SPS

10SPS

5.018SPS

10.037SPS

20.075SPS

40.15SPS

80.301SPS

160.6SPS

321.608SPS

643.21SPS

1000SPS

–74dB

–106dB

–80dB

–69dB

20SPS

–71dB

–66dB

–68dB

40SPS

80SPS

160SPS

320SPS

640SPS

1000SPS

2000SPS

154Hz

495Hz

732Hz

2000SPS

1465Hz

(1) Values shown for f_OSC= 4.096MHz.

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0

-20

-60

-70

-40

-80

-60

-90

-80

-100

-110

-120

-100

-120

0

20

40

60

80 100 120 140 160 180 200

Frequency (Hz)

48

50

52

54

56

58

60

62

Frequency (Hz)

Figure 51. Filter Profile with Data Rate = 5SPS

Figure 54. Detailed View of Filter Profile with Data

Rate = 20SPS between 48Hz and 62Hz

0

-20

0

-20

-40

-60

-80

-100

-120

-100

-120

0

20

40

60

80 100 120 140 160 180 200

Frequency (Hz)

0

200 400 600 800 1000 1200 1400 1600 1800 2000

Frequency (Hz)

Figure 52. Filter Profile with Data Rate = 10SPS

Figure 55. Filter Profile with Data Rate = 40SPS

0

-20

0

-20

-40

-60

-80

-100

-120

-100

-120

0

20

40

60

80 100 120 140 160 180 200

Frequency (Hz)

0

200 400 600 800 1000 1200 1400 1600 1800 2000

Frequency (Hz)

Figure 53. Filter Profile with Data Rate = 20SPS

Figure 56. Filter Profile with Data Rate = 80SPS

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0

-20

0

-20

-40

-60

-80

-100

-120

-100

-120

0

200 400 600 800 1000 1200 1400 1600 1800 2000

Frequency (Hz)

0

1

2

3

4

5

6

7

8

9

10

Frequency (kHz)

Figure 57. Filter Profile with Data Rate = 160SPS

Figure 60. Filter Profile with Data Rate = 1kSPS

0

-20

0

-20

-40

-60

-80

-100

-120

-100

-120

0

500 1000 1500 2000 2500 3000 3500 4000 4500 5000

Frequency (Hz)

0

2

4

6

8

10

12

14

16

18

20

Frequency (kHz)

Figure 58. Filter Profile with Data Rate = 320SPS

Figure 61. Filter Profile with Data Rate = 2kSPS

CLOCK SOURCE

0

-20

The ADS1246/7/8 can use either the internal

oscillator or an external clock. Connect the CLK pin to

DGND before power-on or reset to activate the

internal oscillator. Connecting an external clock to the

CLK pin at any time deactivates the internal oscillator,

with the device then operating on the external clock.

After the device switches to the external clock, it

cannot be switched back to the internal oscillator

without cycling the power supplies or resetting the

device.

-40

-60

-80

-100

-120

0

500 1000 1500 2000 2500 3000 3500 4000 4500 5000

Frequency (Hz)

Figure 59. Filter Profile with Data Rate = 640SPS

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INTERNAL VOLTAGE REFERENCE

EXCITATION CURRENT SOURCE DACS

The ADS1247/8 includes an onboard voltage

reference with a low temperature coefficient. The

output of the voltage reference is 2.048V with the

capability of both sourcing and sinking up to 10mA of

current.

The ADS1247/8 provide two matched excitation

current sources for RTD applications. For three- or

four-wire RTD applications, the matched current

sources can be used to cancel the errors caused by

sensor lead resistance. The output current of the

current source DACs can be programmed to 50mA,

100mA, 250mA, 500mA, 750mA, 1000mA, or 1500mA.

The voltage reference must have

a capacitor

connected between VREFOUT and VREFCOM. The

value of the capacitance should be in the range of

1mF to 47mF. Large values provide more filtering of

the reference; however, the turn-on time increases

with capacitance, as shown in Table 14. For stability

reasons, VREFCOM must have a path with an

impedance less than 10Ω to ac ground nodes, such

as GND (for a 0V to 5V analog power supply), or

AVSS (for a ±2.5V analog power supply). In case this

impedance is higher than 10Ω, a capacitor of at least

0.1mF should be connected between VREFCOM and

an ac ground node (for example, GND). Note that

because it takes time for the voltage reference to

settle to the final voltage, care must be taken when

the device is turned off between conversions. Allow

adequate time for the internal reference to fully settle.

The two matched current sources can be connected

to dedicated current output pins IOUT1 and IOUT2

(ADS1248 only), or to any AIN pin (ADS1247/8); refer

to the ADS1247/48 Detailed Register Definitions

section for more information. It is possible to connect

both current sources to the same pin. Note that the

internal reference must be turned on and properly

compensated when using the excitation current

source DACs.

SENSOR DETECTION

The ADS1246/7/8 provide

a selectable current

(0.5mA, 2mA, or 10mA) to help detect a possible

sensor malfunction.

When enabled, two burnout current sources flow

through the selected pair of analog inputs to the

sensor. One sources the current to the positive input

channel, and the other sinks the same current from

the negative input channel.

Table 14. Internal Reference Settling Time

VREFOUT

CAPACITOR

SETTLING

ERROR

TIME TO REACH THE

SETTLING ERROR

±0.5%

±0.1%

±0.5%

±0.1%

±0.5%

±0.1%

70ms

110ms

290ms

375ms

2.2ms

2.4ms

1mF

4.7mF

47mF

When the burnout current sources are enabled, a

full-scale reading may indicate an open circuit in the

front-end sensor, or that the sensor is overloaded. It

may also indicate that the reference voltage is

absent.

A

near-zero reading may indicate

a

short-circuit in the sensor.

The onboard reference is controlled by the registers;

by default, it is off after startup (see the ADS1247/48

Detailed Register Definitions section for more details).

Therefore, the internal reference must first be turned

on and then connected via the internal reference

multiplexer. Because the onboard reference is used

to generate the current reference for the excitation

current sources, it must be turned on before the

excitation currents become available.

BIAS VOLTAGE GENERATION

A selectable bias voltage is provided for use with

ungrounded thermocouples. The bias voltage is

(AVDD + AVSS)/2 and can applied to any analog

input channel through internal input multiplexer. The

bias voltage turn-on times for different sensor

capacitances are listed in Table 15.

Table 15. Bias Voltage Settling Time

SENSOR CAPACITANCE

SETTLING TIME

220ms

0.1mF

1mF

2.2ms

10mF

200mF

22ms

450ms

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Power-Supply Monitor

GENERAL-PURPOSE DIGITAL I/O

The system monitor can measure the analog or

digital power supply. When measuring the power

supply, the resulting conversion is approximately 1/4

of the actual power supply voltage.

The ADS1248 has eight pins and the ADS1247 has

four pins that serve a dual purpose as either analog

inputs or general-purpose digital inputs/outputs

(GPIOs).

Conversion Result = (V_SP/4)/V_REF

(5)

Figure 62 shows a diagram of how these functions

are combined onto a single pin. Note that when the

pin is configured as a GPIO, the corresponding logic

is powered from AVDD and AVSS. When the

ADS1247/8 are operated with bipolar analog

supplies, the GPIO outputs bipolar voltages. Care

must be taken loading the GPIO pins when used as

outputs because large currents can cause droop or

noise on the analog supplies.

Where V_SPis the selected supply to be measured.

External Voltage Reference Monitor

The ADS1246/7/8 can be selected to measure the

external voltage reference. In this configuration, the

monitored external voltage reference is connected to

the analog input. The result (conversion code) is

approximately 1/4 of the actual reference voltage.

Conversion Result = (V_REX/4)/V_REF

(6)

IOCFG

IODIR

Where V_REXis the external reference to be

monitored.

NOTE: The internal reference voltage must be

enabled when measuring an external voltage

reference using the system monitor.

DIO WRITE

REFx0/GPIOx

AINx/GPIOx

To Analog Mux

Ambient Temperature Monitor

DIO READ

On-chip

diodes

provide

temperature-sensing

capability. When selecting the temperature monitor

function, the anodes of two diodes are connected to

the ADC. Typically, the difference in diode voltage is

118mV at +25°C with a temperature coefficient of

405mV/°C.

Figure 62. Analog/Data Interface Pin

SYSTEM MONITOR

Note that when the onboard temperature monitor is

selected, the PGA is automatically set to '1'.

However, the PGA register bits in are not affected

and the PGA returns to its set value when the

temperature monitor is turned off.

The ADS1247 and ADS1248 provide a system

monitor function. This function can measure the

analog power supply, digital power supply, external

voltage reference, or ambient temperature. Note that

the system monitor function provides a coarse result.

When the system monitor is enabled, the analog

inputs are disconnected.

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CALIBRATION

full-scale calibration register can correct gain errors

> 1 (with gain scaling < 1), make sure to avoid

overloading the analog inputs. The default or reset

value of FSC depends on the PGA setting. A different

factory-trimmed FSC Reset value is stored for each

PGA setting which provides outstanding gain

accuracy over all the ADS1246/7/8 input ranges.

Note: The factory-trimmed FSC reset value loads

automatically loaded whenever the PGA setting

changes.

The conversion data are scaled by offset and gain

registers before yielding the final output code. As

shown in Figure 63, the output of the digital filter is

first subtracted by the offset register (OSC) and then

multiplied by the full-scale register (FSC). A digital

clipping circuit ensures that the output code does not

exceed 24 bits. Equation 7 shows the scaling.

+

Output Data

Clipped to 24 Bits

Final

Output

Table 17. Gain Correction Factor versus

Full-Scale Calibration Register Setting

´

ADC

S

-

FULL-SCALE REGISTER

800000h

GAIN SCALING

OFC

Register

FSC Register

400000h

2.0

1.0

0.5

0

400000h

200000h

Figure 63. Calibration Block Diagram

FSC[2:0]

Final Output Data = (Input - OFC[2:0]) ´

000000h

400000h

Calibration Commands

(7)

The ADS1246/7/8 provide commands for three types

of calibration: system gain calibration, system offset

calibration and self offset calibration. Where absolute

accuracy is needed, it is recommended that

calibration be performed after power on, a change in

temperature, a change of PGA and in some cases a

change in channel. At the completion of calibration,

the DRDY signal goes low indicating the calibration is

finished. The first data after calibration are always

valid. If the START pin is taken low or a SLEEP

command is issued after any calibration command,

the devices goes to sleep after completing calibration.

The values of the offset and full-scale registers are

set by writing to them directly, or they are set

automatically by calibration commands.

Offset Calibration Register: OFC[2:0]

The offset calibration is a 24-bit word, composed of

three 8-bit registers. The offset is in twos complement

format with a maximum positive value of 7FFFFFh

and a maximum negative value of 800000h. This

value is subtracted from the conversion data. A

register value of 000000h provides no offset

correction. Note that while the offset calibration

register value can correct offsets ranging from –FS to

+FS (as shown in Table 16), make sure to avoid

overloading the analog inputs.

System Gain Calibration

System gain calibration corrects for gain error in the

signal path. The system gain calibration is initiated by

sending the SYSGCAL command while applying a

full-scale input to the selected analog inputs.

Afterwards the full-scale calibration register (FSC) is

updated. When a system gain calibration command is

issued, the ADS1246/7/8 stop the current conversion

and start the calibration procedure immediately.

Table 16. Final Output Code versus Offset

Calibration Register Setting

FINAL OUTPUT CODE WITH

OFFSET REGISTER

7FFFFFh

V_IN= 0

8000000h

FFFFFFh

000000h

000001h

7FFFFFh

000001h

System Offset and Self Offset Calibration

000000h

FFFFFFh

System offset calibration corrects both internal and

external offset errors. The system offset calibration is

initiated by sending the SYSGOCAL command while

applying a zero differential input (V_IN= 0) to the

selected analog inputs. The self offset calibration is

initiated by sending the SELFOCAL command.

During self offset calibration, the selected inputs are

disconnected from the internal circuitry and a zero

differential signal is applied internally. With both offset

8000000h

1. Excludes effects of noise and inherent offset

errors.

Full-Scale Calibration Register: FSC[2:0]

The full-scale or gain calibration is a 24-bit word

composed of three 8-bit registers. The full-scale

calibration value is 24-bit, straight binary, normalized

to 1.0 at code 400000h. Table 17 summarizes the

scaling of the full-scale register. Note that while the

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calibrations the offset calibration register (OFC) is

updated afterwards. When either offset calibration

command is issued, the ADS1246/7/8 stop the

current conversion and start the calibration procedure

immediately.

ADC SLEEP MODE

Power consumption can be dramatically reduced by

placing the ADS1246/7/8 into sleep mode. There are

two ways to put the device into sleep mode: the sleep

command (SLEEP) and through the START pin.

Calibration Timing

During sleep mode, the internal reference status

depends on the setting of the VREFCON bits in the

MUX1 register; see the Register Descriptions section

for details.

When calibration is initiated, the device performs 16

consecutive data conversions and averages the

results to calculate the calibration value. This

provides a more accurate calibration value. The time

required for calibration is shown in Table 18 and can

be calculated using Equation 8:

ADC CONTROL

ADC Conversion Control

50

32

16

+

Calibration Time =

The START pin provides easy and precise control of

conversions. Pulse the START pin high to begin a

conversion, as shown in Figure 64 and Table 19. The

conversion completion is indicated by the

DOUT/DRDY pin going low. When the conversion

completes, the ADS1246/7/8 automatically shuts

down to save power. During shutdown, the

conversion result can be retrieved; however, START

must be taken high before communicating with the

configuration registers. The device stays shut down

until the START pin is once again taken high to begin

a new conversion. When the START pin is taken

back high again, the decimation filter is held in a

reset state for 32 modulator clock cycles internally to

allow the analog circuits to settle.

f_OSC

f_MOD

f_DATA

(8)

Table 18. Calibration Time versus Data Rate

DATA RATE (SPS)

CALIBRATION TIME (ms)

5

3201.01

1601.01

801.012

400.26

200.26

100.14

50.14

10

20

40

80

160

320

640

1000

2000

25.14

16.14

The ADS1246/7/8 can be configured to convert

continuously by holding the START pin high, as

shown in Figure 65. With the START pin held high,

the ADC converts the selected input channels

continuously. This configuration continues until the

START pin is taken low.

8.07

1. For f_OSC= 4.096MHz.

ADC POWER-UP

When DVDD is pulled up, the internal power-on reset

module generates a pulse that resets all digital

circuitry. All the digital circuits are held in a reset

state for 2¹⁶system clocks to allow the analog circuits

and the internal digital power supply to settle. SPI

communication cannot occur until the internal reset is

released.

The START pin can also be used to perform the

synchronized measurement for the multi-channel

applications by pulsing the START pin.

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t_START

START

t_CONV

DOUT/DRDY

SCLK

1

2

3

24

DRDY

ADS1246/47/48

Converting

Shutdown

Status

Figure 64. Timing for Single Conversion Using START Pin

Table 19. START Pin Conversion Times for Figure 64

SYMBOL

DESCRIPTION

DATA RATE (SPS)

VALUE

200.295

100.644

50.825

25.169

12.716

6.489

UNIT

ms

5

10

20

40

80

Time from START pulse to DRDY and

DOUT/DRDY going low

t_CONV

160

320

640

1000

2000

3.247

1.692

1.138

0.575

START

Data Ready

DOUT/DRDY

ADS1246/47/48

Converting

Status

NOTE: SCLK held low in this example.

Figure 65. Timing for Conversion with START Pin High

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RESET

In the event of an overloaded state, care must also

be taken to ensure single cycle settling into the next

When the RESET pin goes low, the device is

immediately reset. All the registers are restored to

default values. The device stays in reset mode as

long as the RESET pin stays low. When it goes high,

the ADC comes out of reset mode and is able to

convert data. After the RESET pin goes high, and

when the system clock frequency is 4.096MHz, the

digital filter and the registers are held in a reset state

for 0.6ms when f_OSC= 4.096MHz. Therefore, valid

SPI communication can only be resumed 0.6ms after

the RESET pin goes high; see Figure 4. When the

RESET pin goes low, the clock selection is reset to

the internal oscillator.

cycle. Because the ADS1246/7/8 implement

a

chopper-stabilized PGA, changing data rates during

an overload state can cause the chopper to become

unstable. This instability results in slow settling time.

To prevent this slow settling, always change the PGA

setting or MUX setting to a non-overloaded state

before changing the data rate.

Digital Filter Reset Operation

Apart from the RESET command and the RESET pin,

the digital filter is reset automatically when either a

write operation to the MUX0, VBIAS, MUX1, or SYS0

registers is performed, when a SYNC command is

issued, or the START pin is taken high.

Channel Cycling and Overload Recovery

When cycling through channels, care must be taken

when configuring the ADS1246/7/8 to ensure that

settling occurs within one cycle. For setups that

simply cycle through MUX channels, but do not

change PGA and data rate settings, simply changing

the MUX0 register is sufficient. However, when

changing PGA and data rate settings it is important to

ensure that an overloaded condition cannot occur

during the transmission. When configuration data are

transferred to the ADS1246/7/8, new settings become

active at the end of each byte sent. Therefore, a brief

overload condition can occur during the transmission

of configuration data after the completion of the

MUX0 byte and before completion of the SYS0 byte.

This temporary overload can result in intermittent

incorrect readings. To ensure that an overload does

not occur, it may be necessary to split the

communication into two separate communications

allowing the change of the SYS0 register before the

change of the MUX0 register.

The filter is reset two system clocks after the last bit

of the SYNC command is sent. The reset pulse

created internally lasts for two multiplier clock cycles.

If any write operation takes place in the MUX0

register, the filter is reset regardless of whether the

value changed or not. Internally, the filter pulse lasts

for two system clock periods. If any write activity

takes place in the VBIAS, MUX1, or SYS0 registers,

the filter is reset as well, regardless of whether the

value changed or not. The reset pulse lasts for 32

modulator clocks after the write operation. If there are

multiple write operations, the resulting reset pulse

may be viewed as the ANDed result of the different

active low pulses created individually by each action.

Table 20 shows the conversion time after a filter

reset. Note that this time depends on the operation

initiating the reset. Also, the first conversion after a

filter reset has a slightly different time than the

second and subsequent conversions.

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Table 20. Data Conversion Time

FIRST DATA CONVERSION TIME AFTER FILTER RESET

HARDWARE RESET, RESET

COMMAND, START PIN HIGH,

WAKEUP COMMAND, VBIAS,

MUX1, or SYS0 REGISTER

WRITE

SECOND AND SUBSEQUENT

CONVERSION TIME AFTER

FILTER RESET

SYNC COMMAND, MUX0

REGISTER WRITE

NO. OF

SYSTEM

CLOCK

NO. OF

SYSTEM

CLOCK

NO. OF

SYSTEM

CLOCK

NOMINAL

DATA RATE

(SPS)

EXACT DATA

RATE

(SPS)

(ms)⁽¹⁾

199.264

99.639

49.827

24.920

12.467

6.241

CYCLES

816188

408124

204092

102076

51068

25564

12796

6428

(ms)⁽¹⁾

200.260

100.635

50.822

25.172

12.719

6.492

CYCLES

820265

412201

208169

103106

52098

26594

13314

6946

(ms)

199.250

99.625

49.812

24.906

12.453

6.226

CYCLES

816128

408064

204032

102016

51008

25504

12736

6368

5

5.019

10.038

10

20

20.075

40

40.151

80

80.301

160

320

640

1000

2000

160.602

321.608

643.216

1000.000

2000.000

3.124

3.250

3.109

1.569

1.695

1.554

1.014

4156

1.141

4674

1.000

4096

0.514

2108

0.578

2370

0.500

2048

(1) For f_OSC= 4.096MHz.

command and the RDATA command. These

limitations are explained in detail in the SPI

Commands section of this data sheet. For the basic

serial interface timing characteristics, see Figure 1

and Figure 2 of this datasheet.

Data Format

The ADS1246/7/8 output 24 bits of data in binary

twos complement format. The least significant bit

(LSB) has a weight of (V_REF/PGA)/(2²³– 1). The

positive full-scale input produces an output code of

7FFFFFh and the negative full-scale input produces

an output code of 800000h. The output clips at these

codes for signals exceeding full-scale. Table 21

summarizes the ideal output codes for different input

signals.

CS

The chip select pin (active low). The CS pin activates

SPI communication. CS must be low before data

transactions and must stay low for the entire SPI

communication period. When CS is high, the

DOUT/DRDY pin enters a high-impedance state.

Therefore, reading and writing to the serial interface

are ignored and the serial interface is reset. DRDY

pin operation is independent of CS.

Table 21. Ideal Output Code vs Input Signal

INPUT SIGNAL, V_IN

(AIN_P– AIN_N)

IDEAL OUTPUT CODE

7FFFFFh

Taking CS high deactivates only the SPI

communication with the device. Data conversion

continues and the DRDY signal can be monitored to

check if a new conversion result is ready. A master

device monitoring the DRDY signal can select the

appropriate slave device by pulling the CS pin low.

≥ +V_REF/PGA

(+V_REF/PGA)/(2²³– 1)

0

(–V_REF/PGA)/(2²³– 1)

≤ –(V_REF/PGA) × (2²³/2²³– 1)

000001h

000000h

FFFFFFh

800000h

SCLK

1. Excludes effects of noise, linearity, offset, and

gain errors.

The serial clock signal. SCLK provides the clock for

serial communication. It is a Schmitt-trigger input, but

it is highly recommended that SCLK be kept as clean

as possible to prevent glitches from inadvertently

shifting the data. Data are shifted into DIN on the

falling edge of SCLK and shifted out of DOUT on the

rising edge of SCLK.

Digital Interface

The ADS1246/7/8 provide a standard SPI serial

communication interface plus a data ready signal

(DRDY). Communication is full-duplex with the

exception of a few limitations in regards to the RREG

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DIN

When the DRDY MODE bit is set to '0', this pin

functions as DOUT only. Data are clocked out at

rising edge of SCLK, MSB first (see Figure 66).

The data input pin. DIN is used along with SCLK to

send data to the device. Data on DIN are shifted into

the device on the falling edge of SCLK.

When the DRDY MODE bit is set to '1', this pin

functions as both DOUT and DRDY. Data are shifted

out from this pin, MSB first, at the rising edge of

SCLK. This combined pin allows for the same control

but with fewer pins.

The communication of this device is full-duplex in

nature. The device monitors commands shifted in

even when data are being shifted out. Data that are

present in the output shift register are shifted out

when sending in

a command. Therefore, it is

When the DRDY MODE bit is enabled and a new

conversion is complete, DOUT/DRDY goes low if it is

high. If it is already low, then DOUT/DRDY goes high

and then goes low (see Figure 67). Similar to the

DRDY pin, a falling edge on the DOUT/DRDY pin

signals that a new conversion result is ready. After

DOUT/DRDY goes low, the data can be clocked out

by providing 24 SCLKs. In order to force

DOUT/DRDY high (so that DOUT/DRDY can be

polled for a '0' instead of waiting for a falling edge), a

no operation command (NOP) or any other command

that does not load the data output register can be

sent after reading out the data. Because SCLKs can

only be sent in multiples of eight, a NOP can be sent

to force DOUT/DRDY high if no other command is

pending. The DOUT/DRDY pin goes high after the

first rising edge of SCLK after reading the conversion

result completely (see Figure 68). The same condition

also applies after an RREG command. After all the

register bits have been read out, the rising edge of

SCLK forces DOUT/DRDY high. Figure 69 illustrates

an example where sending four NOP commands after

an RREG command forces the DOUT/DRDY pin

high.

important to make sure that whatever is being sent on

the DIN pin is valid when shifting out data. When no

command is to be sent to the device when reading

out data, the NOP command should be sent on DIN.

DRDY

The data ready pin. The DRDY pin goes low to

indicate a new conversion is complete, and the

conversion result is stored in the conversion result

buffer. The SPI clock must be low in a short time

frame around the DRDY low transition (see Figure 2)

so that the conversion result is loaded into both the

result buffer and the output shift register. Therefore,

no commands should be issued during this time

frame if the conversion result is to be read out later.

This constraint applies only when CS is asserted.

When CS is not asserted, SPI communication with

other devices on the SPI bus does not affect loading

of the conversion result. After the DRDY pin goes

low, it is forced high on the first falling edge of SCLK

(so that the DRDY pin can be polled for '0' instead of

waiting for a falling edge). If the DRDY pin is not

taken high after it falls low, a short high pulse is

created on it to indicate the next data are ready.

DOUT/DRDY

This pin has two modes: data out (DOUT) only, or

data out (DOUT) combined with data ready (DRDY).

The DRDY MODE bit determines the function of this

pin. In either mode, the DOUT/DRDY pin goes to a

high-impedance state when CS is taken high.

1

2

3

22

23

24

1

2

8

SCLK

DOUT/DRDY⁽¹⁾

D[23]

D[22]

D[21]

D[2]

D[1]

D[0]

DRDY

(1) CS tied low.

Figure 66. Data Retrieval with the DRDY MODE Bit = 0 (Disabled)

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1

2

3

22

23

24

1

2

24

SCLK

D[23] D[22] D[21]

NOP

D[2]

D[1]

D[0]

D[23] D[22]

NOP

D[0]

DOUT/DRDY⁽¹⁾

DIN

DRDY

(1) CS tied low.

Figure 67. Data Retrieval with the DRDY MODE Bit = 1 (Enabled)

1

2

3

22

23

24

1

2

8

1

2

24

SCLK

D[23] D[22] D[21]

NOP

D[2]

D[1] D[0]

D[23] D[22]

NOP

D[0]

DOUT/DRDY⁽¹⁾

DIN

NOP

DRDY

(1) DRDY MODE bit enabled, CS tied low.

Figure 68. DOUT/DRDY Forced High After Retrieving the Conversion Result

1

2

7

8

1

2

7

8

SCLK

DOUT/DRDY⁽¹⁾

DIN

reg[7]

reg[1] reg[0]

NOP

(1) DRDY MODE bit enabled, CS tied low.

Figure 69. DOUT/DRDY Forced High After Reading Register Data

The DRDY MODE bit modifies only the DOUT/DRDY

pin functionality. The DRDY pin functionality remains

unaffected.

SPI Communication During Sleep Mode

When the START pin is low or the device is in sleep

mode, only the RDATA, RDATAC, SDATAC,

WAKEUP, and NOP commands can be issued. The

RDATA command can be used to repeatedly read the

last conversion result during sleep mode. Other

commands do not function because the internal clock

is shut down to save power during sleep mode.

SPI Reset

SPI communication can be reset in several ways. In

order to reset the SPI interface (without resetting the

registers or the digital filter), the CS pin can be pulled

high. Taking the RESET pin low causes the SPI

interface to be reset along with all the other digital

functions. In this case, the registers and the

conversion are reset.

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REGISTER DESCRIPTIONS

Table 22. ADS1246 Register Map

ADS1246 REGISTER MAP

ADDRESS REGISTER

BIT 7

BCS1

0

BIT 6

BCS0

0

BIT 5

0

BIT 4

0

BIT 3

0

BIT 2

0

BIT 1

0

BIT 0

1

00h

01h

02h

03h

04h

05h

06h

07h

08h

09h

BCS

VBIAS

MUX1

SYS0

OFC0

OFC1

OFC2

FSC0

FSC1

FSC2

0

VBIAS1

MUXCAL1

DR1

VBIAS0

MUXCAL0

DR0

CLKSTAT

0

MUXCAL2

DR2

PGA2

OFC6

OFC14

OFC22

FSC6

FSC14

FSC22

PGA1

OFC5

OFC13

OFC21

FSC5

FSC13

FSC21

PGA0

OFC4

OFC12

OFC20

FSC4

FSC12

FSC20

DR3

OFC7

OFC15

OFC23

FSC7

FSC15

FSC23

OFC3

OFC11

OFC19

FSC3

FSC11

FSC19

OFC2

OFC10

OFC18

FSC2

FSC10

FSC18

OFC1

OFC9

OFC17

FSC1

OFC0

OFC8

OFC16

FSC0

FSC9

FSC8

FSC17

FSC16

DRDY

MODE

0Ah

ID

ID3

ID2

ID1

ID0

0

ADS1246 DETAILED REGISTER DEFINITIONS

BCS—Burnout Current Source Register. These bits control the settling of the sensor burnout detect current

source.

BCS - ADDRESS 00h

RESET VALUE = 01h

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

BCS1

BCS0

0

1

Bits 7:6

Bits 5:0

BCS1:0

These bits select the magnitude of the sensor burnout detect current source.

00 = Burnout current source off (default)

01 = Burnout current source on, 0.5mA

10 = Burnout current source on, 2mA

11 = Burnout current source on, 10mA

These bits must always be set to '000001'.

38

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ADS1246 DETAILED REGISTER DEFINITIONS (continued)

VBIAS—Bias Voltage Register. This register enables a bias voltage on the analog inputs.

VBIAS - ADDRESS 01h

RESET VALUE = 00h

BIT 0

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

VBIAS1

0

VBIAS0

Bits 7:2

Bits 1:0

These bits must always be set to '000000'.

VBIAS1:0

These bits apply a bias voltage of midsupply (AVDD + AVSS)/2 to the selected analog input. Bit 0

is for AIN0, and bit 1 is for AIN1.

0 = Bias voltage not enabled (default)

1 = Bias voltage is applied to the analog input

MUX—Multiplexer Control Register.

MUX - ADDRESS 02h

RESET VALUE = x0h

BIT 0

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

MUXCAL1

CLKSTAT

0

MUXCAL2

MUXCAL0

Bit 7

CLKSTAT

This bit is read-only and indicates whether the internal or external oscillator is being used.

0 = Internal oscillator in use

1 = External oscillator in use

Bits 6:3

Bits 2:0

These bits must always be set to '0000'.

MUXCAL2:0

These bits are used to select a system monitor. The MUXCAL selection supercedes selections

from the VBIAS register.

000 = Normal operation (default)

001 = Offset calibration. The analog inputs are disconnected and AINP and AINN are internally

connected to midsupply (AVDD + AVSS)/2.

010 = Gain calibration. The analog inputs are connected to the voltage reference.

011 = Temperature measurement. The inputs are connected to a diode circuit that produces a

voltage proportional to the ambient temperature of the device..

Table 23 lists the ADC input connection and PGA settings for each MUXCAL setting. The PGA setting reverts to

the original SYS0 register setting when MUXCAL is taken back to normal operation or offset measurement.

Table 23. MUXCAL Settings

MUXCAL[2:0]

PGA GAIN SETTING

Set by SYS0 register

Forced to 1

ADC INPUT

Normal operation

000

001

010

011

Offset calibration: inputs shorted to midsupply (AVDD + AVSS)/2

Gain calibration: V_REFP– V_REFN(full-scale)

Temperature measurement diode

Forced to 1

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ADS1246 DETAILED REGISTER DEFINITIONS (continued)

SYS0—System Control Register 0.

SYS0 - ADDRESS 03h

RESET VALUE = 00h

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

0

PGA2

PGA1

PGA0

DOR3

DOR2

DOR1

DOR0

Bit 7

Bits 6:4

These bits must always be set to '0'.

PGA2:0

These bits determine the gain of the PGA.

000 = 1 (default)

001 = 2

010 = 4

011 = 8

100 = 16

101 = 32

110 = 64

111 = 128

Bits 3:0

DOR3:0

These bits select the output data rate of the ADC. Bits with a value higher than 1001 select the

highest data rate of 2kSPS.

0000 = 5SPS (default)

0001 = 10SPS

0010 = 20SPS

0011 = 40SPS

0100 = 80SPS

0101 = 160SPS

0110 = 320SPS

0111 = 640SPS

1000 = 1000SPS

1001 to 1111 = 2000SPS

OFC23:0

These bits make up the offset calibration coefficient register of the ADS1248.

OFC0—Offset Calibration Coefficient Register 0

OFC0 - ADDRESS 04h

RESET VALUE = 00h

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

OFC7

OFC6

OFC5

OFC4

OFC3

OFC2

OFC1

OFC0

OFC1—Offset Calibration Coefficient Register 1

OFC1 - ADDRESS 05h

RESET VALUE = 00h

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

OFC15

OFC14

OFC13

OFC12

OFC11

OFC10

OFC9

OFC8

OFC2—Offset Calibration Coefficient Register 2

OFC2 - ADDRESS 06h

RESET VALUE = 00h

BIT 0

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

OFC23

OFC22

OFC21

OFC20

OFC19

OFC18

OFC17

OFC16

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ADS1246 DETAILED REGISTER DEFINITIONS (continued)

FSC23:0

These bits make up the full-scale calibration coefficient register.

FSC0—Full-Scale Calibration Coefficient Register 0

FSC0 - ADDRESS 07h

RESET VALUE IS PGA DEPENDENT⁽¹⁾

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

FSC7

FSC6

FSC5

FSC4

FSC3

FSC2

FSC1

FSC0

(1) The reset value for FSC is factory-trimmed for each PGA setting. Note: the factory-trimmed FSC reset value is automatically loaded

whenever the PGA setting is changed.

FSC1—Full-Scale Calibration Coefficient Register 1

FSC1 - ADDRESS 08h

RESET VALUE IS PGA DEPENDENT⁽¹⁾

BIT 7

BIT 6

FSC14

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

FSC15

FSC13

FSC12

FSC11

FSC10

FSC9

FSC8

(1) The reset value for FSC is factory-trimmed for each PGA setting. Note: the factory-trimmed FSC reset value is automatically loaded

whenever the PGA setting is changed.

FSC2—Full-Scale Calibration Coefficient Register 2

FSC2 - ADDRESS 09h

RESET VALUE IS PGA DEPENDENT⁽¹⁾

BIT 7

BIT 6

FSC22

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

FSC23

FSC21

FSC20

FSC19

FSC18

FSC17

FSC16

(1) The reset value for FSC is factory-trimmed for each PGA setting. Note: the factory-trimmed FSC reset value is automatically loaded

whenever the PGA setting is changed.

ID—ID Register

IDAC0 - ADDRESS 0Ah

RESET VALUE = x0h

BIT 7

BIT 6

ID2

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

ID3

ID1

ID0

DRDY MODE

0

Bits 7:4

ID3:0

Read-only, factory-programmed bits; used for revision identification.

Bit 3

DRDY MODE

This bit sets the DOUT/DRDY pin functionality. In either setting of the DRDY MODE bit, the DRDY

pin continues to indicate data ready, active low.

0 = DOUT/DRDY pin functions only as Data Out (default)

1 = DOUT/DRDY pin functions both as Data Out and Data Ready, active low

Bits 2:0

These bits must always be set to '000'.

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ADS1247 AND ADS1248 REGISTER MAP

Table 24. ADS1247 and ADS1248 Register Map

ADDRESS REGISTER

BIT 7

BCS1

BIT 6

BCS0

BIT 5

MUX_SP2

VBIAS5

BIT 4

MUX_SP1

VBIAS4

BIT 3

MUX_SP0

VBIAS3

BIT 2

MUX_SN2

VBIAS2

BIT 1

MUX_SN1

VBIAS1

MUXCAL1

DR1

BIT 0

MUX_SN0

VBIAS0

MUXCAL0

DR0

00h

01h

02h

03h

04h

05h

06h

07h

08h

09h

MUX0

VBIAS

MUX1

SYS0

OFC0

OFC1

OFC2

FSC0

FSC1

FSC2

VBIAS7

VBIAS6

CLKSTAT VREFCON1 VREFCON0 REFSELT1 REFSELT0 MUXCAL2

0

PGA2

OFC6

PGA1

OFC5

PGA0

OFC4

DR3

DR2

OFC7

OFC15

OFC23

FSC7

OFC3

OFC11

OFC19

FSC3

OFC2

OFC10

OFC18

FSC2

OFC1

OFC0

OFC14

OFC22

FSC6

OFC13

OFC21

FSC5

OFC12

OFC20

FSC4

OFC9

OFC8

OFC17

FSC1

OFC16

FSC0

FSC15

FSC23

FSC14

FSC22

FSC13

FSC21

FSC12

FSC20

FSC11

FSC19

FSC10

FSC18

FSC9

FSC8

FSC17

FSC16

DRDY

MODE

0Ah

IDAC0

ID3

ID2

ID1

ID0

IMAG2

IMAG1

IMAG0

0Bh

0Ch

0Dh

0Eh

IDAC1

I1DIR3

IOCFG7

IODIR7

IODAT7

I1DIR2

IOCFG6

IODIR6

IODAT6

I1DIR1

IOCFG5

IODIR5

IODAT5

I1DIR0

IOCFG4

IODIR4

IODAT4

I2DIR3

IOCFG3

IODIR3

IODAT3

I2DIR2

IOCFG2

IODIR2

IODAT2

I2DIR1

IOCFG1

IODIR1

IODAT1

I2DIR0

IOCFG0

IODIR0

IODAT0

GPIOCFG

GPIODIR

GPIODAT

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SBAS426D –AUGUST 2008–REVISED MARCH 2010

ADS1247 and ADS1248 DETAILED REGISTER DEFINITIONS

MUX0—Multiplexer Control Register 0. This register allows any combination of differential inputs to be selected

on any of the input channels. Note that this setting can be superceded by the MUXCAL and VBIAS bits.

MUX0 - ADDRESS 00h

RESET VALUE = 01h

BIT 0

BIT 7

BIT 6

BCS0

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

MUX_SN1

BCS1

MUX_SP2

MUX_SP1

MUX_SP0

MUX_SN2

MUX_SN0

Bits 7:6

Bits 5:3

BCS1:0

These bits select the magnitude of the sensor detect current source.

00 = Burnout current source off (default)

01 = Burnout current source on, 0.5mA

10 = Burnout current source on, 2mA

11 = Burnout current source on, 10mA

MUX_SP2:0

Positive input channel selection bits.

000 = AIN0 (default)

001 = AIN1

010 = AIN2

011 = AIN3

100 = AIN4 (ADS1248 only)

101 = AIN5 (ADS1248 only)

110 = AIN6 (ADS1248 only)

111 = AIN7 (ADS1248 only)

Bits 2:0

MUX_SN2:0

Negative input channel selection bits.

000 = AIN0

001 = AIN1 (default)

010 = AIN2

011 = AIN3

100 = AIN4 (ADS1248 only)

101 = AIN5 (ADS1248 only)

110 = AIN6 (ADS1248 only)

111 = AIN7 (ADS1248 only)

VBIAS—Bias Voltage Register

VBIAS - ADDRESS 01h

RESET VALUE = 00h

DEVICE

ADS1248

ADS1247

BIT 7

VBIAS7

0

BIT 6

VBIAS6

0

BIT 5

VBIAS5

0

BIT 4

VBIAS4

0

BIT 3

BIT 2

BIT 1

BIT 0

VBIAS3

VBIAS2

VBIAS1

VBIAS0

Bits 7:0

VBIAS7:0

These bits apply a bias voltage of midsupply (AVDD + AVSS)/2 to the selected analog input.

0 = Bias voltage not enabled (default)

1 = Bias voltage is applied on the corresponding analog input (bit 0 corresponds to AIN0, etc.).

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ADS1247 and ADS1248 DETAILED REGISTER DEFINITIONS (continued)

MUX1—Multiplexer Control Register 1

MUX1 - ADDRESS 02h

RESET VALUE = 00h

BIT 0

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

MUXCAL1

CLKSTAT

VREFCON1

VREFCON0

REFSELT1

REFSELT0

MUXCAL2

MUXCAL0

Bit 7

CLKSTAT

This bit is read-only and indicates whether the internal or external oscillator is being used.

0 = Internal oscillator in use

1 = External oscillator in use

Bits 6:5

VREFCON1:0

These bits control the internal voltage reference. These bits allow the reference to be turned on or

off completely, or allow the reference state to follow the state of the device. Note that the internal

reference is required for operation of the IDAC functions.

00 = Internal reference is always off (default)

01 = Internal reference is always on

10 or 11 = Internal reference is on when a conversion is in progress and shuts down when the

device receives a shutdown opcode or the START pin is taken low

Bits 4:3

Bits 2:0

REFSELT1:0

These bits select the reference input for the ADC.

00 = REF0 input pair selected (default)

01 = REF1 input pair selected (ADS1248 only)

10 = Onboard reference selected

11 = Onboard reference selected and internally connected to REF0 input pair

MUXCAL2:0

These bits are used to select a system monitor. The MUXCAL selection supercedes selections

from registers MUX0 and MUX1 (MUX_SP, MUX_SN, and VBIAS).

000 = Normal operation (default)

001 = Offset measurement

010 = Gain measurement

011 = Temperature diode

100 = External REF1 measurement (ADS1248 only)

101 = External REF0 measurement

110 = AVDD measurement

111 = DVDD measurement

Table 25 provides the ADC input connection and PGA settings for each MUXCAL setting. The PGA setting

reverts to the original SYS0 register setting when MUXCAL is taken back to normal operation or offset

measurement.

Table 25. MUXCAL Settings

MUXCAL[2:0]

PGA GAIN SETTING

Set by SYS0 register

Forced to 1

ADC INPUT

Normal operation

000

001

010

011

100

101

110

111

Inputs shorted to midsupply (AVDD + AVSS)/2

V_REFP– V_REFN(full-scale)

Temperature measurement diode

(V_REFP1– V_REFN1)/4

Forced to 1

(V_REFP0– V_REFN0)/4

Forced to 1

(AVDD – AVSS)/4

Forced to 1

(DVDD – DVSS)/4

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ADS1247 and ADS1248 DETAILED REGISTER DEFINITIONS (continued)

SYS0—System Control Register 0

SYS0 - ADDRESS 03h

RESET VALUE = 00h

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

0

PGA2

PGA1

PGA0

DOR3

DOR2

DOR1

DOR0

Bit 7

Bits 6:4

This bit must always be set to '0'

PGA2:0

These bits determine the gain of the PGA.

000 = 1 (default)

001 = 2

010 = 4

011 = 8

100 = 16

101 = 32

110 = 64

111 = 128

Bits 3:0

DOR3:0

These bits select the output data rate of the ADC. Bits with a value higher than 1001 select the

highest data rate of 2000SPS.

0000 = 5SPS (default)

0001 = 10SPS

0010 = 20SPS

0011 = 40SPS

0100 = 80SPS

0101 = 160SPS

0110 = 320SPS

0111 = 640SPS

1000 = 1000SPS

1001 to 1111 = 2000SPS

OFC23:0

These bits make up the offset calibration coefficient register of the ADS1248.

OFC0—Offset Calibration Coefficient Register 0

OFC0 - ADDRESS 04h

RESET VALUE = 000000h

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

OFC7

OFC6

OFC5

OFC4

OFC3

OFC2

OFC1

OFC0

OFC1—Offset Calibration Coefficient Register 1

OFC1 - ADDRESS 05h

RESET VALUE = 000000h

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

OFC15

OFC14

OFC13

OFC12

OFC11

OFC10

OFC9

OFC8

OFC2—Offset Calibration Coefficient Register 2

OFC2 - ADDRESS 06h

RESET VALUE = 000000h

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

OFC23

OFC22

OFC21

OFC20

OFC19

OFC18

OFC17

OFC16

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ADS1247 and ADS1248 DETAILED REGISTER DEFINITIONS (continued)

FSC23:0

These bits make up the full-scale calibration coefficient register.

FSC0—Full-Scale Calibration Coefficient Register 0

FSC0 - ADDRESS 07h

RESET VALUE IS PGA DEPENDENT⁽¹⁾

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

FSC7

FSC6

FSC5

FSC4

FSC3

FSC2

FSC1

FSC0

(1) The reset value for FSC is factory-trimmed for each PGA setting. Note: the factory-trimmed FSC reset value is automatically loaded

whenever the PGA setting is changed.

FSC1—Full-Scale Calibration Coefficient Register 1

FSC1 - ADDRESS 08h

RESET VALUE IS PGA DEPENDENT⁽¹⁾

BIT 7

BIT 6

FSC14

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

FSC15

FSC13

FSC12

FSC11

FSC10

FSC9

FSC8

(1) The reset value for FSC is factory-trimmed for each PGA setting. Note: the factory-trimmed FSC reset value is automatically loaded

whenever the PGA setting is changed.

FSC2—Full-Scale Calibration Coefficient Register 2

FSC2 - ADDRESS 09h

RESET VALUE IS PGA DEPENDENT⁽¹⁾

BIT 7

BIT 6

FSC22

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

FSC23

FSC21

FSC20

FSC19

FSC18

FSC17

FSC16

(1) The reset value for FSC is factory-trimmed for each PGA setting. Note: the factory-trimmed FSC reset value is automatically loaded

whenever the PGA setting is changed.

IDAC0—IDAC Control Register 0

IDAC0 - ADDRESS 0Ah

RESET VALUE = x0h

BIT 7

BIT 6

ID2

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

ID3

ID1

ID0

DRDY MODE

IMAG2

IMAG1

IMAG0

Bits 7:4

ID3:0

Read-only, factory-programmed bits; used for revision identification.

Bit 3

DRDY MODE

This bit sets the DOUT/DRDY pin functionality. In either setting of the DRDY MODE bit, the DRDY

pin continues to indicate data ready, active low.

0 = DOUT/DRDY pin functions only as Data Out (default)

1 = DOUT/DRDY pin functions both as Data Out and Data Ready, active low

Bits 2:0

IMAG2:0

The ADS1247/8 have two programmable current source DACs that can be used for sensor

excitation. The IMAG bits control the magnitude of the excitation current. The IDACs require the

internal reference to be on.

000 = off (default)

001 = 50mA

010 = 100mA

011 = 250mA

100 = 500mA

101 = 750mA

110 = 1000mA

111 = 1500mA

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ADS1247 and ADS1248 DETAILED REGISTER DEFINITIONS (continued)

IDAC1—IDAC Control Register 1

IDAC1 - ADDRESS 0Bh

RESET VALUE = FFh

DEVICE

ADS1248

ADS1247

BIT 7

I1DIR3

0

BIT 6

I1DIR2

0

BIT 5

I1DIR1

BIT 4

I1DIR0

BIT 3

I2DIR3

0

BIT 2

I2DIR2

0

BIT 1

I2DIR1

BIT 0

I2DIR0

The two IDACs on the ADS1247/8 can be routed to either the IEXC1 and IEXC2 output pins or directly to the

analog inputs.

Bits 7:4

I1DIR3:0

These bits select the output pin for the first current source DAC.

0000 = AIN0

0001 = AIN1

0010 = AIN2

0011 = AIN3

0100 = AIN4 (ADS1248 only)

0101 = AIN5 (ADS1248 only)

0110 = AIN6 (ADS1248 only)

0111 = AIN7 (ADS1248 only)

10x0 = IEXT1 (ADS1248 only)

10x1 = IEXT2 (ADS1248 only)

11xx = Disconnected (default)

Bits 3:0

I2DIR3:0

These bits select the output pin for the second current source DAC.

0000 = AIN0

0001 = AIN1

0010 = AIN2

0011 = AIN3

0100 = AIN4 (ADS1248 only)

0101 = AIN5 (ADS1248 only)

0110 = AIN6 (ADS1248 only)

0111 = AIN7 (ADS1248 only)

10x0 = IEXT1 (ADS1248 only)

10x1 = IEXT2 (ADS1248 only)

11xx = Disconnected (default)

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ADS1247 and ADS1248 DETAILED REGISTER DEFINITIONS (continued)

GPIOCFG—GPIO Configuration Register. The GPIO and analog pins are shared as follows:

GPIO0 shared with REFP0

GPIO1 shared with REFN0

GPIO2 shared with AIN2

GPIO3 shared with AIN3

GPIO4 shared with AIN4 (ADS1248)

GPIO5 shared with AIN5 (ADS1248)

GPIO6 shared with AIN6 (ADS1248)

GPIO7 shared with AIN7 (ADS1248)

GPIOCFG - ADDRESS 0Ch

RESET VALUE = 00h

DEVICE

ADS1248

ADS1247

BIT 7

IOCFG7

0

BIT 6

IOCFG6

0

BIT 5

IOCFG5

0

BIT 4

IOCFG4

0

BIT 3

BIT 2

BIT 1

BIT 0

IOCFG3

IOCFG2

IOCFG1

IOCFG0

Bits 7:0

IOCFG7:0

These bits enable the GPIO because the GPIO pins are shared with the analog pins. Note that the

ADS1248 uses all the IOCFG bits, whereas the ADS1247 uses only bits 3:0.

0 = The pin is used as an analog input (default)

1 = The pin is used as a GPIO pin

GPIODIR—GPIO Direction Register

GPIODIR - ADDRESS 0Dh

RESET VALUE = 00h

DEVICE

ADS1248

ADS1247

BIT 7

IODIR7

0

BIT 6

IODIR6

0

BIT 5

IODIR5

0

BIT 4

IODIR4

0

BIT 3

IODIR3

BIT 2

IODIR2

BIT 1

BIT 0

IODIR1

IODIR0

Bits 7:0

IODIR7:0

These bits control the direction of the GPIO when enabled by the IOCFG bits. Note that the

ADS1248 uses all the IODIR bits, whereas the ADS1247 uses only bits 3:0.

0 = The GPIO is an output (default)

1 = The GPIO is an input

GPIODAT—GPIO Data Register

GPIODAT - ADDRESS 0Eh

RESET VALUE = 00h

DEVICE

ADS1248

ADS1247

BIT 7

IODAT7

0

BIT 6

IODAT6

0

BIT 5

IODAT5

0

BIT 4

IODAT4

0

BIT 3

BIT 2

BIT 1

BIT 0

IODAT3

IODAT2

IODAT1

IODAT0

Bits 7:0

IODAT7:0

If a GPIO pin is enabled in the GPIOCFG register and configured as an output in the GPIO

Direction register (GPIODIR), the value written to this register appears on the appropriate GPIO

pin. If a GPIO pin is configured as an input in GPIODIR, reading this register returns the value of

the digital I/O pins. Note that the ADS1248 uses all eight IODAT bits, while the ADS1247 uses only

bits 3:0.

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SPI COMMANDS

SPI COMMAND DEFINITIONS

The commands shown in Table 26 control the operation of the ADS1246/7/8. Some of the commands are

stand-alone commands (for example, RESET), whereas others require additional bytes (for example, WREG

requires command, count, and the data bytes).

Operands:

n = number of registers to be read or written (number of bytes – 1)

r = register (0 to 15)

x = don't care

Table 26. SPI Commands

COMMAND TYPE

COMMAND

WAKEUP

SLEEP

DESCRIPTION

Exit sleep mode

1st COMMAND BYTE

0000 000x (00h, 01h)

0000 001x (02h, 03h)

0000 010x (04h, 05h)

0000 011x (06h, 07h)

1111 1111 (FFh)

2nd COMMAND BYTE

Enter sleep mode

System Control

SYNC

Synchronize the A/D conversion

Reset to power-up values

No operation

0000-010x (04,05h)

RESET

NOP

RDATA

Read data once

0001 001x (12h, 13h)

0001 010x (14h, 15h)

0001 011x (16h, 17h)

0010 rrrr (2xh)

Data Read

RDATAC

SDATAC

RREG

Read data continuously

Stop reading data continuously

Read from register rrrr

Write to register rrrr

Read Register

Write Register

0000_nnnn

WREG

0100 rrrr (4xh)

SYSOCAL

SYSGCAL

SELFOCAL

System offset calibration

System gain calibration

Self offset calibration

0110 0000 (60h)

Calibration

0110 0001 (61h)

0110 0010 (62h)

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SYSTEM CONTROL COMMANDS

WAKEUP—Wake up from sleep mode that is set by the SLEEP command.

Use this command to awaken the device from sleep mode. After execution of the WAKEUP command, the

device wakes up on the rising edge of the eighth SCLK.

SLEEP—Set the device to sleep mode; can only be awakened by the WAKEUP command.

This command places the part into a sleep (power-saving) mode. When the SLEEP command is issued, the

device completes the current conversion and then goes into sleep mode. Note that this command does not

automatically power-down the internal voltage reference; see the VREFCON bits in the MUX1 register for

each device for further details.

To exit sleep mode, issue the WAKEUP command. Single conversions can be performed by issuing a

WAKEUP command followed by a SLEEP command.

Both WAKEUP and SLEEP are the software command equivalents of using the START pin to control the device.

SLEEP

WAKEUP

DIN

SCLK

DRDY

0000 001X

0000 000X

Eighth SCLK

Status

Normal Mode

Sleep Mode

Normal Mode

Finish Current Conversion

Start New Conversion

Figure 70. SLEEP and WAKEUP Commands Operation

SYNC—Synchronize DRDY.

This command resets the ADC digital filter and starts a new conversion. The DRDY pin from multiple devices

connected to the same SPI bus can be synchronized by issuing a SYNC command to all of devices

simultaneously.

SYNC

DIN

0000 010X 0000 010X

SCLK

Synchronization

Occurs Here

2 t_OSC

Figure 71. SYNC Command Operation

RESET—Reset the device to power-up state.

This command restores the registers to the respective power-up values. This command also resets the digital

filter. RESET is the command equivalent of using the RESET pin to reset the device. However, the RESET

command does not reset the SPI interface. If the RESET command is issued when the SPI interface is in the

wrong state, the device does not reset. The CS pin can be used to reset SPI interface first, and then a

RESET command can be issued to reset the device. The RESET command holds the registers and the

decimation filter in a reset state for 0.6ms when the system clock frequency is 4.096MHz, similar to the

hardware reset. Therefore, SPI communication can be only be started 0.6ms after the RESET command is

issued, as shown in Figure 72.

Any SPI

Command

DIN

RESET

1

8

SCLK

0.6ms

Figure 72. SPI Communication After an SPI Reset

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DATA RETRIEVAL COMMANDS

RDATAC—Read data continuously.

The RDATAC command enables the automatic loading of a new conversion result into the output data

register. In this mode, the conversion result can be received once from the device after the DRDY signal

goes low by sending 24 SCLKs. It is not necessary to read back all the bits, as long as the number of bits

read out is a multiple of eight. The RDATAC command must be issued after DRDY goes low, and the

command takes effect on the next DRDY.

Be sure to complete data retrieval (conversion result or register read-back) before DRDY goes low, or the

resulting data will be corrupt. Successful register read operations in RDATAC mode require the knowledge of

when the next DRDY falling edge occurs.

DRDY

RDATAC

NOP

DIN

0001 010X

DOUT

SCLK

24 Bits

1

8

1

24

Figure 73. Read Data Continuously

SDATAC—Stop reading data continuously.

The SDATAC command terminates the RDATAC mode. Afterwards, the conversion result is not

automatically loaded into the output shift register when DRDY goes low, and register read operations can be

performed without interruption from new conversion results being loaded into the output shift register. Use

the RDATA command to retrieve conversion data. The SDATAC command takes effect after the next DRDY.

DRDY

SDATAC

DIN

0001 011X

Figure 74. Stop Reading Data Continuously

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RDATA—Read data once.

The RDATA command loads the most recent conversion result into the output register. After issuing this

command, the conversion result can be read out by sending 24 SCLKs, as shown in Figure 75. This

command also works in RDATAC mode.

When performing multiple reads of the conversion result, the RDATA command can be sent when the last

eight bits of the conversion result are being shifted out during the course of the first read operation by taking

advantage of the duplex communication nature of the SPI interface, as shown in Figure 76.

DRDY

RDATA

NOP

MSB

NOP

LSB

DIN

DOUT

SCLK

0001 001X

Mid-Byte

1

8

1

24

Figure 75. Read Data Once

1

2

7

8

9

10

23

24

1

2

23

24

SCLK

D[23] D[22]

NOP

D[17] D[16] D[15] D[14]

D[1] D[0] D[23] D[22]

D[1] D[0]

NOP

DOUT

DIN

NOP

RDATA

NOP

DRDY

Figure 76. Using RDATA in Full-Duplex Mode

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USER REGISTER READ AND WRITE COMMANDS

RREG—Read from registers.

This command outputs the data from up to 16 registers, starting with the register address specified as part of

the instruction. The number of registers read is one plus the second byte. If the count exceeds the remaining

registers, the addresses wrap back to the beginning.

First Command Byte: 0010 rrrr, where rrrr is the address of the first register to read.

Second Command Byte: 0000 nnnn, where nnnn is the number of bytes to read –1.

It is not possible to use the full-duplex nature of the SPI interface when reading out the register data. For

example, a SYNC command cannot be issued when reading out the VBIAS and MUX1 data, as shown in

Figure 77. Any command sent during the readout of the register data is ignored. Thus, it is advisable to send

NOP through the DIN when reading out the register data.

1st

Command Command

Byte Byte

2nd

DIN

0010 0001 0000 0001

VBIAS

MUX1

DOUT

Data Byte Data Byte

Figure 77. Read from Register

WREG—Write to registers.

This command writes to the registers, starting with the register specified as part of the instruction. The

number of registers that are written is one plus the value of the second byte.

First Command Byte: 0100 rrrr, where rrrr is the address of the first register to be written.

Second Command Byte: 0000 nnnn, where nnnn is the number of bytes to be written – 1.

Data Byte(s): data to be written to the registers.

DIN

0100 0010 0000 0001

MUX2

SYS0

1st

2nd

Data

Byte

Data

Byte

Command Command

Figure 78. Write to Register

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CALIBRATION COMMANDS

The ADS1246/7/8 provide system and offset calibration commands and a system gain calibration command.

SYSOCAL—Offset system calibration.

This command initiates a system offset calibration. For a system offset calibration, the input should be

externally set to zero. The OFC register is updated when this operation completes.

SYSGCAL—System gain calibration.

This command initiates the system gain calibration. For a system gain calibration, the input should be set to

full-scale. The FSC register is updated after this operation.

SELFOCAL—Self offset calibration.

This command initiates a self-calibration for offset. The device internally shorts the inputs and performs the

calibration. The OFC register is updated after this operation.

Calibration

Starts

Calibration

Complete

t_CAL

DRDY

DIN

Calibration

Command

SCLK

1

8

Figure 79. Calibration Command

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APPLICATION INFORMATION

SPI COMMUNICATION EXAMPLES

negative terminal of both sensors (that is, channels

AIN1 and AIN3). All these settings can be changed

by performing a block write operation on the first four

registers of the device. After the DRDY pin goes low,

the conversion result can be immediately retrieved by

sending in 16 SPI clock pulses because the device

defaults to RDATAC mode. As the conversion result

is being retrieved, the active input channels can be

switched to AIN2 and AIN3 by writing into the MUX0

This section contains several examples of SPI

communication with the ADS1246/7/8, including the

power-up sequence.

Channel Multiplexing Example

This first example applies only to the ADS1247 and

ADS1248. It explains a method to use the device with

two sensors connected to two different analog

channels. Figure 80 shows the sequence of SPI

operations performed on the device. After power-up,

2¹⁶system clocks are required before communication

may be started. During the first 2¹⁶system clock

cycles, the devices are internally held in a reset state.

In this example, one of the sensors is connected to

channels AIN0 and AIN1 and the other sensor is

connected to channels AIN2 and AIN3. The ADC is

operated at a data rate of 2kSPS. The PGA gain is

set to 32 for both sensors. VBIAS is connected to the

register in

a full-duplex manner, as shown in

Figure 80. The write operation is completed with an

additional eight SPI clock pulses. The time from the

write operation into the MUX0 register to the next

DRDY low transition is shown in Figure 80 and is

0.513ms in this case. After DRDY goes low, the

conversion result can be retrieved and the active

channel can be switched as before.

Power-up sequence

16ms⁽¹⁾

ADC initial setup

Multiplexer change is channel 2

Data Retrieval for

Channel 2 Conversion

DVDD

START

RESET

CS

WREG

NOP

DIN

3

00 01 02 03

00 00

SCLK

Conversion result

for channel 1

Conversion result

for channel 2

DOUT

DRDY

0.513ms

t_DRDY

for

Initial setting:

MUX0

Write

AIN0 is the positive channel,

AIN1 is the negative channel,

internal reference selected,

PGA gain = 32,

AIN2 is the positive channel,

AIN3 is the negative channel.

data rate = 2kSPS,

VBIAS is connected to the

negative pins AIN1 and AIN3.

(1) For f_OSC= 4.096MHz.

Figure 80. SPI Communication Sequence for Channel Multiplexing

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Sleep Mode Example

be changed by performing a block write operation on

the first four registers of the device. After performing

the block write operation, the START pin can be

taken low. The device enters the power-saving sleep

mode as soon as DRDY goes low 0.575ms after

writing into the SYS0 register. The conversion result

can be retrieved even after the device enters sleep

mode by sending 16 SPI clock pulses.

This second example deals with performing one

conversion after power-up and then entering into the

power-saving sleep mode. In this example, a sensor

is connected to input channels AIN0 and AIN1.

Commands to set up the devices must occur at least

2¹⁶system clock cycles after powering up the

devices. The ADC operates at a data rate of 2kSPS.

The PGA gain is set to 32 for both sensors. VBIAS is

connected to the negative terminal of both the

sensors (that is, channel AIN1). All these settings can

ADC is put to sleep

after a single conversion.

Data are retrieved when

ADC is sleeping.

Power-up sequence

16ms⁽¹⁾

ADC initial setup

DVDD

START

RESET

CS

WREG

NOP

DIN

00 01 02 03

SCLK

Conversion result

for channel 1

DOUT

DRDY

t_DRDY

Initial setting:

ADC enters

power-saving

sleep mode

(0.575ms)

AIN0 is the positive channel,

AIN1 is the negative channel,

internal reference selected,

PGA gain = 32,

data rate = 2kSPS,

VBIAS is connected to the

negative pins, AIN1 and AIN3.

(1) For f_OSC= 4.096MHz.

Figure 81. SPI Communication Sequence for Entering Sleep Mode After a Conversion

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Hardware-Compensated, Three-Wire RTD

Measurement Example

be equal to the resistance of the PT-100 sensor at

+25°C (approximately 110Ω). The IDAC current is set

to 1.5mA. This setting results in a differential input

swing of ±14.7mV at the inputs of the ADC. The PGA

gain is set to 128. The full-scale input for the ADC is

±19.53mV. Fixing R_BIASat 833Ω fixes the reference at

2.5V and the input common-mode at approximately

2.7V, ensuring that the voltage at AIN0 is far away

from the IDAC compliance voltage.

Figure 82 is an application circuit to measure

temperatures in the range of 0°C to +50°C using a

PT-100 RTD and the ADS1247 or ADS1248 in a

three-wire, hardware-compensated topology. The two

onboard matched current DACs of the ADS1247/8

are ideally suited for implementing the three-wire

RTD topology. This circuit uses

a ratiometric

approach, where the reference is derived from the

IDAC currents in order to achieve excellent noise

performance. The resistance of the PT-100 changes

from 100Ω at 0°C to 119.6Ω at +50°C. The

compensating resistor (R_COMP) has been chosen to

The maximum number of noise-free output codes for

this circuit in the 0°C to +50°C temperature range is

(2^ENOB)(14.7mV)/19.53mV.

+5V

+3.3V

IN

EN

V_OUT

TPS79333

GND

0.1mF

2.2mF

NR

AVDD

DVDD

VDD

RESET

IDAC1

1.5mA

IDAC2

1.5mA

RTD

(1)

R_L

15W

AIN0

AIN1

(1)

(2)

MSP430

or

R_L

R_COMP

110W

PGA

Modulator

15W

other

Microprocessor

Gain = 128

(1)

R_L

15W

SCLK

DIN

REFP0

REFN0

(2)

R_BIAS

833W

ADS1247/48

DOUT/DRDY

CS

START

CLK

GND

AVSS

DGND

(1) RTD line resistances.

(2) R_BIASand R_COMPshould be as close to the ADC as possible.

Figure 82. Three-Wire RTD Application with Hardware Compensation

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REVISION HISTORY

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision C (August 2009) to Revision D

Page

•

Updated Description section ................................................................................................................................................. 1

Added Analog Inputs, Full-scale input voltage maximum specification in Electrical Characteristics .................................... 4

Changed Analog Inputs, Absolute input current parameter of Electrical Characteristics ..................................................... 4

Added new footnote 1 to Electrical Characteristics .............................................................................................................. 4

Changed conditions of System Performance, Power-supply rejection parameter of Electricsl Characteristics ................... 4

Changed typical specification of Current Sources (IDACS), Initial mismatch parameter of Electrical Characteristics ........ 5

Changed typical specification of Current Sources (IDACS), Temperature drift parameter of Electrical Characteristics ...... 5

Changed Power Supply, AVDD current typical specification for 3.3V parameter in Electrical Characteristics .................... 5

Changed title of Table 6 ...................................................................................................................................................... 13

Changed title of Table 7 ...................................................................................................................................................... 14

Changed title of Table 9 ...................................................................................................................................................... 15

Updated Figure 5 ................................................................................................................................................................ 16

Updated Figure 6 ................................................................................................................................................................ 16

Added Figure 7, Noise Histogram Plot ............................................................................................................................... 16

Added Figure 8, Noise Histogram Plot ............................................................................................................................... 16

Updated Figure 9 ................................................................................................................................................................ 16

Added Figure 10, RMS Noise vs Input Signal .................................................................................................................... 16

Updated Figure 11 .............................................................................................................................................................. 17

Updated Figure 12 .............................................................................................................................................................. 17

Updated Figure 13 .............................................................................................................................................................. 17

Updated Figure 14 .............................................................................................................................................................. 17

Added Figure 15, Offset Drift vs Temperature .................................................................................................................... 17

Added Figure 16, Offset Drift vs Temperature .................................................................................................................... 17

Added Figure 17, Offset vs Temperature ........................................................................................................................... 18

Added Figure 18, Offset vs Temperature ........................................................................................................................... 18

Updated Figure 19 .............................................................................................................................................................. 18

Updated Figure 20 .............................................................................................................................................................. 18

Updated Figure 21 .............................................................................................................................................................. 18

Updated Figure 22 .............................................................................................................................................................. 18

Added Figure 23, Gain vs Temperature ............................................................................................................................. 19

Added Figure 24, Gain vs Temperature ............................................................................................................................. 19

Added Figure 25, Gain vs Temperature ............................................................................................................................. 19

Added Figure 26, Gain vs Temperature ............................................................................................................................. 19

Updated Figure 29 .............................................................................................................................................................. 20

Added Figure 31, Analog Current vs Temperature ............................................................................................................. 20

Added Figure 32, Digital Current vs Temperature .............................................................................................................. 20

Added Figure 42, Power-Supply Rejection vs Gain ........................................................................................................... 22

Added Figure 43, Internal V_REFInitial Accuracy Histogram ................................................................................................ 22

Added Figure 44, IDAC Initial Accuracy Histogram ............................................................................................................ 22

Added Figure 45, IDAC Mismatch Histogram ..................................................................................................................... 22

Changed Table 11 .............................................................................................................................................................. 25

Updated Figure 55 .............................................................................................................................................................. 27

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•

Updated Figure 56 .............................................................................................................................................................. 27

Revised VREFCOM description in Internal Voltage Reference section ............................................................................. 29

Changed fourth row entry of final output code column in Table 16 .................................................................................... 31

Added ADC Power-Up section ........................................................................................................................................... 32

Added Channel Cycling and Overload Recovery section ................................................................................................... 34

Changed first three rows of hardware reset columns in Table 20 ...................................................................................... 35

Revised Channel Multiplexing Example section ................................................................................................................. 55

Revised Sleep Mode Example section ............................................................................................................................... 56

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PACKAGE MATERIALS INFORMATION

www.ti.com

30-Jul-2010

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

ADS1246IPWR

ADS1247IPWR

ADS1248IPWR

TSSOP

PW

16

20

28

2000

330.0

12.4

16.4

6.9

6.95

7.1

5.6

7.1

1.6

8.0

12.0

16.0

Q1

10.4

12.0

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

30-Jul-2010

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

ADS1246IPWR

ADS1247IPWR

ADS1248IPWR

TSSOP

PW

16

20

28

2000

346.0

29.0

33.0

Pack Materials-Page 2

MECHANICAL DATA

MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999

PW (R-PDSO-G**)

PLASTIC SMALL-OUTLINE PACKAGE

14 PINS SHOWN

0,30

0,19

M

0,10

0,65

14

8

0,15 NOM

4,50

4,30

6,60

6,20

Gage Plane

0,25

1

7

0°–8°

A

0,75

0,50

Seating Plane

0,10

0,15

0,05

1,20 MAX

PINS **

8

14

16

20

24

28

DIM

3,10

2,90

5,10

4,90

5,10

4,90

6,60

6,40

7,90

9,80

9,60

A MAX

A MIN

7,70

4040064/F 01/97

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.

D. Falls within JEDEC MO-153

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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型号：	ADS1246_14
厂家：	TEXAS INSTRUMENTS
描述：	24-Bit Analog-to-Digital Converters for Temperature Sensors
文件：	总66页 (文件大小：1112K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ADS1246_14 [TI]

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