ADS1256 [TI]
Industrial, 14kSPS, 24-Bit Analog-to-Digital Converter with Low-Drift Reference; 工业， 14kSPS ， 24位模拟数字转换器与低漂移基准电压源
| 型号： | ADS1256 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Industrial, 14kSPS, 24-Bit Analog-to-Digital Converter with Low-Drift Reference |
| 文件： | 总45页 (文件大小：573K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ADS1259
www.ti.com
SBAS424C –JUNE 2009–REVISED MARCH 2010
Industrial, 14kSPS, 24-Bit Analog-to-Digital Converter
with Low-Drift Reference
Check for Samples: ADS1259
1
FEATURES
DESCRIPTION
23
•
24 Bits, No Missing Codes
Output Data Rates From 10 To 14kSPS
High Performance:
The ADS1259 is a high-linearity, low-drift, 24-bit,
analog-to-digital converter (ADC) designed for the
needs of industrial process control, precision
instrumentation, and other exacting applications.
Combined with a signal amplifier (such as the
•
•
–
–
–
–
–
INL: 0.4ppm
Reference Drift: 2ppm/°C
Gain Drift: 0.5ppm/°C
Offset Drift: 0.05mV/°C
Noise: 0.7mVRMS at 60SPS
PGA280),
a
high-resolution,
high-accuracy
measurement system is formed that is capable of
digitizing a wide range of signals.
The converter uses a fourth-order, inherently stable,
delta-sigma (ΔΣ) modulator that provides outstanding
noise and linearity performance. The data rates are
programmable up to 14kSPS including 10SPS,
50SPS, and 60SPS that provide excellent normal
mode line-cycle rejection. The digital filter can be
programmed for a fast settling mode where the
conversions settle in a single cycle, or programmed
for a high line-cycle rejection mode. A fast responding
input over-range detector flags the conversion data if
an input over-range should occur.
•
•
•
•
•
Simultaneous 50/60Hz Rejection at 10SPS
Single-Cycle Settling
Internal Oscillator
Out-of-Range Detection
Readback Data Integrity by Checksum and
Redundant Data Read Capability
•
•
•
•
SPI™-Compatible Interface
Analog Supply: +5V or ±2.5V
Digital Supply: +2.7V to +5V
Low Power: 13mW
The ADS1259 also provides an integrated low-noise,
very low drift 2.5V reference. The on-chip oscillator,
an external crystal, or an external clock can by used
as the ADC clock source.
APPLICATIONS
Data and control communication are handled over a
4MHz, SPI-compatible interface capable of operating
with a minimum of three wires. Data integrity is
augmented by data bytes checksum and redundant
data read capability. Conversions are synchronized
either by command or by pin.
•
•
•
Industrial Process Control
Scientific Instrumentation
Test and Measurement
AVDD VREFP VREFN REFOUT
SYNCOUT
DVDD
XTAL1/CLKIN
XTAL2
Clock
Generator
2.5V
Reference
Dissipating only 13mW in operation, the ADS1259
can be powered down, dissipating less than 25mW.
The ADS1259 is offered in a TSSOP-20 package and
is fully specified from –40°C to +105°C.
fCLK/8
AINP
AINN
RESET/PWDN
START
DS
Programmable
Digital Filter
Calibration
Engine
Modulator
Control
and
Serial
DRDY
SCLK
DIN
RELATED PRODUCTS
Out-of-Range
Detection
Interface
FEATURES
24-bit ADC with integrated PGA
Wide-range PGA
PRODUCT
ADS1256
PGA280
DOUT
CS
ADS1259
AVSS
DGND
High-precision PGA; G = 1, 10, 100, 1000
PGA204
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
3
SPI is a trademark of Motorola.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2009–2010, Texas Instruments Incorporated
ADS1259
SBAS424C –JUNE 2009–REVISED MARCH 2010
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION
For the most current package and ordering information see the Package Option Addendum at the end of this
document, or see the TI web site at www.ti.com.
ABSOLUTE MAXIMUM RATINGS(1)
Over operating free-air temperature range, unless otherwise noted.
ADS1259
MIN
–0.3
MAX
+5.5
UNIT
V
AVDD to AVSS
AVSS to DGND
–2.8
+0.3
V
DVDD to DGND
–0.3
+5.5
V
Input current, momentary
Input current, continuous
Analog input voltage to DGND
Digital input voltage to DGND
Maximum junction temperature
Operating temperature range
Storage temperature range
–100
+100
mA
mA
V
–10
+10
AVSS – 0.3
–0.3
AVDD + 0.3
DVDD + 0.3
+150
V
°C
°C
°C
–40
–60
+125
+150
(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not implied.
2
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SBAS424C –JUNE 2009–REVISED MARCH 2010
ELECTRICAL CHARACTERISTICS
Minimum/maximum specifications are at TA = –40°C to +105°C. Typical specifications are at TA = +25°C, AVDD = +2.5V, AVSS = –2.5V,
DVDD = +3.3V, fCLK = 7.3728MHz, VREF = 2.5V, and fDATA = 60SPS, unless otherwise noted.
ADS1259
ADS1259B
PARAMETER
ANALOG INPUTS
TEST CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
UNIT
Full-scale input voltage range (FSR)
VIN = (AINP – AINN)
±VREF
±VREF
V
V
Absolute input voltage
(AINP, AINN to DGND)
AVSS – 0.1
AVDD + 0.1
AVSS – 0.1
AVDD + 0.1
Differential input impedance
Common-mode input impedance
SYSTEM PERFORMANCE
Resolution
120
500
120
500
kΩ
kΩ
No missing codes
Best fit method
24
10
24
10
Bits
SPS(1)
%FSR
mV
Data rate (fDATA
)
14400
±0.001
±250
14400
±0.0003
±250
Integral nonlinearity
Offset error
±0.0003
±40
±0.00004(2)
±40
Offset error after calibration(3)
Offset drift(4)
±1
±1
mV
TA = –40°C to +105°C
0.05
0.25
±0.5
0.05
0.25
±0.5
mV/°C
%
Gain error(5)
±0.05
±0.0002
0.5
±0.05
±0.0002
0.5
Gain error after calibration(3)
Gain drift(4)
%
TA = –40°C to +105°C
See Figure 41
60Hz, ac(6)
2.5
2.5
ppm/°C
Normal mode rejection
Common-mode rejection
Noise
100
120
0.7
100
120
0.7
dB
See Table 1
mV
AVDD, AVSS power-supply
rejection
60Hz, ac(6)
60Hz, ac(6)
85
85
95
85
85
95
dB
dB
DVDD power-supply rejection
110
110
OUT-OF-RANGE DETECTION
Level
±105
±0.5
±105
±0.5
%FSR
%FSR
Threshold(7)
Accuracy
VOLTAGE REFERENCE INPUTS
VREF = (VREFP –
VREFN)
AVDD – AVSS +
200mV
AVDD – AVSS +
200mV
Reference input range (VREF
)
0.5
2.5
0.5
2.5
V
V
V
Negative reference absolute input
(VREFN to DGND)
AVSS –
100mV
AVSS –
100mV
VREFP – 0.5
VREFP – 0.5
Positive reference absolute input
(VREFP to DGND)
VREFN + 0.5
AVDD + 100mV
VREFN + 0.5
AVDD + 100mV
200nA +
60nA/V
200nA +
60nA/V
Average reference input current(8)
Average reference input current drift Internal or external clock
0.2
2.5
10
0.2
nA/°C
V
INTERNAL VOLTAGE REFERENCE
VREFOUT = (REFOUT –
Reference output voltage
AVSS)
2.5
Accuracy
TA = +25°C
±0.4
40
±0.2
12
5
%
TA = –40°C to +105°C
TA = 0°C to +85°C
4
2
ppm/°C
ppm/°C
mA(9)
mV/mA
s
Temperature drift(4)
Drive current sink and source
Load regulation
–10
10
–10
10
10
1
10
1
Turn-on settling time(10)
±0.001% settling
(1) SPS = samples per second.
(2) Shaded cells indicate improved specifications of the ADS1259B.
(3) Calibration accuracy is on the level of noise (signal and ADC), reduced by the effect of 16 reading averaging.
(4) Reference drift specified by design and final production test. Drift calculated over the specified temperature range using box method.
(5) Excludes internal reference error.
(6) fDATA = 14.4kSPS. Placing a notch of the digital filter at 60Hz (setting fDATA = 10SPS or 60SPS) further improves the common-mode
rejection and power-supply rejection of this input frequency.
(7) Absolute input voltage range for out-of-range specification: AVSS + 150mV ≤ AINP or AINN ≤ AVDD – 150mV.
(8) Over the range: AVSS ≤ VREFP or VREFN ≤ AVDD. For reference voltage exceeding AVDD or AVSS, input current = 150nA/10mV.
(9) Limit the reference output current to ±10mA.
(10) CREFOUT = 1mF, CREFIN = 1mF.
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ELECTRICAL CHARACTERISTICS (continued)
Minimum/maximum specifications are at TA = –40°C to +105°C. Typical specifications are at TA = +25°C, AVDD = +2.5V,
AVSS = –2.5V, DVDD = +3.3V, fCLK = 7.3728MHz, VREF = 2.5V, and fDATA = 60SPS, unless otherwise noted.
ADS1259
ADS1259B
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
UNIT
CLOCK SOURCE (fCLK
)
Nominal frequency
Accuracy
7.3728
±0.2
7.3728
±0.2
MHz
%
Internal oscillator
±2
8
±2
8
Frequency range
Start-up time(11)
Frequency range
Duty cycle
2
7.3728
20
2
7.3728
20
MHz
ms
Crystal oscillator
External clock
0.1
40
7.3728
8
0.1
40
7.3728
8
MHz
%
60
60
DIGITAL INPUT/OUTPUT (DVDD = 2.7V to 5.25V)
VIH
VIL
0.8 DVDD
DGND
DVDD
0.8 DVDD
DGND
DVDD
V
V
0.2 DVDD
0.2 DVDD
IOH = 1mA
0.8 DVDD
0.8 DVDD
V
VOH
IOH = 8mA
IOL = 1mA
IOL = 8mA
0.75 DVDD
0.75 DVDD
V
0.2 DVDD
±10
0.2 DVDD
±10
V
VOL
0.2 DVDD
0.1
0.2 DVDD
0.1
V
Input hysteresis
Input leakage
POWER SUPPLY
AVSS
V
0 < VDIGITAL INPUT < DVDD
mA
–2.6
AVSS + 4.75
2.7
0
–2.6
AVSS + 4.75
2.7
0
V
V
V
AVDD
AVSS + 5.25
5.25
AVSS + 5.25
5.25
DVDD
Operating
(reference enabled)
2.3
200
1
3.8
2.3
200
1
3.8
|mA|
|mA|
|mA|
Sleep mode
(reference enabled)
AVDD, AVSS current
Sleep mode
(reference disabled)
40
40
Power-Down mode
Operating
1
40
700
300
10
1
40
700
300
10
|mA|
mA
500
160
1
500
160
1
DVDD current(12)
Power dissipation
Sleep mode
mA
Power-Down mode(13)
mA
Operating
13
22
13
22
mW
Sleep mode
(reference enabled)
1.5
1.5
mW
Sleep mode
(reference disabled)
0.5
10
1.2
0.5
10
1.2
mW
Power-Down mode
240
240
mW
TEMPERATURE RANGE
Specified temperature range
Operating temperature range
Storage temperature range
–40
–40
–60
+105
+125
+150
–40
–40
–60
+105
+125
+150
°C
°C
°C
(11) Crystal operation using 18pF load capacitors.
(12) Specified with internal oscillator operating (internal oscillator current: 40µA, typ).
(13) External CLKIN, SCLK stopped. Digital inputs maintained at VIH or VIL voltage levels.
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SBAS424C –JUNE 2009–REVISED MARCH 2010
PIN CONFIGURATION
PW PACKAGE
TSSOP-20
(TOP VIEW)
AINP
AINN
1
2
3
4
5
6
7
8
9
20
19
18
17
16
15
14
13
12
11
AVDD
AVSS
RESET/PWDN
START
VREFN
VREFP
REFOUT
DVDD
SYNCOUT
CS
ADS1259
SCLK
DGND
BYPASS
XTAL2
DIN
DOUT
DRDY 10
XTAL1/CLKIN
ADS1259 Terminal Functions
PIN NAME
PIN #
FUNCTION
DESCRIPTION
AINP
AINN
1
2
Analog input
Analog input
Digital input
Digital input
Digital output
Digital input
Digital input
Digital input
Digital output
Digital output
Positive analog input
Negative analog input
RESET/PWDN
START
SYNCOUT
CS
3
Reset/Power-Down; reset is active low; hold low for power-down
Start conversions, active high
Sync clock output (fCLK/8)
SPI chip-select, active low
SPI clock input
4
5
6
SCLK
7
DIN
8
SPI data input
DOUT
9
SPI data output
DRDY
10
Data ready output, active low
Internal oscillator: DGND
XTAL1/CLKIN
11
Digital input
External clock: clock input
Crystal oscillator: external crystal1
XTAL2
BYPASS
DGND
12
13
14
15
16
17
18
19
20
Digital
Analog
External crystal2, otherwise no connection
Core voltage bypass
Digital
Digital ground
DVDD
Digital
Digital power supply
REFOUT
VREFP
VREFN
AVSS
Analog output
Analog input
Analog input
Analog
Positive reference output
Positive reference input
Negative reference input
Negative analog power supply and negative reference output
Positive analog power supply
AVDD
Analog
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SPI TIMING CHARACTERISTICS
tSPWH
tSCLK
tCSH
CS
tCSSC
tSPWL
SCLK
tDIST
DIN
B7
B7
B6
B5
B5
B4
tDOPD
B3
B3
B2
B2
B1
B1
B0
B0
tDIHD
DOUT
B6
B4
tCSDOD
tDOHD
tCSDOZ
Figure 1. Serial Interface Timing
TIMING REQUIREMENTS: SERIAL INTERFACE TIMING
At TA = –40°C to +105°C and DVDD = 2.7V to 5.25V, unless otherwise noted.
SYMBOL
tCSSC
DESCRIPTION
MIN
50
MAX
UNIT
CS low to first SCLK: setup time(1)
SCLK period
ns
(2)
tSCLK
1.8
90
tCLK
ns
tSPWH
SCLK pulse width: high
90
ns
tCLK
ns
tSPWL
SCLK pulse width: low(3)
216
60
tDIST
tDIHD
Valid DIN to SCLK falling edge: setup time
Valid DIN to SCLK falling edge: hold time
SCLK rising edge to valid new DOUT: propagation delay(4)
SCLK rising edge to DOUT invalid: hold time
CS low to DOUT driven: propagation delay(4)
CS high to DOUT Hi-Z: propagation delay
CS high pulse
35
20
ns
tDOPD
tDOHD
tCSDOD
tCSDOZ
tCSH
ns
0
0
ns
40
20
ns
ns
20
tCLK
(1) CS can be tied low.
(2) tCLK = 1/fCLK
.
(3) Holding SCLK low longer than 216 × tCLK cycles resets the SPI interface (enabled by SPI register bit).
(4) DOUT load = 20pF || 100kΩ to DGND.
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SBAS424C –JUNE 2009–REVISED MARCH 2010
TYPICAL CHARACTERISTICS
At TA = +25°C, AVDD = +2.5V, AVSS = –2.5V, DVDD = 3.3V, VREF = 2.5V, VREFN = AVSS, fCLK = 7.3728MHz, and
fDATA = 60SPS, unless otherwise noted.
NOISE DISTRIBUTION HISTOGRAM
NOISE DISTRIBUTION HISTOGRAM
200
180
160
140
120
100
80
160
140
120
100
80
Data Rate = 10SPS
Shorted Input
512 Samples
Data Rate = 60SPS
Shorted Input
512 Samples
60
60
40
40
20
20
0
0
Reading (mV)
Reading (mV)
Figure 2.
Figure 3.
NOISE DISTRIBUTION HISTOGRAM
NOISE DISTRIBUTION HISTOGRAM
1600
1400
1200
1000
800
600
400
200
0
2800
2400
2000
1600
1200
800
Data Rate = 14.4kSPS
Shorted Input
4096 Samples
Data Rate = 400SPS
Shorted Input
4096 Samples
400
0
Reading (mV)
Reading (mV)
Figure 4.
Figure 5.
EFFECTIVE NUMBER OF BITS vs TEMPERATURE
EFFECTIVE NUMBER OF BITS HISTOGRAM
25
16
14
12
10
8
Data Rate = 60SPS
30 Units
Data Rate = 10SPS
24
23
Data Rate = 60SPS
22
6
21
4
20
2
Data Rate = 14.4kSPS
19
0
-55 -35 -15
5
25
45
65
85
105 125
Temperature (°C)
ENOB (rms)
Figure 6.
Figure 7.
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TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, AVDD = +2.5V, AVSS = –2.5V, DVDD = 3.3V, VREF = 2.5V, VREFN = AVSS, fCLK = 7.3728MHz, and
fDATA = 60SPS, unless otherwise noted.
NOISE vs INPUT VOLTAGE
NOISE vs INPUT VOLTAGE
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Data Rate = 10SPS
Data Rate = 60SPS
Internal Reference
CREFIN = 1mF
Internal Reference
CREFIN = 1mF
Ratiometric Configuration
REF5025
Ratiometric Configuration
REF5025
-2.5 -2.0 -1.5 -1.0 -0.5
0
0.5 1.0 1.5 2.0 2.5
-2.5 -2.0 -1.5 -1.0 -0.5
0
0.5 1.0 1.5 2.0 2.5
VIN (V)
VIN (V)
Figure 8.
Figure 9.
NOISE vs REFERENCE VOLTAGE
NOISE vs INPUT VOLTAGE
10
8
10
9
8
7
6
5
4
3
2
1
0
Shorted Input
Internal Reference
CREFIN = 1mF
REF5025
Data Rate = 14.4kSPS
6
Ratiometric Configuration
Data Rate = 14.4kSPS
Data Rate = 10SPS
Data Rate = 16.6SPS
4
Data Rate = 400SPS
2
Data Rate = 14.4kSPS
0
-2.5 -2.0 -1.5 -1.0 -0.5
0
0.5 1.0 1.5 2.0 2.5
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Reference Voltage (V)
VIN (V)
Figure 10.
Figure 11.
LINEARITY DEVIATION vs INPUT LEVEL
INTEGRAL NONLINEARITY vs TEMPERATURE
3
2
3.0
2.5
2.0
1.5
1.0
0.5
0
5 Units
T = +125°C
T = +85°C
T = +25°C
T = -40°C
1
0
-1
-2
-3
-2.5 -2.0 -1.5 -1.0 -0.5
0
0.5 1.0 1.5 2.0 2.5
-55 -35 -15
5
25
45
65
85
105 125
Input Signal (V)
Temperature (°C)
Figure 12.
Figure 13.
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TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, AVDD = +2.5V, AVSS = –2.5V, DVDD = 3.3V, VREF = 2.5V, VREFN = AVSS, fCLK = 7.3728MHz, and
fDATA = 60SPS, unless otherwise noted.
OFFSET vs TEMPERATURE
GAIN vs TEMPERATURE
100
75
500
400
5 Units
5 Units
300
50
200
100
25
0
0
-100
-200
-300
-400
-500
-25
-50
-75
-55 -35 -15
5
25
45
65
85
105 125
-55 -35 -15
5
25
45
65
85
105 125
Temperature (°C)
Temperature (°C)
Figure 14.
Figure 15.
OFFSET DRIFT DISTRIBUTION HISTOGRAM
GAIN DRIFT DISTRIBUTION HISTOGRAM
30
25
20
15
10
5
20
16
12
8
60 Units From Two Production Lots
60 Units From Two Production Lots
4
0
0
Gain Drift (ppm/°C)
Offset Drift (mV/°C)
Figure 16.
Figure 17.
INTEGRAL NONLINEARITY vs REFERENCE VOLTAGE
GAIN ERROR AND OFFSET vs REFERENCE VOLTAGE
3.0
50
150
100
50
40
30
2.5
2.0
1.5
1.0
0.5
0
20
10
0
0
-10
-20
-30
-40
-50
-50
-100
-150
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Reference Voltage (V)
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Reference Voltage (V)
Figure 18.
Figure 19.
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TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, AVDD = +2.5V, AVSS = –2.5V, DVDD = 3.3V, VREF = 2.5V, VREFN = AVSS, fCLK = 7.3728MHz, and
fDATA = 60SPS, unless otherwise noted.
POWER-SUPPLY AND COMMON-MODE REJECTION vs
FREQUENCY
POWER-SUPPLY CURRENT vs TEMPERATURE
4.0
140
120
100
80
CMR
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
DVDD
DVDD
CMR
AVDD, AVSS (Internal Reference On)
AVDD, AVSS
AVDD
AVSS
60
40
20
DVDD
-55 -35 -15
0
10
100
1k
10k
100k
1M
5
25
45
65
85
105 125
Power-Supply and Common-Mode Frequency (Hz)
Temperature (°C)
Figure 20.
Figure 21.
INTERNAL REFERENCE VOLTAGE vs TEMPERATURE
INTERNAL REFERENCE VOLTAGE vs TEMPERATURE
2.501
2.504
ADS1259B
ADS1259
2.500
2.499
2.498
2.497
2.496
2.502
2.500
2.498
2.496
2.494
-50
-25
0
25
50
75
100
125
-55 -35 -15
5
25
45
65
85
105 125
Temperature (°C)
Temperature (°C)
Figure 22.
Figure 23.
OUT-OF-RANGE THRESHOLD vs TEMPERATURE
OUT-OF-RANGE THRESHOLD DISTRIBUTION HISTOGRAM
2.0
18
Relative to ±105%
5 Units
1.6
1.2
16
14
12
10
8
30 Units
0.8
0.4
0
-0.4
-0.8
-1.2
-1.6
-2.0
6
4
2
0
-55 -35 -15
5
25
45
65
85
105 125
Temperature (°C)
Threshold Error (%)
Figure 24.
Figure 25.
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TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, AVDD = +2.5V, AVSS = –2.5V, DVDD = 3.3V, VREF = 2.5V, VREFN = AVSS, fCLK = 7.3728MHz, and
fDATA = 60SPS, unless otherwise noted.
REFERENCE INPUT CURRENT vs TEMPERATURE
REFERENCE INPUT CURRENT vs REFERENCE VOLTAGE
0
250
200
150
100
50
-25
-50
VREFP Input Current
-75
-100
VREFN Input Current
(VREFP = AVDD)
-125
-150
-175
-200
-225
-250
0
VREFN Input Current
-50
-100
-150
VREFP Input Current
(VREFN = AVSS)
-200
-250
0.5
1.0 1.5 2.0
2.5
3.0
3.5
4.0
4.5
5.0
-55 -35 -15
5
25
45
65
85
105 125
VREF (V)
Temperature (°C)
Figure 26.
Figure 27.
DIFFERENTIAL INPUT IMPEDANCE vs TEMPERATURE
INTERNAL REFERENCE SETTLING TIME
130
0.010
0.008
0.006
0.004
0.002
0
CREFIN = 1mF X7R
128
Internal Oscillator
126
External Crystal
124
-0.002
-0.004
-0.006
-0.008
-0.010
122
120
0
1
2
3
4
5
6
-55 -35 -15
5
25
45
65
85
105 125
Time (s)
Temperature (°C)
Figure 28.
Figure 29.
INTERNAL OSCILLATOR vs TEMPERATURE
7.50
7.45
7.40
7.35
7.30
7.25
7.20
-55 -35 -15
5
25
45
65
85
105 125
Temperature (°C)
Figure 30.
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OVERVIEW
The ADS1259 is
a
high-linearity, low drift
The digital filter receives the modulator signal and
provides the digital output. The filter consists of a
fifth-order sinc filter followed by a programmable
averager, selectable as either a sinc1 or sinc2. In
sinc1 mode, the filter settles in a single conversion.
The programmable averaging yields output data rates
from 10SPS to 14.4kSPS.
analog-to-digital converter (ADC) designed for the
needs of industrial process control, precision
instrumentation, and similar applications. The
converter provides high-resolution, 24-bit output data
at sample rates ranging from 10SPS to 14.4kSPS.
Figure 31 shows a block diagram of the ADS1259.
The device allows unipolar or bipolar analog
power-supply configuration (AVDD – AVSS = 5V
total). The analog supplies may be set to single +5V
to accept unipolar (or offset-bipolar) signals or the
supplies can be set to ±2.5V to accept true bipolar
signals. The operating range of the digital power
supply (DVDD) is 2.7V to 5V.
The ADS1259 integrates a low-drift, low-noise +2.5V
reference. The internal reference can drive loads up
to ±10mA. The ADS1259 also operates from an
external reference if desired. The reference input is
buffered to reduce loading of external circuits.
An onboard oscillator is provided as the clock source
for the device. Optionally, an external crystal can be
used. As a third clock option, the device can be
driven by an external clock source. SYNCOUT is an
output that provides a 1/8 rate clock intended to drive
the chopping clock input of the PGA280.
An internal low dropout regulator (LDO) powers the
digital core from the DVDD supply while the device
I/O operates directly from DVDD. BYPASS is the
LDO output and requires a 0.1mF or larger capacitor
to ground.
Gain and offset registers scale the digital filter output
to produce the final code value. On-command
calibration corrects for system offset and gain errors.
The inherently stable, fourth-order, ΔΣ modulator
measures the differential input signal [VIN = (AINP –
AINN)] against the differential reference [VREF
=
An SPI-compatible serial interface provides the
control and configuration as well as the data interface
to the ADS1259. Onboard registers combined with
commands are used to control and configure the
device.
(VREFP – VREFN)]. A fast responding out-of-range
detector flags the output data if the input should
over-range while converting.
The RESET/PWDN pin is dual function. A momentary
low resets the device and, if the pin is held low,
powers down the device. The START pin, as well as
commands, controls the conversions.
AVDD
VREFP VREFN
BYPASS DVDD
SYNCOUT
XTAL1/CLKIN
XTAL2
+1.8V
(Digital Core)
Clock
Generator
2.5V
Reference
fCLK/8
LDO
REFOUT
AINP
AINN
RESET/PWDN
START
DS
Programmable
Digital Filter
Calibration
Engine
Modulator
Control
and
Serial
DRDY
SCLK
DIN
FLAG
Out-of-Range
Detection
Interface
DOUT
CS
ADS1259
AVSS
DGND
Figure 31. ADS1259 Block Diagram
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NOISE PERFORMANCE
MODULATOR
The ADS1259 offers excellent noise performance that
can be optimized by adjusting the data rate and by
selection of the digital filter mode. As the averaging is
increased by reducing the data rate, the noise drops
correspondingly. Additionally, because the sinc2
digital filter provides more filtering than the sinc1
digital filter, sinc2 provides lower noise conversions.
Table 1 shows the noise as a function of data rate
and filter mode.
The
high-performance
modulator
is
an
inherently-stable, fourth-order, ΔΣ, 2 + 2 pipelined
structure, as shown in Figure 32. It shifts the
quantization noise to a higher frequency (out of the
passband) where digital filtering can easily remove it.
fMOD = fCLK/8
2nd-Order
DS
Analog Input (VIN
)
1st-Stage
Table 1 expresses typical noise data in several ways:
RMS noise, effective number of bits (ENOB), and
noise-free bits. ENOB is calculated from Equation 1:
To Digital Filter
2nd-Order
DS
2nd-Stage
FSR
ln
4th-Order Modulator
RMS Noise
ENOB =
ln(2)
Figure 32. Fourth-Order Modulator
Where:
FSR = 2VREF
(1)
The modulator first stage converts the analog input
voltage into a pulse-code modulated (PCM) stream.
When the level of differential analog input (AINP –
AINN) is near the level of the reference voltage
(VREFP – VREFN), the 1s density of the PCM data
stream is at its highest. When the level of the
differential analog input is near zero, the PCM 0s and
1s densities are nearly equal. At the two extremes of
the analog input levels (+FS and –FS), the 1s density
of the PCM streams are approximately +90% and
+10%, respectively.
The calculation of noise-free bits uses the same
formula as Equation 1, except that the peak-to-peak
noise value is used instead of RMS noise.
ADC
The analog-to-digital converter (ADC) section of the
ADS1259 is composed of two blocks: a high accuracy
modulator and a programmable digital filter.
The modulator second stage produces a 1s density
data stream designed to cancel the quantization
noise of the first stage. The data streams of the two
stages are then combined in the digital filter stage.
Table 1. Typical Noise Data vs Data Rate and Digital Filter(1)
SINC1 DIGITAL FILTER
SINC2 DIGITAL FILTER
DATA
RATE
(SPS)
SAMPLE
SIZE(2)
NOISE
NOISE
ENOB
(RMS)
NOISE-
FREE BITS
NOISE
NOISE
ENOB
(RMS)
NOISE-
FREE BITS
(mVRMS
)
(mVPP
1.8
2.4
3.5
4
)
(mVRMS
0.45
0.5
)
(mVPP
1.6
2
)
10
16.6
50
128
256
0.5
23.3
23.1
22.9
22.8
21.8
21.1
20.3
19.6
21.4
21.0
20.4
20.3
19.0
18.2
17.3
16.6
23.4
23.3
23.0
22.9
22.0
21.3
21.6
21.3
20.7
20.4
19.2
18.4
0.55
0.65
0.7
512
0.6
3
60
512
0.65
1.2
3.5
8.3
14
400
4096
8192
8192
8192
1.4
9.5
17
1200
3600
14400
2.3
2
3.9
32
3.4
(3)
27
(3)
20.5
(3)
17.5
(3)
6.2
50
(1) Noise data taken with shorted analog inputs and internal 2.5V reference using the circuit of Figure 63.
(2) Data sample sizes used for analysis.
(3) Same as sinc1 mode.
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MODULATOR OVERLOAD BEHAVIOR
ADS1259 recovers as normal. Note that the linear
input range is ±100mV beyond the analog supply
voltages; with input levels greater than this range,
use care to limit the input current to 100mA peak
transient (10mA continuous).
The ADS1259 modulator is inherently stable and
therefore has predictable recovery behavior resulting
from an input overdrive condition. The modulator
does not exhibit the self-resetting behavior of other
modulator types, which often results in unstable
output conversion results when overdriven.
INPUT OUT-OF-RANGE DETECTION (FLAG)
The ADS1259 has a fast-responding out-of-range
circuit that triggers when the differential input exceeds
+105% or –105% of FSR (±1.05 VREF). The
out-of-range circuit latches the result of the
comparator output and appends the result as either
the LSB of conversion data or as bit 7 of the data
checksum byte. After the conversion data are read, or
after a new conversion is started, the comparator
latch is reset. Figure 33 and Figure 34 show the
detection block diagram and the detection operation,
respectively. See the Data Checksum Byte and FLAG
Bit section for more detail.
The ADS1259 modulator outputs a 1s density data
stream at 90% duty cycle with the positive full-scale
input signal applied (10% duty cycle with the negative
full-scale signal). If the input is overdriven past 90%
modulation, but below 100% modulation (10% and
0% for negative overdrive, respectively), the
modulator remains stable and continues to output the
1s density data stream. The digital filter may or may
not clip the output codes to +FS or –FS, depending
on the duration of the overdrive. When the input is
returned to the normal range from a long duration
overdrive (worst case), the modulator returns
immediately to the normal range, but the group delay
of the digital filter delays the return of the conversion
result to within the linear range (one reading for the
sinc1 filter and two readings for completely settled
data).
AINP
å
IABSI
J
1.05 VREF
AINN
Q
fMOD/2
FLAG
K
Data Read
Reset
If the inputs are sufficiently overdriven to drive the
modulator to full duty cycle (that is, all 1s or all 0s),
the modulator enters a stable saturated state. The
digital output code may clip to +FS or –FS, again
depending on the duration. A small duration overdrive
may not always clip the output code. When the input
returns to the normal range, the modulator requires
up to 12 modulator clock cycles (fMOD) to exit
saturation and return to the linear region. The digital
filter requires two additional conversions (sinc1, more
for sinc2) for fully settled data.
Figure 33. Input Out-Of-Range Detect Block
Diagram
+105
(Conversions)
0
-105
In the extreme case of over-range, either input is
overdriven exceeding that either analog supply
voltage plus an internal ESD diode drop. The internal
ESD diodes begin to conduct and the signal on the
input is clipped. If the differential input signal range is
not exceeded, the modulator remains in linear
operation. If the differential input signal range is
exceeded, the modulator is saturated but stable, and
outputs all 1s or 0s. When the input overdrive is
removed, the diodes recovery quickly and the
1
FLAG
Bit
0
Figure 34. Input Out-Of-Range Detect Operation
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ANALOG INPUTS (AINP, AINN)
ESD diodes protect the analog inputs. To keep these
diodes from turning on, make sure the voltages on
the input pins do not go below AVSS by more than
300mV, and likewise do not exceed AVDD by more
than 300mV.
The ADS1259 measures the differential input signal
VIN = (AINP – AINN) against the differential reference
VREF = (VREFP – VREFN) using internal capacitors
that are continuously charged and discharged.
Figure 36 shows the simplified schematic of the ADC
input circuitry; the right side of the figure illustrates
the input circuitry with the capacitors and switches
replaced by an equivalent circuit. Figure 35
demonstrates the ON/OFF timings for the switches of
Figure 36.
AVSS – 300mV < (AINP or AINN) < AVDD + 300mV.
Note that the valid input range is:
AVSS – 100mV < (AINP or AINN) < AVDD + 100mV
tSAMPLE = 1/fMOD
ON
S1
In Figure 36, S1 switches close during the input
sampling phase. With switch S1 closed, CA1 charges
to AINP, CA2 charges to AINN, and CB charges to
(AINP – AINN). For the discharge phase, S1 opens
first and then S2 closes. CA1 and CA2 discharge to
approximately to AVSS + 2.5V and CB discharges to
0V. This two-phase sample/discharge cycle repeats
with a period of tSAMPLE = 1/fMOD. fMOD is the operating
frequency of the modulator, where fMOD = fCLK/8.
OFF
ON
S2
OFF
Figure 35. S1 and S2 Switch Timing for Figure 36
Although optimized for differential signals, the
ADS1259 inputs may be driven with a single-ended
signal by fixing one input to AVSS or mid-supply. Full
dynamic range is achieved when the inputs are
The charging of the input sampling capacitors draws
a transient current from the source driving the
ADS1259 ADC inputs. The average value of this
current can be used to calculate an effective
impedance (REFF) where REFF = VIN/IAVERAGE. These
impedances scale inversely with fMOD. For example, if
fMOD is reduced by a factor of two, the impedances
double. Note that the sampling capacitors can vary
±15% over production lots and typically vary 1% with
temperature. The variations of the sampling
capacitors have a corresponding effect on the analog
input impedance.
differentially driven ±VREF
.
As a result of the switched-capacitor input structure of
the ADS1259, a buffer is recommended to drive the
analog inputs. An input filter comprised of 20Ω to 50Ω
resistors and 10nF capacitors should be used
between the buffer and the ADS1259 inputs.
(fMOD = 0.9216MHz)
AVSS + 2.5V
AVDD
AVSS + 2.5V
S2
REFF A = 500kW
CA1 = 2pF
CB = 8pF
ESD Diodes
Equivalent
AINP
AINP
AINN
Circuit
S1
S1
REFF B = 130kW
AINN
REFF A = 500kW
CA2 = 2pF
ESD Diodes
S2
AVSS + 2.5V
1
REFF
=
f
MOD ´ CX
AVSS
AVSS + 2.5V
RDIFF = REFF B || 2REFF A = 120kW
RCOM = REFF A = 500kW
and fMOD = fCLK/8
Figure 36. Simplified ADC Input Structure
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REFERENCE
the ADC reference input pins, VREFP and VREFN.
(Note that these device pins are not intended to drive
external circuits.) An external 1mF capacitor,
connected from VREFP to VREFN, is recommended
for noise reduction. The capacitor can be increased
for increased noise filtering, but the settling time of
the reference may also increase. The settling time
should be considered upon activating the internal
reference.
The ADS1259 includes an onboard voltage reference
with a low temperature coefficient. The reference
voltage is 2.5V with the capability of sinking and
sourcing 10mA via the REFOUT pin. The ADS1259
can also operate from an external reference. The
external reference is the default selection. Refer to
Figure 37 for a reference block diagram.
Internal Reference
See Figure 29 for typical reference settling CREFIN =
1µF. The capacitor dielectric absorption results in
increased settling time for RC filter circuits.
The reference output is provided between pins
REFOUT and AVSS. Because the reference output
return shares the same pin as AVSS, route the
reference return trace and the AVSS trace
independently as Kelvin-connected printed circuit
board (PCB) traces. For stability reasons, connect a
1mF capacitor between REFOUT and AVSS.
To activate the internal reference, set the register bit
RBIAS = 1. This enables the reference bias. Once
biased, the internal reference can then be selected as
the ADC reference by the register bit EXTREF.
EXTREF = 0 closes the internal switches.
An internal switch connects the internal reference to
AVDD
Reference Bias
RBIAS Register Bit
(1 = Bias On)
REFOUT
(+)
2.5V
Reference
+
1mF
Reference Output
(CREFOUT
)
(-)
AVSS
Reference Select
EXTREF Register Bit
(1 = Switch Open for External Reference)
2kW
VREFP
(+)
Reference Input
(-)
(+)
+
1mF
(CREFIN
ADC Reference Input
)
(-)
VREFN
Figure 37. Reference Block Diagram
Table 2. Reference Selection for Figure 37
ADS1259 REFERENCE
Internal
RBIAS REGISTER BIT
EXTREF REGISTER BIT
1
0
1
(1)
External
See
(1) If the reference output is not required, set RBIAS = 0. If the reference output is enabled (RBIAS = 1), an external 1µF capacitor must be
used between REFOUT and AVSS.
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Reference Drift
For external reference applications, place a 1mF
(minimum) capacitor close to the VREFP and VREFN
pins.
The ADS1259 internal reference is designed for
minimal drift error, which is defined as the change in
reference voltage over temperature. The drift is
calculated using the box method, as described by
Equation 2.
Because the ADS1259 measures the signal inputs
(AINP and AINN) against the reference inputs
(VREFP and VREFN), reference noise and drift may
degrade overall system performance. In ratiometric
measurement applications, reference noise and drift
have a cancelling effect. In absolute measurement
applications, reference noise and drift directly effect
the conversion results.
V
REFMAX - VREFMIN
Drift =
x 106 (ppm)
V
REFNOM ´ Temp Range
Where:
VREFMAX, VREFMIN, and VREFNOM are the maximum,
minimum, and nominal reference output voltages,
respectively, over the specified temperature
Voltage Reference Inputs (VREFP, VREFN)
ESD diodes protect the reference inputs. To keep
these diodes from turning on, make sure the voltages
on the reference pins do not go below AVSS by more
than 300mV, and likewise do not exceed AVDD by
more than 300mV.
range.
(2)
The ADS1259 internal reference features a maximum
drift coefficient of 5ppm/°C over 0°C to +85°C
operating range and 12ppm/°C over –40°C to +105°C
operating range.
The absolute maximum reference input range is:
External Reference
AVSS – 300mV < (VREFP or VREFN) < AVDD + 300mV(3)
To select the ADS1259 for external reference
operation, set the EXTREF register bit = 1 (default). If
desired, the internal reference can continue to
provide a +2.5V reference output via the REFOUT
and AVSS pins. In this case, set the RBIAS register
bit = 1 to power the internal reference. If the internal
reference is activated, an external 1mF capacitor from
REFOUT to AVSS is required.
Note that the valid operating range of the reference
inputs are shown in the Electrical Characteristics
table.
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DIGITAL FILTER
The SINC2 register bit selects either the sinc1 or sinc2
filter. The sinc1 filter settles in one conversion cycle
while the sinc2 filter settles in two conversion cycles.
However, the sinc2 filter has the benefit of wider
frequency notches which improve line cycle rejection.
The programmable low-pass digital filter receives the
modulator output and produces a high-resolution
digital output. By adjusting the amount of filtering,
tradeoffs can be made between resolution and data
rate: filter more for higher resolution, filter less for
higher data rate.
FREQUENCY RESPONSE
The low-pass digital filter sets the overall frequency
response of the ADS1259. The filter response is the
product of the fixed and programmable filter sections,
and is given by Equation 4:
The filter consists of two sections: a fixed decimation
sinc5 filter followed by a variable decimation filter,
configurable as sinc1 or sinc2, as illustrated in
Figure 38. The sinc5 filter has fixed decimation of 64
and reduces the data rate of the modulator from
fCLK/8 to fCLK/512. The second filter stage receives the
data from the sinc5 filter. The second filter stage has
programmable averaging (or decimation) and can be
configured in either sinc1 or sinc2 mode. The
decimation ratio of this stage sets the final output
data rate. As detailed in Table 3, the DR[2:0] register
bits program the decimation ratio and the final output
data rate. The output data rates are identical for both
sinc1 and sinc2 filters.
½H(f)½ = ½Hsinc5(f)½ ´ ½HsincN(f)½ =
5
N
512p ´ f
512p ´ R ´ f
sin
sin
fCLK
fCLK
´
8p ´ f
512p ´ f
64 ´ sin
R ´ sin
fCLK
fCLK
where:
N = 1 (sinc1)
N = 2 (sinc2)
Table 3. Decimation Ratio of Final Filter Stage
R = Decimation ratio (refer to Table 3)
(4)
DR[2:0] REGISTER
BITS
DECIMATION
RATIO (R)
DATA RATE (SPS)
The digital filter attenuates noise on the modulator
output, including noise from within the ADS1259 and
external noise present within the ADS1259 input
signal. Adjusting the filtering by changing the
decimation ratio used in the programmable filter
changes the filter bandwidth. With a higher number of
decimation, the bandwidth is reduced and more noise
is attenuated.
111
110
101
100
011
010
001
000
1
4
14400
3600
1200
400
60
12
36
240
288
864
1440
50
16.6
10
Modulator Rate = fCLK/8
fCLK/512
sinc1 Filter
sinc5 Filter
(decimate by 64)
Output
Data Rate = fCLK/(R ´ 512)
Analog
Modulator
sinc2 Filter
SINC2 Register Bit
(0 = sinc1)
DR[2:0] Register Bits
(Program Decimation)
Figure 38. Block Diagram of Digital Filter
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The sinc5 filter produces wide notches at fCLK/512 and
multiples thereof. At these frequencies the filter has
zero gain. Figure 39 shows the response data rate =
14.4kSPS.
0
-20
-40
With decimation of the second stage, the wide
notches produced by the sinc5 filter remain, but a
number of narrow notches are superimposed in the
response. The first of the notches occur at the data
rate. The number of superimposed notches is
determined by the decimation ratio, minus 1.
-60
-80
-100
-120
-140
The second stage filter has notches (or zeroes) at the
data rate and multiples thereof. Figure 40 shows the
response of the second stage filter combined with the
0
10
20
30
40
50
60
Frequency (kHz)
sinc5 stage. Decimation of
4
produces three
equally-spaced notches between each main notch of
the sinc5 filter. The frequency response of the other
data rates (higher decimation ratios) produces a
similar pattern, but with more equally-spaced notches
between the main sinc5 notches. Table 4 lists the first
notch frequency and the –3dB bandwidth.
Figure 39. Frequency Response
for Data Rate = 14.4kSPS
0
-20
sinc2
sinc1
Figure 41 illustrates the detail of the magnitude
response with data rate = 60SPS. Note that input
frequencies within the ±1% 60Hz bandwidth are
attenuated 40dB by the sinc1 filter and 80dB by the
sinc2 filter.
-40
-60
-80
Table 4. First Notch Frequency and –3dB Filter
Bandwidth(1)
-100
-120
-140
–3dB BANDWIDTH (Hz)
DATA RATE FIRST NOTCH
(SPS)
10(2)
16.6(3)
50
(Hz)
sinc1
sinc2
0
10
20
30
40
50
60
10
4.3
3.1
Frequency (kHz)
16.6
50
7.3
5.2
22
16
Figure 40. Frequency Response
(Data Rate = 3600SPS, R = 4)
60
60
27
19
400
400
177
525
1440
2930
127
380
1100
See (4)
1200
3600
14400
1200
3600
14400
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
(1) fCLK = 7.3728MHz.
(2) Notch at 50Hz and 60Hz.
(3) Notch at 50Hz.
sinc1
sinc2
(4) Same as sinc1.
55
56
57
58
59
60
61
62
63
64 65
Frequency (Hz)
Figure 41. Magnitude Response
for Data Rate = 60SPS
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ALIASING
CLOCK SOURCE
The low-pass characteristic of the digital filter repeats
at multiples of the modulator rate (fMOD = fCLK/8).
Figure 42 shows the responses plotted out to
7.3728MHz at the data rate of 14.4kSPS. Notice how
the responses near dc, 0.9216MHz, 1.8432MHz,
2.7698MHz, etc, are the same as given by f =
NfMOD ± fDATA where N = 0, 1, 2, etc. The digital filter
attenuates high-frequency noise on the ADS1259
inputs up to the frequency where the response
repeats. However, noise or frequency components
existing in the signal where the response repeats
alias into the passband. Often, a simple RC antialias
filter is sufficient to reject these input frequencies.
There are three ways to provide the ADS1259 clock:
the internal oscillator, an external clock, or an
external crystal/ceramic resonator. The ADS1259
selects the clock source automatically. Figure 43
shows the clock select block. If either external clock
sources are present, the internal oscillator is disabled
and the external clock source is selected. If no
external clock is present, the internal oscillator is
selected. The ADS1259 continuously monitors the
clock source. The clock source can be polled by the
EXTCLK bit (bit 6 of register CONFIG2), 0 = internal
oscillator, 1 = external clock.
The data rate and corresponding filter notches scale
by the accuracy of clock frequency. Consideration
should be given to the clock accuracy and the
corresponding effect to the notch frequency locations.
0
-20
-40
-60
Clock
Detect
XTAL1/CLKIN
-80
ENB
Internal
Oscillator
-100
-120
-140
XTAL2
S0
S1
SEL
MUX
System Clock
0
0.9
1.8
2.8
3.7
4.6
5.5
6.5
7.4
Frequency (MHz)
Figure 43. Equivalent Circuitry of the Clock
Source
Figure 42. Frequency Response to 7.3728MHz
(Data Rate = 14400SPS)
Internal Oscillator
Figure 44 shows the internal oscillator connection.
XTAL1/CLKIN is grounded and XTAL2 is not
connected (floating). The internal oscillator draws
approximately 40mA from the DVDD supply. Note that
the internal oscillator has ±2% accuracy over
temperature. The oscillator accuracy has
a
corresponding effect on line-cycle notch frequency
locations.
XTAL1/CLKIN
XTAL2
Figure 44. Internal Oscillator Connection
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a digital output pin intended to
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External Clock
SYNCOUT
Figure 45 shows the external clock connection. The
clock is applied to XTAL1/CLKIN and XTAL2 floats.
Make sure a clean clock input is applied to the
ADS1259, free of overshoot and glitches. A series
resistor often helps to reduce overshoot and should
be placed close to the driving end of the clock
source.
SYNCOUT is
synchronize the chopping frequency of the PGA280
to the sampling frequency of the ADS1259.
Synchronizing the PGA280 to the ADS1259 places
the PGA280 chopped 1/f noise at an exact null in the
ADS1259 frequency response, where the PGA280 1/f
noise is rejected.
SYNCOUT frequency is equal to the ADS1259 clock
rate divided by 8 (fSYNCOUT = fCLK/8). The output clock
is enabled by the register bit SYNCOUT. Disabling
the output stops the clock but the output remains
actively driven low. In power-down mode, the
SYNCOUT output becomes an input. As with all
digital inputs, the pin must not be allowed to float. An
external 1MΩ pull-down resistor is recommended to
ground the input in power-down mode.
50W
External
XTAL1/CLKIN
Clock
XTAL2
Figure 45. External Clock Connection
Crystal Oscillator
The SYNCOUT clock is reset when START is
received and whenever registers CONFIG[2:0] are
changed. Connect SYNCOUT to the PGA280
SYNCIN pin through a 4.7kΩ series resistor. Place
the resistor as close as possible to the ADS1259
SYNCOUT pin.
Figure 46 shows the crystal oscillator connection. The
crystal connects to XTAL1/CLKIN and XTAL2 and the
capacitors connect to ground. The crystal and
capacitors should be placed close to the device pins
with short, direct traces. Neither the XTAL1/CLKIN
nor the XTAL2 pins can be used to drive any other
logic. Table 5 lists the recommended crystal for the
ADS1259. If using other crystals, verify the oscillator
start-up behavior.
SLEEP MODE
SLEEP mode is started by sending the SLEEP
command. In SLEEP mode, the device enters a
reduced power state and only a minimum of circuitry
is kept active. The WAKEUP command exits the
SLEEP mode and after which 512 fCLK cycles are
counted before the ADS1259 is ready for
communication. The register settings are unaffected
in SLEEP.
XTAL1/CLKIN
C1
Crystal
(7.3728MHz)
XTAL2
C2
C1, C2: 5pF to 20pF
SLEEP does not change the RBIAS register bit. For
quick conversions after WAKEUP, keep the internal
reference bias on before entering SLEEP. Otherwise,
after exiting SLEEP mode, allow time for the
reference to settle. Alternatively, to minimize power
consumption during SLEEP, set the internal reference
bias off prior to engaging SLEEP. Note that in SLEEP
mode the SPI timeout function is disabled.
Figure 46. Crystal Connection
Table 5. Recommended Crystal
MANUFACTURER
FREQUENCY
PART NUMBER
ECS
7.3728MHz
ECS-73-18-10
BYPASS
The digital core of the ADS1259 is powered by an
internal low dropout regulator (LDO). The DVDD
supply is the LDO input and the BYPASS pin is the
LDO output. A 1mF capacitor must be connected from
the LDO output to DGND. No other load current
should be drawn from the BYPASS pin.
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RESET/PWDN
RESET
The RESET/PWDN pin has two functions: device
power-down and device reset. Momentarily holding
the pin low resets the device and holding the pin low
for 216 fCLK cycles activates the Power-Down mode.
There are three methods to reset the ADS1259: cycle
the power supplies, take RESET/PWDN low, or send
the RESET opcode command.
When using the RESET/PWDN pin, take it low to
force a reset. Make sure to follow the minimum pulse
width timing specifications before taking the RESET
pin back high.
POWER-DOWN MODE
In power-down mode, internal circuit blocks are
disabled (including the oscillator, reference, and SPI)
and the device enters a micro-power state. To
engage power-down mode, hold the RESET/PWDN
pin low for 216 fCLK cycles. Note that the register
contents are not saved because they are reset when
RESET/PWDN goes high.
The RESET command takes effect on the eighth
falling SCLK edge of the opcode command. On reset,
the configuration registers are initialized to the default
states and the conversion cycle restarts. After reset,
allow eight fCLK cycles before communicating to the
ADS1259. Note that when using the reset command,
the SPI interface itself may require reset before
accepting the command. See the SPI Timing
Characteristics section for details.
Keep the digital inputs at defined VIH or VINL logic
levels (do not 3-state). To minimize power-supply
leakage current, disable the external clock. Note that
the ADS1259 digital outputs remain active in
power-down. The analog signal inputs may float.
POWER-ON SEQUENCE
To exit power-down, take RESET/PWDN high. Wait
216 fCLK cycles before communicating to the
ADS1259, as shown in Figure 47.
The ADS1259 has three power supplies: AVDD,
AVSS, and DVDD. The supplies can be sequenced in
any order but be sure that at any time the analog
inputs do not exceed AVDD or AVSS and the digital
inputs do not exceed DVDD. After the last power
supply has crossed the respective power-on
threshold, 216 fCLK cycles are counted before
releasing the internal reset. After the internal reset is
released, the ADS1259 is ready for operation.
Figure 48 shows the power-on sequence of the
ADS1259.
tLOW
RESET/PWDN
tRHSC
SCLK
Figure 47. RESET/PWDN Timing
Table 6. Timing Characteristics for Figure 47
SYMBOL
tLOW
DESCRIPTION
Pulse width low for reset
MIN
UNIT
tCLK
tCLK
tCLK
tCLK
4
216
tLOW
Pulse width low for power-down
Reset high to SPI communication start
Exit power-down to SPI communication start
tRHSC
tRHSC
8
216
3.5V nom
AVDD - AVSS
1V nom
DVDD
CLK
216 ´ tCLK
ADS1259 Operational
Internal Reset
Figure 48. Power-On Sequence
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START
When using commands to control conversions, hold
the START pin low. The ADS1259 features two
modes to control conversions: Gate Control mode
and Pulse Control mode. The mode is selected by the
PULSE register bit.
START is a digital input that controls the ADS1259
conversions. Conversions are started when START is
taken high and are stopped when START is taken
low. If START is toggled during a conversion, the
conversion is restarted. DRDY goes high when
START is taken high. Figure 49 andTable 7 show the
START timing.
Gate Control Mode (PULSE Bit = 0, Default)
Conversions begin when either the START pin is
taken high or when the START command is sent.
Conversions continue indefinitely until the START pin
is taken low or the STOP command is transmitted. As
seen in Figure 50, DRDY is forced high when the
conversion starts and falls low when data are ready.
When stopped, the conversion in process completes
and further conversions are halted. Figure 49 and
Table 7 show the timing of DRDY and START.
Note that reasserting START within 22 tCLK cycles of
the DRDY falling edge causes DRDY to fall soon
after. This conversion result should be discarded. The
next DRDY falling edge, as given in Table 9, is the
valid conversion data.
tSDSU
tSTDR
DRDY
tPWH
tDSHD
START
or
START Pin
tPWL
STOP
or
START
or
Command(1)
START
STOP
START
Command(1)
STOP
(1) START and STOP commands take effect on the seventh SCLK
falling edge.
Converting
Halted
Halted
Figure 49. START to DRDY Timing
DRDY
CONVERSION CONTROL
(1) START and STOP opcode commands take effect on the
seventh SCLK falling edge.
The conversions of the ADS1259 are controlled by
either the START pin or by the START command.
Figure 50. Gate Control Mode
Table 7. START Timing (See Figure 49)
SYMBOL
DESCRIPTION
MIN
MAX
UNIT
START pin low or STOP opcode to DRDY setup time to halt further
conversions
tSDSU
16
tCLK
START pin low or STOP opcode hold time to complete current
conversion (gate mode)
tDSHD
16
4
tCLK
tPWH, L
tSTDR
START pin pulse width high, low
tCLK
tCLK
START pin rising edge to DRDY rising edge
4
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Pulse Control Mode (PULSE Bit = 1)
Settling Time Using START
In the Pulse Control mode, the ADS1259 performs a
single conversion when either the START pin is taken
high or when the START command is sent. As seen
in Figure 51, DRDY goes high when the conversion is
started. When the conversion is complete, DRDY
goes low and further conversions are halted. To start
a new conversion, transition the START pin back to
high, or transmit the START opcode again.
When START goes high (via pin or command) a
delay may be programmed before the conversion
filter cycle begins. The programmable delay may be
useful to provide time for external circuits (such as
after an external signal mux change), before the
reading is started. Register bits DELAY[2:0] set the
initial delay time as shown in Table 8.
Table 8. Initial START Delay
DELAY[2:0]
000
tDELAY (tCLK
)
tDELAY (µs)(1)
START Pin
0
0
OR
OR
001
64
8.68
17.4
34.7
69.4
139
010
128
START
START
011
256
Single
Conversion
Single
Conversion
Halted
Halted
100
512
101
1024
2048
4096
DRDY
110
278
111
556
(1) START opcode command takes effect on the seventh SCLK
falling edge.
(1) fCLK = 7.3728MHz.
Figure 51. Pulse Control Mode
After the programmable delay, the digital filter is reset
and a new conversion is started. DRDY goes low
when data are ready. There is no need to ignore or
discard data; the data are completely settled. The
total time to perform the first conversion is the sum of
the programmable delay time and the settling of the
digital filter. That is, the value of Table 8 and Table 9
combined. Figure 52 shows the timing and Table 9
shows the settling time with programmable delay
equal to '0'.
CONVERSION SETTLING TIME
The ADS1259 features a digital filter architecture in
which settling time can be traded for wide filter
notches, resulting in improved line-cycle rejection.
This trade-off is determined by the selection of the
sinc1 or sinc2 filter. The sinc1 filter settles in a single
cycle while the sinc2 filter provides wide-width filter
notches. The settling time of the ADS1259 is different
if START is used to begin conversions or if the
ADS1259 is free-running the conversions. These
modes are explained in the Settling Time Using
START and Settling Time While Continuously
Converting sections.
Table 9. Settling Time Using START
SETTLING TIME (tSET) (ms)(1)
DATA RATE
(SPS)
10
sinc1
100
sinc2
200
16.6
50
60.3
20.3
17.0
2.85
1.18
0.632
0.424
120
40.4
33.7
5.42
2.10
0.980
0.563
VIN = AINP - AINN
60
Settled VIN
400
START
Pin
1200
3600
14,400
7th Falling SCLK Edge of Opcode
or
START
Command
(1) fCLK = 7.3728MHz, DELAY[2:0] = 000.
(1)
tSET
DRDY
DOUT
Settled
Data
(1) tSET = initial start delay plus the new conversion cycle time.
Figure 52. Data Retrieval Time After START
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Settling Time While Continuously Converting
OFFSET AND GAIN
If there is a step change on the input signal while
continuously converting, the next data represent a
combination of the previous and current input signal
and should therefore be discarded; see Figure 53 for
this step change. Table 10 shows the number of
conversion cycles for completely settled data while
continuously converting.
The ADS1259 features low offset (40mV, typ) and low
gain errors (0.05%, typ). The offset and gain errors
can be corrected by sending calibration commands to
the ADS1259; see the Calibration section.
The ADS1259 also features very low offset drift
(0.05mV/°C, typ) and very low gain drift (0.5ppm/°C,
typ). The offset and gain drift are calculated using the
box method, as described by Equation 5 and
Equation 6:
Table 10. Settling Time While Continuously
Converting DRDY Periods(1)
V
OFFMAX - VOFFMIN
SETTLING TIME (tSET) (Conversions)
DATA RATE
(SPS)
Offset Drift =
sinc1
sinc2
Temp Range
(5)
10
16.6
50
2
2
2
2
2
2
3
6
3
3
3
3
3
3
4
7
GainErrorMAX - GainErrorMIN
Gain Drift =
Temp Range
60
where:
400
VOFFMAX, VOFFMIN, GainErrorMAX, and GainErrorMIN
are the maximum and minimum offset and gain
error readings recorded over the Temp Range
1200
3600
14,400
(–40°C to +105°C)
(6)
(1) Settling time is defined as the number of DRDY periods after
the input signal has settled following an input step change.
For best data throughput in multiplexed applications, issue a
START condition (START pin or Start command) after the
input has settled following a multiplexer change; see the
Setling Time Using START section.
tSET
New VIN
VIN = AINP - AINN
DRDY
Old VIN
Mix of
Old and New
VIN Data
Fully Settled
Old VIN Data
New VIN Data
Settled
Data
DOUT
Figure 53. Step Change on VIN while Continuously Converting
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Table 11. Offset Calibration Values
OFFSET AND FULL-SCALE CALIBRATION
REGISTERS
OFC REGISTER
7FFFFFh
FINAL OUTPUT CODE(1)
800001h
The conversion data are scaled by offset and gain
registers before yielding the final output code. As
shown in Figure 54, the output of the digital filter is
first subtracted by the offset register (OFC) and then
multiplied by the full-scale register (FSC). Equation 7
shows the scaling:
000001h
FFFFFFh
000000h
000000h
FFFFFFh
800001h
000001h
7FFFFFh
FSC[2:0]
Final Output Data = (Input - OFC[2:0]) ´
400000h
(1) Ideal output code excluding noise and inherent offset error.
FSC[2:0] Registers
(7)
The full-scale calibration is a 24-bit word, composed
of three 8-bit registers, as shown in Table 14. The
full-scale calibration value is 24-bit, straight binary,
normalized to 1.0 at code 400000h. Table 12
summarizes the scaling of the full-scale register. A
register value of 400000h (default value) has no gain
correction (gain = 1). Note that while the gain
calibration register value corrects gain errors above 1
(gain correction < 1), the full-scale range of the
analog inputs cannot exceed 105% full-scale to avoid
input overload.
The values of the offset and full-scale registers are
set by writing to them directly, or they are set by
calibration commands.
OFC[2:0] Registers
The offset calibration is a 24-bit word, composed of
three 8-bit registers, as shown in Table 13. The offset
is in twos complement format with a maximum
positive value of 7FFFFFh and a maximum negative
value of 800000h. This value is subtracted from the
conversion data. A register value of 00000h has no
offset correction (default value). Note that while the
offset calibration register value can correct offsets
ranging from –FS to +FS (as Table 11 shows), to
avoid input overload, the analog inputs cannot
exceed 105% full-scale.
Table 12. Full-Scale Calibration Register Values
FSC REGISTER
800000h
GAIN FACTOR
2.0
1.0
0.5
0
400000h
200000h
000000h
AINP
AINN
+
Output Data
Clipped to 24 Bits
Digital
Filter
´
Final Output
S
Modulator
-
OFC
Register
FSC Register
400000h
Figure 54. Calibration Block Diagram
Table 13. Offset Calibration Word
REGISTER
OFC0
BYTE
BIT ORDER
LSB
MID
MSB
B7
B15
B6
B5
B4
B3
B2
B1
B9
B0 (LSB)
OFC1
B14
B22
B13
B21
B12
B20
B11
B19
B10
B18
B8
OFC2
B23 (MSB)
B17
B16
Table 14. Full-Scale Calibration Word
REGISTER
FSC0
BYTE
LSB
BIT ORDER
B7
B15
B6
B5
B4
B3
B2
B1
B9
B0 (LSB)
B8
FSC1
MID
B14
B22
B13
B21
B12
B20
B11
B19
B10
B18
FSC2
MSB
B23 (MSB)
B17
B16
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CALIBRATION
The internal full-scale calibration word is bypassed
during offset calibration. Do not exceed +105% of
full-scale range for gain calibration. Note that the
out-of-range threshold is unaffected by gain
calibration.
The ADS1259 has commands to correct for system
offset and gain errors. Calibration can be performed
at any time the ADS1259 and associated circuitry
(such as the input amplifier, external reference, power
supplies, etc) have stabilized. Options include
calibrating after power-up, after temperature changes,
or calibration at regular intervals. To calibrate:
Table 15. Calibration Timing
tCAL CALIBRATION TIME (ms)
DATA RATE
(SPS)
14400
3600
1200
400
sinc1
1.89
5.43
14.9
43.2
284
sinc2
2.19
6.15
16.7
48.4
318
•
•
•
Set the gate control mode (PULSE bit = 0)
Start the ADS1259 conversions
Apply the appropriate input to the ADS1259 (zero
or full-scale)
Allow time for the input to completely settle
Send the OFSCAL (offset calibration) or GANCAL
(full-scale calibration) command, as appropriate
•
•
60
50
341
380
•
Wait for calibration to complete as given by the
time listed in
calibration is complete. The conversion result at
this time uses the new offset or full-scale
calibration words.
16.6
10
1020
1700
1140
1900
Table
15. DRDY goes low when
1. fCLK = 7.3728MHz.
Figure
55
DRDY
(DOUT with CS = 0)
shows the calibration timing. During
tCAL
calibration, do not send commands.
Calibration complete
and first data ready.
Perform offset calibration prior to the gain calibration.
CAL Command
DIN
Figure 55. Calibration Timing
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SERIAL INTERFACE
DATA INPUT (DIN)
The SPI-compatible serial interface consists of four
signals: CS, SCLK, DIN, and DOUT or three signals,
in which case CS may be tied low. The interface is
used to read conversion data, configure registers,
and control the ADS1259 operation.
DIN is the input data pin and is used with SCLK to
send data to the ADS1259 (opcode commands and
register data). The device latches input data on the
falling edge of SCLK.
DATA OUTPUT (DOUT)
SERIAL COMMUNICATION
DOUT is the output data pin and is used with SCLK
to read conversion and register data from the
ADS1259. In addition to providing data output, in
RDATAC mode DOUT indicates when data are
ready. Data are ready when DOUT transitions low. In
this manner, DOUT functions the same as DRDY
(with CS = 0), as shown in
data, the data are shifted out on the rising edge of
SCLK. DOUT is in a 3-state condition when CS is
high.
The ADS1259 communications occur by clocking
commands into the device (on DIN) and reading
register and conversion data (on DOUT). The SCLK
input is used to clock the data into and out of the
device. CS disables the ADS1259 serial port but
otherwise does not affect the ADC operation. The
communication protocol to the ADS1259 is
half-duplex. That is, data are transmitted to and from
the device one direction at a time.
Figure
56. When reading
Communications to and from the ADS1259 occurs on
8-bit boundaries. If an unintentional SCLK transition
should occur (such as from a possible noise spike),
the ADS1259 serial port may not respond properly.
The port can be reset by one of the following ways:
DATA READY (DRDY)
DRDY is an output that indicates when conversion
data are available for reading (falling edge active).
DRDY is asserted on an output pin and also a
register bit. To poll the DRDY register bit, set the stop
read data continuous mode and then read the
CONFIG2 register. When the DRDY bit is low, data
can be read. The data read operation must complete
within 20 fCLK cycles of the next DRDY falling edge.
After power-on or after reset, DRDY defaults high.
1. Take CS high and then low to reset the interface
2. Hold SCLK low for 216 fCLK cycles to reset the
interface
3. Take RESET/PWDN low and back high to overall
reset the device
4. Cycle the power supplies to overall reset the
device
When reading data in Gate Control mode, DRDY is
reset high on the first SCLK rising edge. If data are
not retrieved, DRDY pulses high during the new data
update time, as shown in Figure 56. Do not retrieve data
during this time as the data are invalid.
CHIP SELECT (CS)
The chip select (CS) selects the ADS1259 for SPI
communication. To select the device, pull CS low. CS
must remain low for the duration of the serial
communication. When CS is taken high, the serial
interface is reset, input commands are ignored, and
In Pulse Control mode, DRDY remains low until a
new conversion is started. The previous conversion
data may be read 20 tCLK prior to the DRDY falling
edge.
DOUT enters
a
high-impedance state. If the
ADS1259 does not share the serial bus with another
device, CS may be tied low. Note that DRDY remains
active when CS is high.
20 tCLK
Data Updating
DRDY Pin(1)(2)
SERIAL CLOCK (SCLK)
The serial clock (SCLK) is a Schmitt-triggered input
used to clock data into and out of the ADS1259. Even
though the input is relatively noise immune, it is
recommended to keep SCLK as clean as possible to
prevent glitches from accidentally shifting the data. If
SCLK is held low for 216 fCLK periods, the serial
interface resets. After reset the next communication
cycle can be started. The timeout can be used to
recover communication when the serial interface is
interrupted. The SPI timeout is enabled by register bit
SPI. When the serial interface is idle, hold SCLK low.
(1) DOUT functions in the same manner as the DRDY pin if CS is
low and in the RDATAC mode.
(2) The DRDY bit functions in the same manner as the DRDY pin
(SDATAC mode only).
Figure 56. DRDY and DOUT With No Data
Retrieval
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DATA FORMAT
DATA CHECKSUM BYTE AND FLAG BIT
The ADS1259 outputs 24 bits of conversion data in
binary twos complement format, MSB first. The data
LSB has a weight of VREF/(223 – 1). A positive
full-scale input produces an output code of 7FFFFFh
and the negative full-scale input produces an output
An optional checksum byte can be appended to the
conversion data bytes. The checksum makes the
data word length four bytes in length instead of three.
The checksum byte is enabled by the register bit
CHKSUM. The checksum itself is the least significant
byte sum of the three conversion data bytes, offset by
9Bh. Note that the checksum byte option only applies
to the readback conversion data, not to register data.
The checksum is either seven bits or eight bits,
depending if the FLAG register bit is enabled. If the
FLAG bit is enabled the checksum is seven bits, with
bit 7 replaced by the out-of-range flag. Figure 57 and
Table 17 describe the combinations of the FLAG and
CHKSUM register bits.
code of 800000h. The output clips at these codes for
Table 16
signals that exceed full-scale.
summarizes the
ideal output codes for different input signals.
Table 16. Ideal Output Code versus Input Signal
DIFFERENTIAL INPUT SIGNAL VIN
(AINP – AINN)
IDEAL OUTPUT
CODE(1)
≥ VREF
7FFFFFh
+VREF
Checksum = MSB data byte + Mid data byte + LSB
data byte + 9Bh.
000001h
(223 - 1)
0
000000h
FFFFFFh
32-Bit Conversion Data (CHKSUM = 1)
24-Bit Conversion Data (CHKSUM = 0)
-VREF
(223 - 1)
MSB
MID
LSB
CHECKSUM
Bit 7 of Checksum
223
223 - 1
Flag = 1; Bit 0 of LSB Conversion Data
800000h
£ -VREF
or
Figure 57. Checksum Byte and Out-of-Range Flag
(1) Excludes effects of noise, linearity, offset, and gain errors.
DATA INTEGRITY
Table 17. Checksum Byte and Over-Range Flag
Data readback integrity is augmented by a checksum
byte and redundant data read capability. The
checksum byte is the sum of three data conversion
bytes, offset by 9Bh. Additionally, the data conversion
bytes may be read multiple times by continuing to
shift data past the initial read of 24 bits (32 bits if
checksum is enabled).
FLAG
CHKSUM
REGISTER REGISTER
BIT
BIT
DESCRIPTION
No checksum byte, no out-of-range
flag
0
0
8-bit checksum byte, no
out-of-range flag
0
1
1
0
No checksum byte, out-of-range
flag replaces LSB (bit 0) of
conversion data
7-bit checksum byte, out-of-range
replaces MSB (bit 7) of checksum
byte.
1
1
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DATA RETRIEVAL
The Read Data Continuous mode is cancelled by
sending the Stop Read Data Continuous command
(SDATAC). This operation occurs simultaneously with
ADC conversion data on DOUT which can be
ignored. Once the SDATAC command is sent, other
commands may be sent to the ADS1259. Observe
the SCLK and DRDY timing requirements, when
reading data in this mode, as shown in Figure 58 and
Table 18.
New conversion data are available when DRDY goes
low. Read the data within 20 fCLK cycles of the next
DRDY falling edge or the data are incorrect. Do not
read data during this interval. The conversion data
may be read in two ways: Data Read in Continuous
mode and Data Read in Stop Continuous mode.
Data Read Operation in Continuous Mode
In Read Data Continuous mode the conversion data
may be shifted out directly without the need of the
data read command. When DRDY (and DOUT, if CS
is low) assert low, the conversion data are ready. The
data are shifted out on DOUT on the rising edges of
SCLK, with the most significant bit (MSB) clocked out
first. In Gate Convert Mode, DRDY returns to high on
the first falling edge of SCLK. In Pulse Convert mode,
DRDY remains low until a new conversion starts.
tDRSC
DRDY
SCLK
tSCDR
Figure 58. SCLK to DRDY Timing
As shown in Figure 59, the conversion data consist of
three or four bytes (data MSB first), depending on
whether the checksum byte is included. The data
may be read multiple times by continuing to shift the
data. The data read operation must be completed
with 20 fCLK cycles of next DRDY falling edge.
Table 18. SCLK and DRDY Timing Characteristics
for Figure 57
SYMBOL
DESCRIPTION
MIN
UNIT
(1)
tSCDR
SCLK low before DRDY
low(1)
20
tCLK
(1)
tDRSC
DRDY falling edge to SCLK
rising edge(1)
40
ns
(1) These requirements apply only to reading conversion data in
RDATAC mode.
Data Ready
Next Data Ready
DRDY(1)
CS(2)
1
9
17
25
33
(4)
tUPDATE
SCLK(3)
DOUT
DIN(8)
Hi-Z
CHECKSUM(6)
DATA MSB(7)
(5)
DATA MSB
DATA MID
DATA LSB
(1) In Gate Convert Conversion mode, DRDY returns to high on the first falling edge of SCLK. In Pulse Convert mode, DRDY remains low
until the next conversion is started.
(2) CS may be held low. If CS is low, DOUT asserts low with DRDY.
(3) Data are updated on the rising edge of SCLK. DOUT is low until the first rising edge of SCLK.
(4) tUPDATE = 20/fCLK. Do not read data during this time.
(5) During this interval, DOUT follows DRDY.
(6) Optional data checksum byte.
(7) Optional repeat of previous conversion data.
(8) Hold DIN low, except for transmission of the SDATAC (STOP Read Data Continuous command).
Figure 59. Data Read Operation in Continuous Mode
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Data Read Operation in Stop Continuous Mode
As shown in Figure 60, after sending the RDATA
command the data are shifted out on DOUT on the
rising edges of SCLK. The MSB is clocked out on the
first rising edge of SCLK. In Gate Control mode,
DRDY returns to high on the first falling edge of
SCLK. In Pulse Control mode, DRDY remains low
until a new conversion is started.
In Stop Read Data Continuous mode, a read data
command (RDATA) must be sent for each new data
read operation. New conversion data are ready when
DRDY falls low or the DRDY register bit transitions
low. The data read operation may then occur. The
read data command must be sent at least 20 fCLK
cycles before the DRDY falling edge or the data are
incorrect. Do not the read data command during this
time.
The conversion data consist of three or four bytes
(MSB first), depending on whether the checksum byte
is included. The data may be read multiple times by
continuing to shift the data.
Data Ready
Next Data Ready
DRDY(1)
(3)
tUPDATE
CS(2)
1
9
17
25
33
41
SCLK
DOUT
DIN(7)
Hi-Z
CHECKSUM(5)
DATA MSB(6)
(4)
DATA MSB
DATA MID
DATA LSB
012h(8)
(1) In Gate Control mode, DRDY returns to high on the first falling edge of SCLK. In Pulse Control mode, DRDY remains low until the next
conversion is started. The DRDY pin or DRDY register bit can also be polled to determine when data are ready.
(2) CS may be held low.
(3) tUPDATE = 20/fCLK. Do not issue the Read Data opcode during this time.
(4) During this interval, DOUT does not follow DRDY (stop continuous mode).
(5) Optional conversion data checksum.
(6) Optional repeat of previous conversion data.
(7) DIN data are latched on the falling edge of SCLK. Data are output on the rising edges of SCLK.
(8) Read Data command = 012h.
Figure 60. Data Read Operation in STOP Continuous Mode
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COMMAND DEFINITIONS
The commands summarized in Table 19 control and configure the operation of the ADS1259. The commands
are stand-alone, except for the register read and register write operations which require a second command byte
plus data. CS can be taken high or held low between opcode commands but must stay low for the entire
command operation. Note that the Read Data Continuous mode must be cancelled by the Stop Read Data
Continuous mode opcode (SDATAC) before sending further commands.
Table 19. Command Definitions(1)
COMMAND
WAKEUP
SLEEP
TYPE
Control
Control
Control
Control
Control
Control
Control
Data
DESCRIPTION
Wake up from SLEEP mode
Begin SLEEP mode
FIRST OPCODE BYTE
0000 001x (02h or 03h)(2)
0000 010x (04h or 05h)(2)
0000 011x (06h or 07h)(2)
0000 100x (08h or 09h)(2)
0000 101x (0Ah or 0Bh)(2)
0001 0000 (10h)
SECOND OPCODE BYTE
RESET
Reset to power-up values
START conversion
START
STOP
STOP conversion
RDATAC
SDATAC
RDATA
RREG
Set Read Data Continuous mode
Stop Read Data Continuous mode
Read data by opcode
0001 0001 (11h)
0001 001x (12h or 13h)(2)
0010 rrrr (20h + 0000 rrrr)
0100 rrrr (40h + 0000 rrrr)
0001 1000 (18h)
Register
Register
Calibration
Calibration
Read nnnn register at address rrrr
Write nnnn register at address rrrr
Offset calibration
0000 nnnn (00h + nnnn)
0000 nnnn (00h + nnnn)
WREG
OFSCAL
GANCAL
Gain calibration
0001 1001 (19h)
(1) nnnn = number of registers to be read/written – 1. For example, to read/write 3 registers, set nnnn = 2 (0010).
rrrr = starting register address for read/write opcodes.
(2) These commands are decoded on the seventh bit of the opcode. The eighth bit is a don't care bit. All other commands are decoded on
the eighth bit.
WAKEUP: Exit SLEEP Mode
Description: This command exits the low-power SLEEP mode; see the SLEEP Mode section.
SLEEP: Enter SLEEP Mode
Description: This command enters the low-power SLEEP mode. See the SLEEP Mode section.
RESET: Reset Registers to Default Values
Description: This command resets the digital filter cycle and returns all register settings to the default values.
START: Start Conversions
Description: This command starts data conversions. If PULSE bit = 1, then a single conversion is performed. If
PULSE bit = 0, then conversions continue until the STOP command is sent. Tie the START pin low to control
conversions by command.
STOP: Stop Conversions
Description: This command stops conversions. When the STOP command is sent, the conversion in progress
completes and further conversions are stopped. If conversions are already stopped, this command has no effect.
See the Conversion Control section. Tie the START pin low to control conversions by command.
RDATAC: Read Data Continuous
Description: This command enables the Read Data Continuous mode (default). See the Read Data Continuous
Mode section for details. Disable this mode with the SDATAC command before sending other commands.
SDATAC: Stop Read Data Continuous
Description: This command cancels the Read Data Continuous mode.
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RDATA: Read Data
Description: Issue this command opcode after DRDY goes low to read the conversion result (in Stop Read Data
Continuous mode). See the Read Data Mode section for more details.
RREG: Read from Registers
Description: These opcode bytes read register data. The Register Read command is a two-byte opcode
followed by the output of the register data. The first byte contains the command opcode and the register address.
The second byte of the opcode specifies the number of registers to read – 1.
First opcode byte: 0010 rrrr, where rrrr is the starting register address.
Second opcode byte: 0000 nnnn, where nnnn is the number of registers to read.
The 17th SCLK rising edge of the operation clocks out the MSB of the first register.
CS(1)
1
9
17
25
SCLK
DIN
OPCODE 1
OPCODE 2
REG DATA
REG DATA + 1
DOUT
(1) CS may be tied low.
Figure 61. RREG Command Example: Read Two Registers Starting from Register 00h (CONFIG0)
(OPCODE 1 = 0010 0000, OPCODE 2 = 0000 0001)
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WREG: Write to Register
Description: These two opcode bytes write register data. The Register Write command is a two-byte opcode
followed by the register data. The first byte contains the command opcode and the register address. The second
byte of the opcode specifies the number of registers to write – 1.
First opcode byte: 0100 rrrr, where rrrr is the starting register address.
Second opcode byte: 0000 nnnn, where nnnn is the number of registers to write
After the opcode bytes, the register data follows (in MSB-first format).
CS(1)
1
9
17
25
SCLK
DIN
OPCODE 1
OPCODE 2
REG DATA 1
REG DATA 2
DOUT
(1) CS may be tied low.
Figure 62. WREG Command Example: Write Two Registers Starting from 00h (CONFIG0)
(OPCODE 1 = 0100 0000, OPCODE 2 = 0000 0001)
OFSCAL: Offset Calibration
Description: This command performs an offset calibration. Apply a zero signal and allow the input to stabilize
before sending the command; see the Calibration section for more details.
GANCAL: Gain Calibration
Description: This command performs a gain calibration. Apply a full-scale signal and allow the input to stabilize
before sending the command; see the Calibration section for more details.
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REGISTER MAP
The operation of the ADS1259 is controlled through a set of registers. Collectively, the registers contain all the
information needed to configure the part, such as data rate, calibration, etc. Table 20 shows the register map.
Table 20. Register Map
RESET
ADDRESS
REGISTER
CONFIG0
CONFIG1
CONFIG2
OFC0
VALUE
BIT 7
1
BIT 6
0
BIT 5
ID1
BIT 4
ID0
BIT 3
0
BIT 2
RBIAS
DELAY2
DR2
BIT 1
0
BIT 0
SPI
0h
1h
2h
3h
4h
5h
6h
7h
8h
10XX0101b
00001000b
XX000000b
00000000b
00000000b
00000000b
00000000b
00000000b
01000000b
FLAG
DRDY
OFC07
OFC15
OFC23
FSC07
FSC15
FSC23
CHKSUM
EXTCLK
OFC06
OFC14
OFC22
FSC06
FSC14
FSC22
0
SINC2
PULSE
OFC04
OFC12
OFC20
FSC04
FSC12
FSC20
EXTREF
0
DELAY1
DR1
DELAY0
DR0
SYNCOUT
OFC05
OFC13
OFC21
FSC05
FSC13
FSC21
OFC03
OFC11
OFC19
FSC03
FSC11
FSC19
OFC02
OFC10
OFC18
FSC02
FSC10
FSC18
OFC01
OFC09
OFC17
FSC01
FSC09
FSC17
OFC00
OFC08
OFC16
FSC00
FSC08
FSC16
OFC1
OFC2
FSC0
FSC1
FSC2
CONFIG0: CONFIGURATION REGISTER 0 (Address = 0h)
7
1
6
0
5
4
3
2
1
0
0
ID1
ID0
0
RBIAS
SPI
Reset value = 10XX0101b.
Bit 7
Reserved (read-only)
Always returns '1'.
Bit 6
Reserved (read-only)
Always returns '0'.
Bits 5-4
Bit 3
ID[1:0]: Factory-programmed identification bits (read-only)
(Note that these bits may change without notification.)
Reserved
Always write '0'.
Bit 2
RBIAS: Internal reference bias
0 = Internal reference bias disabled
1 = Internal reference bias enabled (default)
Bit 1
Bit 0
Reserved
Always write '0'.
SPI: SCLK timeout of SPI interface
0 = SPI timeout disabled
1 = SPI timeout enabled (default), when SCLK is held low for 216 clock cycles
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CONFIG1: CONFIGURATION REGISTER 1 (Address = 1h)
7
6
5
4
3
2
1
0
FLAG
CHKSUM
0
SINC2
EXTREF
DELAY2
DELAY1
DELAY0
Reset value = 00001000b.
Bit 7
FLAG: Out-of-range flag
0 = Disabled (default)
1 = Enabled: replaces bit 24 (LSB) of the conversion data with the out-of-range bit; if the
CHKSUM byte is enabled, bit 7 of the checksum byte
Bit 6
CHKSUM: Checksum
0 = Disabled (default)
1 = Conversion data checksum byte included in readback
Bit 5
Bit 4
Reserved
Always write '0'.
SINC2: Digital filter mode
0 = sinc1 filter (default)
1 = sinc2 filter
Bit 3
EXTREF: Reference select
0 = Internal
1 = External (default)
Bits 2-0
DELAY[2:0]: START conversion delay
000 = No delay (default)
001 = 64 tCLK
010 = 128 tCLK
011 = 256 tCLK
100 = 512 tCLK
101 = 1024 tCLK
110 = 2048 tCLK
111 = 4096 tCLK
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CONFIG2: CONFIGURATION REGISTER 2 (Address = 2h)
7
6
5
4
3
2
1
0
DRDY
EXTCLK
SYNCOUT
PULSE
0
DR2
DR1
DR0
Reset value = XX000000b.
Bit 7
Bit 6
DRDY: Data ready (read-only)
This bit duplicates the state of the DRDY pin. Poll this bit to indicate that data are ready. When
DRDY is low, data are ready.
EXTCLK: Clock source (read-only)
0 = Device clock source is internal oscillator
1 = Device clock source is external clock
Note that the ADS1259 selects the clock source automatically.
Bit 5
Bit 4
SYNCOUT: SYNCOUT clock enable
0 = SYNCOUT disabled (default)
1 = SYNCOUT enabled
Note that if disabled, the output is driven low.
PULSE: Conversion Control mode select
0 = Gate Control mode (default)
1 = Pulse Control mode
Bit 3
Reserved
Always write '0'
Bits 2-0
DR[2:0] Data rate setting
000 = 10SPS (default)
001 = 16.6SPS
010 = 50SPS
011 = 60SPS
100 = 400SPS
101 = 1200SPS
110 = 3600SPS
111 = 14400SPS
NOTE: fCLK = 7.3728MHz
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OFC0: OFFSET CALIBRATION BYTE 0, LEAST SIGNIFICANT BYTE (Address = 3h)
7
6
5
4
3
2
1
0
OFC07
OFC06
OFC05
OFC04
OFC03
OFC02
OFC01
OFC00
Reset value = 00000000b.
OFC1: OFFSET CALIBRATION BYTE 1 (Address = 4h)
7
6
5
4
3
2
1
0
OFC15
OFC14
OFC13
OFC12
OFC11
OFC10
OFC09
OFC08
Reset value = 00000000b.
OFC2: OFFSET CALIBRATION BYTE 2, MOST SIGNIFICANT BYTE (Address = 5h)
7
6
5
4
3
2
1
0
OFC23
OFC22
OFC21
OFC20
OFC19
OFC18
OFC17
OFC16
Reset value = 00000000b.
FSC0: FULL-SCALE CALIBRATION BYTE 0, LEAST SIGNIFICANT BYTE (Address = 6h)
7
6
5
4
3
2
1
0
FSC07
FSC06
FSC05
FSC04
FSC03
FSC02
FSC01
FSC00
Reset value = 00000000b.
FSC1: FULL-SCALE CALIBRATION BYTE 1 (Address = 7h)
7
6
5
4
3
2
1
0
FSC15
FSC14
FSC13
FSC12
FSC11
FSC10
FSC09
FSC08
Reset value = 00000000b.
FSC2: FULL-SCALE CALIBRATION BYTE 2, MOST SIGNIFICANT BYTE (Address = 8h)
7
6
5
4
3
2
1
0
FSC23
FSC22
FSC21
FSC20
FSC19
FSC18
FSC17
FSC16
Reset value = 01000000b.
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BASIC CONNECTION
The ADS1259 basic connections are shown in Figure 63. The diagram shows the ADS1259 operating with an
internal oscillator and with internal reference. Dual ±2.5V analog power supplies are also shown. Pins 6-9 are the
SPI port connection. The remaining digital I/O pins connect to the controller I/O. Note that the minimum
configuration of the digital I/O may include only SCLK, DIN, and DOUT.
+2.5V
(1)
20W to 50W
ADS1259
1
2
20
19
18
17
16
15
14
13
12
11
1mF
(+)
AINP
AINN
AVDD
AVSS
-2.5V
Signal Input
10nF(2)
(-)
1mF
-
3
20W to 50W
VREFN
RESET/PWDN
START
SYNCOUT
CS
2.5V
Reference Output
1mF
Controller I/O
1mF
4
+
+
VREFP
4.7kW
+
5
Drives the PGA280
SYNCIN Pin
REFOUT
DVDD
6
1MW
+3.3V
1mF
7
SCLK
DGND
1mF
Controller SPI Port
8
+
DIN
BYPASS
XTAL2
9
DOUT
10
Controller I/O
XTAL1/CLKIN
DRDY
1MW
(1) It is recommended to buffer the ADS1259 inputs. The output isolation resistors may be incorporated within the amplifier feedback loop.
(2) Low distortion C0G or film capacitor recommended.
Figure 63. ADS1259 Basic Connection Diagram
LAYOUT
Place the input buffer and input decoupling capacitors close to the ADS1259 inputs. The bypass capacitors for
power-supply and reference decoupling should also be placed close to the device. In some cases, it may be
necessary to use a split ground plane in which digital return currents of external components are routed away
from the ADS1259. In this case, connect the grounds at the power supply.
CONFIGURATION GUIDE
Configuration of the ADS1259 involves configuring the device hardware (power supply, I/O pins, etc) and device
register settings. The registers are configured by commands sent via the device SPI port.
Power Supplies
The ADS1259 analog section operates either with a single +5V or dual ±2.5V supplies. The digital section
operates from +2.7V to +5V. The digital and analog power supplies may be tied together (+5V only).
Reference
Select either the internal reference or an external reference for the ADS1259 (see the Reference section). The
default is external reference. Figure 63 depicts the internal reference connection.
Clock
Choose the desired clock source (see the Clock Source section). Figure 63 depicts the internal clock operation.
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SYNCOUT Pin
Connect the SYNCOUT pin to the SYNCIN pin of the PGA280, using a 4.7kΩ series resistor (placed close to the
ADS1259). The 1MΩ pull-down resistor is required when the ADS1259 is in power-down mode.
RESET/PWDN Pin
This pin must be high in normal operation. If it is desired to completely power down the device, or to have a
hardware reset control, then connect this pin to a controller. If these functions are not needed, tie the pin high.
(Note that the device can both be reset and SLEEP mode engaged by commands.)
START Pin
If it is desired to control conversions by pin, connect this line to the controller. Otherwise, this line can be tied
high to free-run conversions. The conversions can also be controlled by software commands. In this case, tie the
START pin low.
DRDY Pin
DRDY is an output that indicates when data are ready for readback. Note that the DOUT pin (and also the DRDY
register bit) indicates when data are ready as well, so DRDY connection to a controller is optional.
CS Pin
If the ADS1259 is a single device connected to the SPI bus, then CS can be tied low. Otherwise, for applications
where the ADS1259 shares the bus with another device, CS must be connected.
DOUT Pin
When the ADS1259 SPI is deselected (CS = 1), the DOUT pin is in 3-state mode. A pull-down resistor may be
necessary to prevent floating the controller input pin.
Miscellaneous Digital I/O
Avoid ringing on the digital inputs and outputs. Resistors in series with the trace driving end helps to reduce
ringing by controlling impedances.
SOFTWARE GUIDE
After the power supplies have fully established, allow a minimum of 216 system clocks before beginning
communication to the device. The registers can then be configured by commands via the SPI port. The following
steps detail a suggested procedure to initialize the ADS1259.
1. Send the SDATAC command <11h>. This command cancels the RDATAC mode. RDATAC mode must be
cancelled before the register write commands.
2. Send the register write command. The following example shows the register write as a block of nine bytes,
starting at register 0 (CONFIG0).
BYTES
DATA
OPERATION
1, 2
3
01000000, 00001000
00000101
Write register opcode bytes, starting at address 0, 9-byte block
CONFIG0; register data, bias the reference, SPI timeout
4
01010000
CONFIG1; checksum enabled, sinc2 filter selection, internal
reference
5
00000011
CONFIG2; Gate Convert mode, 60SPS
6, 7, 8
00000000, 00000000,
00000000
OFC[2:0]; 3 bytes for offset, no offset correction
9, 10, 11
00000000, 00000000,
01000000
FSC[2:0]; 3 bytes for gain, no full-scale correction
40
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Product Folder Link(s): ADS1259
ADS1259
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SBAS424C –JUNE 2009–REVISED MARCH 2010
3. Optional readback verification of the register data
READ register command: <20h>, <08>
The nine bytes of readback data that follow represent the nine register bytes.
4. Take the START pin high or send the START command to start conversions.
5. Optionally, send the RDATAC command <10h>. This permits reading of conversion data without the need of
the read data command. Otherwise, the read data opcode must be sent to read each conversion result.
6. When the DRDY pin or the DRDY bit goes low, or when DOUT transitions low, read the data.
PGA280 APPLICATION
Figure 64 shows the ADS1259 connected to the PGA280. The PGA280 is a programmable gain, fully-differential
instrumentation amplifier that is ideally suited to drive the ADS1259. The amplifier features ±5V to ±18V supply
input section that accepts wide ranging signal levels and features a +5V output section that matches the
ADS1259 low-voltage inputs. The ADS1259 +2.5V REFOUT drives the PGA280 VOCM pin to level shift the
signal.
The ADS1259 provides a clock output (SYNCOUT) that drives the PGA280 (GPIO6) chopping clock input. An
optional extended CS (ECS) function feature of the PGA280 (GPIO0) allows use of one CS to alternately select
each device for SPI communication. Additionally, the optional BUFA trigger output of the PGA280 (GPIO5) starts
the ADS1259 conversions. The trigger can be delayed to occur after an input multiplexer change. The delay
allows settling of the PGA280 before the ADC conversion begins.
+5V
+15V(1) -15V(1)
1mF
+
4(1)
VSOP
20
17
VREFP VREFN
RESET/PWDN
18
1mF
6
11
VSN
VSP
AVDD
9
10
7
50W
VOP
2
1
16
2
3
INP1
INN1
INP2
INN2
Controller
AINP
10nF(3)
VOCM
VON
3
10
8
MUX
PGA
REFOUT
AINN
DRDY
DIN
50W
1mF
1
8
4.7kW(2)
18
19
24
5
9
GPIO6
GPIO5
GPIO0
SYNCOUT
START
DOUT
SCLK
SPI
4
7
PGA280
ADS1259
12
6
1MW
DGND
CS
+3.3V
17 15 14 16 13 5(1)
1mF
19 15 14 11 12 13
1mF
100kW
(1) Refer to the PGA280 product data sheet for power-supply bypassing recommendations.
(2) Locate this resistor as close as possible to pin 5 of the ADS1259.
(3) C0G or film capacitor.
Figure 64. PGA280 Driving the ADS1259
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ADS1259
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www.ti.com
REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (January 2010) to Revision C
Page
•
Changed ADS1259B and ADS1259 Internal Voltage Reference, Accuracy parameter in the Electrical
Characteristics ...................................................................................................................................................................... 3
Changed ADS1259 Internal Voltage Reference, Temperature drift parameter in the Electrical Characteristics ................. 3
Added Figure 23, ADS1259 internal reference voltage versus temperature graph ............................................................ 10
Added PGA280 Application section .................................................................................................................................... 41
•
•
•
Changes from Revision A (December 2009) to Revision B
Page
•
Updated description of out-of-range flag in Input Out-Of-Range Detection (FLAG) section .............................................. 14
42
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PACKAGE OPTION ADDENDUM
www.ti.com
17-Mar-2010
PACKAGING INFORMATION
Orderable Device
ADS1259BIPW
ADS1259BIPWR
ADS1259IPW
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
TSSOP
PW
20
20
20
20
70 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TSSOP
TSSOP
TSSOP
PW
PW
PW
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
70 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
ADS1259IPWR
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
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