ADS1282-SP [TI]
高分辨率模数转换器 (ADC);
| 型号： | ADS1282-SP |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 高分辨率模数转换器 (ADC) 转换器 模数转换器 |
| 文件： | 总62页 (文件大小：1630K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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ADS1282-SP
ZHCSES1B –MARCH 2016–REVISED OCTOBER 2018
ADS1282-SP 抗辐射加固保障高分辨率 Δ-Σ ADC
1 特性
2 应用
1
•
QMLV（QML V 类）MIL-PRF-38535 认证和抗辐
射加固保障 (RHA)，SMD 5962-14231
•
•
•
太空卫星温度和温度检测
太空卫星精密和科学 应用
高精度仪器
–
5962L1423101VXC - 符合军用级温度范围要求
（–55°C 至 125°C）
•
(1)
可提供工程评估 (/EM) 样片(1)
–
5962L1423102VXC - 符合缩减温度范围要求
（–55°C 至 115°C），提高动态性能
这些部件仅适用于工程评估。以非合规性流程对其进行了处理
（即未进行老化处理等操作）并且仅在 25°C 额定温度下进行
了测试。这些部件不适用于质检、生产、辐射测试或飞行。这
些零部件无法在 –55°C 至 125°C 的完整 MIL 额定温度范围或
运行寿命内保证其性能。
•
5962L14231：
–
–
–
抗辐射加固保障 (RHA) 高达 50kRAD (Si) 总电
离剂量 (TID)
3 说明
在 125°C 的环境温度下，单粒子锁定 (SEL) 对
于 LET 的抗扰度为 50MeV-cm2/mg
ADS1282-SP 是一款超高性能的抗辐射单芯片模数转
换器 (ADC)，具有集成式低噪声可编程增益放大器
(PGA) 和双通道输入多路复用器 (MUX)。ADS1282-
SP 具备超精密性能，适合要求较高的太空 应用 ；同
时能够保持较高的抗辐射性能，适用于各类卫星、有效
载荷及其他环境恶劣的 应用。
在 85°C 的环境温度下，单粒子锁定 (SEL) 对于
LET 的抗扰度为 60MeV-cm2/mg
•
•
高分辨率：124dB 信噪比 (SNR) (1000SPS)
高精度：总谐波失真 (THD)：–102dB
积分非线性 (INL)：0.5ppm
•
•
•
•
低噪声可编程增益放大器 (PGA)
双通道输入多路复用器 (MUX)
固有稳定性的调制器，支持快速响应超范围检测
灵活的数字滤波器：
器件信息(1)
器件型号
封装
封装尺寸（标称值）
ADS1282-SP
CFP (HKV) (28)
18.23mm x 12.70mm
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
–
正弦 + 有限脉冲响应 (FIR) + 无限脉冲响应
(IIR)（可选）
–
–
–
线性或最小相位响应
可编程的高通滤波器
可选择 FIR 数据速率：
250SPS 至 4kSPS
•
•
•
•
•
•
滤波器旁路选项
低功耗：25mW
偏移和增益校准引擎
SYNC 输入
模拟电源：单极 (5V) 或双极 (±2.5V)
数字电源：1.75V 至 3.3V
简化原理图
AVDD
VREFN VREFP
DVDD
CLK
ADS1282
SCLK
DOUT
DIN
Input 1
4th-Order
DS
Programmable
Digital Filter
SPI
PGA
Calibration
Interface
Input 2
Modulator
DRDY
VCOM
Over-Range
SYNC
RESET
PWDN
Control
Modulator Output
3
AVSS
DGND
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SBAS691
ADS1282-SP
ZHCSES1B –MARCH 2016–REVISED OCTOBER 2018
www.ti.com.cn
目录
8.2 Functional Block Diagram ....................................... 16
8.3 Feature Description................................................. 16
8.4 Device Functional Modes........................................ 35
8.5 Programming........................................................... 35
8.6 Register Maps......................................................... 40
Application and Implementation ........................ 45
9.1 Application Information............................................ 45
9.2 Typical Application ................................................. 45
1
2
3
4
5
6
7
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
（说明 （续））....................................................... 3
Pin Configuration and Functions......................... 4
Specifications......................................................... 5
7.1 Absolute Maximum Ratings ...................................... 5
7.2 ESD Ratings.............................................................. 5
7.3 Recommended Operating Conditions....................... 5
7.4 Thermal Information.................................................. 6
7.5 Electrical Characteristics........................................... 6
7.6 Timing Requirements................................................ 9
7.7 Pulse-Sync Timing Requirements............................. 9
7.8 Reset Timing Requirements ................................... 10
7.9 Read Data Timing Requirements............................ 10
7.10 Switching Characteristics...................................... 10
7.11 Typical Characteristics.......................................... 11
Detailed Description ............................................ 15
8.1 Overview ................................................................. 15
9
10 Power Supply Recommendations ..................... 51
11 Layout................................................................... 52
11.1 Layout Guidelines ................................................. 52
11.2 Layout Example .................................................... 53
12 器件和文档支持 ..................................................... 54
12.1 器件支持................................................................ 54
12.2 接收文档更新通知 ................................................. 57
12.3 社区资源................................................................ 57
12.4 商标....................................................................... 57
12.5 静电放电警告......................................................... 57
12.6 术语表 ................................................................... 57
13 机械、封装和可订购信息....................................... 57
8
4 修订历史记录
Changes from Revision A (December 2016) to Revision B
Page
•
•
•
•
•
将文档标题从：“ADS1282-SP 耐辐射...” 更改为“ADS1282-SP 抗辐射加固保障...” ............................................................... 1
在特性 中将“单粒子锁定 (SEL) 对于 LET 的抗扰度为 40...” 更改为“单粒子锁定 (SEL) 对于 LET 的抗扰度为 50...” ............. 1
在特性 中添加“单粒子锁定 (SEL) 对于 LET 的抗扰度为 60...” ............................................................................................... 1
已添加 工程评估样片列表项和脚注至应用 列表...................................................................................................................... 1
Changed the HKV Package appearance................................................................................................................................ 4
Changes from Original (March 2016) to Revision A
Page
•
•
•
•
•
已添加 5962L1423102VXC 缩减温度范围列表项至特性 部分................................................................................................ 1
Added ESD Ratings table to Specifications section............................................................................................................... 5
Added TJ values for 5962L1423102VXC to Recommended Operating Conditions table ...................................................... 5
Added MIN, TYP and MAX values for 5962L1423102VXC to Electrical Characteristics table.............................................. 6
已添加 接收文档更新通知 至器件和文档支持 部分............................................................................................................... 57
2
版权 © 2016–2018, Texas Instruments Incorporated
ADS1282-SP
www.ti.com.cn
ZHCSES1B –MARCH 2016–REVISED OCTOBER 2018
5 （说明 （续））
此转换器使用一个固有稳定性的四阶 Δ-Σ 调制器来获得出色的抗噪性能和线性度。该调制器可与片上数字滤波器搭
配使用，也可通过旁路与后处理滤波器结合使用。
输入 MUX 可灵活提供附加的外部输入用于测量以及内部自检连接。PGA 具有 出色的低噪声性能 (5nV/√Hz) 和高
输入阻抗，能够与较宽增益范围内的传感器轻松连接。
数字滤波器提供 250SPS 至 4000SPS 的可选数据速率。高通滤波器 (HPF) 具有 可调节的角频率。片上增益和偏
移调节寄存器支持系统校准。
同步输入 (SYNC) 可用于对多个 ADS1282 的转换操作进行同步。SYNC 输入还接受外部时钟源输入，用于对转换
操作进行持续校准。
放大器、调制器和滤波器三者的总功耗为 30mW。ADS1282-SP 在 –55°C 至 125°C 温度范围内完全额定运行。
Copyright © 2016–2018, Texas Instruments Incorporated
3
ADS1282-SP
ZHCSES1B –MARCH 2016–REVISED OCTOBER 2018
www.ti.com.cn
6 Pin Configuration and Functions
HKV Package
28-Pin CFP (HKV)
Top View
CLK
SCLK
DRDY
DOUT
DIN
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
BYPAS
DGND
DVDD
DGND
RESET
PWDN
VREFP
VREFN
AVSS
2
3
4
5
DGND
MCLK
M1
6
7
8
M0
9
SYNC
MFLAG
DGND
CAPN
CAPP
10
11
12
13
14
AVDD
AINN1
AINP1
AINN2
AINP2
Not to scale
Pin Functions
PIN
I/O
DESCRIPTION
NO.
1
NAME
CLK
Digital input
Master clock input
Serial clock input
2
SCLK
DRDY
DOUT
DIN
Digital input
Digital output
Digital output
Digital input
Digital ground
3
Data ready output: read data on falling edge
Serial data output
4
5
Serial data input
6, 12, 27, 25 DGND
Digital ground, pin 12 is the key ground point
"Modulator clock output; if in modulator mode:
MCLK: Modulator clock output
Otherwise, the pin is an unused input (must be tied)."
7
8
MCLK
M1
Digital I/O
Digital I/O
"Modulator data output 1; if in modulator mode:
M1: Modulator data output 1
Otherwise, the pin is an unused input (must be tied)."
"Modulator data output 0; if in modulator mode:
M0: Modulator data output 0
9
M0
Digital I/O
Otherwise, the pin is an unused input (must be tied)."
10
11
SYNC
MFLAG
Digital input
Digital output
Synchronize input
Modulator Over-Range flag:
0 = Normal
1 = Modulator over-range
13
14
CAPN
CAPP
Analog
Analog
PGA outputs: Connect 10-nF capacitor from CAPP to CAPN
PGA outputs: Connect 10-nF capacitor from CAPP to CAPN
4
Copyright © 2016–2018, Texas Instruments Incorporated
ADS1282-SP
www.ti.com.cn
ZHCSES1B –MARCH 2016–REVISED OCTOBER 2018
Pin Functions (continued)
PIN
I/O
DESCRIPTION
NO.
15
16
17
18
19
20
21
22
23
24
26
28
NAME
AINP2
Analog input
Analog input
Analog input
Analog input
Analog supply
Analog supply
Analog input
Analog input
Digital input
Digital input
Digital supply
Analog
Positive analog input 2
AINN2
AINP1
AINN1
AVDD
AVSS
Negative analog input 2
Positive analog input 1
Negative analog input 1
Positive analog power supply
Negative analog power supply
Negative reference input
Positive reference input
VREFN
VREFP
PWDN
RESET
DVDD
BYPAS
Power-down input, active low
Reset input, active low
Digital power supply: 1.8 V to 3.3 V
Sub-regulator output: Connect 1-μF capacitor to DGND
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature (unless otherwise noted)(1)
MIN
–0.3
–2.8
–0.3
MAX
UNIT
V
AVDD to AVSS
AVSS to DGND
DVDD to DGND
Input current
5.5
0.3
V
3.9
V
100, momentary
10, continuous
mA
mA
Input current
Analog input voltage (AINP1, AINN1, AINP2, AINN2, VREFN, VREFP,
CAPP, CAPN)
AVSS – 0.3
AVDD + 0.3
V
Digital input voltage to DGND (CLK, SCLK, DRDY, DOUT, DIN, MCLK,
M1, M0, MFLAG, SYNC, PWDN, RESET)
–0.3
–60
DVDD + 0.3
150
V
Storage temperature, Tstg
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings
VALUE
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±2000
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per JEDEC specification JESD22-
C101(2)
±1000
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
–55
–55
NOM
MAX
125
UNIT
5962L1423101VXC
5962L1423102VXC
TJ
Operating temperature
°C
115
Copyright © 2016–2018, Texas Instruments Incorporated
5
ADS1282-SP
ZHCSES1B –MARCH 2016–REVISED OCTOBER 2018
www.ti.com.cn
7.4 Thermal Information
ADS1282-SP
THERMAL METRIC(1)
HKV [CFP (TBAR)]
UNIT
28 PINS
64.4
16
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
58.6
13.3
50.5
5.3
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
ψJB
RθJC(bot)
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.5 Electrical Characteristics
AVDD = 2.5 V, AVSS = –2.5 V, ƒCLK(1) = 4.096 MHz, VREFP = 2.5 V, VREFN = –2.5 V, DVDD = 3.3 V, CAPN – CAPP = 10 nF, PGA = 1,
and ƒDATA = 1000 SPS, over operating temperature range, unless otherwise noted. Typical values are TJ = 25°C. A total ionizing dose of 50
kRad (Si) exposure at a low dose rate of < 10 mRads (Si)/s, post tested at 25°C.
5962L1423101VXC
TYP
5962L1423102VXC
MIN TYP MAX
PARAMETER
TEST CONDITIONS
UNIT
MIN
MAX
ANALOG INPUTS
Full-scale input
voltage
VIN = (AINP – AINN)
(VREFP – VREFN) / (PGA)
(VREFP – VREFN) / (PGA)
Vpp-diff
V
AINP or Absolute input
AVSS +
0.7
AVDD –
1.25
AVSS +
0.7
AVDD –
AINN
range
1.25
PGA input voltage
noise density
5
1
5
1
nV/√Hz
GΩ
Differential input
impedance(2)
Common-mode
input impedance
100
100
MΩ
Input bias current
Crosstalk
1
1
nA
dB
ƒ = 31.25 Hz
–128
–128
MUX on-
resistance
30
30
Ω
PGA OUTPUT (CAPP, CAPN)
Absolute output
range
AVSS +
0.4
AVSS +
0.4
AVDD –
0.4
AVDD – 0.4
V
PGA differential
output impedance
600
±10%
10
600
±10%
10
Ω
Output impedance
tolerance
External bypass
capacitance
100
100
nF
Modulator
differential input
impedance
55
55
kΩ
AC PERFORMANCE
Signal-to-noise
SNR
112
124
112
124
dB
ratio(3)
(1) ƒCLK = system clock.
(2) Input impedance is improved by disabling input chopping (CHOP bit = 0).
(3) VIN = 20 mVDC / PGA, see Table 1.
6
Copyright © 2016–2018, Texas Instruments Incorporated
ADS1282-SP
www.ti.com.cn
ZHCSES1B –MARCH 2016–REVISED OCTOBER 2018
Electrical Characteristics (continued)
AVDD = 2.5 V, AVSS = –2.5 V, ƒCLK(1) = 4.096 MHz, VREFP = 2.5 V, VREFN = –2.5 V, DVDD = 3.3 V, CAPN – CAPP = 10
nF, PGA = 1, and ƒDATA = 1000 SPS, over operating temperature range, unless otherwise noted. Typical values are TJ =
25°C. A total ionizing dose of 50 kRad (Si) exposure at a low dose rate of < 10 mRads (Si)/s, post tested at 25°C.
5962L1423101VXC
5962L1423102VXC
PARAMETER
TEST CONDITIONS
UNIT
MIN
TYP
–122
–117
–115
MAX
–99
MIN
TYP
–122
–117
–115
MAX
–101
–92
PGA = 1...16
PGA = 32
Total harmonic
distortion(4)
THD
–90
dB
dB
PGA = 64
Spurious-free
dynamic range
SFDR
123
123
DC PERFORMANCE
Resolution
No missing codes
FIR filter mode
31
250
31
250
bits
4000
128000
0.0090
4000
128000
0.0090
ƒDATA
Data rate
SPS
SINC filter mode
8000
8000
Integral
0.00005
50
0.00005
50
Differenti
%
nonlinearity
al input
FSR(6)
(INL)(5)
Offset error
0.0170
0.0170
200
750
200
750
Offset error after
calibration(7)
μV
Offset drift
Shorted
input
Gain error(8)
1
0.02
1
0.02
μV
Gain error after
calibration(7)
μV/°C
Gain drift
–1.5%
–1.0%
–0.5%
0.8%
–1.5%
–1.0%
–0.5%
0.8%
0.0002
%
Gain matching(9)
0.0002%
PGA = 1
2
9
2
9
Common-mode
rejection
ppm/°C
PGA = 16
0.3%
110
90
0.3%
110
90
ƒCM = 60 Hz(10)
82
80
82
80
dB
dB
AVDD,
AVSS
Post 50
ƒPS = 60
Power-supply
rejection
kRads (Si), TJ
Hz(10)
64
90
90
64
90
90
dB
dB
= 25°C(11)
DVDD
115
115
VOLTAGE REFERENCE INPUTS
(AVDD –
AVSS) +
0.2
Reference input
voltage
(VREF = VREFP –
VREFN)
(AVDD –
AVSS) + 0.2
0.5
5
0.5
5
V
Negative
reference input
AVSS –
0.1
VREFP –
0.5
AVSS –
0.1
VREFP –
0.5
VREFN
VREFP
V
V
Positive reference
input
VREFN
+ 0.5
VREFN +
0.5
AVDD +
0.1
AVDD + 0.1
±0.003
Reference input
impedance
85
85
kΩ
DIGITAL FILTER RESPONSE
Passband ripple
±0.003
dB
(4) VIN = 31.25 Hz, –0.5 dBFS.
(5) Best-fit method.
(6) FSR: Full-scale range = ±VREF / (2 × PGA).
(7) Calibration accuracy is on the level of noise reduced by 4 (calibration averages 16 readings).
(8) The PGA output impedance and the modulator input impedance results in –1% systematic gain error.
(9) Gain match relative to PGA = 1.
(10) ƒCM is the input common-mode frequency. ƒPS is the power-supply frequency.
(11) The maximum limit applies to SMD 5962L14231 post 50 kRads (Si) test at 25°C.
Copyright © 2016–2018, Texas Instruments Incorporated
7
ADS1282-SP
ZHCSES1B –MARCH 2016–REVISED OCTOBER 2018
www.ti.com.cn
Electrical Characteristics (continued)
AVDD = 2.5 V, AVSS = –2.5 V, ƒCLK(1) = 4.096 MHz, VREFP = 2.5 V, VREFN = –2.5 V, DVDD = 3.3 V, CAPN – CAPP = 10
nF, PGA = 1, and ƒDATA = 1000 SPS, over operating temperature range, unless otherwise noted. Typical values are TJ =
25°C. A total ionizing dose of 50 kRad (Si) exposure at a low dose rate of < 10 mRads (Si)/s, post tested at 25°C.
5962L1423101VXC
TYP
5962L1423102VXC
PARAMETER
TEST CONDITIONS
UNIT
MIN
MAX
MIN
TYP
MAX
Passband (–0.01
dB)
0.375 ×
ƒDATA
0.375 × ƒDATA
0.413 × ƒDATA
Hz
Hz
Hz
dB
Hz
s
Bandwidth (–3
dB)
0.413 ×
ƒDATA
High-pass filter
corner
0.1
10
0.1
10
Stop band
135
135
attenuation(12)
0.500 ×
ƒDATA
Stop band
0.500 × ƒDATA
5 / ƒDATA
5 /
ƒDATA
Minimum phase filter(13)
Settling time (latency)
Minimum phase filter
Linear phase filter
Group delay
31 /
ƒDATA
31 / ƒDATA
62 / ƒDATA
62 / ƒDATA
s
62 /
ƒDATA
s
62 /
ƒDATA
s
DIGITAL INPUT/OUTPUT
0.8 ×
DVDD
0.8 ×
DVDD
VIH
DVDD
DVDD
V
V
V
V
0.2 ×
DVDD
VIL
DGND
0.2 × DVDD
DGND
0.8 ×
DVDD
0.8 ×
DVDD
VOH
IOH = 1 mA
0.2 ×
DVDD
VOL
IOL = 1 mA
0.2 × DVDD
Input leakage
0 < VDIGITAL IN < DVDD
±10
4.096
±10
4.096
μA
ƒCLK
Clock input
1
1
MHz
MHz
ƒSCLK
Serial clock rate
ƒCLK / 2
ƒCLK / 2
POWER SUPPLY
AVSS
–2.6
0
–2.6
0
V
V
AVSS +
4.75
AVSS +
5.25
AVSS +
4.75
AVSS +
5.25
AVDD
DVDD
1.75
3.6
7.2
1.75
3.6
6.5
V
4.5
–200
–200
4.5
-200
-200
|mA|
High-
Post 50
resolution
kRads (Si), TJ
mode
11
200
5
11
200
5
|mA|
|μA|
= 25°C(11)
Power-
AVDD, AVSS
current
Post 50
down
kRads (Si), TJ
mode
|mA|
|μA|
= 25°C(11)
200
5
200
5
Standby
mode
Post 50
kRads (Si), TJ
|mA|
= 25°C(11)
(12) Input frequencies in the range of NƒCLK / 512 ± ƒDATA / 2 (N = 1, 2, 3...) can mix with the modulator chopping clock. In these frequency
ranges intermodulation = 120 dB, typ.
(13) At DC. See Figure 42.
8
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Electrical Characteristics (continued)
AVDD = 2.5 V, AVSS = –2.5 V, ƒCLK(1) = 4.096 MHz, VREFP = 2.5 V, VREFN = –2.5 V, DVDD = 3.3 V, CAPN – CAPP = 10
nF, PGA = 1, and ƒDATA = 1000 SPS, over operating temperature range, unless otherwise noted. Typical values are TJ =
25°C. A total ionizing dose of 50 kRad (Si) exposure at a low dose rate of < 10 mRads (Si)/s, post tested at 25°C.
5962L1423101VXC
5962L1423102VXC
PARAMETER
TEST CONDITIONS
UNIT
MIN
TYP
0.6
32
MAX
1.5
MIN
TYP
0.6
32
MAX
1.2
High-resolution mode
Power-down mode(14)
Standby mode
mA
μA
DVDD current
120
175
41
120
175
41
73
73
μA
25
25
mW
High-
Post 50
resolution
kRads (Si), TJ
mode
60
0.95
25.4
1.1
60
0.95
25.4
1.1
mW
mW
mW
mW
mW
= 25°C(11)
0.45
0.58
0.45
0.58
Power-
Post 50
Power dissipation down
mode
kRads (Si), TJ
= 25°C(11)
Standby
mode
Post 50
kRads (Si), TJ
25.4
25.4
= 25°C(11)
(14) CLK input stopped.
7.6 Timing Requirements
At TA = –55°C to 125°C and DVDD = 1.65 to 3.6 V, unless otherwise noted.
MIN
2
MAX
UNIT
tSCLK
tSPWH, L
tDIST
SCLK period
SCLK pulse width, high and low(1)
16
10
1 / ƒCLK
1 / ƒCLK
ns
0.8
50
50
DIN valid to SCLK rising edge: setup time
Valid DIN to SCLK rising edge: hold time
SCLK falling edge to valid new DOUT: propagation delay(2)
SCLK falling edge to DOUT invalid: hold time
tDIHD
ns
tDOPD
tDOHD
100
ns
0
ns
Final SCLK rising edge of command to first SCLK rising edge for register
read/write data
tSCDL
24
1 / ƒCLK
(1) Holding SCLK low for 64 DRDY falling edges resets the serial interface.
(2) Load on DOUT = 20 pF || 100 kΩ.
7.7 Pulse-Sync Timing Requirements
See Figure 46 and Figure 47 for timing diagrams.
MIN
1
MAX
Infinite
UNIT
n / ƒDATA
ns
tSYNC
SYNC period(1)
tCSHD
CLK to SYNC hold time to not latch on CLK edge
SYNC to CLK setup time to latch on CLK edge
SYNC pulse width, high or low
10
10
2
tSCSU
ns
tSPWH, L
1 / ƒCLK
Time for data ready (SINC filter)
Time for data ready (FIR filter)
See 器件支持, 表 21
62.98046875 / ƒDATA + 466 / ƒCLK
tDR
(1) Continuous-Sync mode; a free-running SYNC clock input without causing re-synchronization.
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7.8 Reset Timing Requirements
See Figure 48 for timing diagram.
MIN
MAX
UNIT
ns
tCRHD
tRCSU
tRST
CLK to RESET hold time
RESET to CLK setup time
RESET low
10
10
ns
2
1 / ƒCLK
s
tDR
Time for data ready
62.98046875 / ƒDATA + 468 / ƒCLK
7.9 Read Data Timing Requirements
MIN
MAX
100
1
UNIT
ns
tDDPD
tDR
DRDY to valid MSB on DOUT propagation delay (see Figure 54)(1)
Time for new data after data read command (see Figure 55)
0
ƒDATA
(1) Load on DOUT = 20 pF || 100 kΩ.
7.10 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Minimum phase filter
Linear phase filter
Minimum phase filter
Linear phase filter
5 / ƒDATA
31 / ƒDATA
62 / ƒDATA
62 / ƒDATA
s
s
s
s
Group delay(1)
Settling time
(latency)
(1) At DC. See Figure 42.
tSCDL
tSPWH
tSCLK
SCLK
DIN
tDIST
tSPWL
tSCDL
tDIHD
tDOHD
DOUT
tDOPD
Figure 1. Timing Diagram
10
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7.11 Typical Characteristics
At 25°C, AVDD = 2.5 V, AVSS = –2.5 V, ƒCLK = 4.096 MHz, VREFP = 2.5 V, VREFN = –2.5 V, DVDD = 3.3 V, CAPN – CAPP = 10 nF, PGA
= 1, and ƒDATA = 1000 SPS, unless otherwise noted.
0
-20
0
-20
8192-Point FFT
VIN = -0.5dBFS, 31.25Hz
8192-Point FFT
VIN = -20dBFS, 31.25Hz
PGA = 1
THD = -124.0dB
PGA = 1
THD = -120.1dB
-40
-40
-60
-60
-80
-80
-100
-120
-140
-160
-180
-100
-120
-140
-160
-180
0
0
0
50 100 150 200 250 300 350 400 450 500
Frequency (Hz)
0
50 100 150 200 250 300 350 400 450 500
Frequency (Hz)
Figure 2. Output Spectrum
Figure 3. Output Spectrum
0
-20
0
-20
8192-Point FFT
VIN = -0.5dBFS, 31.25Hz
8192-Point FFT
Shorted Input
SNR = 124.0dB
PGA = 16
THD = -122.4dB
-40
-40
-60
-60
-80
-80
-100
-120
-140
-160
-180
-100
-120
-140
-160
-180
50 100 150 200 250 300 350 400 450 500
Frequency (Hz)
0
50 100 150 200 250 300 350 400 450 500
Frequency (Hz)
Figure 4. Output Spectrum
Figure 5. Output Spectrum
0
-20
-100
-105
-110
-115
-120
-125
-130
THD Limited by
Signal Generator
8192-Point FFT
20mVDC
SNR = 124.2dB
-40
-60
PGA = 1
PGA = 8
-80
-100
-120
-140
-160
-180
VIN = –0.5 dBFS
50 100 150 200 250 300 350 400 450 500
Frequency (Hz)
10
20
30
40
50
60
70
80
90
100
Input Frequency (Hz)
Figure 6. Output Spectrum
Figure 7. THD vs Input Frequency
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Typical Characteristics (continued)
At 25°C, AVDD = 2.5 V, AVSS = –2.5 V, ƒCLK = 4.096 MHz, VREFP = 2.5 V, VREFN = –2.5 V, DVDD = 3.3 V, CAPN – CAPP
= 10 nF, PGA = 1, and ƒDATA = 1000 SPS, unless otherwise noted.
126
-100
-105
-110
-115
-120
-125
-130
125
124
123
122
121
120
119
118
117
-55
-35
-15
5
25
45
65
85
105
125
-55
-35
-15
5
25
45
65
85
105
125
Temperature (°C)
Temperature (°C)
Figure 8. SNR (1000 SPS) vs Temperature
Figure 9. THD (G = 8) vs Temperature
130
-110
-115
-120
-125
-130
PGA = 1
PGA = 8
125
120
115
110
105
100
PGA = 8
PGA = 1
0
1
2
3
4
5
5.5
0
1
2
3
4
5
6
VREF (V)
VREF (V)
Figure 10. SNR vs Reference Voltage
Figure 11. THD vs Reference Voltage
125
124
123
122
121
120
119
-110
-115
-120
-125
-130
PGA = 8
VIN = 31.25Hz, -0.5dBFS
Data Rate = fCLK/4096
VIN = 20mVDC
Data Rate = fCLK/4096
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
fCLK (MHz)
fCLK (MHz)
Figure 12. SNR vs Clock Frequency
Figure 13. THD vs Clock Frequency
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Typical Characteristics (continued)
At 25°C, AVDD = 2.5 V, AVSS = –2.5 V, ƒCLK = 4.096 MHz, VREFP = 2.5 V, VREFN = –2.5 V, DVDD = 3.3 V, CAPN – CAPP
= 10 nF, PGA = 1, and ƒDATA = 1000 SPS, unless otherwise noted.
130
120
110
100
90
140
120
100
80
DVDD
AVDD
AVSS
60
40
80
20
70
0
10
100
1k
10k
100k
1M
10
100
1k
10k
100k
1M
Input Frequency (Hz)
Power-Supply Frequency (Hz)
Figure 14. CMR vs Input Frequency
Figure 15. Power-Supply Rejection vs Frequency
4
3
2
1
0
30
20
10
0
PGA = 2
-1
PGA = 8
PGA = 32
-2
-3
-4
-10
-100 -75
-50
-25
0
25
50
75
100
-55 -35 -15
5 25 45 65 85 105 125
Temperature (°C)
Input Amplitude (% Full-Scale)
Figure 17. INL vs Temperature
Figure 16. INL vs Input Amplitude
35
0
Shorted Input
8192-Point FFT
Adjacent Channel VIN = -0.5dBFS, 31.25Hz
-20
30
25
20
15
10
-40
-60
-80
-100
-120
-140
-160
-180
0
50 100 150 200 250 300 350 400 450 500
Frequency (Hz)
-55
-25
5
35
65
95
125
Temperature (°C)
Figure 18. Crosstalk Output Spectrum
Figure 19. Power vs Temperature
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Typical Characteristics (continued)
At 25°C, AVDD = 2.5 V, AVSS = –2.5 V, ƒCLK = 4.096 MHz, VREFP = 2.5 V, VREFN = –2.5 V, DVDD = 3.3 V, CAPN – CAPP
= 10 nF, PGA = 1, and ƒDATA = 1000 SPS, unless otherwise noted.
30
25
20
15
10
5
30
25
20
15
10
5
25 Units
PGA = 8
PGA = 1
0
0
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
-100 -80 -60 -40 -20
0
20
40
60
80 100
fCLK (MHz)
Offset (mV)
Figure 20. Power vs Clock Frequency
Figure 21. Offset Histogram
90
80
70
60
50
40
30
20
10
0
10
8
25 Units Based on
25 Units
+20°C Intervals
Over the Range of
-40°C to +85°C
PGA = 8
6
4
2
PGA =1
0
-1.2 -1.1 -1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3
Gain Error (%)
Offset Drift (mV/°C)
Figure 22. Gain Error Histogram
Figure 23. Offset Drift Histogram
90
80
70
60
50
40
30
20
10
0
8
6
4
2
0
25 Units Based on +20°C Intervals
Over the Range of -40°C to +85°C
Worst-Case Gain Match Relative PGA = 1 (25 Units)
PGA = 1, 2, 4
PGA = 32
PGA = 8, 64
PGA = 16
Gain Drift (ppm/°C)
Gain Error (%)
Figure 24. Gain Drift Histogram
Figure 25. Gain Match Histogram
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8 Detailed Description
8.1 Overview
The ADS1282-SP is a high-performance analog-to-digital converter (ADC) intended for space satellite
temperature sensing, precision scientific and high accuracy applications. The converter provides 24- or 32-bit
output data in data rates from 250 SPS to 4000 SPS. The Functional Block Diagram shows the block diagram of
the ADS1282-SP.
The two-channel input MUX allows five configurations: Input 1; Input 2; Input 1 and Input 2 shorted together;
shorted with 400-Ω test; and common-mode test. The input MUX is followed by a continuous time PGA, featuring
very low noise of 5 nV/√Hz. The PGA is controlled by register settings, allowing gains of 1 to 64, in powers of 2.
The inherently-stable, fourth-order, delta-sigma modulator measures the differential input signal VIN = (AINP –
AINN) × PGA against the differential reference VREF = (VREFP – VREFN). A digital output (MFLAG) indicates
that the modulator is in overload as a result of an overdrive condition. The modulator output is available directly
on the MCLK, M0, and M1 output pins when in modulator mode. The modulator connects to an on-chip digital
filter that provides the output code readings.
The digital filter consists of a variable decimation rate, fifth-order sinc filter followed by a variable phase,
decimate-by-32, finite-impulse response (FIR) low-pass filter with programmable phase, and then by an
adjustable high-pass filter for DC removal of the output reading. The output of the digital filter can be taken from
the sinc, the FIR low-pass, or the infinite impulse response (IIR) high-pass sections as long as the maximum
clock rate of the SPI (fclk/2) is respected.
Gain and offset registers scale the digital filter output to produce the final code value. The scaling feature can be
used for calibration and sensor gain matching. The output data word is provided as either a 24-bit word or a full
32-bit word, allowing complete utilization of the inherently high resolution.
The SYNC input resets the operation of both the digital filter and the modulator, allowing synchronization
conversions of multiple ADS1282-SP devices to an external event. The SYNC input supports a continuously-
toggled input mode that accepts an external data frame clock locked to the conversion rate.
The RESET input resets the register settings and also restarts the conversion process. The PWDN input sets the
device into a micro-power state. The register settings are not retained in PWDN mode. Use the STANDBY
command in its place if it is desired to retain register settings (the quiescent current in the Standby mode is
slightly higher).
Noise-immune Schmitt-trigger and clock-qualified inputs (RESET and SYNC) provide increased reliability in high-
noise environments. The serial interface is used to read conversion data, in addition to reading from and writing
to the configuration registers.
The device features unipolar and bipolar analog power supplies (AVDD and AVSS, respectively) for input range
flexibility and a digital supply accepting 1.8 V to 3.3 V. The analog supplies may be set to 5 V to accept unipolar
signals (with input offset) or set lower in the range of ±2.5 V to accept true bipolar input signals (ground
referenced).
An internal sub-regulator is used to supply the digital core from DVDD. The BYPAS pin (pin 28) is the sub-
regulator output and requires a 1-μF capacitor for noise reduction. BYPAS should not be used to drive external
circuitry.
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8.2 Functional Block Diagram
AVDD
CLK
BYPAS DVDD
ADS1282
+1.8V
(Digital core)
Calibration
LDO
AINP2
AINN2
AINP1
DRDY
SCLK
DIN
300W
4th-Order
DS
Programmable
Digital Filter
Serial
Interface
PGA
300W
AINN1
Modulator
DOUT
400W
400W
Over-Range
Detection
SYNC
RESET
PWDN
Control
AVDD + AVSS
2
AVSS
MFLAG
DGND
MCLK M0
M1
8.3 Feature Description
8.3.1 Noise Performance
The ADS1282-SP device offers outstanding noise performance (SNR). SNR depends on the data rate, the PGA
setting, and the mode. As the bandwidth is reduced by decreasing the data rate, the SNR improves
correspondingly. Similarly, as the PGA gain is increased, the SNR decreases. Table 1 summarizes the noise
performance versus data rate, PGA setting, and mode.
8.3.2 Input-Referred Noise
The input-referred noise is related to SNR by Equation 1:
FSRRMS
SNR = 20log
NRMS
where:
•
•
FSRRMS = Full-scale range RMS = (VREFP – VREFN)/(2 × √2 × PGA)
NRMS = Noise RMS (input-referred)
(1)
8.3.3 Idle Tones
The ADS1282-SP modulator incorporates an internal dither signal that randomizes the idle tone energy. Low-
level idle tones may still be present, typically –137-dB less than full-scale. The low-level idle tones can be shifted
out of the passband with an external offset = 20 mV/PGA. See the Application Information section for the
recommended offset circuit.
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Feature Description (continued)
8.3.4 Operating Mode
The default mode is high-resolution.
Table 1. Signal-to-Noise Ratio (dB)(1)
PGA
8
DATA RATE (SPS)
1
2
4
16
32
64
250
500
130
127
124
121
118
130
127
124
121
118
129
126
123
120
117
128
125
122
119
116
125
122
119
116
113
119
116
113
111
108
114
111
108
106
103
1000
2000
4000
(1) VIN = 20 mVDC / PGA.
8.3.5 Analog Inputs and Multiplexer
Figure 26 shows a diagram of the input multiplexer.
ESD diodes protect the multiplexer inputs. If either input is taken less than AVSS – 0.3 V or greater than AVDD +
0.3 V, the ESD protection diodes may turn on. If these conditions are possible, external Schottky clamp diodes
and/or series resistors may be required to limit the input current to safe values (see the Absolute Maximum
Ratings).
Also, overdriving one unused input may affect the conversions of the other input. If overdriven inputs are
possible, TI recommends clamping the signal with external Schottky diodes.
AVDD
S1
AINP1
ESD Diodes
S2
AINP2
(+)
400W
S3
S7
AVSS
AVDD
To PGA
AVDD + AVSS
2
400W
S4
S5
S6
AINN1
AINN2
(-)
ESD Diodes
AVSS
Figure 26. Analog Inputs and Multiplexer
The specified input operating range of the PGA is shown in Equation 2:
AVSS + 0.7 V < (AINN or AINP) < AVDD – 1.25 V
(2)
Absolute input levels (input signal level and common-mode level) should be maintained within these limits for
best operation.
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The multiplexer connects one of the two external differential inputs to the preamplifier inputs, in addition to
internal connections for various self-test modes. Table 2 summarizes the multiplexer configurations for Figure 26.
Table 2. Multiplexer Modes
MUX[2:0]
000
SWITCHES
S1, S5
DESCRIPTION
AINP1 and AINN1 connected to preamplifier
001
S2, S6
AINP2 and AINN2 connected to preamplifier
010
S3, S4
Preamplifier inputs shorted together through 400Ω internal resistors
AINP1, AINN1 and AINP2, AINN2 connected together and to the preamplifier
External short, preamplifier inputs shorted to AINN2 (common-mode test)
011
S1, S5, S2, S6
S6, S7
100
The typical on-resistance (RON) of the multiplexer switch is 30 Ω. When the multiplexer is used to drive an
external load on one input by a signal generator on the other input, on-resistance and on-resistance amplitude
dependency can lead to measurement errors. Figure 27 shows THD versus load resistance and amplitude. THD
improves with high-impedance loads and with lower amplitude drive signals. The data are measured with the
circuit from Figure 28 with MUX[2:0] = 011.
0
PGA = 1
PGA = 2
PGA = 4
PGA = 8
-20
-40
PGA = 16
PGA = 32
PGA = 64
-60
-80
-100
-120
-140
0.1k
1k
10k
100k
1M
10M
RLOAD (W)
Figure 27. THD vs External Load and Signal Magnitude (PGA) (See Figure 28)
500W
500W
ADS1282
Input 1
RLOAD
Input 2
Figure 28. Driving an External Load Through the MUX
8.3.6 PGA (Programmable Gain Amplifier)
The PGA of the ADS1282-SP is a low-noise, continuous-time, differential-in/differential-out CMOS amplifier. The
gain is programmable from 1 to 64, set by register bits, PGA[2:0]. The PGA differentially drives the modulator
through 300-Ω internal resistors. A COG capacitor (10 nF typical) must be connected to CAPP and CAPN to filter
modulator sampling glitches. The external capacitor also serves as an anti-alias filter. The corner frequency is
given in Equation 3:
1
fP =
6.3 ´ 600 ´ C
(3)
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Referring to Figure 29, amplifiers A1 and A2 are chopped to remove the offset, offset drift, and the 1/f noise.
Chopping moves the effects to ƒCLK/128 (8 kHz), which is safely out of the passband. Chopping can be disabled
by setting the CHOP register bit = 0. With chopping disabled, the impedance of the PGA increases substantially
(>> 1 GΩ). As shown in Figure 30, chopping maintains flat noise density; if chopping is disabled, however, it
results in a rising 1/f noise profile.
The PGA has programmable gains from 1 to 64. Table 3 shows the register bit setting for the PGA and resulting
full-scale differential range.
The specified output operating range of the PGA is shown in Equation 4:
AVSS + 0.4 V < (CAPN or CAPP) < AVDD – 0.4 V
(4)
PGA output levels (signal plus common-mode) should be maintained within these limits for best operation.
Table 3. PGA Gain Settings
PGA[2:0]
000
GAIN
1
DIFFERENTIAL INPUT RANGE (V)(1)
±2.5
001
2
±1.25
010
4
±0.625
±0.312
±0.156
±0.078
±0.039
011
8
100
16
32
64
101
110
(1) VREF = VREFP – VREFN = 5 V
AVDD
MUX (+)
300W
A1
CAPP
CHOP
Gain Control
PGA[2:0] Bits
10nF
(55kW, typ(1)
)
Modulator
CAPN
Effective
300W
A2
Impedance
MUX (-)
Chopping Control CHOP Bit
AVSS
Figure 29. PGA Block Diagram
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100
PGA CHOP Off
PGA CHOP On
10
1
10
100
1k
Frequency (Hz)
Figure 30. PGA Noise
8.3.7 ADC
The ADC block of the ADS1282-SP is composed of two sections: a high-accuracy modulator and a
programmable digital filter.
8.3.8 Modulator
The high-performance modulator is an inherently-stable, fourth-order, ΔΣ, 2 + 2 pipelined structure, as Figure 31
shows. It shifts the quantization noise to a higher frequency (out of the passband) where digital filtering can
easily remove it. The modulator can be filtered either by the on-chip digital filter or by use of post-processing
filters.
fCLK/4
MCLK
M0
2nd-Order
DS
Analog Input (VIN
)
1st-Stage
2nd-Order
DS
M1
2nd-Stage
4th-Order Modulator
Figure 31. Fourth-Order Modulator
The modulator first stage converts the analog input voltage into a pulse-code modulated (PCM) stream. When
the level of differential analog input (AINP – AINN) is near one-half the level of the reference voltage 1/2 ×
(VREFP – VREFN), the ‘1’ density of the PCM data stream is at its highest. When the level of the differential
analog input is near zero, the PCM ‘0’ and ‘1’ densities are nearly equal. At the two extremes of the analog input
levels (+FS and –FS), the ‘1’ density of the PCM streams is approximately 90% and 10%, respectively.
The modulator second stage produces a '1' density data stream designed to cancel the quantization noise of the
first stage. The data streams of the two stages are then combined before the digital filter stage, as shown in
Equation 5.
Y[n] = 3M0[n – 2] – 6M0[n –3] + 4M0[n – 4] + 9(M1[n] – 2M1[n – 1] + M1[n – 2])
(5)
M0[n] represents the most recent first-stage output while M0[n – 1] is the previous first-stage output. When the
modulator output is enabled, the digital filter shuts down to save power.
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The modulator is optimized for input signals within a 4-kHz passband. As Figure 32 shows, the noise shaping of
the modulator results in a sharp increase in noise greater than 6 kHz. The modulator has a chopped input
structure that further reduces noise within the passband. The noise moves out of the passband and appears at
the chopping frequency (ƒCLK / 512 = 8 kHz). The component at 5.8 kHz is the tone frequency, shifted out of
band by an external 20 mV/PGA offset. The frequency of the tone is proportional to the applied DC input and is
given by PGA × VIN/0.003 (in kHz).
0
VIN = 20mVDC
-20
-40
-60
-80
-100
-120
-140
-160
-180
1
10
100
1k
10k
100k
Frequency (Hz)
1-Hz resolution
Figure 32. Modulator Output Spectrum
8.3.9 Modulator Over-Range
The ADS1282-SP modulator is inherently stable, and therefore, has predictable recovery behavior resulting from
an input overdrive condition. The modulator does not exhibit self-resetting behavior, which often results in an
unstable output data stream.
The ADS1282-SP modulator outputs a 1s density data stream at 90% duty cycle with the positive full-scale input
signal applied (10% duty cycle with the negative full-scale signal). If the input is overdriven past 90% modulation,
but less than 100% modulation (10% and 0% for negative overdrive, respectively), the modulator remains stable
and continues to output the 1s density data stream. The digital filter may or may not clip the output codes to +FS
or –FS, depending on the duration of the overdrive. When the input returns to the normal range from a long
duration overdrive (worst case), the modulator returns immediately to the normal range, but the group delay of
the digital filter delays the return of the conversion result to within the linear range (31 readings for linear phase
FIR). 31 additional readings (62 total) are required for completely settled data.
If the inputs are sufficiently overdriven to drive the modulator to full duty cycle, all 1s or all 0s, the modulator
enters a stable saturated state. The digital output code may clip to +FS or –FS, again depending on the duration.
A small duration overdrive may not always clip the output code. When the input returns to the normal range, the
modulator requires up to 12 modulator clock cycles (ƒMOD) to exit saturation and return to the linear region. The
digital filter requires an additional 62 conversions for fully settled data (linear phase FIR).
In the extreme case of over-range, either input is overdriven, exceeding the voltage of either analog supply
voltage plus an internal ESD diode drop. The internal diodes begin to conduct and the signal on the input is
clipped. When the input overdrive is removed, the diodes recover quickly. Keep in mind that the input current
must be limited to 100-mA peak or 10-mA continuous if an overvoltage condition is possible.
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8.3.10 Modulator Input Impedance
The modulator samples the buffered input voltage with an internal capacitor to perform conversions. The
charging of the input sampling capacitor draws a transient current from the PGA output. The average value of the
current can be used to calculate an effective input impedance of:
REFF = 1 / (ƒMOD × CS)
where
•
•
ƒMOD = Modulator sample frequency, Mode = CLK / 4
CS = Input sampling capacitor (17 pF, typ)
(6)
The resulting modulator input impedance for CLK = 4.096 MHz is 55 kΩ. The modulator input impedance and the
PGA output resistors result in a systematic gain error of –1%. CS can vary ±20% over production lots, affecting
the gain error.
8.3.11 Modulator Over-Range Detection (MFLAG)
The ADS1282-SP has a fast-responding over-range detection that indicates when the differential input exceeds
±100% full scale. The threshold tolerance is ±2.5%.The MFLAG output asserts high when in an over-range
condition. As Figure 33 and Figure 34 illustrate, the absolute differential input is compared to 100% of range. The
output of the comparator is sampled at the rate of ƒMOD / 2, yielding the MFLAG output. The minimum MFLAG
pulse width is ƒMOD / 2.
AINP
å
IABSI
P
100% FS
AINN
Q
MFLAG
Pin
fMOD/2
Figure 33. Modulator Over-Range Block Diagram
+100
(AINP - AINN)
0
Time
-100
MFLAG
Pin
Figure 34. Modulator Over-Range Flag Operation
8.3.12 Voltage Reference Inputs (VREFP, VREFN)
The voltage reference for the ADS1282-SP is the differential voltage between VREFP and VREFN: VREF
=
VREFP – VREFN. The reference inputs use a structure similar to that of the analog inputs with the circuitry of the
reference inputs shown in Figure 35. The average load presented by the switched capacitor reference input can
be modeled with an effective differential impedance of REFF = tSAMPLE / CIN (tSAMPLE = 1/ƒMOD). The effective
impedance of the reference inputs loads the external reference.
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AVDD
ESD
Diodes
VREFP
VREFN
REFF = 85 kΩ
11.5pF
(fMOD = 1.024 MHz)
ESD
Diodes
1
fMOD ´ CX
REFF
=
AVSS
Figure 35. Simplified Reference Input Circuit
The ADS1282-SP reference inputs are protected by ESD diodes. In order to prevent these diodes from turning
on, the voltage on either input must stay within the range shown in Equation 7:
AVSS – 300 mV < (VREFP or VREFN) < AVDD + 300 mV
(7)
The minimum valid input for VREFN is AVSS – 0.1 V and maximum valid input for VREFP is AVDD + 0.1 V.
A high-quality 5 V reference voltage is necessary for achieving the best performance from the ADS1282-SP.
Noise and drift on the reference degrade overall system performance, and it is critical that special care be given
to the circuitry generating the reference voltages in order to achieve full performance. See Application
Information for reference recommendations.
8.3.13 Digital Filter
The digital filter receives the modulator output and decimates the data stream. By adjusting the amount of
filtering, tradeoffs can be made between resolution and data rate: filter more for higher resolution, filter less for
higher data rate.
The digital filter is comprised of three cascaded filter stages: a variable-decimation, fifth-order sinc filter; a fixed-
decimation FIR, low-pass filter (LPF) with selectable phase; and a programmable, first-order, high-pass filter
(HPF), as shown in Figure 36.
The output can be taken from one of the three filter blocks, as Figure 36 shows. To implement the digital filter
completely off-chip, select the filter bypass setting (modulator output). For partial filtering by the ADS1282-SP,
select the sinc filter output. For complete on-chip filtering, activate both the sinc and FIR stages. The HPF can
then be included to remove DC and low frequencies from the data. Table 4 shows the filter options.
Table 4. Digital Filter Selection
FILTR[1:0] BITS
DIGITAL FILTERS SELECTED
Bypass; modulator output mode
Sinc
00
01
10
Sinc + FIR
Sinc + FIR + HPF
(low-pass and high-pass)
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8.3.13.1 Sinc Filter Stage (Sinx/X)
The sinc filter is a variable decimation rate, fifth-order, low-pass filter. Data are supplied to this section of the filter
from the modulator at the rate of ƒMOD (ƒCLK/4). The sinc filter attenuates the high-frequency noise of the
modulator, then decimates the data stream into parallel data. The decimation rate affects the overall data rate of
the converter; it is set by the DR[2:0] register bits, as shown in Table 5.
Equation 8 shows the scaled Z-domain transfer function of the sinc filter.
5
-N
1 - Z
-1
N(1 - Z )
H(Z) =
(8)
Table 5. Sinc Filter Data Rates (Clk = 4.096 MHz)
DR[2:0] REGISTER
DECIMATION RATIO (N)
SINC DATA RATE (SPS)
000
001
010
011
100
128
64
32
16
8
8000
16000
32000
64000
128000
Direct Modulator
Bit Stream
3
Filter Mode
(Register Select)
30
31
Filter
MUX
To Output Register
Sinc Filter
(Decimate by
8 to 128)
Coefficient Filter
(FIR)
(Decimate by 32)
High-Pass Filter
(IIR)
Code
Clip
CAL
Block
From Modulator
Figure 36. Digital Filter and Output Code Processing
Equation 9 shows the frequency domain transfer function of the sinc filter.
5
pN ´ f
sin
fMOD
½H(f)½ =
p ´ f
N sin
fMOD
where
•
N = Decimation ratio (see Table 5)
(9)
The sinc filter has notches (or zeroes) that occur at the output data rate and multiples thereof. At these
frequencies, the filter has zero gain. Figure 37 shows the frequency response of the sinc filter and Figure 38
shows the roll-off of the sinc filter.
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0
-20
-40
-60
-80
-100
-120
-140
0
1
2
3
4
5
Normalized Frequency (fIN/fDATA
)
Figure 37. Sinc Filter Frequency Response
0
-0.5
-1.0
-1.5
-2.0
-2.5
-3.0
0
0.05
0.10
0.15
0.20
Normalized Frequency (fIN/fDATA
)
Figure 38. Sinc Filter Roll-Off
8.3.13.2 FIR Stage
The second stage of the ADS1282-SP digital filter is an FIR low-pass filter. Data are supplied to this stage from
the sinc filter. The FIR stage is segmented into four sub-stages, as shown in Figure 39. The first two sub-stages
are half-band filters with decimation ratios of 2. The third sub-stage decimates by 4 and the fourth sub-stage
decimates by 2. The overall decimation of the FIR stage is 32. Two coefficient sets are used for the third and
fourth sections, depending on the phase selection. 表 20 (in 器件支持) lists the FIR stage coefficients. Table 6
lists the data rates and overall decimation ratio of the FIR stage.
Table 6. Fir Filter Data Rates
DR[2:0] REGISTER
DECIMATION RATIO (N)
FIR DATA RATE (SPS)
000
001
010
011
100
4096
2048
1024
512
250
500
1000
2000
4000
256
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FIR Stage 1
Decimate by 2
FIR Stage 2
Decimate by 2
FIR Stage 3
Decimate by 4
FIR Stage 4
Decimate by 2
Sinc
Filter
Output
Coefficients
Linear
Minimum
PHASE Select
Figure 39. Fir Filter Sub-Stages
As shown in Figure 40, the FIR frequency response provides a flat passband to 0.375 of the data rate (±0.003-
dB passband ripple). Figure 41 shows the transition from passband to stop band.
2.0
1.5
20
0
-20
1.0
-40
0.5
-60
0
-80
-0.5
-1.0
-1.5
-2.0
-100
-120
-140
-160
0
0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40
Normalized Input Frequency (fIN/fDATA
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
Normalized Input Frequency (fIN/fDATA
)
)
Figure 41. FIR Transition Band Magnitude Response
Figure 40. FIR Passband Magnitude Response (FDATA
500 Hz)
=
Although not shown in Figure 41, the passband response repeats at multiples of the modulator frequency
(NƒMOD – ƒ0 and NƒMOD + ƒ0, where N = 1, 2, and so forth, and ƒ0 = passband). These image frequencies, if
present in the signal and not externally filtered, fold back (or alias) into the passband and cause errors. A low-
pass signal filter reduces the effect of aliasing. Often, the RC low-pass filter provided by the PGA output resistors
and the external capacitor connected to CAPP and CAPN provides sufficient signal attenuation.
8.3.13.3 Group Delay and Step Response
The FIR block is implemented as a multi-stage FIR structure with selectable linear or minimum phase response.
The passband, transition band, and stop band responses of the filters are nearly identical but differ in the
respective phase responses.
8.3.13.3.1 Linear Phase Response
Linear phase filters exhibit constant delay time versus input frequency (that is, constant group delay). Linear
phase filters have the property that the time delay from any instant of the input signal to the same instant of the
output data is constant and is independent of the signal nature. This filter behavior results in essentially zero
phase error when analyzing multi-tone signals. However, the group delay and settling time of the linear phase
filter are somewhat larger than the minimum phase filter, as shown in Figure 42.
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1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
Minimum Phase Filter
Linear Phase Filter
-0.2
0
5
10 15 20 25 30 35 40 45 50 55 60 65
Time Index (1/fDATA
)
Figure 42. FIR Step Response
8.3.13.3.2 Minimum Phase Response
The minimum phase filter provides a short delay from the arrival of an input signal to the output, but the
relationship (phase) is not constant versus frequency, as shown in Figure 43. The filter phase is selected by the
PHS bit, as Table 7 shows.
35
Linear Phase Filter
30
25
20
15
10
Minimum Phase Filter
5
0
20
40
60
80 100 120 140 160 180 200
Frequency (Hz)
Figure 43. FIR Group Delay (FDATA = 500 Hz)
Table 7. Fir Phase Selection
PHS BIT
FILTER PHASE
0
1
Linear
Minimum
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8.3.13.4 HPF Stage
The last stage of the ADS1282-SP filter block is a first-order HPF implemented as an IIR structure. This filter
stage blocks DC signals and rolls off low-frequency components below the cut-off frequency. The transfer
function for the filter is shown in 公式 17 of the 器件支持.
The high-pass corner frequency is programmed by registers HPF[1:0], in hexadecimal. Equation 10 is used to set
the high-pass corner frequency. Table 8 lists example values for the high-pass filter.
cos wN + sin wN - 1
HPF[1:0] = 65,536 1 -
1 - 2
cos wN
where
•
•
•
•
HPF = High-pass filter register value (converted to hexadecimal)
ωN = 2πƒHP/ƒDATA (normalized frequency, radians)
ƒHP = High-pass corner frequency (Hz)
ƒDATA = Data rate (Hz)
(10)
Table 8. High-Pass Filter Value Examples
ƒHP (Hz)
DATA RATE (SPS)
HPF[1:0]
0337h
0.5
1
250
500
0337h
1
1000
019Ah
The HPF causes a small gain error, in which case the magnitude of the error depends on the ratio of ƒHP/ƒDATA
.
For many common values of (ƒHP/ƒDATA), the gain error is negligible. Figure 44 shows the gain error of the HPF.
The gain error factor is illustrated in 公式 16 (see 器件支持).
0
-0.10
-0.20
-0.30
-0.40
-0.50
0.0001
0.001
0.01
0.1
Frequency Ratio (fHP/fDATA
)
Figure 44. HPF Gain Error
Figure 45 shows the first-order amplitude and phase response of the HPF. In the case of applying step inputs or
synchronizing, the settling time of the filter should be taken into account.
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0
-7.5
90
75
60
45
30
15
-15.0
-22.5
-30.0
-37.5
-45.0
Amplitude
Phase
0
0.01
0.1
1
10
100
Normalized Frequency (f/fC)
Figure 45. HPF Amplitude and Phase Response
8.3.14 Master Clock Input (CLK)
The ADS1282-SP requires a clock input for operation. The clock is applied to the CLK pin. The data conversion
rate scales directly with the CLK frequency. Power consumption versus CLK frequency is relatively constant (see
the Typical Characteristics).
As with any high-speed data converter, a high-quality, low-jitter clock is essential for optimum performance.
Crystal clock oscillators are the recommended clock source. Make sure to avoid excess ringing on the clock
input; keep the clock trace as short as possible and use a 50-Ω series resistor close to the source.
8.3.15 Synchronization (SYNC Pin and Sync Command)
The ADS1282-SP can be synchronized to an external event, as well as synchronized to other ADS1282-SP
devices if the sync event is applied simultaneously.
The ADS1282-SP has two sources for synchronization: the SYNC input pin and the SYNC command. The
ADS1282-SP also has two synchronizing modes: Pulse-sync and Continuous-sync. In Pulse-sync mode, the
ADS1282-SP synchronizes to a single sync event. In Continuous-sync mode, either a single SYNC event is used
to synchronize conversions or a continuous clock is applied to the pin with a period equal to integer multiples of
the data rate. When the periods of the sync input and the DRDY output do not match, the ADS1282-SP re-
synchronizes and conversions are restarted.
8.3.16 Pulse-Sync Mode
In pulse-sync mode, the ADS1282-SP stops and restarts the conversion process when a sync event occurs (by
pin or command). When the sync event occurs, the device resets the internal memory; DRDY goes high (pulse
SYNC mode) otherwise in Continuous SYNC mode, DRDY continues to toggle, and after the digital filter has
settled, new conversion data are available, as shown in Figure 46 and Pulse-Sync Timing Requirements.
Resynchronization occurs on the next rising CLK edge after the rising edge of the SYNC pin or after the eighth
rising SCLK edge for opcode SYNC commands. To be effective, the SYNC opcode should be broadcast to all
devices simultaneously.
8.3.17 Continuous-Sync Mode
In Continuous-sync mode, either a single sync pulse or a continuous clock may be applied. When a single sync
pulse is applied (rising edge), the device behaves similar to the Pulse-sync mode. However, in this mode, DRDY
continues to toggle unaffected but the DOUT output is held low until data are ready, 63 DRDY periods later.
When the conversion data are non-zero, new conversion data are ready (as shown in Figure 46).
When a continuous clock is applied to the SYNC pin, the period must be an integral multiple of the output data
rate or the device re-synchronizes. Synchronization results in the restarting of the digital filter and an interruption
of 63 readings (refer to Pulse-Sync Timing Requirements).
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When the sync input is first applied, the device re-synchronizes (under the condition tSYNC ≠ N / ƒDATA). DRDY
continues to output but DOUT is held low until the new data are ready. Then, if SYNC is applied again and the
period matches an integral multiple of the output data rate, the device freely runs without re-synchronization. The
phase of the applied clock and output data rate (DRDY) are not matched because of the initial delay of DRDY
after SYNC is first applied. Figure 47 shows the timing for Continuous-Sync mode.
A SYNC clock input should be applied after the Continuous-Sync mode is set. The first rising edge of SYNC then
causes a synchronization.
tCSHD
System Clock
(fCLK)
tSCSU
SYNC Command
SYNC Pin
tSPWH
New Data
Ready
tSPWL
tDR
DRDY
(Pulse-Sync)
New Data
Ready
tDR
DRDY
(Continuous-Sync)
DOUT
Figure 46. Pulse-Sync Timing, Continuous-Sync Timing With Single Sync
tSCSU
tCSHD
System Clock
(fCLK)
tSPWL
tSPWH
SYNC
DRDY
tSYNC
1/fDATA
Figure 47. Continuous-Sync Timing With Sync Clock
8.3.18 Reset (RESET Pin and Reset Command)
The ADS1282-SP may be reset in two ways: toggle the RESET pin low or send a Reset command. When using
the RESET pin, take it low and hold for at least 2 / ƒCLK to force a reset. The ADS1282-SP is held in reset until
the pin is released. By command, RESET takes effect on the next rising edge of ƒCLK after the eighth rising edge
of SCLK of the command. To ensure the Reset command can function, the SPI interface may require resetting
itself; see Serial Interface.
In reset, registers are set to default and the conversions are synchronized on the next rising edge of CLK. New
conversion data are available, as shown in Figure 48 and Reset Timing Requirements.
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Settled
Data
DRDY
tDR
tCRHD
System Clock
(fCLK)
tRCSU
tRST
RESET Pin
or
RESET Command
Figure 48. Reset Timing
8.3.19 Power-Down (PWDN Pin and Standby Command)
There are two ways to power-down the ADS1282-SP: take the PWDN pin low or send a Standby command.
When the PWDN pin is pulled low, the internal circuitry is disabled to minimize power and the contents of the
register settings are reset.
In power-down, the device outputs remain active and the device inputs must not float. When the Standby
command is sent, the SPI port and the configuration registers are kept active. Figure 49 and Pulse-Sync Timing
Requirements show the timing.
PWDN Pin
Wakeup
Command
DRDY
tDR
Figure 49. PWDN Pin and Wake-Up Command Timing
(Pulse-Sync Timing Requirements Shows tDR
)
8.3.20 Power-On Sequence
The ADS1282-SP has three power supplies: AVDD, AVSS, and DVDD. Figure 50 shows the power-on sequence
of the ADS1282-SP. The power supplies can be sequenced in any order. The supplies [the difference of
(AVDD – AVSS) and DVDD] generate an internal reset whose outputs are summed to generate a global internal
reset. After the supplies have crossed the minimum thresholds, 216 ƒCLK cycles are counted before releasing the
internal reset. After the internal reset is released, new conversion data are available, as shown in Figure 50 and
Pulse-Sync Timing Requirements.
3.5V nom
AVDD - AVSS
1V nom
DVDD
CLK
16
2
fCLK
Internal Reset
DRDY
tDR
Figure 50. Power-On Sequence
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8.3.21 Serial Interface
A serial interface is used to read the conversion data and access the configuration registers. The interface
consists of three basic signals: SCLK, DIN, and DOUT. An additional output, DRDY, transitions low in Read Data
Continuous mode when data are ready for retrieval. Figure 51 shows the connection when multiple converters
are used.
FPGA or Processor
SCLK
SCLK
DOUT1
DOUT1
ADS1282
DIN2
DIN1
DRDY1
IRQ
SCLK
SCLK (optional)
DOUT2
DOUT2
ADS1282
DIN2
DIN2
DRDY2
IRQ (optional)
Figure 51. Interface for Multiple Devices
8.3.21.1 Serial Clock (SCLK)
The serial clock (SCLK) is an input that is used to clock data into (DIN) and out of (DOUT) the ADS1282-SP.
This input is a Schmitt-trigger input that has a high degree of noise immunity. However, TI recommends keeping
SCLK as clean as possible to prevent possible glitches from inadvertently shifting the data.
Data are shifted into DIN on the rising edge of SCLK and data are shifted out of DOUT on the falling edge of
SCLK. If SCLK is held low for 64 DRDY cycles, data transfer or commands in progress terminate and the SPI
interface resets. The next SCLK pulse starts a new communication cycle. This time-out feature can be used to
recover the interface when a transmission is interrupted or SCLK inadvertently glitches. SCLK should remain low
when not active.
8.3.21.2 Data Input (DIN)
The data input pin (DIN) is used to input register data and commands to the ADS1282-SP. Keep DIN low when
reading conversion data in the Read Data Continuous mode (except when issuing a STOP Read Data
Continuous command). Data on DIN are shifted into the converter on the rising edge of SCLK. In Pin mode, DIN
is not used.
8.3.21.3 Data Output (DOUT)
The data output pin (DOUT) is used to output data from the ADS1282-SP. Data are shifted out on DOUT on the
falling edge of SCLK.
8.3.21.4 Data Ready (DRDY)
DRDY is an output; when it transitions low, this transition indicates new conversion data are ready, as shown in
Figure 52. When reading data by the continuous mode, the data must be read within four CLK periods before
DRDY goes low again or the data are overwritten with new conversion data. When reading data by the command
mode, the read operation can overlap the occurrence of the next DRDY without data corruption.
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DRDY
DOUT
SCLK
Bit 31
Bit 30
Bit 29
Figure 52. DRDY With Data Retrieval
DRDY resets high on the first falling edge of SCLK. Figure 52 and Figure 53 show the function of DRDY with and
without data readback, respectively.
If data are not retrieved (no SCLK provided), DRDY pulses high for four ƒCLK periods during the update time, as
shown in Figure 53.
Data Updating
4/fCLK
DRDY
Figure 53. DRDY With No Data Retrieval
8.3.22 Data Format
The ADS1282-SP provides 32 bits of conversion data in binary twos complement format, as shown in Table 9.
The LSB of the data is a redundant sign bit: '0' for positive numbers and '1' for negative numbers. However,
when the output is clipped to +FS, the LSB = 1; when the output is clipped to –FS, the LSB = 0. If desired, the
data readback may be stopped at 24 bits. In sinc filter mode, the output data are scaled by 1/2.
Table 9. Ideal Output Code Versus Input Signal
INPUT SIGNAL VIN
(AINP – AINN)
32-BIT IDEAL OUTPUT CODE(1)
FIR FILTER
SINC FILTER(2)
VREF
(3)
>
7FFFFFFFh
2 x PGA
VREF
2 x PGA
7FFFFFFEh
3FFFFFFFh
VREF
2PGA ´ (230 - 1)
00000002h
00000000h
FFFFFFFFh
00000001h
00000000h
FFFFFFFFh
0
-VREF
2PGA ´ (230 - 1)
230
-VREF
´
80000001h
80000000h
C0000000h
230 - 1
2PGA
230
-VREF
(3)
<
´
230 - 1
2PGA
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(1) Excludes effects of noise, linearity, offset, and gain errors.
(2) Due to the reduction in oversampling ratio (OSR) related to the sinc filter high data rates, full 32-bit available resolution is reduced.
(3) In sinc filter mode, the output does not clip at half-scale code when the full-scale range is exceeded.
8.3.23 Reading Data
The ADS1282-SP has two ways to read conversion data: Read Data Continuous and Read Data By Command.
8.3.23.1 Read Data Continuous
In the Read Data Continuous mode, the conversion data are shifted out directly from the device without the need
for sending a read command. This mode is the default mode at power-on. This mode is also enabled by the
RDATAC command. When DRDY goes low, indicating that new data are available, the MSB of data appears on
DOUT, as shown in Figure 54. The data are normally read on the rising edge of SCLK, at the occurrence of the
first falling edge of SCLK, DRDY returns high. After 32 bits of data have been shifted out, further SCLK
transitions cause DOUT to go low. If desired, the read operation may be stopped at 24 bits. The data shift
operation must be completed within four CLK periods before DRDY falls again or the data may be corrupted.
When a Stop Read Data Continuous command is issued, the DRDY output is blocked but the ADS1282-SP
continues conversions. In stop continuous mode, the data can only be read by command.
8.3.23.2 Read Data by Command
The Read Data Continuous mode is stopped by the SDATAC command. In this mode, conversion data are read
by command. In the Read Data By Command mode, a read data command must be sent to the device for each
data conversion (as shown in Figure 55). When the read data command is received (on the eighth SCLK rising
edge), data are available to read only when DRDY goes low (tDR). When DRDY goes low, conversion data
appear on DOUT. The data may be read on the rising edge of SCLK.
DRDY
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 25 26 27 28 29 30 31 32
SCLK
DOUT
DIN
Data Byte 1 (MSB)
Data Byte 2 (MSB - 1)
Data Byte 4 (LSB)
tDDPD
Figure 54. Read Data Continuous
DRDY
tDR
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 33 34 35 36 37 38 39 40
SCLK
DOUT
DIN
Don't Care
Command Byte (0001 0010)
Data Byte 1 (MSB)
tDDPD
Date Byte 4 (LSB)
Figure 55. Read Data By Command, Rdata (TDDPD Timing Is Given In Read Data Timing Requirements)
8.3.24 One-Shot Operation
The ADS1282-SP can perform very power-efficient, one-shot conversions using the STANDBY command while
under software control. Figure 73 shows this sequence. First, issue the STANDBY command to set the Standby
mode.
When ready to make a measurement, issue the WAKEUP command. Monitor DRDY; when it goes low, the fully
settled conversion data are ready and may be read directly in Read Data Continuous mode. Afterwards, issue
another STANDBY command. When ready for the next measurement, repeat the cycle starting with another
WAKEUP command.
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8.4 Device Functional Modes
8.4.1 Modulator Output Mode
The modulator digital stream output is accessible directly, bypassing and disabling the internal digital filter. The
modulator output mode is activated by setting the CONFIG0 register bits FILTR[1:0] = 00. Pins M0 and M1 then
become the modulator data outputs and the MCLK becomes the modulator clock output. When not in the
modulator mode, these pins are inputs and must be tied.
The modulator output is composed of three signals: one output for the modulator clock (MCLK) and two outputs
for the modulator data (M0 and M1). The modulator clock output rate is ƒMOD (ƒCLK / 4). The SYNC input resets
the MCLK phase, as shown in Figure 56. The SYNC input is latched on the rising edge of CLK. The MCLK
resets and the next rising edge of MCLK occurs five CLK periods later.
The modulator output data are two bits wide, which must be merged together before being filtered. Use the time
domain equation of Equation 5 to merge the data outputs.
tCSHD
CLK
tCMD
tSCSU
SYNC
tSYMD
MCLK(1)
tMCD0, 1
M0
M1
(1) MCLK = ƒCLK / 4.
Figure 56. Modulator Mode Timing
Table 10. Modulator Output Timing for Figure 56
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tMCD0, 1
tCMD
MCLK rising edge to M0, M1 valid
propagation delay
100
ns
CLK rising edge (after SYNC rising
edge) to MCLK rising edge CMD
5
1/ƒCLK
ns
tCSHD
tSCSU
tSYMD
CLK to SYNC hold time to not latch
on CLK edge
10
10
SYNC to CLK setup time to latch on
CLK edge
ns
SYNC to stable bit stream
16 1/ƒMOD
8.5 Programming
8.5.1 Commands
The commands listed in Table 11 control the operation of the ADS1282-SP. Most commands are stand-alone
(that is, 1 byte in length); the register reads and writes require a second command byte in addition to the actual
data bytes.
A delay of 24 ƒCLK cycles between commands and between bytes within a command is required, starting from
the last SCLK rising edge of one command to the first SCLK rising edge of the following command. This delay is
shown in Figure 57.
In Read Data Continuous mode, the ADS1282-SP places conversion data on the DOUT pin as SCLK is applied.
As a consequence of the potential conflict of conversion data on DOUT and data placed on DOUT resulting from
a register or Read Data By Command operation, it is necessary to send a STOP Read Data Continuous
command before Register or Data Read By Command. The STOP Read Data Continuous command disables the
direct output of conversion data on the DOUT pin.
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Programming (continued)
Command
Byte
Command
Byte
DIN
SCLK
(1)
tSCLKDLY
(1) tSCLKDLY = 24/ƒCLK (min).
Figure 57. Consecutive Commands
Table 11. Command Descriptions
COMMAND
WAKEUP
STANDBY
SYNC
TYPE
Control
Control
Control
Control
Control
Control
Data
DESCRIPTION
Wake-up from Standby mode
Enter Standby mode
1st COMMAND BYTE(1)(2)
2nd COMMAND BYTE(3)
0000 000X (00h or 01h)
0000 001X (0 h or 03h)
0000 010X (04h or 5h)
0000 011X (06h or 07h)
0001 0000 (10h)
Synchronize the A/D conversion
Reset registers to default values
Read data continuous
RESET
RDATAC
SDATAC
RDATA
Stop read data continuous
Read data by command(4)
Read nnnnn register(s) at address rrrrr(4)
Write nnnnn register(s) at address rrrrr
Offset calibration
0001 0001 (11h)
0001 0010 (12h)
RREG
Register
Register
Calibration
Calibration
00r rrrr (20h + 000r rrrr)
010r rrrr (40h + 000r rrrr)
0110 0000 (60h)
000n nnnn (00h + n nnnn)
000n nnnn (00h + n nnnn)
WREG
OFSCAL
GANCAL
Gain calibration
0110 0001 (61h)
(1) X = Don't care.
(2) rrrrr = starting address for register read and write commands.
(3) nnnnn = number of registers to be read/written – 1. For example, to read/write three registers, set nnnnn = 2 (00010).
(4) Required to cancel Read Data Continuous mode before sending a command.
8.5.1.1 WAKEUP: Wake-Up from Standby Mode
This command is used to exit the standby mode. Upon sending the command, the time for the first data to be
ready is illustrated in Figure 49 and Table 9. Sending this command during normal operation has no effect; for
example, reading data by the Read Data Continuous method with DIN held low.
8.5.1.2 STANDBY: Standby Mode
This command places the ADS1282-SP into Standby mode. In Standby, the device enters a reduced power state
where a low quiescent current remains to keep the register settings and SPI interface active. For complete
device shutdown, take the PWDN pin low (register settings are not saved). To exit Standby mode, issue the
WAKEUP command. The operation of Standby mode is shown in Figure 58.
0000 001X
(STANDBY)
0000 000X
(WAKEUP)
DIN
SCLK
Operating
Standby Mode
Operating
Figure 58. Standby Command Sequence
8.5.1.3 SYNC: Synchronize the A/D Conversion
This command synchronizes the A/D conversion. Upon receipt of the command, the reading in progress is
cancelled and the conversion process is re-started. In order to synchronize multiple ADS1282-SPs, the command
must be sent simultaneously to all devices. The SYNC pin must be high for this command.
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8.5.1.4 RESET: Reset the Device
The RESET command resets the registers to default values, enables the Read Data Continuous mode, and
restarts the conversion process; the RESET command is functionally the same as the RESET pin. See Figure 48
for the RESET command timing.
8.5.1.5 RDATAC: Read Data Continuous
This command enables the Read Data Continuous mode (default mode). In this mode, conversion data can be
read from the device directly without the need to supply a data read command. Each time DRDY falls low, new
data are available to read. See Read Data Continuous for more details.
8.5.1.6 SDATAC: Stop Read Data Continuous
This command stops the Read Data Continuous mode. Exiting the Read Data Continuous mode is required
before sending Register and Data read commands. This command suppresses the DRDY output, but the
ADS1282-SP continues conversions.
8.5.1.7 RDATA: Read Data By Command
This command reads the conversion data. See Read Data by Command for more details.
8.5.1.8 RREG: Read Register Data
This command is used to read single or multiple register data. The command consists of a two-byte op-code
argument followed by the output of register data. The first byte of the op-code includes the starting address, and
the second byte specifies the number of registers to read – 1.
First command byte: 001r rrrr, where rrrrr is the starting address of the first register.
Second command byte: 000n nnnn, where nnnnn is the number of registers – 1 to read.
Starting with the 16th falling edge of SCLK, the register data appear on DOUT.
The RREG command is illustrated in Figure 59. The a delay of 24 ƒCLK cycles is required between each byte
transaction.
8.5.1.9 WREG: Write to Register
This command writes single or multiple register data. The command consists of a two-byte op-code argument
followed by the input of register data. The first byte of the op-code contains the starting address and the second
byte specifies the number of registers to write – 1.
First command byte: 001r rrrr, where rrrrr is the starting address of the first register.
Second command byte: 000n nnnn, where nnnnn is the number of registers – 1 to write.
Data byte(s): one or more register data bytes, depending on the number of registers specified.
Figure 60 illustrates the WREG command.
A delay of 24 ƒCLK cycles is required between each byte transaction.
8.5.1.10 OFSCAL: Offset Calibration
This command performs an offset calibration. The inputs to the converter (or the inputs to the external pre-
amplifier) should be zeroed and allowed to stabilize before sending this command. The offset calibration register
updates after this operation. See Calibration Commands for more details.
8.5.1.11 GANCAL: Gain Calibration
This command performs a gain calibration. The inputs to the converter should have a stable DC input, preferably
close to (but not exceeding) positive full-scale. The gain calibration register updates after this operation. See
Calibration Commands for more details.
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tDLY
tDLY
tDLY
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
SCLK
DIN
Command Byte 1
Command Byte 2
DOUT
Don't Care
Register Data 5
Register Data 6
Example: Read six registers, starting at register 05h (OFC0)
Command Byte 1 = 0010 0101
Command Byte 2 = 0000 0101
Figure 59. Read Register Data (Equation 11 Shows tDLY
)
tDLY
tDLY
tDLY
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
SCLK
DIN
Command Byte 1
Command Byte 2
Register Data 5
Register Data 6
Example: Write six registers, starting at register 05h (OFC0)
Command Byte 1 = 0100 0101
Command Byte 2 = 0000 0101
Figure 60. Write Register Data (Equation 11 Shows tDLY
)
tDLY = 24 / ƒCLK
(11)
8.5.2 Calibration Commands
Calibration commands may be sent to the ADS1282-SP to calibrate the conversion data. The values of the offset
and gain calibration registers are internally written to perform calibration. The appropriate input signals must be
applied to the ADS1282-SP inputs before sending the commands. Use slower data rates to achieve more
consistent calibration results; this effect is a byproduct of the lower noise that these data rates provide. Also, if
calibrating at power-on, be sure the reference voltage is fully settled.
Figure 61 shows the calibration command sequence. After the analog input voltage (and reference) have
stabilized, send the Stop Data Continuous command followed by the SYNC and Read Data Continuous
commands. 64 data periods later, DRDY goes low. After DRDY goes low, send the Stop Data Continuous, then
the Calibrate command followed by the Read Data Continuous command. After 16 data periods, calibration is
complete and conversion data may be read at this time. The SYNC input must remain high during the calibration
sequence.
The calibration commands apply to specific PGA settings. If the PGA is changed, recalibration is necessary.
Calibration is bypassed in the sinc filter mode.
8.5.2.1 OFSCAL Command
The OFSCAL command performs an offset calibration. Before sending the offset calibration command, a zero
input signal must be applied to the ADS1282-SP and the inputs allowed to stabilize. When the command is sent,
the ADS1282-SP averages 16 readings and then writes this value to the OFC register. The contents of the OFC
register may be subsequently read or written. During offset calibration, the full-scale correction is bypassed.
8.5.2.2 GANCAL Command
The GANCAL command performs a gain calibration. Before sending the GANCAL command, a DC input signal
must be applied that is in the range of, but not exceeding, positive or negative full-scale. After the signal has
stabilized, the command can be sent. The ADS1282-SP averages 16 readings, then computes the value that
compensates for the gain error. The gain correction value is then written to the FSC register. The contents of the
GANCAL register may be subsequently read or written. While the gain calibration command corrects for gain
errors greater than 1 (gain correction <1), to avoid input overload, the analog inputs cannot exceed full-scale
range. The gain calibration should be performed after the offset calibration.
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VIN
Fully stable input and reference voltage.
OFSCAL or
Commands
SDATAC
SYNC
RDATAC
SDATAC
RDATAC
GANCAL
Calibration
Complete
16 Data
Periods
DRDY
SYNC
64 Data Periods
Figure 61. Offset/Gain Calibration Timing
8.5.3 User Calibration
System calibration of the ADS1282-SP can be performed without using the calibration commands. This
procedure requires the calibration values to be externally calculated and then written to the calibration registers.
The steps for this procedure are:
1. Set the OFSCAL[2:0] register = 0h and GANCAL[2:0] = 400000h. These values set the offset and gain
registers to 0 and 1, respectively.
2. Apply a zero differential input to the input of the system. Wait for the system to settle and then average n
output readings. Higher numbers of averaged readings result in more consistent calibration. Write the
averaged value to the OFC register.
3. Apply a differential positive or negative DC signal, or an AC signal, less than the full-scale input to the
system. Wait for the system to settle and then average the n output readings.
The value written to the FSC registers is calculated by Equation 12.
DC signal calibration is shown in Equation 12. The expected output code is based on 31-bit output data.
Expected Output Code
FSC[2:0] = 400000h ´
Actual Output Code
(12)
For AC signal calibration, use an RMS value of collected data (as shown in Equation 13).
Expected RMS Value
FSC[2:0] = 400000h ´
Actual RMS Value
(13)
8.5.4 Configuration Guide
After RESET or power-on, the registers can be configured using the following procedure:
1. Reset the serial interface. Before using the serial interface, it may be necessary to recover the serial
interface (undefined I/O power-up sequencing may cause false SCLK detection). To reset the SPI interface,
toggle the RESET pin or, when in Read Data Continuous mode, hold SCLK low for 64 DRDY periods.
2. Configure the registers. The registers are configured by either writing to them individually or as a group.
Software may be configured in either mode. The SDATAC command must be sent before register read/write
operations to cancel the Read Data Continuous mode.
3. Verify register data. The register may be read back for verification of device communications.
4. Set the data mode. After register configuration, the device may be configured for Read Data Continuous
mode, either by the Read Data Continuous command or configured in Read Data By Register mode using
SDATAC command.
5. Synchronize readings. Whenever SYNC is high, the ADS1282-SP freely runs the data conversions. To stop
and re-sync the conversions, take SYNC low and then high.
6. Read data. If the Read Data Continuous mode is active, the data are read directly after DRDY falls by
applying SCLK pulses. If the Read Data Continuous mode is inactive, the data can only be read by Read
Data By Command. The Read Data opcode command must be sent in this mode to read each conversion
result (DRDY only asserts after each read data command is sent).
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8.6 Register Maps
8.6.1 ADS1282-SP Register Map Information
Collectively, the registers contain all the information needed to configure the part, such as data rate, filter
selection, calibration, and so forth. The registers are accessed by the RREG and WREG commands. The
registers can be accessed individually or as a block of registers by sending or receiving consecutive bytes. After
a register write operation the ADC resets, resulting in an interruption of 63 readings.
Table 12. ADS1282-SP Register Map
RESET
ADDRESS
00h
REGISTER
ID
VALUE
X0h
52h
08h
32h
03h
00h
00h
00h
00h
00h
40h
BIT 7
ID3
BIT 6
ID2
BIT 5
ID1
BIT 4
ID0
BIT 3
0
BIT 2
0
BIT 1
0
BIT 0
0
01h
CONFIG0
CONFIG1
HPF0
SYNC
0
MODE
MUX2
HPF06
HPF14
OFC06
OFC14
OFC22
FSC06
FSC14
FSC22
DR2
DR1
DR0
PHS
FILTR1
PGA1
HPF01
HPF09
OFC01
OFC09
OFC17
FSC01
FSC09
FSC17
FILTR0
PGA0
HPF00
HPF08
OFC00
OFC08
OFC16
FSC00
FSC08
FSC16
02h
MUX1
HPF05
HPF13
OFC05
OFC13
OFC21
FSC05
FSC13
FSC21
MUX0
HPF04
HPF12
OFC04
OFC12
OFC20
FSC04
FSC12
FSC20
CHOP
HPF03
HPF11
OFC03
OFC11
OFC19
FSC03
FSC11
FSC19
PGA2
HPF02
HPF10
OFC02
OFC10
OFC18
FSC02
FSC10
FSC18
03h
HPF07
HPF15
OFC07
OFC15
OFC23
FSC07
FSC15
FSC23
04h
HPF1
05h
OFC0
06h
OFC1
07h
OFC2
08h
FSC0
09h
FSC1
0Ah
FSC2
8.6.2 ID Register
Figure 62. ID: ID Register (Address 00h)
7
6
5
4
3
2
1
0
0
0
ID3
ID2
ID1
ID0
Reserved
0
0
Reset value = X0h
Table 13. ID Register Field Descriptions
Bit
7:4
3:0
Field
Type
Reset
Description
ID[3:0]
Reserved
Factory-programmed identification bits (read-only)
Always write '0'
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8.6.3 Configuration Registers
8.6.3.1 Configuration Register 0
Figure 63. CONFIG0: Configuration Register 0 (Address 01h)
7
6
5
4
3
2
1
0
SYNC
MODE
DR2
DR1
DR0
PHASE
FILTR1
FILTR0
Reset value = 52h
Table 14. Configuration Register 0 Field Descriptions
Bit
Field
Type
Reset
Description
7
SYNC
Synchronization mode
0: Pulse SYNC mode (default)
1: Continuous SYNC mode
6
MODE
1: High-resolution mode (default)
5:3
DR[2:0]
Data Rate Select(1)
000: 250SPS
001: 500SPS
010: 1000SPS (default)
011: 2000SPS
100: 4000SPS
2
PHASE
FIR Phase Response
0: Linear phase (default)
1: Minimum phase
1:0
FILTR[1:0]
Digital Filter Select
Digital filter configuration
00: On-chip filter bypassed, modulator output mode
01: Sinc filter block only
10: Sinc + LPF filter blocks (default)
11: Sinc + LPF + HPF filter blocks
(1) Sample rate based on 4.096-Mhz clock.
8.6.3.2 Configuration Register 1
Figure 64. CONFIG1: Configuration Register 1 (Address 02h)
7
6
5
4
3
2
1
0
RSVD
MUX2
MUX1
MUX0
CHOP
PGA2
PGA1
PGA0
0
Reset value = 08h
Table 15. Configuration Register 1 Field Descriptions
Bit
7
Field
Type
Reset
Description
Reserved
MUX[2:0]
Always write '0'
6:4
MUX Select
000: AINP1 and AINN1 (default)
001: AINP2 and AINN2
010: Internal short via 400Ω
011:AINP1 and AINN1 connected to AINP2 and AINN2
100: External short to AINN2
3
CHOP
PGA Chopping Enable
0: PGA chopping disabled
1: PGA chopping enabled (default)
2:0
PGA[2:0]
PGA Gain Select
000: G = 1 (default)
001: G = 2
010: G = 4
011: G = 8
100: G = 16
101: G = 32
110: G = 64
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8.6.4 HPF1 and HPF0
These two bytes (high-byte and low-byte, respectively) set the corner frequency of the high-pass filter.
8.6.4.1 High-Pass Filter Corner Frequency, Low Byte
Figure 65. HPF0: High-Pass Filter Corner Frequency, Low Byte (Address 03h)
7
6
5
4
3
2
1
0
HP07
HP06
HP05
HP04
HP03
HP02
HP01
HP00
Reset value = 32h
8.6.4.2 High-Pass Filter Corner Frequency, High Byte
Figure 66. HPF1: High-Pass Filter Corner Frequency, High Byte (Address 04h)
7
6
5
4
3
2
1
0
HP15
HP14
HP13
HP12
HP11
HP10
HP09
HP08
Reset value = 03h
8.6.5 OFC2, OFC1, OFC0
These three bytes set the offset calibration value.
8.6.5.1 Offset Calibration, Low Byte
Figure 67. OFC0: Offset Calibration, Low Byte (Address 05h)
7
6
5
4
3
2
1
0
OC07
OC06
OC05
OC04
OC03
OC02
OC01
OC00
Reset value = 00h
8.6.5.2 Offset Calibration, Mid Byte
Figure 68. OFC1: Offset Calibration, Mid Byte (Address 06h)
7
6
5
4
3
2
1
0
OC15
OC14
OC13
OC12
OC11
OC10
OC09
OC08
Reset value = 00h
8.6.5.3 Offset Calibration, High Byte
Figure 69. OFC2: Offset Calibration, High Byte (Address 07h)
7
6
5
4
3
2
1
0
OC23
OC22
OC21
OC20
OC19
OC18
OC17
OC16
Reset value = 00h
8.6.6 FSC2, FSC1, FSC0
These three bytes set the full-scale calibration value.
8.6.6.1 Full-Scale Calibration, Low Byte
Figure 70. FSC0: Full-Scale Calibration, Low Byte (Address 08h)
7
6
5
4
3
2
1
0
FSC07
FSC06
FSC05
FSC04
FSC03
FSC02
FSC01
FSC00
Reset value = 00h
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8.6.6.2 Full-Scale Calibration, Mid Byte
Figure 71. FSC1: Full-Scale Calibration, Mid Byte (Address 09h)
7
6
5
4
3
2
1
0
FSC15
FSC14
FSC13
FSC12
FSC11
FSC10
FSC09
FSC08
Reset value = 00h
8.6.6.3 Full-Scale Calibration, High Byte
Figure 72. FSC2: Full-Scale Calibration, High Byte (Address 0Ah)
7
6
5
4
3
2
1
0
FSC23
FSC22
FSC21
FSC20
FSC19
FSC18
FSC17
FSC16
Reset value = 40h
8.6.7 Offset and Full-Scale Calibration Registers
The conversion data can be scaled for offset and gain before yielding the final output code. As shown in
Figure 74, the output of the digital filter is first subtracted by the offset register (OFC) and then multiplied by the
full-scale register (FSC). Equation 14 shows the scaling:
FSC[2:0]
Final Output Data = (Input - OFC[2:0]) ´
400000h
(14)
The values of the offset and full-scale registers are set by writing to them directly, or they are set automatically
by calibration commands.
The offset and full-scale calibrations apply to specific PGA settings. When the PGA changes, the contents of
these registers may have to be recalculated. Calibration is bypassed in the sinc filter mode.
Standby
Performing One-Shot Conversion
Standby
ADS1282 Status
DRDY
(1)
WAKEUP
STANDBY
STANDBY
DIN
Settled
Data
DOUT
(1) See Figure 49 and Pulse-Sync Timing Requirements for time to new data.
Figure 73. One-Shot Conversions Using the Standby Command
AINP
AINN
+
Output Data
Clipped to 32 Bits
Digital
Filter
´
Final Output
S
Modulator
-
OFC
Register
FSC Register
400000h
Figure 74. Calibration Block Diagram
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8.6.7.1 OFC[2:0] Registers
The offset calibration is a 24-bit word, composed of three 8-bit registers, as shown in Table 18. The offset
register is left-justified to align with the 32-bits of conversion data. The offset is in twos complement format with a
maximum positive value of 7FFFFFh and a maximum negative value of 800000h. This value is subtracted from
the conversion data. A register value of 00000h has no offset correction (default value). While the offset
calibration register value can correct offsets ranging from –FS to +FS (as shown in Table 16), to avoid input
overload, the analog inputs cannot exceed the full-scale range.
Table 16. Offset Calibration Values
OFC REGISTER
7FFFFFh
FINAL OUTPUT CODE(1)
80000000h
000001h
FFFFFF00h
000000h
00000000h
FFFFFFh
800000h
00000100h
7FFFFF00h
(1) Full 32-bit final output code with zero code input.
8.6.7.2 FSC[2:0] Registers
The full-scale calibration is a 24-bit word, composed of three 8-bit registers, as shown in Table 19. The full-scale
calibration value is 24-bit, straight offset binary, normalized to 1 at code 400000h. Table 17 summarizes the
scaling of the full-scale register. A register value of 400000h (default value) has no gain correction (gain = 1).
While the gain calibration register value corrects gain errors greater than 1 (gain correction <1), the full-scale
range of the analog inputs cannot be exceeded to avoid input overload.
Table 17. Full-Scale Calibration Register Values
FSC REGISTER
800000h
GAIN CORRECTION
2
1
400000h
200000h
0.5
0
000000h
Table 18. Offset Calibration Word
REGISTER
OFC0
BYTE
LSB
BIT ORDER
7
15
6
5
4
3
2
1
9
0 (LSB)
OFC1
MID
14
22
13
21
12
20
11
19
10
18
8
OFC2
MSB
23 (MSB)
17
16
Table 19. Full-Scale Calibration Word
REGISTER
FSC0
BYTE
LSB
BIT ORDER
7
15
6
5
4
3
2
1
9
0 (LSB)
FSC1
MID
14
22
13
21
12
20
11
19
10
18
8
FSC2
MSB
23 (MSB)
17
16
44
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The ADS1282-SP is a high-resolution ΔΣ ADC with space grade qualification making it an ideal candidate for
space applications in temperature sensing, accelerometers, and precision instrumentation.
9.2 Typical Application
9.2.1 Thermocouple Temperature Sensing Application
Thermocouples are among the most commonly used sensors to measure temperature. Thermocouples work on
the principle that two dissimilar metals placed in contact will generate an output voltage as a function of
temperature as shown in Figure 75. This output voltage is proportional to the difference between the hot junction
temperature and the cold junction temperature by a scaling factor (α) known as the Seeback coefficient. To
ensure the measured output voltage accurately represents that generated by the hot junction the two junctions
from where Vout is measured should remain at the same (cold junction) reference temperature. Therefore, in
order to determine the temperature of the hot junction the thermocouple output voltage must be measured, the
cold junction temperature known, and the voltage versus temperature characteristics (Seeback coefficient) for the
type of thermocouple used be known.
Measuring (Hot) Junction
Reference (Cold) Junction
Metal A
Copper
Copper
+
+
VH
œ
VOUT
œ
Metal B
TH
TC
VOUT = . (TH œ TC)
Figure 75. Basic Thermocouple Configuration
The output voltage of the common type thermocouples is very repeatable and well documented by the American
National Institute of Standards (ANSI). Figure 76 shows the thermocouple output voltage versus temperature for
the most common types of thermocouples. As the graph illustrates, the output voltage is relatively small, less
than 90 mV across all types of thermocouples.
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Typical Application (continued)
90
80
70
60
50
40
30
20
10
0
Type B
Type E
Type J
Type K
Type N
Type R
Type S
Type T
-10
-20
-300
-100
100
300
500
700
900
1100
1300
1500
1700
1900
Temperature (°C)
D001
Figure 76. Thermocouple Voltage vs Temperature vs TC Type
9.2.1.1 Design Requirements
Since the output voltages of common thermocouple types are well documented, the accuracy of a thermocouple
measurement reduces to accurately measuring the output voltage of the thermocouple at the cold junction and
accurately determining the temperature at that cold junction. Once the cold junction temperature is determined,
the output voltage can be compensated to reflect the actual hot junction temperature. This compensation can be
implemented in hardware on the analog front-end or in software and/or firmware on the digital back-end, each of
which presents its own challenges. Analog compensation is challenging in that any components used in
compensation circuits are also potential sources of error while back-end digital compensation puts additional
processing requirements and algorithms on the FPGA or microprocessor. The premise of this application writing
is that cold junction compensation will be implemented in the digital domain so that minimal circuitry is used in
the analog domain. With this, the front-end design goal becomes effectively digitizing the thermocouple output
voltage as well as the cold junction temperature voltage.
The ADS1282-SP is ideal for achieving these goals as the device offers two analog inputs that are mux’d to one
delta-sigma modulator. Figure 77 illustrates how one input receives the thermocouple output voltage while the
second receives the cold junction compensation voltage. The Temp Sensor shown in the figure can take on
many forms such as a temp sensor IC, an RTD, or a thermistor.
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Typical Application (continued)
Board for Reference
Measuring (Hot) Junction
(Cold) Junction
TC
Metal A
Metal B
+
Temp.
Sensor
TH
VH
œ
TC
AINP2
AINN2
AINP1
AINN1
ADS1282-SP
Figure 77. ADS1282-SP as Thermocouple DAQ
The ADS1282-SP offers a very high dynamic range. To realize this dynamic range, however, the small
thermocouple voltage requires amplification to make use of the full scale range (FSR) of the ADC. The integrated
programmable gain amplifier (PGA) provides this amplification in factors of 1x to 64x (in powers of 2) making the
ADS1282-SP versatile for use with different types of thermocouples.
In addition to amplification, the analog input should be filtered. Filtering serves two purposes: first, to limit the
effect of aliasing during the sampling process and second, to reduce external noise from becoming a part of the
measurement. As with any sampled system, aliasing can occur if proper anti-alias filtering is not in place. Aliasing
occurs when frequency components are present in the input signal that are higher than half the sampling
frequency of the ADC (also known as the Nyquist frequency). These frequency components fold back and show
up in the actual frequency band of interest below half the sampling frequency. The filter response of the digital
filter repeats at multiples of the sampling frequency, also known as modulator frequency f(MOD), as shown in
Figure 78. Any frequency components present in the input signal around the modulator frequency or multiples
thereof are not attenuated and alias back into the band of interest, unless attenuated by an external analog filter.
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Typical Application (continued)
Magnitude
Sensor
Signal
Unwanted
Signals
Unwanted
Signals
Output
Data Rate
f(MOD)/2
f(MOD)
Frequency
Frequency
Frequency
Magnitude
Digital Filter
Aliasing of
Unwanted Signals
Output
Data Rate
f(MOD)/2
f(MOD)
Magnitude
External
Antialiasing Filter
Roll-Off
Output
f(MOD)/2
f(MOD)
Data Rate
Figure 78. Effect of Aliasing
Many sensor signals, such as the thermocouple, are inherently band-limited; the output has a limited rate of
change. In this case, the sensor signal does not alias back into the pass-band when using a ΔΣ ADC. However,
any noise pickup along the sensor wiring or the application circuitry can potentially alias into the pass band.
Power line-cycle frequency and harmonics are one common noise source. External noise can also be generated
from electromagnetic interference (EMI) or radio frequency interference (RFI) sources, such as nearby motors
and RF transceivers. Another noise source typically exists on the printed-circuit-board (PCB) itself in the form of
clocks and other digital signals. Analog input filtering helps remove unwanted signals from affecting the
measurement result. A first-order, resistor-capacitor (RC) filter is, in most cases, sufficient to either eliminate
such noise, or to reduce the effects to a level within the noise floor of the sensor.
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Typical Application (continued)
9.2.1.2 Detailed Design Procedure
Figure 79 below shows a typical thermocouple application utilizing both analog inputs to the ADS1282-SP; one
for hot junction and one for cold junction. The biasing resistors (RPU and RPD) serve two purposes. The first
purpose is to set the common-mode voltage of the thermocouple to within the specified voltage range of the
device. The second purpose is to offer a weak pullup and pulldown to detect an open thermocouple lead. When
one of the thermocouple leads fails open, the positive input is pulled to AVDD and the negative input is pulled to
GND. The ADC consequently reads a full-scale value that is outside the normal measurement range of the
thermocouple voltage to indicate this failure condition. When choosing the values of the biasing resistors, take
care so that the biasing current does not degrade measurement accuracy. The biasing current flows through the
thermocouple and can cause self-heating and additional voltage drops across the thermocouple leads. Typical
values for the biasing resistors range from 1 MΩ to 50 MΩ.
5 V
5 V
1 ꢁF
RPU
CCMA
RDIFFA
AINP1
AINN1
AVDD
CDIFF
RDIFFB
RPD
CCMB
CLK
DOUT
DIN
Digital Filter
and
Interface
PGA
Mux
ûꢀ ADC
DRDY
CCMA
RDIFFA
AINP2
AINN2
Temp.
Sensor
CDIFF
AVSS
RDIFFB
CCMB
Figure 79. ADS1282-SP with Hot and Cold Junction Sensing
Although the device digital filter attenuates high-frequency components of noise, provide a first-order, passive RC
filter at the inputs to further improve performance. The differential RC filter formed by RDIFFA, RDIFFB, and the
differential capacitor CDIFF offers a cutoff frequency that is calculated using Equation 15. Care must be taken
when choosing the filter resistor values because the input currents flowing into and out of the device cause a
voltage drop across the resistors. This voltage drop shows up as an additional offset error at the ADC inputs.
Limit the filter resistor values to below 1 kΩ for best performance.
fC = 1 / [2π × (RDIFFA + RDIFFB) × CDIFF]
(15)
Two common-mode filter capacitors (CCMA and CCMB) are also added to offer attenuation of high-frequency,
common-mode noise components. Differential capacitor CDIFF must be at least an order of magnitude (10x)
larger than these common-mode capacitors because mismatches in the common mode capacitors can convert
common-mode noise into differential noise.
The highest measurement resolution is achieved when the largest potential input signal is slightly lower than the
FSR of the ADC. For a type K thermocouple, the maximum thermocouple voltage (VTC) occurs at a
thermocouple temperature (TTC) of 1370°C. At this temperature, VTC = 54.819 mV, as defined in the tables
published by the National Institute of Standards and Technology (NIST) using a cold-junction temperature (TCJ)
of 0°C. A thermocouple produces an output voltage that is proportional to the temperature difference between the
thermocouple tip and the cold junction. If the cold junction is at a temperature below 0°C, the thermocouple
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Typical Application (continued)
produces a voltage larger than 54.819 mV. The isothermal block area is often constrained by the operating
temperature range of the device. Therefore, the isothermal block temperature is limited to –55°C. A K-type
thermocouple at TTC = 1370°C produces an output voltage of VTC = 54.819 mV – (–2.067 mV) = 56.886 mV
when referenced to a cold-junction temperature of TCJ = –55°C. When invoking the 64x amplification in the PGA
the device offers a full-scale range of 70.3 mVpp-diff (with a reference of 4.5 V) allowing for nearly full utilization
of the FSR with no additional external amplification required.
9.2.2 Digital Connection to a Field Programmable Gate Array (FPGA) Device Typical Application
Figure 80 shows the digital connection to a field programmable gate array (FPGA) device. In this example, two
ADS1282-SP devices are shown connected. The DRDY output from each ADS1282-SP device can be used;
however, when the devices are synchronized, the DRDY output from only one device is sufficient. A shared
SCLK line between the devices is optional.
4.096-MHz Clock
47 W
26
1
+3.3 V(1)
DVDD
CLK
ADS1282
1 mF
28
47 W
24
CLK Input
RESET
DOUT
DIN
RESET
DOUT1
DIN1
47 W
4
BYPAS
47 W
47 W
5
1 mF
47 W
47 W
2
SCLK
SYNC
MFLAG
SCLK1
SYNC
10
11
MFLAG1
DGND
6, 12, 25, 27
1
26
+3.3 V(1)
FPGA
DVDD
CLK
ADS1282
1 mF
24
RESET
47 W
28
4
DOUT2
DIN2
BYPAS
DOUT
DIN
5
1 mF
2
SCLK2
SCLK
SYNC
MFLAG
DRDY
47 W
10
47 W
11
3
MFLAG2
DRDY
47 W
DGND
6, 12, 25, 27
NOTE: Dashed line is optional.
(1) For DVDD < 2.25 V, see the Power Supply Recommendations.
Figure 80. Microcontroller Interface With Dual ADS1282-SPs
9.2.2.1 Design Requirements
It is critical to match the DVDD input and output thresholds of the ADS1282 to the IO voltage of the FPGA. The
FPGA outputs with correct VOH and VOL levels must be compatible with VIH/VIL levels of ADS1282 utilizing
respective DVDD voltage. Conversely the FPGA input thresholds must also be compatible with VOH/VOL levels
of DVDD range of ADS1282. The wide DVDD range of the ADS1282 allows easy interfacing to 1.8-V, 2.5-V, and
3.3-V logic levels. If DVDD is less than 2.25, then the BYPAS pin must be directly connected to DVDD to BYPAS
internal LDO.
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Typical Application (continued)
9.2.2.2 Detailed Design Procedure
The modulator over-range flag (MFLAG) from each device ties to the FPGA. For synchronization, one SYNC
control line connects all ADS1282-SP devices. The RESET line also connects to all ADS1282-SP devices.
For best performance, the FPGA and the ADS1282-SPs should operate from the same clock. Avoid ringing on
the digital inputs. 47-Ω resistors in series with the digital traces can help to reduce ringing by controlling
impedances. Place the resistors at the source (driver) end of the trace. Unused digital inputs should not float; use
pullups or pulldowns to DVDD or GND. This includes the modulator data pins, M0, M1, and MCLK.
Placement and layout of multiple ADS1282s should be done to allow digital and analog signals to be separated
and not cross to minimize coupling of noise from digital signals to analog signals and prevent ground loops.
FPGA firmware can monitor DRDY to initiate SPI transactions to obtain samples from both ADS1282s. Additional
monitoring of MFLAG can be done to take appropriate action if signal is overrange.
10 Power Supply Recommendations
Bypass all supply pins with 1-μF ceramic capacitors. In order to minimize the lead and trace inductance, place
the capacitors as close to the supply pins as possible. Where double-sided component mounting is allowed,
these capacitors are best placed directly under the package. In addition to power supplies, the device has a
reference supply at pins VREFP and VREFN that should also be bypassed. Bypass these pins with at least a 1-
μF capacitor as higher value capacitors yield superior low-frequency noise suppression. For best results, choose
low-inductance ceramic chip capacitors and place as close as possible to the device pins.
The DVDD power supply operates over the range of 1.75 to 3.6 V. If DVDD is operated at less than 2.25 V,
connect the DVDD pin to the BYPAS pin. If DVDD is greater than or equal to 2.25 V, do not connect DVDD to
the BYPAS pin. Figure 81 shows this connection.
1.75 V to 3.6 V
DVDD
ADS1282
Tie DVDD to BYPAS if
DVDD power is < 2.25 V.
Otherwise float BYPAS.
BYPAS
1 μF
Figure 81. DVDD Power
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11 Layout
11.1 Layout Guidelines
In any mixed-signal system design, the power-supply and grounding design plays a significant role. The device
distinguishes between two different grounds: AVSS (analog ground) and DGND (digital ground). In low frequency
applications such as temperature sensing with thermocouples, laying out the printed circuit board (PCB) to use a
single ground plane is adequate but care must be taken so that ground loops are avoided. Ground loops act as
loop antennas picking up interference currents which transform into voltage fluctuations. These fluctuations are
effectively noise which can degrade system performance in high resolution applications. When placing
components and routing over the ground plane, pay close attention to the path that ground currents will take.
Avoid having return currents for digital functions pass close to analog sensitive devices or traces.
Additionally, the proximity of digital devices to an analog signal chain has the potential to induce unwanted noise
into the system. One primary source of noise is the switching noise from any digital circuitry such as the data
output serializer or the microprocessor receiving the data. For the device, care must be taken to ensure that the
interaction between the analog and digital supplies within the device is kept to a minimal amount. The extent of
noise coupled and transmitted from the digital and analog sections depends on the effective inductances of each
of the supply and ground connections. Smaller effective inductances of the supply and ground pins results in
better noise suppression. For this reason, multiple pins are used to connect to the digital ground. Low inductance
properties must be maintained throughout the design of the PCB layout by use of proper planes and layer
thickness.
To avoid noise coupling through supply pins, TI recommends to keep sensitive input pins (such as AINN1,
AINP1, AINN2, AINP2 pins) away from the DVDD and DGND planes. For example, do not route the traces or
vias connected to these pins across these planes; that is, avoid the digital power planes under the analog input
pins. An exception may be acceptable to share DGND and AVSS when utilizing a unipolar supply for AVDD. As
in the example below, DGND is shared with AVSS. Care should be taken to minimize inductance and route
digital signals away from analog section.
The analog inputs represent the most sensitive node of the ADC as the total system accuracy depends on the
how well the integrity of this signal is maintained. The analog differential inputs to the ADC should be routed
tightly coupled and symmetrical for common mode rejection. These inputs should be as short in length as
possible to minimize exposure to potential sources of noise.
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11.2 Layout Example
1 µF
GND Pour
1 CLK
BYPAS 28
DGND 27
DVDD 26
DGND 25
RESET 24
PWDN 23
VREFP 22
VREFN 21
AVSS 20
AVDD 19
AINN1 18
AINP1 17
AINN2 16
AINP2 15
GND
DVDD
GND
2 SCLK
3 DRDY
4 DOUT
5 DIN
1 µF
Digital Signals
to Host
Microprocessor or
FPGA
GND
6 DGND
7 MCLK
8 M1
1 µF
GND
9 M0
1 µF
AVDD
10 SYNC
11 MFLAG
12 DGND
13 CAPN
14 CAPP
GND
Analog
Differential Input
Signals
1 µF
GND
GND
Figure 82. Unipolar Layout Example
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12 器件和文档支持
12.1 器件支持
表 20. FIR 级系数
第 1 部分
第 2 部分
第 3 部分
换算系数 = 134217728
线性相位 最小相位
–73 819
第 4 部分
换算系数 = 134217728
线性相位 最小相位
系数
换算系数 = 1 / 8388608
b0
b1
–10944
0
–774
–132
–432
11767
133882
0
–874
8211
44880
b2
103807
0
8994
–4648
–75
769961
b3
0
–16147
174712
2481
2940447
8262605
17902757
30428735
40215494
39260213
23325925
–1757787
–21028126
–21293602
–3886901
14396783
16314388
1518875
–12979500
–11506007
2769794
12195551
6103823
–6709466
–9882714
–353347
8629331
5597927
–4389168
–7594158
–428064
6566217
4024593
–3679749
–5572954
332589
b4
–507903
0
–51663
–41280
536821
6692
b5
0
199523
0
–80934
1372637
3012996
5788605
9852286
14957445
20301435
24569234
26260385
24247577
18356231
9668991
327749
7419
b6
2512192
4194304
2512192
0
–120064
–118690
–18203
–266
b7
–10663
–8280
b8
–629120
0
b9
224751
10620
b10
b11
b12
b13
b14
b15
b16
b17
b18
b19
b20
b21
b22
b23
b24
b25
b26
b27
b28
b29
b30
b31
b32
b33
b34
b35
b36
b37
b38
b39
b40
b41
–507903
0
2570188
4194304
2570188
0
580196
22008
893263
348
103807
0
891396
–34123
–25549
33460
293598
–10944
–629120
0
–987253
–2635779
–3860322
–3572512
–822573
4669054
12153698
19911100
25779390
27966862
61387
199523
0
–7546
–7171917
–10926627
–10379094
–6505618
–1333678
2972773
5006366
4566808
2505652
126331
–94192
–50629
101135
134826
–56626
–220104
–56082
263758
231231
–215231
–430178
34715
–51663
0
8994
0
–774
只显示一半；从
22 开始对称。
b
–1496514
–1933830
–1410695
–502731
245330
580424
283878
–588382
–693209
366118
1084786
132893
–1300087
–878642
1162189
1741565
–522533
–2490395
565174
492084
231656
–9196
5136333
2351253
–3357202
–3767666
1087392
3847821
919792
–125456
–122207
–61813
–4445
22484
22245
54
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ZHCSES1B –MARCH 2016–REVISED OCTOBER 2018
器件支持 (接下页)
表 20. FIR 级系数 (接下页)
第 1 部分
第 2 部分
第 3 部分
第 4 部分
系数
换算系数 = 134217728
换算系数 = 134217728
换算系数 = 1 / 8388608
线性相位
最小相位
线性相位
–688945
最小相位
–2918303
–2193542
1493873
2595051
–79991
–2260106
–963855
1482337
1480417
–586408
–1497356
–168417
1166800
644405
–675082
–806095
211391
740896
141976
–527673
–327618
278227
363809
–70646
–304819
–63159
205798
124363
–107173
–131357
31104
b42
b43
b44
b45
b46
b47
b48
b49
b50
b51
b52
b53
b54
b55
b56
b57
b58
b59
b60
b61
b62
b63
b64
b65
b66
b67
b68
b69
b70
b71
b72
b73
b74
b75
b76
b77
b78
b79
b80
b81
b82
b83
b84
b85
10775
940
2811738
–2953
–2599
–1052
-43
2425494
–2338095
–4511116
641555
214
6661730
132
2950811
33
–8538057
–10537298
9818477
41426374
56835776
只显示一半；从
b
53 开始对称。
107182
15644
–71728
–36319
38331
38783
–13557
–31453
–1230
20983
7729
–11463
–8791
版权 © 2016–2018, Texas Instruments Incorporated
55
ADS1282-SP
ZHCSES1B –MARCH 2016–REVISED OCTOBER 2018
www.ti.com.cn
器件支持 (接下页)
表 20. FIR 级系数 (接下页)
第 1 部分
第 2 部分
第 3 部分
第 4 部分
换算系数 = 134217728
线性相位 最小相位
系数
换算系数 = 134217728
换算系数 = 1 / 8388608
线性相位
最小相位
b86
b87
4659
7126
–732
–4687
–976
2551
1339
–1103
–1085
314
681
16
b88
b89
b90
b91
b92
b93
b94
b95
b96
b97
b98
–349
–96
144
78
b99
b100
b101
b102
b103
b104
b105
b106
b107
-46
–42
9
16
0
-4
cos wN + sin wN - 1
1 +
1 - 2
cos wN
HPF Gain =
cos wN + sin wN - 1
cos wN
2 -
(16)
有关该公式的使用示例，请参见HPF Stage。
12.1.1 HPF 传递函数
-1
2 - a
1 - Z
HPF(Z) =
´
-1
2
1 - bZ
(17)
(18)
其中，b 的计算公式如公式 18 所示：
(1 + (1 - a)2)2
b =
2
56
版权 © 2016–2018, Texas Instruments Incorporated
ADS1282-SP
www.ti.com.cn
ZHCSES1B –MARCH 2016–REVISED OCTOBER 2018
表 21. 数据就绪时间 tDR（正弦滤波器）
(1)
ƒDATA
128k
64k
ƒCLK
440
616
32k
968
16k
1672
2824
8k
(1) 对于同时有同步命令和唤醒命令的情况，ƒCLK = 从第八个 SCLK 上升
沿后紧接着的下一个 CLK 上升沿到 DRDY 下降沿的 CLK 周期数。对
于仅有唤醒命令的情况，减去两个 ƒCLK 周期。
表 21 被Pulse-Sync Timing Requirements引用。
12.2 接收文档更新通知
要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我进行注册，即可每周接收产
品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
12.3 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
12.4 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
12.6 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、缩写和定义。
13 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。
版权 © 2016–2018, Texas Instruments Incorporated
57
PACKAGE OPTION ADDENDUM
www.ti.com
15-Jul-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
5962L1423101VXC
5962L1423102VXC
ADS1282HKV/EM
ACTIVE
CFP
CFP
CFP
HKV
28
28
28
1
RoHS & Green
RoHS & Green
RoHS & Green
AU
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
-55 to 125
-55 to 115
25 to 25
5962L1423101VXC
ADS1282-SP
Samples
Samples
Samples
ACTIVE
ACTIVE
HKV
1
AU
AU
5962L1423102VXC
ADS1282-SP
HKV
1
ADS1282HKV/EM
EVAL ONLY
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
15-Jul-2023
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF ADS1282-SP :
Catalog : ADS1282
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
TUBE
*All dimensions are nominal
Device
Package Name Package Type
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
5962L1423101VXC
5962L1423102VXC
ADS1282HKV/EM
HKV
HKV
HKV
CFP (TBAR)
CFP (TBAR)
CFP (TBAR)
28
28
28
1
1
1
506.98
506.98
506.98
26.16
26.16
26.16
6220
6220
6220
NA
NA
NA
Pack Materials-Page 1
PACKAGE OUTLINE
HKV0028A
CFP - 2.85 mm max height
S
C
A
L
E
0
.
7
0
0
CERAMIC DUAL FLATPACK
12.9
12.5
9.40
6.35
B
TYP
A
PIN 1 ID
26X 1.27
28
1
18.49
18.08
2X
16.51
(10.795)
14
15
0.53
0.38
0.2
28X
(9.017)
C A
C
B
0.23
0.10
28X
2.85 MAX
9.86
9.45
0.66 MIN
4X 0.25 MIN
4221846/A 01/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This package is hermetically sealed with a metal lid.
4. The terminals are gold plated.
5. Falls within MIL-STD-1835 CDFP-F11A.
www.ti.com
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相关型号：
ADS1282HIPWR
Ultra-high-resolution 4-kSPS 2-channel delta-sigma ADC with PGA for seismic and energy exploration 28-TSSOP -40 to 85
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