ADS1292I_技术文档

ADS1291

ADS1292

ADS1292R

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SBAS502A –DECEMBER 2011–REVISED MARCH 2012

Low-Power, 2-Channel, 24-Bit Analog Front-End for Biopotential Measurements

Check for Samples: ADS1291, ADS1292 , ADS1292R

The

ADS1291,

ADS1292,

and

ADS1292R

1

FEATURES

incorporate all features commonly required in

portable, low-power medical electrocardiogram

(ECG), sports, and fitness applications.

23

•

Two Low-Noise PGAs and

Two High-Resolution ADCs

(ADS1292 and ADS1292R)

With high levels of integration and exceptional

performance, the ADS1291, ADS1292, and

ADS1292R enable the creation of scalable medical

instrumentation systems at significantly reduced size,

power, and overall cost.

•

Low Power: 335 μW/channel

Input-Referred Noise: 8 μV_PP

(150-Hz BW, G = 6)

•

Input Bias Current: 200 pA

Data Rate: 125 SPS to 8 kSPS

CMRR: –105 dB

The ADS1291, ADS1292, and ADS1292R have a

flexible input multiplexer per channel that can be

independently connected to the internally-generated

signals for test, temperature, and lead-off detection.

Additionally, any configuration of input channels can

be selected for derivation of the right leg drive (RLD)

output signal. The ADS1291, ADS1292, and

ADS1292R operate at data rates up to 8 kSPS. Lead-

off detection can be implemented internal to the

device, using the device internal excitation current

sink/source. The ADS1292R version includes a fully

integrated respiration impedance measurement

function.

Programmable Gain: 1, 2, 3, 4, 6, 8, or 12

Supplies: Unipolar or Bipolar

–

Analog: 2.7 V to 5.25 V

Digital: 1.7 V to 3.6 V

•

Built-In Right Leg Drive Amplifier, Lead-Off

Detection, Test Signals

Integrated Respiration Impedance

Measurement (ADS1292R)

•

Built-In Oscillator and Reference

The devices are packaged in a 5-mm × 5-mm, 32-pin

thin quad flat pack (TQFP). Operating temperature is

specified from –40°C to +85°C.

Flexible Power-Down, Standby Mode

SPI™-Compatible Serial Interface

Operating Temperature Range: –40°C to +85°C

REF

Test Signals and

Monitors

APPLICATIONS

Reference

SPI

•

Medical Instrumentation (ECG) including:

(ADS1292R)

–

Patient monitoring: Holter, event, stress,

and vital signs including ECG, AED, and

telemedicine

RESP

DEMOD

A1

A2

ADC1

ADC2

Oscillator

MUX

Control

–

Sports and fitness

(heart rate, respiration, and ECG)

To Channel

•

High-Precision, Simultaneous, Multichannel

Signal Acquisition

¼

(ADS1292R)

RESP

MOD

¼

DESCRIPTION

RESP

The ADS1291, ADS1292, and ADS1292R are

multichannel, simultaneous sampling, 24-bit, delta-

sigma (ΔΣ) analog-to-digital converters (ADCs) with a

built-in programmable gain amplifier (PGA), internal

reference, and an onboard oscillator.

RLD

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2

3

SPI is a trademark of Motorola.

All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

ADS1291

ADS1292

ADS1292R

SBAS502A –DECEMBER 2011–REVISED MARCH 2012

www.ti.com

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

FAMILY AND ORDERING INFORMATION⁽¹⁾

MAXIMUM

SAMPLE

RESOLUTION RATE (kSPS)

OPERATING

TEMPERATUR RESPIRATION

E RANGE

PACKAGE

OPTION

PACKAGE

DESIGNATOR

NUMBER OF

CHANNELS

ADC

PRODUCT

CIRCUITRY

TQFP

QFN

PBS

RSM

PBS

RSM

PBS

RSM

1

2

24

8

–40°C to +85°C

No

ADS1291I

TQFP

QFN

No

ADS1292I

No

TQFP

QFN

Yes

ADS1292RI

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the

device product folder at www.ti.com.

ABSOLUTE MAXIMUM RATINGS⁽¹⁾

Over operating free-air temperature range, unless otherwise noted.

ADS1291, ADS1292, ADS1292R

UNIT

V

AVDD to AVSS

–0.3 to +5.5

DVDD to DGND

–0.3 to +3.9

V

AGND to DGND

–0.3 to +0.3

V

Analog input to AVSS

Digital input to DVDD

Input current to any pin except supply pins

AVSS – 0.3 to AVDD + 0.3

V

DVSS – 0.3 to DVDD + 0.3

V

±10

±100

mA

°C

Momentary

Input current

Continuous

±10

Operating temperature range

Storage temperature range

Maximum junction temperature (T_J)

Human body model (HBM)

–40 to +85

–60 to +150

+150

±1000

±500

V

JEDEC standard 22, test method A114-C.01, all pins

ESD ratings

Charged device model (CDM)

JEDEC standard 22, test method C101, all pins

(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may

degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond

those specified is not implied.

2

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SBAS502A –DECEMBER 2011–REVISED MARCH 2012

ELECTRICAL CHARACTERISTICS

Minimum and maximum specifications apply from –40°C to +85°C. Typical specifications are at +25°C. All specifications are

at DVDD = 1.8 V, AVDD – AVSS = 3 V⁽¹⁾, V_REF= 2.42 V, external f_CLK= 512 kHz, data rate = 500 SPS, C_FILTER= 4.7 nF⁽²⁾

,

and gain = 6, unless otherwise noted.

ADS1291, ADS1292, ADS1292R

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

ANALOG INPUTS

Full-scale differential input voltage

(AINP – AINN)

±V_REF/GAIN

V

See the Input Common-Mode Range

subsection of the PGA Settings and Input

Range section

Input common-mode range

Input capacitance

20

pF

pA

nA

T_A= +25°C, input = 1.5 V

±200

Input bias current (PGA chop = 8 kHz)

T_A= –40°C to +85°C, input = 1.5 V

Chop rates other than 8 kHz

±1

See Pace Detect section

1000

No pull-up or pull-down current source

MΩ

Current source lead-off detection (nA),

AVSS + 0.3 V < AIN < AVDD – 0.3 V

500

100

DC input impedance

Current source lead-off detection (µA),

AVSS + 0.6 V < AIN < AVDD – 0.6 V

MΩ

PGA PERFORMANCE

Gain settings

1, 2, 3, 4, 6, 8, 12

8.5

With a 4.7-nF capacitor on PGA output

(see PGA Settings and Input Range section

for details)

Bandwidth

kHz

ADC PERFORMANCE

Resolution

24

Bits

Data rate

f_CLK= 512 kHz

125

8000

11

SPS

CHANNEL PERFORMANCE (DC Performance)

Gain = 6⁽³⁾, 10 seconds of data

8

μV_PP

Gain = 6, 256 points, 0.5 seconds of data

Input-referred noise

Gain settings other than 6,

data rates other than 500 SPS

See Noise Measurements section

Integral nonlinearity

Offset error

Full-scale with gain = 6, best fit

2

±100

2

ppm

μV

Offset error drift

μV/°C

μV

Offset error with calibration

Gain error

15

Excluding voltage reference error

Excluding voltage reference drift

±0.1

2

±0.2

% of FS

ppm/°C

% of FS

Gain drift

Gain match between channels

CHANNEL PERFORMANCE (AC performance)

0.2

CMRR

PSRR

Common-mode rejection ratio

Power-supply rejection ratio

Crosstalk

f_CM= 50 Hz and 60 Hz⁽⁴⁾

–105

–120

90

dB

f_PS= 50 Hz and 60 Hz

f_IN= 50 Hz and 60 Hz

–120

107

SNR

THD

Signal-to-noise ratio

f_IN= 10 Hz input, gain = 6

10 Hz, –0.5 dBFs, C_FILTER= 4.7nF

100 Hz, –0.5 dBFs, C_FILTER= 4.7nF

–104

–95

Total harmonic distortion

ADS1292R channel 1, 10 Hz, –0.5 dBFS,

C_FILTER= 47 nF

–82

dB

(1) Performance is applicable for 5-V operation as well. Production testing for limits is performed at 3 V.

(2) C_FILTERis the capacitor accross the PGA outputs; see the PGA Settings and Input Range section for details.

(3) Noise data measured in a 10-second interval. Test not performed in production. Input-referred noise is calculated with input shorted

(without electrode resistance) over a 10-second interval.

(4) CMRR is measured with a common-mode signal of AVSS + 0.3 V to AVDD – 0.3 V. The values indicated are the minimum of the two

channels.

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SBAS502A –DECEMBER 2011–REVISED MARCH 2012

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ELECTRICAL CHARACTERISTICS (continued)

Minimum and maximum specifications apply from –40°C to +85°C. Typical specifications are at +25°C. All specifications are

at DVDD = 1.8 V, AVDD – AVSS = 3 V⁽¹⁾, V_REF= 2.42 V, external f_CLK= 512 kHz, data rate = 500 SPS, C_FILTER= 4.7 nF⁽²⁾

,

and gain = 6, unless otherwise noted.

ADS1291, ADS1292, ADS1292R

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

DIGITAL FILTER

–3-dB bandwidth

0.262 f_DR

4

Hz

Digital filter settling

RIGHT LEG DRIVE (RLD) AMPLIFIER

RLD integrated noise

Full setting

Conversions

BW = 150 Hz

1.4

100

0.07

–85

μV_RMS

kHz

V/μs

dB

GBP

SR

Gain bandwidth product

Slew rate

50 kΩ || 10 pF load, gain = 1

f_IN= 100 Hz, gain = 1

THD

CMIR

Total harmonic distortion

Common-mode input range

Common-mode resistor matching

Short-circuit current

AVSS + 0.3

AVDD – 0.3

V

Internal 200-kΩ resistor matching

0.1

1.1

5

%

I_SC

mA

μA

Quiescent power consumption

LEAD-OFF DETECT

Frequency

See Register Map section for settings

ILEAD_OFF [1:0] = 00

0, f_DR/4

6

kHz

nA

μA

%

ILEAD_OFF [1:0] = 01

22

Current

ILEAD_OFF [1:0] = 10

6

ILEAD_OFF [1:0] = 11

22

Current accuracy

Comparator threshold accuracy

RESPIRATION (ADS1292R)

±10

mV

Internal source

32, 64

kHz

Frequency

External source

32

0

64

168.75

10,000

Phase shift

See Register Map section for settings

I_RESP= 30 µA

112.5

2000

Degrees

Ω

Impedance range

0.05-Hz to 2-Hz brick wall filter, 32-kHz

modulation clock, phase = 112.5,

using I_RESP= 30 µA with 2-kΩ baseline load,

gain = 4

Impedance measurement noise

Maximum modulator current

40

mΩ_PP

μA

Using Internal reference

100

EXTERNAL REFERENCE

3-V supply V_REF= (VREFP – VREFN)

5-V supply V_REF= (VREFP – VREFN)

2

2.5

4

VDD – 0.3

V

Reference input voltage

VREFN

VREFP

Negative input

Positive input

AVSS

V

AVSS + 2.5

120

V

Input impedance

kΩ

4

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SBAS502A –DECEMBER 2011–REVISED MARCH 2012

ELECTRICAL CHARACTERISTICS (continued)

Minimum and maximum specifications apply from –40°C to +85°C. Typical specifications are at +25°C. All specifications are

at DVDD = 1.8 V, AVDD – AVSS = 3 V⁽¹⁾, V_REF= 2.42 V, external f_CLK= 512 kHz, data rate = 500 SPS, C_FILTER= 4.7 nF⁽²⁾

,

and gain = 6, unless otherwise noted.

ADS1291, ADS1292, ADS1292R

PARAMETER

INTERNAL REFERENCE

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Register bit CONFIG2.VREF_4V = 0

Register bit CONFIG2.VREF_4V = 1

Available for external use

2.42

4.033

100

V

Output voltage

Output current drive

V_REFaccuracy

µA

±0.5

45

%

Internal reference drift

–40°C ≤ T_A≤ +85°C

ppm/°C

Settled to 0.2% with 10-µF capacitor on

VREFP pin

Start-up time

100

20

ms

µA

Quiescent current consumption

SYSTEM MONITORS

Analog supply reading error

Digital supply reading error

1

%

From power-supply ramp after power-on

reset (POR) to DRDY low

32

ms

Device wake up

From power-down mode to DRDY low

From STANDBY mode to DRDY low

1% accuracy

10

ms

VCAP1 settling time

0.5

145

490

s

Voltage

Coefficient

T_A= +25°C

mV

μV/°C

Temperature sensor

reading

TEST SIGNAL

Signal frequency

Signal voltage

Accuracy

See Register Map section for settings

At dc and 1 Hz

Hz

mV

%

±1

±2

CLOCK

Internal oscillator clock frequency

Internal clock accuracy

Nominal frequency

T_A= +25°C

512

kHz

%

±0.5

±1.5

–40°C ≤ T_A≤ +85°C

%

Internal oscillator start-up time

32

30

μs

Internal oscillator power consumption

μW

kHz

MHz

CLKSEL pin = 0, CLK_DIV = 0

CLKSEL pin = 0, CLK_DIV = 1

485

512

562.5

2.25

External clock input frequency

1.94

2.048

DIGITAL INPUT/OUTPUT

DVDD = 1.8 V to

3.6 V

V_IH

0.8 DVDD

–0.1

DVDD + 0.1

0.2 DVDD

V

DVDD = 1.8 V to

3.6 V

V_IL

V_IH

DVDD = 1.7 V to

1.8 V

DVDD – 0.2

Logic level

V_IL

DVDD = 1.7 V to

1.8 V

0.2

DVDD = 1.7 V to

3.6 V

V_OH

I_OH= –500 μA

0.9 DVDD

–10

DVDD = 1.7 V to

3.6 V

V_OL

I_IN

I_OL= +500 μA

0.1 DVDD

+10

V

Input current

0 V < V_DigitalInput< DVDD

μA

POWER-SUPPLY REQUIREMENTS

AVDD

DVDD

Analog supply

Digital supply

AVDD – DVDD

AVDD – AVSS

DVDD – DGND

2.7

1.7

3

5.25

3.6

V

1.8

–2.1

3.6

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ADS1292

ADS1292R

SBAS502A –DECEMBER 2011–REVISED MARCH 2012

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ELECTRICAL CHARACTERISTICS (continued)

Minimum and maximum specifications apply from –40°C to +85°C. Typical specifications are at +25°C. All specifications are

at DVDD = 1.8 V, AVDD – AVSS = 3 V⁽¹⁾, V_REF= 2.42 V, external f_CLK= 512 kHz, data rate = 500 SPS, C_FILTER= 4.7 nF⁽²⁾

,

and gain = 6, unless otherwise noted.

ADS1291, ADS1292, ADS1292R

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

SUPPLY CURRENT (RLD Amplifier Turned Off)

AVDD – AVSS = 3 V

205

250

75

μA

I_AVDD

AVDD – AVSS = 5 V

DVDD = 3.3 V

Normal mode

I_DVDD

DVDD = 1.8 V

32

POWER DISSIPATION (Analog Supply = 3 V, RLD Amplifier Turned Off)

Normal mode

ADS1292 and

670

160

450

160

335

450

740

495

µW

ADS1292R

Standby mode

Quiescent power

dissipation

Normal mode

ADS1291

Standby mode

ADS1292R

ADS1292

ADS1291

Normal mode

Quiescent power

dissipation, per

channel

POWER DISSIPATION (Analog Supply = 5 V, RLD Amplifier Turned Off)

Normal mode

ADS1292 and

1300

340

950

340

670

860

µW

ADS1292R

Standby mode

Quiescent power

dissipation

Normal mode

ADS1291

Standby mode

ADS1292R

ADS1292

ADS1291

Normal mode

Quiescent power

dissipation, per

channel

POWER DISSIPATION IN POWER-DOWN MODE

DVDD = 1.8 V

Analog supply = 3 V

1

4

µW

DVDD = 3.3 V

DVDD = 1.8 V

Analog supply = 5 V

5

DVDD = 3.3 V

10

TEMPERATURE

Specified temperature range

Operating temperature range

Storage temperature range

–40

–60

+85

°C

+150

THERMAL INFORMATION

ADS1291,

ADS1292,

ADS1292R

THERMAL METRIC⁽¹⁾

UNITS

PBS (TQFP)

32 PINS

68.4

θ_JA

Junction-to-ambient thermal resistance

θ_JCtop

θ_JB

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

25.9

30.5

°C/W

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

0.5

ψ_JB

24.3

θ_JCbot

n/a

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

6

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SBAS502A –DECEMBER 2011–REVISED MARCH 2012

PARAMETER MEASUREMENT INFORMATION

NOISE MEASUREMENTS

The ADS1291, ADS1292, and ADS1292R noise performance can be optimized by adjusting the data rate and

PGA setting. As the averaging is increased by reducing the data rate, the noise drops correspondingly.

Increasing the programmable gain amplifier (PGA) value reduces the input-referred noise, which is particularly

useful when measuring low-level biopotential signals. Table 1 through Table 8 summarize the ADS1291,

ADS1292, and ADS1292R noise performance. The data are representative of typical noise performance at T_A=

+25°C. The data shown are the result of averaging the readings from multiple devices and are measured with the

inputs shorted together. For the shown data rates, the ratio is approximately 6.6.

Table 1 through Table 8 show measurements taken with an internal reference. The data are also representative

of the ADS1291, ADS1292, and ADS1292R noise performance when using a low-noise external reference such

as the REF5025.

In Table 1 through Table 8, µV_RMSand µV_PPare measured values. SNR, noise-free bits, ENOB, and dynamic

range are calculated with Equation 1, Equation 2, and Equation 3.

SNR = ENOB ´ 6.02

(1)

2 V_REF

Noise-Free Bits = 2 log

Gain ´ Peak-to-Peak Noise

(2)

V_REF

ENOB = 2 log

2 ´ Gain ´ RMS Noise

(3)

Table 1. Input-Referred Noise (μV_RMS/μV_PP) 3-V Analog Supply and 2.42-V Reference⁽¹⁾

PGA GAIN = 1

PGA GAIN = 2

DR BITS

OF

CONFIG1

REGISTER

OUTPUT

DATA

RATE

–3-dB

BANDWIDTH

(Hz)

NOISE-

FREE

BITS

NOISE-

FREE

BITS

(SPS)

μV_RMS

1.5

μV_PP

10.3

14.4

18.9

30.8

99

SNR

121.0

117.8

115.1

111.3

104.5

89.7

ENOB

20.10

19.58

19.11

18.49

17.36

14.91

12.53

—

μV_RMS

0.8

μV_PP

5.6

SNR

120.0

117.1

113.9

110.6

104.0

90.3

ENOB

19.94

19.46

18.91

18.37

17.28

15.00

12.52

—

000

001

010

011

100

101

110

111

125

250

32.75

65.5

131

18.83

18.34

17.95

17.25

15.57

13.06

10.68

—

18.71

18.29

17.75

17.23

15.60

13.14

10.67

—

2.2

1.2

7.5

500

3.0

1.7

10.9

15.6

48

1000

2000

4000

8000

NA

262

4.6

2.5

524

10.1

55.2

287.3

—

5.3

1048

2096

NA

563

2930

—

26.0

144.1

—

265

1470

—

75.4

—

(1) At least 1000 consecutive readings were used to calculate the peak-to-peak noise values in this table.

Table 2. Input-Referred Noise (μV_RMS/μV_PP) 3-V Analog Supply and 2.42-V Reference⁽¹⁾

PGA GAIN = 3

PGA GAIN = 4

DR BITS

OF

CONFIG1

REGISTER

OUTPUT

DATA

RATE

–3-dB

BANDWIDTH

(Hz)

NOISE-

FREE

BITS

NOISE-

FREE

BITS

(SPS)

μV_RMS

0.6

μV_PP

4.1

SNR

119.2

115.9

113.0

109.5

103.7

90.5

ENOB

19.80

19.26

18.77

18.19

17.23

15.03

12.59

—

μV_RMS

0.5

μV_PP

3.4

SNR

117.9

114.8

111.9

108.7

103.2

90.8

ENOB

19.58

19.07

18.59

18.06

17.14

15.09

12.63

—

000

001

010

011

100

101

110

111

125

250

32.75

65.5

131

18.58

18.15

17.67

17.02

15.65

13.18

10.74

—

18.42

17.88

17.47

16.83

15.69

13.24

10.78

—

0.9

5.5

0.8

5.0

500

1.3

7.7

1.1

6.6

1000

2000

4000

8000

NA

262

1.9

12.0

31

1.6

10.3

23

524

3.7

2.9

1048

2096

NA

17.0

91.9

—

173

937

—

12.2

66.8

—

124

681

—

75.8

76.1

—

(1) At least 1000 consecutive readings were used to calculate the peak-to-peak noise values in this table.

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Table 3. Input-Referred Noise (μV_RMS/μV_PP) 3-V Analog Supply and 2.42-V Reference⁽¹⁾

PGA GAIN = 6

PGA GAIN = 8

DR BITS

OF

CONFIG1

REGISTER

OUTPUT

DATA

RATE

–3-dB

BANDWIDTH

(Hz)

NOISE-

FREE

BITS

NOISE-

FREE

BITS

(SPS)

μV_RMS

0.5

μV_PP

3.0

4.1

5.6

8.7

16

SNR

115.9

112.8

109.9

106.8

102.1

91.5

ENOB

19.26

18.73

18.25

17.73

16.96

15.19

12.69

—

μV_RMS

0.4

μV_PP

2.6

3.9

5.5

7.6

14

SNR

114.0

111.0

108.0

104.9

100.7

91.7

ENOB

18.94

18.44

17.93

17.42

16.72

15.24

12.73

—

000

001

010

011

100

101

110

111

125

250

32.75

65.5

131

18.04

17.58

17.14

16.49

15.64

13.34

10.84

—

17.82

17.22

16.75

16.26

15.36

13.39

10.88

—

0.7

0.6

500

0.9

0.8

1000

2000

4000

8000

NA

262

1.3

1.2

524

2.2

2.0

1048

2096

NA

7.5

77

5.5

56

42.7

—

436

—

76.4

31.3

—

319

—

76.6

—

(1) At least 1000 consecutive readings were used to calculate the peak-to-peak noise values in this table.

Table 4. Input-Referred Noise (μV_RMS/μV_PP) 3-V Analog Supply and 2.42-V Reference⁽¹⁾

PGA GAIN = 12

OUTPUT

DR BITS

OF

CONFIG1

REGISTER

DATA

RATE

(SPS)

–3-dB

BANDWIDTH

(Hz)

NOISE-

FREE

BITS

μV_RMS

0.4

μV_PP

2.5

3.5

5.0

6.9

11

SNR

111.3

108.4

105.0

102.1

98.6

92.0

76.9

—

ENOB

18.48

18.01

17.44

16.97

16.38

15.29

12.78

—

000

001

010

011

100

101

110

111

125

250

32.75

65.5

131

17.31

16.81

16.29

15.82

15.21

13.44

10.93

—

0.5

500

0.8

1000

2000

4000

8000

NA

262

1.1

524

1.7

1048

2096

NA

3.5

36

20.1

—

205

—

(1) At least 1000 consecutive readings were used to calculate the peak-to-peak noise values in this table.

Table 5. Input-Referred Noise (μV_RMS/μV_PP) 5-V Analog Supply and 4.033-V Reference⁽¹⁾

PGA GAIN = 1

PGA GAIN = 2

DR BITS

OF

CONFIG1

REGISTER

OUTPUT

DATA

RATE

–3-dB

BANDWIDTH

(Hz)

NOISE-

FREE

BITS

NOISE-

FREE

BITS

(SPS)

μV_RMS

1.6

μV_PP

10.2

13.3

18.9

31.9

167

SNR

124.9

122.3

119.3

115.2

105.2

90.0

ENOB

20.75

20.31

19.82

19.14

17.48

14.95

12.59

—

μV_RMS

0.9

μV_PP

5.4

SNR

124.3

121.3

118.2

114.4

105.5

89.9

ENOB

20.65

20.15

19.63

19.00

17.53

14.94

12.59

—

000

001

010

011

100

101

110

111

125

250

32.75

65.5

131

19.58

19.20

18.69

17.94

15.55

13.03

10.67

—

19.50

18.91

18.52

17.77

15.62

13.02

10.67

—

2.2

1.2

8.1

500

3.1

1.7

10.6

17.9

80

1000

2000

4000

8000

NA

262

4.9

2.7

524

15.5

89.6

460.1

—

7.5

1048

2096

NA

959

45.0

229.0

—

481

2450

—

4923

—

75.8

—

(1) At least 1000 consecutive readings were used to calculate the peak-to-peak noise values in this table.

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Table 6. Input-Referred Noise (μV_RMS/μV_PP) 5-V Analog Supply and 4.033-V Reference⁽¹⁾

PGA GAIN = 3

PGA GAIN = 4

DR BITS

OF

CONFIG1

REGISTER

OUTPUT

DATA

RATE

–3-dB

BANDWIDTH

(Hz)

NOISE-

FREE

BITS

NOISE-

FREE

BITS

(SPS)

μV_RMS

0.6

μV_PP

4.2

SNR

123.4

120.7

117.3

113.5

105.3

90.3

ENOB

20.50

20.04

19.49

18.85

17.49

15.00

12.62

—

μV_RMS

0.5

μV_PP

3.6

SNR

122.3

119.5

116.2

112.7

105.2

90.6

ENOB

20.32

19.86

19.31

18.72

17.47

15.06

12.63

—

000

001

010

011

100

101

110

111

125

250

32.75

65.5

131

19.28

18.82

18.27

17.62

15.61

13.08

10.70

—

19.08

18.66

18.04

17.48

15.67

13.14

10.71

—

0.9

5.7

0.7

4.8

500

1.3

8.4

1.1

7.4

1000

2000

4000

8000

NA

262

2.0

13.3

53

1.6

11.0

38

524

5.1

3.9

1048

2096

NA

28.7

149.3

—

307

1598

—

20.7

111.8

—

222

1196

—

76.0

—

(1) At least 1000 consecutive readings were used to calculate the peak-to-peak noise values in this table.

Table 7. Input-Referred Noise (μV_RMS/μV_PP) 5-V Analog Supply and 4.033-V Reference⁽¹⁾

PGA GAIN = 6

PGA GAIN = 8

DR BITS

OF

CONFIG1

REGISTER

OUTPUT

DATA

RATE

–3-dB

BANDWIDTH

(Hz)

NOISE-

FREE

BITS

NOISE-

FREE

BITS

(SPS)

μV_RMS

0.5

μV_PP

3.0

4.0

6.0

8.8

24

SNR

120.4

117.5

114.3

110.8

104.6

91.0

ENOB

19.99

19.52

18.99

18.41

17.38

15.12

12.69

—

μV_RMS

0.4

μV_PP

2.7

3.8

5.3

8.1

18

SNR

118.5

115.7

112.8

109.5

103.6

91.5

ENOB

19.68

19.21

18.74

18.19

17.22

15.21

12.72

—

000

001

010

011

100

101

110

111

125

250

32.75

65.5

131

18.78

18.36

17.75

17.20

15.74

13.20

10.77

—

18.48

18.01

17.53

16.92

15.73

13.29

10.80

—

0.6

500

0.9

0.8

1000

2000

4000

8000

NA

262

1.4

1.2

524

2.8

2.3

1048

2096

NA

13.3

71.5

—

142

765

—

9.3

100

560

—

76.4

52.3

—

76.6

—

(1) At least 1000 consecutive readings were used to calculate the peak-to-peak noise values in this table.

Table 8. Input-Referred Noise (μV_RMS/μV_PP) 5-V Analog Supply and 4.033-V Reference⁽¹⁾

PGA GAIN = 12

OUTPUT

DR BITS

OF

CONFIG1

REGISTER

DATA

RATE

(SPS)

–3-dB

BANDWIDTH

(Hz)

NOISE-

FREE

BITS

μV_RMS

0.4

μV_PP

2.6

3.4

5.2

6.9

14

SNR

115.7

112.9

109.8

106.6

101.9

92.0

ENOB

19.21

18.75

18.24

17.70

16.83

15.29

12.77

—

000

001

010

011

100

101

110

111

125

250

32.75

65.5

131

17.96

17.59

16.96

16.56

15.57

13.37

10.85

—

0.5

500

0.8

1000

2000

4000

8000

NA

262

1.1

524

1.9

1048

2096

NA

5.9

63

33.8

—

362

—

76.9

—

(1) At least 1000 consecutive readings were used to calculate the peak-to-peak noise values in this table.

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TIMING CHARACTERISTICS

t_CLK

CLK

t_CSSC

t_CSH

t_SDECODE

t_SPWL

CS

t_SCCS

t_SCLK

t_SPWH

SCLK

1

2

3

8

1

2

3

8

t_DIHD

t_DIST

t_DOPD

DIN

t_CSDOZ

Hi-Z

t_CSDOD

Hi-Z

DOUT

NOTE: SPI settings are CPOL = 0 and CPHA = 1.

Figure 1. Serial Interface Timing

Timing Requirements For Figure 1⁽¹⁾

2.7 V ≤ DVDD ≤ 3.6 V

1.7 V ≤ DVDD ≤ 2 V

PARAMETER

DESCRIPTION

Master clock period (CLK_DIV bit of LOFF_STAT register = 0)

Master clock period (CLK_DIV bit of LOFF_STAT register = 1)

CS low to first SCLK, setup time

SCLK period

MIN

1775

444

6

TYP

MAX

2170

542

MIN

1775

444

17

TYP

MAX UNIT

2170

542

ns

t_CLK

t_CSSC

ns

t_SCLK

50

66.6

25

ns

t_{SPWH, L}

t_DIST

SCLK pulse width, high and low

DIN valid to SCLK falling edge: setup time

Valid DIN after SCLK falling edge: hold time

SCLK rising edge to DOUT valid

CS high pulse

15

ns

10

ns

t_DIHD

10

11

ns

t_DOPD

t_CSH

t_CSDOD

t_SCCS

t_SDECODE

t_CSDOZ

12

10

22

20

ns

2

10

3

2

20

3

t_CLKs

ns

CS low to DOUT driven

Eighth SCLK falling edge to CS high

Command decode time

t_CLKs

ns

4

CS high to DOUT Hi-Z

(1) Specifications apply from –40°C to +85°C. Load on D_OUT= 20 pF || 100 kΩ.

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PIN CONFIGURATIONS

PBS PACKAGE

TQFP-32

(TOP VIEW)

PGA1N

PGA1P

IN1N

1

2

3

4

5

6

7

8

24 DGND

23 DVDD

22

DRDY

21 DOUT

20

IN1P

IN2N

SCLK

19 DIN

18

IN2P

PGA2N

PGA2P

CS

17 CLK

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PIN ASSIGNMENTS

NAME

AVDD

TERMINAL

FUNCTION

DESCRIPTION

12

13

17

14

18

24

19

21

22

23

26

25

3

Supply

Analog supply

AVSS

Analog ground

CLK

Digital input

Master clock input

CLKSEL

CS

Digital input

Master clock select

Digital input

Chip select

DGND

Supply

Digital ground

DIN

Digital input

SPI data in

DOUT

Digital output

Supply

SPI data out

DRDY

Data ready; active low

DVDD

Digital power supply

GPIO1/RCLK1

GPIO2/RCLK2

IN1N⁽¹⁾

Digital input/output

Analog input

Analog output

Digital input

General-purpose I/O 1 or resp clock 1 (ADS1292R)

General-purpose I/O 2 or resp clock 2 (ADS1292R)

Differential analog negative input 1

Differential analog positive input 1

Differential analog negative input 2

Differential analog positive input 2

PGA1 inverting output

IN1P⁽¹⁾

IN2N⁽¹⁾

IN2P⁽¹⁾

4

5

6

PGA1N

1

PGA1P

2

PGA1 noninverting output

PGA2 inverting output

PGA2N

7

PGA2P

8

PGA2 noninverting output

Power-down or system reset; active low

PWDN/RESET

RESP_MODN/IN3N⁽¹⁾

RESP_MODP/IN3P⁽¹⁾

15

32

31

Analog input/output

N-side respiration excitation signal for respiration or auxiliary input 3N

P-side respiration excitation signal for respiration or auxiliary input 3P

Right leg drive input to MUX or RLD amplifier noninverting input; connect

to AVDD if not used

RLDIN/RLDREF

29

Analog input

RLDINV

RLDOUT

SCLK

28

30

20

16

11

27

10

9

Analog input

Digital input

—

Right leg drive inverting input; connect to AVDD if not used

Right leg drive output

SPI clock

START

VCAP1

VCAP2

VREFN

VREFP

Start conversion

Analog bypass capacitor

—

Analog bypass capacitor

Analog input

Analog input/output

Negative reference voltage; must be connected to AVSS

Positive reference voltage

(1) Connect unused analog inputs to AVDD.

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TYPICAL CHARACTERISTICS

At T_A= +25°C, AVDD = 3 V, AVSS = 0 V, DVDD = 1.8 V, internal VREFP = 2.42 V, VREFN = AVSS, external clock =

512 kHz, data rate = 500 SPS, C_FILTER= 4.7 nF, and gain = 6, unless otherwise noted.

INPUT-REFERRED NOISE

NOISE HISTOGRAM

4

3

1200

1000

800

600

400

200

0

2

1

0

−1

−2

−3

−4

Peak−to−Peak Over 10 seconds = 8 µV

0

2

4

6

8

10

Time (sec)

G001

Input−Referred Noise (µV)

G002

Figure 2.

Figure 3.

INTERNAL REFERENCE vs TEMPERATURE

CMRR vs FREQUENCY

2.424

2.422

2.42

−95

−100

−105

−110

−115

−120

−125

−130

−135

Data Rate = 8 kSPS

AIN = AVDD − 0.3 V to AVSS + 0.3 V

Gain = 1

Gain = 2

Gain = 3

Gain = 4

Gain = 6

Gain = 8

Gain = 12

2.418

2.416

−40

−15

10

35

60

85

10

100

1k

Temperature (°C)

Frequency (Hz)

G003

G004

Figure 4.

Figure 5.

LEAKAGE CURRENT vs INPUT VOLTAGE

LEAKAGE CURRENT vs TEMPERATURE

0.7

2.5

2

AVDD = 3 V, Chop = 8 k

AVDD = 3 V, Chop = 32 k

AVDD = 3 V, Chop = 64 k

AVDD = 5 V, Chop = 8 k

AVDD = 5 V, Chop = 32 k

AVDD = 5 V, Chop =64 k

0.6

0.5

0.4

0.3

0.2

0.1

0

64 kHz Chop Rate

32 kHz Chop Rate

1.5

1

8 kHz Chop Rate

0.5

0

0.5

1

1.5

2

2.5

3

−40

−15

10

35

60

85

Input Signal (V)

Temperature (°C)

G030

G006

Figure 6.

Figure 7.

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TYPICAL CHARACTERISTICS (continued)

At T_A= +25°C, AVDD = 3 V, AVSS = 0 V, DVDD = 1.8 V, internal VREFP = 2.42 V, VREFN = AVSS, external clock =

512 kHz, data rate = 500 SPS, C_FILTER= 4.7 nF, and gain = 6, unless otherwise noted.

PSRR vs FREQUENCY

THD vs FREQUENCY

120

110

100

90

−55

−65

Data Rate = 8 kSPS, −0.5 dBFS

−75

−85

Gain = 1

Gain = 2

Gain = 3

Gain = 4

Gain = 6

Gain = 8

Gain = 12

80

−95

70

−105

−115

−125

Gain = 1

Gain = 2

Gain = 3

Gain = 4

Gain = 6

Gain = 8

Gain = 12

60

50

10

100

1k

10

100

1k

Frequency (Hz)

G007

G008

Figure 8.

Figure 9.

INL vs PGA GAIN

INL vs TEMPERATURE

4

3

2

1

0

4

2

0

−2

−4

−40 °C

−20 °C

0 °C

40 °C

50 °C

70 °C

85 °C

25 °C

2

4

6

8

10

12

−1

−0.5

0

0.5

1

PGA Gain

Input Range (Normalized to Full−Scale)

G009

G010

Figure 10.

Figure 11.

THD FFT PLOT

(60-Hz Signal)

FFT PLOT

(60-Hz Signal)

0

−20

0

−20

PGA Gain = 1

Input = 10Hz, −0.5 dBFS

THD = −103 dB

PGA Gain = 1

Input = 10Hz, −0.5 dBFS

THD = −101 dB

SNR = 80 dB

−40

SNR =117 dB

−60

Data Rate =500 sps

Data Rate = 8 ksps

−60

−80

−100

−120

−140

−160

−180

−100

−120

−140

−160

0

50

100

150

200

250

0

1000

2000

3000

4000

Frequency (Hz)

G011

G012

Figure 12.

Figure 13.

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TYPICAL CHARACTERISTICS (continued)

At T_A= +25°C, AVDD = 3 V, AVSS = 0 V, DVDD = 1.8 V, internal VREFP = 2.42 V, VREFN = AVSS, external clock =

512 kHz, data rate = 500 SPS, C_FILTER= 4.7 nF, and gain = 6, unless otherwise noted.

OFFSET vs PGA GAIN

(Absolute Value)

TEST SIGNAL AMPLITUDE ACCURACY

300

250

200

150

100

50

60

40

20

0

Data from 96 devices, Two lots

0

2

4

6

8

10

12

PGA Gain (dB)

G013

Error (%)

G014

Figure 14.

Figure 15.

LEAD-OFF CURRENT SOURCE ACCURACY

DISTRIBUTION

LEAD-OFF COMPARATOR THRESHOLD ACCURACY

140

120

100

80

60

40

20

0

Data from 96 devices, Two Lots

Data from 125 devices, Two lots

Current Setting = 24 nA

120

100

80

60

40

20

0

Threshold Error (mV)

Error in Current Magnitude (nA)

G015

G016

Figure 16.

Figure 17.

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OVERVIEW

The ADS1291, ADS1292, and ADS1292R are low-power, multichannel, simultaneously-sampling, 24-bit delta-

sigma (ΔΣ) analog-to-digital converters (ADCs) with integrated programmable gain amplifiers (PGAs). These

devices integrate various electrocardiogram (ECG)-specific functions that make them well-suited for scalable

ECG, sports, and fitness applications. The devices can also be used in high-performance, multichannel data

acquisition systems by powering down the ECG-specific circuitry.

The ADS1291, ADS1292, and ADS1292R have a highly programmable multiplexer that allows for temperature,

supply, input short, and RLD measurements. Additionally, the multiplexer allows any of the input electrodes to be

programmed as the patient reference drive. The PGA gain can be chosen from one of seven settings (1, 2, 3, 4,

6, 8, and 12). The ADCs in the device offer data rates from 125 SPS to 8 kSPS. Communication to the device is

accomplished using an SPI-compatible interface. The device provides two general-purpose I/O (GPIO) pins for

general use. Multiple devices can be synchronized using the START pin.

The internal reference can be programmed to either 2.42 V or 4.033 V. The internal oscillator generates a 512-

kHz clock. The versatile right leg drive (RLD) block allows the user to choose the average of any combination of

electrodes to generate the patient drive signal. Lead-off detection can be accomplished either by using an

external pull-up or pull-down resistor or the device internal current source or sink. An internal ac lead-off

detection feature is also available. Apart from the above features, the ADS1292R provides options for internal

respiration circuitry. Figure 18 shows a block diagram for the ADS1291, ADS1292, and ADS1292R.

AVDD

VCAP1

PGA1P PGA1N VREFP VCAP2 VREFN

DVDD

Power-Supply Signal

Temperature Sensor Input

Test Signal

Reference

RESP

DEMOD1

(ADS1292R)

RESP_EN

DRDY

Lead-Off Excitation Source

CS

SCLK

DIN

DOUT

SPI

IN1P

CLKSEL

CLK

EMI

Filter

DS

PGA1

ADC1

IN1N

IN2P

Oscillator

GPIO1/

RCLK

Control

EMI

Filter

MUX

IN2N

GPIO2/

RCLK

RESP_MODP/

IN3P

RESP

DS

PGA2

ADC2

PWDN/

RESET

RESP_MODN/

IN3N

START

(AVDD + AVSS)/2

Resp Mod

(ADS1292R)

RLD

Amplifier

AVSS

DGND

RLDIN/

RLDREF

RLD

OUT

RLD

INV

PGA2N PGA2P

Figure 18. Functional Block Diagram

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THEORY OF OPERATION

This section contains details of the ADS1291, ADS1292, and ADS1292R internal functional elements. The

analog blocks are discussed first followed by the digital interface. Blocks implementing ECG-specific functions

are covered in the end.

Throughout this document, f_CLKdenotes the signal frequency at the CLK pin, t_CLKdenotes the signal period of the

CLK pin, f_DRdenotes the output data rate, t_DRdenotes the output data time period, and f_MODdenotes the

frequency at which the modulator samples the input.

EMI FILTER

An RC filter at the input acts as an electromagnetic interference (EMI) filter on channels 1 and 2. The –3-dB filter

bandwidth is approximately 3 MHz.

INPUT MULTIPLEXER

The ADS1291, ADS1292, and ADS1292R input multiplexers are very flexible and provide many configurable

signal-switching options. Figure 19 shows the multiplexer for the ADS1291, ADS1292, and ADS1292R. Note that

TESTP, TESTM, and RLDIN/RLDREF are common to both channels. INP and INN are separate for each of the

three pins. This flexibility allows for significant device and sub-system diagnostics, calibration, and configuration.

Switch settings for each channel are selected by writing the appropriate values to the CH1SET or CH2SET

register (see the CH1SET and CH2SET Registers in the Register Map section for details). More details of the

ECG-specific features of the multiplexer are discussed in the Input Multiplexer subsection of the ECG-Specifc

Functions.

Device Noise Measurements

Setting CHnSET[3:0] = 0001 sets the common-mode voltage of (VREFP + VREFN)/2 to both inputs of the

channel. This setting can be used to test the inherent noise of the device in the user system.

Test Signals (TestP and TestN)

Setting CHnSET[3:0] = 0101 provides internally-generated test signals for use in sub-system verification at

power-up. This functionality allows the entire signal chain to be tested out. Although the test signals are similar to

the CAL signals described in the IEC60601-2-51 specification, this feature is not intended for use in compliance

testing.

Test signals are controlled through register settings (see the CONFIG2: Configuration Register 2 subsection in

the Register Map section for details). INT_TEST enables the test signal and TEST_FREQ controls switching at

the required frequency.

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INT_TEST

Device

MUX1[3:0] = 0101

MUX1[3:0] = 0100

MUX1[3:0] = 0011

TESTP

TEMPP

MVDDP

From LOFFP

MUX1[3:0] = 0000

IN2P

To PGA2_INP

MUX1[3:0] = 0110 or

MUX1[3:0] = 1000

MUX1[3:0] = 0001

MUX1[3:0] = 0010

VREFP + VREFN

2

EMI

Filter

MUX1[3:0] = 0111 or

MUX1[3:0] = 1000

MUX1[3:0] = 0000

IN2N

To PGA2_INN

From LOFFN

RLD_REF

MUX1[3:0] = 0010

MUX1[3:0] = 0011

MUX1[3:0] = 0100

MUX1[3:0] = 1001

MVDDN

TEMPN

INT_TEST

MUX1[3:0] = 0101

TESTM

TESTP

RLDIN/

RLDREF

INT_TEST

MUX1[3:0] = 0101

MUX1[3:0] = 0100

MUX1[3:0] = 0011

TEMPP

MVDDP

From LOFFP

MUX1[3:0] = 0000

IN1P

To PGA1_INP

MUX1[3:0] = 0111 or

MUX1[3:0] = 1000

MUX1[3:0] = 0001

MUX1[3:0] = 0010

VREFP + VREFN

2

EMI

Filter

MUX1[3:0] = 0110 or

MUX1[3:0] = 1000

MUX1[3:0] = 0001

MUX1[3:0] = 1001

MUX1[3:0] = 0000

IN1N

To PGA1_INN

From LOFFN

RLD_REF

MUX1[3:0] = 0010

MUX1[3:0] = 0011

MUX1[3:0] = 0100

MVDDN

MUX1[3:0] = 1001

TEMPN

RESP

MOD

INT_TEST

MUX1[3:0] = 0101

TESTM

RESP_MODP/IN3P

RESP_MODN/IN3N

NOTE: MVDD monitor voltage supply depends on channel number; see the Supply Measurements (MVDDP, MVDDN) section.

Figure 19. Input Multiplexer Block for Both Channels

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Auxiliary Differential Input (RESP_MODN/IN3N, RESP_MODN/IN3P)

In applications where the respiration modulator output is not used, the RESP_MODN/IN3N and

RESP_MODN/IN3P signals can be used as a third multiplexed differential input channel. These inputs can be

multiplexed to either of the ADC channels.

Temperature Sensor (TEMPP, TEMPN)

The ADS1291, ADS1292, and ADS1292R contain an on-chip temperature sensor. This sensor uses two internal

diodes with one diode having a current density 16x that of the other, as shown in Figure 20. The difference in

diode current densities yields a difference in voltage that is proportional to absolute temperature.

Temperature Sensor Monitor

AVDD

1x

2x

To MUX TEMPP

To MUX TEMPN

8x

1x

AVSS

Figure 20. Temperature Sensor Measurement in the Input

As a result of the low thermal resistance of the package to the printed circuit board (PCB), the internal device

temperature tracks the PCB temperature closely. Note that self-heating of the ADS1291, ADS1292, and

ADS1292R causes a higher reading than the temperature of the surrounding PCB.

The scale factor of Equation 4 converts the temperature reading to °C. Before using this equation, the

temperature reading code must first be scaled to μV.

Temperature Reading (mV) - 145,300 mV

Temperature (°C) =

+ 25°C

490 mV/°C

(4)

Supply Measurements (MVDDP, MVDDN)

Setting CHnSET[3:0] = 0011 sets the channel inputs to different supply voltages of the device. For channel 1

(MVDDP – MVDDN) is [0.5(AVDD + AVSS)]; for channel 2 (MVDDP – MVDDN) is DVDD/4. Note that to avoid

saturating the PGA while measuring power supplies, the gain must be set to '1'.

Lead-Off Excitation Signals (LoffP, LoffN)

The lead-off excitation signals are fed into the multiplexer before the switches. The comparators that detect the

lead-off condition are also connected to the multiplexer block before the switches. For a detailed description of

the lead-off block, refer to the Lead-Off Detection subsection in the ECG-Specific Functions section.

Auxiliary Single-Ended Input

The RLDIN/RLDREF pin is primarily used for routing the right leg drive signal to any of the electrodes in case the

right leg drive electrode falls off. However, the RLDIN/RLDREF pin can be used as a multiple single-ended input

channel. The signal at the RLDIN/RLDREF pin can be measured with respect to the midsupply [(AVDD +

AVSS)/2]. This measurement is done by setting the channel multiplexer setting MUXn[3:0] to '0010' in the

CH1SET and CH2SET registers.

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ANALOG INPUT

The ADS1291, ADS1292, and ADS1292R analog input is fully differential. Assuming PGA = 1, the differential

input (INP – INN) can span between –V_REFto +V_REF. Note that the absolute range for INP and INN must be

between AVSS – 0.3 V and AVDD + 0.3 V. Refer to Table 10 for an explanation of the correlation between the

analog input and the digital codes. There are two general methods of driving the ADS1291, ADS1292, and

ADS1292R analog input: single-ended or differential, as shown in Figure 21 and Figure 22. Note that INP and

INN are 180°C out-of-phase in the differential input method. When the input is single-ended, the INN input is held

at the common-mode voltage, preferably at mid-supply. The INP input swings around the same common voltage

and the peak-to-peak amplitude is (common-mode + 1/2 V_REF) and (common-mode – 1/2 V_REF). When the input

is differential, the common-mode is given by (INP + INN)/2. Both INP and INN inputs swing from (common-mode

+ 1/2 V_REFto common-mode – 1/2 V_REF). For optimal performance, it is recommended that the ADS1291,

ADS1292, and ADS1292R be used in a differential configuration.

-1/2 V_REFto

V_REF

Device

+1/2 V_REF

Peak-to-Peak

Device

Common

Voltage

Common

Voltage

V_REF

Peak-to-Peak

Single-Ended Input

Differential Input

Figure 21. Methods of Driving the ADS1291, ADS1292, and ADS1292R: Single-Ended or Differential

CM + 1/2 V_REF

+1/2 V_REF

INP

CM Voltage

-1/2 V_REF

INN = CM Voltage

CM - 1/2 V_REF

t

Single-Ended Inputs

INP

INN

+V_REF

CM + 1/2 V_REF

CM Voltage

CM - 1/2 V_REF

-V_REF

t

Differential Inputs

(INP) + (INN)

, Common-Mode Voltage (Single-Ended Mode) = INN.

Common-Mode Voltage (Differential Mode) =

2

Input Range (Differential Mode) = (AINP - AINN) = 2 V_REF

.

Figure 22. Using the ADS1291, ADS1292, and ADS1292R in Single-Ended and Differential Input Modes

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PGA SETTINGS AND INPUT RANGE

The PGA is a differential input or differential output amplifier, as shown in Figure 23. It has seven gain settings

(1, 2, 3, 4, 6, 8, and 12) that can be set by writing to the CHnSET register (see the CH1SET and CH2SET

Registers in the Register Map section for details). The ADS1291, ADS1292, and ADS1292R have CMOS inputs

and hence have negligible current noise.

From MuxP

R_S= 2 kW

PGA1P

PgaP

C_P1

R₂

150 kW

R₁

C_FILTER

4.7 nF

60 kW

(for Gain = 6)

R₂

150 kW

R_S= 2 kW

PgaN

PGA1N

C_P2

From MuxN

Figure 23. PGA Implementation

The PGA resistor string that implements the gain has 360 kΩ of resistance for a gain of 6. This resistance

provides a current path across the outputs of the PGA in the presence of a differential input signal. This current

is in addition to the quiescent current specified for the device in the presence of a differential signal at the input.

The PGA output is filtered by an RC filter before it goes to the ADC. The filter is formed by an internal resistor R_S

= 2 kΩ and an external capacitor C_FILTER(4.7 nF, typical). This filter acts as an anti-aliasing filter with the –3-dB

bandwidth of 8.4 kHz. The internal R_Sresistor is accurate to 15% so actual bandwidth will vary. This RC filter

also suppresses the glitch at the PGA output caused by ADC sampling. The minimum value of C_EXTthat can be

used is 4 nF. A larger value C_FILTERcapacitor can be used for increased attenuation at higher frequencies for

anti-aliasing purposes. If channel 1 of the ADS1292R is used for respiration measurement, then a 4.7-nF

external capacitor is recommended. The tradeoff is that a larger capacitor value gives degraded THD

performance. See Figure 24 for a diagram explaining the THD versus C_FILTERvalue for a 10-Hz input signal.

−85

−90

−95

−100

−105

5

10

15

20

25

C_FILTER(nF)

G025

Figure 24. THD versus C_FILTERValue

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Special care must be taken in PCB layout to minimize the parasitic capacitance C_P1/C_P2. The absolute value of

these capacitances must be less than 20 pF. Ideally, C_FILTERshould be placed right at the pins to minimize these

capacitors. Mismatch between these capacitors will lead to CMRR degradation. Assuming everything else is

perfectly matched, the 60-Hz CMRR as a function of this mismatch is given by Equation 5.

Gain

CMRR = 20log

2p ´ 2e3 ´ DC ´ 60

P

(5)

where ΔC_P= C_P1– C_P2

For example, a mismatch of 20 pF with a gain of 6 limits the CMRR to 112 dB. If ΔC_Pis small, then the CMRR is

limited by the PGA itself and is as specified in the Electrical Characteristics table. The PGA are chopped

internally at either 8, 32, or 64 kSPS, as determined by the CHOP bits (see the RLD_SENS: Right Leg Drive

Sense Selection register, bits[7:6]). The digital decimation filter filters out the chopping ripple in the normal path

so the chopping ripple is not a concern. If PGA output is used for hardware PACE detection, the chopping ripple

must be filtered. First-order filtering is provided by the RC filter at the PGA output. Additional filtering may be

needed to suppress the chopping ripple. If the PGA output is routed to other circuitry, a 20-kΩ series resistance

must be added in the path near the C_FILTERcapacitor. The routing should be matched to maintain the CMRR

performance.

Input Common-Mode Range

The usable input common-mode range of the front end depends on various parameters, including the maximum

differential input signal, supply voltage, and PGA gain. Equation 6 describes this range.

Gain V_{MAX_DIFF}

AVDD - 0.2 -

> CM > AVSS + 0.2 +

2

where:

V_{MAX_DIFF}= maximum differential signal at the input of the PGA

CM = common-mode range

(6)

For example:

If V_DD= 3 V, gain = 6, and V_{MAX_DIFF}= 350 mV

Then 1.25 V < CM < 1.75 V

Input Differential Dynamic Range

The differential (INP – INN) signal range depends on the analog supply and reference used in the system.

Equation 7 shows this range.

V_REF

±V_REF2 V_REF

=

Max (INP - INN) <

;

Full-Scale Range =

Gain

(7)

The 3-V supply, with a reference of 2.42 V and a gain of 6 for ECGs, is optimized for power with a differential

input signal of approximately 300 mV. For higher dynamic range, a 5-V supply with a reference of 4.033 V (set

by the VREF_4V bit of the CONFIG2 register) can be used to increase the differential dynamic range.

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ADC ΔΣ Modulator

Each channel of the ADS1291, ADS1292, and ADS1292R has a 24-bit ΔΣ ADC. This converter uses a second-

order modulator optimized for low-power applications. The modulator samples the input signal at the rate of f_MOD

= f_CLK/4 or f_CLK/16, as determined by the CLK_DIV bit. In both cases, the sampling clock has a typical value of

128 kHz. As in the case of any ΔΣ modulator, the ADS1291, ADS1292, and ADS1292R noise is shaped until

f_MOD/2, as shown in Figure 25. The on-chip digital decimation filters explained in the Digital Decimation Filter

section can be used to filter out the noise at higher frequencies. These on-chip decimation filters also provide

antialias filtering. This feature of the ΔΣ converters drastically reduces the complexity of analog antialiasing filters

that are typically needed with nyquist ADCs.

0

−10

−20

−30

−40

−50

−60

−70

−80

−90

−100

−110

−120

−130

−140

−150

−160

0.001

0.01

0.1

1

Normalized Frequency (f_IN/f_MOD

)

G001

Figure 25. Power Spectral Density (PSD) of a ΔΣ Modulator (4-Bit Quantizer)

DIGITAL DECIMATION FILTER

The digital filter receives the modulator output and decimates the data stream. By adjusting the amount of

filtering, tradeoffs can be made between resolution and data rate: filter more for higher resolution, filter less for

higher data rates. Higher data rates are typically used in ECG applications for implement software pace detection

and ac lead-off detection.

The digital filter on each channel consists of a third-order sinc filter. The decimation ratio on the sinc filters can

be adjusted by the DR bits in the CONFIG1 register (see the Register Map section for details). This setting is a

global setting that affects all channels and, therefore, in a device all channels operate at the same data rate.

Sinc Filter Stage (sinx/x)

The sinc filter is a variable decimation rate, third-order, low-pass filter. Data are supplied to this section of the

filter from the modulator at the rate of f_MOD. The sinc filter attenuates the high-frequency noise of the modulator,

then decimates the data stream into parallel data. The decimation rate affects the overall data rate of the

converter.

Equation 8 shows the scaled Z-domain transfer function of the sinc filter.

3

- N

1 - Z

½H(z)½ =

- 1

1 - Z

(8)

The frequency domain transfer function of the sinc filter is shown in Equation 9.

3

Npf

sin

f_MOD

H(f)½ =

pf

N ´ sin

f_MOD

where:

N = decimation ratio

(9)

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The sinc filter has notches (or zeroes) that occur at the output data rate and multiples thereof. At these

frequencies, the filter has infinite attenuation. Figure 26 shows the sinc filter frequency response and Figure 27

shows the sinc filter roll-off. With a step change at input, the filter takes 3 t_DRto settle. After a START signal

rising edge, the filter takes t_SETTLEtime to give the first data output. The filter settling times at various data rates

are discussed in the START subsection of the SPI Interface section. Figure 28 and Figure 29 show the filter

transfer function until f_MOD/2 and f_MOD/16, respectively, at different data rates. Figure 30 shows the transfer

function extended until 4 f_MOD. It can be seen that the ADS1291, ADS1292, and ADS1292R passband repeats

itself at every f_MOD. The input R-C anti-aliasing filters in the system should be chosen such that any interference

in frequencies around multiples of f_MODare attenuated sufficiently.

0

-0.5

-1

-20

-40

-60

-1.5

-2

-80

-100

-120

-140

-2.5

-3

0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5

0

0.05

0.1

0.15

0.2

0.25

0.3

0.35

Normalized Frequency (f_IN/f_DR

)

Normalized Frequency (f_IN/f_DR

)

Figure 26. Sinc Filter Frequency Response

Figure 27. Sinc Filter Roll-Off

0

DR[2:0] = 000

-20

-40

DR[2:0] = 110

-40

-60

-80

-100

-120

-140

-100

-120

-140

0

0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5

Normalized Frequency (f_IN/f_MOD

0

0.01

0.02

0.03

0.04

0.05

0.06

0.07

)

Normalized Frequency (f_IN/f_MOD

)

Figure 28. Transfer Function of On-Chip

Decimation Filters Until f_MOD/2

10

Figure 29. Transfer Function of On-Chip

Decimation Filters Until f_MOD/16

DR[2:0] = 110

DR[2:0] = 000

-10

-30

-50

-70

-90

-110

-130

0

0.5

1

1.5

2

2.5

3

3.5

4

Normalized Frequency (f_IN/f_MOD

)

Figure 30. Transfer Function of On-Chip Decimation Filters

Until 4f_MODfor DR[2:0] = 000 and DR[2:0] = 110

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REFERENCE

Figure 31 shows a simplified block diagram of the ADS1291, ADS1292, and ADS1292R internal reference. The

reference voltage is generated with respect to AVSS. The VREFN pin must always be connected to AVSS.

1 mF

VCAP1

(1)

R₁

2.42 V or

4.033 V

Bandgap

VREFP

(1)

R₃

10 mF

0.1 mF

(1)

R₂

VREFN

AVSS

To ADC Reference Inputs

(1) For V_REF= 2.42 V: R₁= 100 kΩ, R₂= 200 kΩ, and R₃= 200 kΩ. For V_REF= 4.033 V: R₁= 84 kΩ, R₂= 120 kΩ, and R₃= 280 kΩ.

Figure 31. Internal Reference

The external band-limiting capacitors determine the amount of reference noise contribution. For high-end ECG

systems, the capacitor values should be chosen such that the bandwidth is limited to less than 10 Hz so that the

reference noise does not dominate the system noise. When using a 3-V analog supply, the internal reference

must be set to 2.42 V. In case of a 5-V analog supply, the internal reference can be set to 4.033 V by setting the

VREF_4V bit in the CONFIG2 register.

Alternatively, the internal reference buffer can be powered down and VREFP can be applied externally. Figure 32

shows a typical external reference drive circuitry. Power-down is controlled by the PD_REFBUF bit in the

CONFIG2 register. This power-down is also used to share internal references when two devices are cascaded.

By default the device wakes up in external reference mode.

100 kW

10 pF

+5 V

0.1 mF

100 W

To VREFP Pin

OPA211

100 W

22 mF

10 mF

0.1 mF

+5 V

VIN

REF5025

TRIM

OUT

100 mF

22 mF

Figure 32. External Reference Driver

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CLOCK

The ADS1291, ADS1292, and ADS1292R provide two different methods for device clocking: internal and

external. Internal clocking is ideally suited for low-power, battery-powered systems. The internal oscillator is

trimmed for accuracy at room temperature. Over the specified temperature range the accuracy varies; see the

Electrical Characteristics. Clock selection is controlled by the CLKSEL pin and the CLK_EN register bit.

The CLKSEL pin selects either the internal or external clock. The CLK_EN bit in the CONFIG2 register enables

and disables the oscillator clock to be output in the CLK pin. A truth table for these two pins is shown in Table 9.

The CLK_EN bit is useful when multiple devices are used in a daisy-chain configuration. It is recommended that

during power-down the external clock be shut down to save power.

Table 9. CLKSEL Pin and CLK_EN Bit

CONFIG2.CLK_EN

CLKSEL PIN

BIT

CLOCK SOURCE

External clock

CLK PIN STATUS

Input: external clock

3-state

0

1

X

0

Internal clock oscillator

1

Output: internal clock oscillator

The ADS1291, ADS1292, and ADS1292R have the option to choose between two different external clock

frequencies (512 kHz or 2.048 MHz). This frequency is selected by setting the CLK_DIV bit (bit 6) in the

LOFF_STAT register. The modulator must be clocked at 128 kHz, regardless of the external clock frequency.

Figure 33 shows the relationship between the external clock (f_CLK) and the modulator clock (f_MOD). The default

mode of operation is f_CLK= 512 kHz. The higher frequency option has been provided to allow the SPI to run at a

higher speed. SCLK can be only twice the speed of f_CLKduring a register read or write, see section on sending

multi-byte commands. Having the 2.048 MHz option allows for register read and writes to be performed at SCLK

speeds up to 4.096 MHz.

Frequency

Divider

f

CLK

Divide-By-4

f

MOD

Frequency

Divider

Divide-By-16

CLK_DIV

(Bit 6 of LOFF_STAT

Register)

Figure 33. Relationship Between External Clock (f_CLK) and Modulator Clock (f_MOD

)

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DATA FORMAT

The ADS1291, ADS1292, and ADS1292R outputs 24 bits of data per channel in binary twos complement format,

MSB first. The LSB has a weight of V_REF/(2²³– 1). A positive full-scale input produces an output code of

7FFFFFh and the negative full-scale input produces an output code of 800000h. The output clips at these codes

for signals exceeding full-scale. Table 10 summarizes ideal output codes for different input signals. All 24 bits

toggle when the analog input is at positive or negative full-scale.

Table 10. Ideal Output Code versus Input Signal

INPUT SIGNAL, V_IN

(AINP – AINN)

IDEAL OUTPUT CODE⁽¹⁾

7FFFFFh

≥ V_REF

+V_REF/(2²³– 1)

0

000001h

000000h

–V_REF/(2²³– 1)

≤ –V_REF(2²³/2²³– 1)

FFFFFFh

800000h

(1) Excludes effects of noise, linearity, offset, and gain error.

SPI INTERFACE

The SPI-compatible serial interface consists of four signals: CS, SCLK, DIN, and DOUT. The interface reads

conversion data, reads and writes registers, and controls ADS1291, ADS1292, and ADS1292R operation. The

DRDY output is used as a status signal to indicate when data are ready. DRDY goes low when new data are

available.

Chip Select (CS)

CS selects the ADS1291, ADS1292, and ADS1292R for SPI communication. CS must remain low for the entire

duration of the serial communication. After the serial communication is finished, always wait four or more t_CLK

cycles before taking CS high. When CS is taken high, the serial interface is reset, SCLK and DIN are ignored,

and DOUT enters a high-impedance state. DRDY asserts when data conversion is complete, regardless of

whether CS is high or low.

Serial Clock (SCLK)

SCLK is the serial peripheral interface (SPI) serial clock. SCLK is used to shift commands in and shift data out

from the device. The serial clock features a Schmitt-triggered input and clocks data on the DIN and DOUT pins

into and out of the ADS1291, ADS1292, and ADS1292R. Even though the input has hysteresis, it is

recommended to keep SCLK as clean as possible to prevent glitches from accidentally forcing a clock event. The

absolute maximum SCLK limit is specified in the Serial Interface Timing table. When shifting in commands with

SCLK, make sure that the entire set of SCLKs is issued to the device. Failure to do so could result in the device

serial interface being placed into an unknown state, requiring CS to be taken high to recover.

For a single device, the minimum speed needed for the SCLK depends on the number of channels, number of

bits of resolution, and output data rate. (For multiple cascaded devices, see the Cascade Mode subsection of the

Multiple Device Configuration section.) The minimum speed can be calculated with Equation 10.

t_DR- 4 t_CLK

t_SCLK

<

N

_BITS´ N_CHANNELS+ 24

(10)

For example, if the ADS1292R is used in a 500-SPS mode (2 channels, 24-bit resolution), the minimum SCLK

speed is approximately 36 kHz.

Data retrieval can be done either by putting the device in RDATAC mode or by issuing a RDATA command for

data on demand. The above SCLK rate limitation applies to RDATAC. For the RDATA command, the limitation

applies if data must be read in between two consecutive DRDY signals. Equation 10 assumes that there are no

other commands issued in between data captures. SCLK can only be twice the speed of f_CLKduring register

reads and writes. For faster SPI interface, use f_CLK= 2.048 MHz and set the CLK_DIV register bit (in the

LOFF_STAT register) to '1'.

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Data Input (DIN)

The data input pin (DIN) is used along with SCLK to communicate with the ADS1291, ADS1292, and ADS1292R

(opcode commands and register data). The device latches data on DIN on the SCLK falling edge.

Data Output (DOUT)

The data output pin (DOUT) is used with SCLK to read conversion and register data from the ADS1291,

ADS1292, and ADS1292R. Data on DOUT are shifted out on the SCLK rising edge. DOUT goes to a high-

impedance state when CS is high. In read data continuous mode (see the SPI Command Definitions section for

more details), the DOUT output line also indicates when new data are available. This feature can be used to

minimize the number of connections between the device and the system controller.

Figure 34 shows the data output protocol for the ADS1292 and ADS1292R.

DRDY

CS

SCLK

DOUT

DIN

STAT

CH1

CH2

24-Bit

Figure 34. SPI Bus Data Output for the ADS1292 and ADS1292R (Two Channels)

Data Retrieval

Data retrieval can be accomplished in one of two methods. The read data continuous command (see the

RDATAC: Read Data Continuous section) can be used to set the device in a mode to read the data continuously

without sending opcodes. The read data command (see the RDATA: Read Data section) can be used to read

just one data output from the device (see the SPI Command Definitions section for more details). The conversion

data are read by shifting data out on DOUT. The MSB of the data on DOUT is clocked out on the first SCLK

rising edge. DRDY returns to high on the first SCLK falling edge. DIN should remain low for the entire read

operation.

The number of bits in the data output depends on the number of channels and the number of bits per channel.

For the ADS1292R, the number of data outputs is (24 status bits + 24 bits × 2 channels) = 72 bits. The format of

the 24 status bits is: (1100 + LOFF_STAT[4:0] + GPIO[1:0] + 13 '0's). The data format for each channel data is

twos complement, MSB first. When channels are powered down using user register settings, the corresponding

channel output is set to '0'. However, the sequence of channel outputs remains the same.

The ADS1291, ADS1292, and ADS1292R also provide a multiple readback feature. Data can be read out

multiple times by simply giving more SCLKs, in which case the MSB data byte repeats after reading the last byte.

Data Ready (DRDY)

DRDY is an output. When it transitions low, new conversion data are ready. The CS signal has no effect on the

data ready signal. The behavior of DRDY is determined by whether the device is in RDATAC mode or the

RDATA command is being used to read data on demand. (See the RDATAC: Read Data Continuous and

RDATA: Read Data subsections of the SPI Command Definitions section for further details).

When reading data with the RDATA command, the read operation can overlap the occurrence of the next DRDY

without data corruption.

The START pin or the START command is used to place the device either in normal data capture mode or pulse

data capture mode.

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Figure 35 shows the relationship between DRDY, DOUT, and SCLK during data retrieval (in case of an

ADS1291, ADS1292, and ADS1292R with a selected data rate that gives 24-bit resolution). DOUT is latched out

at the SCLK rising edge. DRDY is pulled high at the SCLK falling edge. Note that DRDY goes high on the first

SCLK falling edge regardless of the status of CS and regardless of whether data are being retrieved from the

device or a command is being sent through the DIN pin.

DRDY

DOUT

SCLK

Bit 71

Bit 70

Bit 69

Figure 35. DRDY with Data Retrieval (CS = 0)

GPIO

The ADS1291, ADS1292, and ADS1292R have a total of two general-purpose digital input/output (GPIO) pins

available in the normal mode of operation. The digital I/O pins are individually configurable as either inputs or as

outputs through the GPIOC bits register. The GPIOD bits in the GPIO register control the level of the pins. When

reading the GPIOD bits, the data returned are the logic level of the pins, whether they are programmed as inputs

or outputs. When the GPIO pin is configured as an input, a write to the corresponding GPIOD bit has no effect.

When configured as an output, a write to the GPIOD bit sets the output value.

If configured as inputs, these pins must be driven (do not float). The GPIO pins are set as inputs after power-on

or after a reset. Figure 36 shows the GPIO port structure. The pins should be shorted to DGND with a series

resistor if not used.

GPIO Data (read)

GPIO Pin

GPIO Data (write)

GPIO Control

Figure 36. GPIO Port Pin

Power-Down and Reset (PWDN/RESET)

The PWDN/RESET pins are shared. If PWDN/RESET is held low for longer than 2⁹f_MODclock cycles, the device

is powered down. The implementation is such that the device is always reset when PWDN/RESET makes a

transition from high to low. If the device is powered down it is reset first and then if 2¹⁰clock elapses it is

powered down. Hence, all registers must be rewritten after power up.

There are two methods to reset the ADS1291, ADS1292, and ADS1292R: pull the PWDN/RESET pin low, or

send the RESET opcode command. When using the PWDN/RESET pin, take it low to force a reset. Make sure

to follow the minimum pulse width timing specifications before taking the PWDN/RESET pin back high. The

RESET command takes effect on the eighth SCLK falling edge of the opcode command. On reset it takes 18 t_CLK

cycles to complete initialization of the configuration registers to the default states and start the conversion cycle.

Note that an internal RESET is automatically issued to the digital filter whenever the CONFIG1, RESP1, and

RESP2 registers are set to a new value with a WREG command.

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START

The START pin must be set high or the START command sent to begin conversions. When START is low or if

the START command has not been sent, the device does not issue a DRDY signal (conversions are halted).

When using the START opcode to control conversion, hold the START pin low. The ADS1291, ADS1292, and

ADS1292R feature two modes to control conversion: continuous mode and single-shot mode. The mode is

selected by SINGLE_SHOT (bit 7 of the CONFIG1 register). In multiple device configurations the START pin is

used to synchronize devices (see the Multiple Device Configuration subsection of the SPI Interface section for

more details).

Settling Time

The settling time (t_SETTLE) is the time it takes for the converter to output fully settled data when the START signal

is pulled high. Once START is pulled high, DRDY is also pulled high. The next DRDY falling edge indicates that

data are ready. Figure 37 shows the timing diagram and Table 11 shows the settling time for different data rates.

The settling time depends on f_CLKand the decimation ratio (controlled by the DR[2:0] bits in the CONFIG1

register). Refer to Table 10 for the settling time as a function of t_MOD. Note that when START is held high and

there is a step change in the input signal, it takes 3 t_DRfor the filter to settle to the new value. Settled data are

available on the fourth DRDY pulse. Settling time number uncertainty is one t_MODcycle. Therefore, it is

recommended to add one t_MODcycle delay before issuing SCLK to retrieve data.

t_SETTLE

START Pin

or

START Opcode

DIN

t_DR

4/f_CLK

DRDY

(1) Settling time uncertainty is one t_MODcycle.

Figure 37. Settling Time

Table 11. Settling Time for Different Data Rates

DR[2:0]

000

SETTLING TIME⁽¹⁾

UNIT⁽²⁾

t_MOD

—

4100

2052

1028

516

260

132

68

001

010

011

100

101

110

111

—

(1) Settling time uncertainty is one t_MODcycle.

(2) t_MOD= 4 t_CLKfor CLK_DIV = 0 and t_MOD= 16 t_CLKfor CLK_DIV = 1.

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Continuous Mode

Conversions begin when the START pin is taken high or when the START opcode command is sent. As seen in

Figure 38, the DRDY output goes high when conversions are started and goes low when data are ready.

Conversions continue indefinitely until the START pin is taken low or the STOP opcode command is transmitted.

When the START pin is pulled low or the stop command is issued, the conversion in progress is allowed to

complete. Figure 39 and Table 12 show the required DRDY timing to the START pin and the START and STOP

opcode commands when controlling conversions in this mode. To keep the converter running continuously, the

START pin can be permanently tied high. Note that when switching from pulse mode to continuous mode, the

START signal is pulsed or a STOP command must be issued, followed by a START command. This conversion

mode is ideal for applications that require a fixed continuous stream of conversions results.

START Pin

or

START⁽¹⁾

Opcode

STOP⁽¹⁾

Opcode

DIN

t_DR

t_SETTLE

DRDY

(1) START and STOP opcode commands take effect on the seventh SCLK falling edge.

Figure 38. Continuous Conversion Mode

t_SDSU

DRDY and DOUT

t_DSHD

START Pin

or

STOP⁽¹⁾

STOP Opcode

(1) START and STOP commands take effect on the seventh SCLK falling edge at the end of the opcode transmission.

Figure 39. START to DRDY Timing

Table 12. Timing Characteristics for Figure 39⁽¹⁾

SYMBOL

DESCRIPTION

MIN

UNIT

START pin low or STOP opcode to DRDY setup time

to halt further conversions

t_SDSU

8

t_MOD

START pin low or STOP opcode to complete current

conversion

t_DSHD

8

t_MOD

(1) START and STOP commands take effect on the seventh SCLK falling edge at the end of the opcode transmission.

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Single-Shot Mode

The single-shot mode is enabled by setting the SINGLE_SHOT bit in the CONFIG1 register to '1'. In single-shot

mode, the ADS1291, ADS1292, and ADS1292R perform a single conversion when the START pin is taken high

or when the START opcode command is sent. As seen in Figure 39, when a conversion is complete, DRDY goes

low and further conversions are stopped. Regardless of whether the conversion data are read or not, DRDY

remains low. To begin a new conversion, take the START pin low and then back high, or transmit the START

opcode again. When switching from continuous mode to pulse mode, make sure the START signal is pulsed or

issue a STOP command followed by a START command.

This conversion mode is provided for applications that require non-standard or non-continuous data rates.

Issuing a START command or toggling the START pin high resets the digital filter, effectively dropping the data

rate by a factor of four. Note that this mode leaves the system more susceptible to aliasing effects, requiring

more complex analog anti-aliasing filters at the inputs. Loading on the host processor increases because it must

toggle the START pin or send a START command to initiate a new conversion cycle.

START

t_SETTLE

4/f_CLK

Data Updating

DRDY

Figure 40. DRDY with No Data Retrieval in Single-Shot Mode

MULTIPLE DEVICE CONFIGURATION

The ADS1291, ADS1292, and ADS1292R are designed to provide configuration flexibility when multiple devices

are used in a system. The serial interface typically needs four signals: DIN, DOUT, SCLK, and CS. With one

additional chip select signal per device, multiple devices can be connected together. The number of signals

needed to interface n devices is 3 + n.

The right leg drive amplifiers can be daisy-chained as explained in the RLD Configuration with Multiple Devices

subsection of the ECG-Specific Functions section. To use the internal oscillator in a daisy-chain configuration,

one of the devices must be set as the master for the clock source with the internal oscillator enabled (CLKSEL

pin = 1) and the internal oscillator clock brought out of the device by setting the CLK_EN register bit to '1'. This

master device clock is used as the external clock source for the other devices.

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When using multiple devices, the devices can be synchronized with the START signal. The delay from START to

the DRDY signal is fixed for a fixed data rate (see the START subsection of the SPI Interface section for more

details on the settling times). Figure 41 shows the behavior of two devices when synchronized with the START

signal.

Device₁

START

CLK

START₁

CLK

DRDY₁

DRDY

Device₂

START₂

CLK

DRDY₂

DRDY

CLK

Note 1

START

DRDY₁

DRDY₂

Note 2

(1) Start pulse must be at least one t_MODcycle wide.

(2) Settling time number uncertainty is one t_MODcycle.

Figure 41. Synchronizing Multiple Converters

Standard Mode

Figure 42 shows a configuration with two devices cascaded together. One of the devices is an ADS1292R (two-

channel with RESP) and the other is an ADS1292 (two-channel). Together, they create a system with four

channels. DOUT, SCLK, and DIN are shared. Each device has its own chip select. When a device is not selected

by the corresponding CS being driven to logic 1, the DOUT of this device is high-impedance. This structure

allows the other device to take control of the DOUT bus.

START⁽¹⁾

START

DRDY

CS

INT

CLK

GPO0

GPO1

SCLK

MOSI

MISO

SCLK

DIN

ADS1292

(Device 0)

DOUT

Host Processor

START

CLK

DRDY

CS

SCLK

DIN

ADS1292R

(Device 1)

DOUT

Figure 42. Multiple Device Configurations

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SPI COMMAND DEFINITIONS

The ADS1291, ADS1292, and ADS1292R provide flexible configuration control. The opcode commands

summarized in Table 13 control and configure the ADS1291, ADS1292, and ADS1292R operation. The opcode

commands are stand-alone, except for the register read and register write operations that require a second

command byte plus data. CS can be taken high or held low between opcode commands but must stay low for

the entire command operation (especially for multi-byte commands). System opcode commands and the RDATA

command are decoded by the ADS1291, ADS1292, and ADS1292R on the seventh SCLK falling edge. The

register read and write opcodes are decoded on the eighth SCLK falling edge. Be sure to follow SPI timing

requirements when pulling CS high after issuing a command.

Table 13. Command Definitions

COMMAND

System Commands

WAKEUP

DESCRIPTION

FIRST BYTE

SECOND BYTE

Wake-up from standby mode

Enter standby mode

0000 0010 (02h)

0000 0100 (04h)

0000 0110 (06h)

0000 1000 (08h)

0000 1010 (0Ah)

0001 1010 (1Ah)

STANDBY

RESET

Reset the device

START

Start or restart (synchronize) conversions

Stop conversion

STOP

OFFSETCAL

Channel offset calibration

Data Read Commands

Enable Read Data Continuous mode.

RDATAC

0001 0000 (10h)

This mode is the default mode at power-up.⁽¹⁾

SDATAC

RDATA

Stop Read Data Continuously mode

0001 0001 (11h)

0001 0010 (12h)

Read data by command; supports multiple read back.

Register Read Commands

RREG

WREG

Read n nnnn registers starting at address r rrrr

Write n nnnn registers starting at address r rrrr

001r rrrr (2xh)⁽²⁾

010r rrrr (4xh)⁽²⁾

000n nnnn⁽²⁾

(1) When in RDATAC mode, the RREG command is ignored.

(2) n nnnn = number of registers to be read or written – 1. For example, to read or write three registers, set n nnnn = 0 (0010). r rrrr =

starting register address for read and write opcodes.

WAKEUP: Exit STANDBY Mode

This opcode exits the low-power standby mode; see the STANDBY: Enter STANDBY Mode subsection of the

SPI Command Definitions section. Time is required when exiting standby mode (see the Electrical

Characteristics for details). There are no restrictions on the SCLK rate for this command and it can be

issued any time. Any following command must be sent after 4 t_CLKcycles.

STANDBY: Enter STANDBY Mode

This opcode command enters the low-power standby mode. All parts of the circuit are shut down except for the

reference section. The standby mode power consumption is specified in the Electrical Characteristics. There are

no restrictions on the SCLK rate for this command and it can be issued any time. Do not send any other

command other than the wakeup command after the device enters the standby mode.

RESET: Reset Registers to Default Values

This command resets the digital filter cycle and returns all register settings to the default values. See the Reset

(RESET) subsection of the SPI Interface section for more details. There are no restrictions on the SCLK rate

for this command and it can be issued any time. It takes 9 f_MODcycles to execute the RESET command.

Avoid sending any commands during this time.

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START: Start Conversions

This opcode starts data conversions. Tie the START pin low to control conversions by command. If conversions

are in progress this command has no effect. The STOP opcode command is used to stop conversions. If the

START command is immediately followed by a STOP command then have a gap of 4 t_CLKcycles between them.

When the START opcode is sent to the device, keep the START pin low until the STOP command is issued.

(See the START subsection of the SPI Interface section for more details.) There are no restrictions on the

SCLK rate for this command and it can be issued any time.

STOP: Stop Conversions

This opcode stops conversions. Tie the START pin low to control conversions by command. When the STOP

command is sent, the conversion in progress completes and further conversions are stopped. If conversions are

already stopped, this command has no effect. There are no restrictions on the SCLK rate for this command and it

can be issued any time.

OFFSETCAL: Channel Offset Calibration

This command is used to cancel the channel offset. The CALIB_ON bit in the RESP2 register must be set to '1'

before issuing this command. OFFSETCAL must be executed every time there is a change in the PGA gain

settings.

RDATAC: Read Data Continuous

This opcode enables the output of conversion data on each DRDY without the need to issue subsequent read

data opcodes. This mode places the conversion data in the output register and may be shifted out directly. The

read data continuous mode is the device default mode; the device defaults to this mode on power-up.

RDATAC mode is cancelled by the Stop Read Data Continuous command. If the device is in RDATAC mode, a

SDATAC command must be issued before any other commands can be sent to the device. There is no

restriction on the SCLK rate for this command. However, the subsequent data retrieval SCLKs or the SDATAC

opcode command should wait at least 4 t_CLKcycles. RDATAC timing is shown in Figure 43. As Figure 43 shows,

there is a keep out zone of 4 t_CLKcycles around the DRDY pulse where this command cannot be issued in. To

retrieve data from the device after RDATAC command is issued, make sure either the START pin is high or the

START command is issued. Figure 43 shows the recommended way to use the RDATAC command. RDATAC is

ideally-suited for applications such as data loggers or recorders where registers are set once and do not need to

be re-configured.

START

DRDY

(1)

t_UPDATE

CS

SCLK

RDATAC Opcode

DIN

Hi-Z

Status Register + 2-Channel Data

DOUT

Next Data

(1) t_UPDATE= 4 x t_CLK. Do not read data during this time.

Figure 43. RDATAC Usage

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SDATAC: Stop Read Data Continuous

This opcode cancels the Read Data Continuous mode. There is no restriction on the SCLK rate for this

command, but the following command must wait for 4 t_CLKcycles.

RDATA: Read Data

Issue this command after DRDY goes low to read the conversion result (in Stop Read Data Continuous mode).

There is no restriction on the SCLK rate for this command, and there is no wait time needed for the subsequent

commands or data retrieval SCLKs. To retrieve data from the device after RDATA command is issued, make

sure either the START pin is high or the START command is issued. When reading data with the RDATA

command, the read operation can overlap the occurrence of the next DRDY without data corruption. Figure 44

shows the recommended way to use the RDATA command. RDATA is best suited for ECG- and EEG-type

systems where register setting must be read or changed often between conversion cycles.

START

DRDY

CS

SCLK

RDATA Opcode

DIN

Hi-Z

Status Register+ 8-Channel Data (216 Bits)

DOUT

Figure 44. RDATA Usage

Sending Multi-Byte Commands

The ADS1291, ADS1292, and ADS1292R serial interface decodes commands in bytes and requires 4 t_CLKcycles

to decode and execute. Therefore, when sending multi-byte commands, a 4 t_CLKperiod must separate the end of

one byte (or opcode) and the next.

Assume CLK is 512 kHz, then t_SDECODE(4 t_CLK) is 7.8125 µs. When SCLK is 16 MHz, one byte can be

transferred in 500 ns. This byte-transfer time does not meet the t_SDECODEspecification; therefore, a delay must be

inserted so the end of the second byte arrives 7.3125 µs later. If SCLK is 1 MHz, one byte is transferred in 8 µs.

Because this transfer time exceeds the t_SDECODEspecification, the processor can send subsequent bytes without

delay. In this later scenario, the serial port can be programmed to move from single-byte transfer per cycle to

multiple bytes.

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RREG: Read From Register

This opcode reads register data. The Register Read command is a two-byte opcode followed by the output of the

register data. The first byte contains the command opcode and the register address. The second byte of the

opcode specifies the number of registers to read – 1.

First opcode byte: 001r rrrr, where r rrrr is the starting register address.

Second opcode byte: 000n nnnn, where n nnnn is the number of registers to read – 1.

The 17th SCLK rising edge of the operation clocks out the MSB of the first register, as shown in Figure 45. When

the device is in read data continuous mode it is necessary to issue a SDATAC command before the RREG

command can be issued. The RREG command can be issued at any time. However, because this command is a

multi-byte command, there are restrictions on the SCLK rate depending on the way the SCLKs are issued. See

the Serial Clock (SCLK) subsection of the SPI Interface section for more details. Note that CS must be low for

the entire command.

CS

1

9

17

25

SCLK

DIN

OPCODE 1

OPCODE 2

REG DATA

REG DATA + 1

DOUT

Figure 45. RREG Command Example: Read Two Registers Starting from Register 00h (ID Register)

(OPCODE 1 = 0010 0000, OPCODE 2 = 0000 0001)

WREG: Write to Register

This opcode writes register data. The Register Write command is a two-byte opcode followed by the input of the

register data. The first byte contains the command opcode and the register address.

The second byte of the opcode specifies the number of registers to write – 1.

First opcode byte: 010r rrrr, where r rrrr is the starting register address.

Second opcode byte: 000n nnnn, where n nnnn is the number of registers to write – 1.

After the opcode bytes, the register data follows (in MSB-first format), as shown in Figure 46. The WREG

command can be issued at any time. However, because this command is a multi-byte command, there are

restrictions on the SCLK rate depending on the way the SCLKs are issued. See the Serial Clock (SCLK)

subsection of the SPI Interface section for more details. Note that CS must be low for the entire command.

CS

1

9

17

25

SCLK

DIN

OPCODE 1

OPCODE 2

REG DATA 1

REG DATA 2

DOUT

Figure 46. WREG Command Example: Write Two Registers Starting from 00h (ID Register)

(OPCODE 1 = 0100 0000, OPCODE 2 = 0000 0001)

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REGISTER MAP

Table 14 describes the various ADS1291, ADS1292, and ADS1292R registers.

Table 14. Register Assignments

RESET

VALUE

ADDRESS

Device Settings (Read-Only Registers)

00h ID

Global Settings Across Channels

REGISTER

(Hex)

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

XX

02

REV_ID7

REV_ID6

REV_ID5

1

0

REV_ID1

REV_ID0

SINGLE_

SHOT

01h

CONFIG1

0

DR2

DR1

DR0

PDB_LOFF_

COMP

02h

03h

CONFIG2

LOFF

80

10

1

PDB_REFBUF

COMP_TH0

VREF_4V

1

CLK_EN

0

INT_TEST

0

TEST_FREQ

FLEAD_OFF

COMP_TH2

COMP_TH1

ILEAD_OFF1

ILEAD_OFF0

Channel-Specific Settings

04h

05h

CH1SET

CH2SET

00

PD1

PD2

GAIN1_2

GAIN2_2

GAIN1_1

GAIN2_1

GAIN1_0

GAIN2_0

MUX1_3

MUX2_3

MUX1_2

MUX2_2

MUX1_1

MUX2_1

MUX1_0

MUX2_0

RLD_LOFF_

SENS

06h

RLD_SENS

00

CHOP1

CHOP0

PDB_RLD

RLD2N

RLD2P

RLD1N

RLD1P

07h

08h

LOFF_SENS

LOFF_STAT

00

0

FLIP2

0

FLIP1

LOFF2N

LOFF2P

LOFF1N

LOFF1P

CLK_DIV

RLD_STAT

IN2N_OFF

IN2P_OFF

IN1N_OFF

IN1P_OFF

GPIO and Other Registers

RESP_

DEMOD_EN1

RESP_MOD_

EN

09h

RESP1

00

RESP_PH3

RESP_PH2

RESP_PH1

RESP_PH0

1

RESP_CTRL

0Ah

0Bh

RESP2

GPIO

02

CALIB_ON

0

RESP_FREQ

GPIOC1

RLDREF_INT

GPIOD2

1

0C

GPIOC2

GPIOD1

User Register Description

ID: ID Control Register (Factory-Programmed, Read-Only)

Address = 00h

BIT 7

BIT 6

BIT 5

BIT 4

1

BIT 3

0

BIT 2

0

BIT 1

REV_ID1

BIT 0

REV_ID7

REV_ID6

REV_ID5

REV_ID0

This register is programmed during device manufacture to indicate device characteristics.

Bits[7:5]

REV_ID[7:5]: Revision identification

000 = Reserved

001 = Reserved

010 = ADS1x9x device

011 = ADS1292R device

100 = Reserved

101 = Reserved

110 = Reserved

111 = Reserved

Bit 4

Reads high

Bits[3:2]

Bits[1:0]

Reads low

REV_ID[1:0]: Revision identification

00 = ADS1191

01 = ADS1192

10 = ADS1291

11 = ADS1292 and ADS1292R

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CONFIG1: Configuration Register 1

Address = 01h

BIT 7

BIT 6

0

BIT 5

0

BIT 4

0

BIT 3

0

BIT 2

DR2

BIT 1

DR1

BIT 0

DR0

SINGLE_SHOT

This register configures each ADC channel sample rate.

Bit 7

SINGLE_SHOT: Single-shot conversion

This bit sets the conversion mode

0 = Continuous conversion mode (default)

1 = Single-shot mode

Bits[6:3]

Bits[2:0]

Must be set to '0'

DR[2:0]: Channel oversampling ratio

These bits determine the oversampling ratio of both channel 1 and channel 2.

BIT

000

001

010

011

100

101

110

111

OVERSAMPLING RATIO

f_MOD/1024

f_MOD/512

DATA RATE⁽¹⁾

125 SPS

250 SPS

f_MOD/256

500 SPS (default)

1 kSPS

f_MOD/128

f_MOD/64

2 kSPS

f_MOD/32

4 kSPS

f_MOD/16

8 kSPS

Do not use

(1) f_CLK= 512 kHz and CLK_DIV = 0 or f_CLK= 2.048 MHz and CLK_DIV = 1.

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CONFIG2: Configuration Register 2

Address = 02h

BIT 7

1

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

0

BIT 1

BIT 0

PDB_LOFF_

COMP

PDB_REFBUF

VREF_4V

CLK_EN

INT_TEST

TEST_FREQ

This register configures the test signal, clock, reference, and LOFF buffer.

Bit 7

Bit 6

Must be set to '1'

PDB_LOFF_COMP: Lead-off comparator power-down

This bit powers down the lead-off comparators.

0 = Lead-off comparators disabled (default)

1 = Lead-off comparators enabled

Bit 5

Bit 4

Bit 3

PDB_REFBUF: Reference buffer power-down

This bit powers down the internal reference buffer so that the external reference can be used.

0 = Reference buffer is powered down (default)

1 = Reference buffer is enabled

VREF_4V: Enables 4-V reference

This bit chooses between 2.42-V and 4.033-V reference.

0 = 2.42-V reference (default)

1 = 4.033-V reference

CLK_EN: CLK connection

This bit determines if the internal oscillator signal is connected to the CLK pin when an internal oscillator is used.

0 = Oscillator clock output disabled (default)

1 = Oscillator clock output enabled

Bit 2

Bit 1

Must be set to '0'

INT_TEST: Test signal selection

This bit determines whether the test signal is turned on or off.

0 = Off (default)

1 = On; amplitude = ±(VREFP – VREFN)/2400

Bit 0

TEST_FREQ: Test signal frequency

This bit determines the test signal frequency.

0 = At dc (default)

1 = Square wave at 1 Hz

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LOFF: Lead-Off Control Register

Address = 03h

BIT 7

BIT 6

BIT 5

BIT 4

1

BIT 3

BIT 2

BIT 1

0

BIT 0

COMP_TH2

COMP_TH1

COMP_TH0

ILEAD_OFF1

ILEAD_OFF0

FLEAD_OFF

This register configures the lead-off detection operation.

Bits[7:5]

COMP_TH[2:0]: Lead-off comparator threshold

These bits determine the lead-off comparator threshold. See the Lead-Off Detection subsection of the ECG-Specific

Functions section for a detailed description.

Comparator positive side

000 = 95% (default)

001 = 92.5%

010 = 90%

011 = 87.5%

100 = 85%

101 = 80%

110 = 75%

111 = 70%

Comparator negative side

000 = 5% (default)

001 = 7.5%

010 = 10%

011 = 12.5%

100 = 15%

101 = 20%

110 = 25%

111 = 30%

Bit 4

Must be set to '1'

Bits[3:2]

ILEAD_OFF[1:0]: Lead-off current magnitude

These bits determine the magnitude of current for the current lead-off mode.

00 = 6 nA (default)

01 = 22 nA

10 = 6 µA

11 = 22 µA

Bit 1

Bit 0

Must be set to '0'

FLEAD_OFF: Lead-off frequency

This bit selects ac or dc lead-off.

0 = At dc lead-off detect (default)

1 = At ac lead-off detect at f_DR/4 (500 Hz for an 2-kHz output rate)

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CH1SET: Channel 1 Settings

Address = 04h

BIT 7

PD1

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

GAIN1_2

GAIN1_1

GAIN1_0

MUX1_3

MUX1_2

MUX1_1

MUX1_0

This register configures the power mode, PGA gain, and multiplexer settings channels. See the Input Multiplexer

section for details.

Bit 7

PD1: Channel 1 power-down

0 = Normal operation (default)

1 = Channel 1 power-down⁽¹⁾

Bits[6:4]

GAIN1[2:0]: Channel 1 PGA gain setting

These bits determine the PGA gain setting for channel 1.

000 = 6 (default)

001 = 1

010 = 2

011 = 3

100 = 4

101 = 8

110 = 12

Bits[3:0]

MUX1[3:0]: Channel 1 input selection

These bits determine the channel 1 input selection.

0000 = Normal electrode input (default)

0001 = Input shorted (for offset measurements)

0010 = RLD_MEASURE

0011 = MVDD⁽²⁾for supply measurement

0100 = Temperature sensor

0101 = Test signal

0110 = RLD_DRP (positive input is connected to RLDIN)

0111 = RLD_DRM (negative input is connected to RLDIN)

1000 = RLD_DRPM (both positive and negative inputs are connected to RLDIN)

1001 = Route IN3P and IN3N to channel 1 inputs

1010 = Reserved

(1) When powering down channel 1, make sure the input multiplexer is set to input short configuration. Bits[3:0] = 001.

(2) For channel 1, (MVDDP – MVDDN) is [0.5(AVDD + AVSS)]; for channel 2, (MVDDP – MVDDN) is DVDD/4. Note that to avoid saturating

the PGA while measuring power supplies, the gain must be set to '1'.

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CH2SET: Channel 2 Settings

Address = 05h

BIT 7

PD2

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

GAIN2_2

GAIN2_1

GAIN2_0

MUX2_3

MUX2_2

MUX2_1

MUX2_0

This register configures the power mode, PGA gain, and multiplexer settings channels. See the Input Multiplexer

section for details.

Bit 7

PD2: Channel 2 power-down

0 = Normal operation (default)

1 = Channel 2 power-down⁽¹⁾

Bits[6:4]

GAIN2[2:0]: Channel 2 PGA gain setting

These bits determine the PGA gain setting for channel 2.

000 = 6 (default)

001 = 1

010 = 2

011 = 3

100 = 4

101 = 8

110 = 12

Bits[3:0]

MUX2[3:0]: Channel 2 input selection

These bits determine the channel 2 input selection.

0000 = Normal electrode input (default)

0001 = Input shorted (for offset measurements)

0010 = RLD_MEASURE

0011 = VDD/2 for supply measurement

0100 = Temperature sensor

0101 = Test signal

0110 = RLD_DRP (positive input is connected to RLDIN)

0111 = RLD_DRM (negative input is connected to RLDIN)

1000 = RLD_DRPM (both positive and negative inputs are connected to RLDIN)

1001 = Route IN3P and IN3N to channel 2 inputs

1010 = Reserved

(1) When powering down channel 2 and for ADS1291, make sure the input multiplexer is set to input short configuration. Bits[3:0] = 001.

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RLD_SENS: Right Leg Drive Sense Selection

Address = 06h

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

RLD_LOFF_

SENS

CHOP1

CHOP0

PDB_RLD

RLD2N

RLD2P

RLD1N

RLD1P

This register controls the selection of the positive and negative signals from each channel for right leg drive

derivation. See the Right Leg Drive (RLD DC Bias Circuit) subsection of the ECG-Specific Functions section for

details.

Bits[7:6]

CHOP[1:0]: Chop frequency

These bits determine PGA chop frequency

00 = f_MOD/16

01 = Reserved

10 = f_MOD/2

11 = f_MOD/4

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

PDB_RLD: RLD buffer power

This bit determines the RLD buffer power state.

0 = RLD buffer is powered down (default)

1 = RLD buffer is enabled

RLD_LOFF_SENSE: RLD lead-off sense function

This bit enables the RLD lead-off sense function.

0 = RLD lead-off sense is disabled (default)

1 = RLD lead-off sense is enabled

RLD2N: Channel 2 RLD negative inputs

This bit controls the selection of negative inputs from channel 2 for right leg drive derivation.

0 = Not connected (default)

1 = RLD connected to IN2N

RLD2P: Channel 2 RLD positive inputs

This bit controls the selection of positive inputs from channel 2 for right leg drive derivation.

0 = Not connected (default)

1 = RLD connected to IN2P

RLD1N: Channel 1 RLD negative inputs

This bit controls the selection of negative inputs from channel 1 for right leg drive derivation.

0 = Not connected (default)

1 = RLD connected to IN1N

RLD1P: Channel 1 RLD positive inputs

This bit controls the selection of positive inputs from channel 1 for right leg drive derivation.

0 = Not connected (default)

1 = RLD connected to IN1P

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LOFF_SENS: Lead-Off Sense Selection

Address = 07h

BIT 7

0

BIT 6

0

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

FLIP2

FLIP1

LOFF2N

LOFF2P

LOFF1N

LOFF1P

This register selects the positive and negative side from each channel for lead-off detection. See the Lead-Off

Detection subsection of the ECG-Specific Functions section for details. Note that the LOFF_STAT register bits

should be ignored if the corresponding LOFF_SENS bits are set to '1'.

Bits[7:6]

Bit 5

Must be set to '0'

FLIP2: Current direction selection

This bit controls the direction of the current used for lead-off derivation for channel 2.

0 = Disabled (default)

1 = Enabled

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

FLIP1: Current direction selection

This bit controls the direction of the current used for lead-off derivation for channel 1.

0 = Disabled (default)

1 = Enabled

LOFF2N: Channel 2 lead-off detection negative inputs

This bit controls the selection of negative input from channel 2 for lead-off detection.

0 = Disabled (default)

1 = Enabled

LOFF2P: Channel 2 lead-off detection positive inputs

This bit controls the selection of positive input from channel 2 for lead-off detection.

0 = Disabled (default)

1 = Enabled

LOFF1N: Channel 1 lead-off detection negative inputs

This bit controls the selection of negative input from channel 1 for lead-off detection.

0 = Disabled (default)

1 = Enabled

LOFF1P: Channel 1 lead-off detection positive inputs

This bit controls the selection of positive input from channel 1 for lead-off detection.

0 = Disabled (default)

1 = Enabled

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LOFF_STAT: Lead-Off Status

Address = 08h

BIT 7

0

BIT 6

BIT 5

0

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

RLD_STAT

(read only)

IN2N_OFF

(read only)

IN2P_OFF

(read only)

IN1N_OFF

(read only)

IN1P_OFF

(read only)

CLK_DIV

This register stores the status of whether the positive or negative electrode on each channel is on or off. See the

Lead-Off Detection subsection of the ECG-Specific Functions section for details. Ignore the LOFF_STAT values

if the corresponding LOFF_SENS bits are not set to '1'.

'0' is lead-on (default) and '1' is lead-off. When the LOFF_SENS bits[3:0] are '0', the LOFF_STAT bits should be

ignored.

Bit 7

Bit 6

Must be set to '0'

CLK_DIV : Clock divider selection

This bit sets the modultar divider ratio between f_CLKand f_MOD. Two external clock values are supported: 512 kHz and

2.048 MHz.

0 = f_CLKand f_MOD/4 (default, use when f_CLK= 512 kHz)

1 = f_CLKand f_MOD/16 (use when f_CLK= 2.048 MHz)

Bit 5

Bit 4

Must be set to '0'

RLD_STAT: RLD lead-off status

This bit determines the status of RLD.

0 = RLD is connected (default)

1 = RLD is not connected

Bit 3

Bit 2

Bit 1

Bit 0

IN2N_OFF: Channel 2 negative electrode status

This bit determines if the channel 2 negative electrode is connected or not.

0 = Connected (default)

1 = Not connected

IN2P_OFF: Channel 2 positive electrode status

This bit determines if the channel 2 positive electrode is connected or not.

0 = Connected (default)

1 = Not connected

IN1N_OFF: Channel 1 negative electrode status

This bit determines if the channel 1 negative electrode is connected or not.

0 = Connected (default)

1 = Not connected

IN1P_OFF: Channel 1 positive electrode status

This bit determines if the channel 1 positive electrode is connected or not.

0 = Connected (default)

1 = Not connected

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RESP1: Respiration Control Register 1

Address = 09h

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

1

BIT 0

RESP_

DEMOD_EN1

RESP_MOD_

EN

RESP_PH3

RESP_PH2

RESP_PH1

RESP_PH0

RESP_CTRL

This register controls the respiration functionality. This register applies to the ADS1292R version only. For the

ADS1291 and ADS1292 devices, 02h must be written to the RESP1 register.

Bit 7

RESP_DEMOD_EN1: Enables respiration demodulation circuitry

This bit enables and disables the demodulation circuitry on channel 1.

0 = RESP demodulation circuitry turned off (default)

1 = RESP demodulation circuitry turned on

Bit 6

RESP_MOD_EN: Enables respiration modulation circuitry

This bit enables and disables the modulation circuitry on channel 1.

0 = RESP modulation circuitry turned off (default)

1 = RESP modulation circuitry turned on

Bits[5:2]

RESP_PH[3:0]: Respiration phase⁽¹⁾

These bits control the phase of the respiration demodulation control signal.

RESP_PH[3:0]

0000

RESP_CLK = 32kHz

0° (default)

11.25°

RESP_CLK = 64 kHz

0° (default)

22.5°

0001

0010

22.5°

45°

0011

33.75°

67.5°

0100

45°

90°

0101

56.25°

112.5°

0110

67.5°

135°

0111

78.75°

157.5°

1000

90°

Not available

1001

101.25°

112.5°

1010

1011

123.75°

135°

1100

1101

146.25°

157.5°

1110

1111

168.75°

(1) The RESP_PH3 bit is ignored when RESP_CLK = 64 kHz.

Bit 1

Bit 0

Must be set to '1'

RESP_CTRL: Respiration control

This bit sets the mode of the respiration circuitry.

0 = Internal respiration with internal clock

1 = Internal respiration with external clock

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RESP2: Respiration Control Register 2

Address = 0Ah

BIT 7

BIT 6

0

BIT 5

0

BIT 4

0

BIT 3

0

BIT 2

BIT 1

BIT 0

1

CALIB_ON

RESP_FREQ

RLDREF_INT

This register controls the respiration and calibration functionality.

Bit 7

CALIB_ON: Calibration on

This bit is used to enable offset calibration.

0 = Off (default)

1 = On

Bits[6:3]

Bit 2

Must be '0'

RESP_FREQ: Respiration control frequency (ADS1292R only)

This bit controls the respiration control frequency when RESP_CTRL = 0. This bit must be written with '1' for the ADS1291

and ADS1292.

0 = 32 kHz (default)

1 = 64 kHz

Bit 1

Bit 0

RLDREF_INT: RLDREF signal

This bit determines the RLDREF signal source.

0 = RLDREF signal fed externally

1 = RLDREF signal (AVDD – AVSS)/2 generated internally (default)

Must be set to '1'

GPIO: General-Purpose I/O Register

Address = 0Bh

BIT 7

0

BIT 6

0

BIT 5

0

BIT 4

0

BIT 3

BIT 2

BIT 1

BIT 0

GPIOC2

GPIOC1

GPIOD2

GPIOD1

This register controls the GPIO pins.

Bits[7:4]

Bits[3:2]

Must be '0'

GPIOC[2:1]: GPIO 1 and 2 control

These bits determine if the corresponding GPIOD pin is an input or output.

0 = Output

1 = Input (default)

Bits[1:0]

GPIOD[2:1]: GPIO 1 and 2 data

These bits are used to read and write data to the GPIO ports.

When reading the register, the data returned correspond to the state of the GPIO external pins, whether they are

programmed as inputs or as outputs. As outputs, a write to the GPIOD sets the output value. As inputs, a write to the

GPIOD has no effect. GPIO is not available in certain respiration modes.

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ECG-SPECIFIC FUNCTIONS

INPUT MULTIPLEXER (REROUTING THE RIGHT LEG DRIVE SIGNAL)

The input multiplexer has ECG-specific functions for the right leg drive signal. The RLD signal is available at the

RLDOUT pin once the appropriate channels are selected for RLD derivation, feedback elements are installed

external to the chip, and the loop is closed. This signal can be fed after filtering or fed directly into the RLDIN pin,

as shown in Figure 47. This RLDIN signal can be multiplexed into any one of the input electrodes by setting the

MUX bits of the appropriate channel set registers to '0110' for P-side or '0111' for N-side. Figure 47 shows the

RLD signal generated from channel 1 and routed to the N-side of channel 2. This feature can be used to

dynamically change the electrode that is used as the reference signal to drive the patient body. Note that the

corresponding channel cannot be used and can be powered down.

RLD1P = 1

IN1P

EMI

Filter

PGA1

PGA2

RLD1N = 1

MUX1[3:0] = 0000

IN1N

IN2P

RLD2P = 0

RLD2N = 0

EMI

Filter

MUX1[3:0] = 0111

IN2N

RLDREF_INT = 1

(AVDD + AVSS)

MUX

2

RLDREF_INT = 0

RLD_AMP

ADS1292R

RLDIN/RLDREF

RLDOUT

RLDINV

(1)

1 M

Filter or

Feedthrough

1.5 nF⁽¹⁾

(1) Typical values for example only.

Figure 47. Example RLDOUT Signal Configured to be Routed to IN2N

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Input Multiplexer (Measuring the Right Leg Drive Signal)

The RLDOUT signal can also be routed to a channel (that is not used for the calculation of RLD) for

measurement. Figure 48 shows the register settings to route the RLDIN signal to channel 2. The measurement is

done with respect to the voltage (AVDD + AVSS)/2. This feature is useful for debugging purposes during product

development.

RLD1P = 1

IN1P

EMI

Filter

PGA1

PGA2

RLD1N = 1

MUX1[3:0] = 0000

IN1N

IN2P

RLD2P = 0

RLD2N = 0

EMI

Filter

MUX1[3:0] = 0010

IN2N

RLDREF_INT = 1

(AVDD + AVSS)

2

MUX

MUX1[3:0] = 0010

RLDREF_INT = 0

RLD_AMP

Device

RLDIN/RLDREF

RLDOUT

RLDINV

(1)

1 M

Filter or

Feedthrough

1.5 nF⁽¹⁾

(1) Typical values for example only.

Figure 48. RLDOUT Signal Configured to be Read Back by Channel 2

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LEAD-OFF DETECTION

Patient electrode impedances are known to decay over time. It is necessary to continuously monitor these

electrode connections to verify a suitable connection is present. The ADS1291, ADS1292, and ADS1292R lead-

off detection functional block provides significant flexibility to the user to choose from various lead-off detection

strategies. Though called lead-off detection, this is in fact an electrode-off detection.

The basic principle is to inject an excitation signal and measure the response to find out if the electrode is off. As

shown in the lead-off detection functional block diagram in Figure 49, this circuit provides two different methods

of determining the state of the patient electrode. The methods differ in the frequency content of the excitation

signal. Lead-off can be selectively done on a per channel basis using the LOFF_SENS register. Also, the internal

excitation circuitry can be disabled and just the sensing circuitry can be enabled.

Skin,

Patient

Patient Electrode Contact Protection

Model

Resistor

47 nF

51 k

IN1P_OFF/

IN2P_OFF

30 k

V_INP

V_INN

EMI

Filter

PGA

To ADC

51 k

LOFF1P/

LOFF2P

LOFF1N/

LOFF2N

47 nF

IN1N_OFF/

IN2N_OFF

47 nF

51 k

4-Bit

DAC

AVDD AVSS

COMP_TH[2:0]

30 k

RLD OUT

NOTE: The R_Pvalue must be selected in order to be below the maximum allowable current flow into a patient (in accordance with the

relevant specification the latest revision of IEC 60601).

Figure 49. Lead-Off Detection

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DC Lead-Off

In this method, the lead-off excitation is with a dc signal. The dc excitation signal can be chosen from either an

external pull-up or pull-down resistor or a current source or sink, as shown in Figure 50. One side of the channel

is pulled to supply and the other side is pulled to ground. The internal current source and current sink can be

swapped by setting the FLIP1 and FLIP2 bits in the LOFF_SENS register. In case of current source or sink, the

magnitude of the current can be set by using the ILEAD_OFF[1:0] bits in the LOFF register. The current source

or sink gives larger input impedance compared to the 10-MΩ pull-up or pull-down resistor.

AVDD

Device

10 MW

INP

INN

INP

INN

PGA

10 MW

a) External Pull-Up/Pull-Down Resistors

b) Input Current Source

Figure 50. DC Lead-Off Excitation Options

Sensing of the response can be done either by looking at the digital output code from the device or by monitoring

the input voltages with an on-chip comparator. If either of the electrodes is off, the pull-up resistors and the pull-

down resistors saturate the channel. By looking at the output code it can be determined that either the P-side or

the N-side is off. To pinpoint which one is off, the comparators must be used. The input voltage is also monitored

using a comparator and a 4-bit digital-to-analog converter (DAC) whose levels are set by the COMP_TH[2:0] bits

in the LOFF register. The output of the comparators are stored in the LOFF_STAT register. These two registers

are available as a part of the output data stream. (See the Data Output Protocol (DOUT) subsection of the SPI

Interface section.) If dc lead-off is not used, the lead-off comparators can be powered down by setting the

PD_LOFF_COMP bit in the CONFIG2 register.

An example procedure to turn on dc lead-off is given in the Lead-Off subsection of the Quick-Start Guide section.

AC Lead-Off

In this method, an out-of-band ac signal is used for excitation. The ac signal is generated by alternatively

providing an internal current source and current sink at the input with a fixed frequency. The excitation frequency

is a function of the output data rate and is f_DR/4. This out-of-band excitation signal is passed through the channel

and measured at the output.

Sensing of the ac signal is done by passing the signal through the channel to digitize it and measure at the

output. The ac excitation signals are introduced at a frequency that is above the band of interest, generating an

out-of-band differential signal that can be filtered out separately and processed. By measuring the magnitude of

the excitation signal at the output spectrum, the lead-off status can be calculated. Therefore, the ac lead-off

detection can be accomplished simultaneously with the ECG signal acquisition.

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RLD Lead-Off

The ADS1291, ADS1292, and ADS1292R provide two modes for determining whether the RLD is correctly

connected:

•

RLD lead-off detection during normal operation

RLD lead-off detection during power-up

The following sections provide details of the two modes of operation.

RLD Lead-Off Detection During Normal Operation

During normal operation, the ADS1291, ADS1292, and ADS1292R RLD lead-off at power-up function cannot be

used because it is necessary to power off the RLD amplifier.

RLD Lead-Off Detection At Power-Up

This feature is included in the ADS1291, ADS1292, and ADS1292R for use in determining whether the right leg

electrode is suitably connected. At power-up, the ADS1291, ADS1292, and ADS1292R provides a procedure to

determine the RLD electrode connection status using a current sink, as shown in Figure 51. The reference level

of the comparator is set to determine the acceptable RLD impedance threshold.

Skin,

Patient

Patient Electrode Contact Protection

Model

47 nF

Resistor

To ADC input (through V_REF

connection to any of the channels).

RLD_STAT

30 k

51 k

RLD_LOFF_SENS

AVSS

NOTE: The R_Pvalue must be selected in order to be below the maximum allowable current flow into a patient (in accordance with the

relevant specification the latest revision of IEC 60601).

Figure 51. RLD Lead-Off Detection at Power-Up

When the RLD amplifier is powered on, the current source has no function. Only the comparator can be used to

sense the voltage at the output of the RLD amplifier. The comparator thresholds are set by the same LOFF[7:5]

bits used to set the thresholds for other negative inputs.

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Right Leg Drive (RLD DC Bias Circuit)

The right leg drive (RLD) circuitry is used as a means to counter the common-mode interference in a ECG

system as a result of power lines and other sources, including fluorescent lights. The RLD circuit senses the

common-mode of a selected set of electrodes and creates a negative feedback loop by driving the body with an

inverted common-mode signal. The negative feedback loop restricts the common-mode movement to a narrow

range, depending on the loop gain. Stabilizing the entire loop is specific to the individual user system based on

the various poles in the loop. The ADS1291, ADS1292, and ADS1292R integrates the muxes to select the

channel and an operational amplifier. All the amplifier terminals are available at the pins, allowing the user to

choose the components for the feedback loop. The circuit shown in Figure 52 shows the overall functional

connectivity for the RLD bias circuit.

The reference voltage for the right leg drive can be chosen to be internally generated (AVDD + AVSS)/2 or it can

be provided externally with a resistive divider. The selection of an internal versus external reference voltage for

the RLD loop is defined by writing the appropriate value to the RLDREF_INT bit in the RESP2 register.

From

MUX1P

RLD1P

400 k

PGA1P

PGA1N

From

MUX2P

150 k

RLD2P

400 k

PGA2P

PGA2N

60 k

150 k

60 k

400 k

From

MUX1N

RLD1N

400 k

From

MUX2N

RLD2N

RLDINV

(1)

C_EXT

1.5 nF

R_EXT

1 M

RLD

Amp

(AVDD + AVSS)

2

RLDOUT

RLDREF_INT

RLDIN/RLDREF

RLDREF_INT

To MUX

(1) Typical values.

Figure 52. RLD Channel Selection

If the RLD function is not used, the amplifier can be powered down using the PDB_RLD bit. This bit is also used

in daisy-chain mode to power-down all but one of the RLD amplifiers.

The functionality of the RLDIN pin is explained in the Input Multiplexer section.

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RLD Configuration with Multiple Devices

Figure 53 shows multiple devices connected to an RLD.

(AVDD+AVSS)

2

(AVDD+AVSS)

2

(AVDD+AVSS)

2

Device N

VA2

Device 2

VA2

Device 1

VA2

VA1

Power-Down

RLDIN/

RLDREF

RLDIN/

RLDREF

R_EXT

C_EXT

RLD

OUT

RLD

OUT

RLDIN/

RLDREF

RLDINV

RLD

OUT

Figure 53. RLD Connection for Multiple Devices

PACE DETECT

The ADS1291 and ADS1292 provide flexibility for PACE detection by using an external hardware. The external

hardware approach is made possible by bringing out the output of the PGA at pins: PGA1P, PGA1N and PGA2P,

PGA2N.

External hardware circuitry can be used to detect the presence of the pulse. The output of the PACE detection

logic can then be fed into the device through one of the GPIO pins. The GPIO data are transmitted through the

SPI port and loaded 2 t_CLKs before DRDY goes low.

When in pace detection mode, the chopping ripple can interfere with pace detect in hardware. It is therefore

preffered to chop thee PGA at a higher frequency (32 kHz or 64 kHz). The RC filter at the PGA output,

suppresses this ripple to a reasonable level. Additionally, suppression can be obtained with an additional RC

stage. The trade-off with chopping the PGA at a higher frequency is an increase in the input bias current.

Figure 6 shows bias current versus input voltage for three different chop frequencies.

RESPIRATION

The ADS1292R provides two options for respiration: internal respiration with external clock and internal

respiration with internal clock, as shown in Table 15.

Table 15. Respiration Control

RESP_CTRL

DESCRIPTION

0

1

Internal respiration with internal clock

Internal respiration with external clock

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Internal Respiration Circuitry with Internal Clock (ADS1292R)

This mode is set by RESP_CTRL = 0. Figure 54 shows a block diagram of the internal respiration circuitry. The

internal modulation and demodulator circuitry can be selectively used. The modulation block is controlled by the

RESP_MOD_EN bit and the demodulation block is controlled by the RESP_DEMOD_EN bit. The modulation

signal is a square wave of the magnitude VREFP – AVSS. When the internal modulation circuitry is used, the

output of the modulation circuitry is available at the RESP_MODP and RESP_MODM pins of the device. This

availability allows custom filtering to be added to the square wave modulation signal. In this mode, GPIO1 and

GPIO2 can be used for other purposes. The modulation frequency of the respiration circuit is set by the

RESP_FREQ bits.

CLK (512 kHz)

RESP_FREQ

CLK GEN

RESP_MOD_EN

RESP_MODP

RESP_MODN

VREFP

RESP_CTRL

Modulation

Block

AVSS

I/O

RESP_CTRL

RESP_MOD_CLK

GPIO1

GPIO2

IN1P

Ch1

ADC

EMI

Filter

Ch1

PGA

Demodulation

V_BIAS

MUX

Block

IN1N

RESP_DEMOD_EN

PGA1P

PGA1N

47 nF

Figure 54. Internal Respiration Timing Diagram

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Internal Respiration Circuitry with External Clock (ADS1292R)

This mode is set by RESP_CTRL = 1. In this mode GPIO1 and GPIO2 are automatically configured as inputs.

GPIO1 and GPIO2 cannot be used for other purposes. The signals must be provided as described in Figure 55.

(Modulation Clock)

GPIO1

t_PHASE

t_BLKDLY

(Blocking Signal)

GPIO2

Figure 55. Internal Respiration (RESP_CTRL = 1) Timing Diagram

Table 16. Timing Characteristics for Figure 55⁽¹⁾

1.65 V ≤ DVDD ≤ 3.6 V

PARAMETER

t_PHASE

DESCRIPTION

MIN

TYP

MAX

168.75

5

UNIT

Degrees

ns

Respiration phase delay

0

t_BLKDLY

Modulation clock rising edge to XOR signal

0

(1) Specifications apply from –40°C to +85°C.

ADS1292R Application

The ADS1292R channel 1 with respiration enabled mode cannot be used to acquire ECG signals. If the right arm

(RA) and left arm (LA) leads are intended to measure respiration and ECG signals, the two leads can be wired

into channel 1 for respiration and channel 2 for ECG signals, as shown in Figure 56.

R₆

10 MW

AVDD

R₅

IN1P

10 MW

C₁

AVSS

ADS1292R

2.2 nF

C₂

C₃

R₂

2.2 nF

0.1 mF

40.2 kW

RESP_MODP

IN2P

Left Arm Lead

IN2N

RESP_MODN

Right Arm Lead

C₆

C₄

R₁

2.2 nF

0.1 mF

40.2 kW

R₄

C₅

2.2 nF

10 MW

AVDD

AVSS

R₃

IN1N

10 MW

NOTE: Patient and input protection circuitry not shown.

Figure 56. Typical Respiration Circuitry

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Figure 57 shows a respiration test circuit. Figure 58 and Figure 59 plot noise on channel 1 for the ADS1292R as

baseline impedance, gain, and phase are swept. The x-axis is the baseline impedance, normalized to a 30-µA

modulation current (as shown in Equation 11).

10

Data Rate = 125Hz

Respiration Modulation Clock = 32kHz

ADS1292R

9

IN1P

8

R₂

7

40.2 kW

RESP_MODP

6

5

R_BASELINE= 2.21 kW

4

PGA=3, PHASE = 112.5

3

2

1

RESP_MODN

IN1N

PGA = 4, PHASE = 112.5

PGA = 3, PHASE = 135

PGA = 4, PHASE = 135

R₂

40.2 kW

2.2

5.2

8.2

11.2

14.2

Normalized Baseline Respiration Impedance (kΩ)

G058

Figure 57. Respiration Noise Test Circuit

Figure 58. Channel 1 Noise versus Impedance for

32-kHz Modulation Clock and Phase

(BW = 32 Hz, Respiration Modulation Clock = 32

kHz)

15

Data Rate = 125Hz

Respiration Modulation Clock = 64kHz

14

13

12

11

10

9

8

7

6

5

4

3

2

PGA=2, PHASE = 135

PGA = 3, PHASE = 135

PGA = 2, PHASE = 157.5

PGA = 3, PHASE = 157.5

1

2.2

7.2

12.2

15

Normalized Baseline Respiration Impedance (kΩ)

G059

Figure 59. Channel 1 Noise versus Impedance for 64-kHz Modulation Clock and Phase

(BW = 32 Hz, Respiration Modulation Clock = 64 kHz)

R_ACTUAL´ I_ACTUAL

R_NORMALIZED

=

30 mA

where:

R_ACTUALis the baseline body impedance,

I_ACTUALis the modulation current, as calculated by (VREFP – AVSS) divided by the impedance of the

modulation circuit.

(11)

For example, if modulation frequency = 32 kHz, R_ACTUAL= 3 kΩ, I_ACTUAL= 50 µA, and R_NORMALIZED= (3 kΩ × 50

µA)/29 µA = 5.1 kΩ.

Referring to Figure 58 and Figure 59, it can be noted that gain = 4 and phase = 112.5° yield the best

performance at 4.6 µV_PP. Low-pass filtering this signal with a high-order 2-Hz cutoff can reduce the noise to less

than 1200 nV_PP. The impedance resolution is 1200 nV_PP/30 µA = 40 mΩ.

When the modulation frequency is 32 kHz, gains of 3 and 4 and phase of 112.5° and 135° are recommended.

When the modulation frequency is 64 kHz, gains of 2 and 3 and phase of 135° and 157° are recommended for

best performance.

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QUICK-START GUIDE

PCB LAYOUT

Power Supplies and Grounding

The ADS1291, ADS1292, and ADS1292R have two supplies: AVDD and DVDD. AVDD should be as quiet as

possible. AVDD provides the supply to the charge pump block and has transients at f_CLK. It is important to

eliminate noise from AVDD that is non-synchronous with the ADS1291, ADS1292, and ADS1292R operation.

Each ADS1291, ADS1292, and ADS1292R supply should be bypassed with 10-μF and a 0.1-μF solid ceramic

capacitors. It is recommended that placement of the digital circuits (such as the DSP, microcontrollers, and

FPGAs) in the system is done such that the return currents on those devices do not cross the ADS1291,

ADS1292, and ADS1292R analog return path. The ADS1291, ADS1292, and ADS1292R can be powered from

unipolar or bipolar supplies.

The capacitors used for decoupling can be of the surface-mount, low-cost, low-profile multi-layer ceramic type. In

most cases the VCAP1 capacitor can also be a multi-layer ceramic, but in systems where the board is subjected

to high or low frequency vibration, it is recommend that a non-ferroelectric capacitor such as a tantalum or class

1 capacitor (for example, C0G or NPO) be installed. EIA class 2 and class 3 dielectrics (such as X7R, X5R, X8R,

and such) are ferroelectric. The piezoelectric property of these capacitors can appear as electrical noise coming

from the capacitor. When using internal reference, noise on the VCAP1 node results in performance degradation.

Connecting the Device to Unipolar (+3 V or +1.8 V) Supplies

Figure 60 illustrates the ADS1291, ADS1292, and ADS1292R connected to a unipolar supply. In this example,

the analog supply (AVDD) is referenced to analog ground (AVSS) and the digital supply (DVDD) is referenced to

digital ground (DGND).

+3 V

+1.8 V

0.1 mF

1 mF

0.1 mF

AVDD

DVDD

VREFP

VREFN

0.1 mF

10 mF

PGA1N

(1)

4.7 nF

VCAP1

VCAP2

PGA1P

Device

PGA2N

PGA2P

4.7 nF

1 mF

AVSS DGND

NOTE: Place the capacitors for supply, reference, VCAP1, and VCAP2 as close to the package as possible.

(1) When using the ADS1292R and the channel 1 respiration function, this capacitor must be 47 nF.

Figure 60. Single-Supply Operation

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Connecting the Device to Bipolar (±1.5 V or 1.8 V) Supplies

Figure 61 illustrates the ADS1291, ADS1292, and ADS1292R connected to a bipolar supply. In this example, the

analog supplies connect to the device analog supply (AVDD). This supply is referenced to the device analog

return (AVSS), and the digital supply (DVDD) is referenced to the device digital ground return (DGND).

+1.5 V

+1.8 V

1 mF

0.1 mF

1 mF

AVDD

DVDD

VREFP

0.1 mF

10 mF

VREFN

PGA1N

PGA1P

(1)

4.7 nF

-1.5 V

VCAP1

VCAP2

Device

PGA2N

PGA2P

4.7 nF

AVSS DGND

1 mF

0.1 mF

-1.5 V

NOTE: Place the capacitors for supply, reference, VCAP1, and VCAP2 as close to the package as possible.

(1) When using the ADS1292R and the channel 1 respiration function, this capacitor must be 47 nF.

Figure 61. Bipolar Supply Operation

Shielding Analog Signal Paths

As with any precision circuit, careful PCB layout ensures the best performance. It is essential to make short,

direct interconnections and avoid stray wiring capacitance—particularly at the analog input pins and AVSS.

These analog input pins are high-impedance and extremely sensitive to extraneous noise. The AVSS pin should

be treated as a sensitive analog signal and connected directly to the supply ground with proper shielding.

Leakage currents between the PCB traces can exceed the ADS1291, ADS1292, and ADS1292R input bias

current if shielding is not implemented. Digital signals should be kept as far as possible from the analog input

signals on the PCB.

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POWER-UP SEQUENCING

Before device power-up, all digital and analog inputs must be low. At the time of power-up, all of these signals

should remain low until the power supplies have stabilized, as shown in Figure 62. At this time, begin supplying

the master clock signal to the CLK pin. Wait for time t_POR, then transmit a RESET pulse. After releasing RESET,

the configuration register must be programmed, see the CONFIG1: Configuration Register 1 subsection of the

Register Map section for details. The power-up sequence timing is shown in Table 17.

t_POR

Power Supplies

t_RST

RESET

Start Using the Device

18 t_CLK

Figure 62. Power-Up Timing Diagram

Table 17. Power-Up Sequence Timing

SYMBOL

t_POR

DESCRIPTION

Wait after power-up until reset

Reset low width

MIN

2¹²

1

TYP

MAX

UNIT

t_MOD

t_RST

SETTING THE DEVICE FOR BASIC DATA CAPTURE

This section outlines the procedure to configure the device in a basic state and capture data. This procedure is

intended to put the device in a data sheet condition to check if the device is working properly in the user's

system. It is recommended that this procedure be followed initially to get familiar with the device settings. Once

this procedure has been verified, the device can be configured as needed. For details on the timings for

commands refer to the appropriate sections in the data sheet. Also, some sample programming codes are added

for the ECG-specific functions. Figure 63 details a flow chart of the configuration procedure.

Lead-Off

Sample code to set dc lead-off with current source or sink resistors on all channels

WREG LOFF 10h // Comparator threshold at 95% and 5%, current source or sink resistor // DC lead-off

WREG CONFIG2 E0h // Turn-on dc lead-off comparators

WREG LOFF_SENS 0Fh // Turn on both P- and N-side of all channels for lead-off sensing

Observe the status bits of the output data stream to monitor lead-off status.

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// Follow Power-Up Sequencing

Analog/Digital Power-Up

Set CLKSEL Pin = 0 and

Provide External Clock

f_CLK= 512 kHz

Yes

External

Clock

No

Set CLKSEL Pin = 1

and Wait for Oscillator

to Wake Up

// If START is Tied High, After This Step

// DRDY Toggles at f_MOD/256

Set PWDN/RESET = 1

Wait for 1 s for

// Delay for Power-On Reset and Oscillator Start-Up

Power-On Reset

// Activate DUT

Issue Reset Pulse,

Wait for 18 t_CLKs

//CS can be Either Tied Permanently Low

// Or Selectively Pulled Low Before Sending

// Commands or Reading/Sending Data From/To Device

// Device Wakes Up in RDATAC Mode, so Send

// SDATAC Command so Registers can be Written

SDATAC

Send SDATAC

Command

No

Set PDB_REFBUF = 1

and Wait for Internal

Reference To Settle

// If Using Internal Reference, Send This Command

-- WREG CONFIG2 A0h

External Reference

Yes

// DRATE = 500 SPS

Write Certain Registers,

Including Input Short

WREG CONFIG1 02h

// Set All Channels to Input Short

WREG CHnSET 01h

// Activate Conversion

Set START = 1

RDATAC

// After This Point DRDY Should Toggle at

// f_CLKReview

// Put the Device Back in RDATAC Mode

RDATAC

Capture Data and

Check Noise

// Look for DRDY and Issue 24 + n 24 SCLKs

// Activate a (1 mV V_REF/2.4) Square-Wave Test Signal

// On All Channels

SDATAC

WREG CONFIG2 A3h

WREG CHnSET 05h

RDATAC

Set Test Signals

Capture Data and

Test Signals

// Look for DRDY and Issue 24 + n 24 SCLKs

Figure 63. Initial Flow at Power-Up

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REVISION HISTORY

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Original (December 2011) to Revision A

Page

•

Changed device graphic ....................................................................................................................................................... 1

Changed device status from Mixed Status to Production Data ............................................................................................ 1

Changed second Features bullet .......................................................................................................................................... 1

Updated Family and Ordering Information table ................................................................................................................... 2

Moved ADS1292R to production status ................................................................................................................................ 2

Deleted footnote 2 from Family and Ordering Information table .......................................................................................... 2

Changed values of AVDD to AVSS and DVDD to DGND rows in Absolute Maximum Ratings table .................................. 2

Changed Operating temperature range parameter in Absolute Maximum Ratings table ..................................................... 2

Changed DC Channel Performance, INL parameter test conditions in Electrical Characteristics table .............................. 3

Changed AC Channel Performance, SNR and THD parameters test conditions in Electrical Characteristics table ........... 3

Added third Channel Performance, THD parameter row to Electrical Characteristics table ................................................ 3

Added Digital Filter section to Electrical Characteristics table .............................................................................................. 4

Deleted Right Leg Drive Amplifier, Quiescent power consumption parameter test condition from Electrical

Characteristics table ............................................................................................................................................................. 4

•

Changed Respiration, Impedance measurement noise parameter test conditions in Electrical Characteristics table ......... 4

Changed Respiration, Maximum modulator current parameter in Electrical Characteristics table ...................................... 4

Changed Power-Supply Requirements, Digital supply parameter in Electrical Characteristics table .................................. 5

Changed first I_DVDDSupply Current, Normal mode parameter test conditions in Electrical Characteristics table ................ 6

Changed 3-V Power Dissipation, Quiescent power dissipation, per channel parameter typical specifications in

Electrical Characteristics table .............................................................................................................................................. 6

•

Added C_FILTERto Typical Characteristics conditions ........................................................................................................... 13

Updated Figure 5 ................................................................................................................................................................ 13

Updated Figure 9 and Figure 12 ......................................................................................................................................... 14

Added C_FILTERto Typical Characteristics conditions ........................................................................................................... 14

Added C_FILTERto Typical Characteristics conditions ........................................................................................................... 15

Changed description of CHnSET setting in Supply Measurements (MVDDP, MVDDN) section ....................................... 19

Changed second paragraph of PGA Settings and Input Range section ............................................................................ 21

Changed description of PD_REFBUF bit in the Reference section ................................................................................... 25

Updated second column title in Table 9 ............................................................................................................................. 26

Updated Figure 41 .............................................................................................................................................................. 33

Updated description of DOUT and DRDY in RDATAC: Read Data Continuous section ................................................... 35

Updated RLD_STAT in address 08h of Table 14 ............................................................................................................... 38

Changed description of bit 1 in CONFIG2: Configuration Register 2 ................................................................................. 40

Changed descriptions of bits[3:0] in CH2SET: Channel 2 Settings .................................................................................... 43

Updated Figure 54 .............................................................................................................................................................. 56

Added description of Figure 55, Figure 55, and Table 16 to Internal Respiration Circuitry with External Clock

(ADS1292R) section ........................................................................................................................................................... 57

•

Added ADS1292R Application section ............................................................................................................................... 57

Updated Figure 58 and Figure 59 ....................................................................................................................................... 58

Updated Figure 60 and added footnote 1 ........................................................................................................................... 59

Updated Figure 61 and added footnote 1 ........................................................................................................................... 60

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TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

ADS1291IPBSR

ADS1292IPBSR

ADS1292RIPBSR

TQFP

PBS

32

1000

330.0

16.4

7.2

1.5

12.0

16.0

Q2

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

10-Mar-2012

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

ADS1291IPBSR

ADS1292IPBSR

ADS1292RIPBSR

TQFP

PBS

32

1000

346.0

33.0

Pack Materials-Page 2

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型号：	ADS1292I
厂家：	TEXAS INSTRUMENTS
描述：	Low-Power, 2-Channel, 24-Bit Analog Front-End for Biopotential Measurements 低功耗，双通道， 24位模拟前端的生物电位测量
文件：	总69页 (文件大小：1524K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ADS1292I [TI]

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