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ADS1299, ADS1299-4, ADS1299-6

ZHCS158C –JULY 2012–REVISED JANUARY 2017

ADS1299-x 适用于 EEG 和生物电势测量的低噪声 4 通道、6 通道、8 通

道、24 位模数转换器

1 特性

ADS1299-x 在每条通道中配有一个灵活的输入多路复

用器，该复用器可与内部生成的信号独立相连，完成测

试、温度和导联断开检测。此外，可选择输入通道的任

一配置生成患者偏置输出信号。提供可选 SRB 引脚，

旨在将公共信号路由至参考蒙太奇配置的多路输入。

ADS1299-x 以 250SPS 至 16kSPS 的数据传输速率运

行。可通过激励电流阱/电流源在器件内部实现导联断

开检测。

1

•

多达 8 个低噪声可编程增益放大器 (PGA) 和 8 个

高分辨率同步采样模数转换器 (ADC)

输入参考噪声：1 μV_PP（带宽为 70Hz）

输入偏置电流：300pA

•

数据速率：250 每秒采样率 (SPS) 至 16 每秒千次

采样 (kSPS)

•

共模抑制比 (CMRR)：-110dB

可编程增益：1，2，4，6，8，12 或者 24

单极或者双极电源：

可在通道较多的系统中采用菊花链配置串联多个

ADS1299-4、ADS1299-6 或 ADS1299 器件。

ADS1299-x 采用 TQFP-64 封装，工作温度介于

–40°C 至 +85°C 之间。

–

模拟：4.75V 至 5.25V

数字：1.8V 至 3.6V

•

内置偏置驱动放大器，

持续断线检测，测试信号

器件信息⁽¹⁾

•

内置振荡器

器件型号

ADS1299-x

封装

封装尺寸（标称值）

内部或者外部基准

TQFP (64)

10.00mm x 10.00mm

灵活的省电、待机模式

与ADS129x 引脚兼容

兼容串行外设接口 (SPI) 的串行接口

工作温度范围：-40°C 至 +85°C

(1) 要了解所有可用封装，请参见数据表末尾的可订购产品附录。

方框图

REF

Test Signals and

Monitors

Reference

ADC1

2 应用

SPI

A1

A2

A3

A4

•

医疗器械，包括：

ADC2

–

脑电图 (EEG) 研究

胎儿心电图 (ECG)

睡眠研究监视器

ADC3

Oscillator

ADC4

MUX

Control

A5

A6

ADC5

ADC6

双谱指数 (BIS)

诱发音频电位 (EAP)

A7

A8

ADC7

ADC8

3 说明

ADS1299-4、ADS1299-6 和 ADS1299 器件是一系列

四通道、六通道和八通道低噪声、24 位同步采样 Δ-Σ

模数转换器(ADC)系列产品。该系列内置可编程增益放

大器 (PGA)、内部基准以及板载振荡器。ADS1299-x

具备颅外脑电图 (EEG) 和心电图 (ECG) 应用所需的

全部常用功能。凭借高集成度和出色性能，ADS1299-

x 能够以大幅缩小的尺寸、显著降低的功耗和整体成本

构建可扩展的医疗仪器系统。

To Channel

¼

PATIENT BIAS AND REFERENCE

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

English Data Sheet: SBAS499

ADS1299, ADS1299-4, ADS1299-6

ZHCS158C –JULY 2012–REVISED JANUARY 2017

www.ti.com.cn

9.5 Programming........................................................... 38

9.6 Register Maps......................................................... 44

10 Applications and Implementation...................... 61

10.1 Application Information.......................................... 61

10.2 Typical Application ................................................ 66

11 Power Supply Recommendations ..................... 70

11.1 Power-Up Sequencing .......................................... 70

1

2

3

4

5

6

7

特性.......................................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

Device Comparison ............................................... 5

Pin Configuration and Functions......................... 5

Specifications......................................................... 7

7.1 Absolute Maximum Ratings ...................................... 7

7.2 ESD Ratings.............................................................. 7

7.3 Recommended Operating Conditions....................... 8

7.4 Thermal Information.................................................. 8

7.5 Electrical Characteristics........................................... 9

7.6 Timing Requirements: Serial Interface.................... 12

7.7 Switching Characteristics: Serial Interface.............. 12

7.8 Typical Characteristics............................................ 13

Parametric Measurement Information ............... 16

8.1 Noise Measurements .............................................. 16

Detailed Description ............................................ 18

9.1 Overview ................................................................. 18

9.2 Functional Block Diagram ....................................... 19

9.3 Feature Description................................................. 20

9.4 Device Functional Modes........................................ 34

11.2 Connecting the Device to Unipolar (5 V and 3.3 V)

Supplies ................................................................... 70

11.3 Connecting the Device to Bipolar (±2.5 V and 3.3 V)

Supplies ................................................................... 71

12 Layout................................................................... 72

12.1 Layout Guidelines ................................................. 72

12.2 Layout Example .................................................... 72

13 器件和文档支持 ..................................................... 74

13.1 文档支持................................................................ 74

13.2 相关链接................................................................ 74

13.3 接收文档更新通知 ................................................. 74

13.4 社区资源................................................................ 74

13.5 商标....................................................................... 74

13.6 静电放电警告......................................................... 74

13.7 Glossary................................................................ 74

14 机械、封装和可订购信息....................................... 75

8

9

4 修订历史记录

注：之前版本的页码可能与当前版本有所不同。

Changes from Revision B (October 2016) to Revision C

Page

•

Changed Maximum Junction parameter name to Junction in Absolute Maximum Ratings table .......................................... 7

Changed Recommended Operating Conditions table: changed free-air to ambient in conditions statement, changed

specifications of Input voltage parameter, and added V_CMand f_CLKsymbols ........................................................................ 8

•

Changed conditions statement of Electrical Characteristics table: added T_Ato temperature conditions, moved DVDD

condition to after AVDD – AVSS condition ............................................................................................................................ 9

•

Changed Input bias current parameter test conditions from input to InxP and INxN............................................................. 9

Changed Drift parameter unit from ppm to ppm/°C and changed Internal clock accuracy parameter test conditions

from –40°C ≤ T_A≤ +85°C to T_A= –40°C to +85°C in Electrical Characteristics table ......................................................... 10

•

Changed I_AVDDand I_DVDDparameters [deleted (normal mode) from parameter names and added Normal mode to

test conditions], and deleted Quiescent from Power dissipation parameter name in Electrical Characteristics table ......... 11

•

Changed free-air to ambient in conditions statement of Timing Requirements: Serial Interface table ................................ 12

Changed Analog Input section ............................................................................................................................................ 22

Changed Table 9 cross-reference to Table 7 in Settling Time section ................................................................................ 34

Changed Ideal Output Code versus Input Signal table: changed all V_REFin first column to FS in and deleted footnote

1 ........................................................................................................................................................................................... 38

•

Changed reset settings of bits 4 and 3 in bit register of CONFIG1 register......................................................................... 46

Changed reset value settings of bits 7 to 5 in CONFIG2 register: split cells apart.............................................................. 47

Changed reset value settings of bits 6 to 5 in CONFIG3 register: split cells apart ............................................................. 48

Changed AVDD – AVSS to AVDD + AVSS in description of bit 3 in Configuration Register 3 Field Descriptions ............. 48

Changed Lead-Off Control Register Field Descriptions table: changed 01 bit setting of bits 3:2 to 24 nA from 12 nA

changed description of bits 1:0............................................................................................................................................. 49

•

Changed Unused Inputs and Outputs section: added DRDY description, deleted statement of not floating unused

digital inputs ......................................................................................................................................................................... 61

2

ADS1299, ADS1299-4, ADS1299-6

www.ti.com.cn

ZHCS158C –JULY 2012–REVISED JANUARY 2017

修订历史记录 (接下页)

•

Deleted second Layout Guidelines sub-section from Layout section .................................................................................. 72

Changes from Revision A (August 2012) to Revision B

Page

•

已添加 ESD 额定值表，特性描述部分，器件功能模式，应用和实施部分，电源相关建议部分，布局部分，器件和文

档支持部分以及机械、封装和可订购信息部分........................................................................................................................ 1

已添加 ADS1299-4 和 ADS1299-6 至文档 ............................................................................................................................. 1

已添加 .................................................................................................................................................................................... 1

已删除低功耗特性要点.......................................................................................................................................................... 1

已更改颅外脑电图 (EEG)（位于应用和说明部分................................................................................................................ 1

已删除最后一个应用要点 ....................................................................................................................................................... 1

已更改说明部分：已添加有关 SRB 引脚的句子，已更改第二段的最后一句 ......................................................................... 1

已更改通篇文档中的 ADS1299 系列器件至 ADS1299-x ....................................................................................................... 1

已更改框图：已添加虚线框 ................................................................................................................................................... 1

Changed specifications for Lead-Off Detect, Frequency parameter of Electrical Characteristics table............................... 10

•

Added specifications for ADS1299-4 and ADS1299-6 in Supply Current (Bias Turned Off) and Power Dissipation

(Analog Supply = 5 V, Bias Amplifiers Turned Off) sections of Electrical Characteristics table .......................................... 11

•

Changed Noise Measurements section................................................................................................................................ 16

Changed Functional Block Diagram to show channels 5-8 not covered in ADS1299-4 and channels 7-8 not covered

in ADS1299-6 ....................................................................................................................................................................... 19

•

Changed INxP and INxN pins in Figure 18 ......................................................................................................................... 20

Changed Figure 23: changed PgaP, PgaN to PGAp, PGAn ............................................................................................... 23

Changed Input Common-Mode Range section: changed input common-mode range description .................................... 23

Changed differential input voltage range in the Input Differential Dynamic Range section ................................................. 24

Changed Figure 34: MUX8[2:0] = 010 on IN8N, and BIAS_MEAS = 1 on BIASIN ............................................................. 29

Changed first sentence of second paragraph in Lead-Off Detection section....................................................................... 30

Changed AC Lead-Off (One Time or Periodic) section........................................................................................................ 31

Changed Bias Lead-Off section............................................................................................................................................ 32

Changed title of Figure 38 and power-down description in Bias Drive (DC Bias Circuit) section........................................ 33

Changed START Opcode to START in Figure 39................................................................................................................ 34

Changed Reset (RESET) section for clarity ......................................................................................................................... 35

Changed title, first paragraph, START Opcode and STOP Opcode to START and STOP (Figure 42), and STOP

Opcode to STOP Command (Figure 43) in Continuous Conversion Mode section............................................................. 36

•

Added last sentence to Data Input (DIN) section ................................................................................................................. 39

Added cross-reference to the Sending Multi-Byte Commands section in RDATAC: Read Data Continuous section ........ 41

Changed RDATAC Opcode to RDATAC in Figure 46.......................................................................................................... 41

Changed RDATA Opcode to RDATA in Figure 46............................................................................................................... 42

Changed description of SCLK rate restrictions, OPCODE 1 and OPCODE 2 to BYTE 1 and BYTE 2 in Figure 48 of

RREG: Read From Register section .................................................................................................................................... 43

•

Changed footnotes 1 and 2 and added more cross-references to footnotes in rows 0Dh to 11h in Table 11 ................... 44

Changed register description and description of bit 5 in MISC1: Miscellaneous 1 Register section ................................... 59

Changed output names in Figure 68 from RA, LA, and RL to Electrode 1, Electrode 2, and BIAS Electrode,

respectively........................................................................................................................................................................... 63

•

Changed Power-Up Sequencing section.............................................................................................................................. 70

3

ADS1299, ADS1299-4, ADS1299-6

ZHCS158C –JULY 2012–REVISED JANUARY 2017

www.ti.com.cn

Changes from Original (July 2012) to Revision A

Page

•

已更改器件系列和订购信息表的产品栏 ................................................................................................................................. 1

4

ADS1299, ADS1299-4, ADS1299-6

www.ti.com.cn

ZHCS158C –JULY 2012–REVISED JANUARY 2017

5 Device Comparison

OPERATING

TEMPERATURE

RANGE

PACKAGE

MAXIMUM

SAMPLING RATE

PRODUCT

ADS1299-4

ADS1299-6

ADS1299

OPTIONS

TQFP-64

CHANNELS

ADC RESOLUTION

–40°C to +85°C

4

6

8

24

16 kSPS

6 Pin Configuration and Functions

PAG Package

64-Pin TQFP

Top View

IN8N

IN8P

IN7N

IN7P

IN6N

IN6P

IN5N

IN5P

IN4N

1

2

3

4

5

6

7

8

9

48 DVDD

47 DRDY

46 GPIO4

45 GPIO3

44 GPIO2

43 DOUT

42 GPIO1

41 DAISY_IN

40 SCLK

39 CS

IN4P 10

IN3N 11

IN3P 12

IN2N 13

IN2P 14

IN1N 15

IN1P 16

38 START

37 CLK

36 RESET

35 PWDN

34 DIN

33 DGND

5

ADS1299, ADS1299-4, ADS1299-6

ZHCS158C –JULY 2012–REVISED JANUARY 2017

www.ti.com.cn

Pin Functions

TYPE

DESCRIPTION

NAME

NO.

19, 21, 22, 56, 59

Supply

Analog supply. Connect a 1-μF capacitor to AVSS.

AVDD

59

Charge pump analog supply. Connect a 1-μF capacitor to AVSS, pin 58.

Analog supply. Connect a 1-μF capacitor to AVSS1.

Analog ground

AVDD1

AVSS

54

Supply

20, 23, 32, 57

Supply

58

53

Supply

Analog ground for charge pump

Analog ground

AVSS1

BIASIN

BIASINV

BIASOUT

BIASREF

CS

Supply

62

Analog input

Analog input/output

Analog output

Analog input

Digital input

Supply

Bias drive input to MUX

61

Bias drive inverting input

Bias drive output

63

60

Bias drive noninverting input

Chip select, active low

39

CLK

37

Master clock input

Master clock select⁽¹⁾

CLKSEL

DAISY_IN

DGND

DIN

52

41

Daisy-chain input

33, 49, 51

34

Digital ground

Digital input

Digital output

Supply

Serial data input

DOUT

43

Serial data output

DRDY

47

Data ready, active low

DVDD

48, 50

Digital power supply. Connect a 1-μF capacitor to DGND.

General-purpose input/output pin 1.

Connect to DGND with a ≥10-kΩ resistor if unused.

GPIO1

GPIO2

GPIO3

GPIO4

42

44

45

46

Digital input/output

General-purpose input/output pin 2.

Connect to DGND with a ≥10-kΩ resistor if unused.

General-purpose input/output pin 3.

Connect to DGND with a ≥10-kΩ resistor if unused.

General-purpose input/output pin 4.

Connect to DGND with a ≥10-kΩ resistor if unused.

IN1N

IN1P

IN2N

IN2P

IN3N

IN3P

IN4N

IN4P

IN5N

IN5P

IN6N

IN6P

IN7N

IN7P

IN8N

IN8P

NC

15

16

13

14

11

12

9

Analog input

—

Differential analog negative input 1⁽²⁾

Differential analog positive input 1⁽²⁾

Differential analog negative input 2⁽²⁾

Differential analog positive input 2⁽²⁾

Differential analog negative input 3⁽²⁾

Differential analog positive input 3⁽²⁾

Differential analog negative input 4⁽²⁾

Differential analog positive input 4⁽²⁾

Differential analog negative input 5⁽²⁾(ADS1299-6 and ADS1299 only)

Differential analog positive input 5⁽²⁾(ADS1299-6 and ADS1299 only)

Differential analog negative input 6⁽²⁾(ADS1299-6 and ADS1299 only)

Differential analog positive input 6⁽²⁾(ADS1299-6 and ADS1299 only)

Differential analog negative input 7⁽²⁾(ADS1299 only)

Differential analog positive input 7⁽²⁾(ADS1299 only)

Differential analog negative input 8⁽²⁾(ADS1299 only)

Differential analog positive input 8⁽²⁾(ADS1299 only)

No connection, leave as open circuit

10

7

8

5

6

3

4

1

2

27, 29

64

36

31

40

17

18

Reserved

RESET

RESV1

SCLK

SRB1

SRB2

Analog output

Digital input

Analog input/output

Reserved for future use, leave as open circuit

System reset, active low

Reserved for future use, connect directly to DGND

Serial clock input

Patient stimulus, reference, and bias signal 1

Patient stimulus, reference, and bias signal 2

(1) Set the two-state mode setting pins high to DVDD or low to DGND through ≥10-kΩ resistors.

(2) Connect unused analog inputs directly to AVDD.

6

ADS1299, ADS1299-4, ADS1299-6

www.ti.com.cn

ZHCS158C –JULY 2012–REVISED JANUARY 2017

Pin Functions (continued)

TYPE

DESCRIPTION

NAME

START

NO.

38

Digital input

Synchronization signal to start or restart a conversion

PWDN

35

Power-down, active low

VCAP1

28

Analog output

Analog bypass capacitor pin. Connect a 100-μF capacitor to AVSS.

Analog bypass capacitor pin. Connect a 1-μF capacitor to AVSS.

VCAP2

30

Analog bypass capacitor pin. Connect a parallel combination of 1-μF and 0.1-μF

capacitors to AVSS.

VCAP3

55

Analog output

VCAP4

VREFN

VREFP

26

25

24

Analog output

Analog input

Analog bypass capacitor pin. Connect a 1-μF capacitor to AVSS.

Negative analog reference voltage.

Analog input/output

Positive analog reference voltage. Connect a minimum 10-μF capacitor to VREFN.

7 Specifications

7.1 Absolute Maximum Ratings⁽¹⁾

MIN

–0.3

MAX

5.5

UNIT

AVDD to AVSS

DVDD to DGND

AVSS to DGND

–0.3

3.9

–3

0.2

Voltage

VREFP to AVSS

–0.3

AVDD + 0.3

DVDD + 0.3

10

V

VREFN to AVSS

–0.3

Analog input

AVSS – 0.3

DGND – 0.3

–10

Digital input

Current

Input, continuous, any pin except power supply pins⁽²⁾

mA

°C

Junction, T_J

Storage, T_stg

150

Temperature

–60

150

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) Input pins are diode-clamped to the power-supply rails. Limit the input current to 10 mA or less if the analog input voltage exceeds

AVDD + 0.3 V or is less than AVSS – 0.3 V, or if the digital input voltage exceeds DVDD + 0.3 V or is less than DGND – 0.3 V.

7.2 ESD Ratings

VALUE

±1000

±500

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾

V_(ESD)

Electrostatic discharge

V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7

ADS1299, ADS1299-4, ADS1299-6

ZHCS158C –JULY 2012–REVISED JANUARY 2017

www.ti.com.cn

7.3 Recommended Operating Conditions

over operating ambient temperature range (unless otherwise noted)

MIN

NOM

MAX

UNIT

POWER SUPPLY

Analog power supply

Digital power supply

Analog to Digital supply

AVDD to AVSS

DVDD to DGND

AVDD – DVDD

4.75

1.8

5

5.25

3.6

V

1.8

–2.1

3.6

ANALOG INPUTS

Full-scale differential input

voltage

V_INxP– V_INxN

±V_REF/ gain

V

See the Input Common-Mode Range

V_CM

Input common-mode range

(V_INxP+ V_INxN) / 2

subsection of the PGA Settings and Input

Range section

VOLTAGE REFERENCE INPUTS

V_REF

Reference input voltage

Negative input

V_REF= (V_VREFP– V_VREFN

)

4.5

AVSS

V

VREFN

VREFP

Positive input

AVSS + 4.5

CLOCK INPUT

f_CLK

External clock input frequency CLKSEL pin = 0

1.5

DGND – 0.1

–40

2.048

2.25

DVDD + 0.1

85

MHz

V

DIGITAL INPUTS

Input voltage

TEMPERATURE RANGE

T_A

Operating temperature range

°C

7.4 Thermal Information

ADS1299-4, ADS1299-6, ADS1299

THERMAL METRIC⁽¹⁾

PAG (TQFP)

64 PINS

46.2

UNIT

R_θJA

Junction-to-ambient thermal resistance

°C/W

R_θJC(top)

R_θJB

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

5.8

19.6

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

0.2

ψ_JB

19.2

R_θJC(bot)

n/a

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

8

ADS1299, ADS1299-4, ADS1299-6

www.ti.com.cn

ZHCS158C –JULY 2012–REVISED JANUARY 2017

7.5 Electrical Characteristics

Minimum and maximum specifications apply from T_A= –40°C to 85°C. Typical specifications are at T_A= +25°C. All

specifications are at AVDD – AVSS = 5 V, DVDD = 3.3 V, V_REF= 4.5 V, external f_CLK= 2.048 MHz, data rate = 250 SPS, and

gain = 12 (unless otherwise noted)

PARAMETER

ANALOG INPUTS

Input capacitance

TEST CONDITIONS

MIN

TYP

MAX

UNIT

20

pF

pA

T_A= +25°C, InxP and INxN = 2.5 V

±300

Input bias current

T_A= –40°C to +85°C, InxP and INxN = 2.5

V

±300

500

No lead-off

1000

DC input impedance

MΩ

Current source lead-off detection

(I_LEADOFF= 6 nA)

PGA PERFORMANCE

Gain settings

Bandwidth

1, 2, 4, 6, 8, 12, 24

See Table 5

BW

ADC PERFORMANCE

Resolution

24

250

Bits

DR

Data rate

f_CLK= 2.048 MHz

16000

SPS

DC CHANNEL PERFORMANCE

10 seconds of data, gain = 24⁽¹⁾

1

250 points, 1 second of data, gain = 24,

T_A= +25°C

1.35

1.6

μV_PP

Input-referred noise (0.01 Hz to 70 Hz)

250 points, 1 second of data, gain = 24,

T_A= –40°C to +85°C

1

All other sample rates and gain settings

Full-scale with gain = 12, best fit

See Noise Measurements

INL

Integral nonlinearity

8

60

80

0.1

3

ppm

μV

Offset error

Offset error drift

Gain error

nV/°C

% of FS

ppm/°C

% of FS

Excluding voltage reference error

Excluding voltage reference drift

±0.5

Gain drift

Gain match between channels

0.2

AC CHANNEL PERFORMANCE

CMRR

PSRR

Common-mode rejection ratio

f_CM= 50 Hz and 60 Hz⁽²⁾

–110

–120

96

dB

Power-supply rejection ratio

Crosstalk

f_PS= 50 Hz and 60 Hz

f_IN= 50 Hz and 60 Hz

–110

121

–99

SNR

THD

Signal-to-noise ratio

Total harmonic distortion

V_IN= –2 dBFs, f_IN= 10-Hz input, gain = 12

V_IN= –0.5 dBFs, f_IN= 10 Hz

PATIENT BIAS AMPLIFIER

Integrated noise

BW = 150 Hz

2

100

0.07

–80

μV_RMS

kHz

V/μs

dB

Gain bandwidth product

50-kΩ || 10-pF load, gain = 1

f_IN= 10 Hz, gain = 1

Slew rate

THD

Total harmonic distortion

Common-mode input range

Short-circuit current

AVSS + 0.3

AVDD – 0.3

V

1.1

20

mA

μA

Quiescent power consumption

(1) Noise data measured in a 10-second interval. Test not performed in production. Input-referred noise is calculated with the input shorted

(without electrode resistance) over a 10-second interval.

(2) CMRR is measured with a common-mode signal of AVSS + 0.3 V to AVDD – 0.3 V. The values indicated are the minimum of the eight

channels.

9

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Electrical Characteristics (continued)

Minimum and maximum specifications apply from T_A= –40°C to 85°C. Typical specifications are at T_A= +25°C. All

specifications are at AVDD – AVSS = 5 V, DVDD = 3.3 V, V_REF= 4.5 V, external f_CLK= 2.048 MHz, data rate = 250 SPS, and

gain = 12 (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

LEAD-OFF DETECT

At dc, f_DR/ 4,

see Register Maps for settings

Continuous

Frequency

Current

Hz

One time or periodic

ILEAD_OFF[1:0] = 00

ILEAD_OFF[1:0] = 01

ILEAD_OFF[1:0] = 10

ILEAD_OFF[1:0] = 11

7.8, 31.2

6

24

nA

6

μA

24

Current accuracy

±20%

±30

Comparator threshold accuracy

mV

kΩ

V

EXTERNAL REFERENCE

Input impedance

5.6

INTERNAL REFERENCE

V_REF

Internal reference voltage

4.5

±0.2%

35

V_REFaccuracy

Drift

T_A= –40°C to +85°C

ppm/°C

ms

Start-up time

150

SYSTEM MONITORS

Analog supply

Digital supply

2%

Reading error

2%

From power-up to DRDY low

STANDBY mode

150

ms

µs

Device wake up

31.25

Voltage

T_A= +25°C

145

490

mV

μV/°C

Hz

Temperature

sensor reading

Coefficient

f_CLK/ 2²¹, f_CLK/ 2²⁰

±1, ±2

Signal frequency

Signal voltage

Accuracy

See Register Maps section for settings

Test signal

mV

±2%

CLOCK

Internal oscillator clock frequency

Nominal frequency

T_A= +25°C

2.048

MHz

±0.5%

±2.5%

Internal clock accuracy

T_A= –40°C to +85°C

Internal oscillator start-up time

Internal oscillator power consumption

20

μs

120

μW

DIGITAL INPUT/OUTPUT (DVDD = 1.8 V to 3.6 V)

V_IH

V_IL

High-level input voltage

Low-level input voltage

High-level output voltage

Low-level output voltage

Input current

0.8 DVDD

–0.1

DVDD + 0.1

0.2 DVDD

V

V_OH

V_OL

I_OH= –500 μA

0.9 DVDD

V

I_OL= +500 μA

0.1 DVDD

10

V

0 V < V_DigitalInput< DVDD

–10

μA

10

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ZHCS158C –JULY 2012–REVISED JANUARY 2017

Electrical Characteristics (continued)

Minimum and maximum specifications apply from T_A= –40°C to 85°C. Typical specifications are at T_A= +25°C. All

specifications are at AVDD – AVSS = 5 V, DVDD = 3.3 V, V_REF= 4.5 V, external f_CLK= 2.048 MHz, data rate = 250 SPS, and

gain = 12 (unless otherwise noted)

PARAMETER

TEST CONDITIONS

Normal mode, AVDD – AVSS = 5 V

Normal mode, DVDD = 3.3 V

Normal mode, DVDD = 1.8 V

MIN

TYP

MAX

UNIT

SUPPLY CURRENT (Bias Turned Off)

ADS1299-4

4.06

5.57

7.14

0.54

0.66

1

I_AVDD

AVDD current

DVDD current

ADS1299-6

ADS1299

mA

ADS1299-4

ADS1299-6

ADS1299

I_DVDD

mA

ADS1299-4

ADS1299-6

ADS1299

0.27

0.34

0.5

POWER DISSIPATION (Analog Supply = 5 V, Bias Amplifiers Turned Off)

Normal mode

22

10

24

33

42

mW

µW

ADS1299-4

Power dissipation ADS1299-6

ADS1299

Power-down

Standby mode, internal reference

Normal mode

5.1

30

mW

µW

Power-down

10

Standby mode, internal reference

Normal mode

5.1

39

mW

µW

Power-down

10

Standby mode, internal reference

5.1

mW

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7.6 Timing Requirements: Serial Interface

over operating ambient temperature range (unless otherwise noted)

2.7 V ≤ DVDD ≤ 3.6 V 1.8 V ≤ DVDD ≤ 2.0 V

MIN

414

6

MAX

MIN

414

17

66.6

25

10

11

2

MAX

666

UNIT

ns

t_CLK

Master clock period

666

t_CSSC

Delay time, CS low to first SCLK

SCLK period

ns

t_SCLK

50

15

10

2

ns

t_{SPWH, L}

t_DIST

Pulse duration, SCLK pulse duration, high or low

Setup time, DIN valid to SCLK falling edge

Hold time, valid DIN after SCLK falling edge

Pulse duration, CS high

ns

t_DIHD

ns

t_CSH

t_CLK

ns

t_SCCS

Delay time, final SCLK falling edge to CS high

Command decode time

4

t_SDECODE

t_DISCK2ST

t_DISCK2HT

4

Setup time, DAISY_IN valid to SCLK rising edge

Hold time, DAISY_IN valid after SCLK rising edge

10

ns

7.7 Switching Characteristics: Serial Interface

over operating ambient temperature range (unless otherwise noted)

2.7 V ≤ DVDD ≤ 3.6 V 1.8 V ≤ DVDD ≤ 2.0 V

PARAMETER

MIN

MAX

MIN

MAX

UNIT

ns

t_DOHD

t_DOPD

t_CSDOD

t_CSDOZ

Hold time, SCLK falling edge to invalid DOUT

Propagation delay time, SCLK rising edge to DOUT valid

Propagation delay time, CS low to DOUT driven

Propagation delay time, CS high to DOUT Hi-Z

10

17

32

ns

10

20

ns

10

20

ns

t_CLK

CLK

t_CSSC

t_CSH

t_SDECODE

CS

t_SPWL

t_SCCS

t_SCLK

t_SPWH

SCLK

1

2

3

8

1

2

3

8

t_DIHD

t_DOHD

t_DIST

t_DOPD

DIN

t_CSDOZ

Hi-Z

t_CSDOD

Hi-Z

DOUT

NOTE: SPI settings are CPOL = 0 and CPHA = 1.

Figure 1. Serial Interface Timing

t_DISCK2ST

t_DISCK2HT

MSB_D1

LSB_D1

DAISY_IN

SCLK

1

2

3

216

217

218

219

MSB_D1

MSB

LSB

DOUT

Figure 2. Daisy-Chain Interface Timing

12

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7.8 Typical Characteristics

At T_A= 25°C, AVDD = 5 V, AVSS = 0 V, DVDD = 3.3 V, internal VREFP = 4.5 V, VREFN = AVSS, external clock = 2.048

MHz, data rate = 250 SPS, and gain = 12 (unless otherwise noted)

0.5

0.4

800

700

600

500

400

300

200

100

0

Gain = 24

0.3

0.2

0.1

0

−0.1

−0.2

−0.3

−0.4

−0.5

1

2

3

4

5

6

7

8

9

10

Time (s)

G003

Input−Referred Noise (µV)

G004

Figure 3. Input-Referred Noise

Figure 4. Noise Histogram

400

350

300

250

200

150

100

50

−100

−105

−110

−115

−120

−125

−130

−135

Data Rate = 4 kSPS

A_IN= AVDD − 0.3 V to AVSS + 0.3 V

Data Rate = 250 SPS to 8 kSPS

Data Rate = 16 kSPS

Gain = 1

Gain = 2

Gain = 4

Gain = 6

Gain = 8

Gain = 12

Gain = 24

0

10

100

1000

0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5

Frequency (Hz)

Input Voltage (V)

G005

G006

Figure 5. Common-Mode Rejection Ratio vs Frequency

Figure 6. Leakage Current vs Input Voltage

200

120

115

110

105

100

95

G = 1

G = 2

G = 4

G = 6

G = 8

G = 12

G = 24

175

150

125

100

75

50

90

Input Voltage = 2.5 V

Data Rate = 250 SPS to 8 kSPS

25

0

85

80

−40 −30 −20 −10

0

10 20 30 40 50 60 70 80 90

Temperature (°C)

10

100

Frequency (Hz)

1000

G007

G008

Figure 7. Leakage Current vs Temperature

Figure 8. PSRR vs Frequency

13

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Typical Characteristics (continued)

At T_A= 25°C, AVDD = 5 V, AVSS = 0 V, DVDD = 3.3 V, internal VREFP = 4.5 V, VREFN = AVSS, external clock = 2.048

MHz, data rate = 250 SPS, and gain = 12 (unless otherwise noted)

−60

−65

−70

−75

−80

−85

−90

−95

−100

−105

12

10

8

Gain = 1

Gain = 2

Gain = 4

Gain = 6

Gain = 8

Gain = 12

Gain = 24

Data Rate = 8 kSPS

A_IN= −0.5 dBFS

Gain = 1

Gain = 2

Gain = 4

Gain = 6

Gain = 8

Gain = 12

Gain = 24

6

4

2

0

−2

−4

−6

−8

−10

10

100

Frequency (Hz)

1000

−1 −0.8 −0.6 −0.4 −0.2

0

0.2 0.4 0.6 0.8

Input (Normalized to Full-Scale)

1

G009

G010

Figure 9. THD vs Frequency

Figure 10. INL vs PGA Gain

8

6

0

−20

Gain = 12

PGA Gain = 12

THD = −99 dB

SNR = 120 dB

Data Rate = 500 SPS

4

−40

2

−60

0

−80

−2

−4

−6

−8

−10

−100

−120

−140

−160

−180

+25°C

−40°C

+85°C

−1 −0.8 −0.6 −0.4 −0.2

0

0.2 0.4 0.6 0.8

1

0

50

100

150

200

250

Frequency (Hz)

Input Range (Normalized to Full−Scale)

G011

G012

Figure 11. INL vs Temperature

Figure 12. THD FFT Plot (60-Hz Signal)

0

−20

600

500

400

300

200

100

0

PGA Gain = 12

THD = −94 dB

SNR = 101 dB

−40

Data Rate = 16 kSPS

−60

−80

−100

−120

−140

−160

−180

0

2000

4000

6000

8000

1

10

30

Frequency (Hz)

PGA Gain

G013

G014

Figure 13. FFT Plot (60-Hz Signal)

Figure 14. Offset vs PGA Gain (Absolute Value)

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ZHCS158C –JULY 2012–REVISED JANUARY 2017

Typical Characteristics (continued)

At T_A= 25°C, AVDD = 5 V, AVSS = 0 V, DVDD = 3.3 V, internal VREFP = 4.5 V, VREFN = AVSS, external clock = 2.048

MHz, data rate = 250 SPS, and gain = 12 (unless otherwise noted)

70

60

50

40

30

20

10

0

80

70

60

50

40

30

20

10

0

Data From 31 Devices, Two Lots

Error (%)

G015

Threshold Error (mV)

G016

Figure 15. Test Signal Amplitude Accuracy

Figure 16. Lead-Off Comparator Threshold Accuracy

350

Current Setting = 24 nA

300

250

200

150

100

50

0

Error in Current Magnitude (nA)

G017

Figure 17. Lead-Off Current Source Accuracy Distribution

15

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ZHCS158C –JULY 2012–REVISED JANUARY 2017

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8 Parametric Measurement Information

8.1 Noise Measurements

NOTE

Unless otherwise noted, ADS1299-x refers to all specifications and functional descriptions

of the ADS1299-4, ADS1299-6, and ADS1299.

Optimize the ADS1299-x noise performance by adjusting the data rate and PGA setting. Reduce the data rate to

increase the averaging, and the noise drops correspondingly. Increase the PGA value to reduce the input-

referred noise. This lowered noise level is particularly useful when measuring low-level biopotential signals.

Table 1 to Table 4 summarize the ADS1299-x noise performance with a 5-V analog power supply. The data are

representative of typical noise performance at T_A= +25°C. The data shown are the result of averaging the

readings from multiple devices and are measured with the inputs shorted together. A minimum of 1000

consecutive readings are used to calculate the RMS and peak-to-peak noise for each reading. For the lower data

rates, the ratio is approximately 6.6.

Table 1 shows measurements taken with an internal reference. The data are also representative of the

ADS1299-x noise performance when using a low-noise external reference such as the REF5045.

Table 1, Table 2, Table 3, and Table 4 list the input-referred noise in units of μV_RMSand μV_PPfor the conditions

shown. The corresponding data in units of effective number of bits (ENOB) where ENOB for the RMS noise is

defined as in Equation 1:

≈

’

VREF

ENOB = log₂

∆

«

÷

2 ìGainì V_{RMS ◊}

(1)

Noise-free bits for the peak-to-peak noise are calculated with the same method.

The dynamic range data in Table 1, Table 2, Table 3, and Table 4 are calculated using Equation 2:

≈

’

VREF

Dynamic Range = 20ìlog

∆

«

÷

2 ìGainì V_{RMS ◊}

(2)

Table 1. Input-Referred Noise (μV_RMS, μV_PP) in Normal Mode

5-V Analog Supply and 4.5-V Reference⁽¹⁾

PGA

GAIN = 1

GAIN = 2

DR BITS OF

CONFIG1

REGISTER

OUTPUT

DATA RATE

(SPS)

DYNAMIC

RANGE

(dB)

NOISE-

FREE

BITS

DYNAMIC

RANGE

(dB)

NOISE-

FREE

BITS

–3-dB

BANDWIDTH (Hz)

μV_RMS

21.70

6.93

4.33

3.06

2.17

1.53

1.08

—

μV_PP

151.89

48.53

30.34

21.45

15.17

10.73

7.59

ENOB

17.16

18.81

19.49

19.99

20.49

20.99

21.48

—

μV_RMS

10.85

3.65

2.28

1.61

1.14

0.81

0.57

—

μV_PP

75.94

25.52

15.95

11.29

7.98

5.65

3.99

—

ENOB

000

001

010

011

100

101

110

111

16000

8000

4000

2000

1000

500

4193

2096

1048

524

262

131

65

103.3

113.2

117.3

120.3

123.3

126.3

129.3

—

15.85

17.50

18.18

18.68

19.18

19.68

20.18

—

103.3

112.8

116.9

119.9

122.9

125.9

128.9

—

15.85

17.43

18.11

18.60

19.10

19.60

20.10

—

17.16

18.74

19.41

19.91

20.41

20.91

21.41

—

250

n/a

—

(1) At least 1000 consecutive readings were used to calculate the RMS and peak-to-peak noise values in this table.

16

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ZHCS158C –JULY 2012–REVISED JANUARY 2017

Table 2. Input-Referred Noise (μV_RMS, μV_PP) in Normal Mode

5-V Analog Supply and 4.5-V Reference⁽¹⁾

PGA

GAIN = 4

GAIN = 6

DR BITS OF

CONFIG1

REGISTER

OUTPUT

DATA RATE

(SPS)

DYNAMIC

RANGE

(dB)

NOISE-

FREE

BITS

DYNAMIC

RANGE

(dB)

NOISE-

FREE

BITS

–3-dB

BANDWIDTH (Hz)

μV_RMS

5.60

1.98

1.24

0.88

0.62

0.44

0.31

—

μV_PP

39.23

13.87

8.66

6.13

4.34

3.07

2.16

—

ENOB

17.12

18.62

19.29

19.79

20.29

20.79

21.30

—

μV_RMS

3.87

1.31

0.93

0.66

0.46

0.33

0.23

—

μV_PP

27.10

9.19

6.50

4.60

3.25

2.30

1.62

—

ENOB

17.06

18.62

19.12

19.62

20.12

20.62

21.13

—

000

001

010

011

100

101

110

111

16000

8000

4000

2000

1000

500

4193

2096

1048

524

262

131

65

103.0

112.1

116.1

119.2

122.2

125.2

128.2

—

15.81

17.31

17.99

18.49

18.99

19.49

19.99

—

102.7

112.1

115.1

118.1

121.1

124.1

127.2

—

15.76

17.32

17.82

18.32

18.81

19.31

19.82

—

250

n/a

(1) At least 1000 consecutive readings were used to calculate the RMS and peak-to-peak noise values in this table.

Table 3. Input-Referred Noise (μV_RMS, μV_PP) in Normal Mode

5-V Analog Supply and 4.5-V Reference⁽¹⁾

PGA

GAIN = 8

GAIN = 12

DR BITS OF

CONFIG1

REGISTER

OUTPUT

DATA RATE

(SPS)

DYNAMIC

RANGE

(dB)

NOISE-

FREE

BITS

DYNAMIC

RANGE

(dB)

NOISE-

FREE

BITS

–3-dB

BANDWIDTH (Hz)

μV_RMS

3.05

1.11

0.79

0.56

0.39

0.28

0.20

—

μV_PP

21.32

7.80

5.52

3.90

2.76

1.95

1.38

—

ENOB

16.99

18.45

18.95

19.44

19.94

20.44

20.95

—

μV_RMS

2.27

0.92

0.65

0.46

0.32

0.23

0.16

—

μV_PP

15.89

6.41

4.53

3.20

2.26

1.61

1.13

—

ENOB

16.83

18.14

18.64

19.14

19.65

20.14

20.65

—

000

001

010

011

100

101

110

111

16000

8000

4000

2000

1000

500

4193

2096

1048

524

262

131

65

102.3

111.0

114.0

117.1

120.1

123.1

126.1

—

15.69

17.14

17.64

18.14

18.64

19.14

19.64

—

101.3

109.2

112.2

115.2

118.3

121.2

124.3

—

15.53

16.84

17.34

17.84

18.34

18.83

19.34

—

250

n/a

(1) At least 1000 consecutive readings were used to calculate the RMS and peak-to-peak noise values in this table.

Table 4. Input-Referred Noise (μV_RMS, μV_PP) in Normal Mode

5-V Analog Supply and 4.5-V Reference⁽¹⁾

PGA

GAIN = 24

DR BITS OF CONFIG1

REGISTER

OUTPUT DATA

RATE (SPS)

DYNAMIC

RANGE (dB)

NOISE-FREE

BITS

–3-dB BANDWIDTH (Hz)

μV_RMS

1.66

0.80

0.56

0.40

0.28

0.20

0.14

—

μV_PP

11.64

5.57

3.94

2.79

1.97

1.39

0.98

—

ENOB

000

001

010

011

100

101

110

111

16000

8000

4000

2000

1000

500

4193

2096

1048

524

262

131

65

98.0

104.4

107.4

110.4

113.5

116.5

119.5

—

14.98

16.04

16.54

17.04

17.54

18.04

18.54

—

16.28

17.35

17.84

18.35

18.85

19.35

19.85

—

250

n/a

(1) At least 1000 consecutive readings were used to calculate the RMS and peak-to-peak noise values in this table.

17

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9 Detailed Description

9.1 Overview

The ADS1299-x is a low-noise, low-power, multichannel, simultaneously-sampling, 24-bit, delta-sigma (ΔΣ)

analog-to-digital converter (ADC) with an integrated programmable gain amplifier (PGA). These devices integrate

various EEG-specific functions that makes the family well-suited for scalable electrocardiogram (ECG),

electroencephalography (EEG) applications. These devices can also be used in high-performance, multichannel,

data acquisition systems by powering down the ECG or EEG-specific circuitry.

The devices have a highly-programmable multiplexer that allows for temperature, supply, input short, and bias

measurements. Additionally, the multiplexer allows any input electrodes to be programmed as the patient

reference drive. The PGA gain can be chosen from one of seven settings (1, 2, 4, 6, 8, 12, and 24). The ADCs in

the device offer data rates from 250 SPS to 16 kSPS. Communication to the device is accomplished using an

SPI-compatible interface. The device provides four general-purpose input/output (GPIO) pins for general use.

Multiple devices can be synchronized using the START pin.

The internal reference generates a low noise 4.5 V internal voltage when enabled and the internal oscillator

generates a 2.048-MHz clock when enabled. The versatile patient bias drive block allows the average of any

electrode combination to be chosen in order to generate the patient drive signal. Lead-off detection can be

accomplished by using a current source or sink. A one-time, in-band, lead-off option and a continuous, out-of-

band, internal lead-off option are available.

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9.2 Functional Block Diagram

AVDD AVDD1

VREFP VREFN

DVDD

Test Signal

Temperature Sensor Input

Power-Supply Signal

Reference

Lead-Off Excitation Source

DRDY

IN1P

DS

Low-Noise

PGA1

ADC1

CS

IN1N

IN2P

SCLK

DIN

DOUT

SPI

DS

Low-Noise

PGA2

ADC2

IN2N

IN3P

DS

Low-Noise

PGA3

ADC3

IN3N

IN4P

CLKSEL

CLK

DS

Low-Noise

PGA4

Oscillator

MUX

ADC4

IN4N

Control

GPIO1

IN5P

GPIO4

GPIO3

DS

Low-Noise

PGA5

ADC5

IN5N

IN6P

GPIO2

DS

Low-Noise

PGA6

ADC6

IN6N

IN7P

PWDN

RESET

DS

Low-Noise

PGA7

ADC7

IN7N

IN8P

START

DS

Low-Noise

PGA8

ADC8

IN8N

BIAS

Amplifier

AVSS AVSS1

DGND

BIAS BIAS

REF OUT

BIAS

INV

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9.3 Feature Description

This section contains details of the ADS1299-x internal functional elements. The analog blocks are discussed

first, followed by the digital interface. Blocks implementing EEG-specific functions are covered at the end of this

section.

Throughout this document, f_CLKdenotes the CLK pin signal frequency, t_CLKdenotes the CLK pin signal period,

f_DRdenotes the output data rate, t_DRdenotes the output data time period, and f_MODdenotes the frequency at

which the modulator samples the input.

9.3.1 Analog Functionality

9.3.1.1 Input Multiplexer

The ADS1299-x input multiplexers are very flexible and provide many configurable signal-switching options.

Figure 18 shows the multiplexer on a single channel of the device. Note that the device has either four

(ADS1299-4), six (ADS1299-6) or eight (ADS1299) such blocks, one for each channel. SRB1, SRB2, and

BIASIN are common to all blocks. INxP and INxN are separate for each of the four, six, or eight blocks. This

flexibility allows for significant device and sub-system diagnostics, calibration, and configuration. Switch setting

selections for each channel by writing the appropriate values to the CHnSET[3:0] register (see the CHnSET:

Individual Channel Settings section for details) using the BIAS_MEAS bit in the CONFIG3 register and the SRB1

bit in the MISC1 register (see the CONFIG3: Configuration Register 3 subsection of the Register Maps section

for details). See the Input Multiplexer section for further information regarding the EEG-specific features of the

multiplexer.

To Next Channels

TI Device

MUX

INT_TEST

TESTP

MUX[2:0] = 101

MUX[2:0] =100

MUX[2:0] =011

TempP

MVDDP

From LOFFP

MAIN⁽¹⁾

To PGAP

INxP

INxN

MUX[2:0] =110

MUX[2:0] = 010 AND

BIAS_MEAS

CHxSET[3] = 1

MUX[2:0] =001

(VREFP + VREFN)

2

MUX[2:0] =111

MAIN⁽¹⁾AND SRB1

MUX[2:0] =001

To PGAN

MAIN⁽¹⁾

AND SRB1

From LoffN

(AVDD+AVSS)

BIASREF_INT=1

BIASREF_INT=0

MUX[2:0] = 010

AND

BIAS_MEAS

2

MUX[2:0] = 011

MUX[2:0] = 100

MUX[2:0] = 101

MVDDN

TempN

INT_TEST

TESTM

BIASREF

SRB2

BIAS_IN

SRB1

(1) MAIN is equal to either MUX[2:0] = 000, MUX[2:0] = 110, or MUX[2:0] = 111.

Figure 18. Input Multiplexer Block for One Channel

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Feature Description (continued)

9.3.1.1.1 Device Noise Measurements

Setting CHnSET[2:0] = 001 sets the common-mode voltage of [(V_VREFP+ V_VREFN) / 2] to both channel inputs.

This setting can be used to test inherent device noise in the user system.

9.3.1.1.2 Test Signals (TestP and TestN)

Setting CHnSET[2:0] = 101 provides internally-generated test signals for use in sub-system verification at power-

up. This functionality allows the device internal signal chain to be tested out.

Test signals are controlled through register settings (see the CONFIG2: Configuration Register 2 subsection in

the Register Maps section for details). TEST_AMP controls the signal amplitude and TEST_FREQ controls

switching at the required frequency.

9.3.1.1.3 Temperature Sensor (TempP, TempN)

The ADS1299-x contains an on-chip temperature sensor. This sensor uses two internal diodes with one diode

having a current density 16x that of the other, as shown in Figure 19. The difference in diode current densities

yields a voltage difference proportional to absolute temperature.

As a result of the low thermal resistance of the package to the printed circuit board (PCB), the internal device

temperature tracks PCB temperature closely. Note that self-heating of the ADS1299-x causes a higher reading

than the temperature of the surrounding PCB.

The scale factor of Equation 3 converts the temperature reading to degrees Celsius. Before using this equation,

the temperature reading code must first be scaled to microvolts.

Temperature Reading (mV) - 145,300 mV

Temperature (°C) =

+ 25°C

490 mV/°C

(3)

Temperature Sensor Monitor

AVDD

1x

2x

To MUX TempP

To MUX TempN

8x

1x

AVSS

Figure 19. Temperature Sensor Measurement in the Input

9.3.1.1.4 Supply Measurements (MVDDP, MVDDN)

Setting CHnSET[2:0]

= 011 sets the channel inputs to different supply voltages of the device.

For channels 1, 2, 5, 6, 7, and 8, (MVDDP – MVDDN) is [0.5 × (AVDD + AVSS)].

For channels 3 and 4, (MVDDP – MVDDN) is DVDD / 4.

To avoid saturating the PGA when measuring power supplies, set the gain to 1.

9.3.1.1.5 Lead-Off Excitation Signals (LoffP, LoffN)

The lead-off excitation signals are fed into the multiplexer before the switches. The comparators that detect the

lead-off condition are also connected to the multiplexer block before the switches. For a detailed description of

the lead-off block, see the Lead-Off Detection section.

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Feature Description (continued)

9.3.1.1.6 Auxiliary Single-Ended Input

The BIASIN pin is primarily used for routing the bias signal to any electrodes in case the bias electrode falls off.

However, the BIASIN pin can be used as a multiple single-ended input channel. The signal at the BIASIN pin can

be measured with respect to the voltage at the BIASREF pin using any of the eight channels. This measurement

is done by setting the channel multiplexer setting to '010' and the BIAS_MEAS bit of the CONFIG3 register to '1'.

9.3.1.2 Analog Input

The analog inputs to the device connect directly to an integrated low-noise, low-drift, high input impedance,

programmable gain amplifier. The amplifier is located following the individual channel multiplexer.

The ADS1299-x analog inputs are fully differential. The differential input voltage (V_INxP– V_INxN) can span from

–V_REF/ gain to V_REF/ gain. See the Data Format section for an explanation of the correlation between the analog

input and digital codes. There are two general methods of driving the ADS1299-x analog inputs: pseudo-

differential or fully-differential, as shown in Figure 20, Figure 21, and Figure 22.

-V_REF/ Gain

to

V_REF/ Gain

Peak-to-Peak

Device

Common

Voltage

V_REF/ Gain

Peak-to-Peak

Common

Voltage

a) Psuedo-Differential Input

b) Differential Input

Figure 20. Methods of Driving the ADS1299-x: Pseudo-Differential or Fully Differential

INxP

INxN

V_CM

INxN

Figure 21. Pseudo-Differential Input Mode

Figure 22. Fully-Differential Input Mode

Hold the INxN pin at a common voltage, preferably at mid supply, to configure the fully differential input for a

pseudo-differential signal. Swing the INxP pin around the common voltage –V_REF/ gain to V_REF/ gain and remain

within the absolute maximum specifications. The common-mode voltage (V_CM) changes with varying signal level

when the inputs are configured in pseudo-differential mode. Verify that the differential signal at the minimum and

maximum points meets the common-mode input specification discussed in the Input Common-Mode Range

section.

Configure the signals at INxP and INxN to be 180° out-of-phase centered around a common voltage to use a

fully differential input method. Both the INxP and INxN inputs swing from the common voltage + ½ V_REF/ gain to

the common voltage – ½ V_REF/ gain. The differential voltage at the maximum and minimum points is equal to

–V_REF/ gain to V_REF/ gain and centered around a fixed common-mode voltage (V_CM). Use the ADS1299-x in a

differential configuration to maximize the dynamic range of the data converter. For optimal performance, the

common voltage is recommended to be set at the midpoint of the analog supplies [(AVDD + AVSS) / 2].

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9.3.1.3 PGA Settings and Input Range

The low-noise PGA is a differential input and output amplifier, as shown in Figure 23. The PGA has seven gain

settings (1, 2, 4, 6, 8, 12, and 24) that can be set by writing to the CHnSET register (see the CHnSET: Individual

Channel Settings subsection of the Register Maps section for details). The ADS1299-x has CMOS inputs and

therefore has negligible current noise. Table 5 shows the typical bandwidth values for various gain settings. Note

that Table 5 shows small-signal bandwidth. For large signals, performance is limited by PGA slew rate.

From MuxP

Low-Noise

PGAp

R₂

18.15 kW

R₁

3.3 kW

(for Gain = 12)

To ADC

R₂

18.15 kW

Low-Noise

PGAn

From MuxN

Figure 23. PGA Implementation

Table 5. PGA Gain versus Bandwidth

NOMINAL BANDWIDTH AT ROOM

GAIN

TEMPERATURE (kHz)

1

2

662

332

165

110

83

4

6

8

12

24

55

27

The PGA resistor string that implements the gain has 39.6 kΩ of resistance for a gain of 12. This resistance

provides a current path across the PGA outputs in the presence of a differential input signal. This current is in

addition to the quiescent current specified for the device in the presence of a differential signal at the input.

9.3.1.3.1 Input Common-Mode Range

To stay within the linear operating range of the PGA, the input signals must meet certain requirements that are

discussed in this section.

The outputs of the amplifiers in Figure 23 cannot swing closer to the supplies (AVSS and AVDD) than 200 mV. If

the outputs of the amplifiers are driven to within 200 mV of the supply rails, then the amplifiers saturate and

consequently become nonlinear. To prevent this nonlinear operating condition, the output voltages must not

exceed the common-mode range of the front-end.

The usable input common-mode range of the front-end depends on various parameters, including the maximum

differential input signal, supply voltage, PGA gain, and the 200 mV for the amplifier headroom. This range is

described in Equation 4:

Gain ´ V

MAX _DIFF

æ

ö

æ

ö

MAX _DIFF

AVDD - 0.2 V -

> CM > AVSS + 0.2 V +

ç

÷

ç

÷

ç

÷

ç

÷

2

è

ø

è

ø

where:

V_{MAX_DIFF}= maximum differential signal at the PGA input

CM = common-mode range

(4)

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For example:

If AVDD = 5 V, gain = 12, and V_{MAX_DIFF}= 350 mV

Then 2.3 V < CM < 2.7 V

9.3.1.3.2 Input Differential Dynamic Range

The differential input voltage range (V_INxP– V_INxN) depends on the analog supply and reference used in the

system. This range is shown in Equation 5.

±V_REF

2V_REF

Full-Scale Range =

=

Gain

(5)

9.3.1.3.3 ADC ΔΣ Modulator

Each ADS1299-x channel has a 24-bit, ΔΣ ADC. This converter uses a second-order modulator optimized for

low-noise applications. The modulator samples the input signal at the rate of (f_MOD= f_CLK/ 2). As in the case of

any ΔΣ modulator, the device noise is shaped until f_MOD/ 2, as shown in Figure 24. The on-chip digital

decimation filters explained in the next section can be used to filter out the noise at higher frequencies. These

on-chip decimation filters also provide antialias filtering. This ΔΣ converter feature drastically reduces the

complexity of the analog antialiasing filters typically required with nyquist ADCs.

0

−10

−20

−30

−40

−50

−60

−70

−80

−90

−100

−110

−120

−130

−140

−150

−160

0.001

0.01

0.1

1

Normalized Frequency (f_IN/f_MOD

)

G001

Figure 24. Modulator Noise Spectrum Up To 0.5 × f_MOD

9.3.1.3.4 Reference

Figure 25 shows a simplified block diagram of the ADS1299-x internal reference. The 4.5-V reference voltage is

generated with respect to AVSS. When using the internal voltage reference, connect V_REFNto AVSS.

100 mF

VCAP1

R1⁽¹⁾

Bandgap

4.5 V

VREFP

R3⁽¹⁾

10 mF

R2⁽¹⁾

VREFN

AVSS

To ADC Reference Inputs

(1) For V_REF= 4.5 V: R1 = 9.8 kΩ, R2 = 13.4 kΩ, and R3 = 36.85 kΩ.

Figure 25. Internal Reference

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The external band-limiting capacitors determine the amount of reference noise contribution. For high-end EEG

systems, the capacitor values should be chosen such that the bandwidth is limited to less than 10 Hz so that the

reference noise does not dominate system noise.

Alternatively, the internal reference buffer can be powered down and an external reference can be applied to

VREFP. Figure 26 shows a typical external reference drive circuitry. Power-down is controlled by the

PD_REFBUF bit in the CONFIG3 register. This power-down is also used to share internal references when two

devices are cascaded. By default, the device wakes up in external reference mode.

100 kꢀ

22 nF

+5 V

0.1 ꢁF

10 ꢀ

To VREFP

OPA350

100 ꢀ

10 ꢁF

0.1 ꢁF

VIN

OUT

5 V

100 ꢁF

REF5025

1 ꢁF

TRIM

Figure 26. External Reference Driver

9.3.2 Digital Functionality

9.3.2.1 Digital Decimation Filter

The digital filter receives the modulator output and decimates the data stream. By adjusting the amount of

filtering, tradeoffs can be made between resolution and data rate: filter more for higher resolution, filter less for

higher data rates. Higher data rates are typically used in EEG applications for ac lead-off detection.

The digital filter on each channel consists of a third-order sinc filter. The sinc filter decimation ratio can be

adjusted by the DR bits in the CONFIG1 register (see the Register Maps section for details). This setting is a

global setting that affects all channels and, therefore, all channels operate at the same data rate in a device.

9.3.2.1.1 Sinc Filter Stage (sinx / x)

The sinc filter is a variable decimation rate, third-order, low-pass filter. Data are supplied to this section of the

filter from the modulator at the rate of f_MOD. The sinc filter attenuates the modulator high-frequency noise, then

decimates the data stream into parallel data. The decimation rate affects the overall converter data rate.

Equation 6 shows the scaled Z-domain transfer function of the sinc filter.

3

1 - Z^-N

½H(z)½ =

1 - Z^-1

(6)

The frequency domain transfer function of the sinc filter is shown in Equation 7.

3

Npf

sin

f_MOD

H(f)½ =

pf

N ´ sin

f_MOD

where:

N = decimation ratio

(7)

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The sinc filter has notches (or zeroes) that occur at the output data rate and multiples thereof. At these

frequencies, the filter has infinite attenuation. Figure 27 shows the sinc filter frequency response and Figure 28

shows the sinc filter roll-off. With a step change at input, the filter takes 3 × t_DRto settle. After a rising edge of the

START signal, the filter takes t_SETTLEtime to give the first data output. The settling time of the filters at various

data rates are discussed in the Start subsection of the SPI Interface section. Figure 29 and Figure 30 show the

filter transfer function until f_MOD/ 2 and f_MOD/ 16, respectively, at different data rates. Figure 31 shows the

transfer function extended until 4 × f_MOD. The ADS1299-x pass band repeats itself at every f_MOD. The input R-C

antialiasing filters in the system should be chosen such that any interference in frequencies around multiples of

f_MODare attenuated sufficiently.

0

-20

0

-0.5

-1

-40

-60

-1.5

-2

-80

-100

-120

-140

-2.5

-3

0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5

0

0.05

0.1

0.15

0.2

0.25

0.3

0.35

Normalized Frequency (f_IN/ f_DR

)

Normalized Frequency (f_IN/ f_DR

)

Figure 27. Sinc Filter Frequency Response

Figure 28. Sinc Filter Roll-Off

0

DR[2:0] = 000

DR[2:0] = 001

DR[2:0] = 010

DR[2:0] = 011

DR[2:0] = 100

DR[2:0] = 101

DR[2:0] = 110

DR[2:0] = 000

DR[2:0] = 001

DR[2:0] = 010

DR[2:0] = 011

DR[2:0] = 100

DR[2:0] = 101

DR[2:0] = 110

−20

−40

−20

−40

−60

−80

−100

−120

−140

−160

−100

−120

−140

0

0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5

Normalized Frequency (f_IN/f_MOD

0

0.01

0.02

0.03

0.04

0.05

0.06

0.07

)

Normalized Frequency (f_IN/f_MOD

)

G027

G028

Figure 29. Transfer Function of On-Chip Decimation Filters

Until f_MOD/ 2

Figure 30. Transfer Function of On-Chip Decimation Filters

Until f_MOD/ 16

0

−20

−40

−60

−80

−100

−120

−140

0

0.5

1

1.5

2

2.5

3

3.5

4

Normalized Frequency (f_IN/f_MOD

)

G029

Figure 31. Transfer Function of On-Chip Decimation Filters

Until 4 f_MODfor DR[2:0] = 000 and DR[2:0] = 110

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9.3.2.2 Clock

The ADS1299-x provides two methods for device clocking: internal and external. Internal clocking is ideally

suited for low-power, battery-powered systems. The internal oscillator is trimmed for accuracy at room

temperature. Accuracy varies over the specified temperature range; see the Electrical Characteristics. Clock

selection is controlled by the CLKSEL pin and the CLK_EN register bit.

The CLKSEL pin selects either the internal or external clock. The CLK_EN bit in the CONFIG1 register enables

and disables the oscillator clock to be output in the CLK pin. A truth table for these two pins is shown in Table 6.

The CLK_EN bit is useful when multiple devices are used in a daisy-chain configuration. During power-down, the

external clock is recommended be shut down to save power.

Table 6. CLKSEL Pin and CLK_EN Bit

CONFIG1.CLK_EN

CLKSEL PIN

BIT

CLOCK SOURCE

External clock

CLK PIN STATUS

Input: external clock

3-state

0

1

X

0

Internal clock oscillator

1

Output: internal clock oscillator

9.3.2.3 GPIO

The ADS1299-x has a total of four general-purpose digital I/O (GPIO) pins available in normal mode of operation.

The digital I/O pins are individually configurable as either inputs or outputs through the GPIOC bits register. The

GPIOD bits in the GPIO register control the pin level. When reading the GPIOD bits, the data returned are the

logic level of the pins, whether they are programmed as inputs or outputs. When the GPIO pin is configured as

an input, a write to the corresponding GPIOD bit has no effect. When configured as an output, a write to the

GPIOD bit sets the output value.

If configured as inputs, these pins must be driven (do not float). The GPIO pins are set as inputs after power-on

or after a reset. Figure 32 shows the GPIO port structure. The pins should be shorted to DGND if not used.

GPIO Data (read)

GPIO Pin

GPIO Data (write)

GPIO Control

Figure 32. GPIO Port Pin

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9.3.2.4 ECG and EEG Specific Features

9.3.2.4.1 Input Multiplexer (Rerouting the BIAS Drive Signal)

The input multiplexer has EEG-specific functions for the bias drive signal. The BIAS signal is available at the

BIASOUT pin when the appropriate channels are selected for BIAS derivation, feedback elements are installed

external to the chip, and the loop is closed. This signal can either be fed after filtering or fed directly into the

BIASIN pin, as shown in Figure 33. This BIASIN signal can be multiplexed into any input electrode by setting the

MUX bits of the appropriate channel set registers to '110' for P-side or '111' for N-side. Figure 33 shows the BIAS

signal generated from channels 1, 2, and 3 and routed to the N-side of channel 8. This feature can be used to

dynamically change the electrode that is used as the reference signal to drive the patient body.

BIAS_SENSP[0] = 1

IN1P

Low-Noise

PGA1

BIAS_SENSN[0] = 1

MUX1[2:0] = 000

IN1N

BIAS_SENSP[1] = 1

IN2P

Low-Noise

PGA2

BIAS_SENSN[1] = 1

MUX2[2:0] = 000

IN2N

BIAS_SENSP[2] = 1

IN3P

Low-Noise

PGA3

BIAS_SENSN[2] = 1

MUX3[2:0] = 000

IN3N

BIAS_SENSP[7] = 0

IN8P

Low-Noise

PGA8

BIAS_SENSN[7] = 0

MUX8[2:0] = 111

IN8N

BIASREF_INT = 1

MUX

(AVDD + AVSS)

2

BIASREF_INT = 0

BIAS_AMP

Device

BIASIN

BIASREF

BIASOUT

BIASINV

(1)

1 MW

Filter or

Feedthrough

1.5 nF⁽¹⁾

(1) Typical values for example only.

Figure 33. Example of BIASOUT Signal Configured to be Routed to IN8N

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9.3.2.4.2 Input Multiplexer (Measuring the BIAS Drive Signal)

Also, the BIASOUT signal can be routed to a channel (that is not used for the calculation of BIAS) for

measurement. Figure 34 shows the register settings to route the BIASIN signal to channel 8. The measurement

is done with respect to the voltage on the BIASREF pin. If BIASREF is chosen to be internal, then BIASREF is at

[(AVDD + AVSS) / 2]. This feature is useful for debugging purposes during product development.

BIAS_SENSP[0] = 1

IN1P

Low-Noise

PGA1

BIAS_SENSN[0] = 1

MUX1[2:0] = 000

IN1N

BIAS_SENSP[1] = 1

IN2P

Low-Noise

PGA2

BIAS_SENSN[1] = 1

MUX2[2:0] = 000

IN2N

BIAS_SENSP[2] = 1

IN3P

Low-Noise

PGA3

BIAS_SENSN[2] = 1

MUX3[2:0] = 000

IN3N

BIAS_SENSP[7] = 0

IN8P

Low-Noise

PGA8

BIAS_SENSN[7] = 0

MUX8[2:0] = 010

IN8N

MUX

BIASREF_INT = 1

(AVDD + AVSS)

BIAS_MEAS = 1

2

BIAS_AMP

BIASREF_INT = 0

TI Device

BIASIN

BIASREF

BIASOUT

BIASINV

(1)

1 MW

Filter or

Feedthrough

1.5 nF⁽¹⁾

(1) Typical values for example only.

Figure 34. BIASOUT Signal Configured to be Read Back by Channel 8

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9.3.2.4.3 Lead-Off Detection

Patient electrode impedances are known to decay over time. These electrode connections must be continuously

monitored to verify that a suitable connection is present. The ADS1299-x lead-off detection functional block

provides significant flexibility to the user to choose from various lead-off detection strategies. Though called lead-

off detection, this is in fact an electrode-off detection.

The basic principle is to inject an excitation current and measure the voltage to determine if the electrode is off.

As shown in the lead-off detection functional block diagram in Figure 35, this circuit provides two different

methods of determining the state of the patient electrode. The methods differ in the frequency content of the

excitation signal. Lead-off can be selectively done on a per channel basis using the LOFF_SENSP and

LOFF_SENSN registers. Also, the internal excitation circuitry can be disabled and just the sensing circuitry can

be enabled.

Skin,

Electrode Contact

Model

Patient

Protection

Resistor

Patient

Z₁

47 nF

51 kW

V_INP

To ADC

V_INN

Z₂

LOFF_SENSP

LOFF_SENSN

47 nF

FLEAD_OFF[0:1]

Z₃

47 nF

6 nA and 24 nA

6 mA and 24 mA

51 kW

AVDD

AVSS

BIAS OUT

Figure 35. Lead-Off Detection

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9.3.2.4.3.1 DC Lead-Off

In this method, the lead-off excitation is with a dc signal. The dc excitation signal can be chosen from either an

external pull-up or pull-down resistor or an internal current source or sink, as shown in Figure 36. One side of the

channel is pulled to supply and the other side is pulled to ground. The pull-up and pull-down current can be

swapped (as shown in Figure 36b and Figure 36c) by setting the bits in the LOFF_FLIP register. In case of a

current source or sink, the magnitude of the current can be set by using the ILEAD_OFF[1:0] bits in the LOFF

register. The current source or sink gives larger input impedance compared to the 10-MΩ pull-up or pull-down

resistor.

AVDD

Device

10 MW

INP

INN

INP

INN

INP

INN

Low-Noise

PGAn

Low-Noise

PGAn

Low-Noise

PGAn

10 MW

AVSS

a) External Pull-Up or Pull-Down Resistors

b) Input Current Source

(LOFF_FLIP = 0)

c) Input Current Source

(LOFF_FLIP = 1)

Figure 36. DC Lead-Off Excitation Options

Sensing of the response can be done either by searching the digital output code from the device or by monitoring

the input voltages with an on-chip comparator. If either electrode is off, the pull-up and pull-down resistors

saturate the channel. Searching the output code determines if either the P-side or the N-side is off. To pinpoint

which one is off, the comparators must be used. The input voltage is also monitored using a comparator and a 3-

bit DAC whose levels are set by the COMP_TH[2:0] bits in the LOFF register. The output of the comparators are

stored in the LOFF_STATP and LOFF_STATN registers. These registers are available as a part of the output

data stream. (See the Data Output (DOUT) subsection of the SPI Interface section.) If dc lead-off is not used, the

lead-off comparators can be powered down by setting the PD_LOFF_COMP bit in the CONFIG4 register.

An example procedure to turn on dc lead-off is given in the Lead-Off section.

9.3.2.4.3.2 AC Lead-Off (One Time or Periodic)

In this method, an in-band ac signal is used for excitation. The ac signal is generated by alternatively providing a

current source and sink at the input with a fixed frequency. The frequency can be chosen by the

FLEAD_OFF[1:0] bits in the LOFF register. The excitation frequency is chosen to be one of the two in-band

frequency selections (7.8 Hz or 31.2 Hz). This in-band excitation signal is passed through the channel and

measured at the output.

Sensing of the ac signal is done by passing the signal through the channel to be digitized and then measured at

the output. The ac excitation signals are introduced at a frequency that is in the band of interest. The signal can

be filtered out separately and processed. By measuring the magnitude of the output at the excitation signal

frequency, the electrode impedance can be calculated.

For continuous lead-off, an out-of-band ac current source or sink must be externally applied to the inputs. This

signal can then be digitally processed to determine the electrode impedance.

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9.3.2.4.4 Bias Lead-Off

BIAS Lead-Off Detection During Normal Operation

During normal operation, the ADS1299-x BIAS lead-off at power-up function cannot be used because the BIAS

amplifier must be powered off.

BIAS Lead Off Detection At Power-Up

This feature is included in the ADS1299-x for use in determining whether the bias electrode is suitably

connected. At power-up, the ADS1299-x uses a current source and comparator to determine the BIAS electrode

connection status, as shown in Figure 37. The reference level of the comparator is set to determine the

acceptable BIAS impedance threshold.

Skin,

Patient

Patient Electrode Contact Protection

Model

47 nF

Resistor

To ADC input (through V_REF

connection to any of the channels).

BIAS_STAT

51 kW

BIAS_SENS

ILEAD_OFF[1:0]

AVSS

Figure 37. BIAS Lead-Off Detection at Power-Up

When the BIAS amplifier is powered on, the current source has no function. Only the comparator can be used to

sense the voltage at the output of the BIAS amplifier. The comparator thresholds are set by the same LOFF[7:5]

bits used to set the thresholds for other negative inputs.

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9.3.2.4.5 Bias Drive (DC Bias Circuit)

Use the bias circuitry to counter the common-mode interference in a EEG system as a result of power lines and

other sources, including fluorescent lights. The bias circuit senses the common-mode voltage of a selected set of

electrodes and creates a negative feedback loop by driving the body with an inverted common-mode signal. The

negative feedback loop restricts the common-mode movement to a narrow range, depending on the loop gain.

Stabilizing the entire loop is specific to the individual user system based on the various poles in the loop. The

ADS1299-x integrates the muxes to select the channel and an operational amplifier. All the amplifier terminals

are available at the pins, allowing the user to choose the components for the feedback loop. The circuit in

Figure 38 shows the overall functional connectivity for the bias circuit.

From

MUX1P

BIAS1P

220 kW

PGA1P

From

MUX2P

18.15 kW

BIAS2P

220 kW

PGA2P

18.15 kW

3.3 kW

18.15 kW

3.3 kW

220 kW

PGA1N

From

MUX1N

BIAS1N

18.15 kW

PGA2N

220 kW

From

MUX2N

BIAS2N

BIAS4P

From

MUX3P

BIAS3P

PGA3P

From

MUX4P

18.15 kW

220 kW

PGA4P

18.15 kW

3.3 kW

18.15 kW

3.3 kW

220 kW

PGA3N

From

MUX3N

BIAS3N

18.15 kW

PGA4N

220 kW

From

MUX4N

BIAS4N

BIAS6P

From

MUX5P

BIAS5P

PGA5P

From

MUX6P

18.15 kW

220 kW

PGA6P

18.15 kW

3.3 kW

18.15 kW

3.3 kW

220 kW

PGA5N

From

MUX5N

BIAS5N

18.15 kW

PGA6N

220 kW

From

MUX6N

BIAS6N

BIAS8P

From

MUX7P

BIAS7P

PGA7P

From

MUX8P

18.15 kW

220 kW

PGA8P

18.15 kW

3.3 kW

18.15 kW

3.3 kW

220 kW

PGA7N

From

MUX7N

BIAS7N

18.15 kW

PGA8N

220 kW

BIASINV

From

MUX8N

BIAS8N

(1)

C_EXT

(1)

R_EXT

1.5 nF

1 MW

BIAS

Amp

BIASOUT

BIASREF

(AVDD + AVSS) / 2

BIASREF_INT = 1

BIASREF_INT = 0

(1) Typical values.

Figure 38. Bias Drive Amplifier Channel Selection

The reference voltage for the bias drive can be chosen to be internally generated [(AVDD + AVSS) / 2] or

provided externally with a resistive divider. The selection of an internal versus external reference voltage for the

bias loop is defined by writing the appropriate value to the BIASREF_INT bit in the CONFIG2 register.

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If the bias function is not used, the amplifier can be powered down using the PD_BIAS bit (see the CONFIG3:

Configuration Register 3 subsection of the Register Maps section for details). Use the PD_BIAS bit to power-

down all but one of the bias amplifiers when daisy-chaining multiple ADS1299-x devices.

The BIASIN pin functionality is explained in the Input Multiplexer section. An example procedure to use the bias

amplifier is shown in the Bias Drive section.

9.3.2.4.5.1 Bias Configuration with Multiple Devices

Figure 39 shows multiple devices connected to the bias drive.

Device N

Device 2

Device 1

Power-Down

VA1-8 VA1-8

BIASIN BIAS BIAS

REF OUT

BIASINV

BIASIN BIAS BIAS

REF OUT

BIASINV

BIASIN BIAS BIAS

REF OUT

BIASINV

Figure 39. BIAS Drive Connection for Multiple Devices

9.4 Device Functional Modes

9.4.1 Start

Pull the START pin high for at least 2 t_CLKperiods, or send the START command to begin conversions. When

START is low and the START command has not been sent, the device does not issue a DRDY signal

(conversions are halted).

When using the START command to control conversions, hold the START pin low. The ADS1299-x features two

modes to control conversions: continuous mode and single-shot mode. The mode is selected by SINGLE_SHOT

(bit 3 of the CONFIG4 register). In multiple device configurations, the START pin is used to synchronize devices

(see the Multiple Device Configuration subsection of the SPI Interface section for more details).

9.4.1.1 Settling Time

The settling time (t_SETTLE) is the time required for the converter to output fully-settled data when the START

signal is pulled high. When START is pulled high, DRDY is also pulled high. The next DRDY falling edge

indicates that data are ready. Figure 40 shows the timing diagram and Table 7 lists the settling time for different

data rates. The settling time depends on f_CLKand the decimation ratio (controlled by the DR[2:0] bits in the

CONFIG1 register). When the initial settling time has passed, the DRDY falling edge occurs at the set data rate,

t_DR. If data is not read back on DOUT and the output shift register needs to update, DRDY goes high for 4 t_CLK

before returning back low indicating new data is ready. Table 7 lists the settling time as a function of t_CLK. Note

that when START is held high and there is a step change in the input signal, 3 × t_DRis required for the filter to

settle to the new value. Settled data are available on the fourth DRDY pulse.

t_SETTLE

START Pin

or

START

DIN

t_DR

4 / f_CLK

DRDY

Figure 40. Settling Time

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Device Functional Modes (continued)

Table 7. Settling Time for Different Data Rates

DR[2:0]

000

NORMAL MODE

521

UNIT

t_CLK

001

1033

010

2057

011

4105

100

8201

101

16393

32777

110

9.4.2 Reset (RESET)

There are two methods to reset the ADS1299-x: pull the RESET pin low, or send the RESET command. When

using the RESET pin, make sure to follow the minimum pulse duration timing specifications before taking the pin

back high. The RESET command takes effect on the eighth SCLK falling edge of the command. After a reset, 18

t_CLKcycles are required to complete initialization of the configuration registers to default states and start the

conversion cycle. Note that an internal reset is automatically issued to the digital filter whenever the CONFIG1

register is set to a new value with a WREG command.

9.4.3 Power-Down (PWDN)

When PWDN is pulled low, all on-chip circuitry is powered down. To exit power-down mode, take the PWDN pin

high. Upon exiting from power-down mode, the internal oscillator and the reference require time to wake up.

During power-down, the external clock is recommended to be shut down to save power.

9.4.4 Data Retrieval

9.4.4.1 Data Ready (DRDY)

DRDY is an output signal which transitions from high to low indicating new conversion data are ready. The CS

signal has no effect on the data ready signal. DRDY behavior is determined by whether the device is in RDATAC

mode or the RDATA command is used to read data on demand. (See the RDATAC: Read Data Continuous and

RDATA: Read Data subsections of the SPI Command Definitions section for further details).

When reading data with the RDATA command, the read operation can overlap the next DRDY occurrence

without data corruption.

The START pin or the START command places the device either in normal data capture mode or pulse data

capture mode.

Figure 41 shows the relationship between DRDY, DOUT, and SCLK during data retrieval (in case of an

ADS1299). DOUT is latched out at the SCLK rising edge. DRDY is pulled high at the SCLK falling edge. Note

that DRDY goes high on the first SCLK falling edge, regardless of whether data are being retrieved from the

device or a command is being sent through the DIN pin.

DRDY

DOUT

SCLK

X

Bit 215

Bit 214

Bit 213

Figure 41. DRDY with Data Retrieval (CS = 0)

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Device Functional Modes (continued)

9.4.4.2 Reading Back Data

Data retrieval can be accomplished in one of two methods:

1. RDATAC: the read data continuous command sets the device in a mode that reads data continuously without

sending commands. See the RDATAC: Read Data Continuous section for more details.

2. RDATA: the read data command requires that a command is sent to the device to load the output shift

register with the latest data. See the RDATA: Read Data section for more details.

Conversion data are read by shifting data out on DOUT. The MSB of the data on DOUT is clocked out on the

first SCLK rising edge. DRDY returns high on the first SCLK falling edge. DIN should remain low for the entire

read operation.

The number of bits in the data output depends on the number of channels and the number of bits per channel.

For the 8-channel ADS1299, the number of data outputs is [(24 status bits + 24 bits × 8 channels) = 216 bits].

The format of the 24 status bits is: (1100 + LOFF_STATP + LOFF_STATN + bits[4:7] of the GPIO register). The

data format for each channel data are twos complement and MSB first. When channels are powered down using

the user register setting, the corresponding channel output is set to '0'. However, the channel output sequence

remains the same.

The ADS1299-x also provides a multiple readback feature. Data can be read out multiple times by simply giving

more SCLKs in RDATAC mode, in which case the MSB data byte repeats after reading the last byte. The

DAISY_EN bit in the CONFIG1 register must be set to '1' for multiple readbacks.

9.4.5 Continuous Conversion Mode

Conversions begin when the START pin is taken high or when the START command is sent. As shown in

Figure 42, the DRDY output goes high when conversions are started and goes low when data are ready.

Conversions continue indefinitely until the START pin is taken low or the STOP command is transmitted. When

the START pin is pulled low or the STOP command is issued, the conversion in progress is allowed to complete.

Figure 43 and Table 8 illustrate the required DRDY timing to the START pin or the START and STOP commands

when controlling conversions in this mode. The t_SDSUtiming indicates when to take the START pin low or when to

send the STOP command before the DRDY falling edge to halt further conversions. The t_DSHDtiming indicates

when to take the START pin low or send the STOP command after a DRDY falling edge to complete the current

conversion and halt further conversions. To keep the converter running continuously, the START pin can be

permanently tied high.

When switching from Single-Shot mode to Continuous Conversion mode, bring the START signal low and back

high or send a STOP command followed by a START command. This conversion mode is ideal for applications

that require a fixed continuous stream of conversions results.

START Pin

or

START⁽¹⁾

STOP⁽¹⁾

DIN

t_DR

t_SETTLE

DRDY

(1) START and STOP commands take effect on the seventh SCLK falling edge.

Figure 42. Continuous Conversion Mode

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Device Functional Modes (continued)

t_SDSU

DRDY and DOUT

t_DSHD

START Pin

or

STOP⁽¹⁾

STOP Command

(1) START and STOP commands take effect on the seventh SCLK falling edge at the end of the command.

Figure 43. START to DRDY Timing

Table 8. Timing Characteristics for Figure 43⁽¹⁾

MIN

16

UNIT

t_CLK

t_SDSU

t_DSHD

START pin low or STOP command to DRDY setup time to halt further conversions

START pin low or STOP command to complete current conversion

16

t_CLK

(1) START and STOP commands take effect on the seventh SCLK falling edge at the end of the command.

9.4.6 Single-Shot Mode

Single-shot mode is enabled by setting the SINGLE_SHOT bit in the CONFIG4 register to '1'. In single-shot

mode, the ADS1299-x performs a single conversion when the START pin is taken high or when the START

command is sent. As shown in Figure 44, when a conversion is complete, DRDY goes low and further

conversions are stopped. Regardless of whether the conversion data are read or not, DRDY remains low. To

begin a new conversion, take the START pin low and then back high, or send the START command again. When

switching from Continuous Conversion mode to Single-Shot mode, bring the START signal low and back high or

send a STOP command followed by a START command.

START

t_SETTLE

4 / f_CLK

Data Updating

DRDY

Figure 44. DRDY with No Data Retrieval in Single-Shot Mode

This conversion mode is ideal for applications that require non-standard or non-continuous data rates. Issuing a

START command or toggling the START pin high resets the digital filter, effectively dropping the data rate by a

factor of four. This mode leaves the system more susceptible to aliasing effects, requiring more complex analog

or digital filtering. Loading on the host processor increases because the processor must toggle the START pin or

send a START command to initiate a new conversion cycle.

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9.5 Programming

9.5.1 Data Format

The device provides 24 bits of data in binary twos complement format. The size of one code (LSB) is calculated

using Equation 8.

1 LSB = (2 × V_REF/ Gain) / 2²⁴= +FS / 2²³

(8)

A positive full-scale input produces an output code of 7FFFFFh and the negative full-scale input produces an

output code of 800000h. The output clips at these codes for signals exceeding full-scale. Table 9 summarizes the

ideal output codes for different input signals. All 24 bits toggle when the analog input is at positive or negative

full-scale.

Table 9. Ideal Output Code versus Input Signal

INPUT SIGNAL, V_IN

(INxP - INxN)

IDEAL OUTPUT CODE⁽¹⁾

7FFFFFh

≥ FS

+FS / (2²³– 1)

0

000001h

000000h

–FS / (2²³– 1)

≤ –FS (2²³/ 2²³– 1)

FFFFFFh

800000h

(1) Excludes effects of noise, linearity, offset, and gain error.

9.5.2 SPI Interface

The SPI-compatible serial interface consists of four signals: CS, SCLK, DIN, and DOUT. The interface reads

conversion data, reads and writes registers, and controls ADS1299-x operation. The data-ready output, DRDY

(see the Data Ready (DRDY) section), is used as a status signal to indicate when data are ready. DRDY goes

low when new data are available.

9.5.2.1 Chip Select (CS)

The CS pin activates SPI communication. CS must be low before data transactions and must stay low for the

entire SPI communication period. When CS is high, the DOUT pin enters a high-impedance state. Therefore,

reading and writing to the serial interface are ignored and the serial interface is reset. DRDY pin operation is

independent of CS. DRDY still indicates that a new conversion has completed and is forced high as a response

to SCLK, even if CS is high.

Taking CS high deactivates only the SPI communication with the device and the serial interface is reset. Data

conversion continues and the DRDY signal can be monitored to check if a new conversion result is ready. A

master device monitoring the DRDY signal can select the appropriate slave device by pulling the CS pin low.

After the serial communication is finished, always wait four or more t_CLKcycles before taking CS high.

9.5.2.2 Serial Clock (SCLK)

SCLK provides the clock for serial communication. SCLK is a Schmitt-trigger input, but TI recommends keeping

SCLK as free from noise as possible to prevent glitches from inadvertently shifting the data. Data are shifted into

DIN on the falling edge of SCLK and shifted out of DOUT on the rising edge of SCLK.

The absolute maximum SCLK limit is specified in Figure 1. When shifting in commands with SCLK, make sure

that the entire set of SCLKs is issued to the device. Failure to do so can result in the device serial interface being

placed into an unknown state requiring CS to be taken high to recover.

For a single device, the minimum speed required for SCLK depends on the number of channels, number of bits

of resolution, and output data rate. (For multiple cascaded devices, see the Cascaded Mode subsection of the

Multiple Device Configuration section.)

For example, if the ADS1299 is used in a 500-SPS mode (8 channels, 24-bit resolution), the minimum SCLK

speed is 110 kHz.

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Data retrieval can be accomplished either by placing the device in RDATAC mode or by issuing an RDATA

command for data on demand. The SCLK rate limitation in Equation 9 applies to RDATAC. For the RDATA

command, the limitation applies if data must be read in between two consecutive DRDY signals. Equation 9

assumes that there are no other commands issued in between data captures.

t_DR- 4 t_CLK

t_SCLK

<

N

_BITS´ N_CHANNELS+ 24

(9)

9.5.2.3 Data Input (DIN)

DIN is used along with SCLK to send data to the device. Data on DIN are shifted into the device on the falling

edge of SCLK.

The communication of this device is full-duplex in nature. The device monitors commands shifted in even when

data are being shifted out. Data that are present in the output shift register are shifted out when sending in a

command. Therefore, make sure that whatever is being sent on the DIN pin is valid when shifting out data. When

no command is to be sent to the device when reading out data, send the NOP command on DIN. Make sure that

the t_SDECODEtiming is met in the Sending Multi-Byte Commands section when sending multiple byte commands

on DIN.

9.5.2.4 Data Output (DOUT)

DOUT is used with SCLK to read conversion and register data from the device. Data are clocked out on the

rising edge of SCLK, MSB first. DOUT goes to a high-impedance state when CS is high. Figure 45 shows the

ADS1299 data output protocol.

DRDY

CS

SCLK

216 SCLKs

DOUT

DIN

STAT

CH1

CH2

CH3

CH4

CH5

CH6

CH7

CH8

24-Bit

Figure 45. SPI Bus Data Output

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9.5.3 SPI Command Definitions

The ADS1299-x provides flexible configuration control. The commands, summarized in Table 10, control and

configure device operation. The commands are stand-alone, except for the register read and write operations

that require a second command byte plus data. CS can be taken high or held low between commands but must

stay low for the entire command operation (especially for multi-byte commands). System commands and the

RDATA command are decoded by the device on the seventh SCLK falling edge. The register read and write

commands are decoded on the eighth SCLK falling edge. Be sure to follow SPI timing requirements when pulling

CS high after issuing a command.

Table 10. Command Definitions

COMMAND

System Commands

WAKEUP

DESCRIPTION

FIRST BYTE

SECOND BYTE

Wake-up from standby mode

Enter standby mode

0000 0010 (02h)

0000 0100 (04h)

0000 0110 (06h)

0000 1000 (08h)

0000 1010 (0Ah)

STANDBY

RESET

Reset the device

START

Start and restart (synchronize) conversions

Stop conversion

STOP

Data Read Commands

Enable Read Data Continuous mode.

RDATAC

0001 0000 (10h)

This mode is the default mode at power-up.⁽¹⁾

SDATAC

RDATA

Stop Read Data Continuously mode

0001 0001 (11h)

0001 0010 (12h)

Read data by command; supports multiple read back.

Register Read Commands

RREG

WREG

Read n nnnn registers starting at address r rrrr

Write n nnnn registers starting at address r rrrr

001r rrrr (2xh)⁽²⁾

010r rrrr (4xh)⁽²⁾

000n nnnn⁽²⁾

(1) When in RDATAC mode, the RREG command is ignored.

(2) n nnnn = number of registers to be read or written – 1. For example, to read or write three registers, set n nnnn = 0 (0010). r rrrr =

starting register address for read or write commands.

9.5.3.1 Sending Multi-Byte Commands

The ADS1299-x serial interface decodes commands in bytes and requires 4 t_CLKcycles to decode and execute.

Therefore, when sending multi-byte commands (such as RREG or WREG), a 4 t_CLKperiod must separate the

end of one byte (or command) and the next.

Assuming CLK is 2.048 MHz, then t_SDECODE(4 t_CLK) is 1.96 µs. When SCLK is 16 MHz, one byte can be

transferred in 500 ns. This byte transfer time does not meet the t_SDECODEspecification; therefore, a delay must be

inserted so the end of the second byte arrives 1.46 µs later. If SCLK is 4 MHz, one byte is transferred in 2 µs.

Because this transfer time exceeds the t_SDECODEspecification, the processor can send subsequent bytes without

delay. In this later scenario, the serial port can be programmed to move from single-byte transfers per cycle to

multiple bytes.

9.5.3.2 WAKEUP: Exit STANDBY Mode

The WAKEUP command exits low-power standby mode; see the STANDBY: Enter STANDBY Mode subsection

of the SPI Command Definitions section. Time is required when exiting standby mode (see the Electrical

Characteristics for details). There are no SCLK rate restrictions for this command and can be issued at any

time. Any following commands must be sent after a delay of 4 t_CLKcycles.

9.5.3.3 STANDBY: Enter STANDBY Mode

The STANDBY command enters low-power standby mode. All parts of the circuit are shut down except for the

reference section. The standby mode power consumption is specified in the Electrical Characteristics. There are

no SCLK rate restrictions for this command and can be issued at any time. Do not send any other

commands other than the wakeup command after the device enters standby mode.

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9.5.3.4 RESET: Reset Registers to Default Values

The RESET command resets the digital filter cycle and returns all register settings to default values. See the

Reset (RESET) subsection of the SPI Interface section for more details. There are no SCLK rate restrictions

for this command and can be issued at any time. 18 t_CLKcycles are required to execute the RESET

command. Avoid sending any commands during this time.

9.5.3.5 START: Start Conversions

The START command starts data conversions. Tie the START pin low to control conversions by command. If

conversions are in progress, this command has no effect. The STOP command stops conversions. If the START

command is immediately followed by a STOP command, then there must be a 4-t_CLKcycle delay between them.

When the START command is sent to the device, keep the START pin low until the STOP command is issued.

(See the Start subsection of the SPI Interface section for more details.) There are no SCLK rate restrictions

for this command and can be issued at any time.

9.5.3.6 STOP: Stop Conversions

The STOP command stops conversions. Tie the START pin low to control conversions by command. When the

STOP command is sent, the conversion in progress completes and further conversions are stopped. If

conversions are already stopped, this command has no effect. There are no SCLK rate restrictions for this

command and can be issued at any time.

9.5.3.7 RDATAC: Read Data Continuous

The RDATAC command enables conversion data output on each DRDY without the need to issue subsequent

read data commands. This mode places the conversion data in the output register and may be shifted out

directly. The read data continuous mode is the device default mode; the device defaults to this mode on power-

up.

RDATAC mode is cancelled by the Stop Read Data Continuous command. If the device is in RDATAC mode, a

SDATAC command must be issued before any other commands can be sent to the device. There are no SCLK

rate restrictions for this command. However, subsequent data retrieval SCLKs or the SDATAC command

should wait at least 4 t_CLKcycles before completion (see the Sending Multi-Byte Commands section). RDATAC

timing is illustrated in Figure 46. As depicted in Figure 46, there is a keep out zone of 4 t_CLKcycles around the

DRDY pulse where this command cannot be issued in. If no data are retrieved from the device, DOUT and

DRDY behave similarly in this mode. To retrieve data from the device after the RDATAC command is issued,

make sure either the START pin is high or the START command is issued. Figure 46 shows the recommended

way to use the RDATAC command. RDATAC is ideally-suited for applications such as data loggers or recorders,

where registers are set one time and do not need to be reconfigured.

START

DRDY

t_UPDATE

CS

SCLK

RDATAC

DIN

Hi-Z

Status Register + 8-Channel Data (216 Bits)

DOUT

Next Data

(1) t_UPDATE= 4 / f_CLK. Do not read data during this time.

Figure 46. RDATAC Usage

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9.5.3.8 SDATAC: Stop Read Data Continuous

The SDATAC command cancels the Read Data Continuous mode. There are no SCLK rate restrictions for

this command, but the next command must wait for 4 t_CLKcycles before completion.

9.5.3.9 RDATA: Read Data

The RDATA command loads the output shift register with the latest data when not in Read Data Continuous

mode. Issue this command after DRDY goes low to read the conversion result. There are no SCLK rate

restrictions for this command, and there is no wait time needed for the subsequent commands or data retrieval

SCLKs. To retrieve data from the device after the RDATA command is issued, make sure either the START pin

is high or the START command is issued. When reading data with the RDATA command, the read operation can

overlap the next DRDY occurrence without data corruption. Figure 47 shows the recommended way to use the

RDATA command. RDATA is best suited for ECG- and EEG-type systems, where register settings must be read

or changed often between conversion cycles.

START

DRDY

CS

SCLK

RDATA

DIN

Hi-Z

Status Register+ 8-Channel Data (216 Bits)

DOUT

Figure 47. RDATA Usage

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9.5.3.10 RREG: Read From Register

This command reads register data. The Register Read command is a two-byte command followed by the register

data output. The first byte contains the command and register address. The second command byte specifies the

number of registers to read – 1.

First command byte: 001r rrrr, where r rrrr is the starting register address.

Second command byte: 000n nnnn, where n nnnn is the number of registers to read – 1.

The 17th SCLK rising edge of the operation clocks out the MSB of the first register, as shown in Figure 48. When

the device is in read data continuous mode, an SDATAC command must be issued before the RREG command

can be issued. The RREG command can be issued any time. However, because this command is a multi-byte

command, there are SCLK rate restrictions depending on how the SCLKs are issued to meet the t_SDECODEtiming.

See the Serial Clock (SCLK) subsection of the SPI Interface section for more details. Note that CS must be low

for the entire command.

CS

1

9

17

25

SCLK

DIN

BYTE 1

BYTE 2

REG DATA

REG DATA + 1

DOUT

Figure 48. RREG Command Example: Read Two Registers Starting from Register 00h (ID Register)

(BYTE 1 = 0010 0000, BYTE 2 = 0000 0001)

9.5.3.11 WREG: Write to Register

This command writes register data. The Register Write command is a two-byte command followed by the register

data input. The first byte contains the command and register address. The second command byte specifies the

number of registers to write – 1.

First command byte: 010r rrrr, where r rrrr is the starting register address.

Second command byte: 000n nnnn, where n nnnn is the number of registers to write – 1.

After the command bytes, the register data follows (in MSB-first format), as shown in Figure 49. The WREG

command can be issued any time. However, because this command is a multi-byte command, there are SCLK

rate restrictions depending on how the SCLKs are issued to meet the t_SDECODEtiming. See the Serial Clock

(SCLK) subsection of the SPI Interface section for more details. Note that CS must be low for the entire

command.

CS

1

9

17

25

SCLK

DIN

BYTE 1

BYTE 2

REG DATA 1

REG DATA 2

DOUT

Figure 49. WREG Command Example: Write Two Registers Starting from 00h (ID Register)

(BYTE 1 = 0100 0000, BYTE 2 = 0000 0001)

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9.6 Register Maps

Table 11 describes the various ADS1299-x registers.

Table 11. Register Assignments

REGISTER BITS

DEFAULT

SETTING

ADDRESS

REGISTER

7

6

5

4

3

2

1

0

Read Only ID Registers

00h

ID

xxh

REV_ID[2:0]

1

DEV_ID[1:0]

NU_CH[1:0]

Global Settings Across Channels

01h

02h

CONFIG1

CONFIG2

96h

C0h

1

DAISY_EN

1

CLK_EN

0

1

0

DR[2:0]

CAL_FREQ[1:0]

INT_CAL

CAL_AMP0

PD_BIAS

BIAS_LOFF_

SENS

03h

04h

CONFIG3

LOFF

60h

00h

PD_REFBUF

1

BIAS_MEAS

0

BIASREF_INT

BIAS_STAT

COMP_TH[2:0]

ILEAD_OFF[1:0]

FLEAD_OFF[1:0]

Channel-Specific Settings

05h

06h

07h

08h

09h

0Ah

0Bh

0Ch

0Dh

0Eh

0Fh

10h

11h

CH1SET

CH2SET

CH3SET

CH4SET

61h

00h

PD1

PD2

GAIN1[2:0]

GAIN2[2:0]

GAIN3[2:0]

GAIN4[2:0]

GAIN5[2:0]

GAIN6[2:0]

GAIN7[2:0]

GAIN8[2:0]

BIASP6⁽¹⁾

BIASN6⁽¹⁾

LOFFP6⁽¹⁾

LOFFM6⁽¹⁾

SRB2

MUX1[2:0]

MUX2[2:0]

MUX3[2:0]

MUX4[2:0]

MUX5[2:0]

MUX6[2:0]

MUX7[2:0]

MUX8[2:0]

BIASP2

PD3

SRB2

PD4

SRB2

(1)

CH5SET

CH6SET

CH7SET

CH8SET

PD5

SRB2

(1)

(2)

PD6

SRB2

PD7

SRB2

PD8

SRB2

BIAS_SENSP

BIAS_SENSN

LOFF_SENSP

LOFF_SENSN

LOFF_FLIP

BIASP8⁽²⁾

BIASN8⁽²⁾

LOFFP8⁽²⁾

LOFFM8⁽²⁾

BIASP7⁽²⁾

BIASN7⁽²⁾

LOFFP7⁽²⁾

LOFFM7⁽²⁾

BIASP5⁽¹⁾

BIASN5⁽¹⁾

LOFFP5⁽¹⁾

LOFFM5⁽¹⁾

BIASP4

BIASN4

LOFFP4

LOFFM4

LOFF_FLIP4

BIASP3

BIASN3

BIASP1

BIASN1

BIASN2

LOFFP3

LOFFP2

LOFFP1

LOFFM3

LOFF_FLIP3

LOFFM2

LOFFM1

LOFF_FLIP1

LOFF_FLIP8⁽²⁾LOFF_FLIP7⁽²⁾LOFF_FLIP6⁽¹⁾LOFF_FLIP5⁽¹⁾

LOFF_FLIP2

Lead-Off Status Registers (Read-Only Registers)

12h

13h

LOFF_STATP

LOFF_STATN

00h

IN8P_OFF

IN8M_OFF

IN7P_OFF

IN7M_OFF

IN6P_OFF

IN6M_OFF

IN5P_OFF

IN5M_OFF

IN4P_OFF

IN4M_OFF

IN3P_OFF

IN3M_OFF

IN2P_OFF

IN2M_OFF

IN1P_OFF

IN1M_OFF

GPIO and OTHER Registers

14h

15h

16h

GPIO

MISC1

MISC2

0Fh

00h

GPIOD[4:1]

GPIOC[4:1]

0

SRB1

0

SINGLE_

SHOT

PD_LOFF_

COMP

17h

CONFIG4

00h

0

(1) Register or bit only available in the ADS1299-6 and ADS1299. Register bits set to 0h or 00h in the ADS1299-4.

(2) Register or bit only available in the ADS1299. Register bits set to 0h or 00h in the ADS1299-4 and ADS1299-6.

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9.6.1 User Register Description

The read-only ID control register is programmed during device manufacture to indicate device characteristics.

9.6.1.1 ID: ID Control Register (address = 00h) (reset = xxh)

Figure 50. ID Control Register

7

6

5

4

1

3

2

1

0

REV_ID[2:0]

R-xh

DEV_ID[1:0]

R-3h

NU_CH[1:0]

R-xh

R-1h

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 12. ID Control Register Field Descriptions

Bit

Field

Type

Reset

Description

7:5

REV_ID[2:0]

R

xh

Reserved.

These bits indicate the revision of the device and are subject to

change without notice.

4

Reserved

R

1h

3h

Reserved.

Always read 1.

3:2

DEV_ID[1:0]

Device Identification.

These bits indicates the device.

11 : ADS1299-x

1:0

NU_CH[1:0]

R

xh

Number of Channels.

These bits indicates number of channels.

00 : 4-channel ADS1299-4

01 : 6-channel ADS1299-6

10 : 8-channel ADS1299

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9.6.1.2 CONFIG1: Configuration Register 1 (address = 01h) (reset = 96h)

This register configures the DAISY_EN bit, clock, and data rate.

Figure 51. CONFIG1: Configuration Register 1

7

1

6

5

4

1

3

0

2

1

0

DAISY_EN

R/W-0h

CLK_EN

R/W-0h

DR[2:0]

R/W-6h

R/W-1h

R/W-0h

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 13. Configuration Register 1 Field Descriptions

Bit

Field

Type

Reset

Description

7

Reserved

R/W

1h

Reserved

Always write 1h

6

5

DAISY_EN

CLK_EN

R/W

0h

Daisy-chain or multiple readback mode

This bit determines which mode is enabled.

0 : Daisy-chain mode

1 : Multiple readback mode

CLK connection⁽¹⁾

This bit determines if the internal oscillator signal is connected to

the CLK pin when the CLKSEL pin = 1.

0 : Oscillator clock output disabled

1 : Oscillator clock output enabled

4:3

2:0

Reserved

DR[2:0]

R/W

2h

6h

Reserved

Always write 2h

Output data rate

These bits determine the output data rate of the device. f_MOD

f_CLK/ 2.

=

000 : f_MOD/ 64 (16 kSPS)

001 : f_MOD/ 128 (8 kSPS)

010 : f_MOD/ 256 (4 kSPS)

011 : f_MOD/ 512 (2 kSPS)

100 : f_MOD/ 1024 (1 kSPS)

101 : f_MOD/ 2048 (500 SPS)

110 : f_MOD/ 4096 (250 SPS)

111 : Reserved (do not use)

(1) Additional power is consumed when driving external devices.

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9.6.1.3 CONFIG2: Configuration Register 2 (address = 02h) (reset = C0h)

This register configures the test signal generation. See the Input Multiplexer section for more details.

Figure 52. CONFIG2: Configuration Register 2

7

1

6

1

5

0

4

3

0

2

1

0

INT_CAL

R/W-0h

CAL_AMP

R/W-0h

CAL_FREQ[1:0]

R/W-0h

R/W-1h

R/W-0h

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 14. Configuration Register 2 Field Descriptions

Bit

Field

Type

Reset

Description

7:5

Reserved

R/W

6h

Reserved

Always write 6h

4

INT_CAL

R/W

0h

TEST source

This bit determines the source for the test signal.

0 : Test signals are driven externally

1 : Test signals are generated internally

3

2

Reserved

CAL_AMP

R/W

0h

Reserved

Always write 0h

Test signal amplitude

These bits determine the calibration signal amplitude.

0 : 1 × –(VREFP – VREFN) / 2400

1 : 2 × –(VREFP – VREFN) / 2400

1:0

CAL_FREQ[1:0]

R/W

0h

Test signal frequency

These bits determine the calibration signal frequency.

00 : Pulsed at f_CLK/ 2²¹

01 : Pulsed at f_CLK/ 2²⁰

10 : Do not use

11 : At dc

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9.6.1.4 CONFIG3: Configuration Register 3 (address = 03h) (reset = 60h)

Configuration register 3 configures either an internal or exteral reference and BIAS operation.

Figure 53. CONFIG3: Configuration Register 3

7

6

1

5

1

4

3

2

1

0

BIAS_LOFF_

SENS

PD_REFBUF

R/W-0h

BIAS_MEAS

R/W-0h

BIASREF_INT

R/W-0h

PD_BIAS

R/W-0h

BIAS_STAT

R-0h

R/W-1h

R/W-0h

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 15. Configuration Register 3 Field Descriptions

Bit

Field

Type

Reset

Description

7

PD_REFBUF

R/W

0h

Power-down reference buffer

This bit determines the power-down reference buffer state.

0 : Power-down internal reference buffer

1 : Enable internal reference buffer

6:5

4

Reserved

R/W

3h

0h

Reserved

Always write 3h.

BIAS_MEAS

BIAS measurement

This bit enables BIAS measurement. The BIAS signal may be

measured with any channel.

0 : Open

1 : BIAS_IN signal is routed to the channel that has the

MUX_Setting 010 (V_REF

)

3

2

1

0

BIASREF_INT

PD_BIAS

R/W

R

0h

BIASREF signal

This bit determines the BIASREF signal source.

0 : BIASREF signal fed externally

1 : BIASREF signal (AVDD + AVSS) / 2 generated internally

BIAS buffer power

This bit determines the BIAS buffer power state.

0 : BIAS buffer is powered down

1 : BIAS buffer is enabled

BIAS_LOFF_SENS

BIAS_STAT

BIAS sense function

This bit enables the BIAS sense function.

0 : BIAS sense is disabled

1 : BIAS sense is enabled

BIAS lead-off status

This bit determines the BIAS status.

0 : BIAS is connected

1 : BIAS is not connected

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9.6.1.5 LOFF: Lead-Off Control Register (address = 04h) (reset = 00h)

The lead-off control register configures the lead-off detection operation.

Figure 54. LOFF: Lead-Off Control Register

7

6

5

4

0

3

2

1

0

COMP_TH2[2:0]

R/W-0h

ILEAD_OFF[1:0]

R/W-0h

FLEAD_OFF[1:0]

R/W-0h

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 16. Lead-Off Control Register Field Descriptions

Bit

Field

Type

Reset

Description

7:5

COMP_TH[2:0]

R/W

0h

Lead-off comparator threshold

Comparator positive side

000 : 95%

001 : 92.5%

010 : 90%

011 : 87.5%

100 : 85%

101 : 80%

110 : 75%

111 : 70%

Comparator negative side

000 : 5%

001 : 7.5%

010 : 10%

011 : 12.5%

100 : 15%

101 : 20%

110 : 25%

111 : 30%

4

Reserved

R/W

0h

Reserved

Always write 0h.

3:2

ILEAD_OFF[1:0]

Lead-off current magnitude

These bits determine the magnitude of current for the current

lead-off mode.

00 : 6 nA

01 : 24 nA

10 : 6 µA

11 : 24 µA

1:0

FLEAD_OFF[1:0]

R/W

0h

Lead-off frequency

These bits determine the frequency of lead-off detect for each

channel.

00 : DC lead-off detection

01 : AC lead-off detection at 7.8 Hz (f_CLK/ 2¹⁸

)

10 : AC lead-off detection at 31.2 Hz (f_CLK/ 2¹⁶

11 : AC lead-off detection at f_DR/ 4

)

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9.6.1.6 CHnSET: Individual Channel Settings (n = 1 to 8) (address = 05h to 0Ch) (reset = 61h)

The CH[1:8]SET control register configures the power mode, PGA gain, and multiplexer settings channels. See

the Input Multiplexer section for details. CH[2:8]SET are similar to CH1SET, corresponding to the respective

channels.

Figure 55. CHnSET: Individual Channel Settings Register

7

6

5

4

3

2

1

0

PDn

GAINn[2:0]

R/W-6h

SRB2

R/W-0h

MUXn[2:0]

R/W-0h

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 17. Individual Channel Settings (n = 1 to 8) Field Descriptions

Bit

Field

Type

Reset

Description

7

PDn

R/W

0h

Power-down

This bit determines the channel power mode for the

corresponding channel.

0 : Normal operation

1 : Channel power-down.

When powering down a channel, TI recommends that the

channel be set to input short by setting the appropriate

MUXn[2:0] = 001 of the CHnSET register.

6:4

GAINn[2:0]

R/W

6h

PGA gain

These bits determine the PGA gain setting.

000 : 1

001 : 2

010 : 4

011 : 6

100 : 8

101 : 12

110 : 24

111 : Do not use

3

SRB2

R/W

0h

1h

SRB2 connection

This bit determines the SRB2 connection for the corresponding

channel.

0 : Open

1 : Closed

2:0

MUXn[2:0]

Channel input

These bits determine the channel input selection.

000 : Normal electrode input

001 : Input shorted (for offset or noise measurements)

010 : Used in conjunction with BIAS_MEAS bit for BIAS

measurements.

011 : MVDD for supply measurement

100 : Temperature sensor

101 : Test signal

110 : BIAS_DRP (positive electrode is the driver)

111 : BIAS_DRN (negative electrode is the driver)

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9.6.1.7 BIAS_SENSP: Bias Drive Positive Derivation Register (address = 0Dh) (reset = 00h)

This register controls the selection of the positive signals from each channel for bias voltage (BIAS) derivation.

See the Bias Drive (DC Bias Circuit) section for details.

Registers bits[5:4] are not available for the ADS1299-4. Register bits[7:6] are not available for the ADS1299-4, or

ADS1299-6. Set unavailable bits for the associated device to 0 when writing to the register.

Figure 56. BIAS_SENSP: BIAS Positive Signal Derivation Register

7

6

5

4

3

2

1

0

BIASP8

R/W-0h

BIASP7

R/W-0h

BIASP6

R/W-0h

BIASP5

R/W-0h

BIASP4

R/W-0h

BIASP3

R/W-0h

BIASP2

R/W-0h

BIASP1

R/W-0h

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 18. BIAS Positive Signal Derivation Field Descriptions

Bit

Field

Type

Reset

Description

7

BIASP8

R/W

0h

IN8P to BIAS

Route channel 8 positive signal into BIAS derivation

0 : Disabled

1 : Enabled

6

5

4

3

2

1

0

BIASP7

BIASP6

BIASP5

BIASP4

BIASP3

BIASP2

BIASP1

R/W

0h

IN7P to BIAS

Route channel 7 positive signal into BIAS derivation

0 : Disabled

1 : Enabled

IN6P to BIAS

Route channel 6 positive signal into BIAS derivation

0 : Disabled

1 : Enabled

IN5P to BIAS

Route channel 5 positive signal into BIAS derivation

0 : Disabled

1 : Enabled

IN4P to BIAS

Route channel 4 positive signal into BIAS derivation

0 : Disabled

1 : Enabled

IN3P to BIAS

Route channel 3 positive signal into BIAS derivation

0 : Disabled

1 : Enabled

IN2P to BIAS

Route channel 2 positive signal into BIAS channel

0 : Disabled

1 : Enabled

IN1P to BIAS

Route channel 1 positive signal into BIAS channel

0 : Disabled

1 : Enabled

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9.6.1.8 BIAS_SENSN: Bias Drive Negative Derivation Register (address = 0Eh) (reset = 00h)

This register controls the selection of the negative signals from each channel for bias voltage (BIAS) derivation.

See the Bias Drive (DC Bias Circuit) section for details.

Registers bits[5:4] are not available for the ADS1299-4. Register bits[7:6] are not available for the ADS1299-4, or

ADS1299-6. Set unavailable bits for the associated device to 0 when writing to the register.

Figure 57. BIAS_SENSN: BIAS Negative Signal Derivation Register

7

6

5

4

3

2

1

0

BIASN8

R/W-0h

BIASN7

R/W-0h

BIASN6

R/W-0h

BIASN5

R/W-0h

BIASN4

R/W-0h

BIASN3

R/W-0h

BIASN2

R/W-0h

BIASN1

R/W-0h

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 19. BIAS Negative Signal Derivation Field Descriptions

Bit

Field

Type

Reset

Description

7

BIASN8

R/W

0h

IN8N to BIAS

Route channel 8 negative signal into BIAS derivation

0 : Disabled

1 : Enabled

6

5

4

3

2

1

0

BIASN7

BIASN6

BIASN5

BIASN4

BIASN3

BIASN2

BIASN1

R/W

0h

IN7N to BIAS

Route channel 7 negative signal into BIAS derivation

0 : Disabled

1 : Enabled

IN6N to BIAS

Route channel 6 negative signal into BIAS derivation

0 : Disabled

1 : Enabled

IN5N to BIAS

Route channel 5 negative signal into BIAS derivation

0 : Disabled

1 : Enabled

IN4N to BIAS

Route channel 4 negative signal into BIAS derivation

0 : Disabled

1 : Enabled

IN3N to BIAS

Route channel 3 negative signal into BIAS derivation

0 : Disabled

1 : Enabled

IN2N to BIAS

Route channel 2 negative signal into BIAS derivation

0 : Disabled

1 : Enabled

IN1N to BIAS

Route channel 1 negative signal into BIAS derivation

0 : Disabled

1 : Enabled

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9.6.1.9 LOFF_SENSP: Positive Signal Lead-Off Detection Register (address = 0Fh) (reset = 00h)

This register selects the positive side from each channel for lead-off detection. See the Lead-Off Detection

section for details. The LOFF_STATP register bits are only valid if the corresponding LOFF_SENSP bits are set

to 1.

Registers bits[5:4] are not available for the ADS1299-4. Register bits[7:6] are not available for the ADS1299-4, or

ADS1299-6. Set unavailable bits for the associated device to 0 when writing to the register.

Figure 58. LOFF_SENSP: Positive Signal Lead-Off Detection Register

7

6

5

4

3

2

1

0

LOFFP8

R/W-0h

LOFFP7

R/W-0h

LOFFP6

R/W-0h

LOFFP5

R/W-0h

LOFFP4

R/W-0h

LOFFP3

R/W-0h

LOFFP2

R/W-0h

LOFFP1

R/W-0h

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 20. Positive Signal Lead-Off Detection Field Descriptions

Bit

Field

Type

Reset

Description

7

LOFFP8

R/W

0h

IN8P lead off

Enable lead-off detection on IN8P

0 : Disabled

1 : Enabled

6

5

4

3

2

1

0

LOFFP7

LOFFP6

LOFFP5

LOFFP4

LOFFP3

LOFFP2

LOFFP1

R/W

0h

IN7P lead off

Enable lead-off detection on IN7P

0 : Disabled

1 : Enabled

IN6P lead off

Enable lead-off detection on IN6P

0 : Disabled

1 : Enabled

IN5P lead off

Enable lead-off detection on IN5P

0 : Disabled

1 : Enabled

IN4P lead off

Enable lead-off detection on IN4P

0 : Disabled

1 : Enabled

IN3P lead off

Enable lead-off detection on IN3P

0 : Disabled

1 : Enabled

IN2P lead off

Enable lead-off detection on IN2P

0 : Disabled

1 : Enabled

IN1P lead off

Enable lead-off detection on IN1P

0 : Disabled

1 : Enabled

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9.6.1.10 LOFF_SENSN: Negative Signal Lead-Off Detection Register (address = 10h) (reset = 00h)

This register selects the negative side from each channel for lead-off detection. See the Lead-Off Detection

section for details. The LOFF_STATN register bits are only valid if the corresponding LOFF_SENSN bits are set

to 1.

Registers bits[5:4] are not available for the ADS1299-4. Register bits[7:6] are not available for the ADS1299-4, or

ADS1299-6. Set unavailable bits for the associated device to 0 when writing to the register.

Figure 59. LOFF_SENSN: Negative Signal Lead-Off Detection Register

7

6

5

4

3

2

1

0

LOFFM8

R/W-0h

LOFFM7

R/W-0h

LOFFM6

R/W-0h

LOFFM5

R/W-0h

LOFFM4

R/W-0h

LOFFM3

R/W-0h

LOFFM2

R/W-0h

LOFFM1

R/W-0h

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 21. Negative Signal Lead-Off Detection Field Descriptions

Bit

Field

Type

Reset

Description

7

LOFFM8

R/W

0h

IN8N lead off

Enable lead-off detection on IN8N

0 : Disabled

1 : Enabled

6

5

4

3

2

1

0

LOFFM7

LOFFM6

LOFFM5

LOFFM4

LOFFM3

LOFFM2

LOFFM1

R/W

0h

IN7N lead off

Enable lead-off detection on IN7N

0 : Disabled

1 : Enabled

IN6N lead off

Enable lead-off detection on IN6N

0 : Disabled

1 : Enabled

IN5N lead off

Enable lead-off detection on IN5N

0 : Disabled

1 : Enabled

IN4N lead off

Enable lead-off detectionn on IN4N

0 : Disabled

1 : Enabled

IN3N lead off

Enable lead-off detectionion on IN3N

0 : Disabled

1 : Enabled

IN2N lead off

Enable lead-off detectionction on IN2N

0 : Disabled

1 : Enabled

IN1N lead off

Enable lead-off detectionction on IN1N

0 : Disabled

1 : Enabled

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9.6.1.11 LOFF_FLIP: Lead-Off Flip Register (address = 11h) (reset = 00h)

This register controls the direction of the current used for lead-off derivation. See the Lead-Off Detection section

for details.

Figure 60. LOFF_FLIP: Lead-Off Flip Register

7

6

5

4

3

2

1

0

LOFF_FLIP8

R/W-0h

LOFF_FLIP7

R/W-0h

LOFF_FLIP6

R/W-0h

LOFF_FLIP5

R/W-0h

LOFF_FLIP4

R/W-0h

LOFF_FLIP3

R/W-0h

LOFF_FLIP2

R/W-0h

LOFF_FLIP1

R/W-0h

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 22. Lead-Off Flip Register Field Descriptions

Bit

Field

Type

Reset

Description

7

LOFF_FLIP8

R/W

0h

Channel 8 LOFF polarity flip

Flip the pull-up or pull-down polarity of the current source on

channel 8 for lead-off detection.

0 : No flip = IN8P is pulled to AVDD and IN8N pulled to AVSS

1 : Flipped = IN8P is pulled to AVSS and IN8N pulled to AVDD

6

5

4

3

2

1

0

LOFF_FLIP7

LOFF_FLIP6

LOFF_FLIP5

LOFF_FLIP4

LOFF_FLIP3

LOFF_FLIP2

LOFF_FLIP1

R/W

0h

Channel 7 LOFF polarity flip

Flip the pull-up or pull-down polarity of the current source on

channel 7 for lead-off detection.

0 : No flip = IN7P is pulled to AVDD and IN7N pulled to AVSS

1 : Flipped = IN7P is pulled to AVSS and IN7N pulled to AVDD

Channel 6 LOFF polarity flip

Flip the pull-up or pull-down polarity of the current source on

channel 6 for lead-off detection.

0 : No flip = IN6P is pulled to AVDD and IN6N pulled to AVSS

1 : Flipped = IN6P is pulled to AVSS and IN6N pulled to AVDD

Channel 5 LOFF polarity flip

Flip the pull-up or pull-down polarity of the current source on

channel 5 for lead-off detection.

0 : No flip = IN5P is pulled to AVDD and IN5N pulled to AVSS

1 : Flipped = IN5P is pulled to AVSS and IN5N pulled to AVDD

Channel 4 LOFF polarity flip

Flip the pull-up or pull-down polarity of the current source on

channel 4 for lead-off detection.

0 : No flip = IN4P is pulled to AVDD and IN4N pulled to AVSS

1 : Flipped = IN4P is pulled to AVSS and IN4N pulled to AVDD

Channel 3 LOFF polarity flip

Flip the pull-up or pull-down polarity of the current source on

channel 3 for lead-off detection.

0 : No flip = IN3P is pulled to AVDD and IN3N pulled to AVSS

1 : Flipped = IN3P is pulled to AVSS and IN3N pulled to AVDD

Channel 2 LOFF Polarity Flip

Flip the pull-up or pull-down polarity of the current source on

channel 2 for lead-off detection.

0 : No flip = IN2P is pulled to AVDD and IN2N pulled to AVSS

1 : Flipped = IN2P is pulled to AVSS and IN2N pulled to AVDD

Channel 1 LOFF Polarity Flip

Flip the pull-up or pull-down polarity of the current source on

channel 1 for lead-off detection.

0 : No flip = IN1P is pulled to AVDD and IN1N pulled to AVSS

1 : Flipped = IN1P is pulled to AVSS and IN1N pulled to AVDD

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9.6.1.12 LOFF_STATP: Lead-Off Positive Signal Status Register (address = 12h) (reset = 00h)

This register stores the status of whether the positive electrode on each channel is on or off. See the Lead-Off

Detection section for details. Ignore the LOFF_STATP values if the corresponding LOFF_SENSP bits are not set

to 1.

When the LOFF_SENSEP bits are 0, the LOFF_STATP bits should be ignored.

Figure 61. LOFF_STATP: Lead-Off Positive Signal Status Register (Read-Only)

7

6

5

4

3

2

1

0

IN8P_OFF

R-0h

IN7P_OFF

R-0h

IN6P_OFF

R-0h

IN5P_OFF

R-0h

IN4P_OFF

R-0h

IN3P_OFF

R-0h

IN2P_OFF

R-0h

IN1P_OFF

R-0h

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 23. Lead-Off Positive Signal Status Field Descriptions

Bit

Field

Type

Reset

Description

7

IN8P_OFF

R

0h

Channel 8 positive channel lead-off status

Status of whether IN8P electrode is on or off

0 : Electrode is on

1 : Electrode is off

6

5

4

3

2

1

0

IN7P_OFF

IN6P_OFF

IN5P_OFF

IN4P_OFF

IN3P_OFF

IN2P_OFF

IN1P_OFF

R

0h

Channel 7 positive channel lead-off status

Status of whether IN7P electrode is on or off

0 : Electrode is on

1 : Electrode is off

Channel 6 positive channel lead-off status

Status of whether IN6P electrode is on or off

0 : Electrode is on

1 : Electrode is off

Channel 5 positive channel lead-off status

Status of whether IN5P electrode is on or off

0 : Electrode is on

1 : Electrode is off

Channel 4 positive channel lead-off status

Status of whether IN4P electrode is on or off

0 : Electrode is on

1 : Electrode is off

Channel 3 positive channel lead-off status

Status of whether IN3P electrode is on or off

0 : Electrode is on

1 : Electrode is off

Channel 2 positive channel lead-off status

Status of whether IN2P electrode is on or off

0 : Electrode is on

1 : Electrode is off

Channel 1 positive channel lead-off status

Status of whether IN1P electrode is on or off

0 : Electrode is on

1 : Electrode is off

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9.6.1.13 LOFF_STATN: Lead-Off Negative Signal Status Register (address = 13h) (reset = 00h)

This register stores the status of whether the negative electrode on each channel is on or off. See the Lead-Off

Detection section for details. Ignore the LOFF_STATN values if the corresponding LOFF_SENSN bits are not set

to 1.

When the LOFF_SENSEN bits are 0, the LOFF_STATP bits should be ignored.

Figure 62. LOFF_STATN: Lead-Off Negative Signal Status Register (Read-Only)

7

6

5

4

3

2

1

0

IN8N_OFF

R-0h

IN7N_OFF

R-0h

IN6N_OFF

R-0h

IN5N_OFF

R-0h

IN4N_OFF

R-0h

IN3N_OFF

R-0h

IN2N_OFF

R-0h

IN1N_OFF

R-0h

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 24. Lead-Off Negative Signal Status Field Descriptions

Bit

Field

Type

Reset

Description

7

IN8N_OFF

R

0h

Channel 8 negative channel lead-off status

Status of whether IN8N electrode is on or off

0 : Electrode is on

1 : Electrode is off

6

5

4

3

2

1

0

IN7N_OFF

IN6N_OFF

IN5N_OFF

IN4N_OFF

IN3N_OFF

IN2N_OFF

IN1N_OFF

R

0h

Channel 7 negative channel lead-off status

Status of whether IN7N electrode is on or off

0 : Electrode is on

1 : Electrode is off

Channel 6 negative channel lead-off status

Status of whether IN6N electrode is on or off

0 : Electrode is on

1 : Electrode is off

Channel 5 negative channel lead-off status

Status of whether IN5N electrode is on or off

0 : Electrode is on

1 : Electrode is off

Channel 4 negative channel lead-off status

Status of whether IN4N electrode is on or off

0 : Electrode is on

1 : Electrode is off

Channel 3 negative channel lead-off status

Status of whether IN3N electrode is on or off

0 : Electrode is on

1 : Electrode is off

Channel 2 negative channel lead-off status

Status of whether IN2N electrode is on or off

0 : Electrode is on

1 : Electrode is off

Channel 1 negative channel lead-off status

Status of whether IN1N electrode is on or off

0 : Electrode is on

1 : Electrode is off

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9.6.1.14 GPIO: General-Purpose I/O Register (address = 14h) (reset = 0Fh)

The general-purpose I/O register controls the action of the three GPIO pins. When RESP_CTRL[1:0] is in mode

01 and 11, the GPIO2, GPIO3, and GPIO4 pins are not available for use.

Figure 63. GPIO: General-Purpose I/O Register

7

6

5

4

3

2

1

0

GPIOD[4:1]

R/W-0h

GPIOC[4:1]

R/W-Fh

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 25. General-Purpose I/O Field Descriptions

Bit

Field

Type

Reset

Description

7:4

GPIOD[4:1]

R/W

0h

GPIO data

These bits are used to read and write data to the GPIO ports.

When reading the register, the data returned correspond to the

state of the GPIO external pins, whether they are programmed

as inputs or as outputs. As outputs, a write to the GPIOD sets

the output value. As inputs, a write to the GPIOD has no effect.

GPIO is not available in certain respiration modes.

3:0

GPIOC[4:1]

R/W

Fh

GPIO control (corresponding GPIOD)

These bits determine if the corresponding GPIOD pin is an input

or output.

0 : Output

1 : Input

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9.6.1.15 MISC1: Miscellaneous 1 Register (address = 15h) (reset = 00h)

This register provides the control to route the SRB1 pin to all inverting inputs of the four, six, or eight channels

(ADS1299-4, ADS1299-6, or ADS1299).

Figure 64. MISC1: Miscellaneous 1 Register

7

0

6

0

5

4

0

3

0

2

0

1

0

SRB1

R/W-0h

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 26. Miscellaneous 1 Register Field Descriptions

Bit

Field

Type

Reset

Description

7:6

Reserved

R/W

0h

Reserved

Always write 0h

5

SRB1

R/W

0h

Stimulus, reference, and bias 1

This bit connects the SRB1 to all 4, 6, or 8 channels inverting

inputs

0 : Switches open

1 : Switches closed

4:0

Reserved

Always write 0h

9.6.1.16 MISC2: Miscellaneous 2 (address = 16h) (reset = 00h)

This register is reserved for future use.

Figure 65. MISC1: Miscellaneous 1 Register

7

0

6

0

5

0

4

0

3

0

2

0

1

0

R/W-0h

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 27. Miscellaneous 1 Register Field Descriptions

Bit

Field

Type

Reset

Description

7:0

Reserved

R/W

0h

Reserved

Always write 0h

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9.6.1.17 CONFIG4: Configuration Register 4 (address = 17h) (reset = 00h)

This register configures the conversion mode and enables the lead-off comparators.

Figure 66. CONFIG4: Configuration Register 4

7

0

6

0

5

0

4

0

3

2

0

1

0

PD_LOFF_

COMP

SINGLE_SHOT

R/W-0h

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 28. Configuration Register 4 Field Descriptions

Bit

Field

Type

Reset

Description

7:4

Reserved

R/W

0h

Reserved

Always write 0h

3

SINGLE_SHOT

R/W

0h

Single-shot conversion

This bit sets the conversion mode.

0 : Continuous conversion mode

1 : Single-shot mode

2

1

Reserved

R/W

0h

Reserved

Always write 0h

PD_LOFF_COMP

Lead-off comparator power-down

This bit powers down the lead-off comparators.

0 : Lead-off comparators disabled

1 : Lead-off comparators enabled

0

Reserved

R/W

0h

Reserved

Always write 0h

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10 Applications and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

10.1 Application Information

10.1.1 Unused Inputs and Outputs

Power down unused analog inputs and connect them directly to AVDD.

Power down the Bias amplifier if unused and float BIASOUT and BIASINV. BIASIN can also float or can be tied

directly to AVSS if unused.

Tie BIASREF directly to AVSS or leave floating if unused.

Tie SRB1 and SRB2 directly to AVSS or leave them floating if unused.

Do not float unused digital inputs because excessive power-supply leakage current might result. Set the two-

state mode setting pins high to DVDD or low to DGND through ≥10-kΩ resistors.

Pull DRDY to supply using weak pullup resistor if unused.

If not daisy-chaining devices, tie DAISYIN directly to DGND.

10.1.2 Setting the Device for Basic Data Capture

Figure 67 outlines the procedure to configure the device in a basic state and capture data. This procedure puts

the device into a configuration that matches the parameters listed in the specifications section, in order to check

if the device is working properly in the user system. Follow this procedure initially until familiar with the device

settings. After this procedure has been verified, the device can be configured as needed. For details on the

timings for commands, see the appropriate sections in the data sheet. Sample programming codes are added for

the ECG and EEG-specific functions.

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Application Information (continued)

Analog and Digital Power-Up

// Follow Power-Up Sequencing

Set CLKSEL Pin = 0

and Provide External Clock

f_CLK= 2.048 MHz

Yes

External

Clock

No

Set CLKSEL Pin = 1

and Wait for Oscillator

to Wake Up

// If START is Tied High, After This Step

// DRDY Toggles at f_CLK/ 8192

Set PDWN = 1

Set RESET = 1

Wait > t_PORfor

Power-On Reset

// Delay for Power-On Reset and Oscillator Start-Up

No

VCAP1 ≥ 1.1 V

// If VCAP1 < 1.1 V at t_POR, continue waiting until VCAP ≥ 1.1 V

// Activate DUT

// CS can be Either Tied Low Or Selectively

// Pulled Low Before Sending Commands and

// Data to the Device or Reading Data From

// The Device

Issue Reset Pulse,

Wait for 18 tCLKs

// Device Wakes Up in RDATAC Mode, so Send

// SDATAC Command so Registers can be Written

SDATAC

Send SDATAC

Command

No

Set PDB_REFBUF = 1

and Wait for Internal Reference

to Settle

External

Reference

// If Using Internal Reference, Send This Command

WREG CONFIG3 E0h

Yes

// Set Device for DR = f_MOD/ 4096

WREG CONFIG1 96h

WREG CONFIG2 C0h

// Set All Channels to Input Short

WREG CHnSET 01h

Write Certain Registers,

Including Input Short

// Activate Conversion

// After This Point DRDY Toggles at

// f_CLK/ 8192

Set START = 1

RDATAC

// Put the Device Back in RDATAC Mode

RDATAC

Capture Data

and Check Noise

// Look for DRDY and Issue 24 + n x 24 SCLKs

// Activate a (1 mV x V_REF/ 2.4) Square-Wave Test Signal

// On All Channels

SDATAC

WREG CONFIG2 D0h

WREG CHnSET 05h

RDATAC

Set Test Signals

Capture Data

and Test Signal

// Look for DRDY and Issue 24 + n x 24 SCLKs

Figure 67. Initial Flow at Power-Up

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Application Information (continued)

10.1.2.1 Lead-Off

Sample code to set dc lead-off with pull-up and pull-down resistors on all channels.

WREG LOFF

0x13

// Comparator threshold at 95% and 5%, pullup or pulldown resistor

// dc lead-off

WREG CONFIG4

WREG LOFF_SENSP 0xFF

WREG LOFF_SENSN 0xFF

0x02

// Turn on dc lead-off comparators

// Turn on the P-side of all channels for lead-off sensing

// Turn on the N-side of all channels for lead-off sensing

Observe the status bits of the output data stream to monitor lead-off status.

10.1.2.2 Bias Drive

Sample code to choose bias as an average of the first three channels.

WREG RLD_SENSP 0x07

WREG RLD_SENSN 0x07

// Select channel 1-3 P-side for RLD sensing

// Select channel 1-3 N-side for RLD sensing

WREG CONFIG3

b’x1xx 1100 // Turn on BIAS amplifier, set internal BIASREF voltage

Sample code to route the BIASOUT signal through channel 4 N-side and measure bias with channel 5. Make

sure the external side to the chip BIASOUT is connected to BIASIN.

WREG CONFIG3 b’xxx1 1100 // Turn on BIAS amp, set internal BIASREF voltage, set BIAS measurement bit

WREG CH4SET b’xxxx 0111 // Route BIASIN to channel 4 N-side

WREG CH5SET b’xxxx 0010 // Route BIASIN to be measured at channel 5 w.r.t BIASREF

10.1.3 Establishing the Input Common-Mode

The ADS1299-x measures fully-differential signals where the common-mode voltage point is the midpoint of the

positive and negative analog input. The internal PGA restricts the common-mode input range because of the

headroom required for operation. The human body is prone to common-mode drifts because noise easily couples

onto the human body, similar to an antenna. These common-mode drifts may push the ADS1299-x input

common-mode voltage out of the measurable range of the ADC.

If a patient-drive electrode is used by the system, the ADS1299-x includes an on-chip bias drive (BIAS) amplifier

that connects to the patient drive electrode. The BIAS amplifier function is to bias the patient to maintain the

other electrode common-mode voltages within the valid range. When powered on, the amplifier uses either the

analog midsupply voltage, or the voltage present at the BIASREF pin, as a reference input to drive the patient to

that voltage.

The ADS1299-x provides the option to use input electrode voltages as feedback to the amplifier to more

effectively stabilize the output to the amplifier reference voltage by setting corresponding bits in the

BIAS_SENSP and BIAS_SENSN registers. Figure 68 shows an example of a three-electrode system that

leverages this technique.

Antialiasing,

Protection

Electrode 1

INxP

Antialiasing,

Protection

INxN

Electrode 2

TI Device

BIASINV

1.5 nF

1 Mꢀ

BIAS Electrode

Protection

BIASOUT

Figure 68. Setting Common-Mode Using BIAS Electrode

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Application Information (continued)

10.1.4 Multiple Device Configuration

The ADS1299-x is designed to provide configuration flexibility when multiple devices are used in a system. The

serial interface typically needs four signals: DIN, DOUT, SCLK, and CS. With one additional chip select signal

per device, multiple devices can be connected together. The number of signals needed to interface n devices is

3 + n.

The BIAS drive amplifiers can be daisy-chained, as explained in the Bias Configuration with Multiple Devices

section. To use the internal oscillator in a daisy-chain configuration, one device must be set as the master for the

clock source with the internal oscillator enabled (CLKSEL pin = 1) and the internal oscillator clock brought out of

the device by setting the CLK_EN register bit to '1'. This master device clock is used as the external clock source

for other devices.

When using multiple devices, the devices can be synchronized with the START signal. The delay from START to

the DRDY signal is fixed for a given data rate (see the Start subsection of the SPI Interface section for more

details on the settling times). Figure 69 shows the behavior of two devices when synchronized with the START

signal.

There are two ways to connect multiple devices with a optimal number of interface pins: cascade mode and

daisy-chain mode.

Device 1

START

CLK

START₁

CLK

DRDY₁

DRDY

Device 2

START₂

CLK

DRDY₂

DRDY

CLK

START

DRDY₁

DRDY₂

Figure 69. Synchronizing Multiple Converters

10.1.4.1 Cascaded Mode

Figure 70a illustrates a configuration with two devices cascaded together. Together, the devices create a system

with 16 channels. DOUT, SCLK, and DIN are shared. Each device has its own chip select. When a device is not

selected by the corresponding CS being driven to logic 1, the DOUT of this device is high-impedance. This

structure allows the other device to take control of the DOUT bus. This configuration method is suitable for the

majority of applications.

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Application Information (continued)

10.1.4.2 Daisy-Chain Mode

Daisy-chain mode is enabled by setting the DAISY_EN bit in the CONFIG1 register. Figure 70b shows the daisy-

chain configuration. In this mode SCLK, DIN, and CS are shared across multiple devices. The DOUT of the

second device is connected to the DAISY_IN of the first device, thereby creating a chain. When using daisy-

chain mode, the multiple readback feature is not available. Short the DAISY_IN pin to digital ground if not used.

Figure 2 describes the required timing for the device shown in the configurations of Figure 70. Status and data

from device 1 appear first on DOUT, followed by the status and data from device 2. The ADS1299 can be daisy

chained with a second ADS1299, an ADS1299-6, or an ADS1299-4.

START⁽¹⁾

CLK

START⁽¹⁾

CLK

START

CLK

START

CLK

DRDY

CS

INT

DRDY

CS

INT

GPO0

GPO1

SCLK

MOSI

MISO

GPO

SCLK

DIN

SCLK

DIN

SCLK

MOSI

MISO

Device 1

DOUT₀

DOUT

DAISY_IN₀

Host Processor

START

CLK

DOUT₁

START

CLK

DRDY

CS

DRDY

CS

SCLK

DIN

SCLK

DIN

Device 2

DOUT

DAISY_IN₁

0

a) Standard Configuration

b) Daisy-Chain Configuration

(1) To reduce pin count, set the START pin low and use the START serial command to synchronize and start

conversions.

Figure 70. Multiple Device Configurations

When all devices in the chain operate in the same register setting, DIN can be shared as well. This configuration

reduces the SPI communication signals to four, regardless of the number of devices. The BIAS driver cannot be

shared among the multiple devices and an external clock must be used because the individual devices cannot be

programmed when sharing a common DIN.

Note that from Figure 2, the SCLK rising edge shifts data out of the device on DOUT. The SCLK negative edge

is used to latch data into the device DAISY_IN pin down the chain. This architecture allows for a faster SCLK

rate speed, but also makes the interface sensitive to board-level signal delays. The more devices in the chain,

the more challenging adhering to setup and hold times becomes. A star-pattern connection of SCLK to all

devices, minimizing DOUT length, and other printed circuit board (PCB) layout techniques helps. Placing delay

circuits (such as buffers) between DOUT and DAISY_IN are ways to mitigate this challenge. One other option is

to insert a D flip-flop between DOUT and DAISY_IN clocked on an inverted SCLK. Note also that daisy-chain

mode requires some software overhead to recombine data bits spread across byte boundaries. Figure 71 shows

a timing diagram for this mode.

DOUT₁

MSB₁

LSB₁

DAISY_IN₀

SCLK

1

2

3

216

217

218

219

337

MSB₀

LSB₀

MSB₁

LSB₁

DOUT

0

Data From Device 1

Data From Device 2

Figure 71. Daisy-Chain Timing

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Application Information (continued)

The maximum number of devices that can be daisy-chained depends on the data rate at which the device is

operated at. The maximum number of devices can be approximately calculated with Equation 10.

f_SCLK

N_DEVICES

=

f_DR(N_BITS)(N_CHANNELS) + 24

where:

N_BITS= device resolution (depending on data rate), and

N_CHANNELS= number of channels in the device.

(10)

For example, when the 8-channel ADS1299 is operated at a 2-kSPS data rate with a 4-MHz f_SCLK, 10 devices

can be daisy-chained.

10.2 Typical Application

The biopotential signals that are measured in electroencephalography (EEG) are small when compared to other

types of biopotential signals. The ADS1299 is equipped to measure such small signals due to its extremely low

input-referred noise from its high performance internal PGA. Figure 72 and Figure 73 are examples of how the

ADS1299 may be configured in typical EEG measurement setups. Figure 72 shows how to measure electrode

potentials in a sequential montage, whereas Figure 73 illustrates referential montage measurement connections.

+2.5 V

AVDD

R_Filt

IN1P

Electrode 1

+

C_Filt

ADC

IN1N

Electrode 2

Electrode 3

Electrode 4

R_Filt

IN2P

IN2N

+

C_Filt

R_Filt

.

BIASP1 BIASN1 BIASP2 BIASN2

BIASINV

220 kꢀ 220 kꢀ 220 kꢀ 220 kꢀ

R_F

R_P

C_F

BIASOUT

Bias

Electrode

+

(AVDD + AVSS)/2

BIASREF_INT

AVSS

-2.5 V

Figure 72. Example Schematic Using the ADS1299 in an EEG Data Acquisition Application, Sequential

Montage

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Typical Application (continued)

+2.5 V

AVDD

R_Filt

IN1P

Electrode 1

+

ADC

R_Filt

IN2P

Electrode 2

R_Filt

IN3P

Electrode 3

ADC

R_Filt

IN4P

Electrode 4

.

C_FiltC_FiltC_FiltC_Filt

SRB1

Reference

Electrode

BIASP1 BIASN1 BIASP2 BIASN2 BIASP3 BIASN3 BIASP4 BIASN4

R_Filt

BIASINV

220 kꢀ 220 kꢀ 220 kꢀ 220 kꢀ

R_F

R_P

C_F

BIASOUT

Bias

Electrode

+

(AVDD + AVSS)/2

BIASREF_INT

AVSS

-2.5 V

Figure 73. Example Schematic Using the ADS1299 in an EEG Data Acquisition Application, Referential

Montage

10.2.1 Design Requirements

Table 29 shows the design requirements for a typical EEG measurement system.

Table 29. EEG Data Acquisition Design Requirements

DESIGN PARAMETER

Bandwidth

VALUE

1 Hz - 50 Hz

10 μV_Pk

> 10 MΩ

dc

Minimum signal bandwidth

Input Impedance

Coupling

10.2.2 Detailed Design Procedure

Each channel on the ADS1299 is optimized to measure a separate EEG waveform. The specific connections

depend on the EEG montage. The sequential montage is a configuration where each channel represents the

voltage between two adjacent electrodes. For example, to measure the potential between electrode Fp1 and F7

on channel 1 of the ADS1299, route the Fp1 electrode to IN1P and the F7 electrode to IN1N. The connections

for a sequential montage are illustrated in Figure 72.

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Alternatively, EEG electrodes can be measured in a referential montage in which each of the electrodes is

measured with respect to a single reference electrode. This montage also allows calculation of the waveforms

that would have been measured in a sequential montage by finding the difference between two electrode

waveforms which were measured with respect to the same electrode. The ADS1299 allows for such a

configuration through the use of the SRB1 pin. The SRB1 pin on the ADS1299 may be internally routed to each

channel negative input by setting the SRB1 bit in the MISC1 register. When the reference electrode is connected

to the SRB1 pin and all other electrodes are connected to the respective positive channel inputs, the electrode

voltages can be measured with a referential montage. The referential montage is illustrated in Figure 73. See

Figure 18 for a diagram of the channel input multiplexer options.

The ADS1299 is designed to be an EEG front end such that no additional amplification or buffer stage is needed

between the electrodes and ADS1299. The ADS1299 has a low-noise PGA with excellent input-referred noise

performance. For certain data rate and gain settings, the ADS1299 introduces significantly less than 1 μV_RMSof

input-referred noise to the signal chain making the device more than capable of handling the 10-μV_Pkminimum

signal amplitude. ADS1299 noise performance for different PGA gains and data rate settings is listed in Table 1,

Table 2, Table 3, and Table 4.

Traditional EEG data acquisition systems high-pass filter the signals in the front-end to remove dc signal content.

This topology allows the signal to be amplified by a large gain so the signal can be digitized by a 12- to 16-bit

ADC. The ADS1299 24-bit resolution allows the signal to be dc-coupled to the ADC because small EEG signal

information can be measured in addition to a significant dc offset.

The ADS1299 channel inputs have very low input bias current allowing electrodes to be connected to the inputs

of the ADS1299 with very little leakage current flowing on the patient cables. The ADS1299 has a minimum dc

input impedance of 1 GΩ when the lead-off current sources are disabled and 500 MΩ typically when the lead-off

current sources are enabled.

The passive components R_Filtand C_Filtform low-pass filters. In general, the filter is advised to be formed by using

a differential capacitor C_FIltthat shunts the inputs rather than individual RC filters whose capacitors shunt to

ground. The differential capacitor configuration significantly improves common-mode rejection because this

approach removes dependence on component mismatch.

The cutoff frequency for the filter can be placed well past the data rate of the ADC because of the delta-sigma

ADC filter-then-decimate topology. Take care to prevent aliasing around the first repetition of the digital

decimation filter response at f_MOD. Assuming a 2.048-MHz f_CLK, f_MOD= 1.024 MHz. The value of R_Filthas a

minimum set by technical standards for medical electronics. The capacitor value must be set to arrange the

proper cutoff frequency.

If the system is likely to be exposed to high-frequency EMI, adding very small-value, common-mode capacitors to

the inputs is advisable to filter high-frequency common-mode signals. If these capacitors are added, then the

capacitors should be 10 or 20 times smaller than the differential capacitor to ensure their effect of CMRR is

minimized.

The integrated bias amplifier serves two purposes in an EEG data acquisition system with the ADS1299. The

bias amplifier provides a bias voltage that, when applied to the patient, keeps the measurement electrode

common-mode voltage within the rails of the ADS1299. This scenario allows for dc coupling. In addition, the bias

amplifier can be configured to provide negative common-mode feedback to the patient to cancel unwanted

common-mode signals appearing on the electrodes. This feature is especially helpful because biopotential

acquisition systems are notoriously prone to mains-frequency common-mode interference.

The bias amplifier is powered on by setting the PD_BIAS bit in the CONFIG3 register. Set the BIASREF_INT bit

in the CONFIG3 register to input the internally generated analog mid-supply voltage the noninverting input of the

bias amplifier. To enable an electrode as an input to the bias amplifier, set the corresponding bit in the

BIAS_SENSP or BIAS_SENSN register.

The dc gain of the bias amplifier is determined by R_Biasand the number of channel inputs enabled as inputs to

the bias amplifier. The bias amplifier circuit only passes common-mode signals. Therefore, the 330-kΩ resistors

at each PGA output are in parallel for common-mode signals. The bias amplifier is configured in an inverting gain

scheme. The formula for determining dc gain for common-mode signals input to the bias amplifier is shown in

Equation 11. The capacitor C_fsets the bandwidth for the bias amplifier. Ensure that the amplifier has enough

bandwidth to output all the intended common-mode signals.

V_out

R_fìN

330kW

= -

V

in

(11)

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Another advantage to a dc-coupled EEG data acquisition system is the ability to detect when an electrode no

longer makes good contact with the patient. The ADS1299 features integrated lead-off detection electronics. The

Lead-Off Detection section explains how to use the lead-off feature on the ADS1299. Note that when configured

in a referential montage, only use one lead-off current source with the reference electrode.

10.2.3 Application Curves

Testing the capability of the ADS1299 to measure signals in the band and near the amplitude of typical EEG

signals can be done with a precision signal generator. The ADS1299 was tested in a configuration like the one

shown in Figure 74.

+2.5 V

AVDD

952 kꢀ

4.99 kꢀ

10.3 kꢀ

INxP

INxN

33 ꢁV_RMS

10 Hz

4.7 nF

AVSS

-2.5 V

Figure 74. Example Schematic Using the ADS1299 in an EEG Data Acquisition Application, Referential

Montage

The 952-kΩ and 10.3-kΩ resistors were used to attenuate the voltage from the signal source because the source

could not reach the desired magnitude directly. With the voltage divider, the signal appearing at the inputs was a

3.5-μV_RMS, 10-Hz sine wave. Figure 75 shows the input-referred conversion results from the ADS1299 following

calibration for offset. The signal that is measured is similar to some of the smallest extracranial EEG signals that

can be measured with typical EEG acquisition systems. The signal can be clearly identified. Given this

measurement setup was a single-ended configuration without shielding, the measurement setup was subject to

significant mains interference. A digital low-pass filter was applied to remove the interference.

4.5

3.5

2.5

1.5

0.5

-0.5

-1.5

-2.5

-3.5

-4.5

0

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

Time (s)

1

D001

Figure 75. ADS1299 10-Hz Input Signal Results

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11 Power Supply Recommendations

The ADS1299-x has three power supplies: AVDD, AVDD1, and DVDD. For best performance, both AVDD and

AVDD1 must be as quiet as possible. AVDD1 provides the supply to the charge pump block and has transients

at f_CLK. Therefore, star connect AVDD1 to the AVDD pins and AVSS1 to the AVSS pins. AVDD and AVDD1

noise that is nonsynchronous with the ADS1299-x operation must be eliminated. Bypass each device supply with

10-μF and 0.1-μF solid ceramic capacitors. For best performance, place the digital circuits (DSP,

microcontrollers, FPGAs, and so forth) in the system so that the return currents on those devices do not cross

the analog return path of the device. Power the ADS1299-x from unipolar or bipolar supplies.

Use surface-mount, low-cost, low-profile, multilayer ceramic-type capacitors for decoupling. In most cases, the

VCAP1 capacitor is also a multilayer ceramic; however, in systems where the board is subjected to high- or low-

frequency vibration, install a nonferroelectric capacitor, such as a tantalum or class 1 capacitor (C0G or NPO).

EIA class 2 and class 3 dielectrics such as (X7R, X5R, X8R, and so forth) are ferroelectric. The piezoelectric

property of these capacitors can appear as electrical noise coming from the capacitor. When using internal

reference, noise on the VCAP1 node results in performance degradation.

11.1 Power-Up Sequencing

Before device power up, all digital and analog inputs must be low. At the time of power up, keep all of these

signals low until the power supplies have stabilized, as shown in Figure 76.

Allow time for the supply voltages to reach their final value, and then begin supplying the master clock signal to

the CLK pin. Wait for time t_POR, then transmit a reset pulse using either the RESET pin or RESET command to

initialize the digital portion of the chip. Issue the reset after t_PORor after the VCAP1 voltage is greater than 1.1 V,

whichever time is longer. Note that:

•

t_PORis described in Table 30.

The VCAP1 pin charge time is set by the RC time constant set by the capacitor value on VCAP1; see

Figure 25.

After releasing the RESET pin, program the configuration registers. The power-up sequence timing is shown in

Table 30.

(1)(2)

t_POR

Supplies

(1)

t_BG

1.1V

VCAP1

VCAP = 1.1V

Start using

device

18 × t_CLK

RESET

t_RST

(1) Timing to reset pulse is t_PORor after t_BG, whichever is longer.

(2) When using an external clock, t_PORtiming does not start until CLK is present and valid.

Figure 76. Power-Up Timing Diagram

Table 30. Timing Requirements for Figure 76

MIN

2¹⁸

2

MAX

UNIT

t_CLK

t_POR

t_RST

Wait after power up until reset

Reset low duration

t_CLK

11.2 Connecting the Device to Unipolar (5 V and 3.3 V) Supplies

Figure 77 illustrates the ADS1299-x connected to a unipolar supply. In this example, analog supply (AVDD) is

referenced to analog ground (AVSS) and digital supply (DVDD) is referenced to digital ground (DGND).

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Connecting the Device to Unipolar (5 V and 3.3 V) Supplies (continued)

+5 V

+3.3 V

0.1 mF

1 mF

0.1 mF

AVDD AVDD1 DVDD

VREFP

VREFN

0.1 mF

10 mF

VCAP1

VCAP2

VCAP3

VCAP4

RESV1

Device

1 mF

0.1 mF

1 mF

100 mF

AVSS1 AVSS DGND

NOTE: Place the capacitors for supply, reference, and VCAP1 to VCAP4 as close to the package as possible.

Figure 77. Single-Supply Operation

11.3 Connecting the Device to Bipolar (±2.5 V and 3.3 V) Supplies

Figure 78 shows the ADS1299-x connected to a bipolar supply. In this example, the analog supplies connect to

the device analog supply (AVDD). This supply is referenced to the device analog return (AVSS), and the digital

supply (DVDD) is referenced to the device digital ground return (DGND).

+2.5 V

+3.3 V

1 mF

0.1 mF

1 mF

AVDD AVDD1 DVDD

VREFP

0.1 mF

10 mF

VREFN

-2.5 V

VCAP1

VCAP2

VCAP3

VCAP4

Device

RESV1

AVSS1 AVSS DGND

1 mF

0.1 mF

1 mF

100 mF

1 mF

0.1 mF

-2.5 V

NOTE: Place the capacitors for supply, reference, and VCAP1 to VCAP4 as close to the package as possible.

Figure 78. Bipolar Supply Operation

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12 Layout

12.1 Layout Guidelines

TI recommends employing best design practices when laying out a printed-circuit board (PCB) for both analog

and digital components. This recommendation generally means that the layout separates analog components

[such as ADCs, amplifiers, references, digital-to-analog converters (DACs), and analog MUXs] from digital

components [such as microcontrollers, complex programmable logic devices (CPLDs), field-programmable gate

arrays (FPGAs), radio frequency (RF) transceivers, universal serial bus (USB) transceivers, and switching

regulators]. An example of good component placement is shown in Figure 79. Although Figure 79 provides a

good example of component placement, the best placement for each application is unique to the geometries,

components, and PCB fabrication capabilities employed. That is, there is no single layout that is perfect for every

design and careful consideration must always be used when designing with any analog component.

Ground Fill or

Ground Plane

Ground Fill or

Ground Plane

Supply

Generation

Signal

Conditioning

(RC Filters

and

Interface

Transceiver

Device

Microcontroller

Connector

or Antenna

Amplifiers)

Ground Fill or

Ground Plane

Ground Fill or

Ground Plane

Figure 79. System Component Placement

The following outlines some basic recommendations for the layout of the ADS1299-x to get the best possible

performance of the ADC. A good design can be ruined with a bad circuit layout.

•

Separate analog and digital signals. To start, partition the board into analog and digital sections where the

layout permits. Route digital lines away from analog lines. This configuration prevents digital noise from

coupling back into analog signals.

•

The ground plane can be split into an analog plane (AGND) and digital plane (DGND), but is not necessary.

Place digital signals over the digital plane, and analog signals over the analog plane. As a final step in the

layout, the split between the analog and digital grounds must be connected together at the ADC.

•

Fill void areas on signal layers with ground fill.

Provide good ground return paths. Signal return currents flow on the path of least impedance. If the ground

plane is cut or has other traces that block the current from flowing right next to the signal trace, then the

current must find another path to return to the source and complete the circuit. If current is forced into a

longer path, the chances that the signal radiates increases. Sensitive signals are more susceptible to EMI

interference.

•

Use bypass capacitors on supplies to reduce high-frequency noise. Do not place vias between bypass

capacitors and the active device. Placing the bypass capacitors on the same layer as close to the active

device yields the best results.

Analog inputs with differential connections must have a capacitor placed differentially across the inputs. The

differential capacitors must be of high quality. The best ceramic chip capacitors are C0G (NPO), which have

stable properties and low noise characteristics.

12.2 Layout Example

Figure 80 is an example layout of the ADS1299 requiring a minimum of two PCB layers. The example circuit is

shown for either a single analog supply or a bipolar-supply connection. In this example, polygon pours are used

as supply connections around the device. If a three- or four-layer PCB is used, the additional inner layers can be

dedicated to route power traces. The PCB is partitioned with analog signals routed from the left, digital signals

routed to the right, and power routed above and below the device.

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Layout Example (continued)

Via to AVSS pour

or plane

Via to digital ground

pour or plane

1: IN8N

2: IN8P

48: DVDD

47: DRDY

3: IN7N

4: IN7P

5: IN6N

6: IN6P

46: GPIO4

45: GPIO3

44: GPIO2

43: DOUT

Input filtered with

differential capacitors

7: IN5N

8: IN5P

42: GPIO1

41: DAISY_

IN

!5{1299

9: IN4N

40: SCLK

39: CS

10: IN4P

11: IN3N

12: IN3P

13: IN2N

14: IN2P

15: IN1N

16: IN1P

38: START

37: CLK

36: RESET

35:PWDN

34: DIN

33: DGND

Long digital input lines

terminated with resistors

to prevent reflection

Reference, VCAP, and

power supply decoupling

capacitors close to pins

Figure 80. ADS1299 Example Layout

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13 器件和文档支持

13.1 文档支持

13.1.1 相关文档ꢀ


型号：	ADS1299-4
厂家：	TEXAS INSTRUMENTS
描述：	适用于生物电势测量的低噪声、4 通道、24 位模数转换器转换器模数转换器
文件：	总84页 (文件大小：1950K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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