ADS130E08IPAG [TI]
用于计量应用的低成本、8 通道、集成模拟前端 | PAG | 64 | -40 to 105;
| 型号： | ADS130E08IPAG |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 用于计量应用的低成本、8 通道、集成模拟前端 | PAG | 64 | -40 to 105 转换器 模数转换器 |
| 文件： | 总56页 (文件大小：1706K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ADS131E04
ADS131E06
ADS131E08
www.ti.com
SBAS561 –JUNE 2012
Analog Front-End for Power Monitoring, Control, and Protection
Check for Samples: ADS131E04, ADS131E06 , ADS131E08
The ADS131E0x incorporate features commonly
required in industrial power monitoring, control, and
protection applications. The ADS131E0x inputs can
be independently and directly interfaced with a
resistor-divider network or a transformer to measure
voltage. The inputs can also be interfaced to a
current transformer or Rogowski coil to measure
current. With high integration levels and exceptional
performance, the ADS131E0x family enables the
creation of scalable industrial power systems at
significantly reduced size, power, and low overall
cost.
1
FEATURES
23
•
Eight Differential Current and Voltage Inputs
Outstanding Performance:
•
–
–
–
–
Exceeds Class 0.1 Performance
Dynamic Range at 1 kSPS: 118 dB
Crosstalk: –110 dB
THD: –90 dB at 50 Hz and 60 Hz
•
Supply Range:
–
Analog:
–
–
+3 V to +5 V (Unipolar)
±2.5 V (Bipolar, allows dc coupling)
The ADS131E0x have a flexible input multiplexer per
channel that can be independently connected to the
internally-generated signals for test, temperature, and
fault detection. Fault detection can be implemented
internal to the device, using the integrated
comparators with digital-to-analog converter (DAC)-
controlled trigger levels. The ADS131E0x can operate
at data rates as high as 64 kSPS.
–
Digital: +1.8 V to +3.6 V
•
•
•
•
•
•
•
Low Power: 2 mW per Channel
Data Rates: 1, 2, 4, 8, 16, 32, and 64 kSPS
Programmable Gains (1, 2, 4, 8, and 12)
Fault Detection and Device Testing Capability
SPI™ Data Interface and Four GPIOs
Package: TQFP-64 (PAG)
These complete analog front-end (AFE) solutions are
packaged in a TQFP-64 package and are specified
over the industrial temperature range of –40°C to
+105°C.
Operating Temperature Range:
–40°C to +105°C
Current
ûꢀ
ADC
Sensing
Device
Channel 1
Channel 2
PGA
PGA
Line A
APPLICATIONS
Voltage
Sensing
•
Industrial Power Applications:
ûꢀ
ADC
Voltage
Reference
–
–
Energy Metering
Current
Sensing
ûꢀ
ADC
Oscillator
Monitoring, Control, and Protection
Channel 3
Channel 4
PGA
PGA
Line B
Line C
Line N
Voltage
Sensing
ûꢀ
ADC
EMI
Filters
and
Input
MUX
DESCRIPTION
The ADS131E0x are
simultaneous sampling, 24- and 16-bit, delta-sigma
(ΔΣ), analog-to-digital converters (ADCs) with a built-
in programmable gain amplifier (PGA), internal
reference, and an onboard oscillator.
Control
and
SPI Interface
a family of multichannel,
ûꢀ
ADC
Current
Sensing
Channel 5
Channel 6
PGA
PGA
PGA
PGA
ûꢀ
ADC
Fault
Detection
Voltage
Sensing
Test
ûꢀ
ADC
Channel 7
Channel 8
Current
Sensing
Op
Amp
ûꢀ
ADC
Voltage
Sensing
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
3
SPI is a trademark of Motorola.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2012, Texas Instruments Incorporated
ADS131E04
ADS131E06
ADS131E08
SBAS561 –JUNE 2012
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
FAMILY AND ORDERING INFORMATION(1)
OPERATING
NUMBER OF
CHANNELS
MAXIMUM SAMPLE
RATE (kSPS)
TEMPERATURE
RANGE
PRODUCT
ADS130E08
ADS131E04
ADS131E06
ADS131E08
PACKAGE OPTION
TQFP-64
ACCURACY
Class 1.0
Class 0.1
Class 0.1
Class 0.1
8
4
6
8
8
–40°C to +105°C
–40°C to +105°C
–40°C to +105°C
–40°C to +105°C
TQFP-64
64
64
64
TQFP-64
TQFP-64
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the
device product folder at www.ti.com.
ABSOLUTE MAXIMUM RATINGS(1)
Over operating free-air temperature range, unless otherwise noted.
VALUE
–0.3 to +5.5
–0.3 to +3.9
–0.3 to +0.3
AVSS – 0.3 to AVDD + 0.3
DVSS – 0.3 to DVDD + 0.3
±10
UNIT
V
AVDD to AVSS
DVDD to DGND
V
AGND to DGND
V
Analog input to AVSS
Digital input to DVDD
Input current to any pin except supply pins(2)
V
V
mA
mA
mA
°C
°C
°C
Momentary
Input current
±100
Continuous
±10
Operating, industrial-grade devices only
Storage
–40 to +85
Temperature
–60 to +150
+150
Maximum junction, TJ
Human body model (HBM)
JEDEC standard 22, test method A114-C.01, all pins
±1000
±500
V
V
Electrostatic discharge
(ESD) ratings
Charged device model (CDM)
JEDEC standard 22, test method C101, all pins
(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not implied.
(2) Input terminals are diode-clamped to the power-supply rails. Input signals that can swing beyond the supply rails must be current limited
to 10 mA or less.
2
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Product Folder Link(s): ADS131E04 ADS131E06 ADS131E08
ADS131E04
ADS131E06
ADS131E08
www.ti.com
SBAS561 –JUNE 2012
ELECTRICAL CHARACTERISTICS
Minimum and maximum specifications apply from –40°C to +105°C. Typical specifications are at +25°C. All specifications are
at DVDD = 1.8 V, AVDD = 3 V, AVSS = 0 V, VREF = 2.4 V, external fCLK = 2.048 MHz, data rate = 8 kSPS, and gain = 1,
unless otherwise noted.
ADS131E0x
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ANALOG INPUTS
Full-scale differential input voltage
(AINP – AINN)
±VREF / gain
V
See the Input Common-Mode Range
subsection of the PGA Settings and
Input Range section
Input common-mode range
Ci
IIB
Input capacitance
Input bias current
DC input impedance
20
5
pF
nA
PGA output in normal range
200
MΩ
PGA PERFORMANCE
Gain settings
1, 2, 4, 8, 12
See Table 3
BW
Bandwidth
ADC PERFORMANCE
Data rates up to 16 kSPS
32- and 64-kSPS data rate
fCLK = 2.048 MHz
24
16
Bits
Bits
Resolution
DR
Data rate
1
64
kSPS
CHANNEL PERFORMANCE (DC Performance)
INL
Integral nonlinearity
Dynamic range
Full-scale, best fit
G = 1
10
ppm
dB
105
Gain settings other than 1
See Noise Measurements section
EO
EG
Offset error
350
0.65
0.1
3
μV
μV/°C
%
Offset error drift
Gain error
Excluding voltage reference error
Excluding voltage reference drift
Gain drift
ppm/°C
% of FS
Gain match between channels
0.2
CHANNEL PERFORMANCE (AC Performance)
CMRR
PSRR
Common-mode rejection ratio
Power-supply rejection ratio
Crosstalk
fCM = 50 Hz and 60 Hz(1)
fPS = 50 Hz and 60 Hz
–110
–80
dB
dB
dB
fIN = 50 Hz and 60 Hz
–110
1:3000 dynamic range with a 1-second
Accuracy
0.1
%
measurement (VRMS / IRMS
)
SNR
THD
Signal-to-noise ratio
fIN = 50 Hz and 60 Hz, gain = 1
10 Hz, –0.5 dBFs
107
–93
dB
dB
Total harmonic distortion
FAULT DETECT AND ALARM
Comparator threshold accuracy
EXTERNAL REFERENCE
±30
mV
AVDD = 3 V, VREF = (VREFP – VREFN)
AVDD = 5 V, VREF = (VREFP – VREFN)
2.5
V
V
Reference input voltage
Negative input
4
AVSS
VREFN
VREFP
V
Positive input
AVSS + 2.5
6
V
Input impedance
kΩ
(1) CMRR is measured with a common-mode signal of (AVSS + 0.3 V) to (AVDD – 0.3 V). The values indicated are the minimum of the
eight channels.
Copyright © 2012, Texas Instruments Incorporated
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ADS131E04
ADS131E06
ADS131E08
SBAS561 –JUNE 2012
www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
Minimum and maximum specifications apply from –40°C to +105°C. Typical specifications are at +25°C. All specifications are
at DVDD = 1.8 V, AVDD = 3 V, AVSS = 0 V, VREF = 2.4 V, external fCLK = 2.048 MHz, data rate = 8 kSPS, and gain = 1,
unless otherwise noted.
ADS131E0x
PARAMETER
OPERATIONAL AMPLIFIER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Integrated noise
0.1 Hz to 250 Hz
9
120
100
0.25
50
µVRMS
nV/√Hz
kHz
V/µs
µA
Noise density
2 kHz
GBP
SR
Gain bandwidth product
Slew rate
50 kΩ || 10-pF load
50 kΩ || 10-pF load
Load current
THD
Total harmonic distortion
Common-mode input range
Quiescent power consumption
fIN = 100 Hz
70
dB
CMIR
AVSS + 0.7
AVDD – 0.3
V
20
µA
INTERNAL REFERENCE
CONFIG2.VREF_4V = 0
CONFIG2.VREF_4V = 1
2.4
4
V
V
VO
Output voltage
VREF accuracy
Temperature drift
Start-up time
±0.2
30
%
0°C ≤ TA ≤ +70°C
–40°C ≤ TA ≤ +105°C
Settled to 0.2%
ppm/°C
ppm/°C
ms
40
150
SYSTEM MONITORS
Analog
Digital
2
2
%
%
Supply reading error
From power-up to DRDY low
STANDBY mode
150
31.25
145
490
ms
Device wake up
µs
Voltage
TA = +25°C
mV
μV/°C
Temperature sensor
reading
Coefficient
SELF-TEST SIGNAL
fCLK / 221
fCLK / 220
±1
Hz
Hz
mV
mV
%
Signal frequency
See Register Map section for settings
See Register Map section for settings
Signal voltage
Accuracy
±2
±2
CLOCK
Nominal frequency
TA = +25°C
2.048
MHz
%
Internal oscillator clock frequency
±0.5
2.5
–40°C ≤ TA ≤ +105°C
%
Internal oscillator start-up time
20
120
μs
Internal oscillator power consumption
μW
MHz
MHz
CLKSEL pin = 0, AVDD = 3 V
CLKSEL pin = 0, AVDD = 5 V
1.7
0.7
2.048
2.048
2.25
2.25
External clock input frequency
DIGITAL INPUT AND OUTPUT (DVDD = 1.8 V to 3.6 V)
VIH
VIL
High
Low
High
Low
0.8 DVDD
–0.1
DVDD + 0.1
0.2 DVDD
V
V
Logic level,
input voltage
VOH
VOL
IIN
IOH = –500 µA
0.9 DVDD
V
Logic level,
output voltage
IOL = +500 µA
0.1 DVDD
+10
V
Input current
0 V < VDigitalInput < DVDD
–10
μA
POWER-SUPPLY REQUIREMENTS
AVDD
DVDD
Analog supply
Digital supply
AVDD – DVDD
AVDD – AVSS
2.7
1.8
3
5.25
3.6
V
V
V
1.8
–2.1
3.6
4
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Product Folder Link(s): ADS131E04 ADS131E06 ADS131E08
ADS131E04
ADS131E06
ADS131E08
www.ti.com
SBAS561 –JUNE 2012
ELECTRICAL CHARACTERISTICS (continued)
Minimum and maximum specifications apply from –40°C to +105°C. Typical specifications are at +25°C. All specifications are
at DVDD = 1.8 V, AVDD = 3 V, AVSS = 0 V, VREF = 2.4 V, external fCLK = 2.048 MHz, data rate = 8 kSPS, and gain = 1,
unless otherwise noted.
ADS131E0x
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY CURRENT (Operational Amplifier Turned Off)
AVDD – AVSS = 3 V
AVDD – AVSS = 5 V
5.1
5.8
1
mA
mA
mA
mA
IAVDD
Normal mode
DVDD = 3.3 V
DVDD = 1.8 V
IDVDD
0.4
POWER DISSIPATION (Analog Supply = 3 V)
Normal mode
9.3
10
2
10.2
13.5
17.6
mW
µW
ADS131E04
Power-down mode
Standby mode
Normal mode
mW
mW
µW
12.7
10
2
Quiescent power
ADS131E06
dissipation
Power-down mode
Standby mode
Normal mode
mW
mW
µW
16
10
2
ADS131E08
POWER DISSIPATION (Analog Supply = 5 V)
ADS131E04
Power-down mode
Standby mode
mW
Normal mode
18
20
mW
µW
Power-down mode
Standby mode
Normal mode
4.2
24.3
20
mW
mW
µW
Quiescent power
ADS131E06
dissipation
Power-down mode
Standby mode
Normal mode
4.2
29.7
20
mW
mW
µW
ADS131E08
Power-down mode
Standby mode
4.2
mW
TEMPERATURE
TA
Specified
Temperature range Operating
Storage
–40
–40
–60
+105
+105
+150
°C
°C
°C
TJ
Tstg
THERMAL INFORMATION
ADS131E0x
THERMAL METRIC(1)
PAG (TQFP)
UNITS
64 PINS
35
θJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
θJCtop
θJB
31
Junction-to-board thermal resistance
26
°C/W
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.1
ψJB
NA
θJCbot
NA
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
Copyright © 2012, Texas Instruments Incorporated
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ADS131E04
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ADS131E08
SBAS561 –JUNE 2012
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PARAMETER MEASUREMENT INFORMATION
NOISE MEASUREMENTS
The ADS131E0x noise performance can be optimized by adjusting the data rate and PGA setting. As the
averaging is increased by reducing the data rate, the noise drops correspondingly. Increasing the PGA value
reduces the input-referred noise, which is particularly useful when measuring low-level signals. Table 1
summarizes the ADS131E0x noise performance with a 3-V analog power supply. Table 2 summarizes the
ADS131E0x noise performance with a 5-V analog power supply. The data are representative of typical noise
performance at TA = +25°C. The data shown are the result of averaging the readings from multiple devices and
are measured with the inputs shorted together. A minimum of 1000 consecutive readings are used to calculate
the RMS and peak-to-peak noise for each reading. For the two highest data rates, the noise is limited by ADC
quantization noise and does not have a Gaussian distribution. Table 1 and Table 2 show measurements taken
with an internal reference. The data are also representative of the ADS131E0x noise performance when using a
low-noise external reference, such as the REF5025.
Table 1. Input-Referred Noise, 3-V Analog Supply, and 2.4-V Reference(1)
PGA GAIN
x4
DYNAMIC
OUTPUT
x1
DYNAMIC
x2
DYNAMIC
x8
DYNAMIC
x12
DYNAMIC
DR BITS
(CONFIG1
Register)
DATA
RATE
(kSPS)
–3-dB
BANDWIDTH
(Hz)
RANGE (dB)
ENOB
12.31
14.89
17.07
18.0
RANGE (dB)
ENOB
12.30
14.88
16.99
17.9
RANGE (dB)
ENOB
12.29
14.85
16.72
17.5
RANGE (dB)
ENOB
12.29
14.71
16.12
16.9
RANGE (dB)
ENOB
12.27
14.55
15.65
16.5
000
001
010
011
100
101
110
64
32
16
8
16768
8384
4192
2096
1048
524
74.1
74.1
74.0
74.0
73.9
89.6
89.6
89.4
88.6
87.6
102.8
102.3
100.6
97.1
94.2
108.2
107.4
105.2
101.6
103.5
107.7
110.7
98.9
4
111.4
18.6
109.4
18.4
107.4
18.1
17.4
100.5
104.9
108.0
17.0
2
114.6
19.1
113.7
19.0
111.4
18.6
18.0
17.5
1
262
117.7
19.6
116.8
19.5
114.5
19.1
18.5
18.0
(1) At least 1000 consecutive readings were used to calculate the peak-to-peak noise values in this table.
Table 2. Input-Referred Noise, 5-V Analog Supply, and 4-V Reference
PGA GAIN
OUTPUT
DATA
RATE
x1
DYNAMIC
x2
DYNAMIC
x4
DYNAMIC
x8
DYNAMIC
x12
DR BITS
(CONFIG1
Register)
–3-dB
BANDWIDTH
(Hz)
DYNAMIC
RANGE (dB)
(kSPS)
RANGE (dB)
ENOB
12.41
15.01
17.33
18.7
RANGE (dB)
ENOB
12.41
15.00
17.28
18.6
RANGE (dB)
ENOB
12.41
14.99
17.12
18.3
RANGE (dB)
ENOB
12.41
14.93
16.70
17.7
ENOB
12.39
14.85
16.30
17.3
000
001
010
011
100
101
110
64
32
16
8
16768
8384
4192
2096
1048
524
74.7
74.7
74.7
74.7
74.6
89.4
90.3
90.3
90.2
89.9
104.3
104.0
103.1
100.5
98.1
112.3
111.6
109.7
106.3
103.8
106.9
109.9
112.9
4
116.0
19.3
115.2
19.2
113.1
18.8
109.5
18.3
17.8
2
119.1
19.8
118.2
19.7
116.2
19.4
112.6
18.8
18.3
1
262
122.1
20.4
121.3
20.2
119.1
19.9
115.6
19.3
18.8
6
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SBAS561 –JUNE 2012
TIMING CHARACTERISTICS
tCLK
CLK
tCSSC
tCSH
t SDECODE
tSPWL
CS
tSCCS
tSPWH
tSCLK
SCLK
8
1
2
3
8
1
2
3
tDIHD
tDOHD
tDIST
tDOST
DIN
tCSDOZ
Hi-Z
tCSDOD
Hi-Z
DOUT
NOTE: SPI settings are CPOL = 0 and CPHA = 1.
Figure 1. Serial Interface Timing
tDISCK2ST
tDISCK2HT
MSB
LSB
n
DAISY_IN
SCLK
1
2
3
n+1
n+2
n+3
tDOST
MSB
MSB
DOUT
LSB
0
(1) n = Number of channels × resolution + 24 bits. Number of channels is 4, 6, or 8; resolution is 16-bit or 24-bit.
Figure 2. Daisy-Chain Interface Timing
Timing Requirements For Figure 1 and Figure 2(1)
2.7 V ≤ DVDD ≤ 3.6 V
1.7 V ≤ DVDD ≤ 2.0 V
PARAMETER
tCLK
DESCRIPTION
Master clock period
MIN
444
6
MAX
MIN
444
17
MAX
UNIT
ns
588
588
tCSSC
CS low to first SCLK: setup time
SCLK period
ns
tSCLK
50
15
10
10
10
66.6
25
ns
tSPWH, L
tDIST
SCLK pulse width, high and low
DIN valid to SCLK falling edge: setup time
Valid DIN after SCLK falling edge: hold time
SCLK falling edge to invalid DOUT: hold time
SCLK rising edge to DOUT valid: setup time
CS high pulse
ns
10
ns
tDIHD
11
ns
tDOHD
10
ns
tDOST
17
10
32
20
ns
tCSH
2
10
4
2
20
4
tCLKs
ns
tCSDOD
tSCCS
CS low to DOUT driven
Eighth SCLK falling edge to CS high
Command decode time
tCLKs
tCLKs
ns
tSDECODE
tCSDOZ
tDISCK2ST
tDISCK2HT
4
4
CS high to DOUT Hi-Z
Valid DAISY_IN to SCLK rising edge: setup time
Valid DAISY_IN after SCLK rising edge: hold time
10
10
10
10
ns
ns
(1) Specifications apply from –40°C to +105°C, unless otherwise noted. Load on DOUT = 20 pF || 100 kΩ.
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PIN CONFIGURATIONS
PAG PACKAGE
TQFP-32
(TOP VIEW)
48 DVDD
47 DRDY
IN8N
IN8P
1
2
46 GPIO4
45 GPIO3
44 GPIO2
43 DOUT
42 GPIO1
IN7N
IN7P
IN6N
IN6P
IN5N
IN5P
IN4N
3
4
5
6
7
8
9
41
DAISY_IN
40 SCLK
39 CS
IN4P 10
IN3N 11
IN3P 12
IN2N 13
IN2P 14
IN1N 15
IN1P 16
38 START
37 CLK
36 RESET
35 PWDN
34 DIN
33 DGND
PIN ASSIGNMENTS
NAME
AVDD
AVDD1
AVSS
AVSS1
CS
TERMINAL
FUNCTION
DESCRIPTION
19, 21, 22, 56, 59
Supply
Supply
Analog supply
54
Charge pump analog supply
Analog ground
20, 23, 32, 57, 58
Supply
53
39
Supply
Charge pump analog ground
SPI chip select; active low
Master clock input
Master clock select
Daisy-chain input
Digital ground
Digital input
Digital input
Digital input
Digital input
Supply
CLK
37
CLKSEL
DAISY_IN
DGND
DIN
52
41
33, 49, 51
34
Digital input
Digital output
Digital output
Supply
SPI data in
DOUT
DRDY
DVDD
43
SPI data out
47
Data ready; active low
Digital power supply
48, 50
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PIN ASSIGNMENTS (continued)
NAME
TERMINAL
FUNCTION
Digital input/output
Digital input/output
Digital input/output
Digital input/output
Analog input
DESCRIPTION
GPIO1
GPIO2
GPIO3
GPIO4
IN1N(1)
IN1P(1)
IN2N(1)
IN2P(1)
IN3N(1)
IN3P(1)
IN4N(1)
IN4P(1)
42
44
45
46
15
16
13
14
11
12
9
General-purpose input/output pin
General-purpose input/output pin
General-purpose input/output pin
General-purpose input/output pin
Differential analog negative input 1
Differential analog positive input 1
Differential analog negative input 2
Differential analog positive input 2
Differential analog negative input 3
Differential analog positive input 3
Differential analog negative input 4
Differential analog positive input 4
Analog input
Analog input
Analog input
Analog input
Analog input
Analog input
10
Analog input
Differential analog negative input 5
(ADS131E06 and ADS131E08 only)
IN5N(1)
IN5P(1)
IN6N(1)
7
8
5
Analog input
Analog input
Analog input
Differential analog positive input 5 (ADS131E06 and ADS131E08 only)
Differential analog negative input 6
(ADS131E06 and ADS131E08 only)
IN6P(1)
IN7N(1)
IN7P(1)
IN8N(1)
IN8P(1)
NC
6
Analog input
Analog input
Analog input
Analog input
Analog input
—
Differential analog positive input 6 (ADS131E06 and ADS131E08 only)
Differential analog negative input 7 (ADS131E08 only)
Differential analog positive input 7 (ADS131E08 only)
Differential analog negative input 8 (ADS131E08 only)
Differential analog positive input 8 (ADS131E08 only)
No connection, leave floating
3
4
1
2
27, 29, 62, 64
OPAMPN
OPAMPP
OPAMPOUT
PWDN
61
60
63
35
36
31
40
38
18
17
28
30
55
26
25
24
Analog
Op amp inverting input
—
Op amp noninverting input
Analog
Op amp output
Digital input
Digital input
Digital input
Digital input
Digital input
Analog input/output
Analog input/output
Analog input/output
—
Power-down; active low
RESET
RESV1
SCLK
System reset; active low
Reserved for future use; must tie to logic low (DGND)
SPI clock
START
TESTN(1)
TESTP(1)
VCAP1
VCAP2
VCAP3
VCAP4
VREFN
VREFP
Start conversion
Internal test signal, negative signal
Internal test signal, positive signal
Analog bypass capacitor
Analog bypass capacitor
—
Analog bypass capacitor
Analog output
Analog input
Analog input/output
Analog bypass capacitor
Negative reference voltage
Positive reference voltage
(1) Connect unused terminals to AVDD.
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TYPICAL CHARACTERISTICS
All plots are at TA = +25°C, AVDD = 3 V, AVSS = 0 V, DVDD = 1.8 V, internal VREFP = 2.4 V, VREFN = AVSS, external
clock = 2.048 MHz, data rate = 8 kSPS, and gain = 1, unless otherwise noted.
INPUT-REFERRED NOISE
NOISE HISTOGRAM
10
8
2200
2000
1800
1600
1400
1200
1000
800
Data Rate = 1 kSPS
Gain = 1
Data Rate = 1 kSPS
Gain = 1
6
4
2
0
−2
−4
−6
−8
−10
600
400
200
0
0
1
2
3
4
5
6
7
8
9
10
Time (s)
G003
Input−Referred Noise (µV)
G004
Figure 3.
Figure 4.
CMRR vs FREQUENCY
THD vs FREQUENCY
−90
−95
−75
−80
−85
−90
−95
Gain = 1
Gain = 2
Gain = 4
Gain = 8
Gain = 12
Gain = 1
Gain = 2
Gain = 4
Gain = 8
Gain = 12
−100
−105
−110
−115
−120
−125
−130
Data Rate = 4 kSPS
AIN = AVDD − 0.3 V to AVSS + 0.3 V
10
100
1000
10
100
1000
Frequency (Hz)
Frequency (Hz)
G005
G006
Figure 5.
Figure 6.
PSRR vs FREQUENCY
INL vs PGA GAIN
110
105
100
95
14
12
10
8
6
4
G = 1
G = 2
G = 4
G = 8
G = 12
Gain = 1
Gain = 2
Gain = 4
Gain = 8
Gain = 12
2
0
−2
−4
−6
−8
−10
−12
−14
90
85
80
10
100
1000
−1 −0.8 −0.6 −0.4 −0.2
0
0.2 0.4 0.6 0.8
1
Frequency (Hz)
Input (Normalized to Full−Scale)
G007
G008
Figure 7.
Figure 8.
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TYPICAL CHARACTERISTICS (continued)
All plots are at TA = +25°C, AVDD = 3 V, AVSS = 0 V, DVDD = 1.8 V, internal VREFP = 2.4 V, VREFN = AVSS, external
clock = 2.048 MHz, data rate = 8 kSPS, and gain = 1, unless otherwise noted.
INL vs TEMPERATURE
THD FFT PLOT
24
16
8
0
−20
−40°C
+105°C
+25°C
PGA Gain = 1
THD = −97 dB
SNR = 117 dB
Data Rate = 1 kSPS
−40
−60
−80
0
−100
−120
−140
−160
−180
−8
−16
−24
−1 −0.8 −0.6 −0.4 −0.2
0
0.2 0.4 0.6 0.8
1
0
100
200
300
400
500
Input (Normalized to Full−Scale)
Frequency (Hz)
G009
G010
Figure 9.
Figure 10.
FFT PLOT
OFFSET vs PGA GAIN (Absolute Value)
0
−20
600
500
400
300
200
100
0
PGA Gain = 1
THD = −96 dB
SNR = 74 dB
Data Rate = 64 kSPS
AVDD = 3 V
AVDD = 5 V
−40
−60
−80
−100
−120
−140
−160
−180
0
2
4
6
8
10 12 14 16 18 20 22 24 26 28 30 32
Frequency (kHz)
1
2
3
4
5
6
7
8
9
10 11 12
PGA Gain
G011
G012
Figure 11.
Figure 12.
OFFSET DRIFT vs PGA GAIN
ADS131E08 CHANNEL POWER
900
800
700
600
500
400
300
200
100
0
32
28
24
20
16
12
8
AVDD = 3 V
AVDD = 5 V
AVDD = 3 V
AVDD = 5 V
4
0
1
2
3
4
5
6
7
8
9
10 11 12
0
1
2
3
4
5
6
7
8
Number of Channels Disabled
PGA Gain
G013
G014
Figure 13.
Figure 14.
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OVERVIEW
The ADS131E0x are low-power, multichannel, simultaneously-sampling, 24- and 16-bit delta-sigma (ΔΣ), analog-
to-digital converters (ADCs) with an integrated programmable gain amplifier (PGA). This functionality makes
these devices well-suited for smart-grid and other industrial power monitor, control, and protection applications.
The ADS131E0x have a highly-programmable multiplexer that allows for temperature, supply, and input short
measurements. The PGA gain can be chosen from one of five settings (1, 2, 4, 8, and 12). The ADCs in the
device offer data rates of 1, 2, 4, 8, 16, 32, and 64 kSPS. Device communication is accomplished using an SPI-
compatible interface. The device provides four general-purpose I/O (GPIO) pins for general use. Multiple devices
can be synchronized using the START pin.
The internal reference can be programmed to either 2.4 V or 4 V. The internal oscillator generates a 2.048-MHz
clock. Open-circuit detection can be accomplished by using the integrated comparators, with programmable
trigger-point settings. A detailed diagram of the ADS131E0x is shown in Figure 15.
AVDD AVDD1
VREFP VREFN
Reference
DVDD
Temperature
Supply Check
Test Signal
Fault Detect
DRDY
IN1P
EMI
∆Σ
PGA1
PGA2
PGA3
Filter
ADC1
CS
IN1N
IN2P
SCLK
SPI
DIN
DOUT
EMI
Filter
∆Σ
ADC2
IN2N
IN3P
∆Σ
ADC3
EMI
Filter
IN3N
IN4P
CLKSEL
CLK
EMI
Filter
∆Σ
ADC4
Oscillator
Control
PGA4
PGA5
PGA6
PGA7
PGA8
IN4N
IN5P
MUX
GPIO1
EMI
Filter
GPIO2
GPIO3
∆Σ
ADC5
IN5N
IN6P
GPIO4
EMI
Filter
∆Σ
ADC6
IN6N
IN7P
PWDN
RESET
EMI
Filter
∆Σ
ADC7
IN7N
IN8P
START
EMI
Filter
∆Σ
ADC8
IN8N
Operational
Amplifier
OPAMPN
OPAMPP
OPAMPOUT
AVSS AVSS1
DGND
Figure 15. Functional Block Diagram
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THEORY OF OPERATION
This section contains details of the ADS131E0x internal functional elements. The analog blocks are discussed
first, followed by the digital interface. Information on implementing power monitoring specific applications is
covered towards the end of this document.
Throughout this document, fCLK denotes the signal frequency at the CLK pin, tCLK denotes the signal period at the
CLK pin, fDR denotes the output data rate, tDR denotes the output data time period, and fMOD denotes the
frequency at which the modulator samples the input.
EMI FILTER
An RC filter at the input acts as an EMI filter on all channels. The –3-dB filter bandwidth is approximately
3 MHz.
INPUT MULTIPLEXER
The ADS131E0x input multiplexers are very flexible and provide many configurable signal switching options.
Figure 16 shows a diagram of the multiplexer on a single channel of the device. VINP and VINN are separate for
each of the eight blocks. This flexibility allows for significant device and sub-system diagnostics, calibration, and
configuration. Switch settings for each channel are selected by writing the appropriate values to the CHnSET
register (see the CHnSET Register in the Register Map section for details.)
Device
MUX
INT_TEST
TESTP
INT_TEST
MUX[2:0] = 101
TestP
MUX[2:0] = 100
TempP
MUX[2:0] = 011
(1)
MvddP
MUX[2:0] = 000
VINP
To PgaP
MUX[2:0] = 001
MUX[2:0] = 001
EMI
Filter
(VREFP + VREFN)
2
MUX[2:0] = 000
MUX[2:0] = 011
MUX[2:0] = 100
MUX[2:0] = 101
VINN
To PgaN
(1)
MvddN
TempN
TestN
INT_TEST
INT_TEST
TESTN
(1) MVDD monitor voltage supply depends on channel number; see the Supply Measurements (MVDDP, MVDDN) section.
Figure 16. Input Multiplexer Block for One Channel
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Device Noise Measurements
Setting CHnSET[2:0] = 001 sets the common-mode voltage of [(VREFP + VREFN) / 2] to both channel inputs.
This setting can be used to test inherent device noise in the user system.
Test Signals (TestP and TestN)
Setting CHnSET[2:0] = 101 provides internally-generated test signals for use in sub-system verification at power-
up. Test signals are controlled through register settings (see the CONFIG2: Configuration Register 2 subsection
in the Register Map section for details). TEST_AMP controls the signal amplitude and TEST_FREQ controls
switching at the required frequency. The test signals are multiplexed and transmitted out of the device at the
TESTP and TESTN pins. A bit register (CONFIG2.INT_TEST = 0) deactivates the internal test signals so that the
test signal can be driven externally. This feature allows the calibration of multiple devices with the same signal.
Temperature Sensor (TempP, TempN)
The ADS131E0x contain an on-chip temperature sensor. This sensor uses two internal diodes with one diode
having a current density 16x that of the other, as shown in Figure 17. The difference in diode current densities
yields a difference in voltage that is proportional to absolute temperature.
As a result of the low thermal resistance of the package to the printed circuit board (PCB), the internal device
temperature tracks the PCB temperature closely. Note that self-heating of the ADS131E0x causes a higher
reading than the temperature of the surrounding PCB.
The scale factor of Equation 1 converts the temperature reading to °C. Before using this equation, the
temperature reading code must first be scaled to μV.
Temperature Reading (mV) - 168,000 mV
Temperature (°C) =
+ 25°C
394 mV/°C
(1)
Temperature Sensor Monitor
AVDD
1x
2x
To MUX TempP
To MUX TempN
8x
1x
AVSS
Figure 17. Temperature Sensor Measurement in the Input
Supply Measurements (MVDDP, MVDDN)
Setting CHnSET[2:0] = 011 sets the channel inputs to different device supply voltages. For channels 1, 2, 5, 6, 7,
and 8, (MVDDP – MVDDN) is [0.5(AVDD – AVSS)]; for channels 3 and 4, (MVDDP – MVDDN) is
DVDD / 4. Note that to avoid saturating the PGA while measuring power supplies, the gain must be set to '1'.
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ANALOG INPUT
The ADS131E0x analog input is fully differential. Assuming PGA = 1, the differential input (INP – INN) can span
between –VREF to +VREF. Refer to Table 5 for an explanation of the correlation between the analog input and
digital codes. There are two general methods of driving the ADS131E0x analog input: single-ended or
differential, as shown in Figure 18 and Figure 19, respectively. Note that INP and INN are 180°C out-of-phase in
the differential input method. When the input is single-ended, the INN input is held at the common-mode voltage,
preferably at mid-supply. The INP input swings around the same common voltage and the peak-to-peak
amplitude is (common-mode + 1/2 VREF) and (common-mode – 1/2 VREF). When the input is differential, the
common-mode is given by [(INP + INN) / 2]. Both INP and INN inputs swing from (common-mode + 1/2 VREF to
common-mode – 1/2 VREF). For optimal performance, it is recommended that the ADS131E0x be used in a
differential configuration.
1/2 VREF
to
+1/2 VREF
VREF
Peak-to-Peak
Device
Device
Common
Voltage
Common
Voltage
VREF
Peak-to-Peak
a) Single-Ended Input
b) Differential Input
Figure 18. Methods of Driving the ADS131E0x: Single-Ended or Differential
CM + 1/2 VREF
+1/2 V
INP
REF
CM Voltage
1/2VREF
INN = CM Voltage
CM 1/2 VREF
t
Single-Ended Inputs
CM + 1/2 VREF
CM Voltage
INP
INN
+VREF
VREF
CM 1/2 VREF
t
Differential Inputs
(INP) + (INN)
, Common-Mode Voltage (Single-Ended Mode) =INN
Common-Mode Voltage (Differential Mode) =
2
Input Range (Differential Mode) = (AINP – AINN) = 2 VREF
Figure 19. Using the ADS131E0x in Single-Ended and Differential Input Modes
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PGA SETTINGS AND INPUT RANGE
The PGA is a differential input and output amplifier, as shown in Figure 20. It has five gain settings (1, 2, 4, 8,
and 12) that can be set by writing to the CHnSET register (see the CHnSET Register in the Register Map section
for details). The ADS131E0x have CMOS inputs and therefore have negligible current noise. Table 3 shows the
typical bandwidth values for various gain settings. Note that Table 3 shows small-signal bandwidth. For large
signals, performance is limited by PGA slew rate.
The PGA resistor string that implements the gain has 120 kΩ of resistance for a gain of 2. This resistance
provides a current path across the PGA outputs in the presence of a differential input signal. This current is in
addition to the quiescent current specified for the device in the presence of a differential signal at the input.
From MuxP
PgaP
R2
30 kΩ
R1
60 kΩ
(for Gain = 2)
To ADC
R2
30 kΩ
PgaN
From MuxN
Figure 20. PGA Implementation
Table 3. PGA Gain versus Bandwidth
GAIN
NOMINAL BANDWIDTH AT ROOM TEMPERATURE (kHz)
1
2
237
146
96
4
8
48
12
32
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Input Common-Mode Range
The usable input common-mode range of the analog front-end depends on various parameters, including the
maximum differential input signal, supply voltage, and PGA gain. This range is described in Equation 2:
Gain VMAX_DIFF
Gain VMAX_DIFF
AVDD - 0.3 -
> CM > AVSS + 0.3 +
2
2
where:
VMAX_DIFF = maximum differential signal at the PGA input
CM = common-mode range
(2)
For example:
If VDD = 3.3 V, gain = 2, and VMAX_DIFF = 1000 mV,
Then 1.3 V < CM < 2.0 V
Input Differential Dynamic Range
The differential (INP – INN) signal range depends on the analog supply and reference used in the system. This
range is shown in Equation 3.
VREF
±VREF 2 VREF
=
Max (INP - INN) <
;
Full-Scale Range =
Gain
Gain
Gain
(3)
For higher dynamic range, a 5-V supply with a 4-V reference (set by the VREF_4V bit of the CONFIG3 register)
can be used to increase the differential dynamic range.
ADC ΔΣ Modulator
Each ADS131E0x channel has a ΔΣ ADC. This converter uses a second-order modulator optimized for low-
power applications. The modulator samples the input signal at the rate of [fMOD = fCLK / 2]. As in the case of any
ΔΣ modulator, the ADS131E0x noise is shaped until fMOD / 2, as shown in Figure 21. The on-chip digital
decimation filters also provide antialias filtering. This ΔΣ converter feature drastically reduces the complexity of
the analog antialiasing filters typically required with nyquist ADCs.
0
−10
−20
−30
−40
−50
−60
−70
−80
−90
−100
−110
−120
−130
−140
−150
−160
0.001
0.01
0.1
1
Normalized Frequency (fIN/fMOD
)
G001
Figure 21. Modulator Noise Spectrum Up To 0.5 × fMOD
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DIGITAL DECIMATION FILTER
The digital filter receives the modulator output and decimates the data stream. By adjusting the amount of
filtering, tradeoffs can be made between resolution and data rate: filter more for higher resolution, filter less for
higher data rates. Higher data rates are typically used in power applications that implement software phase
adjustment.
The digital filter on each channel consists of a third-order sinc filter. The decimation ratio on the sinc filters can
be adjusted by the DR bits in the CONFIG1 register (see the Register Map section for details). This setting is a
global setting that affects all channels and, therefore, all channels operate at the same data rate in the device.
Sinc Filter Stage (sinx / x)
The sinc filter is a variable decimation rate, third-order, low-pass filter. Data are supplied to this section of the
filter from the modulator at the rate of fMOD. The sinc filter attenuates the high-frequency modulator noise, then
decimates the data stream into parallel data. The decimation rate affects the overall converter data rate.
Equation 4 shows the scaled sinc filter Z-domain transfer function.
3
1 - Z- N
½H(z)½ =
1 - Z- 1
(4)
The sinc filter frequency domain transfer function is shown in Equation 5.
3
Npf
sin
fMOD
H(f)½ =
pf
N ´ sin
fMOD
where:
N = decimation ratio
(5)
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The sinc filter has notches (or zeroes) that occur at the output data rate and multiples thereof. At these
frequencies, the filter has infinite attenuation. Figure 22 shows the sinc filter frequency response and Figure 23
shows the sinc filter roll-off. With a step change at the input, the filter takes 3 tDR to settle. After a rising edge of
the START signal, the filter takes tSETTLE time to output settled data. The filter settling times at various data rates
are discussed in the START subsection of the SPI Interface section. Figure 24 and Figure 25 show the filter
transfer function until fMOD / 2 and fMOD / 16, respectively, at different data rates. Figure 26 shows the transfer
function extended until 4 fMOD. It can be seen that the ADS131E0x passband repeats itself at every fMOD. The
input R-C antialiasing filters in the system should be chosen such that any interference in frequencies around
multiples of fMOD are attenuated sufficiently.
0
0
-0.5
-1
-20
-40
-60
-1.5
-2
-80
-100
-120
-140
-2.5
-3
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
Normalized Frequency (fIN/fDR
)
Normalized Frequency (fIN/fDR
)
Figure 22. Sinc Filter Frequency Response
Figure 23. Sinc Filter Roll-Off
0
0
DR[2:0] = 110
DR[2:0] = 110
-20
-20
-40
DR[2:0] = 000
DR[2:0] = 000
-40
-60
-60
-80
-80
-100
-120
-140
-100
-120
-140
0
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Normalized Frequency (fIN/fMOD
0
0.01
0.02
0.03
0.04
0.05
0.06
0.07
)
Normalized Frequency (fIN/fMOD
)
Figure 24. Transfer Function of On-Chip
Decimation Filters Until fMOD / 2
10
Figure 25. Transfer Function of On-Chip
Decimation Filters Until fMOD / 16
DR[2:0] = 000
DR[2:0] = 110
-10
-30
-50
-70
-90
-110
-130
0
0.5
1
1.5
2
2.5
3
3.5
4
Normalized Frequency (fIN/fMOD
)
Figure 26. Transfer Function of On-Chip Decimation Filters
Until 4 fMOD for DR[2:0] = 000 and DR[2:0] = 110
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REFERENCE
Figure 27 shows a simplified block diagram of the internal ADS131E0x reference. The reference voltage is
generated with respect to AVSS. When using the internal voltage reference, connect VREFN to AVSS.
22 ꢀF
VCAP1
R1 (1)
Bandgap
2.4 V or 4 V
VREFP
R3 (1)
10 ꢀF
R2 (1)
VREFN
AVSS
To ADC Reference Inputs
(1) For VREF = 2.4 V: R1 = 12.5 kΩ, R2 = 25 kΩ, and R3 = 25 kΩ. For VREF = 4 V: R1 = 10.5 kΩ, R2 = 15 kΩ, and R3 = 35 kΩ.
Figure 27. Internal Reference
The external band-limiting capacitors determine the amount of reference noise contribution. For high-end
systems, the capacitor values should be chosen such that the bandwidth is limited to less than 10 Hz, so that the
reference noise does not dominate the system noise. When using a 3-V analog supply, the internal reference
must be set to 2.4 V. In case of a 5-V analog supply, the internal reference can be set to 4 V by setting the
VREF_4V bit in the CONFIG2 register.
Alternatively, the internal reference buffer can be powered down and VREFP can be driven externally. Figure 28
shows a typical external reference drive circuitry. Power-down is controlled by the PD_REFBUF bit in the
CONFIG3 register. This power-down is also used to share internal references when two devices are cascaded.
By default, the device wakes up in external reference mode.
100 kΩ
10 pF
+5 V
0.1 µF
100 Ω
OPA211
To VREFP Pin
100 Ω
22 µF
10 µF
0.1 µF
+5 V
VIN
OUT
100 µF
REF5025
22 µF
TRIM
Figure 28. External Reference Driver
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CLOCK
The ADS131E0x provide two different device clocking methods: internal and external. Internal clocking is ideally
suited for low-power, battery-powered systems. The internal oscillator is trimmed for accuracy at room
temperature. Accuracy varies over the specified temperature range; refer to the Electrical Characteristics for
details. Clock selection is controlled by the CLKSEL pin and the CLK_EN register bit.
The CLKSEL pin selects either the internal or external clock. The CLK_EN bit in the CONFIG1 register enables
and disables the oscillator clock to be output in the CLK pin. A truth table for these two pins is shown in Table 4.
The CLK_EN bit is useful when multiple devices are used in a daisy-chain configuration. It is recommended that
during power-down the external clock be shut down to save power.
Table 4. CLKSEL Pin and CLK_EN Bit
CONFIG1.CLK_EN
CLKSEL PIN
BIT
CLOCK SOURCE
External clock
CLK PIN STATUS
Input: external clock
3-state
0
1
1
X
0
Internal clock oscillator
Internal clock oscillator
1
Output: internal clock oscillator
DATA FORMAT
The ADS131E0x output resolution is dependent upon the DR[2:0] bit setting in the CONFIG1 register. When
DR[2:0] = 000 or 001, the 16 bits of data per channel are sent in binary twos complement format, MSB first. The
LSB has a weight of VREF / (215 – 1). A positive full-scale input produces an output code of 7FFFh and the
negative full-scale input produces an output code of 8000h. The output clips at these codes for signals exceeding
full-scale. Table 5 summarizes the ideal output codes for different input signals. All 16 bits toggle when the
analog input is at positive or negative full-scale.
Table 5. Ideal Output Code versus Input Signal, LSB Weight = VREF / (215 – 1)
INPUT SIGNAL, VIN
(AINP – AINN)
IDEAL OUTPUT CODE(1)(2)
≥ VREF
7FFFh
0001h
0000h
FFFFh
8000h
+VREF / (215 – 1)
0
–VREF / (215 – 1)
≤ –VREF (215 / 215 – 1)
(1) Assumes gain = 1.
(2) Excludes effects of noise, linearity, offset, and gain error.
When DR[2:0] = 010, 011, 100, 101, or 110, the ADS131E0x outputs 24 bits of data per channel in binary twos
complement format, MSB first. The LSB has a weight of VREF / (223 – 1). A positive full-scale input produces an
output code of 7FFFFFh and the negative full-scale input produces an output code of 800000h. The output clips
at these codes for signals exceeding full-scale. Table 6 summarizes the ideal output codes for different input
signals.
Table 6. Ideal Output Code versus Input Signal, LSB Weight = VREF / (223 – 1)
INPUT SIGNAL, VIN
(AINP – AINN)
IDEAL OUTPUT CODE
7FFFFFh
≥ VREF
+VREF / (223 – 1)
0
000001h
000000h
–VREF / (223 – 1)
≤ –VREF (223 / 223 – 1)
FFFFFFh
800000h
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SPI INTERFACE
The SPI-compatible serial interface consists of four signals: CS, SCLK, DIN, and DOUT. The interface reads
conversion data, reads and writes registers, and controls the ADS131E0x operation. The DRDY output is used
as a status signal to indicate when data are ready. DRDY goes low when new data are available.
Chip Select (CS)
Chip select (CS) selects the ADS131E0x for SPI communication. CS must remain low for the entire serial
communication duration. After the serial communication is finished, four or more tCLK cycles must elapse before
taking CS high. When CS is taken high, the serial interface is reset, SCLK and DIN are ignored, and DOUT
enters a high-impedance state. DRDY asserts when data conversion is complete, regardless of whether CS is
high or low.
Serial Clock (SCLK)
SCLK is the serial peripheral interface (SPI) serial clock. It is used to shift in commands and shift out data from
the device. The serial clock (SCLK) features a Schmitt-triggered input and clocks data on the DIN and DOUT
pins into and out of the ADS131E0x.
Care should be taken to prevent glitches on SCLK while CS is low. Glitches as small as 1 ns wide could be
interpreted as a valid serial clock. After eight serial clock events, the ADS131E0x assume an instruction must be
interrupted and executed. If it is suspected that instructions are being interrupted erroneously, toggle CS high
and back low to return the chip to normal operation. It is also recommended to issue serial clocks in multiples of
eight. The absolute maximum SCLK limit is specified in the Serial Interface Timing table.
For a single device, the minimum speed needed for SCLK depends on the number of channels, number of bits of
resolution, and output data rate. (For multiple cascaded devices, see the Standard Mode subsection of the
Multiple Device Configuration section.) The SCLK rate limitation, as described by Equation 6, applies to RDATAC
mode.
tSCLK < (tDR – 4 tCLK) / (NBITSNCHANNELS + 24)
(6)
For example, if the ADS131E0x is used in an 8-kSPS mode (eight channels, 24-bit resolution), the minimum
SCLK speed is 1.72 MHz.
Data retrieval can be done either by putting the device in RDATAC mode or by issuing an RDATA command for
data on demand. The SCLK rate limitation, as described by Equation 6, applies to RDATAC mode. For the
RDATA command, the limitation applies if data must be read in between two consecutive DRDY signals. The
above calculation assumes that there are no other commands issued in between data captures.
Data Input (DIN)
The data input pin (DIN) is used along with SCLK to communicate with the ADS131E0x (opcode commands and
register data). The device latches data on DIN on the SCLK falling edge.
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Data Output (DOUT)
The data output pin (DOUT) is used with SCLK to read conversion and register data from the ADS131E0x. Data
on DOUT are shifted out on the SCLK rising edge. DOUT goes to a high-impedance state when CS is high. In
read data continuous mode (see the SPI Command Definitions section for more details), the DOUT output line
also indicates when new data are available. This feature can be used to minimize the number of connections
between the device and system controller.
Figure 29 shows the ADS131E0x data output protocol.
DRDY
CS
SCLK
N SCLKS
DOUT
DIN
STAT
24-Bit
CH1
n-Bit
CH2
n-Bit
CH3
n-Bit
CH4
n-Bit
CH5
n-Bit
CH6
n-Bit
CH7
n-Bit
CH8
n-Bit
NOTE: N SCLKs = (N bits)(N channels) + 24 bits. N-bit is dependent upon the DR[2:0] registry bit settings (N = 16 or 24).
Figure 29. ADS131E0x SPI Bus Data Output (Eight Channels)
Data Retrieval
Data retrieval can be accomplished in one of two methods. The read data continuous command (see the
RDATAC: Read Data Continuous section) can be used to set the device in a mode to read the data continuously
without sending opcodes. The read data command (see the RDATA: Read Data section) can be used to read
just one data output from the device (see the SPI Command Definitions section for more details). The conversion
data are read by shifting the data out on DOUT. The MSB of the data on DOUT is clocked out on the first SCLK
rising edge. DRDY returns to high on the first SCLK falling edge. DIN should remain low for the entire read
operation.
The number of bits in the data output depends on the number of channels and the number of bits per channel.
For the ADS131E0x with 32- and 64-kSPS data rates, the number of data outputs is [(24 status bits + 16 bits × 8
channels) = 152 bits]. The format of the 24 status bits is (1100 + FAULT_STATP + FAULT_STATN + GPIO[7:4]).
The data format for each channel data are twos complement and MSB first. When channels are powered down
using the user register setting, the corresponding channel output is set to '0'. However, the sequence of channel
outputs remains the same. The last four (ADS131E04) or two (ADS131E06) channel outputs shown in Figure 29
are '0's.
The ADS131E0x also provide a multiple readback feature. The data can be read out multiple times by simply
giving more SCLKs, in which case the MSB data byte repeats after reading the last byte. The DAISY_IN bit in
the CONFIG1 register must be set to '1' for multiple readbacks.
Data Ready (DRDY)
DRDY is an output. When it transitions low, new conversion data are ready. The CS signal has no effect on the
data ready signal. DRDY behavior is determined by whether the device is in RDATAC mode or the RDATA
command is being used to read data on demand. (See the RDATAC: Read Data Continuous and RDATA: Read
Data subsections of the SPI Command Definitions section for further details).
When reading data with the RDATA command, the read operation can overlap the next DRDY occurrence
without data corruption.
The START pin or the START command is used to place the device either in normal data capture mode or pulse
data capture mode.
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Figure 30 shows the relationship between DRDY, DOUT, and SCLK during data retrieval (in case of an
ADS131E0x with a selected data rate that gives 16-bit resolution). DOUT is latched out at the SCLK rising edge;
DRDY is pulled high at the SCLK falling edge. Note that DRDY goes high on the first SCLK falling edge
regardless of whether data are being retrieved from the device or a command is being sent through the DIN pin.
For 24-bit resolution, the data starts from bit 215.
DRDY
DOUT
SCLK
Bit 71
Bit 70
Bit 69
Figure 30. DRDY with Data Retrieval (CS = 0)
GPIO
The ADS131E0x have a total of four general-purpose digital I/O (GPIO) pins available in the normal mode of
operation. The digital I/O pins are individually configurable as either inputs or outputs through the GPIOC bits
register. The GPIOD bits in the GPIO register control the level of the pins. When reading the GPIOD bits, the
data returned are the logic level of the pins, whether they are programmed as inputs or outputs. When the GPIO
pin is configured as an input, a write to the corresponding GPIOD bit has no effect. When configured as an
output, a write to the GPIOD bit sets the output value.
If configured as inputs, these pins must be driven (do not float). The GPIO pins are set as inputs after power-on
or after a reset. Figure 31 shows the GPIO port structure. The pins should be shorted to DGND if not used.
GPIO Data (Read)
GPIO Pin
GPIO Data (Write)
GPIO Control
Figure 31. GPIO Port Pin
Power-Down (PWDN)
When PWDN is pulled low, all on-chip circuitry is powered down. To exit power-down mode, take the PWDN pin
high. Upon exiting from power-down mode, the internal oscillator and the reference require time to wake up. It is
recommended that during power-down the external clock is shut down to save power.
Reset (RESET)
There are two methods to reset the ADS131E0x: pull the RESET pin low, or send the RESET opcode command.
When using the RESET pin, take it low to force a reset. Make sure to follow the minimum pulse width timing
specifications before taking the RESET pin back high. The RESET command takes effect on the eighth SCLK
falling edge of the opcode command. On reset it takes 18 tCLK cycles to complete initialization of the configuration
registers to the default states and start the conversion cycle. Note that an internal RESET is automatically issued
to the digital filter whenever the CONFIG1 register is set to a new value with a WREG command.
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START
The START pin must be set high (for a minimum of 2 tCLKs) or the START command sent to begin conversions.
When START is low, or if the START command has not been sent, the device does not issue a DRDY signal
(conversions are halted).
When using the START opcode to control conversion, hold the START pin low. In multiple device configurations
the START pin is used to synchronize devices (see the Multiple Device Configuration subsection of the SPI
Interface section for more details).
Settling Time
The settling time (tSETTLE) is the time it takes for the converter to output fully-settled data when the START signal
is pulled high. Once START is pulled high, DRDY is also pulled high. The next DRDY falling edge indicates that
data are ready. Figure 32 shows the timing diagram and Table 7 shows the settling time for different data rates.
The settling time depends on fCLK and the decimation ratio (controlled by the DR[2:0] bits in the CONFIG1
register). Table 5 shows the settling time as a function of tCLK. Note that when START is held high and there is a
step change in the input signal, it takes 3 tDR for the filter to settle to the new value. Settled data are available on
the fourth DRDY pulse.
START Pin
tSETTLE
or
DIN
START Opcode
tDR
4/fCLK
DRDY
Figure 32. Settling Time
Table 7. Settling Time for Different Data Rates
DR[2:0]
SETTLING TIME
UNIT
tCLK
tCLK
tCLK
tCLK
tCLK
tCLK
tCLK
000
001
010
011
100
101
110
152
296
584
1160
2312
4616
9224
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Continuous Mode
Conversions begin when the START pin is taken high or when the START opcode command is sent. As seen in
Figure 33, the DRDY output goes high when conversions are started and then goes low when data are ready.
Conversions continue indefinitely until the START pin is taken low or the STOP opcode command is transmitted.
When the START pin is pulled low or the stop command is issued, the conversion in progress is allowed to
complete. Figure 34 and Table 8 show the required DRDY timing to the START pin and the START and STOP
opcode commands when controlling conversions in this mode. To keep the converter running continuously, the
START pin can be permanently tied high.
START Pin
or
DIN
or
START(1)
Opcode
STOP(1)
Opcode
tDR
SETTLE
t
DRDY
(1) START and STOP opcode commands take effect on the seventh SCLK falling edge.
Figure 33. Continuous Conversion Mode
tSDSU
DRDY and DOUT
tDSHD
START Pin
or
STOP(1)
STOP(1)
STOP Opcode
(1) START and STOP commands take effect on the seventh SCLK falling edge at the end of the opcode transmission.
Figure 34. START to DRDY Timing
Table 8. Timing Characteristics for Figure 34(1)
SYMBOL
DESCRIPTION
MIN
UNIT
START pin low or STOP opcode to DRDY setup time
to halt further conversions
tSDSU
16
1/2 fMOD
START pin low or STOP opcode to complete current
conversion
tDSHD
16
1/2 fMOD
(1) START and STOP commands take effect on the seventh SCLK falling edge at the end of the opcode transmission.
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MULTIPLE DEVICE CONFIGURATION
The ADS131E0x are designed to provide configuration flexibility when multiple devices are used in a system.
The serial interface typically needs four signals: DIN, DOUT, SCLK, and CS. With one additional chip select
signal per device, multiple devices can be connected together. The number of signals needed to interface n
devices is 3 + n.
To use the internal oscillator in a daisy-chain configuration, one device must be set as the master for the clock
source with the internal oscillator enabled (CLKSEL pin = 1) and the internal oscillator clock brought out of the
device by setting the CLK_EN register bit to '1'. This master device clock is used as the external clock source for
the other devices.
When using multiple devices, the devices can be synchronized with the START signal. The delay from START to
the DRDY signal is fixed for a fixed data rate (see the START subsection of the SPI Interface section for more
details on the settling times). Figure 35 shows the behavior of two devices when synchronized with the START
signal.
There are two ways to connect multiple devices with an optimal number of interface pins: standard mode and
daisy-chain mode. Refer to the Standard Mode and Daisy-Chain Mode sections for details.
Device
1
START
CLK
START
CLK
DRDY
DRDY
1
Device
2
START
CLK
DRDY
DRDY
2
CLK
START
1
DRDY
2
DRDY
Figure 35. Synchronizing Multiple Converters
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Standard Mode
Figure 36a shows a configuration with two devices cascaded together. Both devices are an ADS131E0x (eight-
channel) device. Together, they create a system with 16 channels. DOUT, SCLK, and DIN are shared. Each
device has its own chip select. When a device is not selected by the corresponding CS being driven to logic 1,
the DOUT of this device is high-impedance. This structure allows the other device to take control of the DOUT
bus. This configuration method is suitable for the majority of applications.
Daisy-Chain Mode
Daisy-chain mode is enabled by setting the DAISY_IN bit in the CONFIG1 register. Figure 36b shows the daisy-
chain configuration. In this mode SCLK, DIN, and CS are shared across multiple devices. The DOUT pin of
device 1 is connected to the DAISY_IN of device 0, thereby creating a daisy-chain for the data. One extra SCLK
must be issued between each data set. Also, when using daisy-chain mode, the multiple readback feature is not
available. Short the DAISY_IN pin to digital ground if not used. Figure 2 describes the required ADS131E0x
timing shown in Figure 36. Data from the ADS131E0x appear first on DOUT, followed by a don’t care bit, and
finally by the status and data words from the second ADS131E0x device.
When all devices in the chain operate in the same register setting, DIN can be shared as well and thereby
reduce the SPI communication signals to four, regardless of the number of devices. Furthermore, an external
clock must be used.
START(1)
START(1)
CLK
START
CLK
START
CLK
DRDY
CS
INT
DRDY
CS
INT
GPO0
GPO1
SCLK
CLK
GPO
SCLK
DIN
SCLK
DIN
SCLK
MOSI
MISO
ADS13xE0x
(Device 0)
ADS13xE0x
(Device 0)
MOSI
MISO
DOUT0
DOUT0
DAISY_IN0
Host Processor
Host Processor
START
CLK
DOUT
1
DRDY
CS
DRDY
CS
START
CLK
SCLK
SCLK
DIN
DIN
ADS13xE0x
(Device 1)
ADS13xE0x
(Device 1)
DOUT1
DAISY_IN1
0
a) Standard Configuration
b) Daisy-Chain Configuration
(1) To reduce pin count, set the START pin low and use the START serial command to synchronize and start conversions.
Figure 36. Multiple Device Configurations
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Note that from Figure 2, the SCLK rising edge shifts data out of the ADS131E0x on DOUT. The SCLK rising
edge is also used to latch data into the device DAISY_IN pin down the chain. This architecture allows for a faster
SCLK rate speed, but it also makes the interface sensitive to board-level signal delays. The more devices in the
chain, the more challenging it could become to adhere to setup and hold times. A star-pattern connection of
SCLK to all devices, minimizing length of DOUT, and other printed circuit board (PCB) layout techniques helps.
Placing delay circuits (such as buffers) between DOUT and DAISY_IN also helps mitigate this challenge. One
other option is to insert a D flip-flop between DOUT and DAISY_IN clocked on an inverted SCLK. Also note that
daisy-chain mode requires some software overhead to recombine data bits spread across byte boundaries.
Figure 37 shows a timing diagram for daisy-chain mode.
1
DOUT
1
1
MSB
LSB
0
DAISY_IN
CLKS
DOUT
1
2
3
n
n+1
n+2
n+3
0
0
1
1
0
XX
MSB
LSB
MSB
LSB
Data From First Device (ADS131E04/6/8)
Data From Second Device (ADS131E04/6/8)
NOTE: n = (number of channels) × (resolution) + 24 bits. The number of channels is 4, 6, or 8. Resolution is 16-bit or 24-bit.
Figure 37. Daisy-Chain Timing
The maximum number of devices that can be daisy-chained depends on the data rate at which the device is
operated at. The maximum number of devices can be approximately calculated with Equation 7.
fSCLK
NDEVICES
=
fDR (NBITS)(NCHANNELS) + 24
where:
NBITS = device resolution (depends on RDR[1:0] setting),
and NCHANNELS = number of channels in the device (4, 6, or 8).
(7)
For example, when the ADS131E08 (eight-channel version) is operated at a 24-bit, 8-kSPS data rate with fSCLK
10 MHz, up to six devices can be daisy-chained together.
=
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SPI COMMAND DEFINITIONS
The ADS131E0x provide flexible configuration control. The opcode commands, summarized in Table 9, control
and configure device operation. The opcode commands are stand-alone, except for the register read and register
write operations that require a second command byte plus data. CS can be taken high or held low between
opcode commands but must stay low for the entire command operation (especially for multibyte commands).
System opcode commands and the RDATA command are decoded by the ADS131E0x on the seventh SCLK
falling edge. The register read and write opcodes are decoded on the eighth SCLK falling edge. Be sure to follow
SPI timing requirements when pulling CS high after issuing a command.
Table 9. Command Definitions
COMMAND
System Commands
WAKEUP
DESCRIPTION
FIRST BYTE
SECOND BYTE
Wake-up from standby mode
Enter standby mode
0000 0010 (02h)
0000 0100 (04h)
0000 0110 (06h)
0000 1000 (08h)
0000 1010 (0Ah)
0001 1010 (1Ah)
STANDBY
RESET
Reset the device
START
Start or restart (synchronize) conversions
Stop conversion
STOP
OFFSETCAL
Channel offset calibration
Data Read Commands
Enable Read Data Continuous mode.
RDATAC
0001 0000 (10h)
This mode is the default mode at power-up.(1)
SDATAC
RDATA
Stop Read Data Continuously mode
0001 0001 (11h)
0001 0010 (12h)
Read data by command; supports multiple read back.
Register Read Commands
RREG
WREG
Read n nnnn registers starting at address r rrrr
Write n nnnn registers starting at address r rrrr
001r rrrr (2xh)(2)
010r rrrr (4xh)(2)
000n nnnn(2)
000n nnnn(2)
(1) When in RDATAC mode, the RREG command is ignored.
(2) n nnnn = number of registers to be read or written – 1. For example, to read or write three registers, set n nnnn = 0 (0010). r rrrr =
starting register address for read and write opcodes.
WAKEUP: Exit STANDBY Mode
This opcode exits low-power standby mode; see the STANDBY: Enter STANDBY Mode subsection of the SPI
Command Definitions section. Be sure to allow enough time for all circuits in shutdown mode to power up (see
the Electrical Characteristics for details). There are no SCLK rate restrictions for this command and it can be
issued at any time. Any following command must be sent after 4 tCLK cycles.
STANDBY: Enter STANDBY Mode
This opcode command enters low-power standby mode. All parts of the circuit are shut down except for the
reference section. The standby mode power consumption is specified in the Electrical Characteristics. There are
no SCLK rate restrictions for this command and it can be issued at any time. Do not send any other
command other than the wakeup command after the device enters standby mode.
RESET: Reset Registers to Default Values
This command resets the digital filter cycle and returns all register settings to default values. See the Reset
(RESET) subsection of the SPI Interface section for more details. There are no SCLK rate restrictions for this
command and it can be issued at any time. It takes 18 tCLK cycles to execute the RESET command. Avoid
sending any commands during this time.
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START: Start Conversions
This opcode starts data conversions. Tie the START pin low to control conversions by command. If conversions
are in progress, this command has no effect. The STOP opcode command is used to stop conversions. If the
START command is immediately followed by a STOP command, then have a gap of 4 tCLK cycles between them.
When the START opcode is sent to the device, keep the START pin low until the STOP command is issued.
(See the START subsection of the SPI Interface section for more details.) There are no SCLK rate restrictions
for this command and it can be issued at any time.
STOP: Stop Conversions
This opcode stops conversions. Tie the START pin low to control conversions by command. When the STOP
command is sent, the conversion in progress completes and further conversions are stopped. If conversions are
already stopped, this command has no effect. There are no SCLK rate restrictions for this command and it
can be issued at any time.
OFFSETCAL: Channel Offset Calibration
This command is used to cancel the channel offset. OFFSETCAL must be executed every time there is a change
in PGA gain settings.
RDATAC: Read Data Continuous
This opcode enables the conversion data output on each DRDY without the need to issue subsequent read data
opcodes. This mode places the conversion data in the output register and may be shifted out directly. The read
data continuous mode is the default mode of the device and the device defaults in this mode on power-up.
RDATAC mode is cancelled by the Stop Read Data Continuous command. If the device is in RDATAC mode, an
SDATAC command must be issued before any other commands can be sent to the device. There are no SCLK
rate restrictions for this command. However, subsequent data retrieval SCLKs or the SDATAC opcode
command should wait at least 4 tCLK cycles for the command to execute. RDATAC timing is shown in Figure 38.
As Figure 38 shows, there is a keep out zone of 4 tCLK cycles around the DRDY pulse where this command
cannot be issued in. If no data are retrieved from the device, DOUT and DRDY behave similarly in this mode. To
retrieve data from the device after the RDATAC command is issued, make sure either the START pin is high or
the START command is issued. Figure 38 shows the recommended way to use the RDATAC command.
RDATAC is ideally-suited for applications such as data loggers or recorders where registers are set once and do
not need to be reconfigured.
START
DRDY
(1)
tUPDATE
CS
SCLK
RDATAC Opcode
DIN
Hi-Z
DOUT
Status Register + n-Channel Data
Next Data
(1) tUPDATE = 4 / fCLK. Do not read data during this time.
Figure 38. RDATAC Usage
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SDATAC: Stop Read Data Continuous
This opcode cancels the Read Data Continuous mode. There are no SCLK rate restrictions for this command,
but the following command must wait for 4 tCLK cycles to execute.
RDATA: Read Data
Issue this command after DRDY goes low to read the conversion result (in Stop Read Data Continuous mode).
There are no SCLK rate restrictions for this command, and there is no wait time needed for subsequent
commands or data retrieval SCLKs. To retrieve data from the device after the RDATA command is issued, make
sure either the START pin is high or the START command is issued. When reading data with the RDATA
command, the read operation can overlap the next DRDY occurrence without data corruption. Figure 39 shows
the recommended way to use the RDATA command. RDATA is best suited for systems where register settings
must be read or changed often between conversion cycles.
START
DRDY
CS
SCLK
RDATA Opcode
RDATA Opcode
DIN
Hi-Z
DOUT
Status Register + n-Channel Data (216 Bits)
Figure 39. RDATA Usage
Sending Multibyte Commands
The ADS131E0x serial interface decodes commands in bytes and requires 4 tCLK cycles to decode and execute.
Therefore, when sending multibyte commands, a 4-tCLK period must separate the end of one byte (or opcode)
and the next.
Assuming SCLK is 2.048 MHz, then tSDECODE (4 tCLK) is 1.96 µs. When SCLK is 16 MHz, one byte can be
transferred in 500 ns. This byte transfer time does not meet the tSDECODE specification; therefore, a delay must be
inserted so the end of the second byte arrives 1.46 µs later. If SCLK is 4 MHz, one byte is transferred in 2 µs.
Because this transfer time exceeds the tSDECODE specification, the processor can send subsequent bytes without
delay. In this later scenario, the serial port can be programmed to move from single-byte transfers per cycle to
multiple bytes.
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RREG: Read From Register
This opcode reads register data. The Register Read command is a two-byte opcode followed by the register data
output. The first byte contains the command opcode and the register address. The second opcode byte specifies
the number of registers to read – 1.
First opcode byte: 001r rrrr, where r rrrr is the starting register address.
Second opcode byte: 000n nnnn, where n nnnn is the number of registers to read – 1.
The 17th SCLK rising edge of the operation clocks out the MSB of the first register, as shown in Figure 40. When
the device is in read data continuous mode, an SDATAC command must be issued before the RREG command
can be issued. The RREG command can be issued at any time. However, because this command is a multibyte
command, there are SCLK rate restrictions depending on how the SCLKs are issued. See the Serial Clock
(SCLK) subsection of the SPI Interface section for more details. Note that CS must be low for the entire
command.
CS
1
9
17
25
SCLK
DIN
OPCODE 1
OPCODE 2
REG DATA
REG DATA + 1
DOUT
Figure 40. RREG Command Example: Read Two Registers Starting from Register 00h (ID Register)
(OPCODE 1 = 0010 0000, OPCODE 2 = 0000 0001)
WREG: Write to Register
This opcode writes register data. The Register Write command is a two-byte opcode followed by the register data
input. The first byte contains the command opcode and the register address.
The second opcode byte specifies the number of registers to write – 1.
First opcode byte: 010r rrrr, where r rrrr is the starting register address.
Second opcode byte: 000n nnnn, where n nnnn is the number of registers to write – 1.
After the opcode bytes, the register data follows (in MSB-first format), as shown in Figure 41. The WREG
command can be issued at any time. However, because this command is a multibyte command, there are SCLK
rate restrictions depending on how the SCLKs are issued. See the Serial Clock (SCLK) subsection of the SPI
Interface section for more details. Note that CS must be low for the entire command.
CS
1
9
17
25
SCLK
DIN
OPCODE 1
OPCODE 2
REG DATA 1
REG DATA 2
DOUT
Figure 41. WREG Command Example: Write Two Registers Starting from 00h (ID Register)
(OPCODE 1 = 0100 0000, OPCODE 2 = 0000 0001)
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REGISTER MAP
Table 10 describes the various ADS131E0x registers.
Table 10. Register Assignments(1)
RESET
VALUE
(Hex)
ADDRESS
REGISTER
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
NU_CH2
DR1
BIT 0
NU_CH1
DR0
Device Settings (Read-Only Registers)
00h ID
Global Settings Across Channels
xx
REV_ID2
REV_ID1
REV_ID0
1
0
0
01h
02h
03h
04h
CONFIG1
CONFIG2
CONFIG3
FAULT
91
E0
40
00
1
DAISY_IN
CLK_EN
1
1
0
DR2
TEST_AMP0
PDB_OPAMP
0
1
1
INT_TEST
0
TEST_FREQ1 TEST_FREQ0
PDB_REFBUF
COMP_TH2
1
VREF_4V
COMP_TH0
0
0
OPAMP_REF
0
0
0
0
0
COMP_TH1
Channel-Specific Settings
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
CH1SET
CH2SET
CH3SET
CH4SET
CH5SET
CH6SET
CH7SET
CH8SET
10
10
10
10
10
10
10
10
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PD8
GAIN12
GAIN22
GAIN32
GAIN42
GAIN52
GAIN62
GAIN72
GAIN82
GAIN11
GAIN21
GAIN31
GAIN41
GAIN51
GAIN61
GAIN71
GAIN81
GAIN10
GAIN20
GAIN30
GAIN40
GAIN50
GAIN60
GAIN70
GAIN80
0
0
0
0
0
0
0
0
MUX12
MUX22
MUX32
MUX42
MUX52
MUX62
MUX72
MUX82
MUX11
MUX21
MUX31
MUX41
MUX51
MUX61
MUX71
MUX81
MUX10
MUX20
MUX30
MUX40
MUX50
MUX60
MUX70
MUX80
Fault Detect Status Registers (Read-Only Registers)
12h
13h
FAULT_STATP
FAULT_STATN
00
00
IN8P_FAULT
IN8N_FAULT
IN7P_FAULT
IN7N_FAULT
IN6P_FAULT
IN6N_FAULT
IN5P_FAULT
IN5N_FAULT
IN4P_FAULT
IN4N_FAULT
IN3P_FAULT
IN3N_FAULT
IN2P_FAULT
IN2N_FAULT
IN1P_FAULT
IN1N_FAULT
GPIO and Other Registers
14h GPIO
0F
GPIOD4
GPIOD3
GPIOD2
GPIOD1
GPIOC4
GPIOC3
GPIOC2
GPIOC1
(1) Registers 0Dh, 0Eh, 0Fh, 10h, and 11h must be written to all 0's.
User Register Description
ID: ID Control Register (Factory-Programmed, Read-Only)
Address = 00h
BIT 7
BIT 6
BIT 5
BIT 4
1
BIT 3
0
BIT 2
0
BIT 1
NU_CH2
BIT 0
REV_ID2
REV_ID1
REV_ID0
NU_CH1
This register is programmed during device manufacture to indicate device characteristics.
Bits[7:5]
REV_ID[2:0]: Device family identification
These bits indicate the device family.
000, 001, 010, 011, 100, 101 = Reserved
110 = ADS131E08
111 = Reserved
Bit 4
Must be set to '1'
This bit reads high.
Bits[3:2]
Bits[1:0]
Must be set to '0'
These bits read low.
NU_CH[2:1]: Factory-programmed device identification bits (read-only)
These bits indicate the device version.
00 = 4-channel device
01 = 6-channel device
10 = 8-channel device
11 = Reserved
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CONFIG1: Configuration Register 1
Address = 01h
BIT 7
1
BIT 6
BIT 5
BIT 4
1
BIT 3
0
BIT 2
DR2
BIT 1
DR1
BIT 0
DR0
DAISY_IN
CLK_EN
This register configures each ADC channel sample rate.
Bit 7
Bit 6
Must be set to '1'
DAISY_IN: Daisy-chain and multiple read-back mode
This bit determines which mode is enabled.
0 = Daisy-chain mode (default)
1 = Multiple read-back mode
Bit 5
CLK_EN: CLK connection(1)
This bit determines if the internal oscillator signal is connected to the CLK pin when the CLKSEL pin = 1.
0 = Oscillator clock output disabled (default)
1 = Oscillator clock output enabled
Bit 4
Must be set to '1'
Bit 3
Must be set to '0'
Bits[2:0]
DR[2:0]: Output data rate
These bits determine the output data rate and resolution. See Table 11 for details.
Modulator clock fMOD = fCLK / 2. Where fMOD = 1.024 MHz.
(1) Additional power is consumed when driving external devices.
Table 11. Data Rate Settings
DR{2:0]
000
RESOLUTION
DATA RATE (kSPS)
16-bit output
16-bit output
24-bit output
24-bit output
24-bit output
24-bit output
24-bit output
Do not use
64
001
32 (default)
010
16
8
011
100
4
101
2
110
1
111
NA
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CONFIG2: Configuration Register 2
Address = 02h
BIT 7
1
BIT 6
1
BIT 5
1
BIT 4
BIT 3
0
BIT 2
BIT 1
BIT 0
INT_TEST
TEST_AMP0
TEST_FREQ1 TEST_FREQ0
This register configures the test signal generation. See the Input Multiplexer section for more details.
Bits[7:5]
Bit 4
Must be set to '1'
INT_TEST: Test source
This bit determines the source for the Test signal.
0 = Test signals are driven externally (default)
1 = Test signals are generated internally
Bit 3
Bit 2
Must be set to '0'
TEST_AMP: Test signal amplitude
These bits determine the Calibration signal amplitude.
0 = 1 × –(VREFP – VREFN) / 2.4 mV (default)
1 = 2 × –(VREFP – VREFN) / 2.4 mV
Bits[1:0]
TEST_FREQ[1:0]: Test signal frequency
These bits determine the calibration signal frequency.
00 = Pulsed at fCLK / 221 (default)
01 = Pulsed at fCLK / 220
10 = Not used
11 = At dc
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CONFIG3: Configuration Register 3
Address = 03h
BIT 7
BIT 6
1
BIT 5
BIT 4
0
BIT 3
BIT 2
BIT 1
0
BIT 0
0
PDB_REFBUF
VREF_4V
OPAMP_REF
PDB_OPAMP
This register configures the multireference operation.
Bit 7
PDB_REFBUF: Power-down reference buffer
This bit determines the power-down reference buffer state.
0 = Power-down internal reference buffer (default)
1 = Enable internal reference buffer
Bit 6
Bit 5
Must be set to '1'
Default is '1' at power-up.
VREF_4V: Reference voltage
This bit determines the reference voltage, VREFP.
0 = VREFP is set to 2.4 V (default)
1 = VREFP is set to 4 V (use only with a 5-V analog supply)
Bit 4
Bit 3
Must be set to '0'
OPAMP_REF: Op amp reference
This bit determines whether the op amp noninverting input connects to the OPAMPP pin or to the internally-derived 1/2
supply (AVDD + AVSS) / 2.
0 = Noninverting input connected to the OPAMPP pin (default)
1 = Noninverting input connected to (AVDD + AVSS) / 2
Bit 2
PDB_OPAMP: Op amp power down
This bit determines the power-down reference buffer state.
0 = Power-down op amp (default)
1 = Enable op amp
Bits[1:0]
Must be set to '0'
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FAULT: Fault Detect Control Register
Address = 04h
BIT 7
BIT 6
BIT 5
BIT 4
0
BIT 3
0
BIT 2
0
BIT 1
0
BIT 0
0
COMP_TH2
COMP_TH1
COMP_TH0
This register configures the fault detection operation.
Bits[7:5]
COMP_TH[2:0]: Fault detect comparator threshold
These bits determine the fault detect comparator threshold level setting. See the Fault Detection section for a detailed
description.
Comparator high-side threshold
000 = 95% (default)
001 = 92.5%
010 = 90%
011 = 87.5%
100 = 85%
101 = 80%
110 = 75%
111 = 70%
Comparator low-side threshold
000 = 5% (default)
001 = 7.5%
010 = 10%
011 = 12.5%
100 = 15%
101 = 20%
110 = 25%
111 = 30%
Bits[4:0]
Must be set to '0'
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CHnSET: Individual Channel Settings (n = 1 to 8)
Address = 05h to 0Ch
BIT 7
PDn
BIT 6
BIT 5
BIT 4
BIT 3
0
BIT 2
BIT 1
BIT 0
GAINn2
GAINn1
GAINn0
MUXn2
MUXn1
MUXn0
This register configures the power mode, PGA gain, and multiplexer settings channels. See the Input Multiplexer
section for details. CH[2:8]SET are similar to CH1SET, corresponding to the respective channels (refer to
Table 10).
Bit 7
PDn: Power-down (n = individual channel number)
This bit determines the channel power mode for the corresponding channel.
0 = Normal operation (default)
1 = Channel power-down
Bits[6:4]
GAINn[2:0]: PGA gain (n = individual channel number)
These bits determine the PGA gain setting.
000 = Do not use
001 = 1 (default)
010 = 2
011 = Do not use
100 = 4
101 = 8
110 = 12
111 = Do not use
Bit 3
Must be set to '0'
Bits[2:0]
MUXn[2:0]: Channel input (n = individual channel number)
These bits determine the channel input selection.
000 = Normal input (default)
001 = Input shorted (for offset or noise measurements)
010 = Do not use
011 = MVDD for supply measurement
100 = Temperature sensor
101 = Test signal
110 = Do not use
111 = Do not use
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FAULT_STATP: Fault Detect Positive Input Status
Address = 12h
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
IN8P_FAULT
IN7P_FAULT
IN6P_FAULT
IN5P_FAULT
IN4P_FAULT
IN3P_FAULT
IN2P_FAULT
IN1P_FAULT
This register stores the status of whether the positive input on each channel has a fault or not. See the Fault
Detection section for details. Ignore the FAULT_STATP values if the corresponding FAULT_SENSP bits are not
set to '1'.
FAULT_STATN: Fault Detect Negative Input Status
Address = 13h
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
IN8N_FAULT
IN7N_FAULT
IN6N_FAULT
IN5N_FAULT
IN4N_FAULT
IN3N_FAULT
IN2N_FAULT
IN1N_FAULT
This register stores the status of whether the negative input on each channel has a fault or not. See the Fault
Detection section for details. Ignore the FAULT_STATN values if the corresponding FAULT_SENSN bits are not
set to '1'.
GPIO: General-Purpose IO Register
Address = 14h
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
GPIOD4
GPIOD3
GPIOD2
GPIOD1
GPIOC4
GPIOC3
GPIOC2
GPIOC1
This register controls the action of the three GPIO pins.
Bits[7:4]
Bits[1:0]
GPIOD[4:1]: GPIO data
These bits are used to read and write data to the GPIO ports.
When reading the register, the data returned correspond to the state of the GPIO external pins, whether they are
programmed as inputs or outputs. As outputs, a write to the GPIOD sets the output value. As inputs, a write to the GPIOD
has no effect.
GPIOC[4:1]: GPIO control (corresponding to GPIOD)
These bits determine if the corresponding GPIOD pin is an input or output.
0 = Output
1 = Input (default)
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POWER MONITORING SPECIFIC APPLICATIONS
All channels of the ADS131E0x family of devices are exactly identical, yet independently configurable, thus
giving the user the flexibility of selecting any channel for voltage or current monitoring. An overview of this
system is illustrated in Figure 42. Also, the simultaneously sampling capability of the device allows the user to
monitor both the current and the voltage at the same time. The full-scale differential input voltage of each
channel is determined by the PGA gain setting (see the CHnSET: Individual Channel Settings section) for the
respective channel and VREF (see the CONFIG3: Configuration Register 3 section). Table 12 summarizes the full-
scale differential input voltage range for an internal VREF
.
Table 12. Full-Scale Differential Input Voltage Summary
FULL-SCALE DIFFERENTIAL INPUT
VREF
PGA GAIN
VOLTAGE, FSDI (VPP
)
RMS VOLTAGE [= FSDI / (2√2)] (VRMS)
1
2
4.8
2.4
1.2
0.6
0.4
8
1.698
0.849
0.424
0.212
0.141
2.828
1.414
0.707
0.354
0.236
2.4 V
4
8
12
1
2
4
4.0 V
4
2
8
1
12
0.66
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Neutral
Phase C
Phase B
Phase A
+1.5 V
AVDD
+1.8 V
DVDD
A
INP1
N
INN1
INP2
INN2
INP3
B
N
INN3
INP4
Device
INN4
INP5
C
INN5
INP6
N
INN6
INP7
INN7
AVSS
-1.5 V
Figure 42. Overview of Power Monitoring System
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CURRENT SENSING
Figure 43 shows a simplified diagram of typical configurations used for current sensing with a Rogowski coil,
current transformer (CT), or an air coil that outputs a current or voltage. In the case of the current output
transformers, the burden resistors (R1) are used for current-to-voltage conversion. The output of the burden
resistors is connected to the ADS131E0x INP and INN inputs through an antialiasing RC filter for current
sensing. In the case of the voltage output transformers (such as certain types of Rogowski coils), the output
terminals of the transformers are directly connected to the ADS131E0x INP and INN inputs through an
antialiasing RC filter for current sensing. The common-mode bias voltage (AVDD + AVSS) / 2, can be obtained
from the ADS131E0x by either configuring the internal op amp in a unity-gain configuration using the RF resistor
and setting bit 3 of the CONFIG3 register, or it can be generated externally with a simple resistor divider network
between the positive and negative supplies.
The value of resistor R1 for the current output transformer and turns ratio of the transformer should be selected
so as not to exceed the ADS131E0x full-scale differential input voltage (FSDI) range. Likewise, the output
voltage (V) for the voltage output transformer should be selected to not exceed the FSDI. In addition, the
selection of resistor (R) and turns ratio should not saturate the transformer over the full operating dynamic range
of the energy meter. Figure 43a shows differential input current sensing and Figure 43b shows single-ended
input sensing.
Device
Device
N
L
N
L
I
R2
R2
INP
INN
INP
INN
R1
R1
EMI
Filter
EMI
Filter
V
C
C
To PGA
To PGA
R2
I
OPAMP_REF
OPAMP_REF
(AVDD + AVSS)
2
(AVDD + AVSS)
2
OPAMPOUT
OPAMPOUT
-
-
Rf
Rf
OPAMPN
OPAMPP
OPAMPN
OPAMPP
(b) Voltage Output CT with Single-Ended Input
(a) Current Output CT with Differential Input
Figure 43. Simplified Current Sensing Connections
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VOLTAGE SENSING
Figure 44 shows a simplified diagram of commonly-used differential and single-ended methods of voltage
sensing. A resistor divider network is used to step down the line voltage within the acceptable ADS131E0x input
range and then directly connect to the inputs (INP and INN) through an antialiasing RC filter formed by resistor
R3 and capacitor C. The common-mode bias voltage (AVDD + AVSS) / 2, can be obtained from the ADS131E0x
by either configuring the internal op amp in a unity-gain configuration using the RF resistor and setting bit 3 of the
CONFIG3 register, or it can be generated externally by using a simple resistor divider network between the
positive and negative supplies.
In either of the below cases (Figure 44a for a differential input and Figure 44b for a single-ended input), the line
voltage is divided down by a factor of [R2 / (R1 + R2)]. Values of R1 and R2 must be carefully chosen so that the
voltage across the ADS131E0x inputs (INP and INN) does not exceed the FSDI range of ADS131E0x (see
Table 12) over the full operating dynamic range of the energy meter.
Device
Device
N
L
N
L
R1
R3
R1
R1
R3
INP
INN
INP
INN
R2
R2
EMI
Filter
EMI
Filter
C
R2
C
To PGA
To PGA
R3
OPAMP_REF
OPAMP_REF
(AVDD + AVSS)
2
(AVDD + AVSS)
2
OPAMPOUT
OPAMPOUT
-
-
RF
RF
OPAMPN
OPAMPP
OPAMPN
OPAMPP
(a) Voltage Sensing with Differential Input
(b) Voltage Sensing with Single-Ended Input
Figure 44. Simplified Voltage Sensing Connections
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FAULT DETECTION
The ADS131E0x have integrated comparators that can be used in conjunction with the external pull-up or pull-
down resistors (R) to detect various fault conditions. The basic principle is to compare the input voltage with the
one set by the fault comparator 3-bit digital-to-analog converter (DAC), as shown in Figure 45. The comparator
trigger threshold level is set by the COMP_TH[2:0] bits in the FAULT register. Assuming that the ADS131E0x is
powered from ±2.5-V supply and COMP_TH[2:0] = 000 (95% and 5%), the high-side trigger threshold is set at
+2.25 V [equal to AVSS + (AVDD + AVSS) × 95%] and the low-side threshold is set at –2.25 V [equal to AVSS +
(AVDD + AVSS) × 5%]. The threshold calculation formula applies to unipolar as well as bipolar supplies.
A fault condition, such as an input signal going out of a predetermined range, can be detected by setting the
appropriate threshold level using the COMP_TH[2:0] bits. An open-circuit fault at the INP or INN pin can be
detected by using the external pull-up and pull-down resistors, which rail the corresponding input when the input
circuit breaks, causing the fault comparators to trip. To pinpoint which of the inputs is out of range, the status of
the FAULT_STATP and FAULT_STATN registers can be read, which is available as part of the output data
stream; see the Data Output (DOUT) subsection of the SPI Interface section.
3-Bit
COMP_TH[2:0]
DAC(1)
Fault Detect
Control Register
AVDD
FAULT_STATP
R
+
INP
INN
Voltage
Or
Current
Sensing
To
ADC
EMI
Filter
PGA
-
R
FAULT_STATN
AVSS
Device
(1) The configurable 3-bit DAC is common to all channels.
Figure 45. Fault Detect Comparators
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SBAS561 –JUNE 2012
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QUICK-START GUIDE
PCB LAYOUT
Power Supplies and Grounding
The ADS131E0x have three supplies: AVDD, AVDD1, and DVDD. Both AVDD and AVDD1 should be as quiet as
possible. AVDD1 provides the supply to the charge pump block and has transients at fCLK. Therefore, it is
recommended that AVDD1 and AVSS1 be star-connected to AVDD and AVSS. It is important to eliminate noise
from AVDD and AVDD1 that is non-synchronous with device operation. Each ADS131E0x supply should be
bypassed with 10-μF and a 0.1-μF solid ceramic capacitors. It is recommended to place the digital circuits [such
as digital signal processors (DSPs), microcontrollers, and field-programmable gate arrays (FPGAs)] in the
system such that the return currents on those devices do not cross the ADS131E0x analog return path. The
ADS131E0x can be powered from unipolar or bipolar supplies.
The decoupling capacitors can be surface-mount, low-cost, low-profile multi-layer ceramic. In most cases the
VCAP1 capacitor can also be a multilayer ceramic. However, in systems where the board is subjected to high- or
low-frequency vibration, it is recommend that a non-ferroelectric capacitor (such as a tantalum or class 1
capacitor, C0G or NPO for example) be installed. EIA class 2 and class 3 dielectrics (such as X7R, X5R, and
X8R) are ferroelectric. The piezoelectric property of these capacitors can appear as electrical noise coming from
the capacitor. When using the internal reference, noise on the VCAP1 node results in performance degradation.
Connecting the Device to Unipolar (+3 V or +1.8 V) Supplies
Figure 46 illustrates the ADS131E0x connected to a unipolar supply. In this example, the analog supply (AVDD)
is referenced to analog ground (AVSS) and the digital supplies (DVDD) are referenced to digital ground (DGND).
+3 V
+1.8 V
0.1 µF
1 µF
1 µF
0.1 µF
AVDD AVDD1 DVDD
VREFP
VREFN
0.1 µF
10 µF
VCAP1
VCAP2
VCAP3
VCAP4
RESV1
Device
1 µF
1 µF
0.1 µF
1 µF
22 µF
AVSS1 AVSS DGND
NOTE: Place the supply, reference, and VCAP1 to VCAP4 capacitors as close to the package as possible.
Figure 46. Single-Supply Operation
46
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SBAS561 –JUNE 2012
Connecting the Device to Bipolar (±1.5 V or 1.8 V) Supplies
Figure 47 illustrates the ADS131E0x connected to a bipolar supply. In this example, the analog supplies connect
to the device analog supply (AVDD). This supply is referenced to the device analog return (AVSS), and the
digital supply (DVDD) is referenced to the device digital ground return (DGND).
+1.5 V
+1.8 V
1 µF
0.1 µF
0.1 µF
1 µF
AVDD AVDD1 DVDD
VREFP
0.1 µF
10 µF
VREFN
1.5 V
VCAP1
VCAP2
VCAP3
VCAP4
Device
RESV1
AVSS1 AVSS DGND
1 µF
0.1 µF
1 µF
22 µF
1 µF
1 µF
0.1 µF
1.5 V
NOTE: Place the capacitors for supply, reference, and VCAP1 to VCAP4 as close to the package as possible.
Figure 47. Bipolar Supply Operation
Shielding Analog Signal Paths
As with any precision circuit, careful PCB layout ensures the best performance. It is essential to make short,
direct interconnections and avoid stray wiring capacitance—particularly at the analog input pins and AVSS.
These analog input pins are high-impedance and extremely sensitive to extraneous noise. The AVSS pin should
be treated as a sensitive analog signal and connected directly to the supply ground with proper shielding.
Leakage currents between the PCB traces can exceed the ADS131E0x input bias current if shielding is not
implemented. Digital signals should be kept as far as possible from the analog input signals on the PCB.
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POWER-UP SEQUENCING
Before device power-up, all digital and analog inputs must be low. At power-up, these signals should remain low
until the power supplies have stabilized, as shown in Figure 48. Once the supply voltages have reached the final
value, the digital power-on reset (tPOR) executes to set the digital portion of the chip. The reset pin, or reset
command, should be issued after tPOR and when the VCAP1 voltage is greater than 800 mV. The VCAP1 pin
charge time is set by RC time constant; see Figure 27. If the VCAP1 capacitor is 22 µF, a reset can be issued
within 400 ms after power up. After releasing RESET, the configuration register must be programmed (see the
CONFIG1: Configuration Register 1 subsection of the Register Map section for details). The power-up sequence
timing is shown in Table 13.
tPOR
Power Supplies
tRST
RESET
Start Using the Device
18 tCLK
Figure 48. Power-Up Timing Diagram
Table 13. Power-Up Sequence Timing
SYMBOL
tPOR
DESCRIPTION
MIN
216
1
TYP
MAX
UNIT
tCLK
Wait after power-up until reset
Reset low width
tRST
tCLK
SETTING THE DEVICE FOR BASIC DATA CAPTURE
This section outlines the procedure to configure the device in a basic state and capture data. This procedure is
intended to put the device in a data sheet condition to check if the device is working properly in the user system.
It is recommended that this procedure be followed initially to get familiar with the device settings. When this
procedure is verified, the device can be configured as needed. For details on the timings for commands refer to
the appropriate sections in the data sheet. The flow chart of Figure 49 details the initial ADS131E0x configuration
and setup.
48
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SBAS561 –JUNE 2012
Analog or Digital
External
// Follow Power-Up Sequencing
Set CLKSEL Pin = 0
and Provide External Clock
f = 2.048 MHz
YES
Set CLKSEL Pin = 1,
Wait for Internal
Oscillator to Start Up
// If START is tied high, after this step
// DRDY toggles at fCLK / 64
NO
Set PWDN = 1
Set RESET = 1
Wait for 1 s
// Delay for Power-On Reset and Oscillator Start-Up
// Activate DUT
Issue Reset Pulse,
// CS can be Either Tied Permanently Low
// Or Selectively Pulled Low Before Sending
Wait for 18 tCLK
s
// Commands or Reading and Sending Data from or to the Device
// Device Wakes Up in RDATAC Mode, so Send
// SDATAC Command so Registers can be Written
SDATAC
Send SDATAC
Command
Set PDB_REFBUF = 1
and Wait for Internal
Reference
NO
External
Reference
// If Using Internal Reference, Send This Command
WREG CONFIG3 C0h
YES
// Set Device for DR = fMOD / 32
WREG CONFIG1 91h
WREG CONFIG2 E0h
Write Certain
Registers,
Including Input
// Set All Channels to Input Short
WREG CHnSET 01h
// Activate Conversion
Set START = 1
// After This Point DRDY Should Toggle at
// fCLK / 64
// Put the Device Back in RDATAC Mode
RDATAC
RDATAC
Capture Data
and Check Noise
// Look for DRDY and Issue 24 + n ì 24 SCLKs
// Activate a (1 mV / 2.4 V) Square-Wave Test Signal
// On All Channels
SDATAC
WREG CONFIG2 F0h
WREG CHnSET 05h
RDATAC
Set Test Signals
Capture Data
and Test Signal
// Look for DRDY and Issue 24 + n ì 24 SCLKs
Figure 49. Initial Flow at Power-Up
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PACKAGE OPTION ADDENDUM
www.ti.com
17-Jul-2012
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
ADS131E04IPAG
ADS131E04IPAGR
ADS131E06IPAG
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
PAG
PAG
PAG
PAG
PAG
PAG
64
64
64
64
64
64
0
160
1500
160
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
CU NIPDAU Level-3-260C-168 HR
CU NIPDAU Level-3-260C-168 HR
CU NIPDAU Level-3-260C-168 HR
CU NIPDAU Level-3-260C-168 HR
Green (RoHS
& no Sb/Br)
ADS131E06IPAGR
ADS131E08IPAG
1500
160
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
ADS131E08IPAGR
COMBOSMARTMETER
1500
Green (RoHS
& no Sb/Br)
TBD
Call TI
Call TI
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
17-Jul-2012
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
ADS131E04IPAGR
ADS131E06IPAGR
ADS131E08IPAGR
TQFP
TQFP
TQFP
PAG
PAG
PAG
64
64
64
1500
1500
1500
330.0
330.0
330.0
24.4
24.4
24.4
13.0
13.0
13.0
13.0
13.0
13.0
1.5
1.5
1.5
16.0
16.0
16.0
24.0
24.0
24.0
Q2
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
ADS131E04IPAGR
ADS131E06IPAGR
ADS131E08IPAGR
TQFP
TQFP
TQFP
PAG
PAG
PAG
64
64
64
1500
1500
1500
367.0
367.0
367.0
367.0
367.0
367.0
45.0
45.0
45.0
Pack Materials-Page 2
MECHANICAL DATA
MTQF006A – JANUARY 1995 – REVISED DECEMBER 1996
PAG (S-PQFP-G64)
PLASTIC QUAD FLATPACK
0,27
0,17
0,50
48
M
0,08
33
49
32
64
17
0,13 NOM
1
16
7,50 TYP
Gage Plane
10,20
SQ
9,80
0,25
12,20
SQ
0,05 MIN
11,80
0°–7°
1,05
0,95
0,75
0,45
Seating Plane
0,08
1,20 MAX
4040282/C 11/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
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