ADS131B23PHPR [TI]
24 位、64kSPS、三通道同步采样 Δ-Σ ADC | PHP | 48 | -40 to 125;
| 型号： | ADS131B23PHPR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 24 位、64kSPS、三通道同步采样 Δ-Σ ADC | PHP | 48 | -40 to 125 |
| 文件： | 总223页 (文件大小：3940K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ADS131B23
ZHCSR89 –DECEMBER 2022 –REVISED DECEMBER 2022
ADS131B23 适用于工业电池管理系统的电流、电压和温度测量模拟前端
1 特性
3 说明
• 两个用于电流分流测量的同步采样24 位ADC
（ADC1A、ADC1B）
ADS131B23 是一款适用于工业电池管理系统 (BMS)
的完整模拟前端(AFE)。该器件集成两个同步采样、高
精度、24 位 ADC 通道（ADC1A、ADC1B），可使用
外部分流电阻器来以高分辨率和高精度测量电池电流。
两个独立的数字比较器可与两个 ADC 并联来实现快速
过流检测。
– 可编程满标量程：
• ±39mV 至±312.5mV
• 支持多种分流电阻器值和电流测量范围
– 通过以下特性实现高精度电流分流测量：
• 失调电压误差：±1.5μV（最大值）
• 增益漂移：25ppm/°C（最大值）
– 可编程数据速率：500SPS 至64kSPS
– 每个ADC 具有可编程阈值的数字过流比较器，
可实现快速过流检测
另外还提供一个多路复用的 16 位 ADC (ADC2A)，可
使用外部高压电阻分压器来测量分流器温度和系统中的
其他电压，例如电池包电压。分流器温度通过热敏电阻
或模拟输出温度传感器等外部温度传感器进行测量。
ADC2A 配备一个通道序列发生器，后者会自动逐步调
试配置的多路复用器输入，以减少SPI 上的通信。
• 一个用于电压和温度测量的多路复用16 位ADC
(ADC2A)
该器件集成了多种监控和诊断功能，可缓解和检测随机
硬件故障，从而帮助开发功能安全的BMS。
– 8 路模拟输入
– 可编程满量程范围：
±312.5mV 至±1.25V
– 通道序列发生器
输入范围高达 16V 的内部线性稳压器支持使用非稳压
直流/直流转换器为器件供电。
• 监控和诊断功能，用于缓解和检测随机硬件故障
• 电源电压范围：2.9 V 至16 V
• 与SPI 兼容的接口
ADS131B23 采用 48 引脚 HTQFP 封装，额定工业级
温度范围为–40°C 至+105°C。
封装信息(1)
• 9 个具有PWM 功能的GPIO
器件型号
封装
封装尺寸（标称值）
2 应用
ADS131B23
7.00mm × 7.00mm
PHP（HTQFP、
48）
• 电池储能系统(ESS)：
– 电流分流测量
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
– 使用外部电阻分压器实现电压测量
– 使用热敏电阻或模拟输出温度传感器实现温度测
量
Isolated
Supply
DC/DC-Converter
IBAT
HV-
ADS131B23
UI-Sensor AFE
SPI
SPI
Digital
Isolator
Shunt
MCU
HV-
Isolation Barrier
Temperature
Sensor
BMS 电流检测模块(CSM) 系统方框图
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SBASAP8
ADS131B23
ZHCSR89 –DECEMBER 2022 –REVISED DECEMBER 2022
www.ti.com.cn
Table of Contents
8.1 Overview...................................................................22
8.2 Functional Block Diagram.........................................23
8.3 Feature Description...................................................24
8.4 Device Functional Modes..........................................51
8.5 Programming............................................................ 59
8.6 Register Map.............................................................72
9 Application and Implementation................................212
9.1 Application Information........................................... 212
9.2 Typical Application.................................................. 212
9.3 Power Supply Recommendations...........................216
9.4 Layout..................................................................... 219
10 Device and Documentation Support........................220
10.1 Documentation Support........................................ 220
10.2 接收文档更新通知................................................. 220
10.3 支持资源................................................................220
10.4 Trademarks...........................................................220
10.5 静电放电警告........................................................ 220
10.6 术语表................................................................... 220
11 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 5
6.1 Absolute Maximum Ratings........................................ 5
ESD Ratings..................................................................... 5
6.2 Recommended Operating Conditions.........................6
6.3 Thermal Information....................................................7
6.4 Electrical Characteristics.............................................7
6.5 时序要求....................................................................13
6.6 Switching Characteristics..........................................14
6.7 Timing Diagram.........................................................14
6.8 Typical Characteristics..............................................15
7 Parameter Measurement Information..........................20
7.1 Offset Drift Measurement..........................................20
7.2 Gain Drift Measurement............................................20
7.3 Noise Performance................................................... 21
8 Detailed Description......................................................22
Information.................................................................. 220
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
DATE
REVISION
NOTES
December 2022
*
Initial Release
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5 Pin Configuration and Functions
V1A
V0A
1
36
35
34
33
32
31
30
29
28
27
26
25
DCAP
2
DGND
IOVDD
GPIO0/MHD
CLK
GPIO0A
GPIO1A
CPA
3
4
5
CNA
6
CSn
Thermal
Pad
GPIO1B
GPIO0B
CNB
7
SDI
8
SDO
9
SCLK
CPB
10
11
12
DRDYn
GPIO1
GPIO2/FAULT
NC
NC
Not to scale
图5-1. PHP Package, 48-Pin HTQFP (Top View)
表5-1. Pin Functions
PIN
TYPE
DESCRIPTION(1)
NAME
AGND
NO.
39
21
42
19
38
Analog supply Analog ground
Analog supply Analog ground
AGND
AGNDA
AGNDB
APWR
Analog supply Section A analog ground. Connect to AGND.
Analog supply Section B analog ground. Connect to AGND.
Analog supply
Analog supply
Digital I/O
Analog power supply. Connect a 1-μF capacitor to AGND.
Analog supply. Connect a 1-μF capacitor to AGND.
Sets the logic levels for GPIO0A, GPIO1A, GPIO0B, and GPIO1B.
AVDD
40
CLK
CNA
CNB
CPA
32
6
Main clock input(4)
Analog input ADC1A negative analog input
Analog input ADC1B negative analog input
Analog input ADC1A positive analog input
9
5
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表5-1. Pin Functions (continued)
PIN
TYPE
DESCRIPTION(1)
NAME
NO.
10
31
36
35
37
27
3
CPB
CSn
Analog input ADC1B positive analog input
Digital input
Chip-select input. Active low. Internal pullup resistor to IOVDD.(4)
DCAP
Digital supply DVDD LDO output. Connect a 220-nF capacitor to DGND.
Digital supply Digital ground
DGND
DPWR
DRDYn
GPIO0A
GPIO0B
Digital supply
Digital output Data-ready output. Active low.(2) (4)
Digital power supply. Connect a 1-μF capacitor to DGND.
Digital I/O
Digital I/O
General-purpose digital input/output 0A.(2) (3)
General-purpose digital input/output 0B.(2) (3)
8
General-purpose digital input/output 0.(2) (4)
Missing host detect output.(2) (4)
GPIO0/MHD
33
Digital I/O
GPIO1
26
4
Digital I/O
Digital I/O
Digital I/O
General-purpose digital input/output 1.(2) (4)
General-purpose digital input/output 1A.(2) (3)
General-purpose digital input/output 1B.(2) (3)
GPIO1A
GPIO1B
7
General-purpose digital input/output 2.(2) (4)
Fault output.(2) (4)
GPIO2/FAULT
GPIO3/OCCA
GPIO4/OCCB
IOVDD
25
24
22
34
Digital I/O
Digital I/O
General-purpose digital input/output 3.(2) (4)
Overcurrent comparator A output.(2) (4)
General-purpose digital input/output 4.(2) (4)
Overcurrent comparator B output.(2) (4)
Digital I/O
Digital I/O supply.
Digital supply
Sets the logic levels for the digital I/Os, except for GPIO0A, GPIO1A, GPIO0B, and GPIO1B.
No connect. Leave these pins floating or connected to AGNDB.
REFA voltage reference output. Connect a 1-μF capacitor to AGNDA.
REFB voltage reference output. Connect a 1-μF capacitor to AGNDB.
Reset input. Active low. Internal pulldown resistor to DGND.
Serial data clock input(4)
NC
11 to 18
41
20
23
28
30
29
2
NC
RCAPA
RCAPB
RESETn
SCLK
SDI
Analog output
Analog output
Digital input
Digital input
Digital input
Serial data input(4)
SDO
Digital output Serial data output(2) (4)
Analog input ADC2A analog input 0A
Analog input ADC2A analog input 1A
Analog input ADC2A analog input 2A
Analog input ADC2A analog input 3A
Analog input ADC2A analog input 4A
Analog input ADC2A analog input 5A
Analog input ADC2A analog input 6A
Analog input ADC2A analog input 7A
V0A
V1A
1
V2A
48
47
46
45
44
43
—
V3A
V4A
V5A
V6A
V7A
Thermal Pad
Thermal power pad. Connect to AGND.
—
(1) See the Unused Inputs and Outputs section for details on how to connect unused pins.
(2) Push-pull output.
(3) Logic levels referenced to AVDD.
(4) Logic levels referenced to IOVDD.
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6 Specifications
6.1 Absolute Maximum Ratings
see (1)
MIN
–0.3
MAX
UNIT
APWR to AGND
20
DPWR to DGND
20
–0.3
AGND, AGNDy to DGND
0.3
–0.3
Power-supply voltage
AVDD to AGND
IOVDD to DGND
DCAP to DGND
RCAPy to AGND
CPy, CNy, Vxy
3.9
V
–0.3
7
2.2
–0.3
–0.3
2.2
–0.3
Analog input voltage
Digital input voltage
AVDD + 0.3
V
V
AGND –1.6
CSn, SCLK, SDI, SDO, RESETn, DRDYn, CLK, GPIO0/MHD,
GPIO1, GPIO2/FAULT, GPIO3/OCCA, GPIO4/OCCB
IOVDD + 0.3
DGND –0.3
GPIO0A, GPIO1A
AVDD + 0.3
AVDD + 0.3
10
AGNDA –0.3
AGNDB –0.3
–10
GPIO0B, GPIO1B
Input current
Temperature
Continuous, all pins except power-supply pins
Junction, TJ
mA
°C
150
Storage, Tstg
150
–60
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If
briefly operating outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not
sustain damage, but it may not be fully functional –this may affect device reliability, functionality, performance, and shorten the device
lifetime.
ESD Ratings
VALUE
2000
500
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per ANSI/ESDA/JEDEC JS-002(2)
V(ESD)
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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6.2 Recommended Operating Conditions
over operating ambient temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
POWER SUPPLY
APWR to AGND
4
2.9
16
3.6
16
APWR = AVDD to AGND
(APWR shorted to AVDD, AVDD LDO
bypassed)
3.3
DPWR to DGND
4
Power supply
V
DPWR = IOVDD to DGND
(DPWR shorted to IOVDD, IOVDD LDO
bypassed)
2.9
3.3
0
5.5
0.2
AGND, AGNDy to DGND
–0.2
ANALOG INPUTS ADC1A, ADC1B(1)
VCPy, VCNy
VIN1y
Absolute input voltage
Differential input voltage
Gain = 4, 8, 16, 32
V
V
AGND –0.3125
–VREFy / Gain
AVDD –2.4
VREFy / Gain
VIN1y = VCPy –VCNy
ANALOG INPUTS ADC2A(1)
Gain = 1, 2
Gain = 4
AGND –0.1
AVDD –1.2
AVDD –2.4
VVxy
Absolute input voltage
V
V
AGND –0.3125
VIN2y = VVxy –VAGNDy or
VIN2y = VVxy –V7y
VIN2y
Differential input voltage
VREFy / Gain
–VREFy / Gain
EXTERNAL CLOCK SOURCE(2)
fCLK External clock frequency
Duty cycle
DIGITAL INPUTS
7.8
8.192
50%
8.4
MHz
40%
60%
CSn, SCLK, SDI, SDO, RESETn, DRDYn,
CLK, GPIO0/MHD, GPIO1, GPIO2/FAULT,
GPIO3/OCCA, GPIO4/OCCB
DGND
IOVDD
Input voltage
V
GPIO0A, GPIO1A
GPIO0B, GPIO1B
AGNDA
AGNDB
AVDD
AVDD
EXTERNAL CAPACITORS
APWR, DPWR
AVDD, IOVDD
RCAPA, RCAPB
DCAP
1
1
0.5
0.5
2
µF
nF
Capacitor value(3)
1
1.4
220
TEMPERATURE RANGE
Specified ambient temperature
Operating ambient temperature
105
125
–40
–45
TA
°C
(1) The subscript 'y' refers to section 'A' or section 'B'.
The subscript 'x' refers to the analog input channel 'x' on ADC2y.
(2) An external clock is not required when the internal oscillator is used.
(3) Capacitor values that need to be met over temperature and lifetime.
See the Power-Supply Decoupling section for additional information.
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6.3 Thermal Information
TQFP (PHP)
UNIT
48 PINS
THERMAL METRIC(1)
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
23.7
15.3
7.8
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-board thermal resistance
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.2
ΨJT
7.7
ΨJB
RθJC(bot)
1.3
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.4 Electrical Characteristics
minimum and maximum specifications apply from TA = –40°C to +105°C; typical specifications are at TA = 25°C; all
specifications are at APWR = 5 V, DPWR = 5 V, IOVDD = 3.3 V, external clock, fCLK = 8.192 MHz, global-chop mode
disabled, ADC1y data rate = 1 kSPS (unless otherwise noted)
PARAMETER
CURRENT MEASUREMENT ADCS (ADC1A, ADC1B)
Resolution
TEST CONDITIONS
MIN
TYP
MAX
UNIT
24
Bits
V/V
Gain settings
4, 8, 16, 32
fDATA
Output data rate
fCLK = 8.192 MHz
500
64k
5
SPS
All data rates, all gains, global-chop enabled or
disabled, VCPy = VCNy = 0 V
Absolute input current
±0.5
±1
nA
nA
All data rates, all gains, global-chop enabled or
disabled, VCPy = VCNy = 0 V
Differential input current
–5
All data rates, all gains, global-chop enabled or
disabled
Differential input impedance
1.8
MΩ
Gain = 4, global-chop disabled
Gain = 8 to 32, global-chop disabled
All gains, global-chop enabled
All gains, global-chop disabled
All gains, global-chop enabled
±1
±15
±0.5
20
Offset error (input referred)
Offset drift
µV
1.5
100
7
–1.5
nV/°C
1
TA = 25°C, all gains, single-ended operation with
CNy held at AGNDy, including initial accuracy of
REFy
Gain error
Gain drift
±0.05%
7
0.15%
–0.15%
–0.07%
All gains, single-ended operation with CNy held
at AGNDy, incuding drift of REFy
25 ppm/°C
0.07%
Gain match
Between gain settings
±0.04%
0.65
110
Noise (input referred)
Gain = 8, fDATA = 1 kSPS
µVRMS
At DC, global-chop disabled
CMRR
PSRR
Common-mode rejection ratio
Power-supply rejection ratio
dB
At DC, global-chop enabled
113
APWR at DC, global-chop enabled or disabled
DPWR at DC, global-chop enabled or disabled
AVDD at DC, global-chop enabled or disabled
IOVDD at DC, global-chop enabled or disabled
133
133
dB
115
131
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6.4 Electrical Characteristics (continued)
minimum and maximum specifications apply from TA = –40°C to +105°C; typical specifications are at TA = 25°C; all
specifications are at APWR = 5 V, DPWR = 5 V, IOVDD = 3.3 V, external clock, fCLK = 8.192 MHz, global-chop mode
disabled, ADC1y data rate = 1 kSPS (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VOLTAGE AND TEMPERATURE MEASUREMENT ADC (ADC2A)
Resolution
16
Bits
V/V
nA
Gain settings
1, 2, 4
±0.2
±0.4
15
Absolute input current
Differential input current
OSR2y = 64, all gains, VVxy = 0 V
OSR2y = 64, all gains, VVxy = 0 V
OSR2y = 64, all gains
OSR2y = 128, all gains
OSR2y = 256, all gains
OSR2y = 512, all gains
Gain = 1
nA
30
Differential input impedance
Offset error (input referred)
MΩ
60
120
±85
±5
350
25
–350
–25
µV
Gain = 2 and 4
Gain = 1
60
300
150
Offset drift
Gain error
nV/°C
Gain = 2 and 4
30
TA = 25°C, all gains,
including initial accuracy of REFy
±0.1%
0.3%
–0.3%
Gain drift
All gains, including drift of REFy
Between gain settings
8
±0.06%
95
30 ppm/°C
0.15%
Gain match
–0.15%
CMRR
PSRR
Common-mode rejection ratio At DC
APWR at DC
dB
103
DPWR at DC
AVDD at DC
IOVDD at DC
103
Power-supply rejection ratio
dB
91
96
PRECISION VOLTAGE REFERENCES (REFA, REFB)
VREFA
VREFB
,
Reference voltage
1.25
V
Accuracy
TA = 25°C
±0.05%
4
0.15%
14 ppm/°C
–0.15%
–10
Temperature drift
Source only,
available for external loads on RCAPy pin
Output current
250
µA
Short-circuit current limit
Start-up time
Sink or source
10
mA
ms
8
1-μF capacitor on RCAPy, 0.01% settling
MAIN OSCILLATOR (OSCM)
fOSCM
Frequency
Accuracy
8.192
MHz
MHz
µV
2.5%
2.5%
–2.5%
–2.5%
DIAGNOSTIC OSCILLATOR (OSCD)
fOSCD
Frequency
Accuracy
8.192
OVERCURRENT COMPARATORS (OCCA, OCCB)
Offset error (input referred)
All gains
20
500
–500
Gain error
All gains, including error of REFy
±0.2%
0.5%
–0.5%
TEMPERATURE SENSOR (TSA)
TSOffset
TSTC
Output voltage
TA = 25°C
118.4
410
mV
Temperature coefficient
µV/°C
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6.4 Electrical Characteristics (continued)
minimum and maximum specifications apply from TA = –40°C to +105°C; typical specifications are at TA = 25°C; all
specifications are at APWR = 5 V, DPWR = 5 V, IOVDD = 3.3 V, external clock, fCLK = 8.192 MHz, global-chop mode
disabled, ADC1y data rate = 1 kSPS (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
COMMON-MODE OUTPUT BUFFERS (VCMA)
VCMA
Common-mode output voltage
Output current
0.75
–1
–5
0.78
0.81
1
V
Sink or source
Sink or source
mA
mA
pF
Short-circuit current limit
Capacitive load
5
100
TEST DACS (TDACA, TDACB)
1 × VREFy / 40
2 × VREFy / 40
4 × VREFy / 40
9 × VREFy / 40
18 × VREFy / 40
36 × VREFy / 40
–4 × VREFy / 40
–9 × VREFy / 40
Output voltage settings
V
Accuracy
Drift
±0.3%
6
Positive output voltages
Negative output voltages
35
70
ppm/°C
12
OPEN-WIRE DETECTION CURRENT SOURCES AND SINKS (OWD1A, OWD1B, OWD2A)
Current source settings
Current sink settings
4, 40, 240
4, 40, 240
±8%
µA
µA
Current source accuracy
Current sink accuracy
±8%
DIGITAL INPUTS/OUTPUTS (GPIO0A, GPIO1A, GPIO0B, GPIO1B)
VIL
Logic input level, low
Logic input level, high
Logic output level, low
Logic output level, high
AGNDy
0.3 AVDD
AVDD
V
V
V
V
VIH
VOL
VOH
0.7 AVDD
0.2 AVDD
IOL = –100 µA
IOH = 100 µA
0.8 AVDD
DIGITAL INPUTS/OUTPUTS (CSn, SCLK, SDI, SDO, RESETn, DRDYn, CLK, GPIO0/MHD, GPIO1, GPIO2/FAULT, GPIO3/OCCA, GPIO4/OCCB)
VIL
Logic input level, low
Logic input level, high
Logic output level, low
Logic output level, high
Input current
DGND
0.3 IOVDD
IOVDD
V
V
VIH
VOL
VOH
IIN
0.7 IOVDD
0.2 IOVDD
V
IOL = –1 mA
IOH = 1 mA
0.8 IOVDD
V
DGND < VDigital Input < IOVDD
1
µA
–1
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6.4 Electrical Characteristics (continued)
minimum and maximum specifications apply from TA = –40°C to +105°C; typical specifications are at TA = 25°C; all
specifications are at APWR = 5 V, DPWR = 5 V, IOVDD = 3.3 V, external clock, fCLK = 8.192 MHz, global-chop mode
disabled, ADC1y data rate = 1 kSPS (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER SUPPLY MONITORS
AVDD_UV_TH
AVDD_OV_TH
AVDD undervoltage threshold
AVDD overvoltage threshold
2.9
3.8
2.95
3.9
3.0
4.0
3.0
4.4
4.0
5.9
1.65
2.0
V
V
IOVDD_UV_TH = 1b
2.9
2.95
4.3
IOVDD_UV_TH IOVDD undervoltage threshold
IOVDD_OV_TH IOVDD overvoltage threshold
V
V
IOVDD_UV_TH = 0b
IOVDD_OV_TH = 1b
IOVDD_OV_TH = 0b
4.2
3.8
3.9
5.6
5.75
1.6
DVDD_UV_TH DVDD undervoltage threshold
DVDD_OV_TH DVDD overvoltage threshold
AVDD_OSC_MA AVDD oscillation detection
1.55
1.90
V
V
1.95
Amplitude required to generate fault
500
2
mVpp
kHz
G
magnitude
AVDD_OSC_FR AVDD oscillation detection
EQ input frequency
Oscillation frequency range to generate fault
Amplitude required to generate fault
500
500
500
IOVDD_OSC_M IOVDD oscillation detection
AG magnitude
500
2
mVpp
kHz
IOVDD_OSC_F IOVDD oscillation detection
REQ input frequency
Oscillation frequency range to generate fault
Amplitude required to generate fault
DVDD_OSC_M DVDD oscillation detection
AG magnitude
500
2
mVpp
kHz
DVDD_OSC_FR DVDD oscillation detection
EQ
Oscillation frequency range to generate fault
input frequency
–60
100
120
140
AVDD overtemperature
warning thresholds
AVDD_OTW_TH
°C
°C
°C
°C
AVDD overtemperature
warning threshold accuracy
±2
–60
100
120
140
IOVDD_OTW_T IOVDD overtemperature
H
warning thresholds
IOVDD overtemperature
warning threshold accuracy
±2
APWR
DPWR
AVDD
IOVDD
DVDD
103
103
4
ADC2y power-supply
readback attenuation factor
4
2
ADC2y power-supply
readback accuracy
±1%
2.7
OSR2y = 128, MUX2y_DELAY ≥256 × tMCLK
AVDD_POR_TH AVDD POR release threshold
2.6
2.6
1.4
2.85
2.85
1.6
V
V
V
IOVDD_POR_T
IOVDD POR release threshold
H
2.7
DVDD_POR_TH DVDD POR release threshold
1.5
ADC MONITORS
ADC1y overrange detection
threshold
±115
±115
% of FS
% of FS
ADC2y overrange detection
threshold
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6.4 Electrical Characteristics (continued)
minimum and maximum specifications apply from TA = –40°C to +105°C; typical specifications are at TA = 25°C; all
specifications are at APWR = 5 V, DPWR = 5 V, IOVDD = 3.3 V, external clock, fCLK = 8.192 MHz, global-chop mode
disabled, ADC1y data rate = 1 kSPS (unless otherwise noted)
PARAMETER
CLOCK MONITORS
Main clock (MCLK) watchdog Watchdog indicates a fault when MCLK
TEST CONDITIONS
MIN
TYP
MAX
UNIT
fMCLK_WD_TH
300
300
kHz
kHz
frequency threshold
frequency drops below frequency threshold
Diagnostic oscillator (OSCD)
watchdog frequency threshold frequency drops below frequency threshold
Watchdog indicates a fault when OSCD
fOSCD_WD_TH
MCLK_FAULT_ Main clock fault detection
TH frequency threshold
Difference in clock frequencies between MCLK
and OSCD to generate a fault
10%
FAULT MONITOR RESPONSE TIMES
AVDD overvoltage detection
Delay time from AVDD exceeding AVDD
overvoltage threshold to FAULT pin active
tp(AVDD_OV)
tp(IOVDD_OV)
tp(DVDD_OV)
tp(AVDD_UV)
tp(IOVDD_UV)
tp(DVDD_UV)
tp(AVDD_OSC)
tp(IOVDD_OSC)
tp(DVDD_OSC)
tp(AVDD_CL)
tp(IOVDD_CL)
4
4
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
response time
IOVDD overvoltage detection Delay time from IOVDD exceeding IOVDD
response time
overvoltage threshold to FAULT pin active
DVDD overvoltage detection
response time
Delay time from DVDD exceeding DVDD
overvoltage threshold to FAULT pin active
4
AVDD undervoltage detection Delay time from AVDD dropping below AVDD
response time undervoltage threshold to FAULT pin active
4
IOVDD undervoltage detection Delay time from IOVDD dropping below IOVDD
response time undervoltage threshold to FAULT pin active
4
DVDD undervoltage detection Delay time from DVDD dropping below DVDD
response time
4
undervoltage threshold to FAULT pin active
AVDD oscillation detection
response time
Delay time from AVDD oscillations exceeding
AVDD oscillation threshold to FAULT pin active
30
30
30
40
40
IOVDD oscillation detection
response time
Delay time from IOVDD oscillations exceeding
IOVDD oscillation threshold to FAULT pin active
DVDD oscillation detection
response time
Delay time from DVDD oscillations exceeding
DVDD oscillation threshold to FAULT pin active
AVDD current limit detection
response time
Delay time from AVDD exceeding AVDD current
limit threshold to FAULT pin active
IOVDD current limit detection Delay time from IOVDD exceeding IOVDD
response time
current limit threshold to FAULT pin active
Delay time from AVDD exceeding AVDD
overtemperature warning threshold to FAULT pin
active
AVDD overtemperature
warning response time
tp(AVDD_OTW)
300
300
µs
µs
Delay time from IOVDD exceeding IOVDD
overtemperature warning threshold to FAULT pin
active
IOVDD overtemperature
warning response time
tp(IOVDD_OTW)
DGND open detection
response time
Delay time from DGND pin disconnected to
FAULT pin active
tp(DGND_OPEN)
tp(AGNDA_OPEN)
tp(AGNDB_OPEN)
tp(MEM_MAP_CRC)
tp(REG_MAP_CRC)
tp(MCLK_WD)
4
4
µs
µs
AGNDA open detection
response time
Delay time from AGNDA pin disconnected to
FAULT pin active
AGNDB open detection
response time
Delay time from AGNDB pin disconnected to
FAULT pin active
4
µs
Memory map CRC fault
detection response time
Delay time from bit flip occurence in memory
map to FAULT pin active
69
138
2048
2
tOSCD
tOSCD
µs
Register map CRC fault
detection response time
Delay time from bit flip occurence in register map
to FAULT pin active
1024
Main clock watchdog
response time
Delay time from main clock watchdog timeout to
FAULT pin active
Diagnostic oscillator watchdog Delay time from diagnostic oscillator watchdog
tp(OSCD_WD)
2
µs
response time
timeout to FAULT pin active
Main clock fault detection
response time
Delay time from main clock fault detection to
FAULT pin active
tp(MCLK_FAULT)
4096
tMCLK
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6.4 Electrical Characteristics (continued)
minimum and maximum specifications apply from TA = –40°C to +105°C; typical specifications are at TA = 25°C; all
specifications are at APWR = 5 V, DPWR = 5 V, IOVDD = 3.3 V, external clock, fCLK = 8.192 MHz, global-chop mode
disabled, ADC1y data rate = 1 kSPS (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
AVDD LDO
AVDD
Output voltage
3.1
3.3
3.5
20
60
V
mA
Load current
Available to external circuitry on the AVDD pin
Short-circuit current limit
Load regulation
mA
1
mV/mA
IOVDD LDO
IOVDD
Output voltage
3.1
3.3
3.5
20
60
V
mA
Load current
Available to external circuitry on the IOVDD pin
Short-circuit current limit
Load regulation
mA
1
mV/mA
SUPPLY CURRENTS
Power-down mode
0.01
0.46
0.9
Standby mode
Active mode, all ADCs disabled
APWR supply current
Active mode, all ADCs enabled and converting
(all features enabled, no external load on AVDD
LDO)
4.8
5.8
IAPWR
mA
ADC1y enabled and converting,
all gains, all data rates
1.7
0.5
APWR supply current per
individual ADC
ADC2A enabled and converting,
all gains, all data rates
Power-down mode
0.01
0.4
Standby mode
DPWR supply current(1)
Active mode, all ADCs disabled
0.8
Active mode, all ADCs enabled and converting
(all features enabled, no external load on IOVDD
LDO)
IDPWR
mA
1.0
1.5
ADC1y enabled and converting, all data rates
ADC2A enabled and converting, all data rates
0.06
0.06
DPWR supply current per
individual ADC(1)
APWR shorted to AVDD, AVDD LDO bypassed,
active mode, all ADCs enabled and converting
(all features enabled)
IAVDD
IIOVDD
PD
AVDD supply current
IOVDD supply current(1)
Power dissipation
4.8
1.0
29
mA
mA
mW
DPWR shorted to IOVDD, IOVDD LDO
bypassed,
active mode, all ADCs enabled and converting
(all features enabled)
Active mode, all ADCs enabled and converting
(all features enabled, no external load on AVDD
LDO)
(1) Currents measured with SPI idle.
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6.5 时序要求
在工作环境温度范围内，SDO 负载：20pF || 100kΩ（除非另有说明）
最小值
最大值
单位
3.0V ≤IOVDD ≤3.6V
tw(CLH)
tw(CLL)
tc(SC)
49
49
64
32
32
16
10
20
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
脉冲持续时间，CLK 高电平
脉冲持续时间，CLK 低电平
SCLK 周期
tw(SCL)
tw(SCH)
td(CSSC)
td(SCCS)
tw(CSH)
tsu(DI)
脉冲持续时间，SCLK 为低电平
脉冲持续时间，SCLK 为高电平
延时时间，CSn 下降沿后的第一个SCLK 上升沿
延时时间，最后一个SCLK 下降沿后的CSn 上升沿
脉冲持续时间，CSn 高电平
建立时间，SCLK 下降沿前的SDI 有效
保持时间，SCLK 下降沿后的SDI 有效
脉冲持续时间，RESETn 低电平以生成器件复位
th(DI)
8
tw(RSL)
500
4.5V ≤IOVDD ≤5.5V
tw(CLL)
tw(CLH)
tc(SC)
49
49
50
25
25
16
10
15
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
脉冲持续时间，CLK 低电平
脉冲持续时间，CLK 高电平
SCLK 周期
tw(SCL)
tw(SCH)
td(CSSC)
td(SCCS)
tw(CSH)
tsu(DI)
脉冲持续时间，SCLK 为低电平
脉冲持续时间，SCLK 为高电平
延时时间，CSn 下降沿后的第一个SCLK 上升沿
延时时间，最后一个SCLK 下降沿后的CSn 上升沿
脉冲持续时间，CSn 高电平
建立时间，SCLK 下降沿前的SDI 有效
保持时间，SCLK 下降沿后的SDI 有效
脉冲持续时间，RESETn 低电平以生成器件复位
th(DI)
8
tw(RSL)
500
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6.6 Switching Characteristics
over operating ambient temperature range, SDO load: 20 pF || 100 kΩ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
3.0 V ≤IOVDD ≤3.6 V
Propagation delay time, CSn falling edge to
SDO driven
tp(CSDO)
tp(CSDOZ)
tp(SCDO)
50
75
32
ns
ns
ns
Propagation delay time, CSn rising edge to
SDO high impedance
Progapation delay time, SCLK rising edge to
valid new SDO
tw(DRH)
Pulse duration, DRDYn high
SPI timeout
4
tMCLK
tOSCD
tTIMEOUT
16385
Measured from supplies crossing POR
threshold to DRDYn rising edge
tPOR
Power-on-reset time
250
44
µs
µs
Measured from RESETn rising edge to
DRDYn rising edge
tREGACQ
Register default value acquisition time
114
4.5 V ≤IOVDD ≤5.5 V
Propagation delay time, CSn falling edge to
SDO driven
tp(CSDO)
tp(SCDO)
tp(CSDOZ)
50
20
75
ns
ns
ns
Progapation delay time, SCLK rising edge to
valid new SDO
Propagation delay time, CSn rising edge to
SDO high impedance
tw(DRH)
Pulse duration, DRDYn high
SPI timeout
4
tMCLK
tOSCD
tTIMEOUT
16385
Measured from supplies crossing POR
threshold to DRDYn rising edge
tPOR
Power-on-reset time
250
44
µs
µs
Measured from RESETn rising edge to
DRDYn rising edge
tREGACQ
Register default value acquisition time
114
6.7 Timing Diagram
tw(CLH)
tw(CLL)
CLK
DRDYn
tw(DRH)
CSn
SCLK
SDI
tw(SCL)
td(SCCS)
td(CSSC)
tc(SC)
tw(CSH)
tw(SCH)
tsu(DI)
th(DI)
tp(CSDO)
tp(SCDO)
tw(CSDOZ)
MSB
MSB - 1
LSB + 1
LSB
SDO
图6-1. SPI Timing Requirements and Switching Characteristics
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6.8 Typical Characteristics
at TA = 25°C, APWR = 5 V, DPWR = 5 V, and external clock with fCLK = 8.192 MHz (unless otherwise noted)
25
20
ADC1A
ADC1B
15
Gain = 4
Gain = 8
Gain = 16
Gain = 32
20
10
5
15
0
10
-5
-10
5
-15
-20
0
-40
-20
0
20
40
60
80
100 120 140
-25
-20
-15
-10
-5
0
5
10
15
20
25
Offset Error (V)
Temperature (°C)
32 devices, gain = 8, global-chop disabled, input referred
Global-chop disabled, input referred
图6-2. ADC1y Offset Error Histogram
图6-3. ADC1y Offset Error vs Temperature
25
ADC1A
ADC1B
20
15
10
5
0
-0.5
-0.4
-0.3
-0.2
-0.1
0.0
0.1
0.2
0.3
0.4
0.5
Offset Error (V)
32 devices, gain = 8, global-chop enabled, input referred
Global-chop enabled, input referred
图6-4. ADC1y Offset Error Histogram
图6-5. ADC1y Offset Error vs Temperature
25
20
15
10
5
0.4
ADC1A
ADC1B
Gain = 4
Gain = 8
Gain = 16
Gain = 32
0.3
0.2
0.1
0.0
-0.1
-0.2
-0.3
-0.4
0
-40
-20
0
20
40
60
80
100 120 140
-0.01 0.00 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09
Gain Error (%)
Temperature (°C)
32 devices, gain = 4, including error of REFy
Including error of REFy
图6-7. ADC1y Gain Error vs Temperature
图6-6. ADC1y Gain Error Histogram
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6.8 Typical Characteristics (continued)
at TA = 25°C, APWR = 5 V, DPWR = 5 V, and external clock with fCLK = 8.192 MHz (unless otherwise noted)
25
100
75
20
50
25
15
0
10
-25
-50
5
Gain = 1
Gain = 2
Gain = 4
-75
-100
0
-40
-20
0
20
40
60
80
100 120 140
-250 -200 -150 -100
-50
0
50
100
150
200
250
Offset Error (V)
Temperature (°C)
32 devices, gain = 1, input referred
Input referred
图6-8. ADC2A Offset Error Histogram
图6-9. ADC2A Offset Error vs Temperature
25
20
15
10
5
0.4
0.3
Gain = 1
Gain = 2
Gain = 4
0.2
0.1
0.0
-0.1
-0.2
-0.3
-0.4
0
-40
-20
0
20
40
60
80
100 120 140
0.07 0.08 0.09 0.10 0.11 0.12 0.13 0.14 0.16 0.17 0.18
Gain Error (%)
Temperature (°C)
32 devices, gain = 1, including error of REFy
Including error of REFy
图6-11. ADC2A Gain Error vs Temperature
图6-10. ADC2A Gain Error Histogram
25
20
15
10
5
1.2510
1.2505
1.2500
1.2495
1.2490
1.2485
1.2480
REFA
REFB
REFA
REFB
0
-40
-20
0
20
40
60
80
100 120 140
1.2490 1.2491 1.2492 1.2493 1.2494 1.2495 1.2496 1.2497 1.2498 1.2499 1.2500
Output Voltage (V)
Temperature (°C)
图6-12. REFy Output Voltage Histogram
图6-13. REFy Output Voltage vs Temperature
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6.8 Typical Characteristics (continued)
at TA = 25°C, APWR = 5 V, DPWR = 5 V, and external clock with fCLK = 8.192 MHz (unless otherwise noted)
25
8.5
OSCM
OSCD
OSCM
OSCD
8.4
20
8.3
15
8.2
10
8.1
5
8.0
7.9
0
-40
-20
0
20
40
60
80
100 120 140
8.19
8.2
8.21
8.22
8.23
8.24
8.25
8.26
8.27
8.28
Temperature (°C)
Frequency [MHz]
图6-14. OSCM and OSCD Frequency Histogram
图6-15. OSCM and OSCD Frequency vs Temperature
25
20
15
10
5
20
OCCA
OCCB
Gain = 4
Gain = 8
Gain = 16
Gain = 32
15
10
5
0
-5
-10
-15
-20
0
-40
-20
0
20
40
60
80
100 120 140
-10
-8
-6
-4
-2
0
2
4
6
8
10
Offset Error (V)
Temperature (°C)
27 devices, ADC1y gain = 4, input referred
Input referred
图6-16. OCCy Offset Error Histogram
图6-17. OCCy Offset Error vs Temperature
25
20
15
10
5
0.4
0.3
OCCA
OCCB
Gain = 4
Gain = 8
Gain = 16
Gain = 32
0.2
0.1
0.0
-0.1
-0.2
-0.3
-0.4
0
-40
-20
0
20
40
60
80
100 120 140
-0.2 -0.19 -0.18 -0.17 -0.16 -0.15 -0.14 -0.13 -0.12 -0.11 -0.10
Gain Error (%)
Temperature (°C)
32 devices, ADC1y gain = 4, including error of REFy
Including error of REFy
图6-19. OCCy Gain Error vs Temperature
图6-18. OCCy Gain Error Histogram
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6.8 Typical Characteristics (continued)
at TA = 25°C, APWR = 5 V, DPWR = 5 V, and external clock with fCLK = 8.192 MHz (unless otherwise noted)
25
20
15
10
5
0
118.0 118.1 118.2 118.3 118.4 118.5 118.6 118.7 118.8 118.9 119
Output Voltage (V)
28 devices
图6-20. Temperature Sensor Output Voltage Histogram
图6-21. Temperature Sensor Measurement Error vs Ambient
Temperature
25
282.0
281.5
281.0
280.5
280.0
20
15
10
5
0
-40
-20
0
20
40
60
80
100 120 140
276
277
278
279
280
281
282
283
284
285
286
Temperature (°C)
Output Voltage (mV)
TDACy Output Voltage = 9 × VREFy / 40
图6-22. Test DACy Output Voltage Histogram
TDACy Output Voltage = 9 × VREFy / 40
图6-23. Test DACy Output Voltage vs Temperature
25
20
15
10
5
-280.0
-280.5
-281.0
-281.5
-282.0
0
-40
-20
0
20
40
60
80
100 120 140
-286
-285
-284
-283
-282
-281
-280
-279
-278
Temperature (°C)
Output Voltage (mV)
TDACy Output Voltage = –9 × VREFy / 40
图6-24. Test DACy Output Voltage Histogram
TDACy Output Voltage = –9 × VREFy / 40
图6-25. Test DACy Output Voltage vs Temperature
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6.8 Typical Characteristics (continued)
at TA = 25°C, APWR = 5 V, DPWR = 5 V, and external clock with fCLK = 8.192 MHz (unless otherwise noted)
2
1
0
-1
-2
-3
-4
-5
-6
OSR2y = 64
OSR2y = 128
OSR2y = 256
OSR2y = 512
16
64
128
256
512
1024
2048
4096
Multiplexer Delay Time (tMCLK
)
APWR or DPWR
AVDD or IOVDD
图6-26. ADC2A Supply Voltage Readback Measurement
图6-27. ADC2A Supply Voltage Readback Measurement
Accuracy
Accuracy
25
0.80
0.79
0.78
0.77
0.76
0.75
AVDD
IOVDD
20
15
10
5
0
-40
-20
0
20
40
60
80
100 120 140
3.32 3.33 3.34 3.35 3.36 3.37 3.38 3.39
Output Voltage (V)
3.4
3.41 3.42
Temperature (°C)
32 devices
图6-28. VCMA Output Voltage vs Temperature
图6-29. AVDD and IOVDD LDO Output Voltage Histogram
3.6
3.5
3.4
3.3
3.2
3.1
7
AVDD
IOVDD
IAPWR
IDPWR
6
5
4
3
2
1
0
-40
-20
0
20
40
60
80
100 120 140
-40
-20
0
20
40
60
80
100 120 140
Temperature (°C)
Temperature (°C)
Active mode, all ADCs enabled and converting
图6-30. AVDD and IOVDD LDO Output Voltage vs Temperature
图6-31. Supply Current vs Temperature
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7 Parameter Measurement Information
7.1 Offset Drift Measurement
Offset drift is defined as the change in offset voltage over the specified temperature range. Offset drift is
calculated using the box method in which a box is formed over the maximum and minimum offset voltages and
over the specified temperature range. The box method specifies limits for the temperature error but does not
specify the exact shape and slope of the device under test. For that reason offset drift is specified as a positive
number only, even though the drift can possibly be negative. 方程式 1 shows the offset drift calculation using the
box method:
Offset Drift (nV/°C) = 109 × (VOFSMAX –VOFSMIN) / (TMAX –TMIN
)
(1)
where:
• VOFSMIN and VOFSMAX = Minimum and maximum offset voltages over the specified temperature range
• TMIN and TMAX = Minimum and maximum temperatures
7.2 Gain Drift Measurement
Gain drift is defined as the change of gain error over the specified temperature range. Gain drift is calculated
using the box method in which a box is formed over the maximum and minimum gain errors and over the
specified temperature range. The box method specifies limits for the temperature error but does not specify the
exact shape and slope of the device under test. For that reason gain drift is specified as a positive number only
even though the drift can possibly be negative. 方程式 2 describes the gain drift calculation using the box
method.
Gain Drift (ppm/°C) = (GEMAX –GEMIN) / (TMAX –TMIN
)
(2)
where:
• GEMIN and GEMAX = Minimum and maximum gain errors over the specified temperature range
• TMIN and TMAX = Minimum and maximum temperatures
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7.3 Noise Performance
Adjust the data rate and gain to optimize the noise performance of the individual ADCs. When reducing the data
rate by increasing the oversampling ratio (OSR), averaging is increased and results in lower noise. 表7-1 and 表
7-2 summarize the noise performance of ADC1y and ADC2y. The data are representative of typical noise
performance at TA = 25°C using fMCLK = 8.192 MHz. The data shown are typical input-referred noise results in
units of μVRMS with the analog inputs shorted together and averaging data across a 1-ms period. Use 方程式 3
to calculate effective resolution from the provided μVRMS numbers.
Effective Resolution = ln[(2 × VREFy / Gain) / VRMS-Noise] / ln(2)
(3)
The noise performance of ADC1y improves by a factor of √2 in global-chop mode.
表7-1. ADC1y Noise Performance (μVRMS) at TA = 25°C
GAIN
DATA RATE,
fMCLK = 8.192 MHz
OSR1y
4
8
16
32
64
64 kSPS
32 kSPS
16 kSPS
8 kSPS
4 kSPS
2 kSPS
1 kSPS
0.5 kSPS
20.7
6.19
3.70
2.61
1.88
1.46
1.15
0.88
10.8
3.96
2.51
1.78
1.28
0.91
0.65
0.44
10.8
3.96
2.51
1.78
1.28
0.91
0.65
0.44
10.8
3.96
2.51
1.78
1.28
0.91
0.65
0.44
128
256
512
1024
2048
4096
8192
表7-2. ADC2y Noise Performance (μVRMS) at TA = 25°C
GAIN
CONVERSION TIME,
fMCLK = 8.192 MHz
OSR2y
1
2
4
64
93.4
48.4
31.9
22.4
48.3
26.5
17.5
12.1
48.3
26.5
17.5
12.1
46.87 μs
62.50 μs
93.75 μs
156.25 μs
128
256
512
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8 Detailed Description
8.1 Overview
The ADS131B23 is a complete analog front-end (AFE) for industrial battery management systems (BMS) that
integrates two simultaneous-sampling, high-precision, 24-bit ADC channels (ADC1A, ADC1B) to redundantly
measure battery current with high resolution and accuracy using an external shunt resistor. Two independent
digital overcurrent detection comparators (OCCA, OCCB) work in parallel to the two ADCs for fast overcurrent
detection.
Additionally, a multiplexed, 16-bit ADC (ADC2A) is available to measure shunt temperature using external
temperature sensors, such as thermistors or analog output temperature sensors, as well as other voltages in the
system. ADC2A is equipped with a channel sequencer that automatically steps through the configured
multiplexer inputs, selects them for measurement, and starts ADC conversions.
The device is partitioned into two sections, A and B. The circuitry in section A is independent from the circuitry in
section B, however both sections are powered from the same supply, derive their respective clocks from the
same main clock source, and share the same digital control and serial interface.
Besides the various ADC channels, each section provides:
• A precision, low-drift, 1.25-V voltage reference (REFA, REFB) that feeds the ADCs in each section
• A negative charge pump (NCPA, NCPB) that provides a negative supply voltage for the gain stages in front of
each ADC to allow signal measurements below ground
• A Test DAC (Test DAC A, Test DAC B), which generates precision test voltages that can be routed for
measurement to the ADCs in the other section
• Two GPIOs (GPIO0A, GPIO1A and GPIO0B, GPIO1B) with logic levels based on AVDD
In many BMS applications, the AFE is powered from an unregulated isolated DC/DC converter. For that reason,
the ADS131B23 integrates linear regulators (AVDD and IOVDD LDOs) that accept voltages between 4 V and 16
V and provide regulated 3.3-V analog and digital supply rails for the internal circuitry. The two low-dropout
regulators (LDOs) can also provide a limited amount of current to external circuitry. A common use case is to
power the primary side of a digital isolator, to isolate the SPI communication to a host microcontroller, with the
IOVDD LDO output; see the ADS131B26Q1EVM-PDK Evaluation Module user guide.
The main clock for the ADS131B23 is either provided by the internal 8.192-MHz oscillator or by an external clock
provided at the CLK pin.
A multitude of monitoring and diagnostic features are integrated in the device to mitigate and detect random
hardware faults to aid in the development of functional safe BMS, such as:
• Supply undervoltage, overvoltage, overtemperature, and oscillation monitors
• Supply-voltage readback capability through ADC2A
• ADC overrange monitors
• A set of open-wire detection current sources and sinks per ADC
• Clock monitors
• Cyclic redundancy check (CRC), timeout monitor, and SCLK counter on the SPI to achieve high data integrity
for the communication
• Register and memory map CRC
• ADC conversion and sequence counters
The device offers five GPIOs (GPIO0 through GPIO4) with logic levels based on IOVDD and optional pulse-
width modulation (PWM) input and output capability. GPIO2 can alternatively be configured as a FAULT output,
and GPIO3 and GPIO4 can be configured as overcurrent comparator outputs.
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8.2 Functional Block Diagram
RCAPA
AVDD
APWR
AGND
AVDD
AVDD
LDO
Negative
Charge-
Pump A
Precision
REFA
Buf
VREFA = 1.25 V
VNCPA
AVDD = 3.3 V
GPIO0A
RCAPA
IOVDD
GPIO1A
Section A
RBIAS
V0A
V1A
Gain = 1 to 4
IOVDD
LDO
DPWR
DGND
16-bit, 64-kSPS
Delta-Sigma
ADC2A
V2A
V3A
PGA
Sequencer
TMP61
IOVDD
V4A
V5A
Mux
V6A
VREFA
MCLK
DVDD
LDO
V7A
AGNDA
DCAP
Internal
Temperature
Sensor A
Supply
Voltage
Readback
Test DAC A
VREFA
ADC1B
DVDD
HV-
Battery
Current
Gain = 4, 8, 16, 32
PGA
CPA
CNA
24-bit, 64-kSPS
Delta-Sigma
ADC1A
CSn
OCCA
Fast Filter
Path
SCLK
SDI
SDO
DRDYn
VREFA
MCLK
Control,
SPI with CRC
Gain = 4, 8, 16, 32
PGA
CPB
CNB
24-bit, 64-kSPS
Delta-Sigma
ADC1B
RESETn
OCCB
Fast Filter
Path
VREFB
MCLK
Section B
GPIO0/MHD
GPIO1
Monitors
GPIOs
&
with PWM
Capability
GPIO2/FAULT
GPIO3/OCCA
GPIO4/OCCB
Diagnostics
ADC1A
ADC2A
Test DAC B
VREFB
GPIO0B
GPIO1B
MCLK
CLK Select
CLK
VNCPB
VREFB = 1.25 V
Diagnostic
Oscillator
OSCD
Main
Oscillator
OSCM
Negative
Charge-
Pump B
Precision
REFB
Buf
ADS131B23
AVDD
RCAPB
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8.3 Feature Description
8.3.1 Naming Conventions
Throughout this document, suffixes x and y refer to certain elements of the device:
• Suffix y refers to elements in both sections A and B.
For example, ADC1y refers to ADC1A as well as to ADC1B.
• Suffix x either refers to all ADCs in one section or to all analog inputs of ADC2y.
For example, ADCxA refers to ADC1A and ADC2A, and VxA refers to analog inputs V0A to V7A of ADC2A.
8.3.2 Precision Voltage References (REFA, REFB)
The ADS131B23 integrates two precision, low-drift, band-gap voltage references (REFA and REFB), one for
each section of the device. The references have a nominal voltage of 1.25 V. No external voltage reference can
be provided to the device. All ADCs in section A use REFA and, correspondingly, all ADCs in section B use
REFB. The RCAPA and RCAPB pins are outputs of the voltage references. Decouple the RCAPA pin with a 1-
μF capacitor to AGNDA and the RCAPB pin with a 1-μF capacitor to AGNDB. The voltage references are
buffered and can source external circuitry with a limited amount of current out of the RCAPy pins. The buffers
cannot sink any current. See the Electrical Characteristics table for details.
8.3.3 Clocking (MCLK, OSCM, OSCD)
The ADS131B23 requires a main clock (MCLK) to operate. As shown in 图 8-1, the main clock to the
ADS131B23 is provided in one of two ways:
• By the internal 8.192-MHz main oscillator (OSCM) or
• By an external clock on the CLK pin
The CLK_SOURCE bit selects the according main clock source for the device. At device power-up or after
device reset, the internal main oscillator is selected as the MCLK source by default.
CLK pin
Mux
Main Clock (fMCLK)
Main Oscillator
(OSCM)
Clock Divider
÷2
Modulator Clock (fMOD
)
图8-1. Main Clock Selection Diagram
The modulator clock of the various delta-sigma ADCs is derived from the common main clock. A clock divider
divides the main clock frequency (fMCLK) by a factor of two to create the modulator frequency (fMOD = fMCLK / 2)
with a duty cycle of 50%.
Before changing the clock source using the CLK_SOURCE bit, disable all ADCs using the respective ADC
enable bits or set the device in standby mode to prevent clock glitching during the clock switchover. When
switching from an external clock source to the internal main oscillator, keep the external clock running until after
the device switched over to the internal main oscillator.
The ADS131B23 integrates a second internal oscillator, called the diagnostic oscillator (OSCD), which is used
for various monitoring and diagnostic functions.
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8.3.4 ADC1y
The primary purpose of the 24-bit ADC1A and ADC1B is to redundantly measure battery current across an
external low-side, GND-referenced shunt resistor.
The ADC1y channel signal chain consists of two differential analog inputs (CPy, CNy), an input multiplexer
followed by a programmable gain amplifier (PGA), a delta-sigma modulator and digital filter, and the global-chop
and calibration logic.
8.3.4.1 ADC1y Input Multiplexer
The input multiplexer controls which signals are routed to the PGA of the ADC1y channel. Configure the input
multiplexer using the MUX1y[1:0] bits. The input multiplexer allows the following inputs to be connected to the
PGA:
• The differential analog signal between the CPy and CNy inputs.
• The inverse differential analog signal between the CPy and CNy inputs.
• Internal short to AGNDy. The analog inputs CPy and CNy are disconnected from the PGA in this case. Use
this setting for self-offset calibration of the ADC1y channel.
• DC test signal provided by the Test DAC of the other section.
图 8-2 shows a diagram of the ADC1A input multiplexer and 表 8-1 lists the according switch positions
depending on the MUX1A[1:0] bit settings.
AVDD
Current
Source
S3
S1
ADC1AP
CPA
S2
S3n
AGNDA
CNA
ADC1AN
S_TDAC
Current
Sink
Test DAC B
AGNDA
图8-2. ADC1A Input Multiplexer
表8-1. ADC1A Multiplexer Switch Positions Based on MUX1A[1:0] Bit Settings
MUX1A[1:0]
SETTING
S1
S2
S3
S3n
S_TDAC
00b
Closed
Closed
Open
Open
Open
Closed
Open
Open
Closed
Open
Open
Open
Open
01b
10b
Closed
Closed
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表8-1. ADC1A Multiplexer Switch Positions Based on MUX1A[1:0] Bit Settings (continued)
MUX1A[1:0]
SETTING
S1
S2
S3
S3n
S_TDAC
11b
Open
Open
Closed
Open
Closed
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8.3.4.2 ADC1y Programmable Gain Amplifier (PGA)
ADC1y features an integrated programmable gain amplifier (PGA) that provides gains of 4, 8, 16, and 32. Select
the gain setting using the GAIN1y[1:0] bits.
Varying the PGA gain scales the differential full-scale input voltage range (FSR) of ADC1y. 方程式 4 describes
the relationship between FSR and gain. 方程式 4 uses the internal reference voltage, 1.25 V, as the scaling
factor without accounting for gain error caused by tolerance in the reference voltage.
FSR = ±1.25 V / Gain
(4)
表8-2 shows the corresponding full-scale ranges for each gain setting.
表8-2. ADC1y Full-Scale Range
GAIN SETTING
FSR
4
8
±312.5 mV
±156.25 mV
±78.125 mV
±39.063 mV
16
32
To measure bidirectional currents across a shunt resistor that is GND referenced, the PGA must accept voltages
below GND. For that reason, the negative supply of the PGA is provided by an internal negative charge pump
(NCPy). This provision allows the PGA to accept absolute input voltages on each input below GND.
The input impedance of the ADC1y channel is independent of the gain, OSR, and global-chop mode settings.
The input impedance does, however, scale indirectly proportional with the MCLK frequency.
8.3.4.3 ADC1y ΔΣModulator
ADC1y uses a second-order delta-sigma (ΔΣ) modulator to convert the analog input signal to a 1's density
modulated digital bit-stream. The ΔΣ modulator oversamples the input signal at a frequency many times
greater than the output data rate. The modulator frequency, fMOD, of ADC1y is equal to half the main clock
frequency (that is, fMOD = fMCLK / 2).
8.3.4.4 ADC1y Digital Filter
The ADC1y ΔΣ modulator bitstream feeds into a digital filter. The digital filter is a linear phase, finite impulse
response (FIR), low-pass sinc3 filter that attenuates the out-of-band quantization noise of the ΔΣ modulator.
The low-resolution, high-speed modulator output is decimated and downsampled by the digital filter to produce
high-resolution ADC data at an output data rate of fDATA. The decimation factor, defined as per 方程式5, is called
the oversampling ratio (OSR).
OSR = fMOD / fDATA
(5)
The OSR determines the amount of averaging that is applied to the modulator output in the digital filter and,
therefore, the filter bandwidth and conversion noise. Higher OSRs lead to lower filter bandwidth and better noise
performance.
The OSR is programmable within a range of 64 and 8192 using the OSR1y[2:0] bits. 表 8-3 lists the OSR
settings for ADC1y together with the corresponding output data rates and –3-dB frequencies of the sinc3 filter
for a nominal MCLK frequency of 8.192 MHz.
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表8-3. ADC1y OSR Settings, Output Data Rates and –3-dB Frequencies for
fMCLK = 8.192 MHz
OSR
64
OUTPUT DATA RATE (fDATA)
–3-dB FREQUENCY
16.8 kHz
8.4 kHz
64 kSPS
32 kSPS
16 kSPS
8 kSPS
4 kSPS
2 kSPS
1 kSPS
500 SPS
128
256
4.2 kHz
512
2.1 kHz
1024
2048
4096
8192
1.0 kHz
524 Hz
262 Hz
131 Hz
图 8-3 and 图 8-4 show the filter frequency response of the sinc3 filter. The sinc3 filter has infinite attenuation at
integer multiples of the output data rate except for integer multiples of fMOD. As with all digital filters, the digital
filter response repeats at integer multiples of the modulator frequency, fMOD. The data rate and filter notch
frequencies scale with fMOD
.
0
-20
0
-20
-40
-40
-60
-60
-80
-80
-100
-120
-140
-160
-100
-120
-140
-160
0
8
16
24
32
40
48
)
56
64
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
Normalized Frequency (fIN/fDATA
Normalized Frequency (fIN/fDATA
)
图8-4. Sinc3 Filter Frequency Response to fMOD
图8-3. Sinc3 Filter Frequency Response
(OSR = 64)
8.3.4.5 ADC1y Offset and Gain Calibration
ADC1y provides the ability to compute offset and gain corrected conversion data using user-programmable
offset and gain correction registers. As shown in 图 8-5, the 24-bit offset correction value (OCAL1y[23:0]) is
subtracted from the conversion data before being multiplied by the 16-bit gain correction factor (GCAL1y[15:0]).
Output data are rounded to the final resolution and clipped to +FS and –FS code values after the scaling
operation. The offset and gain calibration coefficients must be stored in external nonvolatile memory and
programmed into the offset and gain calibration registers each time the device powers up or resets because the
ADS131B23 registers are volatile.
+
Digital
Filter
Output data
clipped to 24 bits
ADC1y
X
-
OCAL1y[23:0]
GCAL1y[15:0]
图8-5. Calibration Logic Block Diagram
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The 24-bit offset calibration value is provided in two's complement format and programmed into the
OCAL1y[23:0] bit field that spans across the ADC1y_OCAL_MSB and ADC1y_OCAL_LSB registers. 表 8-4
shows example offset calibration values. The LSB size of the offset calibration value is calculated as follows:
LSB size = (2 × VREFy) / (GAIN1y × 224)
表8-4. Offset Calibration Value Examples
OCAL1y[23:0] VALUE
APPLIED OFFSET CORRECTION
000010h
–16 LSB
–1 LSB
1 LSB
000001h
FFFFFFh
FFFFF0h
16 LSB
The 16-bit gain calibration value is provided in two's complement format and programmed into the GCAL1y[15:0]
bit field. One LSB of the gain calibration value equals a gain correction factor of 1/216 = 0.000015. 表 8-5 shows
example gain calibration values.
表8-5. Gain Calibration Value Examples
GCAL1y[15:0] VALUE
APPLIED GAIN CORRECTION
7FFFh
0001h
0000h
FFFFh
8000h
1.499985
1.000015
1
0.999985
0.5
The recommended calibration procedure is as follows:
1. Preset the offset and gain calibration registers to OCAL1y[23:0] = 000000h and GCAL1y[15:0] = 0000h,
respectively.
2. Perform an offset calibration by shorting the ADC1y inputs internally using the respective input multiplexer
setting (MUX1y[1:0] = 10b), or short the inputs externally at the system level to include the offset error of the
external filter stages. Acquire multiple conversion data and write the average value of the data into the offset
calibration registers. Averaging the data reduces conversion noise to improve calibration accuracy.
3. Perform a gain calibration by applying a precision calibration signal to the ADC1y inputs or at the system
level to include the gain error of the external filter stages. Choose the calibration voltage to be less than the
full-scale input range to avoid clipping the output code. Clipped output codes result in inaccurate calibration.
For example, use a 150-mV calibration signal when using gain = 8. Acquire multiple conversion data and
average the results. Use 方程式6 to calculate the gain calibration value.
Gain Calibration Value = (expected output code / actual output code)
(6)
The expected output code for a 150-mV calibration voltage using gain = 8 is: (150 mV / LSB size) =
7AE148h, where LSB size = (2 × 1.25 V) / (8 × 224). If the actual measured output code is 6FB587h for
example, then the gain calibration factor calculates to 1.1. The resulting gain calibration value to write into
the GCAL1y[15:0] bit field is: (1.1 –1) / (1 / 216) = 199Ah.
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8.3.4.6 ADC1y Conversion Data
Conversion data for ADC1A and ADC1B are 24 bits and are automatically output on SDO as part of the SPI
frame, unless register data are output following a register read command.
Data are provided in binary two's complement format. Use 方程式7 to calculate the size of one code (LSB).
1 LSB = (2 × VREFy / Gain) / 224 = +FSR / 223
(7)
A positive full-scale input VIN ≥ +FSR – 1 LSB = VREFy / Gain – 1 LSB produces an output code of 7FFFFFh
and a negative full-scale input (VIN ≤–FSR = –VREFy / Gain) produces an output code of 800000h. The output
clips at these codes for signals that exceed full-scale.
表8-6 summarizes the ideal output codes for different input signals.
表8-6. Ideal Output Code versus Input Signal (24-Bit
Conversion Data)
INPUT SIGNAL
(VIN = VAINP –VAINN
IDEAL OUTPUT CODE
)
≥FSR (223 –1) / 223
FSR / 223
7FFFFFh
000001h
000000h
FFFFFFh
800000h
0
–FSR / 223
≤–FSR
图8-6 shows the mapping of the analog input signal to the output codes.
7FFFFFh
7FFFFEh
000001h
000000h
FFFFFFh
800001h
800000h
¼
¼
-FS
-FS
0
FS
Input Voltage VIN
223 - 1
223 - 1
FS
223
223
图8-6. Code Transition Diagram (24-Bit Conversion Data)
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8.3.5 ADC2y
The purpose of the multiplexed, 16-bit ADC2A is to measure shunt temperature using external thermistors or
analog output temperature sensors, and any other voltages that must be measured in the BMS.
The ADC2y channel signal chain consists of eight analog inputs (V0y to V7y), an input multiplexer followed by a
programmable gain amplifier (PGA), a delta-sigma modulator and digital filter, calibration logic, and a channel
sequencer.
8.3.5.1 ADC2y Input Multiplexer
The input multiplexer controls which signals are routed to the positive and negative PGA inputs of the ADC2y
channel in each sequence step. Configure the input multiplexer using the SEQ2y_STEPn_CH_P[3:0] and
SEQ2y_STEPn_CH_N bits.
The input multiplexer allows the following inputs to be connected to the PGA:
• Any of the eight analog inputs, V0y to V7y, in single-ended measurement configuration when AGNDy is
selected as the negative multiplexer channel.
• Any of the seven analog inputs, V0y to V6y, in single-ended measurement configuration when V7y is selected
as the negative multiplexer channel and connected to AGNDy externally.
• Any of the seven analog inputs, V0y to V6y, in pseudo-differential measurement configuration when V7y is
selected as the negative multiplexer channel. Connect a positive bias voltage to V7y in this case, either using
an external bias voltage or the internal common-mode voltage of the VCMy buffer.
• Internal temperature sensor, TSy.
• Internal short to AGNDy. Use this setting for self-offset calibration of the ADC2y channel.
• DC test signal provided by the Test DAC of the other section.
• Attenuated signals of the various supply voltages (APWR, DPWR, AVDD, IOVDD, and DVDD).
Whenever a signal other than an analog input is selected as the positive multiplexer input, the analog inputs are
disconnected from the PGA and AGNDy is selected automatically as the negative multiplexer input. 图 8-7
illustrates a diagram of the ADC2A input multiplexer.
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Temperature Sensor TSA
Test DAC B
APWR/103
DPWR/103
AVDD/4
IOVDD/4
DVDD/2
AVDD
AGNDA
Current
Source
200 Ω
MUX2AP
ADC2AP
V0A
Current
Sink
V1A
V2A
V3A
V4A
V1A to V6A use same structure as V0A
V5A
V6A
Current
Source
200 Ω
V7A
Current
Sink
+
–
VCMA
MUX2AN
ADC2AN
AGNDA
AGNDA
AGNDA
图8-7. ADC2A Input Multiplexer
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8.3.5.2 ADC2y Programmable Gain Amplifier (PGA)
ADC2y features an integrated programmable gain amplifier (PGA) that provides gains of 1, 2, and 4. Select the
gain setting using the SEQ2y_STEPn_GAIN[1:0] bits.
Varying the PGA gain scales the differential full-scale input voltage range (FSR) of ADC2y. 方程式 8 describes
the relationship between FSR and gain. 方程式 8 uses the internal reference voltage, 1.25 V, as the scaling
factor without accounting for gain error caused by tolerance in the reference voltage.
FSR = ±1.25 V / Gain
(8)
表8-7 shows the corresponding full-scale ranges for each gain setting.
表8-7. ADC2y Full-Scale Range
GAIN SETTING
FSR
1
2
4
±1.25 V
±625 mV
±312.5 mV
When performing single-ended measurements (that is, AGNDy is selected as the negative multiplexer channel
for ADC2y), gain settings of 1 and 2 only allow for unipolar measurements, whereas gain setting of 4 allows for
both unipolar and bipolar input voltage measurements. See the absolute input voltage range specification of
ADC2y in the Recommended Operating Conditions table for details and the ADC2y Measurement Configurations
section for example input configurations. Unipolar measurements only use the positive code range from
approximately 0000h to 7FFFh, which maps to an input voltage range from approximately 0 V to +FS.
The input impedance of the ADC2y channel depends on two factors: the main clock frequency (fMCLK) and the
selected OSR setting. The Electrical Characteristics table lists typical input impedance values for fMCLK = 8.192
MHz at the various OSR settings. Increasing the OSR by twice the value effectively doubles the input
impedance. The input impedance scales indirectly proportional with the MCLK frequency.
8.3.5.3 ADC2y ΔΣModulator
ADC2y uses a second-order, delta-sigma (ΔΣ) modulator to convert the analog input signal to a 1's density
modulated digital bitstream. The ΔΣmodulator oversamples the input signal at a frequency many times greater
than the output data rate. The modulator frequency, fMOD, of ADC2y is equal to half the main clock frequency
(that is, fMOD = fMCLK / 2).
8.3.5.4 ADC2y Digital Filter
The ADC2y ΔΣ modulator bitstream feeds into a digital filter. The digital filter is a linear phase, finite impulse
response (FIR), low-pass sinc filter that attenuates the out-of-band quantization noise of the ΔΣmodulator.
In contrast to ADC1y, ADC2y always operates in a single-shot conversion mode fashion. The ADC2y sequencer
triggers the individual conversions. The digital filter resets at the start of every conversion and must completely
settle for every conversion. ADC2y only outputs settled conversion results, assuming that the input signal settled
before the conversion started.
Use the OSR2y[1:0] bits to select the conversion time for ADC2y. For an OSR = 64, the filter is comprised of a
pure sinc3 filter. A sinc3 filter takes three cycles to settle. Therefore, the conversion time for an OSR = 64 equals
(3 × 64 / fMOD = 192 tMOD = 384 tMCLK). For higher OSR settings the sinc3 filter is followed by a sinc1 filter.
表 8-8 lists an overview of the OSR settings and the corresponding conversion times for ADC2y based on a
nominal MCLK frequency of 8.192 MHz.
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表8-8. ADC2y OSR Settings and Conversion Times for fMCLK = 8.192 MHz
OSR
SINC3
64
CONVERSION TIME
OVERALL
64
SINC1
tMCLK
μs
1
2
4
8
384 tMCLK
512 tMCLK
768 tMCLK
1280 tMCLK
46.87 μs
128
64
62.50 μs
93.75 μs
156.25 μs
256
64
512
64
8.3.5.5 ADC2y Offset and Gain Calibration
ADC2y provides the ability to compute offset and gain corrected conversion data using user-programmable
offset and gain correction registers. The same calibration values are used for all sequence steps, however, the
offset and gain correction factors are not applied when the internal temperature sensor is selected for
measurement by MUX2y. As shown in 图 8-8, the 16-bit offset correction value (OCAL2y[15:0]) is subtracted
from the conversion data before being multiplied by the 16-bit gain correction factor (GCAL2y15:0]). Output data
are rounded to the final resolution and clipped to +FS and –FS code values after the scaling operation. The
offset and gain calibration coefficients must be stored in external nonvolatile memory and programmed into the
offset and gain calibration registers each time the device powers up or resets because the ADS131B23 registers
are volatile.
+
Digital
Filter
Output data
clipped to 16 bits
ADC2y
X
-
OCAL2y[15:0]
GCAL2y[15:0]
图8-8. Calibration Logic Block Diagram
The 16-bit offset calibration value is provided in two's-complement format and programmed into the
OCAL2y[15:0] bit field. 表 8-9 shows example offset calibration values. The LSB size of the offset calibration
value is calculated using 方程式9 and 方程式10 depending on the selected gain setting.
GAIN2y = 1: LSB size = VREFy / 215
(9)
GAIN2y = 2 or 4: LSB size = VREFy / (2 × 215)
(10)
表8-9. Offset Calibration Value Examples
OCAL2y[15:0] VALUE
APPLIED OFFSET CORRECTION
0010h
0001h
FFFFh
FFF0h
–16 LSB
–1 LSB
1 LSB
16 LSB
The 16-bit gain calibration value is provided in two's-complement format and programmed into the GCAL2y[15:0]
bit field. One LSB of the gain calibration value equals a gain correction factor of 1/216 = 0.000015. 表8-10 shows
example gain calibration values.
表8-10. Gain Calibration Value Examples
GCAL2y[15:0] VALUE
APPLIED GAIN CORRECTION
7FFFh
0001h
0000h
FFFFh
1.499985
1.000015
1
0.999985
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表8-10. Gain Calibration Value Examples
(continued)
GCAL2y[15:0] VALUE
APPLIED GAIN CORRECTION
8000h
0.5
The recommended calibration procedure is as follows:
1. Preset the offset and gain calibration registers to OCAL2y[15:0] = 0000h and GCAL2y[15:0] = 0000h,
respectively.
2. Perform an offset calibration by shorting the ADC2y input in one or multiple sequence steps internally to
AGNDy using the respective input multiplexer setting (SEQ2y_STEPn_CH_P[3:0] = 1001b), or short one of
the ADC2y inputs externally at the system level to include the offset error of the external filter stages. Set the
gain for the respective sequence step to 1 or 2. Acquire multiple conversion data and write the average
value of the data into the offset calibration registers. Averaging the data reduces conversion noise to
improve calibration accuracy.
3. Perform a gain calibration by applying a precision calibration signal to one of the ADC2y inputs or at the
system level to include the gain error of the external filter stages. Choose the calibration voltage to be less
than the full-scale input range to avoid clipping the output code. Clipped output codes result in inaccurate
calibration. For example, use a 1.2-V calibration signal when using gain = 1. Acquire multiple conversion
data and average the results. Use 方程式11 to calculate the gain calibration value.
Gain Calibration Value = (expected output code / actual output code)
(11)
The expected output code for a 1.2-V calibration voltage using gain = 1 is: (1.2 V / LSB size) = 7AE1h,
where LSB size = (1.25 V / 215). If the actual measured output code is 6FB6h for example, then the gain
calibration factor calculates to 1.1. The resulting gain calibration value to write into the GCAL2y[15:0] bit field
is: (1.1 –1) / (1 / 216) = 199Ah.
8.3.5.6 ADC2y Sequencer
See the ADC2y Sequencer Operation and Sequence Modes section for details.
8.3.5.7 VCMy Buffers
The ADC2y signal chain includes a bias voltage generator of typically 0.78 V followed by a common-mode
buffer, VCMy. When the VCMy_EN bit is set, the output of the VCMy buffer is internally connected to the V7y
multiplexer channel to provide the bias voltage to V7y. Use the VCMy buffer to implement pseudo-differential
measurements, where V7y is selected as the negative multiplexer channel of ADC2y.
When the VCMy buffer is enabled, the capacitive load from V7y to AGNDy must be limited to less than 100 pF.
8.3.5.8 ADC2y Measurement Configurations
ADC2y allows measurements of input voltages in three different configurations, as summarized in 表 8-11, 图
8-9, 图8-10, and 图8-11.
表8-11. Overview of Possible Measurement Configurations for ADC2y
INPUT
CONFIGURATION
POSITIVE MUX
CHANNEL
NEGATIVE MUX
CHANNEL
GAIN
INPUT RANGE
ABSOLUTE
INPUT VOLTAGE
FIGURE
0 V to +FS =
VREFy / Gain
Single-ended
V0y to V7y
AGNDy
1, 2, or 4
Unipolar
图8-9
–0.3125 V to
0.3125 V
Single-ended
V0y to V7y
V0y to V6y
AGNDy
V7y
4
Bipolar
Bipolar
图8-10
图8-11
Pseudo-differential
1, 2, or 4
VV7y ±FS(1)
(1) Actual input range limited by absolute input voltage range specification in the Recommended Operating Conditions table.
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V0y
0 V to 1.25 V
Gain = 1
PGA
0.78 V
VCMy
Mux
ADC2y
HV-
V7y
AGNDy
HV-
图8-9. Single-Ended Input, Unipolar Voltage Measurement (Gain = 1)
V0y
-0.3125 V to 0.3125 V
Gain = 4
0.78 V
VCMy
Mux
PGA
ADC2y
HV-
V7y
AGNDy
HV-
图8-10. Single-Ended Input, Bipolar Voltage Measurement (Gain = 4)
V0y
0.78 V ±0.625 V
Gain = 2
0.78 V
VCMy
Mux
PGA
ADC2y
V7y
AGNDy
HV-
图8-11. Pseudo-Differential Input, Bipolar Voltage Measurement
(Gain = 2, Using Internal Bias Voltage)
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8.3.5.9 ADC2y Conversion Data
Conversion data for the sequence steps of ADC2y are 16 bits and (in contrast to ADC1y conversion data) stored
in the user register space (register addresses 10h to 1Fh). Read ADC2y conversion data using the register read
command.
Data are provided in binary two's-complement format. Use 方程式12 to calculate the size of one code (LSB).
1 LSB = (2 × VREFy / Gain) / 216 = +FSR / 215
(12)
A positive full-scale input VIN ≥+FSR –1 LSB = VREFy / Gain –1 LSB produces an output code of 7FFFh and
a negative full-scale input (VIN ≤ –FSR = –VREFy / Gain) produces an output code of 8000h. The output clips
at these codes for signals that exceed full-scale.
表8-12 summarizes the ideal output codes for different input signals.
表8-12. Ideal Output Code versus Input Signal (16-
Bit Conversion Data)
INPUT SIGNAL
(VIN = VAINP –VAINN
IDEAL OUTPUT CODE
)
≥FSR (215 –1) / 215
FSR / 215
7FFFh
0001h
0000h
FFFFh
8000h
0
–FSR / 215
≤–FSR
图8-12 shows the mapping of the analog input signal to the output codes.
0x7FFF
0x7FFE
0x0001
0x0000
0xFFFF
0x8001
0x8000
¼
¼
-FS
-FS
0
FS
Input Voltage (VIN
)
215 - 1
215 - 1
FS
215
215
图8-12. Code Transition Diagram (16-Bit Conversion Data)
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8.3.6 General-Purpose Digital Inputs and Outputs (GPIO0 to GPIO4)
The ADS131B23 offers five GPIO pins (GPIO0 to GPIO4) that use logic levels based on the IOVDD supply. See
the Electrical Characteristics table for details regarding the logic high and low levels. The GPIOs offer a
multitude of configuration options:
• Configure the individual GPIOs as either digital inputs or digital outputs using the respective GPIOx_DIR bits
(x = 0, 1, 2, 3, or 4).
• Configure the input and output format of the individual GPIOs as either static logic levels or PWM using the
respective GPIOx_FMT bits. See the GPIOx PWM Output Configuration section for details on how to
configure the PWM period and duty cycle for a specific GPIO.
• Four of the GPIO pins can be configured with a special output function (FAULT, MHD, OCCA, and OCCB)
using the respective GPIOx_SRC bits. Configure GPIOx as a digital output using the GPIOx_DIR bit when
selecting the special output function for GPIOx.
Use the GPOx_DAT bit to drive a logic high or low level on the respective GPIO pin when GPIOx is configured
as a digital output. The GPIO outputs are push-pull. GPIOx ignores the value written to the GPOx_DAT bit when
configured for a special output function.
The device always reads back the value of the GPIOs and provides the detected logic level in the
GPIx_DAT[1:0] bit fields, no matter if GPIOx is configured as digital input or output. See the GPIx_DAT[1:0] bit
field descriptions for details on how the device decodes PWM signals.
The GPIOs are configured as inputs when the device is held in reset.
8.3.6.1 GPIOx PWM Output Configuration
When GPIOx is configured for PWM format using the GPIOx_FMT bit, the PWM period and duty cycle can be
independently configured for a logic high and low level with fine granularity. The GPIOx_LL_PWM_LC[6:0]
(GPIOx logic low level PWM low counter value) and GPIOx_LL_PWM_HC[6:0] (GPIOx logic low level PWM high
counter value) bits together with the GPIOx_PWM_TB[1:0] (GPIOx PWM time base) bits determine the PWM
period and duty cycle when a logic low level is driven as per the GPOx_DAT bit. Similarly, the
GPIOx_LH_PWM_LC[6:0] (GPIOx logic high level PWM low counter value) and GPIOx_LH_PWM_HC[6:0]
(GPIOx logic high level PWM high counter value) bits together with the GPIOx_PWM_TB[1:0] bits determine the
PWM period and duty cycle when a logic high level is driven as per the GPOx_DAT bit.
The following equations specify the PWM period and duty cycle:
PWM period = (PWM high counter value + PWM low counter value) × PWM time base
PWM low time = (PWM low counter value × PWM time base)
(13)
(14)
(15)
(16)
PWM high time = (PWM high counter value × PWM time base)
PWM duty cycle = PWM high time / (PWM high time + PWM low time)
图 8-13 depicts a visual representation of how the various configuration values produce a certain PWM output.
The PWM period always starts with the PWM low time. Changes to the PWM period and duty cycle based on the
GPOx_DAT bit only take effect at the start of a new PWM period.
表 8-13 provides example configuration values for GPIO1 where the logic high level is configured for 75% duty
cycle using a 1-ms period and the logic low level for a 25% duty cycle using the same 1-ms period. The PWM
time base is chosen as 8.192 MHz / 1024 = 125 μs, assuming an fMCLK = 8.192 MHz is used. The sum of the
high and low counter must be eight in this case to yield a PWM period of 8 × 125 μs = 1 ms. Changing the
GPIO1_LL_PWM_LC[6:0] = 3Ch = 60 and the GPIO1_LL_PWM_HC[6:0] = 14h = 20 (for example) results in the
same 25% duty cycle, but at a PWM period of 80 × 125 μs = 10 ms.
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Host changes GPOx_DAT
using WREG command
PWM time base
1
6
1
2
1
6
1
2
1
2
1
6
Time Base Clock
GPIOx Output
PWM low time
PWM high time
PWM changes duty cycle at the
start of a new PWM period.
PWM period
图8-13. GPIOx PWM Output Timing Diagram
表8-13. GPIO1 PWM Configuration Example
CORRESPONDING TIME
(BASED ON fMCLK = 8.192 MHz)
BIT FIELD
GPIO1_PWM_TB[1:0]
BIT FIELD SETTING
VALUE
3h
1024 × tMCLK
125 μs
750 μs
250 μs
250 μs
750 μs
GPIO1_LL_PWM_LC[6:0]
GPIO1_LL_PWM_HC[6:0]
GPIO1_LH_PWM_LC[6:0]
GPIO1_LH_PWM_HC[6:0]
06h
02h
02h
06h
6
2
2
6
8.3.6.2 GPIOx PWM Input Readback
For GPIOx to decode PWM input signals, configure the GPIOx_FMT bit for PWM decoding. GPIOx uses the time
base configured in the GPIOx_PWM_TB[1:0] bits for PWM decoding. The decoded input value is provided in the
GPIx_DAT[1:0] bit field. The GPIOs decode PWM signals with four different levels as specified in the
GPI_DAT[1:0] bit field description.
The GPIx_DAT[1:0] bits need up to two PWM cycles to indicate the correct logic level after the PWM period or
duty cycle applied to GPIOx changed.
8.3.7 General-Purpose Digital Inputs and Outputs (GPIO0A, GPIO1A, GPIO0B, GPIO1B)
The ADS131B23 offers four additional GPIO pins (GPIO0A, GPIO1A, GPIO0B, and GPIO1B) that use logic
levels based on the AVDD supply. See the Electrical Characteristics table for details regarding the logic high and
low levels. The GPIOs offer a multitude of configuration options:
• Configure the individual GPIOs as either digital inputs or digital outputs using the respective GPIOxy_DIR bits
(x = 0 or 1, y = A or B).
• Configure the input format of the individual GPIOs for either static logic level or PWM inputs using the
respective GPIOxy_FMT bits. In contrast to GPIO0 to GPIO4, the GPIOxy do not offer PWM output capability.
Select the appropriate PWM timebase for each GPIO PWM decoder using the GPIOxy_PWM_TB[1:0] bits.
The timebase of the source driving the GPIOxy input must be equal to or slower than the timebase of the
GPIOxy input decoder, otherwise the logic levels are not correctly decoded. GPIOxy always uses static logic
levels when configured as a digital output.
Use the GPOxy_DAT bit to drive a logic high or low level on the respective GPIO pin when GPIOxy is configured
as a digital output. The GPIO outputs are push-pull.
The device always reads back the value of the GPIOs and provides the detected logic level in the
GPIxy_DAT[1:0] bit fields, regardless if GPIOxy is configured as a digital input or output. See the
GPIxy_DAT[1:0] bit field descriptions for details on how the device decodes PWM signals.
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8.3.8 Monitors and Diagnostics
The ADS131B23 integrates many monitor and diagnostic circuits to aid in the design of functional safe systems.
Monitors detect faults in the device, such as a supply undervoltage condition, whereas diagnostics detect faults
within the monitoring circuit to check if the monitor is still working as intended.
表 8-14 provides an overview of all available monitors and diagnostics. Most monitors can be enabled or
disabled as required using a dedicated monitor enable bit. In case a monitor detects a fault, the according low-
active fault flag is set to 0b. Except for the communication-related monitor fault flags, the fault flags must be
cleared to 1b by the host after the fault condition is removed. The communication-related monitor fault flags reset
to 1b automatically in the SPI frame following a frame where no communication fault occurred.
The monitors that have a dedicated diagnostic circuit to check the integrity of the monitor show the respective
diagnostic enable bit in 表8-14.
The monitors have individual fault response times, which is the time from fault occurrence to fault flag indication,
as specified in the Electrical Characteristics table.
表8-14. Monitor and Diagnostic Overview
DIAGNOSTIC ENABLE FAULT FLAG REGISTER
MONITOR NAME
MONITOR ENABLE BIT MONITOR FAULT FLAG
BIT
LOCATION
SUPPLY MONITORS AND DIAGNOSTICS
Reset
N/A
RESETn
AVDD_OVn
AVDD_UVn
IOVDD_OVn
IOVDD_UVn
DVDD_OVn
DVDD_UVn
AVDD_OSCn
IOVDD_OSCn
DVDD_OSCn
N/A
STATUS_MSB
AVDD overvoltage
AVDD undervoltage
IOVDD overvoltage
IOVDD undervoltage
DVDD overvoltage
DVDD undervoltage
AVDD oscillation
IOVDD oscillation
DVDD oscillation
AVDD_OV_EN
AVDD_UV_EN
IOVDD_OV_EN
IOVDD_UV_EN
DVDD_OV_EN
DVDD_UV_EN
AVDD_OSC_EN
IOVDD_OSC_EN
DVDD_OSC_EN
AVDD_OV_DIAG_EN
AVDD_UV_DIAG_EN
IOVDD_OV_DIAG_EN
IOVDD_UV_DIAG_EN
DVDD_OV_DIAG_EN
DVDD_UV_DIAG_EN
AVDD_OSC_DIAG_EN
IOVDD_OSC_DIAG_EN
DVDD_OSC_DIAG_EN
SUPPLY_STATUS
SUPPLY_STATUS
SUPPLY_STATUS
SUPPLY_STATUS
SUPPLY_STATUS
SUPPLY_STATUS
SUPPLY_STATUS
SUPPLY_STATUS
SUPPLY_STATUS
AVDD LDO
overtemperature warning
AVDD_OTW_EN
IOVDD_OTW_EN
AVDD_CL_EN
AVDD_OTWn
IOVDD_OTWn
AVDD_CLn
N/A
N/A
N/A
N/A
SUPPLY_STATUS
SUPPLY_STATUS
SUPPLY_STATUS
SUPPLY_STATUS
IOVDD LDO
overtemperature warning
AVDD LDO output current
limit
IOVDD LDO output
current limit
IOVDD_CL_EN
IOVDD_CLn
AGNDA pin disconnect
AGNDB pin disconnect
DGND pin disconnect
AGNDA_DISC_EN
AGNDB_DISC_EN
DGND_DISC_EN
AGNDA_DISCn
AGNDB_DISCn
DGND_DISCn
AGNDA_DISC_DIAG_EN
AGNDB_DISC_DIAG_EN
DGND_DISC_DIAG_EN
SUPPLY_STATUS
SUPPLY_STATUS
SUPPLY_STATUS
ADC MONITORS AND DIAGNOSTICS
ADC1A overrange
ADC1B overrange
ADC2A overrange
ADC1A_OR_EN
ADC1A_ORn
ADC1B_ORn
ADC2A_ORn
N/A
N/A
N/A
ADC_STATUS
ADC_STATUS
ADC_STATUS
ADC1B_OR_EN
ADC2A_OR_EN
CLOCK MONITORS AND DIAGNOSTICS
MCLK_HI_DIAG_EN,
MCLK_LO_DIAG_EN
Main clock frequency
MCLK_MON_EN
MCLK_FAULTn
ADC_STATUS
Diagnostic oscillator
watchdog
OSCD_WD_EN
MCLK_WD_EN
OSCD_WDn
MCLK_WDn
OSCD_WD_DIAG_EN
MCLK_WD_DIAG_EN
ADC_STATUS
ADC_STATUS
Main clock watchdog
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表8-14. Monitor and Diagnostic Overview (continued)
DIAGNOSTIC ENABLE FAULT FLAG REGISTER
MONITOR NAME
MONITOR ENABLE BIT MONITOR FAULT FLAG
BIT
LOCATION
DIGITAL MONITORS AND DIAGNOSTICS
Register map section 1
CRC
REG_MAP1_CRC_FAULT
n
REG_MAP1_CRC_EN
N/A
DIGITAL_STATUS
DIGITAL_STATUS
DIGITAL_STATUS
DIGITAL_STATUS
Register map section 2
CRC
REG_MAP2_CRC_FAULT
n
REG_MAP2_CRC_EN
REG_MAP3_CRC_EN
N/A
N/A
N/A
Register map section 3
CRC
REG_MAP3_CRC_FAULT
n
MEM_MAP_CRC_FAULT MEM_MAP_CRC_DIAG[1:
Memory map CRC
n
0]
GPIOA readback
GPIOB readback
GPIO readback
N/A
N/A
N/A
N/A
N/A
N/A
GPIOA_DIAG_EN
GPIOB_DIAG_EN
GPIO_DIAG_EN
GPIA_GPIB_DATA
GPIA_GPIB_DATA
GPI_DATA
COMMUNICATION MONITORS AND DIAGNOSTICS
SPI CRC
N/A
TIMEOUT_EN
SCLK_COUNTER_EN
N/A
SPI_CRC_FAULTn
SPI_TIMEOUTn
N/A
N/A
N/A
N/A
STATUS_MSB
STATUS_MSB
STATUS_MSB
STATUS_MSB
SPI timeout
SCLK counter
Register access
SCLK_COUNT_FAULTn
REG_ACCESS_FAULTn
In addition to the monitors that detect faults in the device, the ADS131B23 also provides the indicators shown in
表8-15, which provide feedback about the device state or behavior.
表8-15. Indicator Overview
INDICATOR NAME
Command response
INDICATOR STATUS BIT
COMMAND_RESPONSE[3:0]
LOCK
STATUS BIT REGISTER LOCATION
STATUS_MSB
Lock state
STATUS_MSB
Clock source
CLOCK
STATUS_MSB
Operating mode
ADC2A sequence active
OTP bank
MODE
STATUS_MSB
SEQ2A_ACTIVE
OTB_BANK
STATUS_LSB
DIGITAL_STATUS
Lastly, the device provides the conversion and sequence counters shown in 表8-16 for the individual ADCs.
表8-16. Conversion and Sequence Counter Overview
COUNTER NAME
COUNTER BITS
CONV1A_COUNT[1:0]
CONV1B_COUNT[1:0]
SEQ2A_COUNT[1:0]
COUNTER BITS REGISTER LOCATION
ADC1A conversion counter
STATUS_LSB
ADC1B conversion counter
ADC2A sequencer counter
STATUS_LSB
STATUS_LSB
Besides the monitors, indicators, and counters mentioned in the previous tables, the ADS131B23 offers
additional means to check the integrity of the device, such as:
• Power-supply voltage readback using ADC2A
• A temperature sensor, TSA
• Two test DACs, TDACA and TDACB
• Open-wire detection current sources and sinks on every ADC
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8.3.8.1 Supply Monitors
Individual power-on reset (POR) circuits are implemented on the AVDD, IOVDD, and DVDD supplies. If any of
the three supplies drops below the respective POR threshold, the device is held in reset.
The ADS131B23 monitors the outputs of the three internal LDOs (AVDD, IOVDD, and DVDD) for overvoltage
(OV), undervoltage (UV), and oscillations. See the Electrical Characteristics table for the according monitor
detection thresholds. In case of an OV event, the respective LDO shuts down to prevent damage to the internal
circuitry. The LDO turns back on after the output voltage drops below the OV threshold. There is the potential
that the device resets if the supply voltage drops below the POR threshold before the LDO is turned on again.
The LDOs do not shut down when an OV diagnostic is performed.
AVDD or IOVDD can be supplied externally when shorting APWR to AVDD or DPWR to IOVDD, respectively,
and thus bypassing the internal LDOs. The monitors check the externally provided supply when bypassing the
internal LDO. Configure the IOVDD OV and UV monitor thresholds using the IOVDD_OV_TH and
IOVDD_UV_TH bits based on the used IOVDD supply.
The AVDD and IOVDD LDOs integrate individual temperature sensors to indicate potential overtemperature
events. Configure the overtemperature warning thresholds using the AVDD_OTW_CFG[1:0] and
IOVDD_OTW_CFG[1:0] bits.
The AGNDA, AGNDB, and DGND pins are monitored for pin disconnections. The AGND pin is implemented
redundantly and therefore does not provide a pin disconnection monitor.
The AVDD and IOVDD LDOs are designed with an output current limit to prevent excessive current draw from
the LDOs. When the LDOs are operating in current limit, the according fault flags are set. If more current draw is
demanded from the LDOs than the current limit, then the LDO output voltage typically drops below the POR
threshold and causes a POR event.
8.3.8.2 ADC Monitors
Every ADC has an individual delta-sigma modulator overrange monitor that indicates when a differential input
signal larger than the ADC overrange detection threshold is applied to the ADC inputs, as specified in the
Electrical Characteristics table.
The individual ADCs must be enabled, but do not need to convert for the overrange monitors to work.
8.3.8.3 Clock Monitors
The ADS131B23 integrates a diagnostic oscillator (OSCD) to monitor the frequency of the selected main clock
(MCLK), which is either sourced from the internal main oscillator (OSCM) or from an external clock provided at
the CLK pin. The MCLK_FAULTn flag is set to 0b when the frequencies between the main clock and the
diagnostic oscillator deviate by more than the main clock fault detection frequency threshold
(MCLK_FAULT_TH).
Additionally, individual watchdogs (MCLK_WD and OSCD_WD) monitor the main clock and the diagnostic
oscillator to detect a missing clock signal. The MCLK_WDn flag is set to 0b when the MCLK frequency drops
below fMCLK_WD_TH, and the OSCD_WDn flag is set to 0b when the OSCD frequency drops below fOSCD_WD_TH
.
8.3.8.4 Digital Monitors
The following sections explain the available digital monitors, such as Register Map CRC, Memory Map CRC,
and GPIO readback functionality.
8.3.8.4.1 Register Map CRC
Register map CRCs in the ADS131B23 are used to detect unintended changes in the register map contents.
The register map is divided into four sections.
Section 0 includes read-only bits only that update their values based on the device state or ADC2y conversion
data. Therefore, section 0 does not offer any register map CRC check.
Sections 1 to 3 include the device configuration bits and provide independent CRC checks. Enable the register
map CRC for each section using the REG_MAPx_CRC_EN (x = 1 to 3) bits. When the register map CRC for a
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section is enabled, the device constantly calculates a 16-bit CRC value across that register map section and
compares the internal calculation result against the CRC value provided by the user in the
REG_MAPx_CRC_VALUE[15:0]
bit
field.
If
the
internal
calculation
result
and
the
REG_MAPx_CRC_VALUE[15:0] do not match, the REG_MAPx_CRC_FAULTn is set to 0b. No other action is
taken by the device in the event of a register map section CRC fault.
The CRC calculation begins with the MSB of the first register in the respective register section and ends with the
LSB of last specified register in the respective register section using the polynomial selected in the CRC_TYPE
bit. Two types of CRC polynomials are available: CCITT CRC and ANSI CRC (CRC-16). See the
Communication Cyclic Redundancy Check (CRC) section for details on the CRC polynomials. The CRC
calculations are initialized with the seed value of FFFFh.
The CRC calculation is implemented serially, one register map bit per OSCD period. Therefore, unintended bit
changes are not indicated immediately in the REG_MAPx_CRC_FAULTn fault flags, but can take up to
tp(REG_MAP_CRC)
.
Use the following procedure to change register bits in sections 1 to 3 without accidentally causing a
REG_MAPx_CRC_FAULTn indication:
• Disable register map section x CRC by setting REG_MAPx_CRC_EN = 0b
• Wait fault response time tp(REG_MAP_CRC)
• In case REG_MAPx_CRC_FAULTn fault flag is set to 0b, clear the fault flag by writing 1b to the
REG_MAPx_CRC_FAULTn bit
• Optional: Verify REG_MAPx_CRC_FAULTn fault flag is cleared to 1b
• Optional: Clear DIGITAL_FAULTn fault flag by writing 1b to the DIGITAL_FAULTn bit
• Change the section x register bits as needed
• Update REG_MAPx_CRC_VALUE[15:0] based on the new register map section x settings
• Enable the register map section x CRC by setting REG_MAPx_CRC_EN = 1b
Register bits in section x can also be changed while the register map section x CRC is enabled as discussed in
the following procedure, but can cause unintended REG_MAPx_CRC_FAULTn indications.
• Change the section x register bits as needed while the register map section x CRC is enabled
• Update REG_MAPx_CRC_VALUE[15:0] based on the new register map section x settings
• Wait fault response time tp(REG_MAP_CRC)
• In case the REG_MAPx_CRC_FAULTn fault flag is set to 0b, clear the fault flag by writing 1b to the
REG_MAPx_CRC_FAULTn bit
• Optional: Verify the REG_MAPx_CRC_FAULTn fault flag is cleared to 1b
• Optional: Clear the DIGITAL_FAULTn fault flag by writing 1b to the DIGITAL_FAULTn bit
8.3.8.4.2 Memory Map CRC
Similar to the register map CRC, the device uses a memory map CRC to check the internal memory for random
bit changes. Changes to the internal memory bits can cause undetermined device behavior or degraded device
performance.
The memory map CRC is always enabled and constantly calculates the CRC value across the internal memory
map. The device compares the calculation result against a memory map CRC value that is stored in the memory
map in production. If the internal calculation result and the stored memory map CRC value do not match, the
MEM_MAP_CRC_FAULTn is set to 0b. No other action is taken by the device in the event of a memory map
CRC fault.
The CRC calculation is implemented serially, one memory map word per OSCD period. Therefore random bit
changes are not indicated immediately in the MEM_MAP_CRC_FAULTn fault flag, but can take up to
tp(MEM_MAP_CRC)
.
In case of a memory map CRC fault, write 1b to the MEM_MAP_CRC_FAULTn bit to clear the fault flag to 1b.
Reset the device in case the fault flag continues to set to 0b.
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8.3.8.4.3 GPIO Readback
All available GPIOs (GPIOx, GPIOxy) in ADS131B23 provide an independent readback path when the
respective GPIO is configured as digital output. That means an input receiver circuit independent from the output
driver circuit detects the voltage level driven on the GPIO pin. The result of the readback is displayed in the
according GPIx_DAT[1:0] and GPIxy_DAT[1:0] bit fields.
8.3.8.5 Communication Monitors
The communication related monitors (SPI CRC, SPI timeout, and SCLK counter) are explained in detail in the
Serial Interface Communication Structure section.
In addition the register access monitor indicates if a read or write register access was attempted to register
addresses FFh or beyond. Writing to or reading from not specified register addresses within the address range
from 00h to FEh does not trigger a fault indication. The data and register address returned when reading from a
non-existing register is all 0s.
8.3.8.6 Fault Flags and Fault Masking
Every monitor in the ADS131B23 has a corresponding fault flag (see 表 8-14) that sets to 0b when the
respective monitor detects a fault condition. The RESETn and communication related fault flags are located in
the STATUS_MSB register, whereas the supply, ADC, clock, and digital related fault flags are grouped together
in detailed status registers, as shown in 表 8-17. The STATUS_MSB register is transmitted as part of the
STATUS word at the beginning of every SPI frame as described in the STATUS Word section. To allow
immediate indication of any of the supply, ADC, clock, or digital related faults as part of the STATUS word, every
detailed status register has a corresponding combined fault flag in the STATUS_MSB register. That is, if any of
the fault flags in the detailed status register set to 0b, then the combined fault flag sets to 0b as well.
表8-17. Detailed Status Registers and Corresponding Combined Fault Flags
MONITOR FAULT FLAGS FOR:
DETAILED STATUS REGISTER LOCATION
COMBINED FAULT FLAG
IN STATUS_MSB REGISTER
Supply
ADC and clock
Digital
SUPPLY_STATUS
ADC_STATUS
SUPPLY_FAULTn
ADC_FAULTn
DIGITAL_STATUS
DIGITAL_FAULTn
To clear a set combined fault flag to 1b, the host must first clear all set fault flags in the corresponding detailed
status register. Only after all fault flags in the detailed status register are cleared to 1b can the host clear the
combined fault flag by writing 1b.
The ADS131B23 allows additional masking of individual fault flags located in the detailed status registers from
triggering the combined fault flag in the STATUS_MSB register. The masking bits are located in the
SUPPLY_FAULT_MASK, ADC_FAULT_MASK, and DIGITAL_FAULT_MASK registers. In case a fault flag in a
detailed status register is masked, a fault indicated by this masked fault flag does not trigger a fault indication of
the combined fault flag in the STATUS_MSB register. However, the fault is still indicated by the fault flag in the
detailed status register.
The following examples for the AVDD OV monitor explain the various configuration options:
• No AVDD OV fault indication required in either SUPPLY_STATUS (AVDD_OVn fault flag) or STATUS_MSB
(SUPPLY_FAULTn fault flag) register: Disable the AVDD OV monitor by setting AVDD_OV_EN = 0b.
• AVDD OV fault indication in SUPPLY_STATUS, but not in STATUS_MSB register: Enable the AVDD OV
monitor by setting AVDD_OV_EN = 1b. Mask the AVDD_OVn fault flag from triggering the SUPPLY_FAULTn
fault flag by setting AVDD_OV_MASK = 1b.
• AVDD OV fault indication in both SUPPLY_STATUS and STATUS_MSB register: Enable the AVDD OV
monitor by setting AVDD_OV_EN = 1b. Unmask the AVDD_OVn fault flag by setting AVDD_OV_MASK = 0b.
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8.3.8.7 FAULT Pin
The GPIO2/FAULT pin can be configured as a FAULT indication output by setting GPIO2_DIR = 1b and
GPIO2_SRC = 0b. The FAULT pin is active when any of the STATUS_MSB[14:7] fault flags set to 0b. The
FAULT pin changes to inactive as soon as all STATUS_MSB[14:7] fault flags are cleared to 1b.
The actual output signal of the FAULT pin when active or inactive depends on the GPIO2 format (GPIO2_FMT
bit) and FAULT pin polarity (FAULT_POL bit) configuration. See the respective bit descriptions and the General-
Purpose Digital Inputs and Outputs (GPIO0 to GPIO4) section for details. 表 8-18 shows an example where the
FAULT pin is configured for a static low signal in an active state, and a static high signal in an inactive state. The
pin can for example also be configured for a static low signal in an active state, and a PWM output signal with
50% duty cycle in an inactive state to act as some sort of heart beat signal when everything is okay. The
configuration options are endless.
表8-18. FAULT Pin Output Behavior Configuration Example
REGISTER BIT
GPIO2_DIR
GPIO2_SRC
GPIO2_FMT
FAULT_POL
BIT SETTING
DESCRIPTION
1b
0b
0b
0b
GPIO2/FAULT pin configured as digital output
FAULT selected as data source for GPIO2/FAULT pin
GPIO2/FAULT pin configured for static output levels
FAULT output is active low
Additionally, the ADS131B23 allows masking of any of the eight STATUS_MSB[14:7] fault flags from triggering
the FAULT pin. Use the mask bits in the FAULT_PIN_MASK register to mask individual fault flags. If a fault flag
is masked and the respective fault flag is set to 0b in the STATUS_MSB register, then no fault is indicated on the
FAULT pin.
8.3.8.8 Diagnostics and Diagnostic Procedure
Diagnostics detect faults within a monitoring circuit to check if the monitor is still working as intended. Enable a
diagnostic using the respective enable bit in 表 8-14 to inject a fault condition into the monitoring circuit. When
the according monitor fault flag sets to 0b within the specified monitor fault response time (see the Electrical
Characteristics table), the diagnostic completed successfully, indicating a correctly working monitor.
Except for the main clock frequency monitor diagnostics (MCLK_HI_DIAG_EN and MCLK_LO_DIAG_EN), all
diagnostics can be performed simultaneously to save execution time. The MCLK_HI_DIAG_EN and
MCLK_LO_DIAG_EN diagnostics must be performed sequentially. However, either the MCLK_HI_DIAG_EN or
the MCLK_LO_DIAG_EN can be executed together with all other diagnostics.
The following steps outline the general procedure for implementing a monitor diagnostic. An example for
implementing the AVDD UV monitor diagnostic is shown in parentheses.
• Enable monitor (set AVDD_UV_EN = 1b)
• Wait fault response time (wait tp(AVDD_UV)
)
• Clear detailed fault flag (write 1b to AVDD_UVn)
• Optional: Verify detailed fault flag is cleared to 1b (read AVDD_UVn)
• Optional: Clear main fault flag (write 1b to SUPPLY_FAULTn)
• Enable diagnostic (set AVDD_UV_DIAG_EN = 1b)
• Wait fault response time (wait tp(AVDD_UV)
)
• Check if detailed fault flag is set to 0b (read AVDD_UVn)
• Disable monitor (set AVDD_UV_EN = 0b)
• Disable diagnostic (set AVDD_UV_DIAG_EN = 0b)
• Clear detailed fault flag (write 1b to AVDD_UVn)
• Optional: Clear main fault flag (write 1b to SUPPLY_FAULTn)
• Enable monitor (set AVDD_UV_EN = 1b)
The memory map CRC diagnostic is a small exception. Instead of an enable bit, select any of the three bit
patterns available in the MEM_MAP_CRC_DIAG[1:0] bit field to inject into the memory map CRC calculation.
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8.3.8.9 Indicators
The ADS131B23 provides a set of indicator bits inside the STATUS_MSB and STATUS_LSB registers that help
to verify the state of the device:
• Command response: The COMMAND_RESPONSE[3:0] bit field is transmitted in every SPI frame and
provides feedback about the command that was received by the device in the previous frame. Information
about which command was executed is also provided. See the COMMAND_RESPONSE[3:0] register bit field
description for details.
• Lock state: The LOCK bit indicates if the device is currently locked or unlocked. See the Commands section
for details on how to lock and unlock the device.
• Clock source: The CLOCK bit indicates which clock source the device is using as the main clock, either the
internal main oscillator (OSCM) or an external clock provided at the CLK pin.
• Operating mode: The MODE bit indicates which mode the device is currently operating in, either active,
standby, or power-down mode.
• ADC2A sequence active: The SEQ2A_ACTIVE bit indicates if a sequence on ADC2A is currently in progress.
An additional OTP_BANK status bit is provided in the DIGITAL_STATUS register. The device includes two one-
time programmable (OTP) memory banks, bank 0 and bank 1. Device configuration and calibration data are
stored during device production in those OTP banks. A corrupted OTP bank can cause undetermined device
behavior or degraded device performance. The information in bank 0 is duplicated in bank 1 for redundancy. At
device power-up or during reset, the device loads the content of OTP bank 0 into the internal memory. If the
device fails to acquire the data from bank 0, then the device loads the content from OTP bank 1. The
OTP_BANK bit indicates which bank was acquired. The device performs normally even when running from OTP
bank 1.
If the device fails to acquire data from OTP bank 1 as well, then the memory map CRC fault flag is set to 0b. If
resetting the device does not clear the MEM_MAP_CRC_FAULTn fault flag, consider the device damaged.
8.3.8.10 Conversion and Sequence Counters
The STATUS_LSB register includes 2-bit conversion and sequence counters for the various ADCs
(CONV1y_COUNT[1:0], SEQ2y_COUNT[1:0]).
The conversion counter, CONV1y_COUNT[1:0], increments every time a new conversion on ADC1y completes.
The counter rolls over from 11b to 00b. To reset the counter, disable ADC1y or place the device in standby or
power-down mode. The device makes sure that the conversion counter value always matches to the ADC1y
conversion result that is output in the same SPI frame.
The sequence counter, SEQ2y_COUNT[1:0], increments every time a new sequence on ADC2y completes. The
counter rolls over from 11b to 00b. To reset the counter, disable ADC2y or place the device in standby or power-
down mode. The device makes sure that the sequence counter value always matches to the ADC2y conversion
step results that are output in the same SPI frame. That means, in case a new sequence completes while
reading out conversion results from the ADC2y conversion step result registers (SEQxy_STEPx_DATA), the
conversion results from the new sequence run are blocked from overwriting the conversion result registers, but
are internally buffered. Only after the read command is complete do the buffered conversion results from the
new sequence run update the conversion step result registers.
8.3.8.11 Supply Voltage Readback
In addition to the dedicated supply monitors, all supplies (APWR, DPWR, AVDD, IOVDD, and DVDD) can also
be measured back internally through ADC2A. Resistor dividers are integrated in the device to attenuate the
supply voltages to within the input voltage range of ADC2A. See the Electrical Characteristics table for the
according attenuation factors. Use the SEQ2y_STEPx_CH_P[3:0] bits to configure an ADC2y sequence step for
any of the supply voltage measurements.
The supply voltage measurement accuracy depends on two factors:
• Multiplexer delay time (configured using the MUX2y_DELAY[2:0] bits)
• ADC2y conversion time (configured using the OSR2y[1:0] bits)
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The large resistor divider values used internally to divide the supply voltages down together with the internal filter
capacitor lead to a large RC filter time constant. The input signal therefore needs considerable time to settle
when the ADC2y multiplexer selects one of the supply voltage measurements. Increasing the multiplexer delay
time provides more time for the input signal to settle after the multiplexer change before ADC2y starts
converting. Setting the multiplexer delay time to equal to or greater than 256 × tMCLK provides sufficient time for
the input signals to settle when measuring the supply voltages.
In case increasing the multiplexer delay time is not possible, because the delay time affects all sequence steps
equally, configure multiple consecutive sequence steps for the same supply voltage measurement. Then
disregard the initial sequence step readings where the conversions are not settled yet.
The input impedance of ADC2y changes with the selected conversion time, see the Electrical Characteristics
table. The impedance of the resistor divider interacts with the input impedance of ADC2y leading to a gain error.
Increasing the ADC2y input impedance by increasing the ADC2y conversion time reduces the gain error for the
supply voltage measurements.
See 图 6-26 for details on how the supply voltage measurement accuracy changes with the multiplexer delay
time and the ADC2y conversion time.
8.3.8.12 Temperature Sensor (TSA)
The ADS131B23 integrates a temperature sensor (TSA) to measure the die temperature of the device. The
temperature sensor outputs a linear voltage that is proportional to temperature. The output voltage
characteristics (TSOffset, TSTC) of the temperature sensor are specified in the Electrical Characteristics table.
Use ADC2A to measure the output signal of TSA. To select TSA for measurement, configure any of the ADC2A
sequence steps (SEQ2A_STEPx_CH_P[3:0]) for TSA measurement. For best measurement performance,
configure the respective sequence step for gain = 2 using the SEQ2A_STEPx_GAIN[1:0] bits.
Use 方程式17 to convert the measured temperature sensor output voltage to die temperature:
Die temperature [°C] = 25°C + (Measured voltage –TSOffset) × TSTC
(17)
8.3.8.13 Test DACs (TDACA, TDACB)
The ADS131B23 integrates two independent Test DACs, TDACA and TDACB, one in each section of the device.
TDACA uses the voltage reference in section A (REFA), and TDACB the voltage reference in section B (REFB).
Use the TDACy_VALUE[2:0] bits to set the Test DAC output voltage to one of eight available settings. The output
voltage of Test DAC A can be applied as an input signal to any of the ADCs in section B for measurement to
check the accuracy and integrity of the ADCxB signal chains including the voltage reference (REFB). Use the
respective ADCxB multiplexer configuration bits to select Test DAC A as an input signal. Correspondingly, the
output voltage of Test DAC B can be applied as an input signal to any of the ADCs in section A for
measurement.
Selecting the Test DAC as an input signal for multiple ADCs at the same time may degrade the measurement
accuracy because of loading of the Test DAC output.
8.3.8.14 Open-Wire Detection
To detect potential pin fault conditions (such as open, short-to-adjacent pin, short-to-GND, or short-to-supply) on
the individual ADC analog input pins, every ADC integrates a dedicated open-wire detection (OWD) current
source and sink. See 图 8-2 and 图 8-7 for how the current sources and sinks are connected to the ADC inputs.
The input path of ADC2y includes a series impedance of approximately 200 Ω, see 图 8-7. Consider the
additional voltage drop across this impedance when enabling the current source or sink on any of the ADC2y
inputs.
As listed in 表8-19, every current source and sink offers individual configuration and control.
表8-19. Open-wire Detection Current Source and Sink Configuration
REGISTER BIT(S)
FUNCTION
OWDxy_SOURCE_VALUE[1:0]
Enables current source and selects current source value from three available settings
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表8-19. Open-wire Detection Current Source and Sink Configuration (continued)
REGISTER BIT(S)
OWDxy_SINK_VALUE[1:0]
OWDxy_SOURCE_MUX
OWDxy_SINK_MUX
FUNCTION
Enables current sink and selects current sink value from three available settings
Selects the input channel that the current source is routed to
Selects the input channel that the current sink is routed to
8.3.8.15 Overcurrent Comparators (OCCA, OCCB)
The ADS131B23 integrates two digital overcurrent comparators (OCCA, OCCB), which are used to provide a
faster response to overcurrent conditions than ADC1y, especially when ADC1y is operated at low data rates.
The comparators use the ADC1y ΣΔ-modulator (and therefore the same multiplexer and PGA settings as
ADC1y) but with a separate digital fast filter that works in parallel to the main ADC1y digital filter. This fast filter is
a sinc3 implementation with a fixed OSR of 64. The offset and gain calibration registers (OCAL1y[23:0],
GALC1y[15:0]) for ADC1y do not affect the OCCy comparators, means there is no user calibration of the
overcurrent comparators possible.
Enable the overcurrent comparators using the OCCy_EN bits. To use overcurrent comparator OCCy, ADC1y
must be enabled (ADC1y_EN =1b) as well so that the ADC1y modulator is active. However conversions on
ADC1y do not need to be started to use the overcurrent comparator function. The sinc3 filter of the comparator
starts operating as soon as the OCCy_EN bit is set and runs independently of the conversion state of ADC1y.
The digital fast filter of the comparator outputs 16-bit conversion results that are internally compared against a
high and low threshold, configured by the OCCy_HIGH_TH[15:0] and OCCy_LOW_TH[15:0] register bits,
respectively. The comparator triggers when the conversion results exceed the high threshold or when the results
fall below the low threshold. Set OCCy_HIGH_TH[15:0] = 7FFFh to disable the high threshold detection.
Similarly, set OCCy_LOW_TH[15:0] = 8000h to disable the low threshold detection.
OCCy_NUM[4:0] configures the number of conversions that the output of the digital fast filter must exceed the
programmed high or low threshold before flagging an overcurrent condition in the OCCy_HTn or OCCy_LTn
status bits, respectively. An internal counter keeps track of the number of conversions that exceed either the high
or low threshold. The counter resets as soon as one conversion result drops below the threshold again or when
the OCCy comparator is disabled (OCCy_EN = 0b).
Disable the overcurrent comparator (OCCy_EN = 0b) before changing any of the comparator settings in the
OCCy_CFG, OCCy_HIGH_THRESHOLD, or OCCy_LOW_THRESHOLD registers.
Similar to the detailed ADC, supply, and digital status flags, the detailed status flags in the OCC_STATUS
register feed a combined OCC_FAULTn flag in the STATUS_MSB register. That is, if any of the fault flags in the
OCC_STATUS register set to 0b, then the OCC_FAULTn flag sets to 0b as well.
To clear a set OCC_FAULTn flag to 1b after the overcurrent condition has been removed, the host must first
clear all set fault flags in the OCC_STATUS register. Only after all fault flags in the OCC_STATUS register are
cleared to 1b can the host clear the OCC_FAULTn flag by writing 1b.
The ADS131B23 allows additional masking of the four fault flags located in the OCC_STATUS register from
triggering the combined OCC_FAULTn flag in the STATUS_MSB register. The masking bits are located in the
OCC_FAULT_MASK register. In case a fault flag in the OCC_STATUS register is masked, then a fault indicated
by this masked fault flag does not trigger the OCC_FAULTn flag in the STATUS_MSB register. However the fault
is still indicated by the fault flag in the OCC_STATUS register.
8.3.8.15.1 OCCA and OCCB Pins
Each comparator can be configured to drive a dedicated overcurrent comparator fault pin (OCCA and OCCB
pins) for fast overcurrent indication without SPI communication. To configure GPIO3/OCCA for overcurrent
comparator output, set GPIO3_DIR = 1b for digital output function and GPIO3_SRC = 0b for OCCA output.
Equivalently, set GPIO4_DIR = 1b and GPIO4_SRC = 0b to configure GPIO4/OCCB for overcurrent comparator
B output.
The OCCy pins indicate a fault when either the OCCy_HTn or OCCy_LTn bits, or both set to 0b. The mask bits
in the OCC_FAULT_MASK register do not affect the output of the OCCy pins.
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The actual output signal of the OCCy pins when active or inactive is configured in the same way as the FAULT
pin. Use the GPIO3_FMT and OCCA_POL bits to configure the output behavior of the OCCA pin, and the
GPIO4_FMT and OCCB_POL bits to configure the OCCB pin behavior.
8.3.8.15.2 Overcurrent Indication Response Time
The fault indication response time to an overcurrent event depends on the amount of overshoot of the input
signal beyond the comparator threshold. The reason for this dependency is the settling time of the sinc3 filter
that is used for the digital comparator function.
图8-14 and 图8-15 show two examples for the OCCA fault indication behavior with OCCA_NUM[4:0] = 00000b,
that is only one conversion must exceed the threshold to trigger a fault. In 图8-14 the comparator triggers in less
than 64/fMOD (= 15.6 μs when using fMCLK = 8.192 MHz) because the sinc3 filter already settles to a value
above the set high threshold in one conversion due to the large overshoot beyond the high threshold on the
input signal. 图 8-15 shows a worst case scenario where the sinc3 filter needs even four conversion periods to
settle to a value above the set high threshold because the input signal barely exceeds the high threshold and the
overcurrent event happens in the middle of a fast filter conversion cycle.
VCPA – VCNA
OCCA High Threshold
OCCA Sinc3
Filter Output
OCCA High Threshold
Sinc3 Filter
Conversion Period
64/fMOD
OCCA_HTn
Status Flag
Response
Time
图8-14. OCCA Behavior With Large Input Overshoot
OCCA High Threshold
VCPA – VCNA
OCCA High Threshold
OCCA Sinc3
Filter Output
Sinc3 Filter
Conversion Period
64/fMOD
OCCA_HTn
Status Flag
Response Time
图8-15. OCCA Behavior With Small Input Overshoot
The response time changes when global-chop mode of ADC1y is enabled and ADC1y is converting. See the
Overcurrent Indication Response Time in Global-Chop Mode section for details.
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8.3.8.16 Missing Host Detection and MHD Pin
The ADS131B23 offers a missing host detection (MHD) monitor that detects when the host is not communicating
with the device anymore. A watchdog timer checks the time between two SPI frames with valid commands
including valid CRCs. If a valid command with a valid CRC is not received within the watchdog time window, the
host is considered missing. There is no monitor fault flag that indicates a missing host, only the MHD pin is used
to detect this fault.
To use the missing host detection mode, configure the GPIO0/MHD pin as output (GPIO0_DIR = 1b) and the
GPIO0 source for missing host detection mode (GPIO0_SRC = 0b). When the watchdog times out, the MHD pin
is set active. Enable the missing host detection mode by setting the MHD_CFG[1:0] bits to one of the three
available watchdog timeout windows. To reset the MHD output after a missing host was detected, disable the
missing host detection mode by setting MHD_CFG = 00b.
The actual output signal of the MHD pin when active or inactive depends on the GPIO0 format (GPIO0_FMT bit)
and MHD pin polarity (MHD_POL bit) configuration. See the respective bit descriptions and the General-Purpose
Digital Inputs and Outputs (GPIO0 to GPIO4) section for details. 表 8-20 shows an example where the MHD pin
is configured for a static low signal in an active state, and a static high signal in an inactive state. The pin can for
example also be configured for a static low signal in an active state, and a PWM output signal with 50% duty
cycle in an inactive state to act as some sort of heart beat signal as long as the device detects a valid host.
表8-20. MHD Pin Output Behavior Configuration Example
REGISTER BIT
GPIO0_DIR
GPIO0_SRC
GPIO0_FMT
MHD_POL
BIT SETTING
DESCRIPTION
1b
0b
0b
0b
GPIO0/MHD pin configured as digital output
MHD selected as data source for GPIO0/MHD pin
GPIO0/MHD pin configured for static output levels
MHD output is active low
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8.4 Device Functional Modes
8.4.1 Power-Up and Reset
The ADS131B23 is reset in one three ways:
• Power-on reset (POR)
• RESETn pin (hardware reset)
• RESET command (software reset)
After a reset occurs, the user registers reset to the respective default settings and the device is in active mode.
All ADCs are enabled, but no conversions are started. With all three reset options, a low-to-high transition on the
DRDYn pin indicates that the SPI interface is ready for communication. The device ignores any SPI
communication before this point and SDO stays low.
8.4.1.1 Power-On Reset (POR)
Power-on reset (POR) is the reset that occurs when valid supply voltages are first applied to the device. The
POR process requires tPOR to complete from when the supply voltages reach 90% of the nominal value to allow
for the internal circuitry to power up. The DRDYn pin transitions from low to high immediately after tPOR
,
indicating the SPI interface is ready for communication.
8.4.1.2 RESETn Pin
The RESETn pin is an active low pin with an internal pulldown resistor to DGND. The device resets if the pin is
held low for longer than tw(RSL) and maintains a reset state until the RESETn pin is returned high. The host must
actively drive the pin high for the device to operate. Wait for at least tREGACQ after the RESETn pin is brought
high or for the DRDYn rising edge before communicating with the device.
8.4.1.3 RESET Command
The ADS131B23 can be reset with the SPI RESET command. See the RESET section for details. A device reset
occurs immediately after the RESET command is latched. The host must wait for at least tREGACQ or for the
DRDYn rising edge before communicating with the device.
8.4.2 Operating Modes
The ADS131B23 offers three operating modes: active, standby, and power-down mode. The mode is
programmable using the OP_MODE[1:0] bits. 图 8-16 shows how the device transitions between the different
operating modes.
OP_MODE[1:0] = 1xb
OP_MODE[1:0] = 01b
OP_MODE[1:0] = 00b
OP_MODE[1:0] = 1xb
OP_MODE[1:0] = 01b
Power-up
or
Reset
Active
Mode
Standby
Mode
Power-down
Mode
OP_MODE[1:0] = 00b
图8-16. Operating Mode State Diagram
8.4.2.1 Active Mode
Active mode is the default operating mode after power-up or reset. In active mode all internal circuitry is powered
up. By default all ADCs are enabled, but no conversions are started. The individual ADCs can be enabled or
disabled using the respective ADCxy_EN bits. ADC conversions can only be started in active mode and when
the respective ADC is enabled.
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8.4.2.2 Standby Mode
In standby mode all internal circuitry is powered up, but all ADCs are disabled and ongoing conversions are
stopped immediately irrespective of the ADCxy_EN bit settings. No ADC conversions can be started in standby
mode. Transition the device to standby mode before changing the main clock source using the CLK_SOURCE
bit to prevent clock glitching during the clock switchover.
8.4.2.3 Power-Down Mode
In power-down mode, all nonessential internal circuitry (such as the ADCs, voltage references, and oscillators) is
powered down. The LDOs and POR circuitry stay active. Register settings are retained in power-down mode. All
ADCs are disabled and ongoing conversions are stopped immediately irrespective of the ADCxy_EN bit settings.
No conversions can be started in power-down mode. When transitioning to active mode, wait for the voltage
reference start-up time before starting any conversions to allow the voltage references to power up.
8.4.3 ADC Conversion Modes
8.4.3.1 ADC1y Conversion Modes
The ADS131B23 offers two conversion modes for ADCs ADC1y: continuous-conversion and single-shot
conversion mode.
The CONV_MODE1A bit selects the conversion mode for ADC1y.
Do not change the contents of the following registers while conversions on ADC1y are ongoing: ADC1y_CFG,
ADC1y_OCAL_MSB, ADC1y_OCAL_LSB, and ADC1y_GCAL. Stop conversions or disable ADC1y before
making changes to these registers.
8.4.3.1.1 Continuous-Conversion Mode
In continuous-conversion mode, ADC1y converts indefinitely until stopped by the host. Set the respective
STARTy bits in the CONVERSION_CTRL register to start conversions of the enabled ADC, ADC1y. Conversions
on ADC1A and ADC1B can be started at different times using the respective STARTA and STARTB bits. Setting
the STARTy bit while conversions are ongoing on an ADC aborts the ongoing conversion and restarts
conversions. Use the STOPy bits to stop conversions of the enabled ADC, ADC1y. The currently ongoing
conversion is allowed to finish after the STOPy bit is set and the digital filter is held in reset thereafter. After
setting the STOPy bits, the STOPy bits read back 1b until conversions are stopped.
The STARTy bits take priority over the STOPy bits. That means if both the STARTy and STOPy bits in the
CONVERSION_CTRL register are set at the same time, then conversions are started or ongoing conversions
are aborted and new conversions are started.
The last conversion result of an ADC is still available for readout after conversions are stopped. The conversion
results of an ADC are only cleared after a device reset, when the ADC is disabled, when the device is in standby
or power-down mode, or are overwritten when a new conversion result becomes available.
The STARTy bits take effect and conversions start at the last SCLK falling edge of the register data CRC word
within the SPI frame where the CONVERSION_CTRL register is written. See the Serial Interface Communication
Structure section for details on the SPI frame of a register write command.
Setting the STARTy bit drives the DRDYn pin high in case DRDYn was low, however the old conversion data can
still be read until the new conversions become available.
ADC1y use a sinc3 digital filter that requires three conversion periods to settle. When conversions are started or
restarted using the STARTy bits, the device hides the first two unsettled conversions and only provides a settled
conversion result after the third conversion period. Use 方程式 18 to calculate the time until the first conversion
after a conversion start is available. All subsequent conversions have a conversion period, as illustrated in 图
8-17, of tDATA = 1/fDATA = OSR / fMOD
.
tSETTLE = (3 × OSR + 44) × tMOD
(18)
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Start of
new conversions
DRDYn
tSETTLE
tDATA
tDATA
图8-17. Sinc3 Filter Settling Time and Conversion Period
The ADC does not detect when a sudden step change on the analog input occurs while the ADC is continuously
converting. Therefore, the ADC continues to output conversion data at the programmed output data rate. If the
step change occurs concurrently with the start of a new conversion period, then settled data are output three
conversion periods after the step change. However, the sinc3 filter takes four conversion periods to provide
settled data, as shown in 图8-18, if the step change occurs in the middle of a conversion period.
Analog Input
Fully Settled Data
ADC Output
DRDYn
tDATA
图8-18. SINC3 Filter Behavior During Input Step Change
8.4.3.1.2 Single-Shot Conversion Mode
In single-shot conversion mode, ADC ADC1y performs one single conversion after the STARTy bit is set. Setting
the STARTy bit while a conversion is ongoing on an ADC aborts the ongoing conversion and restarts a single
new conversion. The STOPy bits have no effect in single-shot conversion mode.
Equivalent to continuous-conversion mode, the STARTy bits take effect and conversions start at the last SCLK
falling edge of the register data CRC word within the SPI frame where the CONVERSION_CTRL register is
written.
Every conversion in single-shot conversion mode is available after the first-conversion settling time as calculated
by 方程式 18. If an input step change occurs during the conversion process, the conversion result is not fully
settled. Another subsequent single-shot conversion is required in that case to output a settled conversion result.
8.4.3.1.3 Global-Chop Mode
The signal chain of ADC1y uses a very low-drift, chopper-stabilized PGA and ΣΔ-modulator to provide very low
offset error and offset drift. However, a small amount of offset drift remains in normal measurement. For that
reason, the ADC1y signal chain incorporates an optional global-chop mode to reduce offset error and offset drift
over both temperature and time to exceptionally low levels. When the global-chop mode is enabled by setting
the GC1y_EN bit, ADC1y performs two consecutive conversions with alternate input signal polarity to cancel
offset error. The first conversion is taken with normal input polarity. The global-chop control logic inverts the input
polarity and resets the digital filter for the second conversion. The average of the two conversions yields the final
corrected result, removing the offset voltage. 图 8-19 illustrates a block diagram of the ADC1y global-chop
implementation. VOFS models the combined PGA and ADC1y internal offset voltage. Only this device-inherent
offset voltage is reduced by global-chop mode. Offset in the external circuitry connected to the analog inputs is
not affected by global-chop mode.
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Global-chop Switches
within MUX1y
VOFS
CPA
Global-
chop
Control
Digital
Filter
Calibration
Logic
PGA
ADC1y
CNA
图8-19. ADC1y Global-Chop Mode Control Diagram
The operational sequence of global-chop mode is as follows:
• Conversion C1: VCPA –VCNA –VOFS →First conversion withheld after conversion start
• Conversion C2: VCNA –VCPA –VOFS →Output 1 = (VC1 –VC2) / 2 = VCPA –VCNA
• Conversion C3: VCPA –VCNA –VOFS →Output 2 = (VC3 –VC2) / 2 = VCPA –VCNA
• ...
The first conversion result (Output 1) after a conversion start is available after ADC1y takes two settled
conversions. Because of the sinc3 filter, data of one conversion settles in three conversions cycles. 方程式 19
calculates the time required to output the first conversion result after a conversion start.
In continuous-conversion mode with the global-chop mode enabled, subsequent conversions complete in
t
GC_DATA, as calculated by 方程式 20 and shown in 图 8-20. That means the data rate in global-chop mode is
approximately 1/3rd the data rate in normal mode.
tGC_SETTLE = 2 × (tGC1y_DELAY + 3 × OSR × tMOD) + 44 tMOD
(19)
(20)
tGC_DATA = tGC1y_DELAY + 3 × OSR × tMOD
,
Before starting conversions after the input polarity is inverted, ADC1y waits the global-chop delay time,
GC1y_DELAY[2:0], to allow for the internal circuitry to settle. In some cases, the programmable global-chop
delay time must be increased to allow for settling of external components.
Global-chop delay
Modulator sampling
Conversion
start
Data not
settled
Data not
settled
Swap inputs,
digital filter reset
Data not
settled
Data not
settled
Output 1
Output 2
Sampling
C1
Sampling
C1
Sampling
C1
Sampling
C2
Sampling
C2
Sampling
C2
Sampling
C3
Sampling
C3
Sampling
C3
Sampling
C4
Sampling
C4
tDATA
DRDYn
tGC_SETTLE
tGC_DATA
图8-20. Sinc3 Filter Settling Time and Conversion Period in Global-Chop Mode
Global-chop mode reduces the ADC1y noise by a factor of √2 because two conversions are averaged. Divide
the input-referred noise values in 表 7-1 by √2 to derive the noise performance when global-chop mode is
enabled.
The notches of the sinc3 filter in 图 8-3 do not change in global-chop mode. However, additional filter notches
appear at multiples of fGC_DATA / 2.
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8.4.3.1.3.1 Overcurrent Indication Response Time in Global-Chop Mode
Enabling global-chop mode of ADC1y changes the overcurrent detection behavior of OCCy when ADC1y is
converting. The OCCy digital fast filter resets each time ADC1y inverts the polarity of the analog inputs. After
every fast filter reset, the device ignores the first two conversions of the OCCy filter because these conversions
are unsettled. The device does not increment the OCCy_NUM counter for these two conversions. Depending on
the OCCy_NUM and OSR1y settings, the overcurrent indication response time in global-chop mode can
therefore be longer compared to when global-chop mode is disabled. The difference in response time is most
noticeable when using large OCCy_NUM and small OSR1y settings.
图 8-21 shows an example of the OCCy behavior with OSR1y = 32. The OCCy DRDYn signal indicates when
conversion of the OCCy fast filter completes. This signal is internal only and is not accessible by the host. In this
specific example, the OCCy_NUM counter only manages to increment four times per ADC1y data period. If
OCCy_NUM = 8, then the OCCy fast filter resets two times before the OCCy_NUM counter reaches 8. The
approximate overcurrent indication response time is calculated as (8 + (2 × 2)) × 64/fMOD = 12 × 64/fMOD
.
First two conversions
OCCy digital
filter resets.
after OCCy digital filter
reset are ignored.
64/fMOD
OCCy DRDYn (internal)
OCCy_NUM Count
...
1
2
3
4
5
6
7
8
tGC_DATA
32/fMOD
ADC1y DRDYn
...
Overcurrent event
occurrence
ADC1y input polarity changes,
ADC1y digital filter resets.
Internally hidden conversions
of ADC1y digital filter.
图8-21. Overcurrent Detection Behavior with Global-Chop Mode Enabled (ADC1y OSR = 32)
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8.4.3.2 ADC2y Sequencer Operation and Sequence Modes
In contrast to ADC1y, conversions on ADC2y are controlled by means of a channel sequencer. 图8-22 depicts a
flow chart of the sequencer operation. The ADC2y sequencer has up to 16 sequence steps that are individually
enabled or disabled using the SEQ2y_STEPn_EN bits (n = 0 to 15). Each sequence step corresponds to one
single conversion of ADC2y, which means up to 16 different measurements can be taken in one sequence run.
The SEQ2y_STEPn_CFG registers configure the PGA gain, and the positive and negative input for the PGA for
every sequence step. When a sequence is started, the sequencer steps through all enabled sequence steps,
always starting with step 0. The sequencer ignores sequence steps that are disabled. One conversion is taken
by ADC2y in each step before the sequencer configures ADC2y for the next step in the sequence. After the
sequencer configures ADC2y for the next sequence step, the sequencer adds a programmable delay before
starting the conversion to allow for settling of the input signal. The MUX2y_DELAY[2:0] bits select the delay time
globally for all sequence steps. The time required to complete a sequence is given by 方程式21:
tSEQ = N × (tMUX_DELAY + tCONVERSION
)
(21)
where:
• N is the number of enabled steps
• tMUX_DELAY is the multiplexer delay time
• tCONVERSION is the conversion time of ADC2y
While a sequence is ongoing, the SEQ2y_ACTIVE bit is set in the STATUS register.
Do not make any changes to registers in the address range from 0x8C to 0x9F while ADC2A is enabled. Follow
the following procedure to configure and start the sequencer to avoid false sequencer starts:
1. Disable ADC2y by setting ADC2y_EN = 0b, or alternatively put the device into standby mode
2. Configure the ADC2y sequencer register bits
3. Enable ADC2y by setting ADC2y_EN = 1b, or alternatively put the device back into active mode
4. Start the sequence by setting the SEQ2y_START bit
Setting the SEQ2y_START bit while ADC2y is disabled does not start a sequence.
Conversion data for the sequence steps of ADC2y are 16 bits and (in contrast to ADC1y conversion data) are
stored in the user register space (register addresses 10h to 1Fh). The conversion data for sequence step n are
stored in the corresponding SEQ2y_STEPn_DATA register. Conversion data for a sequence step that is disabled
are set to 0000h. Read ADC2y conversion data using the register read command.
The conversion data of all SEQ2y_STEPn_DATA registers only update when a sequence run of ADC2y
completes. While a sequence run is ongoing, the conversion data of the previous sequence run are read from
the SEQ2y_STEPn_DATA registers. There is no data corruption or mix of data from two different sequence runs,
even when a sequence completes while the SEQ2y_STEPn_DATA registers are read.
The ADC2y sequencer offers three sequence modes:
• Continuous sequence mode
• Single-shot sequence mode
• Synchronized single-shot sequence mode based on ADC1y conversion starts
The SEQ2y_MODE[1:0] bits select the sequence mode for ADC2y.
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No
Bit
SEQ2y_START
= 1b ?
Yes
Start Sequence
Configure ADC2y
based on
SEQ2y_STEP0_CFG
register settings
Yes
Wait
Store conversion data for
Start ADC2y
conversion
Step 0
enabled?
MUX2y_DELAY[2:0]
time
step 0 in shadow register
after conversion completed
No
Configure ADC2y
based on
SEQ2y_STEP1_CFG
register settings
Yes
Wait
MUX2y_DELAY[2:0]
time
Store conversion data for
step 1 in shadow register
after conversion completed
Step 1
enabled?
Start ADC2y
conversion
No
Configure ADC2y
based on
SEQ2y_STEP15_CFG
register settings
Yes
Wait
MUX2y_DELAY[2:0]
time
Store conversion data for
step 15 in shadow register
after conversion completed
Step 15
enabled?
Start ADC2y
conversion
No
Any of the
Yes
SEQ2y_STEPn_DATA
registers currently
output on SDO?
This process runs in the background. It does not prevent
the sequencer from starting a new sequence run.
No
Copy all conversion data from
shadow registers to
Data from disabled steps are set to 0000h.
SEQ2y_STEPn_DATA registers
Increment sequence counter
SEQ2y_COUNT[1:0]
No
Yes
Bit
Continuous
Sequence Mode?
SEQ2y_STOP
= 1b ?
Yes
No
Stop Sequence
图8-22. ADC2y Sequencer Flow Chart
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8.4.3.2.1 Continuous Sequence Mode
In continuous sequence mode, the ADC2y sequencer runs through the configured sequence over and over
again until stopped by the host. Set the respective SEQ2y_START bit in the CONVERSION_CTRL register to
start the sequencer of ADC2y. Setting the SEQ2y_START bit while the sequencer is running aborts the ongoing
sequence run and restarts a new sequence run from the beginning. Use the SEQ2y_STOP bit to stop the
sequencer of ADC2y. The currently ongoing sequence run is allowed to finish after the SEQ2y_STOP bit is set.
After setting the SEQ2y_STOP bit, the SEQ2y_STOP bit reads back 1b until the sequencer stopped. Disabling
ADC2y or putting the device into standby or power-down mode aborts the sequence run immediately.
The SEQ2y_START bits take priority over the SEQ2y_STOP bits. That means if both the SEQ2y_START and
SEQ2y_STOP bits in the CONVERSION_CTRL register are set at the same time, then the sequencer starts a
sequence run or aborts an ongoing sequence run and starts a new sequence run from the beginning.
The last conversion results of an ADC2y sequence run are still available for readout after the sequencer
stopped. The conversion results of the sequencer are only cleared to 0000h after a device reset, when the ADC
is disabled, when the device is in standby or power-down mode, or are overwritten when conversion results from
a new sequence run become available.
8.4.3.2.2 Single-Shot Sequence Mode
In single-shot sequence mode the ADC2y sequencer runs through the configured sequence one time after the
SEQ2y_START bit is set. Setting the SEQ2y_START bit while a sequence is ongoing aborts the ongoing
sequence and restarts a single new sequence run from the beginning. The SEQ2y_STOP bit has no effect in
single-shot sequence mode.
8.4.3.2.3 Synchronized Single-Shot Sequence Mode Based on ADC1y Conversion Starts
The synchronized sequence mode allows the sequence starts of ADC2A to be synchronized with the conversion
starts of ADC1A. In this mode a single sequence run is started on ADC2y whenever a new conversion on
ADC1y starts. However, an ongoing sequence run on ADC2y does not abort and restart when a new conversion
on ADC1y starts. This means a single new sequence run on ADC2y is only triggered by ADC1y when no
sequence is currently ongoing.
Start the ADC2y sequencer initially by setting the SEQ2y_START bit.
The synchronized single-shot sequence mode is only useful when ADC1y is configured for continuous-
conversion mode. When ADC1y is configured for single-shot conversion mode, synchronize conversions of
ADC1y and sequence starts of ADC2y by setting the STARTy and SEQy_START bits at the same time.
图 8-23 shows an example of how ADC1A conversions and ADC2A sequence starts are synchronized. The
falling edge of the internally generated DRDYAn signal in 图 8-23 indicates when new ADC1A conversions
results are available and a new ADC1A conversion starts.
ADC1A STARTA bit set.
ADC2A SEQ2A_START bit set.
New ADC2A sequence starts at
ADC1A DRDYAn falling edge
No new ADC2A sequence starts
because a sequence is ongoing
Internal DRDYAn
Conversion 1
(unsettled)
Conversion 2
(unsettled)
Conversion 3
(settled)
Conversion 4
(settled)
Conversion 5
(settled)
Conversion 6
(settled)
Conversion 7
(settled)
ADC1A
ADC2A
Sequence 1
Sequence 2
Sequence 3
图8-23. Synchronizing ADC1A Conversions and ADC2A Sequence Starts
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8.5 Programming
8.5.1 Serial Interface
The ADS131B23 uses an SPI-compatible interface to configure the device and retrieve conversion data. The
device always acts as an SPI peripheral; SCLK and CSn are inputs to the interface. The interface operates in
SPI mode 1 where CPOL = 0 and CPHA = 1. In SPI mode 1, SCLK idles low and data are launched or changed
only on SCLK rising edges; data are latched or read by the controller and peripheral on SCLK falling edges. The
interface is full-duplex, meaning data can be sent and received simultaneously by the interface. The device
includes the typical SPI signals: CSn, SCLK, SDI, and SDO. In addition, the DRDYn pin serves as a flag to the
host to indicate new conversion data are available.
8.5.1.1 Serial Interface Signals
8.5.1.1.1 Chip Select (CSn)
The CSn pin is an active low input signal that selects the device for communication. The device ignores any
communication and SDO is high impedance when CSn is held high. Hold CSn low for the duration of a
communication frame to ensure proper communication. The interface is reset each time CSn is taken high.
8.5.1.1.2 Serial Data Clock (SCLK)
The SCLK pin is an input that serves as the serial clock for the interface. Output data on SDO transition on the
rising edge of SCLK and input data on SDI are latched on the falling edge of SCLK.
8.5.1.1.3 Serial Data Input (SDI)
The SDI pin is the serial data input pin for the device. Serial commands are shifted in through the SDI pin by the
device with each SCLK falling edge when the CSn pin is low.
8.5.1.1.4 Serial Data Output (SDO)
The SDO pin is the serial data output pin for the device. The device shifts out data serially with each rising SCLK
edge when the CSn pin is low. This pin assumes a high-impedance state when CSn is high. When CSn
transitions low, the SDO pin drives low.
SDO stays at the level of the last bit sent if the host does not send any extra SCLK pulses after the last data is
shifted out on SDO. If the host sends additional SCLK pulses after the last data is shifted out, then SDO drives
low. 图 8-24 and 图 8-25 show timing diagrams of the SDO behavior both without and with additional SCLK
pulses, respectively.
CSn
SCLK
SDO
CSn
SCLK
SDO
LSB
LSB
图8-24. SDO Behavior Without Additional SCLK
图8-25. SDO Behavior With Additional SCLK
Pulses
Pulses
8.5.1.1.5 Data Ready (DRDYn)
The DRDYn pin is an active-low, push-pull output. A DRDYn falling edge indicates when new conversion data of
ADC1A or ADC1B are available for readout. The DRDY_CTRL bit selects which ADC drives the DRDYn signal,
either ADC1A or ADC1B. If the host starts ADC1A and ADC1B conversions at the same time by setting both the
STARTA and STARTB bits during the same CONVERSION_CTRL register write, conversions of both ADCs
complete at the same time. The period between DRDYn falling edges is the data rate period of the ADC that
controls the DRDYn pin.
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During device power-up or while the device is held in reset, the DRDYn pin drives low. As shown in 图 8-26 and
图8-27, the DRDYn pin drives high after the POR is released and the device is ready for communication.
POR reset time (tPOR
)
90%
Supplies
CSn
SDI
COMMAND
STATUS
Command CRC
ADC1A Data
SDO
High-Z
ADC1B Data
DRDYn
DRDYn transitions high to indicate
device is ready for communication.
Conversion data are all zeros in the first
frame following a device reset.
RESETn bit in STATUS register sets to 0b.
All counters reset.
COMMAND_RESPONSE[3:0] indicates that
this is the first frame after power-up or reset
and that a NULL command is executed.
图8-26. DRDYn Pin Behavior After POR
Reset is released here
Device reset happens here
Reset time (tREGACQ
)
RESETn
CSn
SDI
COMMAND
STATUS
Command CRC
SDO
High-Z
ADC1A Data
ADC1B Data
DRDYn
DRDYn transitions high to indicate
device is ready for communication.
Conversion data are all zeros in the first
frame following a device reset.
RESETn bit in STATUS register sets to 0b.
All counters reset.
COMMAND_RESPONSE[3:0] indicates that
this is the first frame after power-up or reset
and that a NULL command is executed.
图8-27. DRDYn Pin Behavior After Device Reset
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8.5.1.2 Serial Interface Communication Structure
8.5.1.2.1 SPI Communication Frames
SPI communication on the ADS131B23 is performed in frames. Each SPI communication frame starts with a
CSn falling edge, consists of several words, and ends with a CSn rising edge. The interface is full duplex,
meaning that the interface is capable of transmitting data on SDO while simultaneously receiving data on SDI. 图
8-28 provides an overview of the general SPI frame structure and frame length for the various commands.
The input frame that the host sends on SDI always begins with a command word followed by a command CRC
word. The first word on the output frame that the device transmits on SDO always begins with the STATUS word.
The number of words in a frame depends on the command provided. See the Commands section for a list of all
valid commands on the ADS131B23.
For the NULL, RESET, LOCK, UNLOCK, and RREG commands there are four words in a frame. On SDI, the
host provides the command, the command CRC, and two additional words of zeros. Simultaneously on SDO, the
device outputs the STATUS word, two words of ADC data (representing the data from ADC1A and ADC1B), and
an output CRC word. 图 8-28 shows a typical communication frame structure. In the remaining sections of this
document the SCLK signal is omitted in the figures for clarity.
CSn
SCLK
SDI
NULL
Command CRC
ADC1A Data
SDO
High-Z
STATUS
ADC1B Data
Output CRC
High-Z
图8-28. Typical Communication Frame
In the case of a write register (WREG) command where more than one register is written, the frame extends to
accommodate the additional data. See the WREG section for more details on the WREG command.
In the case of a read register (RREG) command the response to the command in the following frame contains
the STATUS word followed by the register data requested, which can require a shorter or longer frame
depending on how many registers are read. See the RREG section for more details on the RREG command.
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8.5.1.2.2 SPI Communication Words
An SPI communication frame of the ADS131B23 is made of multiple words. The word size is configurable as
either 24 bits, or 32 bits using the WORD_LENGTH bit in the DEVICE_CFG register. The content within each
word is always most significant bit (MSB) aligned and least significant bit (LSB) padded with zeros to
accommodate 24-bit or 32-bit word sizes. 表8-21 provides an overview of all available word types and the actual
unpadded data length of the respective content.
表8-21. Unpadded Data Length of Individual Word Types
DIRECTION
SDI
WORD TYPE
UNPADDED DATA LENGTH
Command
16 bits
SDI
Command CRC
16 bits
SDI
Register data for WREG command
Register data CRC for WREG command
STATUS
16 bits
SDI
16 bits
SDO
SDO
SDO
SDO
24 bits
ADC1A and ADC1B conversion data
Register data for RREG command
Output CRC
24 bits
16 bits register data + 8 bits register address
16 bits
图 8-29 and 图 8-30 show the bit alignments and zero padding within the individual words for a WREG and
RREG command, respectively.
CSn
SDI
WREG
Command CRC
REG Data 0
Register Data CRC
Output CRC
23
23
8
8
0
0
23
23
8
0
0
23
23
8
0
0
23
8
8
0
0
SDO
STATUS
ADC1A Data
ADC1B Data
23
图8-29. Bit Alignment, 24-Bit Word Size, WREG Command
CSn
SDI
RREG
Command CRC
23
23
8
8
0
0
23
23
8
0
0
SDO
STATUS
ADC1A Data
ADC1B Data
Output CRC
23
0
23
8
0
CSn
SDI
NULL
Command CRC
23
23
8
0
0
23
23
8
8
0
0
SDO
STATUS
REG Data n
ADDR
REG Data n+1
ADDR
Output CRC
23
8
0
23
8
0
图8-30. Bit Alignment, 24-Bit Word Size, RREG Command
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8.5.1.2.3 STATUS Word
The ADS131B23 outputs a STATUS word as the first word in every frame on SDO. The 24-bit STATUS word is a
concatenation of the STATUS_MSB[15:0] and STATUS_LSB[15:8] register bits. Fault flags, status flags, ADC1A
and ADC1B conversion counters, ADC2A sequence counters, and the command response are all part of these
bits. See the respective register bit descriptions in the 节8.6.1 section for details.
• Communication-related fault flags, such as the SPI_CRC_FAULTn, SPI_TIMEOUTn,
SCLK_COUNT_FAULTn, and REG_ACCESS_FAULTn flags, always indicate faults that occurred in the
previous SPI frame. These fault flags clear automatically for the next SPI frame.
• All other device-related fault and status flags indicate the state of the device at the instance of the start of the
current SPI frame.
• All fault flags, except for the communication related fault flags mentioned above, are latching. That means,
these fault flags do not reset automatically to 1b when the fault condition is removed and must be cleared by
the host.
• The command response indicates which command was received by the device in the previous SPI frame and
was executed.
• The conversion and sequence counters indicate the count of the data which is output in the current SPI
frame.
8.5.1.2.4 Communication Cyclic Redundancy Check (CRC)
The ADS131B23 features a cyclic redundancy check (CRC) engine on both input and output data to detect SPI
communication errors. Overall there are three different CRCs that are all 16 bits wide:
• On SDI: Command CRC and, in case of a WREG command, a register data CRC
• On SDO: Output CRC
The command CRC covers the command word(that is, the first word on SDI in every frame). The WREG
command is a special case that requires an additional register data CRC. The register data CRC covers the
register data words transmitted after the command CRC word. The output CRC covers all words on SDO
preceding the output CRC word. The CRCs also cover all zero-padded bits.
The device checks the provided command CRC, and (in case of a WREG command) the register data CRC
against the internally calculated CRCs based on the received input data. A CRC error occurs if the CRC words
do not match. The device does not execute any commands if the command CRC or register data CRC checks
fail. The device sets the SPI_CRC_FAULTn bit in the STATUS_MSB register for all cases of a CRC error on the
input data.
The response on the output in the SPI frame following a frame where a CRC error occurred is that of a NULL
command, which means the STATUS word plus the conversion data for ADC1A and ADC1B are output in the
following SPI frame. The SPI_CRC_FAULTn bit is output as part of the STATUS word to provide immediate
indication that a CRC error occurred in the previous frame. The SPI_CRC_FAULTn bit clears automatically in the
next SPI frame.
There are two types of CRC polynomials available: CCITT CRC and ANSI CRC (CRC-16). The CRC polynomial
setting determines the algorithm for all three CRCs. The CRC type is programmed using the CRC_TYPE bit. 表
8-22 lists the details of the two CRC types.
The CRC calculation is initialized with the seed value of FFFFh to detect errors in the event that SDI or SDO are
stuck low.
表8-22. CRC Types
CRC TYPE
CCITT CRC
ANSI CRC
POLYNOMIAL
x16 + x12 + x5 + 1
x16 + x15 + x2 + 1
BINARY POLYNOMIAL
0001 0000 0010 0001
1000 0000 0000 0101
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8.5.1.2.5 Commands
表 8-23 contains a list of all valid commands, a short description of the command functionality, and the binary
command word.
表8-23. Command Definitions
COMMAND
NULL
DESCRIPTION
COMMAND WORD
0000 0000 0000 0000b
0000 0000 0001 0001b
No operation
RESET
Reset the device
Lock the interface such that only the NULL, UNLOCK, and RREG
commands are valid
LOCK
0000 0101 0101 0101b
UNLOCK
WREG
RREG
Unlock the interface after the interface is locked
0000 0110 0101 0101b
011a aaaa aaa0 0nnnb
101a aaaa aaan nnnnb
Write nnn plus 1 registers beginning at address a aaaa aaa
Read n nnnn plus 1 registers beginning at address a aaaa aaa
8.5.1.2.5.1 NULL (0000 0000 0000 0000b)
The NULL command is the no-operation command that results in no registers being read or written, and the
state of the device remains unchanged. The intended use case for the NULL command is to read out conversion
data for ADC1A and ADC1B.
The command response in the next frame indicates if an error occurred during the transmission of the NULL
command frame. However, a NULL command is executed regardless if an error occurred or not.
图8-31 shows a typical NULL command frame where no faults occurred during the communication.
CSn
SDI
NULL
Command CRC
ADC1A Data
Command
STATUS
Command CRC
ADC1A Data
SDO
STATUS
ADC1B Data
Output CRC
ADC1B Data
Output CRC
COMMAND_RESPONSE[3:0] = 0001b
indicates that a NULL command was
received in the previous frame
Conversion data for ADC1A and ADC1B are
output as response to a NULL command.
图8-31. NULL Command Frame
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8.5.1.2.5.2 RESET (0000 0000 0001 0001b)
The RESET command resets the device and sets all user registers to the respective default values. The
command is latched by the device at the last SCLK falling edge of the output CRC word. Terminating the frame
before the output CRC word is shifted out on SDO causes the RESET command to be ignored. A reset occurs
immediately after the command is latched. The DRDYn pin transitions low at the same instance. The host must
wait for tREGACQ after reset or for the DRDYn rising edge to ensure the device completed the reset process
before communicating with the device.
The RESETn status bit and the command response in the next frame indicate if the RESET command executed
successfully or if an error occurred that prevented the RESET command from executing. A NULL command is
executed in case the RESET command did not execute.
图8-32 shows a RESET command frame where no faults occurred during the communication.
Device reset happens at the last SCLK
falling edge of the output CRC word.
DRDYn transitions high to indicate
device is ready for communication.
CSn
SDI
RESET
Command CRC
ADC1A Data
Command
STATUS
Command CRC
ADC1A Data
SDO
STATUS
ADC1B Data
Output CRC
High-Z
ADC1B Data
Output CRC
DRDYn
Reset time (tREGACQ
)
RESETn bit in STATUS register sets to 0b.
All counters reset.
COMMAND_RESPONSE[3:0] = 1001b
indicates that this is the first frame after power-up
or reset and that a NULL command is executed.
Conversion data for ADC1A and ADC1B
which are all zero are output in the first
frame following a device reset.
图8-32. RESET Command Frame
8.5.1.2.5.3 LOCK (0000 0101 0101 0101b)
The LOCK command locks the interface, preventing the device from accidentally latching unwanted commands
that can change the state of the device. When the interface is locked, the device only responds to the NULL,
RREG, and UNLOCK commands. The device continues to output conversion data even when locked.
The LOCK status bit and the command response in the next frame indicate if the LOCK command executed
successfully or if an error occurred that prevented the LOCK command from executing. A NULL command is
executed in case the LOCK command did not execute.
图8-33 shows a LOCK command frame where no faults occurred during the communication.
CSn
SDI
LOCK
Command CRC
ADC1A Data
Command
STATUS
Command CRC
ADC1A Data
SDO
STATUS
ADC1B Data
Output CRC
ADC1B Data
Output CRC
LOCK bit in STATUS register is set.
COMMAND_RESPONSE[3:0] = 0010b
indicates that a LOCK command was
received in the previous frame.
Conversion data for ADC1A and ADC1B are
output as response to a LOCK command.
图8-33. LOCK Command Frame
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8.5.1.2.5.4 UNLOCK (0000 0110 0101 0101b)
The UNLOCK command unlocks the interface if previously locked by the LOCK command.
The LOCK status bit and the command response in the next frame indicate if the UNLOCK command executed
successfully or if an error occurred that prevented the UNLOCK command from executing. A NULL command is
executed in case the UNLOCK command did not execute.
图8-34 shows an UNLOCK command frame where no faults occurred during the communication.
CSn
SDI
UNLOCK
STATUS
Command CRC
ADC1A Data
Command
STATUS
Command CRC
ADC1A Data
SDO
ADC1B Data
Output CRC
ADC1B Data
Output CRC
LOCK bit in STATUS register is cleared.
COMMAND_RESPONSE[3:0] = 0011b
indicates that an UNLOCK command
was received in the previous frame.
Conversion data for ADC1A and ADC1B are
output as response to an UNLOCK command.
图8-34. UNLOCK Command Frame
8.5.1.2.5.5 WREG (011a aaaa aaa0 0nnnb)
The WREG command is used to write the device registers. The binary format of the command word is 011a
aaaa aaa0 0nnn, where a aaaa aaa is the binary address of the register to begin writing to and nnn is the
unsigned binary number of consecutive registers to write minus one. Send the register data to be written
immediately following the WREG command CRC word. Write the intended contents of each register into
individual words, MSB aligned. Follow the register data words with the register data CRC word that covers the
register data content.
The device prevents register data writes if the command CRC or register data CRC fail. The command response
in the next frame indicates if the WREG command executed successfully or if an error occurred that prevented
the WREG command from executing. A NULL command is executed in case the WREG command did not
execute.
图 8-35 shows a WREG command frame for a single register write where no faults occurred during the
communication.
CSn
SDI
WREG
Command CRC
ADC1A Data
REG Data 0
ADC1B Data
REG Data CRC
Output CRC
Command
STATUS
Command CRC
ADC1A Data
SDO
STATUS
ADC1B Data
Output CRC
COMMAND_RESPONSE[3:0] = 0110b
indicates that a WREG command was
received in the previous frame and the
register data updated.
Conversion data for ADC1A and ADC1B are
output as response to a WREG command.
图8-35. WREG Command Frame (Single Register)
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图 8-36 shows a WREG command frame where the number of registers to write is larger than one and,
therefore, the frame extends beyond the regular four words.
CSn
SDI
WREG
Command CRC
ADC1A Data
REG Data 0
ADC1B Data
REG Data 1
Output CRC
REG Data 2
REG Data 3
REG Data 4
REG Data 5
REG Data CRC
SDO
STATUS
图8-36. WREG Command Frame (Six Registers)
8.5.1.2.5.6 RREG (101a aaaa aaan nnnnb)
RREG is used to read the device registers. The binary format of the command word is 101a aaaa aaan nnnn,
where a aaaa aaa is the binary address of the register to begin reading from and n nnnn is the unsigned binary
number of consecutive registers to read minus one. The device outputs the requested register data sequentially
in order of addresses in the following frame instead of the conversion data of ADC1A and ADC1B. In case more
than two registers are read, the frame extends beyond the regular four words.
Send the NULL command in the frame following the RREG command frame to shift out the register data. No
other command is accepted in the frame following the RREG command frame.
The 16-bit register data are MSB aligned within the individual words. As shown in 图8-30, the device outputs the
respective 8-bit register address following the register data within each word for traceability. When reading from
an invalid register address, the device responds with 0000h for the register data and 00h for the register
address.
The command response in the frame following the RREG command frame indicates if the RREG command
executed successfully or if an error occurred that prevented the RREG command from executing. A NULL
command is executed in case the RREG command did not execute.
图8-37 shows a RREG command frame where no faults occurred during the communication.
NULL command must be sent
in register read-back frame.
CSn
SDI
RREG
Command CRC
ADC1A Data
NULL
Command CRC
REG Data n
SDO
STATUS
ADC1B Data
Output CRC
STATUS
REG Data n+1
REG Data n+2
...
Output CRC
COMMAND_RESPONSE[3:0] = 0100b
indicates that a RREG command was
received in the previous frame and
register data are output in this frame.
Up to 32 registers can be read
within a single SPI frame.
图8-37. RREG Command Frame
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8.5.1.2.6 SCLK Counter
The ADS131B23 implements an SCLK counter that counts the received SCLK pulses within a frame. If the
number of received SCLK pulses does not match the number of SCLKs to complete a specific frame, then the
SCLK_COUNT_FAULTn flag is set in the following frame. Enable or disable the SCLK counter using the
SCLK_COUNTER_EN bit.
The device determines the number of SCLKs expected for a specific SPI frame at the end of the command CRC
word. Both the expected number of words to be received on SDI and the words to be transmitted on SDO are
considered in the SCLK count calculation. The larger of the two values determines the SCLK count for the frame.
For example, the SCLK count in the two frames in 图 8-35 is (4 × NWORD_LENGTH), while in 图 8-36 the SCLK
count for the frame is (9 × NWORD_LENGTH). The data word length, NWORD_LENGTH, is either 24 or 32, as
configured by the WORD_LENGTH bit.
Sending more SCLK pulses than required to complete a frame does not impact the SPI communication, however
the SCLK_COUNT_FAULTn does still set in that case to indicate that too many SCLKs were received.
Sending insufficient SCLK pulses to complete a frame does impact the SPI communication in certain situations:
• NULL command: No effect.
• RESET command: Does not execute until sufficient SCLK pulses are provided to clock out the complete
output CRC word on SDO.
• LOCK, UNLOCK, RREG commands: Do execute if at least the command and command CRC words are
received on SDI.
• WREG command: Does execute if at least the command, command CRC, register data, and register data
CRC words are received on SDI.
• DRDYn pin: The DRDYn pin only transitions high after the conversion data word for ADC1B is clocked out on
SDO. Otherwise, the device assumes the host did not receive the latest conversion data and the DRDYn pin
stays low.
8.5.1.2.7 SPI Timeout
The ADS131B23 implements an SPI timeout feature that measures the time between the CSn falling and CSn
rising edge within a frame. If the CSn rising edge does not occur within the SPI timeout period (tTIMEOUT) after
the CSn falling edge, then the SPI_TIMEOUTn flag is set in the following frame. When a timeout occurs, the rest
of the SPI frame on SDI is ignored before the rising edge of CSn. A new SPI transaction starts at the next CSn
falling edge. Enable or disable the SPI timeout using the TIMEOUT_EN bit.
If the SPI times out after a complete frame was transmitted on SDI and SDO already, then there is no impact to
the SPI communication, however the SPI_TIMEOUTn flag does still set in that case to indicate that the CSn
signal was held low for too long.
If the SPI times out before a complete frame is transmitted on SDI and SDO, then there is potential impact to the
SPI communication in certain situations:
• NULL command: No effect.
• RESET command: Does not execute until the complete output CRC word is clocked out on SDO before the
SPI times out.
• LOCK, UNLOCK, RREG commands: Do execute if at least the command and command CRC words are
received on SDI before the SPI times out.
• WREG command: Does execute if at least the command, command CRC, register data, and register data
CRC words are received on SDI before the SPI times out.
• DRDYn pin: The DRDYn pin only transitions high after the conversion data word for ADC1B is clocked out on
SDO before the SPI times out. Otherwise, the device assumes the host did not receive the latest conversion
data and the DRDYn pin stays low.
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8.5.1.2.8 Reading ADC1A, ADC1B, and ADC2A Conversion Data
Conversion data from all three ADCs of the ADS131B23 can be read within two SPI frames. Conversion data for
ADC1A and ADC1B are always output as the response to a NULL command in the following SPI frame.
Conversion data for ADC2A must be read from the user registers using the RREG command. The conversion
results for the various sequence steps of ADC2A are stored in consecutive register address locations starting at
register address 10h. The RREG command allows to read up to 32 consecutive registers within one SPI frame,
which is sufficient to read conversion data for all sequence steps of ADC2A. 图 8-38 shows an SPI frame
sequence example of how to read all ADC conversion data.
RREG command to request
conversion data for ADC2A in next
SPI frame.
CSn
SDI
RREG
Command CRC
ADC1A Data
SDO
STATUS
ADC1B Data
Output CRC
NULL command to request conversion
data for ADC1A and ADC1B in next
SPI frame.
Conversion data for ADC1A and ADC1B
are output as response to a NULL
command sent in the previous frame.
CSn
SDI
NULL
Command CRC
SDO
STATUS
ADC2A Data n
...
ADC2A Data m
Output CRC
Between one and 16 conversion results can
be read from ADC2A within one SPI frame.
图8-38. Reading Conversion Data From ADC1A, ADC1B, and ADC2A Within Two SPI Frames
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8.5.1.2.9 DRDYn Pin Behavior
This section provides details about the DRDYn pin behavior in various scenarios.
DRDYn transitions low whenever new conversion data complete on ADC1A or ADC1B, depending on which
ADC drives the DRDYn signal as configured in the DRDY_CTRL bit. If DRDYn is low when a new conversion
completes on ADC1y, DRDYn drives high tw(DRH) before the DRDYn falling edge (see 图8-40 and 图8-42).
DRDYn transitions high after the conversion data for ADC1B are retrieved on SDO (图 8-39). If CSn is driven
high before the ADC1B conversion data are retrieved, then DRDYn stays low, indicating that not all conversion
data were read (图8-40 and 图8-41).
图 8-41 shows that the same conversion data can be read multiple times until new conversions complete. The
ADC1y conversion counters indicate if the same data were read again or if new data were read.
The device avoids data corruption in case new conversions n+1 complete while conversion data n are being
read. Conversion data n+1 are held in an internal buffer until the read of conversion data n is complete. In the
following frame, conversion data n+1 are loaded into the SDO output buffer. DRDYn does not transition high
after conversion data n have been read in this case to indicate that new conversion data n+1 are available for
readout (see 图8-42).
图 8-43 illustrates that conversion data n+1 are lost in case the host does not read the data before conversions
n+2 complete. The ADC1y conversion counters are helpful in this situation to detect if the host missed reading
the intermediate conversion results.
CSn
SDI
SDO
NULL
Command CRC
ADC1A Data
NULL
Command CRC
ADC1A Data
STATUS
ADC1B Data
Output CRC
High-Z
STATUS
ADC1B Data
Output CRC
DRDYn
Conversion data n are output
Conversions n+1 complete
Conversion data n+1 are output
图8-39. DRDYn Pin Behavior: Reading All Conversion Data Before New Conversions Complete
CSn
SDI
SDO
NULL
Command CRC
ADC1A Data
NULL
Command CRC
ADC1A Data
STATUS
High-Z
STATUS
ADC1B Data
Output CRC
DRDYn
Conversion data n are output
Conversions n+1 complete
Conversion data n+1 are output
DRDYn does not transition high because
not all conversion data were read.
图8-40. DRDYn Pin Behavior: Incomplete Read of Conversion Data Before New Conversions Complete
CSn
SDI
SDO
NULL
Command CRC
ADC1A Data
NULL
Command CRC
ADC1A Data
STATUS
High-Z
STATUS
ADC1B Data
Output CRC
DRDYn
Conversion data n are output
Conversion data n are output
DRDYn does not transition high because
not all conversion data were read.
图8-41. DRDYn Pin Behavior: Incomplete Read of Conversion Data Followed by Complete Read of Same
Conversion Data
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Conversion data n
are not corrupted.
CSn
SDI
NULL
Command CRC
ADC1A Data
NULL
Command CRC
SDO
STATUS
ADC1B Data
Output CRC
High-Z
STATUS
ADC1A Data
ADC1B Data
Output CRC
DRDYn
Conversion data n are output
DRDYn does not transition high because
new data are available for readout.
Conversion data n+1 are output
Conversions n+1 complete
图8-42. DRDYn Pin Behavior: Reading Conversion Data While New Conversions Complete
CSn
SDI
NULL
Command CRC
ADC1A Data
NULL
Command CRC
ADC1A Data
SDO
STATUS
ADC1B Data
Output CRC
High-Z
STATUS
ADC1B Data
Output CRC
DRDYn
Conversion data n are output
Conversions n+1 complete
Conversions n+2 complete
Conversion data n+2 are output
图8-43. DRDYn Pin Behavior: Missed Reading Intermediate Conversion Results
Setting the STARTy bit drives the DRDYn pin high at the last SCLK falling edge of the register data CRC word
within the SPI frame where the CONVERSION_CTRL register is written. However, the old conversion data can
still be read until the new conversions become available. 图 8-44 shows the device behavior when setting the
STARTy bit to abort an ongoing conversion and to restart new conversions while reading out conversion data. 图
8-45 shows a scenario where new conversions complete while setting the STARTy bit and reading out
conversion data.
Aborts ongoing conversion n+1 and
restarts conversion n+1 after matching
Set ADC1y STARTy bit
Register Data CRC word is received.
CSn
SDI
WREG
Command CRC
Data 0
REG Data CRC
NULL
Command CRC
ADC1A Data
SDO
STATUS
ADC1A Data
ADC1B Data
Output CRC
High-Z
STATUS
ADC1B Data
Output CRC
DRDYn
Conversion data n are output
Conversions n+1 complete
Conversion data n+1 are output
图8-44. DRDYn Pin Behavior: Setting the STARTy Bit While Reading Conversion Data
Aborts ongoing conversion n+2 and
restarts conversion n+2 after matching
Set ADC1y STARTy bit
Register Data CRC word is received.
CSn
SDI
WREG
Command CRC
Data 0
REG Data CRC
NULL
REG Data CRC
ADC1A Data
SDO
STATUS
ADC1A Data
ADC1B Data
Output CRC
High-Z
STATUS
ADC1B Data
Output CRC
DRDYn
Conversion data n are output
DRDYn does not transition high because
new data are available for readout.
Conversions n+2 complete
Conversion data n+2 are output
Conversions n+1 complete
图8-45. DRDYn Pin Behavior: Setting the STARTy Bit and Reading Conversion Data While New
Conversions Complete
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8.6 Register Map
The ADS131B23 register map spans across the address space from 00h to FEh and is divided into four general
sections:
• Section 0 (address space: 00h to 1Fh): Only includes read-only bits (such as ID, status, GPIO input data,
ADC2y conversion data, and the conversion and sequence control bits)
• Section 1 (address space: 40h to 7Eh): Includes global device configuration bits that are not specific to
section A or B of the device
• Section 2 (address space: 80h to BEh): Includes device configuration bits that are specific to section A
• Section 3 (address space: C0h to FEh): Includes device configuration bits that are specific to section B
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8.6.1 Registers
表 8-24 lists the memory-mapped registers for the Registers registers. All register offset addresses not listed in
表8-24 should be considered as reserved locations and the register contents should not be modified.
表8-24. Register Map
Address
Acronym
Reset
Bit 15
Bit 7
Bit 14
Bit 6
Bit 13
Bit 12
Bit 11
Bit 3
Bit 10
Bit 2
Bit 9
Bit 1
Bit 8
Bit 0
Bit 5
Bit 4
SECTION 0
00h
ID
X
REV[7:0]
ADC_COUNT[2:0]
DEVICE_ID[4:0]
01h
02h
STATUS_MSB
7FC8h
RESETn
SUPPLY_FAUL ADC_FAULTn DIGITAL_FAUL OCC_FAULTn SPI_CRC_FAU SPI_TIMEOUT SCLK_COUNT
Tn
Tn
LTn
n
_FAULTn
REG_ACCESS
_FAULTn
COMMAND_RESPONSE[3:0]
LOCK
CLOCK
MODE
STATUS_LSB
0000h
SEQ2A_COUNT[1:0]
RESERVED
RESERVED
CONV1A_COUNT[1:0]
CONV1B_COUNT[1:0]
SEQ2A_ACTIV RESERVED
E
03h
04h
05h
SUPPLY_STATUS
ADC_STATUS
FFFFh
FC07h
AVDD_OVn
AVDD_UVn
AVDD_OTWn
ADC1B_ORn
IOVDD_OVn
IOVDD_OTWn
ADC2A_ORn
RESERVED
IOVDD_UVn
AVDD_CLn
DVDD_OVn
DVDD_UVn
AVDD_OSCn
IOVDD_OSCn
DVDD_OSCn
ADC1A_ORn
IOVDD_CLn
AGNDA_DISCn AGNDB_DISCn DGND_DISCn
RESERVED
MCLK_FAULTn
OTP_BANK
OSCD_WDn
MCLK_WDn
DIGITAL_STATUS
EC00h REG_MAP1_C REG_MAP2_C REG_MAP3_C
RC_FAULTn RC_FAULTn RC_FAULTn
RESERVED
MEM_MAP_CR
C_FAULTn
RESERVED
RESERVED
RESERVED
OCCA_HTn
06h
07h
08h
OCC_STATUS
GPI_DATA
000Fh
0000h
0000h
RESERVED
OCCA_LTn
OCCB_HTn
GPI4_DAT[1:0]
OCCB_LTn
RESERVED
GPI2_DAT[1:0]
GPI3_DAT[1:0]
GPI1_DAT[1:0]
GPI0_DAT[1:0]
GPI0A_DAT[1:0]
GPI0B_DAT[1:0]
GPIA_GPIB_DATA
RESERVED
RESERVED
GPI1A_DAT[1:0]
GPI1B_DAT[1:0]
09h
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
CONVERSION_CTR 0000h
L
RESERVED
RESERVED
STARTA
SEQ2A_START
RESERVED
STARTB
RESERVED
RESERVED
STOPA
SEQ2A_STOP
RESERVED
STOPB
RESERVED
SEQ2A_STEP0_DAT 0000h
A
SEQ2A_STEP0_DAT[15:0]
SEQ2A_STEP0_DAT[15:0]
SEQ2A_STEP1_DAT[15:0]
SEQ2A_STEP1_DAT[15:0]
SEQ2A_STEP2_DAT[15:0]
SEQ2A_STEP2_DAT[15:0]
SEQ2A_STEP3_DAT[15:0]
SEQ2A_STEP3_DAT[15:0]
SEQ2A_STEP4_DAT[15:0]
SEQ2A_STEP4_DAT[15:0]
SEQ2A_STEP5_DAT[15:0]
SEQ2A_STEP5_DAT[15:0]
SEQ2A_STEP6_DAT[15:0]
SEQ2A_STEP6_DAT[15:0]
SEQ2A_STEP7_DAT[15:0]
SEQ2A_STEP7_DAT[15:0]
SEQ2A_STEP8_DAT[15:0]
SEQ2A_STEP8_DAT[15:0]
SEQ2A_STEP9_DAT[15:0]
SEQ2A_STEP9_DAT[15:0]
SEQ2A_STEP10_DAT[15:0]
SEQ2A_STEP10_DAT[15:0]
SEQ2A_STEP11_DAT[15:0]
SEQ2A_STEP11_DAT[15:0]
SEQ2A_STEP12_DAT[15:0]
SEQ2A_STEP12_DAT[15:0]
SEQ2A_STEP1_DAT 0000h
A
SEQ2A_STEP2_DAT 0000h
A
SEQ2A_STEP3_DAT 0000h
A
SEQ2A_STEP4_DAT 0000h
A
SEQ2A_STEP5_DAT 0000h
A
SEQ2A_STEP6_DAT 0000h
A
SEQ2A_STEP7_DAT 0000h
A
SEQ2A_STEP8_DAT 0000h
A
SEQ2A_STEP9_DAT 0000h
A
SEQ2A_STEP10_DA 0000h
TA
SEQ2A_STEP11_DA 0000h
TA
SEQ2A_STEP12_DA 0000h
TA
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表8-24. Register Map (continued)
Address
1Dh
Acronym
Reset
Bit 15
Bit 7
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 2
Bit 9
Bit 1
Bit 8
Bit 0
Bit 6
Bit 5
Bit 4
Bit 3
SEQ2A_STEP13_DA 0000h
TA
SEQ2A_STEP13_DAT[15:0]
SEQ2A_STEP13_DAT[15:0]
SEQ2A_STEP14_DAT[15:0]
SEQ2A_STEP14_DAT[15:0]
SEQ2A_STEP15_DAT[15:0]
SEQ2A_STEP15_DAT[15:0]
1Eh
SEQ2A_STEP14_DA 0000h
TA
1Fh
SEQ2A_STEP15_DA 0000h
TA
SECTION 1
40h
DEVICE_MONITOR_ 3000h
REG_MAP1_C
RC_EN
CRC_TYPE
SCLK_COUNT TIMEOUT_EN
ER_EN
RESERVED
MHD_POL
FAULT_POL
CFG
RESERVED
MHD_CFG[1:0]
41h
SUPPLY_MONITOR FFFFh
_CFG1
AVDD_OV_EN AVDD_UV_EN IOVDD_OV_EN IOVDD_UV_EN DVDD_OV_EN DVDD_UV_EN AVDD_OSC_E IOVDD_OSC_E
N
N
DVDD_OSC_E AVDD_OTW_E IOVDD_OTW_ AVDD_CL_EN IOVDD_CL_EN AGNDA_DISC_ AGNDB_DISC_ DGND_DISC_E
N
N
EN
EN
EN
N
42h
43h
SUPPLY_MONITOR
_CFG2
10F0h
RESERVED
AVDD_OTW_CFG[1:0]
IOVDD_OV_TH IOVDD_UV_TH
IOVDD_OTW_CFG[1:0]
RESERVED
RESERVED
ADC_MONITOR_CF FC07h
G
ADC1A_OR_E ADC1B_OR_E ADC2A_OR_E
SPARE[2:0]
RESERVED
N
N
N
RESERVED
MCLK_MON_E OSCD_WD_EN MCLK_WD_EN
N
44h
SUPPLY_MONITOR
_DIAGNOSTIC_CFG
0000h AVDD_OV_DIA AVDD_UV_DIA IOVDD_OV_DI IOVDD_UV_DI DVDD_OV_DIA DVDD_UV_DIA AVDD_OSC_DI IOVDD_OSC_D
G_EN
G_EN
AG_EN
AG_EN
G_EN
G_EN
AG_EN
IAG_EN
DVDD_OSC_DI
AG_EN
RESERVED
AGNDA_DISC_ AGNDB_DISC_ DGND_DISC_D
DIAG_EN DIAG_EN IAG_EN
45h
46h
47h
ADC_MONITOR_DI
AGNOSTIC_CFG
0000h
0000h
SPARE[11:0]
MCLK_HI_DIA MCLK_LO_DIA OSCD_WD_DI MCLK_WD_DI
SPARE[11:0]
G_EN G_EN AG_EN AG_EN
DIGITAL_MONITOR
_DIAGNOSTIC_CFG
RESERVED
RESERVED
MEM_MAP_CRC_DIAG[1:0]
GPIOA_DIAG_ GPIOB_DIAG_ GPIO_DIAG_E
EN EN
N
SUPPLY_FAULT_MA 0000h
SK
AVDD_OV_MA AVDD_UV_MA IOVDD_OV_M IOVDD_UV_MA DVDD_OV_MA DVDD_UV_MA AVDD_OSC_M IOVDD_OSC_
SK SK ASK SK SK SK ASK MASK
DVDD_OSC_M AVDD_OTW_M IOVDD_OTW_ AVDD_CL_MA IOVDD_CL_MA AGNDA_DISC_ AGNDB_DISC_ DGND_DISC_
ASK
ASK
MASK
SK
SK
MASK
MASK
MASK
48h
49h
ADC_FAULT_MASK
0000h
ADC1A_OR_M ADC1B_OR_M ADC2A_OR_M
SPARE[2:0]
RESERVED
ASK
ASK
ASK
RESERVED
MCLK_FAULT_ OSCD_WD_MA MCLK_WD_MA
MASK
SK
SK
DIGITAL_FAULT_MA 0000h
SK
REG_MAP1_C REG_MAP2_C REG_MAP3_C
RC_FAULT_MA RC_FAULT_MA RC_FAULT_MA
RESERVED
MEM_MAP_CR
C_FAULT_MAS
K
RESERVED
SK
SK
SK
RESERVED
RESERVED
OCCA_HT_MA OCCA_LT_MA OCCB_HT_MA OCCB_LT_MA
4Ah
4Bh
OCC_FAULT_MASK
FAULT_PIN_MASK
0000h
0780h
RESERVED
SK SK SK SK
RESERVED
SUPPLY_FAUL ADC_FAULT_M DIGITAL_FAUL OCC_FAULT_ SPI_CRC_FAU SPI_TIMEOUT SCLK_COUNT
T_MASK
ASK
T_MASK
MASK
LT_MASK
_MASK
_FAULT_MASK
REG_ACCESS
_FAULT_MASK
RESERVED
4Ch
DEVICE_CFG
0000h
RESERVED
DRDY_CTRL
RESERVED
CLK_SOURCE WORD_LENGT
H
RESERVED
OP_MODE[1:0]
RESERVED
4Dh
4Eh
4Fh
GPIO_CFG
GPO_DATA
0000h
0000h
007Fh
RESERVED
GPIO2_DIR
GPIO4_FMT
GPIO1_DIR
GPIO3_FMT
GPIO0_DIR
GPIO2_FMT
GPIO4_SRC
GPIO1_FMT
GPIO3_SRC
GPIO0_FMT
GPIO2_SRC
GPIO4_DIR
RESERVED
GPIO3_DIR
GPIO0_SRC
SPARE[10:0]
SPARE[10:0]
GPO4_DAT
GPO3_DAT
GPO2_DAT
GPO1_DAT
GPO0_DAT
GPIO0_LL_PWM_C
FG
GPIO0_PWM_TB[1:0]
GPIO0_LL_PWM_HC[6:0]
GPIO0_LL_PWM_LC[6:0]
GPIO0_LL_PW
M_HC[6:0]
50h
GPIO0_LH_PWM_C
FG
3F80h
RESERVED
GPIO0_LH_PWM_HC[6:0]
GPIO0_LH_PWM_LC[6:0]
GPIO0_LH_PW
M_HC[6:0]
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表8-24. Register Map (continued)
Address
Acronym
Reset
Bit 15
Bit 7
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 2
Bit 9
Bit 1
Bit 8
Bit 0
Bit 6
Bit 5
Bit 4
Bit 3
51h
GPIO1_LL_PWM_C
FG
007Fh
GPIO1_PWM_TB[1:0]
GPIO1_LL_PW
GPIO1_LL_PWM_HC[6:0]
GPIO1_LL_PWM_LC[6:0]
M_HC[6:0]
52h
53h
54h
55h
56h
57h
58h
GPIO1_LH_PWM_C
FG
3F80h
007Fh
3F80h
007Fh
3F80h
007Fh
3F80h
RESERVED
GPIO1_LH_PWM_HC[6:0]
GPIO1_LH_PWM_LC[6:0]
GPIO1_LH_PW
M_HC[6:0]
GPIO2_LL_PWM_C
FG
GPIO2_PWM_TB[1:0]
GPIO2_LL_PWM_HC[6:0]
GPIO2_LL_PWM_LC[6:0]
GPIO2_LL_PW
M_HC[6:0]
GPIO2_LH_PWM_C
FG
RESERVED
GPIO2_LH_PWM_HC[6:0]
GPIO2_LH_PWM_LC[6:0]
GPIO2_LH_PW
M_HC[6:0]
GPIO3_LL_PWM_C
FG
GPIO3_PWM_TB[1:0]
GPIO3_LL_PWM_HC[6:0]
GPIO3_LL_PWM_LC[6:0]
GPIO3_LL_PW
M_HC[6:0]
GPIO3_LH_PWM_C
FG
RESERVED
GPIO3_LH_PWM_HC[6:0]
GPIO3_LH_PWM_LC[6:0]
GPIO3_LH_PW
M_HC[6:0]
GPIO4_LL_PWM_C
FG
GPIO4_PWM_TB[1:0]
GPIO4_LL_PWM_HC[6:0]
GPIO4_LL_PWM_LC[6:0]
GPIO4_LL_PW
M_HC[6:0]
GPIO4_LH_PWM_C
FG
RESERVED
GPIO4_LH_PWM_HC[6:0]
GPIO4_LH_PWM_LC[6:0]
GPIO4_LH_PW
M_HC[6:0]
59h
7Eh
SPARE_59h
5555h
0000h
SPARE[15:0]
SPARE[15:0]
REGISTER_MAP1_
CRC
REG_MAP1_CRC_VALUE[15:0]
REG_MAP1_CRC_VALUE[15:0]
SECTION 2
80h
REGMAP2_TDACA_ 0000h
CFG
REG_MAP2_C
RC_EN
RESERVED
RESERVED
SPARE[2:0]
TDACA_VALUE[2:0]
GPIO1A_DIR
GPO1A_DAT
81h
82h
GPIOA_CFG
8000h
0400h
RESERVED
GPIO1A_FMT
GPIO0A_FMT
GPIO0A_DIR
GPO0A_DAT
GPIO1A_PWM_TB[1:0]
GPIO0A_PWM_TB[1:0]
SPARE[1:0]
ADC1A_CFG1
RESERVED
CONV_MODE1
A
OSR1A[2:0]
RESERVED
RESERVED
OWD1A_SOUR OWD1A_SINK_ OWD1A_SOURCE_VALUE[1:0]
GC1A_EN
GC1A_DELAY[2:0]
83h
ADC1A_CFG2
8010h
ADC1A_EN
RESERVED
GAIN1A[1:0]
MUX1A[1:0]
OWD1A_SINK_VALUE[1:0]
CE_MUX
MUX
84h
85h
86h
87h
88h
89h
8Ah
8Bh
ADC1A_OCAL_MSB 0000h
OCAL1A[23:8]
OCAL1A[23:8]
OCAL1A[7:0]
RESERVED
ADC1A_OCAL_LSB
ADC1A_GCAL
OCCA_CFG
0000h
0000h
0000h
GCAL1A[15:0]
GCAL1A[15:0]
OCCA_EN
OCCA_POL
RESERVED
OCCA_NUM[4:0]
RESERVED
OCCA_HIGH_TH[15:0]
OCCA_HIGH_TH[15:0]
OCCA_LOW_TH[15:0]
OCCA_LOW_TH[15:0]
SPARE[15:0]
OCCA_HIGH_THRE 7FFFh
SHOLD
OCCA_LOW_THRE
SHOLD
8000h
5555h
8010h
SPARE_8Ah
SPARE[15:0]
ADC2A_CFG1
ADC2A_EN
RESERVED
OWD2A_SINK_MUX[2:0]
VCMA_EN
OWD2A_SOURCE_VALUE[1:0]
OWD2A_SOURCE_MUX[2:0]
OWD2A_SINK_VALUE[1:0]
OWD2A_SOUR
CE_MUX[2:0]
8Ch
ADC2A_CFG2
0000h
SEQ2A_MODE[1:0]
RESERVED
MUX2A_DELAY[2:0]
OSR2A[1:0]
RESERVED
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表8-24. Register Map (continued)
Address
8Dh
Acronym
Reset
0000h
0000h
0000h
Bit 15
Bit 7
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 2
Bit 9
Bit 1
Bit 8
Bit 0
Bit 6
Bit 5
Bit 4
Bit 3
SPARE_8Dh
ADC2A_OCAL
ADC2A_GCAL
RESERVED
SPARE[7:0]
8Eh
OCAL2A[15:0]
OCAL2A[15:0]
GCAL2A[15:0]
GCAL2A[15:0]
8Fh
90h
SEQ2A_STEP0_CF
G
0000h SEQ2A_STEP0
_EN
SEQ2A_STEP0_GAIN[1:0]
RESERVED
RESERVED
SEQ2A_STEP0
SEQ2A_STEP0_CH_P[3:0]
RESERVED
_CH_N
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
SEQ2A_STEP1_CF
G
0001h SEQ2A_STEP1
_EN
SEQ2A_STEP1_GAIN[1:0]
RESERVED
SEQ2A_STEP1
_CH_N
SEQ2A_STEP1_CH_P[3:0]
RESERVED
SEQ2A_STEP2_CF
G
0002h SEQ2A_STEP2
_EN
SEQ2A_STEP2_GAIN[1:0]
RESERVED
SEQ2A_STEP2
_CH_N
SEQ2A_STEP2_CH_P[3:0]
RESERVED
SEQ2A_STEP3_CF
G
0003h SEQ2A_STEP3
_EN
SEQ2A_STEP3_GAIN[1:0]
RESERVED
SEQ2A_STEP3
_CH_N
SEQ2A_STEP3_CH_P[3:0]
RESERVED
SEQ2A_STEP4_CF
G
0004h SEQ2A_STEP4
_EN
SEQ2A_STEP4_GAIN[1:0]
RESERVED
SEQ2A_STEP4
_CH_N
SEQ2A_STEP4_CH_P[3:0]
RESERVED
SEQ2A_STEP5_CF
G
0005h SEQ2A_STEP5
_EN
SEQ2A_STEP5_GAIN[1:0]
RESERVED
SEQ2A_STEP5
_CH_N
SEQ2A_STEP5_CH_P[3:0]
RESERVED
SEQ2A_STEP6_CF
G
0006h SEQ2A_STEP6
_EN
SEQ2A_STEP6_GAIN[1:0]
RESERVED
SEQ2A_STEP6
_CH_N
SEQ2A_STEP6_CH_P[3:0]
RESERVED
SEQ2A_STEP7_CF
G
0007h SEQ2A_STEP7
_EN
SEQ2A_STEP7_GAIN[1:0]
RESERVED
SEQ2A_STEP7
_CH_N
SEQ2A_STEP7_CH_P[3:0]
RESERVED
SEQ2A_STEP8_CF
G
0008h SEQ2A_STEP8
_EN
SEQ2A_STEP8_GAIN[1:0]
RESERVED
SEQ2A_STEP8
_CH_N
SEQ2A_STEP8_CH_P[3:0]
RESERVED
SEQ2A_STEP9_CF
G
0009h SEQ2A_STEP9
_EN
SEQ2A_STEP9_GAIN[1:0]
RESERVED
SEQ2A_STEP9
_CH_N
SEQ2A_STEP9_CH_P[3:0]
RESERVED
SEQ2A_STEP10_CF 000Ah SEQ2A_STEP1
0_EN
SEQ2A_STEP10_GAIN[1:0]
RESERVED
G
SEQ2A_STEP1
0_CH_N
SEQ2A_STEP10_CH_P[3:0]
RESERVED
SEQ2A_STEP11_CF 000Bh SEQ2A_STEP1
1_EN
SEQ2A_STEP11_GAIN[1:0]
RESERVED
G
SEQ2A_STEP1
1_CH_N
SEQ2A_STEP11_CH_P[3:0]
RESERVED
SEQ2A_STEP12_CF 000Ch SEQ2A_STEP1
2_EN
SEQ2A_STEP12_GAIN[1:0]
RESERVED
G
SEQ2A_STEP1
2_CH_N
SEQ2A_STEP12_CH_P[3:0]
RESERVED
SEQ2A_STEP13_CF 000Dh SEQ2A_STEP1
3_EN
SEQ2A_STEP13_GAIN[1:0]
RESERVED
G
SEQ2A_STEP1
3_CH_N
SEQ2A_STEP13_CH_P[3:0]
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表8-24. Register Map (continued)
Address
Acronym
Reset
Bit 15
Bit 7
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 2
Bit 9
Bit 1
Bit 8
Bit 0
Bit 6
Bit 5
Bit 4
Bit 3
9Eh
SEQ2A_STEP14_CF 000Eh SEQ2A_STEP1
4_EN
SEQ2A_STEP14_GAIN[1:0]
RESERVED
RESERVED
G
SEQ2A_STEP1
4_CH_N
SEQ2A_STEP14_CH_P[3:0]
RESERVED
9Fh
SEQ2A_STEP15_CF 000Fh SEQ2A_STEP1
SEQ2A_STEP15_GAIN[1:0]
RESERVED
G
5_EN
SEQ2A_STEP1
5_CH_N
SEQ2A_STEP15_CH_P[3:0]
A0h
A1h
SPARE_A0h
SPARE_A1h
SPARE_A2h
SPARE_A3h
0210h
0000h
0000h
0000h
0000h
RESERVED
SPARE[1:0]
RESERVED
RESERVED
SPARE[1:0]
RESERVED
SPARE[15:0]
SPARE[15:0]
SPARE[7:0]
RESERVED
SPARE[15:0]
SPARE[15:0]
A2h
A3h
BEh
REGISTER_MAP2_
CRC
REG_MAP2_CRC_VALUE[15:0]
REG_MAP2_CRC_VALUE[15:0]
SECTION 3
C0h
REGMAP3_TDACB_ 0000h
CFG
REG_MAP3_C
RC_EN
RESERVED
RESERVED
SPARE[2:0]
TDACB_VALUE[2:0]
C1h
C2h
GPIOB_CFG
8000h
0400h
RESERVED
GPIO1B_FMT
GPIO0B_FMT
GPIO1B_DIR
GPO1B_DAT
OSR1B[2:0]
GPIO0B_DIR
GPO0B_DAT
GPIO1B_PWM_TB[1:0]
GPIO0B_PWM_TB[1:0]
SPARE[1:0]
ADC1B_CFG1
RESERVED
CONV_MODE1
B
RESERVED
GC1B_EN
GC1B_DELAY[2:0]
C3h
ADC1B_CFG2
8010h
ADC1B_EN
RESERVED
GAIN1B[1:0]
MUX1B[1:0]
OWD1B_SINK_VALUE[1:0]
RESERVED
OWD1B_SOUR OWD1B_SINK_ OWD1B_SOURCE_VALUE[1:0]
CE_MUX
MUX
OCAL1B[23:8]
C4h
C5h
C6h
C7h
C8h
C9h
CAh
CBh
CCh
CDh
CEh
CFh
D0h
ADC1B_OCAL_MSB 0000h
OCAL1B[23:8]
OCAL1B[7:0]
RESERVED
ADC1B_OCAL_LSB
ADC1B_GCAL
OCCB_CFG
0000h
0000h
0000h
GCAL1B[15:0]
GCAL1B[15:0]
OCCB_EN
OCCB_POL
RESERVED
OCCB_NUM[4:0]
RESERVED
OCCB_HIGH_TH[15:0]
OCCB_HIGH_TH[15:0]
OCCB_LOW_TH[15:0]
OCCB_LOW_TH[15:0]
SPARE[15:0]
OCCB_HIGH_THRE 7FFFh
SHOLD
OCCB_LOW_THRE
SHOLD
8000h
5555h
0010h
0000h
0000h
0000h
0000h
0000h
SPARE_CAh
SPARE_CBh
SPARE_CCh
SPARE_CDh
SPARE_CEh
SPARE_CFh
SPARE_D0h
SPARE[15:0]
RESERVED
SPARE[6:0]
RESERVED
SPARE[2:0]
SPARE[1:0]
SPARE[6:0]
SPARE[1:0]
RESERVED
RESERVED
RESERVED
SPARE[7:0]
SPARE[15:0]
SPARE[15:0]
SPARE[15:0]
SPARE[15:0]
SPARE[2:0]
RESERVED
RESERVED
SPARE[4:0]
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表8-24. Register Map (continued)
Address
D1h
D2h
D3h
D4h
D5h
D6h
D7h
D8h
D9h
DAh
DBh
DCh
DDh
DEh
DFh
E0h
Acronym
Reset
0001h
0002h
0003h
0004h
0005h
0006h
0007h
0008h
0009h
000Ah
000Bh
000Ch
000Dh
000Eh
000Fh
0210h
0000h
0000h
0000h
0000h
Bit 15
Bit 7
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 1
Bit 8
Bit 0
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
SPARE_D1h
SPARE_D2h
SPARE_D3h
SPARE_D4h
SPARE_D5h
SPARE_D6h
SPARE_D7h
SPARE_D8h
SPARE_D9h
SPARE_DAh
SPARE_DBh
SPARE_DCh
SPARE_DDh
SPARE_DEh
SPARE_DFh
SPARE_E0h
SPARE_E1h
SPARE_E2h
SPARE_E3h
SPARE[2:0]
RESERVED
SPARE[2:0]
RESERVED
SPARE[2:0]
RESERVED
SPARE[2:0]
RESERVED
SPARE[2:0]
RESERVED
SPARE[2:0]
RESERVED
SPARE[2:0]
RESERVED
SPARE[2:0]
RESERVED
SPARE[2:0]
RESERVED
SPARE[2:0]
RESERVED
SPARE[2:0]
RESERVED
SPARE[2:0]
RESERVED
SPARE[2:0]
RESERVED
SPARE[2:0]
RESERVED
SPARE[2:0]
RESERVED
RESERVED
SPARE[4:0]
RESERVED
SPARE[4:0]
RESERVED
SPARE[4:0]
RESERVED
SPARE[4:0]
RESERVED
SPARE[4:0]
RESERVED
SPARE[4:0]
RESERVED
SPARE[4:0]
RESERVED
SPARE[4:0]
RESERVED
SPARE[4:0]
RESERVED
SPARE[4:0]
RESERVED
SPARE[4:0]
RESERVED
SPARE[4:0]
RESERVED
SPARE[4:0]
RESERVED
SPARE[4:0]
RESERVED
SPARE[4:0]
RESERVED
SPARE[1:0]
RESERVED
RESERVED
SPARE[1:0]
RESERVED
E1h
SPARE[15:0]
SPARE[15:0]
SPARE[7:0]
RESERVED
SPARE[15:0]
SPARE[15:0]
E2h
E3h
FEh
REGISTER_MAP3_
CRC
REG_MAP3_CRC_VALUE[15:0]
REG_MAP3_CRC_VALUE[15:0]
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8.6.1.1 ID Register (Address = 00h) [Reset = X]
Return to the Summary Table.
图8-46. ID Register
15
14
13
12
11
10
9
1
8
0
REV[7:0]
R-X
7
6
5
4
3
2
DEVICE_ID[4:0]
R-X
ADC_COUNT[2:0]
R-011b
表8-25. ID Register Field Descriptions
Bit
Field
Type
Reset
Description
15:8
REV[7:0]
R
X
Revision ID
Values are subject to change without notice
7:5
ADC_COUNT[2:0]
DEVICE_ID[4:0]
R
R
011b
X
ADC count
011b = 3 (ADC1A, ADC1B, ADC2A)
4:0
Device ID
Values are subject to change without notice
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8.6.1.2 STATUS_MSB Register (Address = 01h) [Reset = 7FC8h]
Return to the Summary Table.
图8-47. STATUS_MSB Register
15
14
13
12
11
10
9
8
RESETn
SUPPLY_FAULTn
ADC_FAULTn
DIGITAL_FAULTn
OCC_FAULTn
SPI_CRC_FAULTn
SPI_TIMEOUTn
SCLK_COUNT_FAU
LTn
R/W-0b
7
R/W-1b
6
R/W-1b
5
R/W-1b
4
R/W-1b
3
R-1b
R-1b
R-1b
2
1
0
REG_ACCESS_FAU
LTn
COMMAND_RESPONSE[3:0]
LOCK
CLOCK
MODE
R-1b
R-1001b
R-0b
R-0b
R-0b
表8-26. STATUS_MSB Register Field Descriptions
Bit
Field
RESETn
Type
Reset
Description
15
R/W
0b
RESET flag
Indicates a device reset occurred. Write 1b to clear this bit to 1b.
0b = Reset occurred
1b = No reset occurred
14
SUPPLY_FAULTn
R/W
1b
Supply fault flag
Indicates that one or more of the unmasked supply fault flags in the SUPPLY_STATUS
register is set. Write 1b to clear this bit to 1b after all set unmasked supply fault flags are
cleared.
0b = One or more of the unmasked supply fault flags is set
1b = None of the unmasked supply fault flags are set
13
12
ADC_FAULTn
R/W
R/W
1b
1b
ADC fault flag
Indicates that one or more of the unmasked ADC fault flags in the ADC_STATUS register is
set. Write 1b to clear this bit to 1b after all set unmasked ADC fault flags are cleared.
0b = One or more of the unmasked ADC fault flags is set
1b = None of the unmasked supply ADC fault flags are set
DIGITAL_FAULTn
Digital fault flag
Indicates that one or more of the unmasked digital fault flags in the DIGITAL_STATUS
register is set. Write 1b to clear this bit to 1b after all set unmasked digital fault flags are
cleared.
0b = One or more of the unmasked digital fault flags is set
1b = None of the unmasked digital fault flags are set
11
OCC_FAULTn
R/W
1b
Overcurrent comparator fault flag
Indicates that one or more of the unmasked overcurrent comparator fault flags in the
OCC_STATUS register is set. Write 1b to clear this bit to 1b after all set unmasked
overcurrent comparator fault flags are cleared.
0b = One or more of the unmasked overcurrent comparator fault flags is set
1b = None of the unmasked overcurrent comparator fault flags are set
10
9
SPI_CRC_FAULTn
SPI_TIMEOUTn
R
R
R
1b
1b
1b
SPI CRC fault flag
Indicates an SPI CRC fault occurred in the previous SPI frame. This bit clears automatically
to 1b in each new SPI frame.
0b = SPI CRC fault occurred
1b = No SPI CRC fault occurred
SPI timeout fault flag
Indicates an SPI timeout fault occurred in the previous SPI frame. This bit clears
automatically to 1b in each new SPI frame.
0b = SPI timeout fault occurred
1b = No SPI timeout fault occurred
8
SCLK_COUNT_FAULTn
SCLK counter fault flag
Indicates an SCLK counter fault occurred in the previous SPI frame (that is, fewer or more
SCLKs than required for the previous frame were sent). This bit clears automatically to 1b in
each new SPI frame.
0b = SCLK counter fault occurred
1b = No SCLK counter fault occurred
7
REG_ACCESS_FAULTn
R
1b
Register access fault flag
Indicates a read or write access to an invalid register address (register address FFh or
beyond) occurred. This flag sets to 0b in the subsequent frame following the frame where a
read or write operation to a register with an invalid register address was attempted. This bit
clears automatically to 1b in each new SPI frame.
0b = Register access fault occurred
1b = No register access fault occurred
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表8-26. STATUS_MSB Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
6:3
COMMAND_RESPONSE[3:0]
R
1001b
Command response indication
Indicates which command was executed in the previous SPI frame.
0000b = Invalid response that does not occur under normal circumstances. Can indicate a
stuck-at SDO signal or that the device is held in reset.
0001b = NULL command
0010b = LOCK command
0011b = UNLOCK command
0100b = RREG command
0101b = NULL command (because a NULL command was correctly sent as the second
frame after a RREG command). This response serves as the frame counter for the two-
frame RREG command.
0110b = WREG command
0111b = Invalid response that does not occur under normal circumstances.
1000b = Invalid response that does not occur under normal circumstances.
1001b = NULL command (first frame after power-up or reset). This response is only sent in
the first frame after reset or power-up, the second frame has the response based on the
command sent in the first frame.
1010b = NULL command (resulting from one of the following errors: a timeout occurred
before a complete command CRC was received, insufficient SCLKs were sent to complete a
command, a CRC mismatch between the command word and command CRC word, or a
CRC mismatch between data words and the data CRC word in a WREG command). For the
NULL, RREG, LOCK, and UNLOCK commands, the command and command CRC words
must be sent to complete the command. For the RESET command, the STATUS word, all
ADC data words, and the output CRC word must be read to complete the command. For the
WREG command, the command and command CRC words, as well as the data and data
CRC words must be sent to complete the command.
1011b = NULL command (resulting from an invalid command word with a matching CRC
between the command word and command CRC word).
1100b = NULL command (resulting from a command other than the NULL command was
sent in the second frame after the RREG command and ignored). This response serves as
the frame counter for the two-frame RREG command.
1101b = NULL command (the RESET or WREG commands are ignored because the device
is locked).
1110b = Invalid response that does not occur under normal circumstances.
1111b = Invalid response that does not occur under normal circumstances. Can indicate a
stuck-at SDO signal.
2
1
0
LOCK
R
R
R
0b
0b
0b
Lock state indication
Indicates if the device is locked or unlocked.
0b = Device is unlocked
1b = Device is locked
CLOCK
MODE
Clock source indication
Indicates which clock source the device is currently using.
0b = Internal oscillator
1b = External clock
Operating mode indication
Indicates which operating mode the device is currently in.
0b = Active mode
1b = Standby or power-down mode
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8.6.1.3 STATUS_LSB Register (Address = 02h) [Reset = 0000h]
Return to the Summary Table.
图8-48. STATUS_LSB Register
15
14
13
12
11
CONV1A_COUNT[1:0]
R-00b
10
9
8
SEQ2A_COUNT[1:0]
RESERVED
R-00b
CONV1B_COUNT[1:0]
R-00b
R-00b
7
6
5
4
3
2
1
0
RESERVED
R-000000b
SEQ2A_ACTIVE
R-0b
RESERVED
R-0b
表8-27. STATUS_LSB Register Field Descriptions
Bit
Field
Type
Reset
Description
15:14
SEQ2A_COUNT[1:0]
R
00b
ADC2A sequence counter
Circular counter that increments each time a new sequence on ADC2A completes. This
counter resets to 00b when ADC2A is disabled, when the device is put in standby or power-
down mode, or after a device reset.
13:12
11:10
RESERVED
R
R
00b
00b
Reserved
Always reads 00b.
CONV1A_COUNT[1:0]
ADC1A conversion counter
Circular counter that increments each time a new conversion on ADC1A completes. This
counter resets to 00b when ADC1A is disabled, when the device is put in standby or power-
down mode, or after a device reset.
9:8
CONV1B_COUNT[1:0]
R
00b
ADC1B conversion counter
Circular counter that increments each time a new conversion on ADC1B completes. This
counter resets to 00b when ADC1B is disabled, when the device is put in standby or power-
down mode, or after a device reset.
7:2
1
RESERVED
R
R
000000b
0b
Reserved
Always reads 000000b.
SEQ2A_ACTIVE
ADC2A sequence in progress indication
Indicates that a sequence on ADC2A is currently in progress. Changes to registers from
address 8Ch to 9Fh of ADC2A must only be made when ADC2A is disabled.
0b = No sequence in progress
1b = Sequence in progress
0
RESERVED
R
0b
Reserved
Always reads 0b.
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8.6.1.4 SUPPLY_STATUS Register (Address = 03h) [Reset = FFFFh]
Return to the Summary Table.
图8-49. SUPPLY_STATUS Register
15
14
13
12
11
10
9
8
AVDD_OVn
R/W-1b
AVDD_UVn
R/W-1b
IOVDD_OVn
R/W-1b
IOVDD_UVn
R/W-1b
DVDD_OVn
R/W-1b
DVDD_UVn
R/W-1b
AVDD_OSCn
R/W-1b
IOVDD_OSCn
R/W-1b
7
6
5
4
3
2
1
0
DVDD_OSCn
R/W-1b
AVDD_OTWn
R/W-1b
IOVDD_OTWn
R/W-1b
AVDD_CLn
R/W-1b
IOVDD_CLn
R/W-1b
AGNDA_DISCn
R/W-1b
AGNDB_DISCn
R/W-1b
DGND_DISCn
R/W-1b
表8-28. SUPPLY_STATUS Register Field Descriptions
Bit
Field
Type
Reset
Description
15
AVDD_OVn
R/W
1b
AVDD overvoltage fault flag
Indicates the AVDD supply voltage exceeded the AVDD overvoltage threshold. See the
AVDD monitor description for details regarding the AVDD LDO shutdown during
overvoltage. Write 1b to clear this bit to 1b.
0b = Overvoltage fault occurred
1b = No overvoltage fault occurred
14
13
AVDD_UVn
IOVDD_OVn
R/W
R/W
1b
1b
AVDD undervoltage fault flag
Indicates the AVDD supply voltage dropped below the AVDD undervoltage threshold. Write
1b to clear this bit to 1b.
0b = Undervoltage fault occurred
1b = No undervoltage fault occurred
IOVDD overvoltage fault flag
Indicates the IOVDD supply voltage exceeded the IOVDD overvoltage threshold. See the
IOVDD monitor description for details regarding the IOVDD LDO shutdown during
overvoltage. Write 1b to clear this bit to 1b.
0b = Overvoltage fault occurred
1b = No overvoltage fault occurred
12
11
IOVDD_UVn
DVDD_OVn
R/W
R/W
1b
1b
IOVDD undervoltage fault flag
Indicates the IOVDD supply voltage dropped below the IOVDD undervoltage threshold.
Write 1b to clear this bit to 1b.
0b = Undervoltage fault occurred
1b = No undervoltage fault occurred
DVDD overvoltage fault flag
Indicates the DVDD supply voltage exceeded the DVDD overvoltage threshold. See the
DVDD monitor description for details regarding the DVDD LDO shutdown during
overvoltage. Write 1b to clear this bit to 1b.
0b = Overvoltage fault occurred
1b = No overvoltage fault occurred
10
DVDD_UVn
R/W
1b
DVDD undervoltage fault flag
Indicates the DVDD supply voltage dropped below the DVDD undervoltage threshold. Write
1b to clear this bit to 1b.
0b = Undervoltage fault occurred
1b = No undervoltage fault occurred
9
8
7
6
AVDD_OSCn
IOVDD_OSCn
DVDD_OSCn
AVDD_OTWn
R/W
R/W
R/W
R/W
1b
1b
1b
1b
AVDD oscillation fault flag
Indicates the AVDD supply voltage is oscillating. Write 1b to clear this bit to 1b.
0b = Oscillation fault occurred
1b = No oscillation fault occurred
IOVDD oscillation fault flag
Indicates the IOVDD supply voltage is oscillating. Write 1b to clear this bit to 1b.
0b = Oscillation fault occurred
1b = No oscillation fault occurred
DVDD oscillation fault flag
Indicates the DVDD supply voltage is oscillating. Write 1b to clear this bit to 1b.
0b = Oscillation fault occurred
1b = No oscillation fault occurred
AVDD overtemperature warning flag
Indicates the AVDD LDO temperature exceeded the AVDD overtemperature warning
threshold. Write 1b to clear this bit to 1b.
0b = Overtemperature warning
1b = No overtemperature warning
5
4
IOVDD_OTWn
AVDD_CLn
R/W
R/W
1b
1b
IOVDD overtemperature warning flag
Indicates the IOVDD LDO temperature exceeded the IOVDD overtemperature warning
threshold. Write 1b to clear this bit to 1b.
0b = Overtemperature warning
1b = No overtemperature warning
AVDD current limit flag
Indicates the AVDD LDO current limit is active. Write 1b to clear this bit to 1b.
0b = Current limit
1b = No current limit
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表8-28. SUPPLY_STATUS Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
3
IOVDD_CLn
R/W
1b
IOVDD current limit flag
Indicates the IOVDD LDO current limit is active. Write 1b to clear this bit to 1b.
0b = Current limit
1b = No current limit
2
1
0
AGNDA_DISCn
AGNDB_DISCn
DGND_DISCn
R/W
R/W
R/W
1b
1b
1b
AGNDA pin disconnect detection flag
Indicates the AGNDA pin is disconnected. Write 1b to clear this bit to 1b.
0b = AGNDA pin disconnected
1b = AGNDA pin connected
AGNDB pin disconnect detection flag
Indicates the AGNDB pin is disconnected. Write 1b to clear this bit to 1b.
0b = AGNDB pin disconnected
1b = AGNDB pin connected
DGND pin disconnect detection flag
Indicates the DGND pin is disconnected. Write 1b to clear this bit to 1b.
0b = DGND pin disconnected
1b = DGND pin connected
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8.6.1.5 ADC_STATUS Register (Address = 04h) [Reset = FC07h]
Return to the Summary Table.
图8-50. ADC_STATUS Register
15
14
13
12
11
10
9
8
ADC1A_ORn
R/W-1b
ADC1B_ORn
R/W-1b
ADC2A_ORn
R/W-1b
RESERVED
R-1110000000b
7
6
5
4
3
2
1
0
RESERVED
R-1110000000b
MCLK_FAULTn
R/W-1b
OSCD_WDn
R/W-1b
MCLK_WDn
R/W-1b
表8-29. ADC_STATUS Register Field Descriptions
Bit
Field
Type
Reset
Description
15
ADC1A_ORn
ADC1B_ORn
ADC2A_ORn
R/W
1b
ADC1A modulator overrange fault flag
Indicates the ADC1A modulator was overranged. Write 1b to clear this bit to 1b.
0b = Overrange fault occurred
1b = No overrange fault occurred
14
13
R/W
R/W
1b
1b
ADC1B modulator overrange fault flag
Indicates the ADC1B modulator was overranged. Write 1b to clear this bit to 1b.
0b = Overrange fault occurred
1b = No overrange fault occurred
ADC2A modulator overrange fault flag
Indicates the ADC2A modulator was overranged. Write 1b to clear this bit to 1b.
0b = Overrange fault occurred
1b = No overrange fault occurred
12:3
2
RESERVED
R
1110000000b
1b
Reserved
Always reads 1110000000b.
MCLK_FAULTn
R/W
MCLK frequency too high or too low fault flag
Indicates the main clock frequency of the selected clock source either exceeded the clock
frequency high threshold or dropped below the clock frequency low threshold. Write 1b to
clear this bit to 1b.
0b = MCLK frequency too high or too low fault occurred
1b = No MCLK frequency too high or too low fault occurred
1
0
OSCD_WDn
MCLK_WDn
R/W
R/W
1b
1b
Diagnostic oscillator watchdog fault flag
Indicates a diagnostic oscillator watchdog fault occurred. Write 1b to clear this bit to 1b.
0b = Watchdog fault occurred
1b = No watchdog fault occurred
Main clock watchdog fault flag
Indicates a main clock watchdog fault occurred. Write 1b to clear this bit to 1b.
0b = Watchdog fault occurred
1b = No watchdog fault occurred
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8.6.1.6 DIGITAL_STATUS Register (Address = 05h) [Reset = EC00h]
Return to the Summary Table.
图8-51. DIGITAL_STATUS Register
15
14
13
12
11
10
9
1
8
REG_MAP1_CRC_F REG_MAP2_CRC_F REG_MAP3_CRC_F
RESERVED
MEM_MAP_CRC_FA
ULTn
OTP_BANK
RESERVED
AULTn
AULTn
AULTn
R/W-1b
R/W-1b
R/W-1b
R-0b
4
R/W-1b
3
R-1b
2
R-0000000000b
7
6
5
0
RESERVED
R-0000000000b
表8-30. DIGITAL_STATUS Register Field Descriptions
Bit
Field
Type
Reset
Description
15
REG_MAP1_CRC_FAULTn
REG_MAP2_CRC_FAULTn
REG_MAP3_CRC_FAULTn
R/W
1b
Register map section 1 CRC fault flag
Indicates a register map CRC fault in section 1 (register address space from 40h to 59h)
occurred. Write 1b to clear this bit to 1b.
0b = Register map CRC fault occurred
1b = No register map CRC fault occurred
14
13
R/W
R/W
1b
1b
Register map section 2 CRC fault flag
Indicates a register map CRC fault in section 2 (register address space from 80h to A3h)
occurred. Write 1b to clear this bit to 1b.
0b = Register map CRC fault occurred
1b = No register map CRC fault occurred
Register map section 3 CRC fault flag
Indicates a register map CRC fault in section 3 (register address space from C0h to E3h)
occurred. Write 1b to clear this bit to 1b.
0b = Register map CRC fault occurred
1b = No register map CRC fault occurred
12
11
RESERVED
R
0b
1b
Reserved
Always reads 0b.
MEM_MAP_CRC_FAULTn
R/W
Memory map CRC fault flag
Indicates a memory map CRC fault in the internal memory occurred. Write 1b to clear this
bit to 1b. Reset the device in case the flag continues to set to 0b.
0b = Memory map CRC fault occurred
1b = No memory map CRC fault occurred
10
OTP_BANK
RESERVED
R
R
1b
OTP bank indication
Indicates which OTP bank the device selected after reset. The OTP_BANK bit does not
trigger the DIGITAL_FAULTn bit in the STATUS_MSB register. Reset the device in case the
flag indicates that the backup OTP bank is used.
0b = Backup OTP bank (bank 1)
1b = Primary OTP bank (bank 0)
9:0
0000000000b
Reserved
Always reads 0000000000b.
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8.6.1.7 OCC_STATUS Register (Address = 06h) [Reset = 000Fh]
Return to the Summary Table.
图8-52. OCC_STATUS Register
15
14
13
12
11
10
9
8
RESERVED
R-000000000000b
7
6
5
4
3
2
1
0
RESERVED
OCCA_HTn
R/W-1b
OCCA_LTn
R/W-1b
OCCB_HTn
R/W-1b
OCCB_LTn
R/W-1b
R-000000000000b
表8-31. OCC_STATUS Register Field Descriptions
Bit
Field
Type
Reset
Description
15:4
RESERVED
R
000000000000b Reserved
Always reads 000000000000b.
ADC1A overcurrent comparator high threshold fault flag
Indicates the ADC1A digital fast filter output exceeded the set high threshold for the set
amount of conversions. Write 1b to clear this bit to 1b.
0b = High threshold fault occurred
3
OCCA_HTn
OCCA_LTn
OCCB_HTn
OCCB_LTn
R/W
R/W
R/W
R/W
1b
1b
1b
1b
1b = No high threshold fault occurred
2
1
0
ADC1A overcurrent comparator low threshold fault flag
Indicates the ADC1A digital fast filter output dropped below the set low threshold for the set
amount of conversions. Write 1b to clear this bit to 1b.
0b = Low threshold fault occurred
1b = No low threshold fault occurred
ADC1B overcurrent comparator high threshold fault flag
Indicates the ADC1B digital fast filter output exceeded the set high threshold for the set
amount of conversions. Write 1b to clear this bit to 1b.
0b = High threshold fault occurred
1b = No high threshold fault occurred
ADC1B overcurrent comparator low threshold fault flag
Indicates the ADC1B digital fast filter output dropped below the set low threshold for the set
amount of conversions. Write 1b to clear this bit to 1b.
0b = Low threshold fault occurred
1b = No low threshold fault occurred
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8.6.1.8 GPI_DATA Register (Address = 07h) [Reset = 0000h]
Return to the Summary Table.
图8-53. GPI_DATA Register
15
7
14
6
13
5
12
11
10
2
9
1
8
RESERVED
R-000000b
GPI4_DAT[1:0]
R-00b
4
3
0
GPI3_DAT[1:0]
R-00b
GPI2_DAT[1:0]
R-00b
GPI1_DAT[1:0]
R-00b
GPI0_DAT[1:0]
R-00b
表8-32. GPI_DATA Register Field Descriptions
Bit
Field
Type
Reset
Description
15:10
RESERVED
R
000000b
Reserved
Always reads 000000b.
9:8
GPI4_DAT[1:0]
GPI3_DAT[1:0]
GPI2_DAT[1:0]
GPI1_DAT[1:0]
GPI0_DAT[1:0]
R
R
R
R
R
00b
00b
00b
00b
00b
GPIO4 data readback
Readback value of GPIO4 when configured as a digital input or output.
00b = Low (static low or PWM with a low period >66.6%)
01b = Weak low (PWM with a low period ≥50% but ≤66.6%)
10b = Weak high (PWM with a high period >50% but ≤66.6%)
11b = High (static high or PWM with a high period >66.6%)
7:6
5:4
3:2
1:0
GPIO3 data readback
Readback value of GPIO3 when configured as a digital input or output.
00b = Low (static low or PWM with a low period >66.6%)
01b = Weak low (PWM with a low period ≥50% but ≤66.6%)
10b = Weak high (PWM with a high period >50% but ≤66.6%)
11b = High (static high or PWM with a high period >66.6%)
GPIO2 data readback
Readback value of GPIO2 when configured as a digital input or output.
00b = Low (static low or PWM with a low period >66.6%)
01b = Weak low (PWM with a low period ≥50% but ≤66.6%)
10b = Weak high (PWM with a high period >50% but ≤66.6%)
11b = High (static high or PWM with a high period >66.6%)
GPIO1 data readback
Readback value of GPIO1 when configured as a digital input or output.
00b = Low (static low or PWM with a low period >66.6%)
01b = Weak low (PWM with a low period ≥50% but ≤66.6%)
10b = Weak high (PWM with a high period >50% but ≤66.6%)
11b = High (static high or PWM with a high period >66.6%)
GPIO0 data readback
Readback value of GPIO0 when configured as a digital input or output.
00b = Low (static low or PWM with a low period >66.6%)
01b = Weak low (PWM with a low period ≥50% but ≤66.6%)
10b = Weak high (PWM with a high period >50% but ≤66.6%)
11b = High (static high or PWM with a high period >66.6%)
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8.6.1.9 GPIA_GPIB_DATA Register (Address = 08h) [Reset = 0000h]
Return to the Summary Table.
图8-54. GPIA_GPIB_DATA Register
15
14
13
12
11
10
2
9
1
8
0
RESERVED
R-0000b
GPI1A_DAT[1:0]
R-00b
GPI0A_DAT[1:0]
R-00b
7
6
5
4
3
RESERVED
R-0000b
GPI1B_DAT[1:0]
R-00b
GPI0B_DAT[1:0]
R-00b
表8-33. GPIA_GPIB_DATA Register Field Descriptions
Bit
Field
Type
Reset
Description
15:12
RESERVED
R
0000b
Reserved
Always reads 0000b.
11:10
GPI1A_DAT[1:0]
R
00b
GPIO1A data readback
Readback value of GPIO1A when configured as a digital input or output.
00b = Low (static low or PWM with a low period >66.6%)
01b = Weak low (PWM with a low period ≥50% but ≤66.6%)
10b = Weak high (PWM with a high period >50% but ≤66.6%)
11b = High (static high or PWM with a high period >66.6%)
9:8
GPI0A_DAT[1:0]
R
00b
GPIO0A data readback
Readback value of GPIO0A when configured as a digital input or output.
00b = Low (static low or PWM with a low period >66.6%)
01b = Weak low (PWM with a low period ≥50% but ≤66.6%)
10b = Weak high (PWM with a high period >50% but ≤66.6%)
11b = High (static high or PWM with a high period >66.6%)
7:4
3:2
RESERVED
R
R
0000b
00b
Reserved
Always reads 0000b.
GPI1B_DAT[1:0]
GPIO1B data readback
Readback value of GPIO1B when configured as a digital input or output.
00b = Low (static low or PWM with a low period >66.6%)
01b = Weak low (PWM with a low period ≥50% but ≤66.6%)
10b = Weak high (PWM with a high period >50% but ≤66.6%)
11b = High (static high or PWM with a high period >66.6%)
1:0
GPI0B_DAT[1:0]
R
00b
GPIO0B data readback
Readback value of GPIO0B when configured as a digital input or output.
00b = Low (static low or PWM with a low period >66.6%)
01b = Weak low (PWM with a low period ≥50% but ≤66.6%)
10b = Weak high (PWM with a high period >50% but ≤66.6%)
11b = High (static high or PWM with a high period >66.6%)
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8.6.1.10 CONVERSION_CTRL Register (Address = 09h) [Reset = 0000h]
Return to the Summary Table.
图8-55. CONVERSION_CTRL Register
15
14
13
12
11
10
9
8
RESERVED
R-0b
STARTA
R/W-0b
RESERVED
R-0b
STARTB
R/W-0b
RESERVED
R-0b
STOPA
R/W-0b
RESERVED
R-0b
STOPB
R/W-0b
7
6
5
4
3
2
1
0
RESERVED
R-0b
SEQ2A_START
R/W-0b
RESERVED
R-000b
SEQ2A_STOP
R/W-0b
RESERVED
R-00b
表8-34. CONVERSION_CTRL Register Field Descriptions
Bit
Field
Type
Reset
Description
15
RESERVED
R
0b
Reserved
Always reads 0b.
14
13
12
11
10
STARTA
R/W
R
0b
0b
0b
0b
0b
Start or re-start ADC1A conversions
Write 1b to start or restart conversions of enabled ADC1A. Always reads back 0b.
RESERVED
STARTB
Reserved
Always reads 0b.
R/W
R
Start or restart ADC1B conversions
Write 1b to start or restart conversions of enabled ADC1B. Always reads back 0b.
RESERVED
STOPA
Reserved
Always reads 0b.
R/W
Stop ADC1A conversions
Write 1b to stop conversions of ADC1A in continuous-conversion mode. Ongoing
conversions are allowed to complete. The STOPA bit has no effect in single-shot conversion
mode. The STARTA bit takes priority over the STOPA bit if both bits are set during the same
WREG command frame. The STOPA bit clears to 0b after the ongoing conversion finishes
or when the STARTA bit is set before the ongoing conversion finishes, which aborts the
ongoing conversion and restarts new conversions.
9
8
RESERVED
STOPB
R
0b
0b
Reserved
Always reads 0b.
R/W
Stop ADC1B conversions
Write 1b to stop conversions of ADC1B in continuous-conversion mode. Ongoing
conversions are allowed to complete. The STOPB bit has no effect in single-shot conversion
mode. The STARTB bit takes priority over the STOPB bit if both bits are set during the same
WREG command frame. The STOPB bit clears to 0b after the ongoing conversion finishes
or when the STARTB bit is set before the ongoing conversion finishes, which aborts the
ongoing conversion and restarts new conversions.
7
6
RESERVED
R
0b
Reserved
Always reads 0b.
SEQ2A_START
RESERVED
R/W
R
0b
Start ADC2A sequence
Write 1b to start or restart sequence of ADC2A. Always reads back 0b.
5:3
2
000b
0b
Reserved
Always reads 000b.
SEQ2A_STOP
R/W
Stop ADC2A sequence
Write 1b to stop ADC2A sequence. A sequence in progress is allowed to finish. The
SEQ2A_START bit takes priority over the SEQ2A_STOP bit if both bits are set during the
same WREG command frame. The SEQ2A_STOP bit clears to 0b after the ongoing
sequence finishes or when the SEQ2A_START bit is set before the ongoing sequence
finishes, which aborts the ongoing sequence and restarts a new sequence.
1:0
RESERVED
R
00b
Reserved
Always reads 00b.
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8.6.1.11 SEQ2A_STEP0_DATA Register (Address = 10h) [Reset = 0000h]
Return to the Summary Table.
图8-56. SEQ2A_STEP0_DATA Register
15
14
13
12
11
10
9
1
8
0
SEQ2A_STEP0_DAT[15:0]
R-0000000000000000b
7
6
5
4
3
2
SEQ2A_STEP0_DAT[15:0]
R-0000000000000000b
表8-35. SEQ2A_STEP0_DATA Register Field Descriptions
Bit
15:0
Field
Type
Reset
Description
SEQ2A_STEP0_DAT[15:0]
R
0000000000000 ADC2A sequence step 0 conversion data
000b Value provided in two's complement format.
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8.6.1.12 SEQ2A_STEP1_DATA Register (Address = 11h) [Reset = 0000h]
Return to the Summary Table.
图8-57. SEQ2A_STEP1_DATA Register
15
14
13
12
11
10
9
1
8
0
SEQ2A_STEP1_DAT[15:0]
R-0000000000000000b
7
6
5
4
3
2
SEQ2A_STEP1_DAT[15:0]
R-0000000000000000b
表8-36. SEQ2A_STEP1_DATA Register Field Descriptions
Bit
15:0
Field
Type
Reset
Description
SEQ2A_STEP1_DAT[15:0]
R
0000000000000 ADC2A sequence step 1 conversion data
000b
Value provided in two's complement format.
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8.6.1.13 SEQ2A_STEP2_DATA Register (Address = 12h) [Reset = 0000h]
Return to the Summary Table.
图8-58. SEQ2A_STEP2_DATA Register
15
14
13
12
11
10
9
1
8
0
SEQ2A_STEP2_DAT[15:0]
R-0000000000000000b
7
6
5
4
3
2
SEQ2A_STEP2_DAT[15:0]
R-0000000000000000b
表8-37. SEQ2A_STEP2_DATA Register Field Descriptions
Bit
15:0
Field
Type
Reset
Description
SEQ2A_STEP2_DAT[15:0]
R
0000000000000 ADC2A sequence step 2 conversion data
000b Value provided in two's complement format.
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8.6.1.14 SEQ2A_STEP3_DATA Register (Address = 13h) [Reset = 0000h]
Return to the Summary Table.
图8-59. SEQ2A_STEP3_DATA Register
15
14
13
12
11
10
9
1
8
0
SEQ2A_STEP3_DAT[15:0]
R-0000000000000000b
7
6
5
4
3
2
SEQ2A_STEP3_DAT[15:0]
R-0000000000000000b
表8-38. SEQ2A_STEP3_DATA Register Field Descriptions
Bit
15:0
Field
Type
Reset
Description
SEQ2A_STEP3_DAT[15:0]
R
0000000000000 ADC2A sequence step 3 conversion data
000b
Value provided in two's complement format.
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8.6.1.15 SEQ2A_STEP4_DATA Register (Address = 14h) [Reset = 0000h]
Return to the Summary Table.
图8-60. SEQ2A_STEP4_DATA Register
15
14
13
12
11
10
9
1
8
0
SEQ2A_STEP4_DAT[15:0]
R-0000000000000000b
7
6
5
4
3
2
SEQ2A_STEP4_DAT[15:0]
R-0000000000000000b
表8-39. SEQ2A_STEP4_DATA Register Field Descriptions
Bit
15:0
Field
Type
Reset
Description
SEQ2A_STEP4_DAT[15:0]
R
0000000000000 ADC2A sequence step 4 conversion data
000b Value provided in two's complement format.
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8.6.1.16 SEQ2A_STEP5_DATA Register (Address = 15h) [Reset = 0000h]
Return to the Summary Table.
图8-61. SEQ2A_STEP5_DATA Register
15
14
13
12
11
10
9
1
8
0
SEQ2A_STEP5_DAT[15:0]
R-0000000000000000b
7
6
5
4
3
2
SEQ2A_STEP5_DAT[15:0]
R-0000000000000000b
表8-40. SEQ2A_STEP5_DATA Register Field Descriptions
Bit
15:0
Field
Type
Reset
Description
SEQ2A_STEP5_DAT[15:0]
R
0000000000000 ADC2A sequence step 5 conversion data
000b
Value provided in two's complement format.
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8.6.1.17 SEQ2A_STEP6_DATA Register (Address = 16h) [Reset = 0000h]
Return to the Summary Table.
图8-62. SEQ2A_STEP6_DATA Register
15
14
13
12
11
10
9
1
8
0
SEQ2A_STEP6_DAT[15:0]
R-0000000000000000b
7
6
5
4
3
2
SEQ2A_STEP6_DAT[15:0]
R-0000000000000000b
表8-41. SEQ2A_STEP6_DATA Register Field Descriptions
Bit
15:0
Field
Type
Reset
Description
SEQ2A_STEP6_DAT[15:0]
R
0000000000000 ADC2A sequence step 6 conversion data
000b Value provided in two's complement format.
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8.6.1.18 SEQ2A_STEP7_DATA Register (Address = 17h) [Reset = 0000h]
Return to the Summary Table.
图8-63. SEQ2A_STEP7_DATA Register
15
14
13
12
11
10
9
1
8
0
SEQ2A_STEP7_DAT[15:0]
R-0000000000000000b
7
6
5
4
3
2
SEQ2A_STEP7_DAT[15:0]
R-0000000000000000b
表8-42. SEQ2A_STEP7_DATA Register Field Descriptions
Bit
15:0
Field
Type
Reset
Description
SEQ2A_STEP7_DAT[15:0]
R
0000000000000 ADC2A sequence step 7 conversion data
000b
Value provided in two's complement format.
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8.6.1.19 SEQ2A_STEP8_DATA Register (Address = 18h) [Reset = 0000h]
Return to the Summary Table.
图8-64. SEQ2A_STEP8_DATA Register
15
14
13
12
11
10
9
1
8
0
SEQ2A_STEP8_DAT[15:0]
R-0000000000000000b
7
6
5
4
3
2
SEQ2A_STEP8_DAT[15:0]
R-0000000000000000b
表8-43. SEQ2A_STEP8_DATA Register Field Descriptions
Bit
15:0
Field
Type
Reset
Description
SEQ2A_STEP8_DAT[15:0]
R
0000000000000 ADC2A sequence step 8 conversion data
000b Value provided in two's complement format.
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8.6.1.20 SEQ2A_STEP9_DATA Register (Address = 19h) [Reset = 0000h]
Return to the Summary Table.
图8-65. SEQ2A_STEP9_DATA Register
15
14
13
12
11
10
9
1
8
0
SEQ2A_STEP9_DAT[15:0]
R-0000000000000000b
7
6
5
4
3
2
SEQ2A_STEP9_DAT[15:0]
R-0000000000000000b
表8-44. SEQ2A_STEP9_DATA Register Field Descriptions
Bit
15:0
Field
Type
Reset
Description
SEQ2A_STEP9_DAT[15:0]
R
0000000000000 ADC2A sequence step 9 conversion data
000b
Value provided in two's complement format.
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8.6.1.21 SEQ2A_STEP10_DATA Register (Address = 1Ah) [Reset = 0000h]
Return to the Summary Table.
图8-66. SEQ2A_STEP10_DATA Register
15
14
13
12
11
10
9
1
8
0
SEQ2A_STEP10_DAT[15:0]
R-0000000000000000b
7
6
5
4
3
2
SEQ2A_STEP10_DAT[15:0]
R-0000000000000000b
表8-45. SEQ2A_STEP10_DATA Register Field Descriptions
Bit
15:0
Field
Type
Reset
Description
SEQ2A_STEP10_DAT[15:0]
R
0000000000000 ADC2A sequence step 10 conversion data
000b Value provided in two's complement format.
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8.6.1.22 SEQ2A_STEP11_DATA Register (Address = 1Bh) [Reset = 0000h]
Return to the Summary Table.
图8-67. SEQ2A_STEP11_DATA Register
15
14
13
12
11
10
9
1
8
0
SEQ2A_STEP11_DAT[15:0]
R-0000000000000000b
7
6
5
4
3
2
SEQ2A_STEP11_DAT[15:0]
R-0000000000000000b
表8-46. SEQ2A_STEP11_DATA Register Field Descriptions
Bit
15:0
Field
Type
Reset
Description
SEQ2A_STEP11_DAT[15:0]
R
0000000000000 ADC2A sequence step 11 conversion data
000b
Value provided in two's complement format.
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8.6.1.23 SEQ2A_STEP12_DATA Register (Address = 1Ch) [Reset = 0000h]
Return to the Summary Table.
图8-68. SEQ2A_STEP12_DATA Register
15
14
13
12
11
10
9
1
8
0
SEQ2A_STEP12_DAT[15:0]
R-0000000000000000b
7
6
5
4
3
2
SEQ2A_STEP12_DAT[15:0]
R-0000000000000000b
表8-47. SEQ2A_STEP12_DATA Register Field Descriptions
Bit
15:0
Field
Type
Reset
Description
SEQ2A_STEP12_DAT[15:0]
R
0000000000000 ADC2A sequence step 12 conversion data
000b Value provided in two's complement format.
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8.6.1.24 SEQ2A_STEP13_DATA Register (Address = 1Dh) [Reset = 0000h]
Return to the Summary Table.
图8-69. SEQ2A_STEP13_DATA Register
15
14
13
12
11
10
9
1
8
0
SEQ2A_STEP13_DAT[15:0]
R-0000000000000000b
7
6
5
4
3
2
SEQ2A_STEP13_DAT[15:0]
R-0000000000000000b
表8-48. SEQ2A_STEP13_DATA Register Field Descriptions
Bit
15:0
Field
Type
Reset
Description
SEQ2A_STEP13_DAT[15:0]
R
0000000000000 ADC2A sequence step 13 conversion data
000b
Value provided in two's complement format.
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8.6.1.25 SEQ2A_STEP14_DATA Register (Address = 1Eh) [Reset = 0000h]
Return to the Summary Table.
图8-70. SEQ2A_STEP14_DATA Register
15
14
13
12
11
10
9
1
8
0
SEQ2A_STEP14_DAT[15:0]
R-0000000000000000b
7
6
5
4
3
2
SEQ2A_STEP14_DAT[15:0]
R-0000000000000000b
表8-49. SEQ2A_STEP14_DATA Register Field Descriptions
Bit
15:0
Field
Type
Reset
Description
SEQ2A_STEP14_DAT[15:0]
R
0000000000000 ADC2A sequence step 14 conversion data
000b Value provided in two's complement format.
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8.6.1.26 SEQ2A_STEP15_DATA Register (Address = 1Fh) [Reset = 0000h]
Return to the Summary Table.
图8-71. SEQ2A_STEP15_DATA Register
15
14
13
12
11
10
9
1
8
0
SEQ2A_STEP15_DAT[15:0]
R-0000000000000000b
7
6
5
4
3
2
SEQ2A_STEP15_DAT[15:0]
R-0000000000000000b
表8-50. SEQ2A_STEP15_DATA Register Field Descriptions
Bit
15:0
Field
Type
Reset
Description
SEQ2A_STEP15_DAT[15:0]
R
0000000000000 ADC2A sequence step 15 conversion data
000b
Value provided in two's complement format.
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8.6.1.27 DEVICE_MONITOR_CFG Register (Address = 40h) [Reset = 3000h]
Return to the Summary Table.
图8-72. DEVICE_MONITOR_CFG Register
15
14
13
12
11
10
9
1
8
REG_MAP1_CRC_E
N
CRC_TYPE
SCLK_COUNTER_E
N
TIMEOUT_EN
RESERVED
FAULT_POL
R/W-0b
7
R/W-0b
6
R/W-1b
R/W-1b
4
R-000b
R/W-0b
0
5
3
2
RESERVED
R-00000b
MHD_POL
R/W-0b
MHD_CFG[1:0]
R/W-00b
表8-51. DEVICE_MONITOR_CFG Register Field Descriptions
Bit
Field
Type
Reset
Description
15
REG_MAP1_CRC_EN
R/W
0b
Register map section 1 CRC enable
Enables the register map CRC for section 1 (register address space from 40h to 59h).
0b = Disabled
1b = Enabled
14
13
12
CRC_TYPE
R/W
R/W
R/W
0b
1b
1b
CRC type selection
Selects the CRC polynomial that is used for the SPI and register map CRC calculation.
0b = 16-bit CCITT
1b = 16-bit ANSI
SCLK_COUNTER_EN
TIMEOUT_EN
SCLK counter enable
Enables the SCLK counter.
0b = Disabled
1b = Enabled
SPI timeout enable
Enables the SPI timeout. When enabled the timeout checks that a rising edge of CSn
happens within 214 tOSCD cycles after a CSn falling edge. When a timeout occurs, the
remainder of the SPI frame on SDI is ignored before the rising edge of CSn. A new SPI
transaction starts at the next CSn falling edge.
0b = Disabled
1b = Enabled
11:9
8
RESERVED
FAULT_POL
R
000b
0b
Reserved
Always reads back 000b.
R/W
FAULT pin polarity selection
Selects the polarity of the FAULT pin. The actual output behavior of the GPIO2/FAULT pin,
when configured as a FAULT output in the GPIO2_SRC bit, depends on the GPIO2_FMT
setting. A FAULT is active when any of the non-masked STATUS_MSB[14:7] bits are active.
0b = Active low. In case of a fault a logic low level is driven.
1b = Active high. In case of a fault a logic high level is driven.
7:3
2
RESERVED
MHD_POL
R
00000b
0b
Reserved
Always reads back 00000b.
R/W
Missing host detection fault pin polarity selection
Selects the polarity of the MHD pin. The actual output behavior of the GPIO0/MHD pin,
when configured as an MHD output in the GPIO0_SRC bit, depends on the GPIO0_FMT
setting.
0b = Active low. In case of a fault a logic low level is driven.
1b = Active high. In case of a fault a logic high level is driven.
1:0
MHD_CFG[1:0]
R/W
00b
Missing host detection configuration
Detects when the host is not communicating with the device anymore. A watchdog timer
checks the time between two valid commands with a valid CRC. If a valid command with a
valid CRC is not received within the watchdog time window, the host is considered missing.
When the watchdog times out, the GPIO0/MHD pin is set to active. To use the missing host
detection mode, configure the GPIO0/MHD pin as an output using the GPIO0_DIR bit and
the source for missing host detection mode using the GPIO0_SRC bit. To reset the
GPIO0/MHD output after a missing host was detected, disable the missing host detection
mode by setting MHD_CFG = 00b.
00b = Disabled
01b = 5120 x tOSCD (= 0.625 ms for fOSCD = 8.192 MHz)
10b = 10240 x tOSCD (= 1.25 ms for fOSCD = 8.192 MHz)
11b = 20480 x tOSCD (= 2.5 ms for fOSCD = 8.192 MHz)
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8.6.1.28 SUPPLY_MONITOR_CFG1 Register (Address = 41h) [Reset = FFFFh]
Return to the Summary Table.
图8-73. SUPPLY_MONITOR_CFG1 Register
15
14
13
12
11
10
9
8
AVDD_OV_EN
R/W-1b
AVDD_UV_EN
R/W-1b
IOVDD_OV_EN
R/W-1b
IOVDD_UV_EN
R/W-1b
DVDD_OV_EN
R/W-1b
DVDD_UV_EN
R/W-1b
AVDD_OSC_EN
R/W-1b
IOVDD_OSC_EN
R/W-1b
7
6
5
4
3
2
1
0
DVDD_OSC_EN
R/W-1b
AVDD_OTW_EN
R/W-1b
IOVDD_OTW_EN
R/W-1b
AVDD_CL_EN
R/W-1b
IOVDD_CL_EN
R/W-1b
AGNDA_DISC_EN
R/W-1b
AGNDB_DISC_EN
R/W-1b
DGND_DISC_EN
R/W-1b
表8-52. SUPPLY_MONITOR_CFG1 Register Field Descriptions
Bit
Field
Type
Reset
Description
15
AVDD_OV_EN
R/W
1b
AVDD LDO overvoltage monitor enable
Enables the AVDD LDO output overvoltage monitor.
0b = Disabled
1b = Enabled
14
13
12
11
10
9
AVDD_UV_EN
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1b
1b
1b
1b
1b
1b
1b
1b
1b
1b
1b
1b
1b
1b
AVDD LDO undervoltage monitor enable
Enables the AVDD LDO output undervoltage monitor.
0b = Disabled
1b = Enabled
IOVDD_OV_EN
IOVDD_UV_EN
DVDD_OV_EN
DVDD_UV_EN
AVDD_OSC_EN
IOVDD_OSC_EN
DVDD_OSC_EN
AVDD_OTW_EN
IOVDD_OTW_EN
AVDD_CL_EN
IOVDD LDO overvoltage monitor enable
Enables the IOVDD LDO output overvoltage monitor.
0b = Disabled
1b = Enabled
IOVDD LDO undervoltage monitor enable
Enables the IOVDD LDO output undervoltage monitor.
0b = Disabled
1b = Enabled
DVDD LDO overvoltage monitor enable
Enables the DVDD LDO output overvoltage monitor.
0b = Disabled
1b = Enabled
DVDD LDO undervoltage monitor enable
Enables the DVDD LDO output undervoltage monitor.
0b = Disabled
1b = Enabled
AVDD LDO oscillation monitor enable
Enables the AVDD LDO output oscillation monitor.
0b = Disabled
1b = Enabled
8
IOVDD LDO oscillation monitor enable
Enables the IOVDD LDO output oscillation monitor.
0b = Disabled
1b = Enabled
7
DVDD LDO oscillation monitor enable
Enables the DVDD LDO output oscillation monitor.
0b = Disabled
1b = Enabled
6
AVDD LDO overtemperature warning monitor enable
Enables the AVDD LDO overtemperature warning monitor.
0b = Disabled
1b = Enabled
5
IOVDD LDO overtemperature warning monitor enable
Enables the IOVDD LDO overtemperature warning monitor.
0b = Disabled
1b = Enabled
4
AVDD LDO current limit enable
Enables the AVDD LDO current limit.
0b = Disabled
1b = Enabled
3
IOVDD_CL_EN
AGNDA_DISC_EN
AGNDB_DISC_EN
IOVDD LDO current limit enable
Enables the IOVDD LDO current limit.
0b = Disabled
1b = Enabled
2
AGNDA disconnect monitor enable
Enables the AGNDA disconnect monitor.
0b = Disabled
1b = Enabled
1
AGNDB disconnect monitor enable
Enables the AGNDB disconnect monitor.
0b = Disabled
1b = Enabled
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表8-52. SUPPLY_MONITOR_CFG1 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
0
DGND_DISC_EN
R/W
1b
DGND disconnect monitor enable
Enables the DGND disconnect monitor.
0b = Disabled
1b = Enabled
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8.6.1.29 SUPPLY_MONITOR_CFG2 Register (Address = 42h) [Reset = 10F0h]
Return to the Summary Table.
图8-74. SUPPLY_MONITOR_CFG2 Register
15
14
13
12
11
10
9
1
8
0
RESERVED
R-00b
IOVDD_OV_TH
R/W-0b
IOVDD_UV_TH
R/W-1b
RESERVED
R-0000b
7
6
5
4
3
2
AVDD_OTW_CFG[1:0]
R/W-11b
IOVDD_OTW_CFG[1:0]
R/W-11b
RESERVED
R-0000b
表8-53. SUPPLY_MONITOR_CFG2 Register Field Descriptions
Bit
Field
Type
Reset
Description
15:14
RESERVED
R
00b
Reserved
Always reads back 00b.
13
12
IOVDD_OV_TH
IOVDD_UV_TH
RESERVED
R/W
R/W
0b
1b
IOVDD overvoltage threshold selection
Selects the threshold for the IOVDD LDO output overvoltage monitor.
0b = 5.7 V
1b = 3.9 V
IOVDD undervoltage threshold selection
Selects the threshold for the IOVDD LDO output undervoltage monitor.
0b = 4.3 V
1b = 2.95 V
11:8
7:6
R
0000b
11b
Reserved
Always reads back 0000b.
AVDD_OTW_CFG[1:0]
R/W
AVDD LDO overtemperature warning threshold selection
Selects the threshold for AVDD LDO overtemperature warning.
00b = #dash<deg#C
01b = 100°C
10b = 120°C
11b = 140°C
5:4
3:0
IOVDD_OTW_CFG[1:0]
R/W
11b
IOVDD LDO overtemperature warning threshold selection
Selects the threshold for IOVDD LDO overtemperature warning.
00b = #dash<deg#C
01b = 100°C
10b = 120°C
11b = 140°C
RESERVED
R
0000b
Reserved
Always reads back 0000b.
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8.6.1.30 ADC_MONITOR_CFG Register (Address = 43h) [Reset = FC07h]
Return to the Summary Table.
图8-75. ADC_MONITOR_CFG Register
15
14
13
12
11
10
9
1
8
ADC1A_OR_EN
R/W-1b
ADC1B_OR_EN
R/W-1b
ADC2A_OR_EN
R/W-1b
SPARE[2:0]
R/W-111b
RESERVED
R-0000000b
7
6
5
4
3
2
0
RESERVED
R-0000000b
MCLK_MON_EN
R/W-1b
OSCD_WD_EN
R/W-1b
MCLK_WD_EN
R/W-1b
表8-54. ADC_MONITOR_CFG Register Field Descriptions
Bit
Field
ADC1A_OR_EN
Type
Reset
Description
15
R/W
1b
ADC1A modulator overrange detection monitor enable
Enables the ADC1A modulator overrange detection monitor.
0b = Disabled
1b = Enabled
14
13
ADC1B_OR_EN
ADC2A_OR_EN
SPARE[2:0]
R/W
R/W
R/W
1b
ADC1B modulator overrange detection monitor enable
Enables the ADC1B modulator overrange detection monitor.
0b = Disabled
1b = Enabled
1b
ADC2A modulator overrange detection monitor enable
Enables the ADC2A modulator overrange detection monitor.
0b = Disabled
1b = Enabled
12:10
111b
Spare bits
Provided as R/W bits as a means to check the register map section 1 CRC. Bit settings
have no effect.
9:3
2
RESERVED
R
0000000b
1b
Reserved
Always reads back 0000000b.
MCLK_MON_EN
R/W
MCLK monitor enable
Enables the main clock frequency monitor.
0b = Disabled
1b = Enabled
1
0
OSCD_WD_EN
MCLK_WD_EN
R/W
R/W
1b
1b
Diagnostic oscillator watchdog enable
Enables the diagnostic oscillator watchdog.
0b = Disabled
1b = Enabled
Main clock watchdog enable
Enables the main clock watchdog.
0b = Disabled
1b = Enabled
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8.6.1.31 SUPPLY_MONITOR_DIAGNOSTIC_CFG Register (Address = 44h) [Reset = 0000h]
Return to the Summary Table.
图8-76. SUPPLY_MONITOR_DIAGNOSTIC_CFG Register
15
14
13
12
11
10
9
8
AVDD_OV_DIAG_EN AVDD_UV_DIAG_EN IOVDD_OV_DIAG_E IOVDD_UV_DIAG_E DVDD_OV_DIAG_E DVDD_UV_DIAG_E AVDD_OSC_DIAG_E IOVDD_OSC_DIAG_
N
N
N
N
N
EN
R/W-0b
7
R/W-0b
6
R/W-0b
R/W-0b
R/W-0b
R/W-0b
R/W-0b
R/W-0b
5
4
3
2
1
0
DVDD_OSC_DIAG_
EN
RESERVED
R-0000b
AGNDA_DISC_DIAG AGNDB_DISC_DIAG DGND_DISC_DIAG_
_EN
_EN
EN
R/W-0b
R/W-0b
R/W-0b
R/W-0b
表8-55. SUPPLY_MONITOR_DIAGNOSTIC_CFG Register Field Descriptions
Bit
Field
Type
Reset
Description
15
AVDD_OV_DIAG_EN
AVDD_UV_DIAG_EN
IOVDD_OV_DIAG_EN
IOVDD_UV_DIAG_EN
DVDD_OV_DIAG_EN
DVDD_UV_DIAG_EN
AVDD_OSC_DIAG_EN
IOVDD_OSC_DIAG_EN
DVDD_OSC_DIAG_EN
RESERVED
R/W
0b
AVDD LDO overvoltage monitor diagnostic enable
Enables the AVDD LDO output overvoltage monitor diagnostic. AVDD_OV_EN must be set
for the diagnostic to work. The AVDD_OVn fault flag sets within tp(AVDD_OV) when the
diagnostic completed successfully.
0b = Disabled
1b = Enabled
14
13
12
11
10
9
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
0b
AVDD LDO undervoltage monitor diagnostic enable
Enables the AVDD LDO output undervoltage monitor diagnostic. AVDD_UV_EN must be set
for the diagnostic to work. The AVDD_UVn fault flag sets within tp(AVDD_UV) when the
diagnostic completed successfully.
0b = Disabled
1b = Enabled
0b
IOVDD LDO overvoltage monitor diagnostic enable
Enables the IOVDD LDO output overvoltage monitor diagnostic. IOVDD_OV_EN must be
set for the diagnostic to work. The IOVDD_OVn fault flag sets within tp(IOVDD._OV) when the
diagnostic completed successfully.
0b = Disabled
1b = Enabled
0b
IOVDD LDO undervoltage monitor diagnostic enable
Enables the IOVDD LDO output undervoltage monitor diagnostic. IOVDD_UV_EN must be
set for the diagnostic to work. The IOVDD_UVn fault flag sets within tp(IOVDD_UV) when the
diagnostic completed successfully.
0b = Disabled
1b = Enabled
0b
DVDD LDO overvoltage monitor diagnostic enable
Enables the DVDD LDO output overvoltage monitor diagnostic. DVDD_OV_EN must be set
for the diagnostic to work. The DVDD_OVn fault flag sets within tp(DVDD_OV) when the
diagnostic completed successfully.
0b = Disabled
1b = Enabled
0b
DVDD LDO undervoltage monitor diagnostic enable
Enables the DVDD LDO output undervoltage monitor diagnostic. DVDD_UV_EN must be
set for the diagnostic to work. The DVDD_UVn fault flag sets within tp(DVDD_UV) when the
diagnostic completed successfully.
0b = Disabled
1b = Enabled
0b
AVDD LDO oscillation monitor diagnostic enable
Enables the AVDD LDO output oscillation monitor diagnostic. AVDD_OSC_EN must be set
for the diagnostic to work. The AVDD_OSCn fault flag sets within tp(AVDD_OSC) when the
diagnostic completed successfully.
0b = Disabled
1b = Enabled
8
0b
IOVDD LDO oscillation monitor diagnostic enable
Enables the IOVDD LDO output oscillation monitor diagnostic. IOVDD_OSC_EN must be
set for the diagnostic to work. The IOVDD_OSCn fault flag sets within tp(IOVDD_OSC) when
the diagnostic completed successfully.
0b = Disabled
1b = Enabled
7
0b
DVDD LDO oscillation monitor diagnostic enable
Enables the DVDD LDO output oscillation monitor diagnostic. DVDD_OSC_EN must be set
for the diagnostic to work. The DVDD_OSCn fault flag sets within tp(DVDD_OSC) when the
diagnostic completed successfully.
0b = Disabled
1b = Enabled
6:3
0000b
Reserved
Always reads back 0000b.
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表8-55. SUPPLY_MONITOR_DIAGNOSTIC_CFG Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
2
AGNDA_DISC_DIAG_EN
R/W
0b
AGNDA disconnect monitor diagnostic enable
Enables the AGNDA disconnect monitor diagnostic. AGNDA_DISC_EN must be set for the
diagnostic to work. The AGNDA_DISCn fault flag sets within tp(AGNDA_OPEN) when the
diagnostic completed successfully.
0b = Disabled
1b = Enabled
1
0
AGNDB_DISC_DIAG_EN
DGND_DISC_DIAG_EN
R/W
R/W
0b
0b
AGNDB disconnect monitor diagnostic enable
Enables the AGNDB disconnect monitor diagnostic. AGNDB_DISC_EN must be set for the
diagnostic to work. The AGNDB_DISCn fault flag sets within tp(AGNDB_OPEN) when the
diagnostic completed successfully.
0b = Disabled
1b = Enabled
DGND disconnect monitor diagnostic enable
Enables the DGND disconnect monitor diagnostic. DGND_DISC_EN must be set for the
diagnostic to work. The DGND_DISCn fault flag sets within tp(DGND_OPEN) when the
diagnostic completed successfully.
0b = Disabled
1b = Enabled
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8.6.1.32 ADC_MONITOR_DIAGNOSTIC_CFG Register (Address = 45h) [Reset = 0000h]
Return to the Summary Table.
图8-77. ADC_MONITOR_DIAGNOSTIC_CFG Register
15
14
13
12
11
10
9
8
0
SPARE[11:0]
R/W-000000000000b
7
6
5
4
3
2
1
SPARE[11:0]
MCLK_HI_DIAG_EN MCLK_LO_DIAG_EN OSCD_WD_DIAG_E MCLK_WD_DIAG_E
N
N
R/W-000000000000b
R/W-0b
R/W-0b
R/W-0b
R/W-0b
表8-56. ADC_MONITOR_DIAGNOSTIC_CFG Register Field Descriptions
Bit
Field
Type
Reset
Description
15:4
SPARE[11:0]
R/W
000000000000b Spare bits
Provided as R/W bits as a means to check the register map section 1 CRC. Bit settings
have no effect.
3
MCLK_HI_DIAG_EN
MCLK_LO_DIAG_EN
R/W
R/W
0b
0b
MCLK frequency too high monitor diagnostic enable
Enables the main clock frequency too high monitor diagnostic. MCLK_MON_EN must be set
for the diagnostic to work. The MCLK_FAULTn fault flag sets within tp(MCLK_FAULT) when the
diagnostic completed successfully. Do not enable the MCLK_LO_DIAG_EN at the same
time. Execute the MCLK_HI_DIAG_EN and MCLK_LO_DIAG_EN sequentially.
0b = Disabled
1b = Enabled
2
MCLK frequency too low monitor diagnostic enable
Enables the main clock frequency too low monitor diagnostic. MCLK_MON_EN must be set
for the diagnostic to work. The MCLK_FAULTn fault flag sets within tp(MCLK_FAULT) when the
diagnostic completed successfully. Do not enable the MCLK_HI_DIAG_EN at the same
time. Execute the MCLK_HI_DIAG_EN and MCLK_LO_DIAG_EN sequentially.
0b = Disabled
1b = Enabled
1
0
OSCD_WD_DIAG_EN
MCLK_WD_DIAG_EN
R/W
R/W
0b
0b
Diagnostic oscillator watchdog diagnostic enable
Enables the diagnostic oscillator watchdog diagnostic. OSCD_WD_EN must be set for the
diagnostic to work. The OSCD_WDn fault flag sets within tp(OSCD_WD) when the diagnostic
completed successfully.
0b = Disabled
1b = Enabled
Main clock watchdog diagnostic enable
Enables the main clock watchdog diagnostic. MCLK_WD_EN must be set for the diagnostic
to work. The MCLK_WDn fault flag sets within tp(MCLK_WD) when the diagnostic completed
successfully.
0b = Disabled
1b = Enabled
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8.6.1.33 DIGITAL_MONITOR_DIAGNOSTIC_CFG Register (Address = 46h) [Reset = 0000h]
Return to the Summary Table.
图8-78. DIGITAL_MONITOR_DIAGNOSTIC_CFG Register
15
14
13
12
11
10
9
8
RESERVED
R-000000b
MEM_MAP_CRC_DIAG[1:0]
R/W-00b
7
6
5
4
3
2
1
0
RESERVED
R-00000b
GPIOA_DIAG_EN
R/W-0b
GPIOB_DIAG_EN
R/W-0b
GPIO_DIAG_EN
R/W-0b
表8-57. DIGITAL_MONITOR_DIAGNOSTIC_CFG Register Field Descriptions
Bit
Field
Type
Reset
Description
15:10
RESERVED
R
000000b
Reserved
Always reads back 000000b.
9:8
MEM_MAP_CRC_DIAG[1:0]
R/W
00b
Memory map CRC diagnostic bit pattern selection
Selects the bit pattern to use for the memory map CRC diagnostic. The
MEM_MAP_CRC_FAULTn fault flag sets within tp(MEM_MAP_CRC) when the diagnostic
completed successfully. Any of the three available bit patterns can be used for the
diagnostic.
00b = Disabled
01b = Pattern 1
10b = Pattern 2
11b = Pattern 3
7:3
2
RESERVED
R
00000b
0b
Reserved
Always reads back 00000b.
GPIOA_DIAG_EN
R/W
GPIOA readback diagnostic enable
Inverts the readback value of the GPIxA_DAT[1:0] bits if GPIOxA_DIR is configured as a
digital output.
0b = Disabled
1b = Enabled
1
0
GPIOB_DIAG_EN
GPIO_DIAG_EN
R/W
R/W
0b
0b
GPIOB readback diagnostic enable
Inverts the readback value of the GPIxB_DAT[1:0] bits if GPIOxB_DIR is configured as a
digital output.
0b = Disabled
1b = Enabled
GPIO readback diagnostic enable
Inverts the readback value of the GPIx_DAT[1:0] bits if GPIOx_DIR is configured as a digital
output.
0b = Disabled
1b = Enabled
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8.6.1.34 SUPPLY_FAULT_MASK Register (Address = 47h) [Reset = 0000h]
Return to the Summary Table.
图8-79. SUPPLY_FAULT_MASK Register
15
14
13
12
11
10
9
8
AVDD_OV_MASK
R/W-0b
AVDD_UV_MASK
R/W-0b
IOVDD_OV_MASK
R/W-0b
IOVDD_UV_MASK
R/W-0b
DVDD_OV_MASK
R/W-0b
DVDD_UV_MASK
R/W-0b
AVDD_OSC_MASK IOVDD_OSC_MASK
R/W-0b
1
R/W-0b
0
7
6
5
4
3
2
DVDD_OSC_MASK AVDD_OTW_MASK IOVDD_OTW_MASK
AVDD_CL_MASK
IOVDD_CL_MASK
AGNDA_DISC_MAS AGNDB_DISC_MAS DGND_DISC_MASK
K
K
R/W-0b
R/W-0b
R/W-0b
R/W-0b
R/W-0b
R/W-0b
R/W-0b
R/W-0b
表8-58. SUPPLY_FAULT_MASK Register Field Descriptions
Bit
Field
Type
Reset
Description
15
AVDD_OV_MASK
AVDD_UV_MASK
IOVDD_OV_MASK
IOVDD_UV_MASK
DVDD_OV_MASK
DVDD_UV_MASK
AVDD_OSC_MASK
IOVDD_OSC_MASK
DVDD_OSC_MASK
AVDD_OTW_MASK
IOVDD_OTW_MASK
AVDD_CL_MASK
R/W
0b
AVDD overvoltage fault flag mask
Masks the AVDD overvoltage fault flag (AVDD_OVn) from triggering the SUPPLY_FAULTn
flag in the STATUS_MSB register.
0b = Unmasked
1b = Masked
14
13
12
11
10
9
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0b
0b
0b
0b
0b
0b
0b
0b
0b
0b
0b
AVDD undervoltage fault flag mask
Masks the AVDD undervoltage fault flag (AVDD_UVn) from triggering the SUPPLY_FAULTn
flag in the STATUS_MSB register.
0b = Unmasked
1b = Masked
IOVDD overvoltage fault flag mask
Masks the IOVDD overvoltage fault flag (IOVDD_OVn) from triggering the
SUPPLY_FAULTn flag in the STATUS_MSB register.
0b = Unmasked
1b = Masked
IOVDD undervoltage fault flag mask
Masks the IOVDD undervoltage fault flag (IOVDD_UVn) from triggering the
SUPPLY_FAULTn flag in the STATUS_MSB register.
0b = Unmasked
1b = Masked
DVDD overvoltage fault flag mask
Masks the DVDD overvoltage fault flag (DVDD_OVn) from triggering the SUPPLY_FAULTn
flag in the STATUS_MSB register.
0b = Unmasked
1b = Masked
DVDD undervoltage fault flag mask
Masks the DVDD undervoltage fault flag (DVDD_UVn) from triggering the SUPPLY_FAULTn
flag in the STATUS_MSB register.
0b = Unmasked
1b = Masked
AVDD oscillation fault flag mask
Masks the AVDD oscillation fault flag (AVDD_OSCn) from triggering the SUPPLY_FAULTn
flag in the STATUS_MSB register.
0b = Unmasked
1b = Masked
8
IOVDD oscillation fault flag mask
Masks the IOVDD oscillation fault flag (IOVDD_OSCn) from triggering the SUPPLY_FAULTn
flag in the STATUS_MSB register.
0b = Unmasked
1b = Masked
7
DVDD oscillation fault flag mask
Masks the DVDD oscillation fault flag (DVDD_OSCn) from triggering the SUPPLY_FAULTn
flag in the STATUS_MSB register.
0b = Unmasked
1b = Masked
6
AVDD overtemperature warning flag mask
Masks the AVDD LDO overtemperature warning flag (AVDD_OTWn) from triggering the
SUPPLY_FAULTn flag in the STATUS_MSB register.
0b = Unmasked
1b = Masked
5
IOVDD overtemperature warning flag mask
Masks the IOVDD LDO overtemperature warning flag (IOVDD_OTWn) from triggering the
SUPPLY_FAULTn flag in the STATUS_MSB register.
0b = Unmasked
1b = Masked
4
AVDD current limit flag mask
Masks the AVDD LDO current limit flag (AVDD_CLn) from triggering the SUPPLY_FAULTn
flag in the STATUS_MSB register.
0b = Unmasked
1b = Masked
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表8-58. SUPPLY_FAULT_MASK Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
3
IOVDD_CL_MASK
R/W
0b
IOVDD current limit flag mask
Masks the IOVDD LDO current limit flag (IOVDD_CLn) from triggering the
SUPPLY_FAULTn flag in the STATUS_MSB register.
0b = Unmasked
1b = Masked
2
1
0
AGNDA_DISC_MASK
AGNDB_DISC_MASK
DGND_DISC_MASK
R/W
R/W
R/W
0b
0b
0b
AGNDA pin disconnect detection flag mask
Masks the AGNDA pin disconnect detection flag (AGNDA_DISCn) from triggering the
SUPPLY_FAULTn flag in the STATUS_MSB register.
0b = Unmasked
1b = Masked
AGNDB pin disconnect detection flag mask
Masks the AGNDB pin disconnect detection flag (AGNDB_DISCn) from triggering the
SUPPLY_FAULTn flag in the STATUS_MSB register.
0b = Unmasked
1b = Masked
DGND pin disconnect detection flag mask
Masks the DGND pin disconnect detection flag (DGND_DISCn) from triggering the
SUPPLY_FAULTn flag in the STATUS_MSB register.
0b = Unmasked
1b = Masked
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8.6.1.35 ADC_FAULT_MASK Register (Address = 48h) [Reset = 0000h]
Return to the Summary Table.
图8-80. ADC_FAULT_MASK Register
15
14
13
12
11
10
2
9
1
8
ADC1A_OR_MASK
R/W-0b
ADC1B_OR_MASK
R/W-0b
ADC2A_OR_MASK
R/W-0b
SPARE[2:0]
R/W-000b
RESERVED
R-0000000b
7
6
5
4
3
0
RESERVED
MCLK_FAULT_MAS
K
OSCD_WD_MASK
MCLK_WD_MASK
R-0000000b
R/W-0b
R/W-0b
R/W-0b
表8-59. ADC_FAULT_MASK Register Field Descriptions
Bit
Field
Type
Reset
Description
15
ADC1A_OR_MASK
ADC1B_OR_MASK
ADC2A_OR_MASK
SPARE[2:0]
R/W
0b
ADC1A modulator overrange fault flag mask
Masks the ADC1A modulator overrange fault flag (ADC1A_ORn) from triggering the
ADC_FAULTn flag in the STATUS_MSB register.
0b = Unmasked
1b = Masked
14
13
R/W
R/W
R/W
0b
ADC1B modulator overrange fault flag mask
Masks the ADC1B modulator overrange fault flag (ADC1B_ORn) from triggering the
ADC_FAULTn flag in the STATUS_MSB register.
0b = Unmasked
1b = Masked
0b
ADC2A modulator overrange fault flag mask
Masks the ADC2A modulator overrange fault flag (ADC2A_ORn) from triggering the
ADC_FAULTn flag in the STATUS_MSB register.
0b = Unmasked
1b = Masked
12:10
000b
Spare bits
Provided as R/W bits as a means to check the register map section 1 CRC. Bit settings
have no effect.
9:3
2
RESERVED
R
0000000b
0b
Reserved
Always reads back 0000000b.
MCLK_FAULT_MASK
R/W
MCLK frequency too high or too low fault flag mask
Masks the MCLK frequency too high or too low fault flag (MCLK_FAULTn) from triggering
the ADC_FAULTn flag in the STATUS_MSB register.
0b = Unmasked
1b = Masked
1
0
OSCD_WD_MASK
MCLK_WD_MASK
R/W
R/W
0b
0b
Diagnostic oscillator watchdog fault flag mask
Masks the diagnostic oscillator watchdog fault flag (OSCD_WDn) from triggering the
ADC_FAULTn flag in the STATUS_MSB register.
0b = Unmasked
1b = Masked
Main clock watchdog fault flag mask
Masks the main clock watchdog fault flag (MCLK_WDn) from triggering the ADC_FAULTn
flag in the STATUS_MSB register.
0b = Unmasked
1b = Masked
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8.6.1.36 DIGITAL_FAULT_MASK Register (Address = 49h) [Reset = 0000h]
Return to the Summary Table.
图8-81. DIGITAL_FAULT_MASK Register
15
14
13
12
11
10
9
8
0
REG_MAP1_CRC_F REG_MAP2_CRC_F REG_MAP3_CRC_F
RESERVED
MEM_MAP_CRC_FA
ULT_MASK
RESERVED
AULT_MASK
R/W-0b
AULT_MASK
R/W-0b
AULT_MASK
R/W-0b
R-0b
4
R/W-0b
3
R-00000000000b
1
7
6
5
2
RESERVED
R-00000000000b
表8-60. DIGITAL_FAULT_MASK Register Field Descriptions
Bit
Field
Type
Reset
Description
15
REG_MAP1_CRC_FAULT_MASK R/W
REG_MAP2_CRC_FAULT_MASK R/W
REG_MAP3_CRC_FAULT_MASK R/W
0b
Register map section 1 CRC fault flag mask
Masks the register map section 1 CRC fault flag (REG_MAP1_CRC_FAULTn) from
triggering the DIGITAL_FAULTn flag in the STATUS_MSB register.
0b = Unmasked
1b = Masked
14
13
0b
0b
Register map section 2 CRC fault flag mask
Masks the register map section 2 CRC fault flag (REG_MAP2_CRC_FAULTn) from
triggering the DIGITAL_FAULTn flag in the STATUS_MSB register.
0b = Unmasked
1b = Masked
Register map section 3 CRC fault flag mask
Masks the register map section 3 CRC fault flag (REG_MAP3_CRC_FAULTn) from
triggering the DIGITAL_FAULTn flag in the STATUS_MSB register.
0b = Unmasked
1b = Masked
12
11
RESERVED
R
0b
0b
Reserved
Always reads back 0b.
MEM_MAP_CRC_FAULT_MASK
R/W
Memory map CRC fault flag mask
Masks the memory map CRC fault flag (MEM_MAP_CRC_FAULTn) from triggering the
DIGITAL_FAULTn flag in the STATUS_MSB register.
0b = Unmasked
1b = Masked
10:0
RESERVED
R
00000000000b
Reserved
Always reads back 00000000000b.
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8.6.1.37 OCC_FAULT_MASK Register (Address = 4Ah) [Reset = 0000h]
Return to the Summary Table.
图8-82. OCC_FAULT_MASK Register
15
14
13
12
11
10
9
8
RESERVED
R-000000000000b
7
6
5
4
3
2
1
0
RESERVED
OCCA_HT_MASK
R/W-0b
OCCA_LT_MASK
R/W-0b
OCCB_HT_MASK
R/W-0b
OCCB_LT_MASK
R/W-0b
R-000000000000b
表8-61. OCC_FAULT_MASK Register Field Descriptions
Bit
Field
Type
Reset
Description
15:4
RESERVED
R
000000000000b Reserved
Always reads back 000000000000b.
ADC1A overcurrent comparator high threshold fault flag mask
Masks the ADC1A overcurrent comparator high threshold fault flag (OCCA_HTn) from
triggering the OCC_FAULTn flag in the STATUS_MSB register.
0b = Unmasked
1b = Masked
3
OCCA_HT_MASK
OCCA_LT_MASK
OCCB_HT_MASK
OCCB_LT_MASK
R/W
R/W
R/W
R/W
0b
0b
0b
0b
2
1
0
ADC1A overcurrent comparator low threshold fault flag mask
Masks the ADC1A overcurrent comparator low threshold fault flag (OCCA_LTn) from
triggering the OCC_FAULTn flag in the STATUS_MSB register.
0b = Unmasked
1b = Masked
ADC1B overcurrent comparator high threshold fault flag mask
Masks the ADC1B overcurrent comparator high threshold fault flag (OCCB_HTn) from
triggering the OCC_FAULTn flag in the STATUS_MSB register.
0b = Unmasked
1b = Masked
ADC1B overcurrent comparator low threshold fault flag mask
Masks the ADC1B overcurrent comparator low threshold fault flag (OCCB_LTn) from
triggering the OCC_FAULTn flag in the STATUS_MSB register.
0b = Unmasked
1b = Masked
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8.6.1.38 FAULT_PIN_MASK Register (Address = 4Bh) [Reset = 0780h]
Return to the Summary Table.
图8-83. FAULT_PIN_MASK Register
15
14
13
12
11
10
9
8
RESERVED
SUPPLY_FAULT_MA ADC_FAULT_MASK DIGITAL_FAULT_MA OCC_FAULT_MASK SPI_CRC_FAULT_M SPI_TIMEOUT_MAS SCLK_COUNT_FAU
SK
SK
ASK
K
LT_MASK
R/W-1b
R-0b
7
R/W-0b
R/W-0b
5
R/W-0b
R/W-0b
R/W-1b
R/W-1b
6
4
3
2
1
0
REG_ACCESS_FAU
LT_MASK
RESERVED
R/W-1b
R-0000000b
表8-62. FAULT_PIN_MASK Register Field Descriptions
Bit
Field
RESERVED
Type
Reset
Description
15
R
0b
Reserved
Always reads back 0b.
14
13
12
11
10
9
SUPPLY_FAULT_MASK
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
0b
Supply fault flag mask
Masks the supply fault flag (SUPPLY_FAULTn) in the STATUS_MSB register from triggering
the FAULT pin when the GPIO2/FAULT pin is configured as a FAULT output.
0b = Unmasked
1b = Masked
ADC_FAULT_MASK
0b
ADC fault flag mask
Masks the ADC fault flag (ADC_FAULTn) in the STATUS_MSB register from triggering the
FAULT pin when the GPIO2/FAULT pin is configured as a FAULT output.
0b = Unmasked
1b = Masked
DIGITAL_FAULT_MASK
OCC_FAULT_MASK
0b
Digital fault flag mask
Masks the digital fault flag (DIGITAL_FAULTn) in the STATUS_MSB register from triggering
the FAULT pin when the GPIO2/FAULT pin is configured as a FAULT output.
0b = Unmasked
1b = Masked
0b
Overcurrent comparator fault flag mask
Masks the overcurrent comparator fault flag (OCC_FAULTn) in the STATUS_MSB register
from triggering the FAULT pin when the GPIO2/FAULT pin is configured as a FAULT output.
0b = Unmasked
1b = Masked
SPI_CRC_FAULT_MASK
SPI_TIMEOUT_MASK
SCLK_COUNT_FAULT_MASK
REG_ACCESS_FAULT_MASK
RESERVED
1b
SPI CRC fault flag mask
Masks the SPI CRC fault flag (SPI_CRC_FAULTn) in the STATUS_MSB register from
triggering the FAULT pin when the GPIO2/FAULT pin is configured as a FAULT output.
0b = Unmasked
1b = Masked
1b
SPI timeout fault flag mask
Masks the SPI timeout fault flag (SPI_TIMEOUTn) in the STATUS_MSB register from
triggering the FAULT pin when the GPIO2/FAULT pin is configured as a FAULT output.
0b = Unmasked
1b = Masked
8
1b
SCLK counter fault flag mask
Masks the SCLK counter fault flag (SCLK_COUNT_FAULTn) in the STATUS_MSB register
from triggering the FAULT pin when the GPIO2/FAULT pin is configured as a FAULT output.
0b = Unmasked
1b = Masked
7
1b
Register access fault flag mask
Masks the register access fault flag (REG_ACCESS_FAULTn) in the STATUS_MSB register
from triggering the FAULT pin when the GPIO2/FAULT pin is configured as a FAULT output.
0b = Unmasked
1b = Masked
6:0
0000000b
Reserved
Always reads back 00000000b.
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8.6.1.39 DEVICE_CFG Register (Address = 4Ch) [Reset = 0000h]
Return to the Summary Table.
图8-84. DEVICE_CFG Register
15
14
13
12
11
10
9
1
8
RESERVED
R-0b
DRDY_CTRL
R/W-0b
RESERVED
R/W-0b
CLK_SOURCE
R/W-0b
WORD_LENGTH
R/W-0b
RESERVED
R-0b
OP_MODE[1:0]
R/W-00b
7
6
5
4
3
2
0
RESERVED
R-00000000b
表8-63. DEVICE_CFG Register Field Descriptions
Bit
Field
Type
Reset
Description
15
RESERVED
R
0b
Reserved
Always reads back 0b.
14
DRDY_CTRL
R/W
0b
DRDYn pin control selection
Selects which ADC controls the DRDYn pin indication.
0b = ADC1A
1b = ADC1B
13
12
RESERVED
R/W
R/W
0b
0b
Reserved
Always write 0b.
CLK_SOURCE
MCLK clock source selection
Selects the main clock source of the device. Before changing this bit, all ADCs must be
disabled or the device placed in standby or power-down mode. When switching from an
external clock to the internal oscillator, the external clock must be provided until after the
switch-over is complete.
0b = Internal oscillator
1b = External clock
11
WORD_LENGTH
R/W
0b
Data word length selection
Selects the length of every word in the SPI frame.
0b = 24 bits
1b = 32 bits; LSB zero padding
10
RESERVED
R
0b
Reserved
Always reads back 0b.
9:8
OP_MODE[1:0]
R/W
00b
Operating mode selection
Selects the operating mode for the device.
00b = Active mode
01b = Standby mode (Disables all ADCs)
10b = Power-down mode
11b = Power-down mode
7:0
RESERVED
R
00000000b
Reserved
Always reads back 00000000b.
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8.6.1.40 GPIO_CFG Register (Address = 4Dh) [Reset = 0000h]
Return to the Summary Table.
图8-85. GPIO_CFG Register
15
14
13
12
11
10
9
8
RESERVED
R-0b
GPIO4_FMT
R/W-0b
GPIO3_FMT
R/W-0b
GPIO2_FMT
R/W-0b
GPIO1_FMT
R/W-0b
GPIO0_FMT
R/W-0b
GPIO4_DIR
R/W-0b
GPIO3_DIR
R/W-0b
7
6
5
4
3
2
1
0
GPIO2_DIR
R/W-0b
GPIO1_DIR
R/W-0b
GPIO0_DIR
R/W-0b
GPIO4_SRC
R/W-0b
GPIO3_SRC
R/W-0b
GPIO2_SRC
R/W-0b
RESERVED
R-0b
GPIO0_SRC
R/W-0b
表8-64. GPIO_CFG Register Field Descriptions
Bit
Field
Type
Reset
Description
15
RESERVED
R
0b
Reserved
Always reads back 0b.
14
13
12
11
10
GPIO4_FMT
R/W
R/W
R/W
R/W
R/W
0b
0b
0b
0b
0b
GPIO4 format
Configures GPIO4 for static input and output levels or for PWM input and output levels
0b = When GPIO4 is configured as a digital input: Logic levels are based on static input
levels. When GPIO4 is configured as a digital output: Output with static output levels.
(GPIO4_LL_PWM_CFG and GPIO4_LH_PWM_CFG registers are ignored in this case). For
parallel GPO readback purposes the readback path is configured for logic levels based on
static input levels in this case.
1b = When GPIO4 is configured as a digital input: Logic levels are based on PWM input
decoding. When GPIO4 is configured as a digital output: Output with PWM output defined
by the GPIO4_LL_PWM_CFG and GPIO4_LH_PWM_CFG registers. For parallel GPO
readback purposes the readback path is configured for logic levels based on PWM decoding
using the time base configured in GPIO4_PWM_TB in this case.
GPIO3_FMT
GPIO2_FMT
GPIO1_FMT
GPIO0_FMT
GPIO3 format
Configures GPIO3 for static input and output levels or for PWM input and output levels
0b = When GPIO3 is configured as a digital input: Logic levels are based on static input
levels. When GPIO3 is configured as a digital output: Output with static output levels.
(GPIO3_LL_PWM_CFG and GPIO3_LH_PWM_CFG registers are ignored in this case). For
parallel GPO readback purposes the readback path is configured for logic levels based on
static input levels in this case.
1b = When GPIO3 is configured as a digital input: Logic levels are based on PWM input
decoding. When GPIO3 is configured as a digital output: Output with PWM output defined
by the GPIO3_LL_PWM_CFG and GPIO3_LH_PWM_CFG registers. For parallel GPO
readback purposes the readback path is configured for logic levels based on PWM decoding
using the time base configured in GPIO3_PWM_TB in this case.
GPIO2 format
Configures GPIO2 for static input and output levels or for PWM input and output levels
0b = When GPIO2 is configured as a digital input: Logic levels are based on static input
levels. When GPIO2 is configured as a digital output: Output with static output levels.
(GPIO2_LL_PWM_CFG and GPIO2_LH_PWM_CFG registers are ignored in this case). For
parallel GPO readback purposes the readback path is configured for logic levels based on
static input levels in this case.
1b = When GPIO2 is configured as a digital input: Logic levels are based on PWM input
decoding. When GPIO2 is configured as a digital output: Output with PWM output defined
by the GPIO2_LL_PWM_CFG and GPIO2_LH_PWM_CFG registers. For parallel GPO
readback purposes the readback path is configured for logic levels based on PWM decoding
using the time base configured in GPIO2_PWM_TB in this case.
GPIO1 format
Configures GPIO1 for static input and output levels or for PWM input and output levels
0b = When GPIO1 is configured as a digital input: Logic levels are based on static input
levels. When GPIO1 is configured as a digital output: Output with static output levels.
(GPIO1_LL_PWM_CFG and GPIO1_LH_PWM_CFG registers are ignored in this case). For
parallel GPO readback purposes the readback path is configured for logic levels based on
static input levels in this case.
1b = When GPIO1 is configured as a digital input: Logic levels are based on PWM input
decoding. When GPIO1 is configured as a digital output: Output with PWM output defined
by the GPIO1_LL_PWM_CFG and GPIO1_LH_PWM_CFG registers. For parallel GPO
readback purposes the readback path is configured for logic levels based on PWM decoding
using the time base configured in GPIO1_PWM_TB in this case.
GPIO0 format
Configures GPIO0 for static input and output levels or for PWM input and output levels
0b = When GPIO0 is configured as a digital input: Logic levels are based on static input
levels. When GPIO0 is configured as a digital output: Output with static output levels.
(GPIO0_LL_PWM_CFG and GPIO0_LH_PWM_CFG registers are ignored in this case). For
parallel GPO readback purposes the readback path is configured for logic levels based on
static input levels in this case.
1b = When GPIO0 is configured as a digital input: Logic levels are based on PWM input
decoding. When GPIO0 is configured as a digital output: Output with PWM output defined
by the GPIO0_LL_PWM_CFG and GPIO0_LH_PWM_CFG registers. For parallel GPO
readback purposes the readback path is configured for logic levels based on PWM decoding
using the time base configured in GPIO0_PWM_TB in this case.
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表8-64. GPIO_CFG Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
9
GPIO4_DIR
R/W
0b
GPIO4 direction
Configures GPIO4 as a digital input or output. Configure as a digital output when used as
OCCB output.
0b = Digital input
1b = Digital output
8
7
GPIO3_DIR
GPIO2_DIR
R/W
R/W
0b
0b
GPIO3 direction
Configures GPIO3 as a digital input or output. Configure as a digital output when used as
OCCA output.
0b = Digital input
1b = Digital output
GPIO2 direction
Configures GPIO2 as a digital input or output. Configure as a digital output when used as
FAULT output.
0b = Digital input
1b = Digital output
6
5
GPIO1_DIR
GPIO0_DIR
R/W
R/W
0b
0b
GPIO1 direction
Configures GPIO1 as a digital input or output.
0b = Digital input
1b = Digital output
GPIO0 direction
Configures GPIO0 as a digital input or output. Configure as a digital output when used as
MHD output.
0b = Digital input
1b = Digital output
4
3
2
GPIO4_SRC
GPIO3_SRC
GPIO2_SRC
R/W
R/W
R/W
0b
0b
0b
GPIO4 data source selection
Selects the data source of the GPIO4/OCCB pin when GPIO4 is configured as an output.
0b = OCCB
1b = GPIO
GPIO3 data source selection
Selects the data source of the GPIO3/OCCA pin when GPIO3 is configured as an output.
0b = OCCA
1b = GPIO
GPIO2 data source selection
Selects the data source of the GPIO2/FAULT pin when GPIO2 is configured as an output.
0b = FAULT
1b = GPIO
1
0
RESERVED
GPIO0_SRC
R
0b
0b
Reserved
Always reads back 0b.
R/W
GPIO0 data source selection
Selects the data source of the GPIO0/MHD pin when GPIO0 is configured as an output.
0b = Missing host detection (MHD)
1b = GPIO
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8.6.1.41 GPO_DATA Register (Address = 4Eh) [Reset = 0000h]
Return to the Summary Table.
图8-86. GPO_DATA Register
15
14
13
12
11
10
9
8
SPARE[10:0]
R/W-00000000000b
7
6
5
4
3
2
1
0
SPARE[10:0]
GPO4_DAT
R/W-0b
GPO3_DAT
R/W-0b
GPO2_DAT
R/W-0b
GPO1_DAT
R/W-0b
GPO0_DAT
R/W-0b
R/W-00000000000b
表8-65. GPO_DATA Register Field Descriptions
Bit
Field
Type
Reset
Description
15:5
SPARE[10:0]
R/W
00000000000b
Spare bits
Provided as R/W bits as a means to check the register map section 1 CRC. Bit settings
have no effect.
4
GPO4_DAT
R/W
R/W
R/W
R/W
R/W
0b
0b
0b
0b
0b
GPIO4 output data
Output value of GPIO4 when configured as a digital output. Bit setting has not effect when
GPIO4 is configured as an input or as OCCB output.
0b = Low
1b = High
3
2
1
0
GPO3_DAT
GPO2_DAT
GPO1_DAT
GPO0_DAT
GPIO3 output data
Output value of GPIO3 when configured as a digital output. Bit setting has not effect when
GPIO3 is configured as an input or as OCCA output.
0b = Low
1b = High
GPIO2 output data
Output value of GPIO2 when configured as a digital output. Bit setting has not effect when
GPIO2 is configured as an input or as FAULT output.
0b = Low
1b = High
GPIO1 output data
Output value of GPIO1 when configured as a digital output. Bit setting has not effect when
GPIO1 is configured as an input.
0b = Low
1b = High
GPIO0 output data
Output value of GPIO0 when configured as a digital output. Bit setting has not effect when
GPIO0 is configured as an input or as MHD output.
0b = Low
1b = High
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8.6.1.42 GPIO0_LL_PWM_CFG Register (Address = 4Fh) [Reset = 007Fh]
Return to the Summary Table.
图8-87. GPIO0_LL_PWM_CFG Register
15
GPIO0_PWM_TB[1:0]
R/W-00b
14
13
12
11
10
9
1
8
0
GPIO0_LL_PWM_HC[6:0]
R/W-0000000b
7
6
5
4
3
2
GPIO0_LL_PWM_H
C[6:0]
GPIO0_LL_PWM_LC[6:0]
R/W-0000000b
R/W-1111111b
表8-66. GPIO0_LL_PWM_CFG Register Field Descriptions
Bit
Field
Type
Reset
Description
15:14
GPIO0_PWM_TB[1:0]
R/W
00b
GPIO0/MHD PWM time base selection
Selects the time base used for the GPIO0/MHD PWM generation when the GPIO0/MHD pin
is configured as an output as well as the time base used for the PWM encoder.
00b = 16 x tMCLK (= 1/512 kHz for fMCLK = 8.192 MHz)
01b = 64 x tMCLK (= 1/128 kHz for fMCLK = 8.192 MHz)
10b = 256 x tMCLK (= 1/32 kHz for fMCLK = 8.192 MHz)
11b = 1024 x tMCLK (= 1/8 kHz for fMCLK = 8.192 MHz)
13:7
GPIO0_LL_PWM_HC[6:0]
GPIO0_LL_PWM_LC[6:0]
R/W
R/W
0000000b
1111111b
GPIO0/MHD logic low level PWM high counter
Sets the high period of the PWM for a logic low level of GPIO0/MHD.
PWM period = (PWM high counter value + PWM low counter value) x PWM time base
PWM high time = (PWM high counter value x PWM time base)
Setting the PWM high counter value to 0000000b configures the GPIO0/MHD logic low level
as static low. Setting both the PWM high and low counter values to 0000000b configures the
GPIO0/MHD logic low level as static low.
6:0
GPIO0/MHD logic low level PWM low counter
Sets the low period of the PWM for a logic low level of GPIO0/MHD.
PWM period = (PWM high counter value + PWM low counter value) x PWM time base
PWM low time = (PWM low counter value x PWM time base)
Setting the PWM low counter value to 0000000b configures the GPIO0/MHD logic low level
as static high. Setting both the PWM high and low counter values to 0000000b configures
the GPIO0/MHD logic low level as static low.
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8.6.1.43 GPIO0_LH_PWM_CFG Register (Address = 50h) [Reset = 3F80h]
Return to the Summary Table.
图8-88. GPIO0_LH_PWM_CFG Register
15
14
13
12
11
10
9
1
8
0
RESERVED
R-00b
GPIO0_LH_PWM_HC[6:0]
R/W-1111111b
7
6
5
4
3
2
GPIO0_LH_PWM_H
C[6:0]
GPIO0_LH_PWM_LC[6:0]
R/W-1111111b
R/W-0000000b
表8-67. GPIO0_LH_PWM_CFG Register Field Descriptions
Bit
Field
RESERVED
Type
Reset
Description
15:14
R
00b
Reserved
Always reads 00b.
13:7
GPIO0_LH_PWM_HC[6:0]
R/W
1111111b
GPIO0/MHD logic high level PWM high counter
Sets the high period of the PWM for a logic high level of GPIO0/MHD.
PWM period = (PWM high counter value + PWM low counter value) x PWM time base
PWM high time = (PWM high counter value x PWM time base)
Setting the PWM high counter value to 0000000b configures the GPIO0/MHD logic high
level as static low. Setting both the PWM high and low counter values to 0000000b
configures the GPIO0/MHD logic high level as static low.
6:0
GPIO0_LH_PWM_LC[6:0]
R/W
0000000b
GPIO0/MHD logic high level PWM low counter
Sets the low period of the PWM for a logic high level of GPIO0/MHD.
PWM period = (PWM high counter value + PWM low counter value) x PWM time base
PWM low time = (PWM low counter value x PWM time base)
Setting the PWM low counter value to 0000000b configures the GPIO0/MHD logic high level
as static high. Setting both the PWM high and low counter values to 0000000b configures
the GPIO0/MHD logic high level as static low.
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8.6.1.44 GPIO1_LL_PWM_CFG Register (Address = 51h) [Reset = 007Fh]
Return to the Summary Table.
图8-89. GPIO1_LL_PWM_CFG Register
15
GPIO1_PWM_TB[1:0]
R/W-00b
14
13
12
11
10
9
1
8
0
GPIO1_LL_PWM_HC[6:0]
R/W-0000000b
7
6
5
4
3
2
GPIO1_LL_PWM_H
C[6:0]
GPIO1_LL_PWM_LC[6:0]
R/W-0000000b
R/W-1111111b
表8-68. GPIO1_LL_PWM_CFG Register Field Descriptions
Bit
Field
Type
Reset
Description
15:14
GPIO1_PWM_TB[1:0]
R/W
00b
GPIO1 PWM time base selection
Selects the time base used for the GPIO1 PWM generation when the GPIO1 pin is
configured as an output as well as the time base used for the PWM encoder.
00b = 16 x tMCLK (= 1/512 kHz for fMCLK = 8.192 MHz)
01b = 64 x tMCLK (= 1/128 kHz for fMCLK = 8.192 MHz)
10b = 256 x tMCLK (= 1/32 kHz for fMCLK = 8.192 MHz)
11b = 1024 x tMCLK (= 1/8 kHz for fMCLK = 8.192 MHz)
13:7
GPIO1_LL_PWM_HC[6:0]
GPIO1_LL_PWM_LC[6:0]
R/W
R/W
0000000b
1111111b
GPIO1 logic low level PWM high counter
Sets the high period of the PWM for a logic low level of GPIO1.
PWM period = (PWM high counter value + PWM low counter value) x PWM time base
PWM high time = (PWM high counter value x PWM time base)
Setting the PWM high counter value to 0000000b configures the GPIO1 logic low level as
static low. Setting both the PWM high and low counter values to 0000000b configures the
GPIO1 logic low level as static low.
6:0
GPIO1 logic low level PWM low counter
Sets the low period of the PWM for a logic low level of GPIO1.
PWM period = (PWM high counter value + PWM low counter value) x PWM time base
PWM low time = (PWM low counter value x PWM time base)
Setting the PWM low counter value to 0000000b configures the GPIO1 logic low level as
static high. Setting both the PWM high and low counter values to 0000000b configures the
GPIO1 logic low level as static low.
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8.6.1.45 GPIO1_LH_PWM_CFG Register (Address = 52h) [Reset = 3F80h]
Return to the Summary Table.
图8-90. GPIO1_LH_PWM_CFG Register
15
14
13
12
11
10
9
1
8
0
RESERVED
R-00b
GPIO1_LH_PWM_HC[6:0]
R/W-1111111b
7
6
5
4
3
2
GPIO1_LH_PWM_H
C[6:0]
GPIO1_LH_PWM_LC[6:0]
R/W-1111111b
R/W-0000000b
表8-69. GPIO1_LH_PWM_CFG Register Field Descriptions
Bit
Field
RESERVED
Type
Reset
Description
15:14
R
00b
Reserved
Always reads 00b.
13:7
GPIO1_LH_PWM_HC[6:0]
R/W
1111111b
GPIO1 logic high level PWM high counter
Sets the high period of the PWM for a logic high level of GPIO1.
PWM period = (PWM high counter value + PWM low counter value) x PWM time base
PWM high time = (PWM high counter value x PWM time base)
Setting the PWM high counter value to 0000000b configures the GPIO1 logic high level as
static low. Setting both the PWM high and low counter values to 0000000b configures the
GPIO1 logic high level as static low.
6:0
GPIO1_LH_PWM_LC[6:0]
R/W
0000000b
GPIO1 logic high level PWM low counter
Sets the low period of the PWM for a logic high level of GPIO1.
PWM period = (PWM high counter value + PWM low counter value) x PWM time base
PWM low time = (PWM low counter value x PWM time base)
Setting the PWM low counter value to 0000000b configures the GPIO1 logic high level as
static high. Setting both the PWM high and low counter values to 0000000b configures the
GPIO1 logic high level as static low.
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8.6.1.46 GPIO2_LL_PWM_CFG Register (Address = 53h) [Reset = 007Fh]
Return to the Summary Table.
图8-91. GPIO2_LL_PWM_CFG Register
15
GPIO2_PWM_TB[1:0]
R/W-00b
14
13
12
11
10
9
1
8
0
GPIO2_LL_PWM_HC[6:0]
R/W-0000000b
7
6
5
4
3
2
GPIO2_LL_PWM_H
C[6:0]
GPIO2_LL_PWM_LC[6:0]
R/W-0000000b
R/W-1111111b
表8-70. GPIO2_LL_PWM_CFG Register Field Descriptions
Bit
Field
Type
Reset
Description
15:14
GPIO2_PWM_TB[1:0]
R/W
00b
GPIO2/FAULT PWM time base selection
Selects the time base used for the GPIO2/FAULT PWM generation when the GPIO2/FAULT
pin is configured as an output as well as the time base used for the PWM encoder.
00b = 16 x tMCLK (= 1/512 kHz for fMCLK = 8.192 MHz)
01b = 64 x tMCLK (= 1/128 kHz for fMCLK = 8.192 MHz)
10b = 256 x tMCLK (= 1/32 kHz for fMCLK = 8.192 MHz)
11b = 1024 x tMCLK (= 1/8 kHz for fMCLK = 8.192 MHz)
13:7
GPIO2_LL_PWM_HC[6:0]
GPIO2_LL_PWM_LC[6:0]
R/W
R/W
0000000b
1111111b
GPIO2/FAULT logic low level PWM high counter
Sets the high period of the PWM for a logic low level of GPIO2/FAULT.
PWM period = (PWM high counter value + PWM low counter value) x PWM time base
PWM high time = (PWM high counter value x PWM time base)
Setting the PWM high counter value to 0000000b configures the GPIO2/FAULT logic low
level as static low. Setting both the PWM high and low counter values to 0000000b
configures the GPIO2/FAULT logic low level as static low.
6:0
GPIO2/FAULT logic low level PWM low counter
Sets the low period of the PWM for a logic low level of GPIO2/FAULT.
PWM period = (PWM high counter value + PWM low counter value) x PWM time base
PWM low time = (PWM low counter value x PWM time base)
Setting the PWM low counter value to 0000000b configures the GPIO2/FAULT logic low
level as static high. Setting both the PWM high and low counter values to 0000000b
configures the GPIO2/FAULT logic low level as static low.
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8.6.1.47 GPIO2_LH_PWM_CFG Register (Address = 54h) [Reset = 3F80h]
Return to the Summary Table.
图8-92. GPIO2_LH_PWM_CFG Register
15
14
13
12
11
10
9
1
8
0
RESERVED
R-00b
GPIO2_LH_PWM_HC[6:0]
R/W-1111111b
7
6
5
4
3
2
GPIO2_LH_PWM_H
C[6:0]
GPIO2_LH_PWM_LC[6:0]
R/W-1111111b
R/W-0000000b
表8-71. GPIO2_LH_PWM_CFG Register Field Descriptions
Bit
Field
RESERVED
Type
Reset
Description
15:14
R
00b
Reserved
Always reads 00b.
13:7
GPIO2_LH_PWM_HC[6:0]
R/W
1111111b
GPIO2/FAULT logic high level PWM high counter
Sets the high period of the PWM for a logic high level of GPIO2/FAULT.
PWM period = (PWM high counter value + PWM low counter value) x PWM time base
PWM high time = (PWM high counter value x PWM time base)
Setting the PWM high counter value to 0000000b configures the GPIO2/FAULT logic high
level as static low. Setting both the PWM high and low counter values to 0000000b
configures the GPIO2/FAULT logic high level as static low.
6:0
GPIO2_LH_PWM_LC[6:0]
R/W
0000000b
GPIO2/FAULT logic high level PWM low counter
Sets the low period of the PWM for a logic high level of GPIO2/FAULT.
PWM period = (PWM high counter value + PWM low counter value) x PWM time base
PWM low time = (PWM low counter value x PWM time base)
Setting the PWM low counter value to 0000000b configures the GPIO2/FAULT logic high
level as static high. Setting both the PWM high and low counter values to 0000000b
configures the GPIO2/FAULT logic high level as static low.
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8.6.1.48 GPIO3_LL_PWM_CFG Register (Address = 55h) [Reset = 007Fh]
Return to the Summary Table.
图8-93. GPIO3_LL_PWM_CFG Register
15
GPIO3_PWM_TB[1:0]
R/W-00b
14
13
12
11
10
9
1
8
0
GPIO3_LL_PWM_HC[6:0]
R/W-0000000b
7
6
5
4
3
2
GPIO3_LL_PWM_H
C[6:0]
GPIO3_LL_PWM_LC[6:0]
R/W-0000000b
R/W-1111111b
表8-72. GPIO3_LL_PWM_CFG Register Field Descriptions
Bit
Field
Type
Reset
Description
15:14
GPIO3_PWM_TB[1:0]
R/W
00b
GPIO3/OCCA PWM time base selection
Selects the time base used for the GPIO3/OCCA PWM generation when the GPIO3/OCCA
pin is configured as an output as well as the time base used for the PWM encoder.
00b = 16 x tMCLK (= 1/512 kHz for fMCLK = 8.192 MHz)
01b = 64 x tMCLK (= 1/128 kHz for fMCLK = 8.192 MHz)
10b = 256 x tMCLK (= 1/32 kHz for fMCLK = 8.192 MHz)
11b = 1024 x tMCLK (= 1/8 kHz for fMCLK = 8.192 MHz)
13:7
GPIO3_LL_PWM_HC[6:0]
GPIO3_LL_PWM_LC[6:0]
R/W
R/W
0000000b
1111111b
GPIO3/OCCA logic low level PWM high counter
Sets the high period of the PWM for a logic low level of GPIO3/OCCA.
PWM period = (PWM high counter value + PWM low counter value) x PWM time base
PWM high time = (PWM high counter value x PWM time base)
Setting the PWM high counter value to 0000000b configures the GPIO3/OCCA logic low
level as static low. Setting both the PWM high and low counter values to 0000000b
configures the GPIO3/OCCA logic low level as static low.
6:0
GPIO3/OCCA logic low level PWM low counter
Sets the low period of the PWM for a logic low level of GPIO3/OCCA.
PWM period = (PWM high counter value + PWM low counter value) x PWM time base
PWM low time = (PWM low counter value x PWM time base)
Setting the PWM low counter value to 0000000b configures the GPIO3/OCCA logic low
level as static high. Setting both the PWM high and low counter values to 0000000b
configures the GPIO3/OCCA logic low level as static low.
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8.6.1.49 GPIO3_LH_PWM_CFG Register (Address = 56h) [Reset = 3F80h]
Return to the Summary Table.
图8-94. GPIO3_LH_PWM_CFG Register
15
14
13
12
11
10
9
1
8
0
RESERVED
R-00b
GPIO3_LH_PWM_HC[6:0]
R/W-1111111b
7
6
5
4
3
2
GPIO3_LH_PWM_H
C[6:0]
GPIO3_LH_PWM_LC[6:0]
R/W-1111111b
R/W-0000000b
表8-73. GPIO3_LH_PWM_CFG Register Field Descriptions
Bit
Field
RESERVED
Type
Reset
Description
15:14
R
00b
Reserved
Always reads 00b.
13:7
GPIO3_LH_PWM_HC[6:0]
R/W
1111111b
GPIO3/OCCA logic high level PWM high counter
Sets the high period of the PWM for a logic high level of GPIO3/OCCA.
PWM period = (PWM high counter value + PWM low counter value) x PWM time base
PWM high time = (PWM high counter value x PWM time base)
Setting the PWM high counter value to 0000000b configures the GPIO3/OCCA logic high
level as static low. Setting both the PWM high and low counter values to 0000000b
configures the GPIO2/OCCA logic high level as static low.
6:0
GPIO3_LH_PWM_LC[6:0]
R/W
0000000b
GPIO3/OCCA logic high level PWM low counter
Sets the low period of the PWM for a logic high level of GPIO3/OCCA.
PWM period = (PWM high counter value + PWM low counter value) x PWM time base
PWM low time = (PWM low counter value x PWM time base)
Setting the PWM low counter value to 0000000b configures the GPIO3/OCCA logic high
level as static high. Setting both the PWM high and low counter values to 0000000b
configures the GPIO2/OCCA logic high level as static low.
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8.6.1.50 GPIO4_LL_PWM_CFG Register (Address = 57h) [Reset = 007Fh]
Return to the Summary Table.
图8-95. GPIO4_LL_PWM_CFG Register
15
GPIO4_PWM_TB[1:0]
R/W-00b
14
13
12
11
10
9
1
8
0
GPIO4_LL_PWM_HC[6:0]
R/W-0000000b
7
6
5
4
3
2
GPIO4_LL_PWM_H
C[6:0]
GPIO4_LL_PWM_LC[6:0]
R/W-0000000b
R/W-1111111b
表8-74. GPIO4_LL_PWM_CFG Register Field Descriptions
Bit
Field
Type
Reset
Description
15:14
GPIO4_PWM_TB[1:0]
R/W
00b
GPIO4/OCCB PWM time base selection
Selects the time base used for the GPIO4/OCCB PWM generation when the GPIO4/OCCB
pin is configured as an output as well as the time base used for the PWM encoder
00b = 16 x tMCLK (= 1/512 kHz for fMCLK = 8.192 MHz)
01b = 64 x tMCLK (= 1/128 kHz for fMCLK = 8.192 MHz)
10b = 256 x tMCLK (= 1/32 kHz for fMCLK = 8.192 MHz)
11b = 1024 x tMCLK (= 1/8 kHz for fMCLK = 8.192 MHz)
13:7
GPIO4_LL_PWM_HC[6:0]
GPIO4_LL_PWM_LC[6:0]
R/W
R/W
0000000b
1111111b
GPIO4/OCCB logic low level PWM high counter
Sets the high period of the PWM for a logic low level of GPIO4/OOCB.
PWM period = (PWM high counter value + PWM low counter value) x PWM time base
PWM high time = (PWM high counter value x PWM time base)
Setting the PWM high counter value to 0000000b configures the GPIO4/OCCB logic low
level as static low. Setting both the PWM high and low counter values to 0000000b
configures the GPIO4/OCCB logic low level as static low.
6:0
GPIO4/OCCB logic low level PWM low counter
Sets the low period of the PWM for a logic low level of GPIO4/OCCB.
PWM period = (PWM high counter value + PWM low counter value) x PWM time base
PWM low time = (PWM low counter value x PWM time base)
Setting the PWM low counter value to 0000000b configures the GPIO4/OCCB logic low
level as static high. Setting both the PWM high and low counter values to 0000000b
configures the GPIO4/OCCB logic low level as static low.
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8.6.1.51 GPIO4_LH_PWM_CFG Register (Address = 58h) [Reset = 3F80h]
Return to the Summary Table.
图8-96. GPIO4_LH_PWM_CFG Register
15
14
13
12
11
10
9
1
8
0
RESERVED
R-00b
GPIO4_LH_PWM_HC[6:0]
R/W-1111111b
7
6
5
4
3
2
GPIO4_LH_PWM_H
C[6:0]
GPIO4_LH_PWM_LC[6:0]
R/W-1111111b
R/W-0000000b
表8-75. GPIO4_LH_PWM_CFG Register Field Descriptions
Bit
Field
RESERVED
Type
Reset
Description
15:14
R
00b
Reserved
Always reads 00b.
13:7
GPIO4_LH_PWM_HC[6:0]
R/W
1111111b
GPIO4BOCCB logic high level PWM high counter
Sets the high period of the PWM for a logic high level of GPIO4.
PWM period = (PWM high counter value + PWM low counter value) x PWM time base
PWM high time = (PWM high counter value x PWM time base)
Setting the PWM high counter value to 0000000b configures the GPIO4 logic high level as
static low. Setting both the PWM high and low counter values to 0000000b configures the
GPIO4/OCCB logic high level as static low.
6:0
GPIO4_LH_PWM_LC[6:0]
R/W
0000000b
GPIO4/OCCB logic high level PWM low counter
Sets the low period of the PWM for a logic high level of GPIO4/OCCB.
PWM period = (PWM high counter value + PWM low counter value) x PWM time base
PWM low time = (PWM low counter value x PWM time base)
Setting the PWM low counter value to 0000000b configures the GPIO4/OCCB logic high
level as static high. Setting both the PWM high and low counter values to 0000000b
configures the GPIO4/OCCB logic high level as static low.
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8.6.1.52 SPARE_59h Register (Address = 59h) [Reset = 5555h]
Return to the Summary Table.
图8-97. SPARE_59h Register
15
14
13
12
11
10
2
9
1
8
0
SPARE[15:0]
R/W-0101010101010101b
7
6
5
4
3
SPARE[15:0]
R/W-0101010101010101b
表8-76. SPARE_59h Register Field Descriptions
Bit
15:0
Field
Type
Reset
Description
SPARE[15:0]
R/W
0101010101010 Spare bits
101b
Provided as R/W bits as a means to check the register map section 1 CRC. Bit settings
have no effect.
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8.6.1.53 REGISTER_MAP1_CRC Register (Address = 7Eh) [Reset = 0000h]
Return to the Summary Table.
图8-98. REGISTER_MAP1_CRC Register
15
14
13
12
11
10
9
1
8
0
REG_MAP1_CRC_VALUE[15:0]
R/W-0000000000000000b
7
6
5
4
3
2
REG_MAP1_CRC_VALUE[15:0]
R/W-0000000000000000b
表8-77. REGISTER_MAP1_CRC Register Field Descriptions
Bit
15:0
Field
Type
Reset
Description
REG_MAP1_CRC_VALUE[15:0]
R/W
0000000000000 Register map CRC value for section 1
000b Register map CRC value for section 1.
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8.6.1.54 REGMAP2_TDACA_CFG Register (Address = 80h) [Reset = 0000h]
Return to the Summary Table.
图8-99. REGMAP2_TDACA_CFG Register
15
14
13
12
11
10
9
8
0
REG_MAP2_CRC_E
N
RESERVED
R/W-0b
7
R-000000000000b
3
6
5
4
2
1
RESERVED
TDACA_VALUE[2:0]
R/W-000b
R-000000000000b
表8-78. REGMAP2_TDACA_CFG Register Field Descriptions
Bit
Field
Type
Reset
Description
15
REG_MAP2_CRC_EN
R/W
0b
Register map section 2 CRC enable
Enables the register map CRC for section 2 (register address space from 80h to A3h).
0b = Disabled
1b = Enabled
14:3
2:0
RESERVED
R
000000000000b Reserved
Always reads 000000000000b.
TDACA_VALUE[2:0]
R/W
000b
Test DAC A output value
Selects the output value of Test DAC A.
000b = 1 x VREFA/40
001b = 2 x VREFA/40
010b = 4 x VREFA/40
011b = 9 x VREFA/40
100b = 18 x VREFA/40
101b = 36 x VREFA/40
110b = –4 x VREFA/40
111b = –9 x VREFA/40
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8.6.1.55 GPIOA_CFG Register (Address = 81h) [Reset = 8000h]
Return to the Summary Table.
图8-100. GPIOA_CFG Register
15
14
13
12
11
10
9
8
RESERVED
R-1b
SPARE[2:0]
R/W-000b
GPIO1A_FMT
R/W-0b
GPIO0A_FMT
R/W-0b
GPIO1A_DIR
R/W-0b
GPIO0A_DIR
R/W-0b
7
6
5
4
3
2
1
0
GPIO1A_PWM_TB[1:0]
GPIO0A_PWM_TB[1:0]
R/W-00b
SPARE[1:0]
R/W-00b
GPO1A_DAT
R/W-0b
GPO0A_DAT
R/W-0b
R/W-00b
表8-79. GPIOA_CFG Register Field Descriptions
Bit
Field
Type
Reset
Description
15
RESERVED
R
1b
Reserved
Always reads 1b.
14:12
11
SPARE[2:0]
R/W
R/W
000b
0b
Spare bits
Provided as R/W bits as a means to check the register map section 2 CRC. Bit settings
have no effect.
GPIO1A_FMT
GPIO1A format
Configures GPIO1A for static input and output levels or for PWM input levels.
0b = When GPIO1A is configured as a digital input: Logic levels are based on static input
levels. When GPIO1A is configured as a digital output: Output with static output levels.
1b = When GPIO1A is configured as a digital input: Logic levels are based on PWM input
decoding. When GPIO1A is configured as a digital output: Output with static output levels.
GPIO1A does not have PWM output capability.
10
GPIO0A_FMT
R/W
0b
GPIO0A format
Configures GPIO0A for static input and output levels or for PWM input levels.
0b = When GPIO0A is configured as a digital input: Logic levels are based on static input
levels. When GPIO0A is configured as a digital output: Output with static output levels.
1b = When GPIO0A is configured as a digital input: Logic levels are based on PWM input
decoding. When GPIO0A is configured as a digital output: Output with static output levels.
GPIO0A does not have PWM output capability.
9
8
GPIO1A_DIR
R/W
R/W
R/W
0b
GPIO1A direction
Configures GPIO1A as a digital input or digital output.
0b = Digital input
1b = Digital output
GPIO0A_DIR
0b
GPIO0A direction
Configures GPIO0A as a digital input or digital output.
0b = Digital input
1b = Digital output
7:6
GPIO1A_PWM_TB[1:0]
00b
GPIO1A PWM time base selection
Selects the time base used for the PWM encoder when GPIO1A is configured as a digital
input.
00b = 16 x tMCLK (= 1/512 kHz for fMCLK = 8.192 MHz)
01b = 64 x tMCLK (= 1/128 kHz for fMCLK = 8.192 MHz)
10b = 256 x tMCLK (= 1/32 kHz for fMCLK = 8.192 MHz)
11b = 1024 x tMCLK (= 1/8 kHz for fMCLK = 8.192 MHz)
5:4
GPIO0A_PWM_TB[1:0]
R/W
00b
GPIO0A PWM time base selection
Selects the time base used for the PWM encoder when GPIO0A is configured as a digital
input.
00b = 16 x tMCLK (= 1/512 kHz for fMCLK = 8.192 MHz)
01b = 64 x tMCLK (= 1/128 kHz for fMCLK = 8.192 MHz)
10b = 256 x tMCLK (= 1/32 kHz for fMCLK = 8.192 MHz)
11b = 1024 x tMCLK (= 1/8 kHz for fMCLK = 8.192 MHz)
3:2
1
SPARE[1:0]
R/W
R/W
00b
0b
Spare bits
Provided as R/W bits as a means to check the register map section 2 CRC. Bit settings
have no effect.
GPO1A_DAT
GPIO1A output data
Output value of GPIO1A when configured as a digital output. Bit setting has not effect when
GPIO1A is configured as a digital input.
0b = Low
1b = High
0
GPO0A_DAT
R/W
0b
GPIO0A output data
Output value of GPIO0A when configured as a digital output. Bit setting has not effect when
GPIO0A is configured as a digital input.
0b = Low
1b = High
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8.6.1.56 ADC1A_CFG1 Register (Address = 82h) [Reset = 0400h]
Return to the Summary Table.
图8-101. ADC1A_CFG1 Register
15
14
13
12
11
10
2
9
8
0
RESERVED
R-0000b
CONV_MODE1A
R/W-0b
OSR1A[2:0]
R/W-100b
7
6
5
4
3
1
RESERVED
R-0000b
GC1A_EN
R/W-0b
GC1A_DELAY[2:0]
R/W-000b
表8-80. ADC1A_CFG1 Register Field Descriptions
Bit
Field
Type
Reset
Description
15:12
RESERVED
R
0000b
Reserved
Always reads 0000b.
11
CONV_MODE1A
OSR1A[2:0]
R/W
R/W
0b
Conversion mode selection
Selects the conversion mode for ADC1A.
0b = Continuous-conversion mode
1b = Single-shot conversion mode
10:8
100b
Oversampling ratio selection
Selects the oversampling ratio for ADC1A. The data rate calculates to fMOD / OSR.
000b = 64
001b = 128
010b = 256
011b = 512
100b = 1024
101b = 2048
110b = 4096
111b = 8192
7:4
3
RESERVED
GC1A_EN
R
0000b
0b
Reserved
Always reads 0000b.
R/W
Global-chop mode enable
Enables the global-chop mode for ADC1A.
0b = Disabled
1b = Enabled
2:0
GC1A_DELAY[2:0]
R/W
000b
Global-chop mode delay time selection
Selects the delay time in global-chop mode for ADC1A.
000b = 2 x tMOD
001b = 4 x tMOD
010b = 8 x tMOD
011b = 16 x tMOD
100b = 32 x tMOD
101b = 64 x tMOD
110b = 128 x tMOD
111b = 256 x tMOD
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8.6.1.57 ADC1A_CFG2 Register (Address = 83h) [Reset = 8010h]
Return to the Summary Table.
图8-102. ADC1A_CFG2 Register
15
14
13
12
11
10
2
9
1
8
0
ADC1A_EN
R/W-1b
RESERVED
R-000b
GAIN1A[1:0]
R/W-00b
MUX1A[1:0]
R/W-00b
7
6
5
4
3
RESERVED
R-00b
OWD1A_SOURCE_ OWD1A_SINK_MUX
MUX
OWD1A_SOURCE_VALUE[1:0]
OWD1A_SINK_VALUE[1:0]
R/W-0b
R/W-1b
R/W-00b
R/W-00b
表8-81. ADC1A_CFG2 Register Field Descriptions
Bit
Field
Type
Reset
Description
15
ADC1A_EN
R/W
1b
ADC1A enable
Enables ADC1A.
The conversion data of ADC1A reset to 000000h and the conversion counter
CONV1A_COUNT[1:0] resets to 00b when ADC1A is disabled or when the device is put in
standby or power-down mode.
0b = Disabled
1b = Enabled
14:12
11:10
RESERVED
GAIN1A[1:0]
R
000b
00b
Reserved
Always reads 000b.
R/W
ADC1A gain selection
Selects the gain (FSR = full scale range) of ADC1A. Gains 16 and 32 are digital gains using
analog gain = 8.
00b = 4
01b = 8
10b = 16
11b = 32
9:8
MUX1A[1:0]
RESERVED
R/W
00b
ADC1A multiplexer channel selection
Selects the multiplexer channel for ADC1A.
00b = AINp = CPA, AINn = CNA
01b = AINp = CNA, AINn = CPA
10b = Internal short to AGNDA. Analog inputs CPA, CNA disconnected from ADC1A.
11b = Test DAC B output
7:6
5
R
00b
0b
Reserved
Always reads 00b.
OWD1A_SOURCE_MUX
R/W
ADC1A current source multiplexer selection
Selects the multiplexer channel for the ADC1A current source.
0b = CPA
1b = CNA
4
OWD1A_SINK_MUX
R/W
R/W
1b
ADC1A current sink multiplexer selection
Selects the multiplexer channel for the ADC1A current sink.
0b = CPA
1b = CNA
3:2
OWD1A_SOURCE_VALUE[1:0]
00b
ADC1A current source value selection
Selects the current value for the ADC1A current source.
00b = Off
01b = 4 µA
10b = 40 µA
11b = 240 µA
1:0
OWD1A_SINK_VALUE[1:0]
R/W
00b
ADC1A current sink value selection
Selects the current value for the ADC1A current sink.
00b = Off
01b = 4 µA
10b = 40 µA
11b = 240 µA
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8.6.1.58 ADC1A_OCAL_MSB Register (Address = 84h) [Reset = 0000h]
Return to the Summary Table.
图8-103. ADC1A_OCAL_MSB Register
15
14
13
12
11
10
9
1
8
0
OCAL1A[23:8]
R/W-0000000000000000b
7
6
5
4
3
2
OCAL1A[23:8]
R/W-0000000000000000b
表8-82. ADC1A_OCAL_MSB Register Field Descriptions
Bit
15:0
Field
OCAL1A[23:8]
Type
Reset
Description
R/W
0000000000000 ADC1A offset calibration bits [23:8]
000b
Value provided in two's complement format.
LSB size = (2 x VREFA) / (GAIN1A x 224
)
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8.6.1.59 ADC1A_OCAL_LSB Register (Address = 85h) [Reset = 0000h]
Return to the Summary Table.
图8-104. ADC1A_OCAL_LSB Register
15
14
13
12
11
10
9
1
8
0
OCAL1A[7:0]
R/W-00000000b
7
6
5
4
3
2
RESERVED
R-00000000b
表8-83. ADC1A_OCAL_LSB Register Field Descriptions
Bit
Field
Type
Reset
Description
15:8
OCAL1A[7:0]
R/W
00000000b
ADC1A offset calibration bits [7:0]
Value provided in two's complement format.
LSB size = (2 x VREFA) / (GAIN1A x 224
)
7:0
RESERVED
R
00000000b
Reserved
Always reads 00000000b.
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8.6.1.60 ADC1A_GCAL Register (Address = 86h) [Reset = 0000h]
Return to the Summary Table.
图8-105. ADC1A_GCAL Register
15
14
13
12
11
10
2
9
1
8
0
GCAL1A[15:0]
R/W-0000000000000000b
7
6
5
4
3
GCAL1A[15:0]
R/W-0000000000000000b
表8-84. ADC1A_GCAL Register Field Descriptions
Bit
15:0
Field
GCAL1A[15:0]
Type
Reset
Description
R/W
0000000000000 ADC1A gain calibration bits [15:0]
000b
Value provided in two's complement format.
LSB size = 1/216 = 0.000015
Mapping:
0111111111111111b = 1.499985
0000000000000001b = 1.000015
0000000000000000b = 1
1111111111111111b = 0.999985
1000000000000000b = 0.5
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8.6.1.61 OCCA_CFG Register (Address = 87h) [Reset = 0000h]
Return to the Summary Table.
图8-106. OCCA_CFG Register
15
14
13
12
11
10
9
1
8
0
OCCA_EN
R/W-0b
OCCA_POL
R/W-0b
RESERVED
R/W-0b
OCCA_NUM[4:0]
R/W-00000b
7
6
5
4
3
2
RESERVED
R-00000000b
表8-85. OCCA_CFG Register Field Descriptions
Bit
Field
Type
Reset
Description
15
OCCA_EN
R/W
0b
ADC1A overcurrent comparator enable
Enables the digital fast filter and digital comparator on ADC1A. ADC1A must be enabled to
use the overcurrent comparator. The fast filter is not affected by the STARTA and STOPA
bits.
0b = Disabled
1b = Enabled
14
OCCA_POL
R/W
0b
OCCA pin polarity selection
Selects the polarity of the OCCA pin. The actual output behavior of the GPIO3/OCCA pin,
when configured as OCCA output in the GPIO3_SRC bit, depends on the GPIO3_FMT
setting. An OCCA fault is active when any of the OCCA_HTn or OCCA_LTn bits are active.
0b = Active low. In case of a fault a logic low level is driven.
1b = Active high. In case of a fault a logic high level is driven.
13
RESERVED
R/W
R/W
0b
Reserved
Always write 0b.
12:8
OCCA_NUM[4:0]
00000b
ADC1A overcurrent comparator deglitch filter selection
Selects the number of conversions the output of the ADC1A digital fast filter must exceed
the set high or low thresholds to trip the OCCA_HTn or OCCA_LTn comparator output. The
fast filter path uses a SINC3 filter with a fixed OSR = 64. The counter starts again whenever
the digital fast filter output falls below the threshold, means there is no hysteresis.
00000b = 1
00001b = 2
00010b = 3
00011b = 4
00100b = 5
00101b = 6
00110b = 7
00111b = 8
01000b = 9
01001b = 10
01010b = 12
01011b = 14
01100b = 16
01101b = 18
01110b = 20
01111b = 22
10000b = 24
10001b = 26
10010b = 28
10011b = 32
10100b = 40
10101b = 48
10110b = 56
10111b = 64
11000b = 72
11001b = 80
11010b = 88
11011b = 96
11100b = 104
11101b = 112
11110b = 120
11111b = 128
7:0
RESERVED
R
00000000b
Reserved
Always reads 00000000b
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8.6.1.62 OCCA_HIGH_THRESHOLD Register (Address = 88h) [Reset = 7FFFh]
Return to the Summary Table.
图8-107. OCCA_HIGH_THRESHOLD Register
15
14
13
12
OCCA_HIGH_TH[15:0]
R/W-0111111111111111b
11
10
9
1
8
0
7
6
5
4
3
2
OCCA_HIGH_TH[15:0]
R/W-0111111111111111b
表8-86. OCCA_HIGH_THRESHOLD Register Field Descriptions
Bit
15:0
Field
Type
Reset
Description
OCCA_HIGH_TH[15:0]
R/W
011111111111111 ADC1A overcurrent comparator high threshold bits [15:0]
1b Value provided in two's complement format.
LSB size = (2 x VREFA) / (GAIN1A x 216
)
Values larger than the high threshold trigger an OCCA_HTn event. Setting the value to +FS
(= 7FFFh) disables the high threshold detection.
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8.6.1.63 OCCA_LOW_THRESHOLD Register (Address = 89h) [Reset = 8000h]
Return to the Summary Table.
图8-108. OCCA_LOW_THRESHOLD Register
15
14
13
12
OCCA_LOW_TH[15:0]
R/W-1000000000000000b
11
10
9
1
8
0
7
6
5
4
3
2
OCCA_LOW_TH[15:0]
R/W-1000000000000000b
表8-87. OCCA_LOW_THRESHOLD Register Field Descriptions
Bit
15:0
Field
Type
Reset
Description
OCCA_LOW_TH[15:0]
R/W
1000000000000 ADC1A overcurrent comparator low threshold bits [15:0]
000b Value provided in two's complement format.
LSB size = (2 x VREFA) / (GAIN1A x 216
)
Values smaller than the low threshold trigger an OCCA_LTn event. Setting the value to –FS
(= 8000h) disables the low threshold detection.
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8.6.1.64 SPARE_8Ah Register (Address = 8Ah) [Reset = 5555h]
Return to the Summary Table.
图8-109. SPARE_8Ah Register
15
14
13
12
11
10
2
9
1
8
0
SPARE[15:0]
R/W-0101010101010101b
7
6
5
4
3
SPARE[15:0]
R/W-0101010101010101b
表8-88. SPARE_8Ah Register Field Descriptions
Bit
15:0
Field
Type
Reset
Description
SPARE[15:0]
R/W
0101010101010 Spare bits
101b
Provided as R/W bits as a means to check the register map section 2 CRC. Bit settings
have no effect.
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8.6.1.65 ADC2A_CFG1 Register (Address = 8Bh) [Reset = 8010h]
Return to the Summary Table.
图8-110. ADC2A_CFG1 Register
15
14
13
12
11
10
9
8
ADC2A_EN
R/W-1b
RESERVED
R-0000b
VCMA_EN
R/W-0b
OWD2A_SOURCE_MUX[2:0]
R/W-000b
7
6
5
4
3
2
1
0
OWD2A_SOURCE_
MUX[2:0]
OWD2A_SINK_MUX[2:0]
R/W-001b
OWD2A_SOURCE_VALUE[1:0]
OWD2A_SINK_VALUE[1:0]
R/W-000b
R/W-00b
R/W-00b
表8-89. ADC2A_CFG1 Register Field Descriptions
Bit
Field
Type
Reset
Description
15
ADC2A_EN
R/W
1b
ADC2A enable
Enables ADC2A.
Only change settings of registers from address 8Ch to 9Fh of ADC2A when ADC2A is
disabled.
The conversion data of ADC2A reset to 0000h and the sequence counter
SEQ2A_COUNT[1:0] resets to 00b when ADC2A is disabled or when the device is put in
standby or power-down mode.
0b = Disabled
1b = Enabled
14:11
10
RESERVED
VCMA_EN
R
0000b
0b
Reserved
Always reads 0000b.
R/W
Common-mode output buffer VCMA enable
Enables the common-mode output buffer VCMA on analog input V7A.
0b = Disabled
1b = Enabled
9:7
OWD2A_SOURCE_MUX[2:0]
R/W
000b
ADC2A current source multiplexer selection
Selects the multiplexer channel for the ADC2A current source.
000b = V0A
001b = V1A
010b = V2A
011b = V3A
100b = V4A
101b = V5A
110b = V6A
111b = V7A
6:4
OWD2A_SINK_MUX[2:0]
R/W
001b
ADC2A current sink multiplexer selection
Selects the multiplexer channel for the ADC2A current sink.
000b = V0A
001b = V1A
010b = V2A
011b = V3A
100b = V4A
101b = V5A
110b = V6A
111b = V7A
3:2
1:0
OWD2A_SOURCE_VALUE[1:0]
OWD2A_SINK_VALUE[1:0]
R/W
R/W
00b
00b
ADC2A current source value selection
Selects the current value for the ADC2A current source.
00b = Off
01b = 4 µA
10b = 40 µA
11b = 240 µA
ADC2A current sink value selection
Selects the current value for the ADC2A current sink.
00b = Off
01b = 4 µA
10b = 40 µA
11b = 240 µA
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8.6.1.66 ADC2A_CFG2 Register (Address = 8Ch) [Reset = 0000h]
Return to the Summary Table.
图8-111. ADC2A_CFG2 Register
15
14
13
12
11
10
2
9
8
0
SEQ2A_MODE[1:0]
R/W-00b
RESERVED
R-000b
MUX2A_DELAY[2:0]
R/W-000b
7
6
5
4
3
1
RESERVED
R-000000b
OSR2A[1:0]
R/W-00b
表8-90. ADC2A_CFG2 Register Field Descriptions
Bit
Field
Type
Reset
Description
15:14
SEQ2A_MODE[1:0]
R/W
00b
ADC2A sequencer mode selection
Selects the way the ADC2A sequencer starts a new sequence. Setting the SEQ2A_START
bit always aborts and restarts an ongoing sequence in all modes.
00b = Single-shot sequence mode based on SEQ2A_START bit (ADC2A runs one time
through the sequence after the SEQ2A_START bit is set)
01b = Single-shot sequence mode based on ADC1A conversion starts or SEQ2A_START
bit. This setting is only useful when ADC1A is configured for continuous-conversion mode.
Sequences are started at the falling edge of DRDYAn or when the SEQ2A_START bit is set.
Conversion starts triggered by the DRDYAn signal are ignored, that is do not abort and
restart a sequence, while a sequence is ongoing.
10b = Continuous sequence mode based on SEQ2A_START bit
11b = Continuous sequence mode based on SEQ2A_START bit
13:11
10:8
RESERVED
R
000b
000b
Reserved
Always reads 00b.
MUX2A_DELAY[2:0]
R/W
ADC2A multiplexer delay time selection
Selects the delay time before starting conversion on the next sequence step.
000b = 16 x tMCLK (= 2 µs for fMCLK = 8.192 MHz)
001b = 64 x tMCLK (= 7.8 µs for fMCLK = 8.192 MHz)
010b = 128 x tMCLK (= 15.6 µs for fMCLK = 8.192 MHz)
011b = 256 x tMCLK (= 31.2 µs for fMCLK = 8.192 MHz)
100b = 512 x tMCLK (= 62.5 µs for fMCLK = 8.192 MHz)
101b = 1024 x tMCLK (= 124.9 µs for fMCLK = 8.192 MHz)
110b = 2048 x tMCLK (= 249.9 µs for fMCLK = 8.192 MHz)
111b = 4096 x tMCLK (= 499.7 µs for fMCLK = 8.192 MHz)
7:2
1:0
RESERVED
OSR2A[1:0]
R
000000b
00b
Reserved
Always reads 000000b.
R/W
ADC2A oversampling ratio selection
Selects the oversampling ratio for ADC2A.
00b = 64 (SINC3 OSR = 64, conversion time = 384 x tMCLK
)
01b = 128 (SINC3 OSR = 64, SINC1 OSR = 2, conversion time = 512 x tMCLK
10b = 256 (SINC3 OSR = 64, SINC1 OSR = 4, conversion time = 768 x tMCLK
)
)
11b = 512 (SINC3 OSR = 64, SINC1 OSR = 8, conversion time = 1280 x tMCLK
)
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8.6.1.67 SPARE_8Dh Register (Address = 8Dh) [Reset = 0000h]
Return to the Summary Table.
图8-112. SPARE_8Dh Register
15
14
13
12
11
10
2
9
1
8
0
RESERVED
R-00000000b
7
6
5
4
3
SPARE[7:0]
R/W-00000000b
表8-91. SPARE_8Dh Register Field Descriptions
Bit
Field
Type
Reset
Description
15:8
RESERVED
R
00000000b
Reserved
Always reads 00000000b.
7:0
SPARE[7:0]
R/W
00000000b
Spare bits
Provided as R/W bits as a means to check the register map section 2 CRC. Bit settings
have no effect.
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8.6.1.68 ADC2A_OCAL Register (Address = 8Eh) [Reset = 0000h]
Return to the Summary Table.
图8-113. ADC2A_OCAL Register
15
14
13
12
11
10
2
9
1
8
0
OCAL2A[15:0]
R/W-0000000000000000b
7
6
5
4
3
OCAL2A[15:0]
R/W-0000000000000000b
表8-92. ADC2A_OCAL Register Field Descriptions
Bit
15:0
Field
OCAL2A[15:0]
Type
Reset
Description
R/W
0000000000000 ADC2A offset calibration bits [15:0]
000b
Value provided in two's complement format.
GAIN2A = 1: LSB size = (2 x VREFA) / 216
GAIN2A = 2, 4: LSB size = (2 x VREFA) / (2 x 216
)
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8.6.1.69 ADC2A_GCAL Register (Address = 8Fh) [Reset = 0000h]
Return to the Summary Table.
图8-114. ADC2A_GCAL Register
15
14
13
12
11
10
2
9
1
8
0
GCAL2A[15:0]
R/W-0000000000000000b
7
6
5
4
3
GCAL2A[15:0]
R/W-0000000000000000b
表8-93. ADC2A_GCAL Register Field Descriptions
Bit
15:0
Field
GCAL2A[15:0]
Type
Reset
Description
R/W
0000000000000 ADC2A gain calibration bits [15:0]
000b
Value provided in two's complement format.
LSB size = 1/216 = 0.000015
Mapping:
0111111111111111b = 1.499985
0000000000000001b = 1.000015
0000000000000000b = 1
1111111111111111b = 0.999985
1000000000000000b = 0.5
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8.6.1.70 SEQ2A_STEP0_CFG Register (Address = 90h) [Reset = 0000h]
Return to the Summary Table.
图8-115. SEQ2A_STEP0_CFG Register
15
14
13
12
11
10
9
1
8
0
SEQ2A_STEP0_EN
R/W-0b
SEQ2A_STEP0_GAIN[1:0]
R/W-00b
RESERVED
R-00000000b
7
6
5
4
3
2
RESERVED
SEQ2A_STEP0_CH_
N
SEQ2A_STEP0_CH_P[3:0]
R-00000000b
R/W-0b
R/W-0000b
表8-94. SEQ2A_STEP0_CFG Register Field Descriptions
Bit
Field
Type
Reset
Description
15
SEQ2A_STEP0_EN
R/W
0b
ADC2A sequence step 0 enable
Enables sequence step 0 of the ADC2A sequencer.
0b = Disabled
1b = Enabled
14:13
SEQ2A_STEP0_GAIN[1:0]
R/W
00b
ADC2A sequence step 0 gain selection
Selects the gain of ADC2A for sequence step 0.
00b = 1
01b = 2
10b = 4
11b = 4
12:5
4
RESERVED
R
00000000b
0b
Reserved
Always reads 00000000b.
SEQ2A_STEP0_CH_N
R/W
ADC2A sequence step 0 negative input channel selection
Selects the negative ADC2A analog input for sequence step 0.
0b = AGNDA
1b = V7A
3:0
SEQ2A_STEP0_CH_P[3:0]
R/W
0000b
ADC2A sequence step 0 positive input channel selection
Selects the positive ADC2A analog input for sequence step 0. For settings where the
negative ADC input is automatically selected, the SEQ2A_STEP0_CH_N bit has no effect.
0000b = V0A
0001b = V1A
0010b = V2A
0011b = V3A
0100b = V4A
0101b = V5A
0110b = V6A
0111b = V7A
1000b = Temperature sensor A (negative ADC input is automatically selected)
1001b = Internal short to AGNDA, disconnected from inputs (negative ADC input is
automatically selected)
1010b = Test DAC B (negative ADC input is automatically selected)
1011b = AVDD/4 (negative ADC input is automatically selected)
1100b = IOVDD/4 (negative ADC input is automatically selected)
1101b = DVDD/2 (negative ADC input is automatically selected)
1110b = APWR/103 (negative ADC input is automatically selected)
1111b = DPWR/103 (negative ADC input is automatically selected)
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8.6.1.71 SEQ2A_STEP1_CFG Register (Address = 91h) [Reset = 0001h]
Return to the Summary Table.
图8-116. SEQ2A_STEP1_CFG Register
15
14
13
12
11
10
9
1
8
0
SEQ2A_STEP1_EN
R/W-0b
SEQ2A_STEP1_GAIN[1:0]
R/W-00b
RESERVED
R-00000000b
7
6
5
4
3
2
RESERVED
SEQ2A_STEP1_CH_
N
SEQ2A_STEP1_CH_P[3:0]
R-00000000b
R/W-0b
R/W-0001b
表8-95. SEQ2A_STEP1_CFG Register Field Descriptions
Bit
Field
Type
Reset
Description
15
SEQ2A_STEP1_EN
R/W
0b
ADC2A sequence step 1 enable
Enables sequence step 1 of the ADC2A sequencer.
0b = Disabled
1b = Enabled
14:13
SEQ2A_STEP1_GAIN[1:0]
R/W
00b
ADC2A sequence step 1 gain selection
Selects the gain of ADC2A for sequence step 1.
00b = 1
01b = 2
10b = 4
11b = 4
12:5
4
RESERVED
R
00000000b
0b
Reserved
Always reads 00000000b.
SEQ2A_STEP1_CH_N
R/W
ADC2A sequence step 1 negative input channel selection
Selects the negative ADC2A analog input for sequence step 1.
0b = AGNDA
1b = V7A
3:0
SEQ2A_STEP1_CH_P[3:0]
R/W
0001b
ADC2A sequence step 1 positive input channel selection
Selects the positive ADC2A analog input for sequence step 1. For settings where the
negative ADC input is automatically selected, the SEQ2A_STEP1_CH_N bit has no effect.
0000b = V0A
0001b = V1A
0010b = V2A
0011b = V3A
0100b = V4A
0101b = V5A
0110b = V6A
0111b = V7A
1000b = Temperature sensor A (negative ADC input is automatically selected)
1001b = Internal short to AGNDA, disconnected from inputs (negative ADC input is
automatically selected)
1010b = Test DAC B (negative ADC input is automatically selected)
1011b = AVDD/4 (negative ADC input is automatically selected)
1100b = IOVDD/4 (negative ADC input is automatically selected)
1101b = DVDD/2 (negative ADC input is automatically selected)
1110b = APWR/103 (negative ADC input is automatically selected)
1111b = DPWR/103 (negative ADC input is automatically selected)
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8.6.1.72 SEQ2A_STEP2_CFG Register (Address = 92h) [Reset = 0002h]
Return to the Summary Table.
图8-117. SEQ2A_STEP2_CFG Register
15
14
13
12
11
10
9
1
8
0
SEQ2A_STEP2_EN
R/W-0b
SEQ2A_STEP2_GAIN[1:0]
R/W-00b
RESERVED
R-00000000b
7
6
5
4
3
2
RESERVED
SEQ2A_STEP2_CH_
N
SEQ2A_STEP2_CH_P[3:0]
R-00000000b
R/W-0b
R/W-0010b
表8-96. SEQ2A_STEP2_CFG Register Field Descriptions
Bit
Field
Type
Reset
Description
15
SEQ2A_STEP2_EN
R/W
0b
ADC2A sequence step 2 enable
Enables sequence step 2 of the ADC2A sequencer.
0b = Disabled
1b = Enabled
14:13
SEQ2A_STEP2_GAIN[1:0]
R/W
00b
ADC2A sequence step 2 gain selection
Selects the gain of ADC2A for sequence step 2.
00b = 1
01b = 2
10b = 4
11b = 4
12:5
4
RESERVED
R
00000000b
0b
Reserved
Always reads 00000000b.
SEQ2A_STEP2_CH_N
R/W
ADC2A sequence step 2 negative input channel selection
Selects the negative ADC2A analog input for sequence step 2.
0b = AGNDA
1b = V7A
3:0
SEQ2A_STEP2_CH_P[3:0]
R/W
0010b
ADC2A sequence step 2 positive input channel selection
Selects the positive ADC2A analog input for sequence step 2. For settings where the
negative ADC input is automatically selected, the SEQ2A_STEP2_CH_N bit has no effect.
0000b = V0A
0001b = V1A
0010b = V2A
0011b = V3A
0100b = V4A
0101b = V5A
0110b = V6A
0111b = V7A
1000b = Temperature sensor A (negative ADC input is automatically selected)
1001b = Internal short to AGNDA, disconnected from inputs (negative ADC input is
automatically selected)
1010b = Test DAC B (negative ADC input is automatically selected)
1011b = AVDD/4 (negative ADC input is automatically selected)
1100b = IOVDD/4 (negative ADC input is automatically selected)
1101b = DVDD/2 (negative ADC input is automatically selected)
1110b = APWR/103 (negative ADC input is automatically selected)
1111b = DPWR/103 (negative ADC input is automatically selected)
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8.6.1.73 SEQ2A_STEP3_CFG Register (Address = 93h) [Reset = 0003h]
Return to the Summary Table.
图8-118. SEQ2A_STEP3_CFG Register
15
14
13
12
11
10
9
1
8
0
SEQ2A_STEP3_EN
R/W-0b
SEQ2A_STEP3_GAIN[1:0]
R/W-00b
RESERVED
R-00000000b
7
6
5
4
3
2
RESERVED
SEQ2A_STEP3_CH_
N
SEQ2A_STEP3_CH_P[3:0]
R-00000000b
R/W-0b
R/W-0011b
表8-97. SEQ2A_STEP3_CFG Register Field Descriptions
Bit
Field
Type
Reset
Description
15
SEQ2A_STEP3_EN
R/W
0b
ADC2A sequence step 3 enable
Enables sequence step 3 of the ADC2A sequencer.
0b = Disabled
1b = Enabled
14:13
SEQ2A_STEP3_GAIN[1:0]
R/W
00b
ADC2A sequence step 3 gain selection
Selects the gain of ADC2A for sequence step 3.
00b = 1
01b = 2
10b = 4
11b = 4
12:5
4
RESERVED
R
00000000b
0b
Reserved
Always reads 00000000b.
SEQ2A_STEP3_CH_N
R/W
ADC2A sequence step 3 negative input channel selection
Selects the negative ADC2A analog input for sequence step 3.
0b = AGNDA
1b = V7A
3:0
SEQ2A_STEP3_CH_P[3:0]
R/W
0011b
ADC2A sequence step 3 positive input channel selection
Selects the positive ADC2A analog input for sequence step 3. For settings where the
negative ADC input is automatically selected, the SEQ2A_STEP3_CH_N bit has no effect.
0000b = V0A
0001b = V1A
0010b = V2A
0011b = V3A
0100b = V4A
0101b = V5A
0110b = V6A
0111b = V7A
1000b = Temperature sensor A (negative ADC input is automatically selected)
1001b = Internal short to AGNDA, disconnected from inputs (negative ADC input is
automatically selected)
1010b = Test DAC B (negative ADC input is automatically selected)
1011b = AVDD/4 (negative ADC input is automatically selected)
1100b = IOVDD/4 (negative ADC input is automatically selected)
1101b = DVDD/2 (negative ADC input is automatically selected)
1110b = APWR/103 (negative ADC input is automatically selected)
1111b = DPWR/103 (negative ADC input is automatically selected)
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8.6.1.74 SEQ2A_STEP4_CFG Register (Address = 94h) [Reset = 0004h]
Return to the Summary Table.
图8-119. SEQ2A_STEP4_CFG Register
15
14
13
12
11
10
9
1
8
0
SEQ2A_STEP4_EN
R/W-0b
SEQ2A_STEP4_GAIN[1:0]
R/W-00b
RESERVED
R-00000000b
7
6
5
4
3
2
RESERVED
SEQ2A_STEP4_CH_
N
SEQ2A_STEP4_CH_P[3:0]
R-00000000b
R/W-0b
R/W-0100b
表8-98. SEQ2A_STEP4_CFG Register Field Descriptions
Bit
Field
Type
Reset
Description
15
SEQ2A_STEP4_EN
R/W
0b
ADC2A sequence step 4 enable
Enables sequence step 4 of the ADC2A sequencer.
0b = Disabled
1b = Enabled
14:13
SEQ2A_STEP4_GAIN[1:0]
R/W
00b
ADC2A sequence step 4 gain selection
Selects the gain of ADC2A for sequence step 4.
00b = 1
01b = 2
10b = 4
11b = 4
12:5
4
RESERVED
R
00000000b
0b
Reserved
Always reads 00000000b.
SEQ2A_STEP4_CH_N
R/W
ADC2A sequence step 4 negative input channel selection
Selects the negative ADC2A analog input for sequence step 4.
0b = AGNDA
1b = V7A
3:0
SEQ2A_STEP4_CH_P[3:0]
R/W
0100b
ADC2A sequence step 4 positive input channel selection
Selects the positive ADC2A analog input for sequence step 4. For settings where the
negative ADC input is automatically selected, the SEQ2A_STEP4_CH_N bit has no effect.
0000b = V0A
0001b = V1A
0010b = V2A
0011b = V3A
0100b = V4A
0101b = V5A
0110b = V6A
0111b = V7A
1000b = Temperature sensor A (negative ADC input is automatically selected)
1001b = Internal short to AGNDA, disconnected from inputs (negative ADC input is
automatically selected)
1010b = Test DAC B (negative ADC input is automatically selected)
1011b = AVDD/4 (negative ADC input is automatically selected)
1100b = IOVDD/4 (negative ADC input is automatically selected)
1101b = DVDD/2 (negative ADC input is automatically selected)
1110b = APWR/103 (negative ADC input is automatically selected)
1111b = DPWR/103 (negative ADC input is automatically selected)
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8.6.1.75 SEQ2A_STEP5_CFG Register (Address = 95h) [Reset = 0005h]
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图8-120. SEQ2A_STEP5_CFG Register
15
14
13
12
11
10
9
1
8
0
SEQ2A_STEP5_EN
R/W-0b
SEQ2A_STEP5_GAIN[1:0]
R/W-00b
RESERVED
R-00000000b
7
6
5
4
3
2
RESERVED
SEQ2A_STEP5_CH_
N
SEQ2A_STEP5_CH_P[3:0]
R-00000000b
R/W-0b
R/W-0101b
表8-99. SEQ2A_STEP5_CFG Register Field Descriptions
Bit
Field
Type
Reset
Description
15
SEQ2A_STEP5_EN
R/W
0b
ADC2A sequence step 5 enable
Enables sequence step 5 of the ADC2A sequencer.
0b = Disabled
1b = Enabled
14:13
SEQ2A_STEP5_GAIN[1:0]
R/W
00b
ADC2A sequence step 5 gain selection
Selects the gain of ADC2A for sequence step 5.
00b = 1
01b = 2
10b = 4
11b = 4
12:5
4
RESERVED
R
00000000b
0b
Reserved
Always reads 00000000b.
SEQ2A_STEP5_CH_N
R/W
ADC2A sequence step 5 negative input channel selection
Selects the negative ADC2A analog input for sequence step 5.
0b = AGNDA
1b = V7A
3:0
SEQ2A_STEP5_CH_P[3:0]
R/W
0101b
ADC2A sequence step 5 positive input channel selection
Selects the positive ADC2A analog input for sequence step 5. For settings where the
negative ADC input is automatically selected, the SEQ2A_STEP5_CH_N bit has no effect.
0000b = V0A
0001b = V1A
0010b = V2A
0011b = V3A
0100b = V4A
0101b = V5A
0110b = V6A
0111b = V7A
1000b = Temperature sensor A (negative ADC input is automatically selected)
1001b = Internal short to AGNDA, disconnected from inputs (negative ADC input is
automatically selected)
1010b = Test DAC B (negative ADC input is automatically selected)
1011b = AVDD/4 (negative ADC input is automatically selected)
1100b = IOVDD/4 (negative ADC input is automatically selected)
1101b = DVDD/2 (negative ADC input is automatically selected)
1110b = APWR/103 (negative ADC input is automatically selected)
1111b = DPWR/103 (negative ADC input is automatically selected)
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8.6.1.76 SEQ2A_STEP6_CFG Register (Address = 96h) [Reset = 0006h]
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图8-121. SEQ2A_STEP6_CFG Register
15
14
13
12
11
10
9
1
8
0
SEQ2A_STEP6_EN
R/W-0b
SEQ2A_STEP6_GAIN[1:0]
R/W-00b
RESERVED
R-00000000b
7
6
5
4
3
2
RESERVED
SEQ2A_STEP6_CH_
N
SEQ2A_STEP6_CH_P[3:0]
R-00000000b
R/W-0b
R/W-0110b
表8-100. SEQ2A_STEP6_CFG Register Field Descriptions
Bit
Field
Type
Reset
Description
15
SEQ2A_STEP6_EN
R/W
0b
ADC2A sequence step 6 enable
Enables sequence step 6 of the ADC2A sequencer.
0b = Disabled
1b = Enabled
14:13
SEQ2A_STEP6_GAIN[1:0]
R/W
00b
ADC2A sequence step 6 gain selection
Selects the gain of ADC2A for sequence step 6.
00b = 1
01b = 2
10b = 4
11b = 4
12:5
4
RESERVED
R
00000000b
0b
Reserved
Always reads 00000000b.
SEQ2A_STEP6_CH_N
R/W
ADC2A sequence step 6 negative input channel selection
Selects the negative ADC2A analog input for sequence step 6.
0b = AGNDA
1b = V7A
3:0
SEQ2A_STEP6_CH_P[3:0]
R/W
0110b
ADC2A sequence step 6 positive input channel selection
Selects the positive ADC2A analog input for sequence step 6. For settings where the
negative ADC input is automatically selected, the SEQ2A_STEP6_CH_N bit has no effect.
0000b = V0A
0001b = V1A
0010b = V2A
0011b = V3A
0100b = V4A
0101b = V5A
0110b = V6A
0111b = V7A
1000b = Temperature sensor A (negative ADC input is automatically selected)
1001b = Internal short to AGNDA, disconnected from inputs (negative ADC input is
automatically selected)
1010b = Test DAC B (negative ADC input is automatically selected)
1011b = AVDD/4 (negative ADC input is automatically selected)
1100b = IOVDD/4 (negative ADC input is automatically selected)
1101b = DVDD/2 (negative ADC input is automatically selected)
1110b = APWR/103 (negative ADC input is automatically selected)
1111b = DPWR/103 (negative ADC input is automatically selected)
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8.6.1.77 SEQ2A_STEP7_CFG Register (Address = 97h) [Reset = 0007h]
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图8-122. SEQ2A_STEP7_CFG Register
15
14
13
12
11
10
9
1
8
0
SEQ2A_STEP7_EN
R/W-0b
SEQ2A_STEP7_GAIN[1:0]
R/W-00b
RESERVED
R-00000000b
7
6
5
4
3
2
RESERVED
SEQ2A_STEP7_CH_
N
SEQ2A_STEP7_CH_P[3:0]
R-00000000b
R/W-0b
R/W-0111b
表8-101. SEQ2A_STEP7_CFG Register Field Descriptions
Bit
Field
Type
Reset
Description
15
SEQ2A_STEP7_EN
R/W
0b
ADC2A sequence step 7 enable
Enables sequence step 7 of the ADC2A sequencer.
0b = Disabled
1b = Enabled
14:13
SEQ2A_STEP7_GAIN[1:0]
R/W
00b
ADC2A sequence step 7 gain selection
Selects the gain of ADC2A for sequence step 7.
00b = 1
01b = 2
10b = 4
11b = 4
12:5
4
RESERVED
R
00000000b
0b
Reserved
Always reads 00000000b.
SEQ2A_STEP7_CH_N
R/W
ADC2A sequence step 7 negative input channel selection
Selects the negative ADC2A analog input for sequence step 7.
0b = AGNDA
1b = V7A
3:0
SEQ2A_STEP7_CH_P[3:0]
R/W
0111b
ADC2A sequence step 7 positive input channel selection
Selects the positive ADC2A analog input for sequence step 7. For settings where the
negative ADC input is automatically selected, the SEQ2A_STEP7_CH_N bit has no effect.
0000b = V0A
0001b = V1A
0010b = V2A
0011b = V3A
0100b = V4A
0101b = V5A
0110b = V6A
0111b = V7A
1000b = Temperature sensor A (negative ADC input is automatically selected)
1001b = Internal short to AGNDA, disconnected from inputs (negative ADC input is
automatically selected)
1010b = Test DAC B (negative ADC input is automatically selected)
1011b = AVDD/4 (negative ADC input is automatically selected)
1100b = IOVDD/4 (negative ADC input is automatically selected)
1101b = DVDD/2 (negative ADC input is automatically selected)
1110b = APWR/103 (negative ADC input is automatically selected)
1111b = DPWR/103 (negative ADC input is automatically selected)
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8.6.1.78 SEQ2A_STEP8_CFG Register (Address = 98h) [Reset = 0008h]
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图8-123. SEQ2A_STEP8_CFG Register
15
14
13
12
11
10
9
1
8
0
SEQ2A_STEP8_EN
R/W-0b
SEQ2A_STEP8_GAIN[1:0]
R/W-00b
RESERVED
R-00000000b
7
6
5
4
3
2
RESERVED
SEQ2A_STEP8_CH_
N
SEQ2A_STEP8_CH_P[3:0]
R-00000000b
R/W-0b
R/W-1000b
表8-102. SEQ2A_STEP8_CFG Register Field Descriptions
Bit
Field
Type
Reset
Description
15
SEQ2A_STEP8_EN
R/W
0b
ADC2A sequence step 8 enable
Enables sequence step 8 of the ADC2A sequencer.
0b = Disabled
1b = Enabled
14:13
SEQ2A_STEP8_GAIN[1:0]
R/W
00b
ADC2A sequence step 8 gain selection
Selects the gain of ADC2A for sequence step 8.
00b = 1
01b = 2
10b = 4
11b = 4
12:5
4
RESERVED
R
00000000b
0b
Reserved
Always reads 00000000b.
SEQ2A_STEP8_CH_N
R/W
ADC2A sequence step 8 negative input channel selection
Selects the negative ADC2A analog input for sequence step 8.
0b = AGNDA
1b = V7A
3:0
SEQ2A_STEP8_CH_P[3:0]
R/W
1000b
ADC2A sequence step 8 positive input channel selection
Selects the positive ADC2A analog input for sequence step 8. For settings where the
negative ADC input is automatically selected, the SEQ2A_STEP8_CH_N bit has no effect.
0000b = V0A
0001b = V1A
0010b = V2A
0011b = V3A
0100b = V4A
0101b = V5A
0110b = V6A
0111b = V7A
1000b = Temperature sensor A (negative ADC input is automatically selected)
1001b = Internal short to AGNDA, disconnected from inputs (negative ADC input is
automatically selected)
1010b = Test DAC B (negative ADC input is automatically selected)
1011b = AVDD/4 (negative ADC input is automatically selected)
1100b = IOVDD/4 (negative ADC input is automatically selected)
1101b = DVDD/2 (negative ADC input is automatically selected)
1110b = APWR/103 (negative ADC input is automatically selected)
1111b = DPWR/103 (negative ADC input is automatically selected)
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8.6.1.79 SEQ2A_STEP9_CFG Register (Address = 99h) [Reset = 0009h]
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图8-124. SEQ2A_STEP9_CFG Register
15
14
13
12
11
10
9
1
8
0
SEQ2A_STEP9_EN
R/W-0b
SEQ2A_STEP9_GAIN[1:0]
R/W-00b
RESERVED
R-00000000b
7
6
5
4
3
2
RESERVED
SEQ2A_STEP9_CH_
N
SEQ2A_STEP9_CH_P[3:0]
R-00000000b
R/W-0b
R/W-1001b
表8-103. SEQ2A_STEP9_CFG Register Field Descriptions
Bit
Field
Type
Reset
Description
15
SEQ2A_STEP9_EN
R/W
0b
ADC2A sequence step 9 enable
Enables sequence step 9 of the ADC2A sequencer.
0b = Disabled
1b = Enabled
14:13
SEQ2A_STEP9_GAIN[1:0]
R/W
00b
ADC2A sequence step 9 gain selection
Selects the gain of ADC2A for sequence step 9.
00b = 1
01b = 2
10b = 4
11b = 4
12:5
4
RESERVED
R
00000000b
0b
Reserved
Always reads 00000000b.
SEQ2A_STEP9_CH_N
R/W
ADC2A sequence step 9 negative input channel selection
Selects the negative ADC2A analog input for sequence step 9.
0b = AGNDA
1b = V7A
3:0
SEQ2A_STEP9_CH_P[3:0]
R/W
1001b
ADC2A sequence step 9 positive input channel selection
Selects the positive ADC2A analog input for sequence step 9. For settings where the
negative ADC input is automatically selected, the SEQ2A_STEP9_CH_N bit has no effect.
0000b = V0A
0001b = V1A
0010b = V2A
0011b = V3A
0100b = V4A
0101b = V5A
0110b = V6A
0111b = V7A
1000b = Temperature sensor A (negative ADC input is automatically selected)
1001b = Internal short to AGNDA, disconnected from inputs (negative ADC input is
automatically selected)
1010b = Test DAC B (negative ADC input is automatically selected)
1011b = AVDD/4 (negative ADC input is automatically selected)
1100b = IOVDD/4 (negative ADC input is automatically selected)
1101b = DVDD/2 (negative ADC input is automatically selected)
1110b = APWR/103 (negative ADC input is automatically selected)
1111b = DPWR/103 (negative ADC input is automatically selected)
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8.6.1.80 SEQ2A_STEP10_CFG Register (Address = 9Ah) [Reset = 000Ah]
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图8-125. SEQ2A_STEP10_CFG Register
15
14
13
12
11
10
9
1
8
0
SEQ2A_STEP10_EN
R/W-0b
SEQ2A_STEP10_GAIN[1:0]
R/W-00b
RESERVED
R-00000000b
7
6
5
4
3
2
RESERVED
SEQ2A_STEP10_CH
_N
SEQ2A_STEP10_CH_P[3:0]
R-00000000b
R/W-0b
R/W-1010b
表8-104. SEQ2A_STEP10_CFG Register Field Descriptions
Bit
Field
Type
Reset
Description
15
SEQ2A_STEP10_EN
R/W
0b
ADC2A sequence step 10 enable
Enables sequence step 10 of the ADC2A sequencer.
0b = Disabled
1b = Enabled
14:13
SEQ2A_STEP10_GAIN[1:0]
R/W
00b
ADC2A sequence step 10 gain selection
Selects the gain of ADC2A for sequence step 10.
00b = 1
01b = 2
10b = 4
11b = 4
12:5
4
RESERVED
R
00000000b
0b
Reserved
Always reads 00000000b.
SEQ2A_STEP10_CH_N
R/W
ADC2A sequence step 10 negative input channel selection
Selects the negative ADC2A analog input for sequence step 10.
0b = AGNDA
1b = V7A
3:0
SEQ2A_STEP10_CH_P[3:0]
R/W
1010b
ADC2A sequence step 10 positive input channel selection
Selects the positive ADC2A analog input for sequence step 10. For settings where the
negative ADC input is automatically selected, the SEQ2A_STEP10_CH_N bit has no effect.
0000b = V0A
0001b = V1A
0010b = V2A
0011b = V3A
0100b = V4A
0101b = V5A
0110b = V6A
0111b = V7A
1000b = Temperature sensor A (negative ADC input is automatically selected)
1001b = Internal short to AGNDA, disconnected from inputs (negative ADC input is
automatically selected)
1010b = Test DAC B (negative ADC input is automatically selected)
1011b = AVDD/4 (negative ADC input is automatically selected)
1100b = IOVDD/4 (negative ADC input is automatically selected)
1101b = DVDD/2 (negative ADC input is automatically selected)
1110b = APWR/103 (negative ADC input is automatically selected)
1111b = DPWR/103 (negative ADC input is automatically selected)
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8.6.1.81 SEQ2A_STEP11_CFG Register (Address = 9Bh) [Reset = 000Bh]
Return to the Summary Table.
图8-126. SEQ2A_STEP11_CFG Register
15
14
13
12
11
10
9
1
8
0
SEQ2A_STEP11_EN
R/W-0b
SEQ2A_STEP11_GAIN[1:0]
R/W-00b
RESERVED
R-00000000b
7
6
5
4
3
2
RESERVED
SEQ2A_STEP11_CH
_N
SEQ2A_STEP11_CH_P[3:0]
R-00000000b
R/W-0b
R/W-1011b
表8-105. SEQ2A_STEP11_CFG Register Field Descriptions
Bit
Field
Type
Reset
Description
15
SEQ2A_STEP11_EN
R/W
0b
ADC2A sequence step 11 enable
Enables sequence step 11 of the ADC2A sequencer.
0b = Disabled
1b = Enabled
14:13
SEQ2A_STEP11_GAIN[1:0]
R/W
00b
ADC2A sequence step 11 gain selection
Selects the gain of ADC2A for sequence step 11.
00b = 1
01b = 2
10b = 4
11b = 4
12:5
4
RESERVED
R
00000000b
0b
Reserved
Always reads 00000000b.
SEQ2A_STEP11_CH_N
R/W
ADC2A sequence step 11 negative input channel selection
Selects the negative ADC2A analog input for sequence step 11.
0b = AGNDA
1b = V7A
3:0
SEQ2A_STEP11_CH_P[3:0]
R/W
1011b
ADC2A sequence step 11 positive input channel selection
Selects the positive ADC2A analog input for sequence step 11. For settings where the
negative ADC input is automatically selected, the SEQ2A_STEP11_CH_N bit has no effect.
0000b = V0A
0001b = V1A
0010b = V2A
0011b = V3A
0100b = V4A
0101b = V5A
0110b = V6A
0111b = V7A
1000b = Temperature sensor A (negative ADC input is automatically selected)
1001b = Internal short to AGNDA, disconnected from inputs (negative ADC input is
automatically selected)
1010b = Test DAC B (negative ADC input is automatically selected)
1011b = AVDD/4 (negative ADC input is automatically selected)
1100b = IOVDD/4 (negative ADC input is automatically selected)
1101b = DVDD/2 (negative ADC input is automatically selected)
1110b = APWR/103 (negative ADC input is automatically selected)
1111b = DPWR/103 (negative ADC input is automatically selected)
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8.6.1.82 SEQ2A_STEP12_CFG Register (Address = 9Ch) [Reset = 000Ch]
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图8-127. SEQ2A_STEP12_CFG Register
15
14
13
12
11
10
9
1
8
0
SEQ2A_STEP12_EN
R/W-0b
SEQ2A_STEP12_GAIN[1:0]
R/W-00b
RESERVED
R-00000000b
7
6
5
4
3
2
RESERVED
SEQ2A_STEP12_CH
_N
SEQ2A_STEP12_CH_P[3:0]
R-00000000b
R/W-0b
R/W-1100b
表8-106. SEQ2A_STEP12_CFG Register Field Descriptions
Bit
Field
Type
Reset
Description
15
SEQ2A_STEP12_EN
R/W
0b
ADC2A sequence step 12 enable
Enables sequence step 12 of the ADC2A sequencer.
0b = Disabled
1b = Enabled
14:13
SEQ2A_STEP12_GAIN[1:0]
R/W
00b
ADC2A sequence step 12 gain selection
Selects the gain of ADC2A for sequence step 12.
00b = 1
01b = 2
10b = 4
11b = 4
12:5
4
RESERVED
R
00000000b
0b
Reserved
Always reads 00000000b.
SEQ2A_STEP12_CH_N
R/W
ADC2A sequence step 12 negative input channel selection
Selects the negative ADC2A analog input for sequence step 12.
0b = AGNDA
1b = V7A
3:0
SEQ2A_STEP12_CH_P[3:0]
R/W
1100b
ADC2A sequence step 12 positive input channel selection
Selects the positive ADC2A analog input for sequence step 12. For settings where the
negative ADC input is automatically selected, the SEQ2A_STEP12_CH_N bit has no effect.
0000b = V0A
0001b = V1A
0010b = V2A
0011b = V3A
0100b = V4A
0101b = V5A
0110b = V6A
0111b = V7A
1000b = Temperature sensor A (negative ADC input is automatically selected)
1001b = Internal short to AGNDA, disconnected from inputs (negative ADC input is
automatically selected)
1010b = Test DAC B (negative ADC input is automatically selected)
1011b = AVDD/4 (negative ADC input is automatically selected)
1100b = IOVDD/4 (negative ADC input is automatically selected)
1101b = DVDD/2 (negative ADC input is automatically selected)
1110b = APWR/103 (negative ADC input is automatically selected)
1111b = DPWR/103 (negative ADC input is automatically selected)
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8.6.1.83 SEQ2A_STEP13_CFG Register (Address = 9Dh) [Reset = 000Dh]
Return to the Summary Table.
图8-128. SEQ2A_STEP13_CFG Register
15
14
13
12
11
10
9
1
8
0
SEQ2A_STEP13_EN
R/W-0b
SEQ2A_STEP13_GAIN[1:0]
R/W-00b
RESERVED
R-00000000b
7
6
5
4
3
2
RESERVED
SEQ2A_STEP13_CH
_N
SEQ2A_STEP13_CH_P[3:0]
R-00000000b
R/W-0b
R/W-1101b
表8-107. SEQ2A_STEP13_CFG Register Field Descriptions
Bit
Field
Type
Reset
Description
15
SEQ2A_STEP13_EN
R/W
0b
ADC2A sequence step 13 enable
Enables sequence step 13 of the ADC2A sequencer.
0b = Disabled
1b = Enabled
14:13
SEQ2A_STEP13_GAIN[1:0]
R/W
00b
ADC2A sequence step 13 gain selection
Selects the gain of ADC2A for sequence step 13.
00b = 1
01b = 2
10b = 4
11b = 4
12:5
4
RESERVED
R
00000000b
0b
Reserved
Always reads 00000000b.
SEQ2A_STEP13_CH_N
R/W
ADC2A sequence step 13 negative input channel selection
Selects the negative ADC2A analog input for sequence step 13.
0b = AGNDA
1b = V7A
3:0
SEQ2A_STEP13_CH_P[3:0]
R/W
1101b
ADC2A sequence step 13 positive input channel selection
Selects the positive ADC2A analog input for sequence step 13. For settings where the
negative ADC input is automatically selected, the SEQ2A_STEP13_CH_N bit has no effect.
0000b = V0A
0001b = V1A
0010b = V2A
0011b = V3A
0100b = V4A
0101b = V5A
0110b = V6A
0111b = V7A
1000b = Temperature sensor A (negative ADC input is automatically selected)
1001b = Internal short to AGNDA, disconnected from inputs (negative ADC input is
automatically selected)
1010b = Test DAC B (negative ADC input is automatically selected)
1011b = AVDD/4 (negative ADC input is automatically selected)
1100b = IOVDD/4 (negative ADC input is automatically selected)
1101b = DVDD/2 (negative ADC input is automatically selected)
1110b = APWR/103 (negative ADC input is automatically selected)
1111b = DPWR/103 (negative ADC input is automatically selected)
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8.6.1.84 SEQ2A_STEP14_CFG Register (Address = 9Eh) [Reset = 000Eh]
Return to the Summary Table.
图8-129. SEQ2A_STEP14_CFG Register
15
14
13
12
11
10
9
1
8
0
SEQ2A_STEP14_EN
R/W-0b
SEQ2A_STEP14_GAIN[1:0]
R/W-00b
RESERVED
R-00000000b
7
6
5
4
3
2
RESERVED
SEQ2A_STEP14_CH
_N
SEQ2A_STEP14_CH_P[3:0]
R-00000000b
R/W-0b
R/W-1110b
表8-108. SEQ2A_STEP14_CFG Register Field Descriptions
Bit
Field
Type
Reset
Description
15
SEQ2A_STEP14_EN
R/W
0b
ADC2A sequence step 14 enable
Enables sequence step 14 of the ADC2A sequencer.
0b = Disabled
1b = Enabled
14:13
SEQ2A_STEP14_GAIN[1:0]
R/W
00b
ADC2A sequence step 14 gain selection
Selects the gain of ADC2A for sequence step 14.
00b = 1
01b = 2
10b = 4
11b = 4
12:5
4
RESERVED
R
00000000b
0b
Reserved
Always reads 00000000b.
SEQ2A_STEP14_CH_N
R/W
ADC2A sequence step 14 negative input channel selection
Selects the negative ADC2A analog input for sequence step 14.
0b = AGNDA
1b = V7A
3:0
SEQ2A_STEP14_CH_P[3:0]
R/W
1110b
ADC2A sequence step 14 positive input channel selection
Selects the positive ADC2A analog input for sequence step 14. For settings where the
negative ADC input is automatically selected, the SEQ2A_STEP14_CH_N bit has no effect.
0000b = V0A
0001b = V1A
0010b = V2A
0011b = V3A
0100b = V4A
0101b = V5A
0110b = V6A
0111b = V7A
1000b = Temperature sensor A (negative ADC input is automatically selected)
1001b = Internal short to AGNDA, disconnected from inputs (negative ADC input is
automatically selected)
1010b = Test DAC B (negative ADC input is automatically selected)
1011b = AVDD/4 (negative ADC input is automatically selected)
1100b = IOVDD/4 (negative ADC input is automatically selected)
1101b = DVDD/2 (negative ADC input is automatically selected)
1110b = APWR/103 (negative ADC input is automatically selected)
1111b = DPWR/103 (negative ADC input is automatically selected)
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8.6.1.85 SEQ2A_STEP15_CFG Register (Address = 9Fh) [Reset = 000Fh]
Return to the Summary Table.
图8-130. SEQ2A_STEP15_CFG Register
15
14
13
12
11
10
9
1
8
0
SEQ2A_STEP15_EN
R/W-0b
SEQ2A_STEP15_GAIN[1:0]
R/W-00b
RESERVED
R-00000000b
7
6
5
4
3
2
RESERVED
SEQ2A_STEP15_CH
_N
SEQ2A_STEP15_CH_P[3:0]
R-00000000b
R/W-0b
R/W-1111b
表8-109. SEQ2A_STEP15_CFG Register Field Descriptions
Bit
Field
Type
Reset
Description
15
SEQ2A_STEP15_EN
R/W
0b
ADC2A sequence step 15 enable
Enables sequence step 15 of the ADC2A sequencer.
0b = Disabled
1b = Enabled
14:13
SEQ2A_STEP15_GAIN[1:0]
R/W
00b
ADC2A sequence step 15 gain selection
Selects the gain of ADC2A for sequence step 15.
00b = 1
01b = 2
10b = 4
11b = 4
12:5
4
RESERVED
R
00000000b
0b
Reserved
Always reads 00000000b.
SEQ2A_STEP15_CH_N
R/W
ADC2A sequence step 15 negative input channel selection
Selects the negative ADC2A analog input for sequence step 15.
0b = AGNDA
1b = V7A
3:0
SEQ2A_STEP15_CH_P[3:0]
R/W
1111b
ADC2A sequence step 15 positive input channel selection
Selects the positive ADC2A analog input for sequence step 15. For settings where the
negative ADC input is automatically selected, the SEQ2A_STEP15_CH_N bit has no effect.
0000b = V0A
0001b = V1A
0010b = V2A
0011b = V3A
0100b = V4A
0101b = V5A
0110b = V6A
0111b = V7A
1000b = Temperature sensor A (negative ADC input is automatically selected)
1001b = Internal short to AGNDA, disconnected from inputs (negative ADC input is
automatically selected)
1010b = Test DAC B (negative ADC input is automatically selected)
1011b = AVDD/4 (negative ADC input is automatically selected)
1100b = IOVDD/4 (negative ADC input is automatically selected)
1101b = DVDD/2 (negative ADC input is automatically selected)
1110b = APWR/103 (negative ADC input is automatically selected)
1111b = DPWR/103 (negative ADC input is automatically selected)
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8.6.1.86 SPARE_A0h Register (Address = A0h) [Reset = 0210h]
Return to the Summary Table.
图8-131. SPARE_A0h Register
15
14
13
12
11
10
2
9
1
8
RESERVED
R-0000b
SPARE[1:0]
R/W-00b
RESERVED
R-1000b
7
6
5
4
3
0
RESERVED
R-1000b
SPARE[1:0]
R/W-01b
RESERVED
R-0000b
表8-110. SPARE_A0h Register Field Descriptions
Bit
Field
Type
Reset
Description
15:12
RESERVED
R
0000b
Reserved
Always reads 0000b.
11:10
SPARE[1:0]
R/W
00b
Spare bits
Provided as R/W bits as a means to check the register map section 2 CRC. Bit settings
have no effect.
9:6
5:4
RESERVED
SPARE[1:0]
R
1000b
01b
Reserved
Always reads 1000b.
R/W
Spare bits
Provided as R/W bits as a means to check the register map section 2 CRC. Bit settings
have no effect.
3:0
RESERVED
R
0000b
Reserved
Always reads 0000b.
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8.6.1.87 SPARE_A1h Register (Address = A1h) [Reset = 0000h]
Return to the Summary Table.
图8-132. SPARE_A1h Register
15
14
13
12
11
10
2
9
1
8
0
SPARE[15:0]
R/W-0000000000000000b
7
6
5
4
3
SPARE[15:0]
R/W-0000000000000000b
表8-111. SPARE_A1h Register Field Descriptions
Bit
15:0
Field
Type
Reset
Description
SPARE[15:0]
R/W
0000000000000 Spare bits
000b
Provided as R/W bits as a means to check the register map section 2 CRC. Bit settings
have no effect.
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8.6.1.88 SPARE_A2h Register (Address = A2h) [Reset = 0000h]
Return to the Summary Table.
图8-133. SPARE_A2h Register
15
14
13
12
11
10
2
9
1
8
0
SPARE[7:0]
R/W-00000000b
7
6
5
4
3
RESERVED
R-00000000b
表8-112. SPARE_A2h Register Field Descriptions
Bit
Field
Type
Reset
Description
15:8
SPARE[7:0]
R/W
00000000b
Spare bits
Provided as R/W bits as a means to check the register map section 2 CRC. Bit settings
have no effect.
7:0
RESERVED
R
00000000b
Reserved
Always reads 00000000b.
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8.6.1.89 SPARE_A3h Register (Address = A3h) [Reset = 0000h]
Return to the Summary Table.
图8-134. SPARE_A3h Register
15
14
13
12
11
10
2
9
1
8
0
SPARE[15:0]
R/W-0000000000000000b
7
6
5
4
3
SPARE[15:0]
R/W-0000000000000000b
表8-113. SPARE_A3h Register Field Descriptions
Bit
15:0
Field
Type
Reset
Description
SPARE[15:0]
R/W
0000000000000 Spare bits
000b
Provided as R/W bits as a means to check the register map section 2 CRC. Bit settings
have no effect.
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8.6.1.90 REGISTER_MAP2_CRC Register (Address = BEh) [Reset = 0000h]
Return to the Summary Table.
图8-135. REGISTER_MAP2_CRC Register
15
14
13
12
11
10
9
1
8
0
REG_MAP2_CRC_VALUE[15:0]
R/W-0000000000000000b
7
6
5
4
3
2
REG_MAP2_CRC_VALUE[15:0]
R/W-0000000000000000b
表8-114. REGISTER_MAP2_CRC Register Field Descriptions
Bit
15:0
Field
Type
Reset
Description
REG_MAP2_CRC_VALUE[15:0]
R/W
0000000000000 Register map CRC value for section 2
000b Register map CRC value for section 2.
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8.6.1.91 REGMAP3_TDACB_CFG Register (Address = C0h) [Reset = 0000h]
Return to the Summary Table.
图8-136. REGMAP3_TDACB_CFG Register
15
14
13
12
11
10
9
8
0
REG_MAP3_CRC_E
N
RESERVED
R/W-0b
7
R-000000000000b
3
6
5
4
2
1
RESERVED
TDACB_VALUE[2:0]
R/W-000b
R-000000000000b
表8-115. REGMAP3_TDACB_CFG Register Field Descriptions
Bit
Field
Type
Reset
Description
15
REG_MAP3_CRC_EN
R/W
0b
Register map section 3 CRC enable
Enables the register map CRC for section 3 (register address space from C0h to E3h).
0b = Disabled
1b = Enabled
14:3
2:0
RESERVED
R
000000000000b Reserved
Always reads 000000000000b.
TDACB_VALUE[2:0]
R/W
000b
Test DAC B output value
Selects the output value of Test DAC B.
000b = 1 x VREFB/40
001b = 2 x VREFB/40
010b = 4 x VREFB/40
011b = 9 x VREFB/40
100b = 18 x VREFB/40
101b = 36 x VREFB/40
110b = –4 x VREFB/40
111b = –9 x VREFB/40
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8.6.1.92 GPIOB_CFG Register (Address = C1h) [Reset = 8000h]
Return to the Summary Table.
图8-137. GPIOB_CFG Register
15
14
13
12
11
10
9
8
RESERVED
R-1b
SPARE[2:0]
R/W-000b
GPIO1B_FMT
R/W-0b
GPIO0B_FMT
R/W-0b
GPIO1B_DIR
R/W-0b
GPIO0B_DIR
R/W-0b
7
6
5
4
3
2
1
0
GPIO1B_PWM_TB[1:0]
GPIO0B_PWM_TB[1:0]
R/W-00b
SPARE[1:0]
R/W-00b
GPO1B_DAT
R/W-0b
GPO0B_DAT
R/W-0b
R/W-00b
表8-116. GPIOB_CFG Register Field Descriptions
Bit
Field
Type
Reset
Description
15
RESERVED
R
1b
Reserved
Always reads 1b.
14:12
11
SPARE[2:0]
R/W
R/W
000b
0b
Spare bits
Provided as R/W bits as a means to check the register map section 2 CRC. Bit settings
have no effect.
GPIO1B_FMT
GPIO1B format
Configures GPIO1B for static input and output levels or for PWM input levels.
0b = When GPIO1B is configured as a digital input: Logic levels are based on static input
levels. When GPIO1B is configured as a digital output: Output with static output levels.
1b = When GPIO1B is configured as a digital input: Logic levels are based on PWM input
decoding. When GPIO1B is configured as a digital output: Output with static output levels.
GPIO1B does not have PWM output capability.
10
GPIO0B_FMT
R/W
0b
GPIO0B format
Configures GPIO0B for static input and output levels or for PWM input levels.
0b = When GPIO0B is configured as a digital input: Logic levels are based on static input
levels. When GPIO0B is configured as a digital output: Output with static output levels.
1b = When GPIO0B is configured as a digital input: Logic levels are based on PWM input
decoding. When GPIO0B is configured as a digital output: Output with static output levels.
GPIO0B does not have PWM output capability.
9
8
GPIO1B_DIR
R/W
R/W
R/W
0b
GPIO1B direction
Configures GPIO1B as a digital input or digital output.
0b = Digital input
1b = Digital output
GPIO0B_DIR
0b
GPIO0B direction
Configures GPIO0B as a digital input or digital output.
0b = Digital input
1b = Digital output
7:6
GPIO1B_PWM_TB[1:0]
00b
GPIO1B PWM time base selection
Selects the time base used for the PWM encoder when GPIO1B is configured as a digital
input.
00b = 16 x tMCLK (= 1/512 kHz for fMCLK = 8.192 MHz)
01b = 64 x tMCLK (= 1/128 kHz for fMCLK = 8.192 MHz)
10b = 256 x tMCLK (= 1/32 kHz for fMCLK = 8.192 MHz)
11b = 1024 x tMCLK (= 1/8 kHz for fMCLK = 8.192 MHz)
5:4
GPIO0B_PWM_TB[1:0]
R/W
00b
GPIO0B PWM time base selection
Selects the time base used for the PWM encoder when GPIO0B is configured as a digital
input.
00b = 16 x tMCLK (= 1/512 kHz for fMCLK = 8.192 MHz)
01b = 64 x tMCLK (= 1/128 kHz for fMCLK = 8.192 MHz)
10b = 256 x tMCLK (= 1/32 kHz for fMCLK = 8.192 MHz)
11b = 1024 x tMCLK (= 1/8 kHz for fMCLK = 8.192 MHz)
3:2
1
SPARE[1:0]
R/W
R/W
00b
0b
Spare bits
Provided as R/W bits as a means to check the register map section 2 CRC. Bit settings
have no effect.
GPO1B_DAT
GPIO1B output data
Output value of GPIO1B when configured as an output. Bit setting has not effect when
GPIO1B is configured as a digital input.
0b = Low
1b = High
0
GPO0B_DAT
R/W
0b
GPIO0B output data
Output value of GPIO0B when configured as an output. Bit setting has not effect when
GPIO0B is configured as a digital input.
0b = Low
1b = High
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8.6.1.93 ADC1B_CFG1 Register (Address = C2h) [Reset = 0400h]
Return to the Summary Table.
图8-138. ADC1B_CFG1 Register
15
14
13
12
11
10
2
9
8
0
RESERVED
R-0000b
CONV_MODE1B
R/W-0b
OSR1B[2:0]
R/W-100b
7
6
5
4
3
1
RESERVED
R-0000b
GC1B_EN
R/W-0b
GC1B_DELAY[2:0]
R/W-000b
表8-117. ADC1B_CFG1 Register Field Descriptions
Bit
Field
Type
Reset
Description
15:12
RESERVED
R
0000b
Reserved
Always reads 0000b.
11
CONV_MODE1B
OSR1B[2:0]
R/W
R/W
0b
Conversion mode selection
Selects the conversion mode for ADC1B.
0b = Continuous-conversion mode
1b = Single-shot conversion mode
10:8
100b
Oversampling ratio selection
Selects the oversampling ratio for ADC1B. The data rate calculates to fMOD / OSR.
000b = 64
001b = 128
010b = 256
011b = 512
100b = 1024
101b = 2048
110b = 4096
111b = 8192
7:4
3
RESERVED
GC1B_EN
R
0000b
0b
Reserved
Always reads 0000b.
R/W
Global-chop mode enable
Enables the global-chop mode for ADC1B.
0b = Disabled
1b = Enabled
2:0
GC1B_DELAY[2:0]
R/W
000b
Global-chop mode delay time selection
Selects the delay time in global-chop mode for ADC1B.
000b = 2 x tMOD
001b = 4 x tMOD
010b = 8 x tMOD
011b = 16 x tMOD
100b = 32 x tMOD
101b = 64 x tMOD
110b = 128 x tMOD
111b = 256 x tMOD
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8.6.1.94 ADC1B_CFG2 Register (Address = C3h) [Reset = 8010h]
Return to the Summary Table.
图8-139. ADC1B_CFG2 Register
15
14
13
12
11
10
2
9
1
8
ADC1B_EN
R/W-1b
RESERVED
R-000b
GAIN1B[1:0]
R/W-00b
MUX1B[1:0]
R/W-00b
7
6
5
4
3
0
RESERVED
R-00b
OWD1B_SOURCE_ OWD1B_SINK_MUX
MUX
OWD1B_SOURCE_VALUE[1:0]
OWD1B_SINK_VALUE[1:0]
R/W-0b
R/W-1b
R/W-00b
R/W-00b
表8-118. ADC1B_CFG2 Register Field Descriptions
Bit
Field
Type
Reset
Description
15
ADC1B_EN
R/W
1b
ADC1B enable
Enables ADC1B.
The conversion data of ADC1B reset to 000000h and the conversion counter
CONV1B_COUNT[1:0] resets to 00b when ADC1B is disabled or when the device is put in
standby or power-down mode..
0b = Disabled
1b = Enabled
14:12
11:10
RESERVED
GAIN1B[1:0]
R
000b
00b
Reserved
Always reads 000b.
R/W
ADC1B gain selection
Selects the gain (FSR = full scale range) of ADC1B. Gains 16 and 32 are digital gains using
analog gain = 8.
00b = 4
01b = 8
10b = 16
11b = 32
9:8
MUX1B[1:0]
RESERVED
R/W
00b
ADC1B multiplexer channel selection
Selects the multiplexer channel for ADC1B.
00b = AINp = CPB, AINn = CNB
01b = AINp = CNB, AINn = CPB
10b = Internal short to AGNDB. Analog inputs CPB, CNB disconnected from ADC1B.
11b = Test DAC A output
7:6
5
R
00b
0b
Reserved
Always reads 00b.
OWD1B_SOURCE_MUX
R/W
ADC1B current source multiplexer selection
Selects the multiplexer channel for the ADC1B current source.
0b = CPB
1b = CNB
4
OWD1B_SINK_MUX
R/W
R/W
1b
ADC1B current sink multiplexer selection
Selects the multiplexer channel for the ADC1B current sink.
0b = CPB
1b = CNB
3:2
OWD1B_SOURCE_VALUE[1:0]
00b
ADC1B current source value selection
Selects the current value for the ADC1B current source.
00b = Off
01b = 4 µA
10b = 40 µA
11b = 240 µA
1:0
OWD1B_SINK_VALUE[1:0]
R/W
00b
ADC1B current sink value selection
Selects the current value for the ADC1B current sink.
00b = Off
01b = 4 µA
10b = 40 µA
11b = 240 µA
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8.6.1.95 ADC1B_OCAL_MSB Register (Address = C4h) [Reset = 0000h]
Return to the Summary Table.
图8-140. ADC1B_OCAL_MSB Register
15
14
13
12
11
10
9
1
8
0
OCAL1B[23:8]
R/W-0000000000000000b
7
6
5
4
3
2
OCAL1B[23:8]
R/W-0000000000000000b
表8-119. ADC1B_OCAL_MSB Register Field Descriptions
Bit
15:0
Field
OCAL1B[23:8]
Type
Reset
Description
R/W
0000000000000 ADC1B offset calibration bits [23:8]
000b Value provided in two's complement format.
LSB size = (2 x VREFB) / (GAIN1B x 224
)
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8.6.1.96 ADC1B_OCAL_LSB Register (Address = C5h) [Reset = 0000h]
Return to the Summary Table.
图8-141. ADC1B_OCAL_LSB Register
15
14
13
12
11
10
9
1
8
0
OCAL1B[7:0]
R/W-00000000b
7
6
5
4
3
2
RESERVED
R-00000000b
表8-120. ADC1B_OCAL_LSB Register Field Descriptions
Bit
Field
Type
Reset
Description
15:8
OCAL1B[7:0]
R/W
00000000b
ADC1B offset calibration bits [7:0]
Value provided in two's complement format.
LSB size = (2 x VREFB) / (GAIN1B x 224
)
7:0
RESERVED
R
00000000b
Reserved
Always reads 00000000b.
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8.6.1.97 ADC1B_GCAL Register (Address = C6h) [Reset = 0000h]
Return to the Summary Table.
图8-142. ADC1B_GCAL Register
15
14
13
12
11
10
2
9
1
8
0
GCAL1B[15:0]
R/W-0000000000000000b
7
6
5
4
3
GCAL1B[15:0]
R/W-0000000000000000b
表8-121. ADC1B_GCAL Register Field Descriptions
Bit
15:0
Field
GCAL1B[15:0]
Type
Reset
Description
R/W
0000000000000 ADC1B gain calibration bits [15:0]
000b
Value provided in two's complement format.
LSB size = 1/216 = 0.000015
Mapping:
0111111111111111b = 1.499985
0000000000000001b = 1.000015
0000000000000000b = 1
1111111111111111b = 0.999985
1000000000000000b = 0.5
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8.6.1.98 OCCB_CFG Register (Address = C7h) [Reset = 0000h]
Return to the Summary Table.
图8-143. OCCB_CFG Register
15
14
13
12
11
10
9
1
8
0
OCCB_EN
R/W-0b
OCCB_POL
R/W-0b
RESERVED
R/W-0b
OCCB_NUM[4:0]
R/W-00000b
7
6
5
4
3
2
RESERVED
R-00000000b
表8-122. OCCB_CFG Register Field Descriptions
Bit
Field
Type
Reset
Description
15
OCCB_EN
R/W
0b
ADC1B overcurrent comparator enable
Enables the digital fast filter and digital comparator on ADC1B. ADC1B must be enabled to
use the overcurrent comparator. The fast filter is not affected by the STARTB and STOPB
bits.
0b = Disabled
1b = Enabled
14
OCCB_POL
R/W
0b
OCCB pin polarity selection
Selects the polarity of the OCCB pin. The actual output behavior of the GPIO4/OCCB pin,
when configured as OCCB output in the GPIO4_SRC bit, depends on the GPIO4_FMT
setting. An OCCB fault is active when any of the OCCB_HTn or OCCB_LTn bits are active.
0b = Active low. In case of a fault a logic low level is driven.
1b = Active high. In case of a fault a logic high level is driven.
13
RESERVED
R/W
R/W
0b
Reserved
Always write 0b.
12:8
OCCB_NUM[4:0]
00000b
ADC1B overcurrent comparator deglitch filter selection
Selects the number of conversions the output of the ADC1B digital fast filter must exceed
the set high or low thresholds to trip the OCCB_HTn or OCCB_LTn comparator output. The
fast filter path uses a SINC3 filter with a fixed OSR = 64. The counter starts again whenever
the digital fast filter output falls below the threshold, means there is no hysteresis.
00000b = 1
00001b = 2
00010b = 3
00011b = 4
00100b = 5
00101b = 6
00110b = 7
00111b = 8
01000b = 9
01001b = 10
01010b = 12
01011b = 14
01100b = 16
01101b = 18
01110b = 20
01111b = 22
10000b = 24
10001b = 26
10010b = 28
10011b = 32
10100b = 40
10101b = 48
10110b = 56
10111b = 64
11000b = 72
11001b = 80
11010b = 88
11011b = 96
11100b = 104
11101b = 112
11110b = 120
11111b = 128
7:0
RESERVED
R
00000000b
Reserved
Always reads 00000000b.
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8.6.1.99 OCCB_HIGH_THRESHOLD Register (Address = C8h) [Reset = 7FFFh]
Return to the Summary Table.
图8-144. OCCB_HIGH_THRESHOLD Register
15
14
13
12
OCCB_HIGH_TH[15:0]
R/W-0111111111111111b
11
10
9
1
8
0
7
6
5
4
3
2
OCCB_HIGH_TH[15:0]
R/W-0111111111111111b
表8-123. OCCB_HIGH_THRESHOLD Register Field Descriptions
Bit
15:0
Field
Type
Reset
Description
OCCB_HIGH_TH[15:0]
R/W
011111111111111 ADC1B overcurrent comparator high threshold bits [15:0]
1b Value provided in two's complement format.
LSB size = (2 x VREFB) / (GAIN1B x 216
)
Values larger than the high threshold trigger an OCCB_HTn event. Setting the value to +FS
(= 7FFFh) disables the high threshold detection.
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8.6.1.100 OCCB_LOW_THRESHOLD Register (Address = C9h) [Reset = 8000h]
Return to the Summary Table.
图8-145. OCCB_LOW_THRESHOLD Register
15
14
13
12
OCCB_LOW_TH[15:0]
R/W-1000000000000000b
11
10
9
1
8
0
7
6
5
4
3
2
OCCB_LOW_TH[15:0]
R/W-1000000000000000b
表8-124. OCCB_LOW_THRESHOLD Register Field Descriptions
Bit
15:0
Field
Type
Reset
Description
OCCB_LOW_TH[15:0]
R/W
1000000000000 ADC1B overcurrent comparator low threshold bits [15:0]
000b Value provided in two's complement format.
LSB size = (2 x VREFB) / (GAIN1B x 216
)
Values smaller than the low threshold trigger an OCCB_LTn event. Setting the value to –FS
(= 8000h) disables the low threshold detection.
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8.6.1.101 SPARE_CAh Register (Address = CAh) [Reset = 5555h]
Return to the Summary Table.
图8-146. SPARE_CAh Register
15
14
13
12
11
10
2
9
1
8
0
SPARE[15:0]
R/W-0101010101010101b
7
6
5
4
3
SPARE[15:0]
R/W-0101010101010101b
表8-125. SPARE_CAh Register Field Descriptions
Bit
15:0
Field
Type
Reset
Description
SPARE[15:0]
R/W
0101010101010 Spare bits
101b
Provided as R/W bits as a means to check the register map section 3 CRC. Bit settings
have no effect.
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8.6.1.102 SPARE_CBh Register (Address = CBh) [Reset = 0010h]
Return to the Summary Table.
图8-147. SPARE_CBh Register
15
14
13
12
11
10
2
9
8
0
RESERVED
R-00000b
SPARE[6:0]
R/W-0000001b
7
6
5
4
3
1
SPARE[6:0]
R/W-0000001b
RESERVED
R-0000b
表8-126. SPARE_CBh Register Field Descriptions
Bit
Field
Type
Reset
Description
15:11
RESERVED
R
00000b
Reserved
Always reads 00000b.
10:4
SPARE[6:0]
RESERVED
R/W
R
0000001b
0000b
Spare bits
Provided as R/W bits as a means to check the register map section 3 CRC. Bit settings
have no effect.
3:0
Reserved
Always reads 0000b.
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8.6.1.103 SPARE_CCh Register (Address = CCh) [Reset = 0000h]
Return to the Summary Table.
图8-148. SPARE_CCh Register
15
14
13
12
11
10
2
9
8
0
SPARE[1:0]
R/W-00b
RESERVED
R-000b
SPARE[2:0]
R/W-000b
7
6
5
4
3
1
RESERVED
R-000000b
SPARE[1:0]
R/W-00b
表8-127. SPARE_CCh Register Field Descriptions
Bit
Field
Type
Reset
Description
15:14
SPARE[1:0]
R/W
00b
Spare bits
Provided as R/W bits as a means to check the register map section 3 CRC. Bit settings
have no effect.
13:11
10:8
RESERVED
SPARE[2:0]
R
000b
000b
Reserved
Always reads 00b.
R/W
Spare bits
Provided as R/W bits as a means to check the register map section 3 CRC. Bit settings
have no effect.
7:2
1:0
RESERVED
SPARE[1:0]
R
000000b
00b
Reserved
Always reads 000000b.
R/W
Spare bits
Provided as R/W bits as a means to check the register map section 3 CRC. Bit settings
have no effect.
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8.6.1.104 SPARE_CDh Register (Address = CDh) [Reset = 0000h]
Return to the Summary Table.
图8-149. SPARE_CDh Register
15
14
13
12
11
10
2
9
1
8
0
RESERVED
R-00000000b
7
6
5
4
3
SPARE[7:0]
R/W-00000000b
表8-128. SPARE_CDh Register Field Descriptions
Bit
Field
Type
Reset
Description
15:8
RESERVED
R
00000000b
Reserved
Always reads 00000000b.
7:0
SPARE[7:0]
R/W
00000000b
Spare bits
Provided as R/W bits as a means to check the register map section 3 CRC. Bit settings
have no effect.
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8.6.1.105 SPARE_CEh Register (Address = CEh) [Reset = 0000h]
Return to the Summary Table.
图8-150. SPARE_CEh Register
15
14
13
12
11
10
2
9
1
8
0
SPARE[15:0]
R/W-0000000000000000b
7
6
5
4
3
SPARE[15:0]
R/W-0000000000000000b
表8-129. SPARE_CEh Register Field Descriptions
Bit
15:0
Field
Type
Reset
Description
SPARE[15:0]
R/W
0000000000000 Spare bits
000b
Provided as R/W bits as a means to check the register map section 3 CRC. Bit settings
have no effect.
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8.6.1.106 SPARE_CFh Register (Address = CFh) [Reset = 0000h]
Return to the Summary Table.
图8-151. SPARE_CFh Register
15
14
13
12
11
10
2
9
1
8
0
SPARE[15:0]
R/W-0000000000000000b
7
6
5
4
3
SPARE[15:0]
R/W-0000000000000000b
表8-130. SPARE_CFh Register Field Descriptions
Bit
15:0
Field
Type
Reset
Description
SPARE[15:0]
R/W
0000000000000 Spare bits
000b
Provided as R/W bits as a means to check the register map section 3 CRC. Bit settings
have no effect.
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8.6.1.107 SPARE_D0h Register (Address = D0h) [Reset = 0000h]
Return to the Summary Table.
图8-152. SPARE_D0h Register
15
14
13
12
11
10
9
1
8
0
SPARE[2:0]
R/W-000b
RESERVED
R-00000000b
7
6
5
4
3
2
RESERVED
R-00000000b
SPARE[4:0]
R/W-00000b
表8-131. SPARE_D0h Register Field Descriptions
Bit
Field
Type
Reset
Description
15:13
SPARE[2:0]
R/W
000b
Spare bits
Provided as R/W bits as a means to check the register map section 3 CRC. Bit settings
have no effect.
12:5
4:0
RESERVED
SPARE[4:0]
R
00000000b
00000b
Reserved
Always reads 00000000b.
R/W
Spare bits
Provided as R/W bits as a means to check the register map section 3 CRC. Bit settings
have no effect.
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8.6.1.108 SPARE_D1h Register (Address = D1h) [Reset = 0001h]
Return to the Summary Table.
图8-153. SPARE_D1h Register
15
14
13
12
11
10
9
1
8
0
SPARE[2:0]
R/W-000b
RESERVED
R-00000000b
7
6
5
4
3
2
RESERVED
R-00000000b
SPARE[4:0]
R/W-00001b
表8-132. SPARE_D1h Register Field Descriptions
Bit
Field
Type
Reset
Description
15:13
SPARE[2:0]
R/W
000b
Spare bits
Provided as R/W bits as a means to check the register map section 3 CRC. Bit settings
have no effect.
12:5
4:0
RESERVED
SPARE[4:0]
R
00000000b
00001b
Reserved
Always reads 00000000b.
R/W
Spare bits
Provided as R/W bits as a means to check the register map section 3 CRC. Bit settings
have no effect.
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8.6.1.109 SPARE_D2h Register (Address = D2h) [Reset = 0002h]
Return to the Summary Table.
图8-154. SPARE_D2h Register
15
14
13
12
11
10
9
1
8
0
SPARE[2:0]
R/W-000b
RESERVED
R-00000000b
7
6
5
4
3
2
RESERVED
R-00000000b
SPARE[4:0]
R/W-00010b
表8-133. SPARE_D2h Register Field Descriptions
Bit
Field
Type
Reset
Description
15:13
SPARE[2:0]
R/W
000b
Spare bits
Provided as R/W bits as a means to check the register map section 3 CRC. Bit settings
have no effect.
12:5
4:0
RESERVED
SPARE[4:0]
R
00000000b
00010b
Reserved
Always reads 00000000b.
R/W
Spare bits
Provided as R/W bits as a means to check the register map section 3 CRC. Bit settings
have no effect.
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8.6.1.110 SPARE_D3h Register (Address = D3h) [Reset = 0003h]
Return to the Summary Table.
图8-155. SPARE_D3h Register
15
14
13
12
11
10
9
1
8
0
SPARE[2:0]
R/W-000b
RESERVED
R-00000000b
7
6
5
4
3
2
RESERVED
R-00000000b
SPARE[4:0]
R/W-00011b
表8-134. SPARE_D3h Register Field Descriptions
Bit
Field
Type
Reset
Description
15:13
SPARE[2:0]
R/W
000b
Spare bits
Provided as R/W bits as a means to check the register map section 3 CRC. Bit settings
have no effect.
12:5
4:0
RESERVED
SPARE[4:0]
R
00000000b
00011b
Reserved
Always reads 00000000b.
R/W
Spare bits
Provided as R/W bits as a means to check the register map section 3 CRC. Bit settings
have no effect.
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8.6.1.111 SPARE_D4h Register (Address = D4h) [Reset = 0004h]
Return to the Summary Table.
图8-156. SPARE_D4h Register
15
14
13
12
11
10
9
1
8
0
SPARE[2:0]
R/W-000b
RESERVED
R-00000000b
7
6
5
4
3
2
RESERVED
R-00000000b
SPARE[4:0]
R/W-00100b
表8-135. SPARE_D4h Register Field Descriptions
Bit
Field
Type
Reset
Description
15:13
SPARE[2:0]
R/W
000b
Spare bits
Provided as R/W bits as a means to check the register map section 3 CRC. Bit settings
have no effect.
12:5
4:0
RESERVED
SPARE[4:0]
R
00000000b
00100b
Reserved
Always reads 00000000b.
R/W
Spare bits
Provided as R/W bits as a means to check the register map section 3 CRC. Bit settings
have no effect.
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8.6.1.112 SPARE_D5h Register (Address = D5h) [Reset = 0005h]
Return to the Summary Table.
图8-157. SPARE_D5h Register
15
14
13
12
11
10
9
1
8
0
SPARE[2:0]
R/W-000b
RESERVED
R-00000000b
7
6
5
4
3
2
RESERVED
R-00000000b
SPARE[4:0]
R/W-00101b
表8-136. SPARE_D5h Register Field Descriptions
Bit
Field
Type
Reset
Description
15:13
SPARE[2:0]
R/W
000b
Spare bits
Provided as R/W bits as a means to check the register map section 3 CRC. Bit settings
have no effect.
12:5
4:0
RESERVED
SPARE[4:0]
R
00000000b
00101b
Reserved
Always reads 00000000b.
R/W
Spare bits
Provided as R/W bits as a means to check the register map section 3 CRC. Bit settings
have no effect.
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8.6.1.113 SPARE_D6h Register (Address = D6h) [Reset = 0006h]
Return to the Summary Table.
图8-158. SPARE_D6h Register
15
14
13
12
11
10
9
1
8
0
SPARE[2:0]
R/W-000b
RESERVED
R-00000000b
7
6
5
4
3
2
RESERVED
R-00000000b
SPARE[4:0]
R/W-00110b
表8-137. SPARE_D6h Register Field Descriptions
Bit
Field
Type
Reset
Description
15:13
SPARE[2:0]
R/W
000b
Spare bits
Provided as R/W bits as a means to check the register map section 3 CRC. Bit settings
have no effect.
12:5
4:0
RESERVED
SPARE[4:0]
R
00000000b
00110b
Reserved
Always reads 00000000b.
R/W
Spare bits
Provided as R/W bits as a means to check the register map section 3 CRC. Bit settings
have no effect.
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8.6.1.114 SPARE_D7h Register (Address = D7h) [Reset = 0007h]
Return to the Summary Table.
图8-159. SPARE_D7h Register
15
14
13
12
11
10
9
1
8
0
SPARE[2:0]
R/W-000b
RESERVED
R-00000000b
7
6
5
4
3
2
RESERVED
R-00000000b
SPARE[4:0]
R/W-00111b
表8-138. SPARE_D7h Register Field Descriptions
Bit
Field
Type
Reset
Description
15:13
SPARE[2:0]
R/W
000b
Spare bits
Provided as R/W bits as a means to check the register map section 3 CRC. Bit settings
have no effect.
12:5
4:0
RESERVED
SPARE[4:0]
R
00000000b
00111b
Reserved
Always reads 00000000b.
R/W
Spare bits
Provided as R/W bits as a means to check the register map section 3 CRC. Bit settings
have no effect.
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8.6.1.115 SPARE_D8h Register (Address = D8h) [Reset = 0008h]
Return to the Summary Table.
图8-160. SPARE_D8h Register
15
14
13
12
11
10
9
1
8
0
SPARE[2:0]
R/W-000b
RESERVED
R-00000000b
7
6
5
4
3
2
RESERVED
R-00000000b
SPARE[4:0]
R/W-01000b
表8-139. SPARE_D8h Register Field Descriptions
Bit
Field
Type
Reset
Description
15:13
SPARE[2:0]
R/W
000b
Spare bits
Provided as R/W bits as a means to check the register map section 3 CRC. Bit settings
have no effect.
12:5
4:0
RESERVED
SPARE[4:0]
R
00000000b
01000b
Reserved
Always reads 00000000b.
R/W
Spare bits
Provided as R/W bits as a means to check the register map section 3 CRC. Bit settings
have no effect.
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8.6.1.116 SPARE_D9h Register (Address = D9h) [Reset = 0009h]
Return to the Summary Table.
图8-161. SPARE_D9h Register
15
14
13
12
11
10
9
1
8
0
SPARE[2:0]
R/W-000b
RESERVED
R-00000000b
7
6
5
4
3
2
RESERVED
R-00000000b
SPARE[4:0]
R/W-01001b
表8-140. SPARE_D9h Register Field Descriptions
Bit
Field
Type
Reset
Description
15:13
SPARE[2:0]
R/W
000b
Spare bits
Provided as R/W bits as a means to check the register map section 3 CRC. Bit settings
have no effect.
12:5
4:0
RESERVED
SPARE[4:0]
R
00000000b
01001b
Reserved
Always reads 00000000b.
R/W
Spare bits
Provided as R/W bits as a means to check the register map section 3 CRC. Bit settings
have no effect.
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8.6.1.117 SPARE_DAh Register (Address = DAh) [Reset = 000Ah]
Return to the Summary Table.
图8-162. SPARE_DAh Register
15
14
13
12
11
10
9
1
8
0
SPARE[2:0]
R/W-000b
RESERVED
R-00000000b
7
6
5
4
3
2
RESERVED
R-00000000b
SPARE[4:0]
R/W-01010b
表8-141. SPARE_DAh Register Field Descriptions
Bit
Field
Type
Reset
Description
15:13
SPARE[2:0]
R/W
000b
Spare bits
Provided as R/W bits as a means to check the register map section 3 CRC. Bit settings
have no effect.
12:5
4:0
RESERVED
SPARE[4:0]
R
00000000b
01010b
Reserved
Always reads 00000000b.
R/W
Spare bits
Provided as R/W bits as a means to check the register map section 3 CRC. Bit settings
have no effect.
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8.6.1.118 SPARE_DBh Register (Address = DBh) [Reset = 000Bh]
Return to the Summary Table.
图8-163. SPARE_DBh Register
15
14
13
12
11
10
9
1
8
0
SPARE[2:0]
R/W-000b
RESERVED
R-00000000b
7
6
5
4
3
2
RESERVED
R-00000000b
SPARE[4:0]
R/W-01011b
表8-142. SPARE_DBh Register Field Descriptions
Bit
Field
Type
Reset
Description
15:13
SPARE[2:0]
R/W
000b
Spare bits
Provided as R/W bits as a means to check the register map section 3 CRC. Bit settings
have no effect.
12:5
4:0
RESERVED
SPARE[4:0]
R
00000000b
01011b
Reserved
Always reads 00000000b.
R/W
Spare bits
Provided as R/W bits as a means to check the register map section 3 CRC. Bit settings
have no effect.
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8.6.1.119 SPARE_DCh Register (Address = DCh) [Reset = 000Ch]
Return to the Summary Table.
图8-164. SPARE_DCh Register
15
14
13
12
11
10
9
1
8
0
SPARE[2:0]
R/W-000b
RESERVED
R-00000000b
7
6
5
4
3
2
RESERVED
R-00000000b
SPARE[4:0]
R/W-01100b
表8-143. SPARE_DCh Register Field Descriptions
Bit
Field
Type
Reset
Description
15:13
SPARE[2:0]
R/W
000b
Spare bits
Provided as R/W bits as a means to check the register map section 3 CRC. Bit settings
have no effect.
12:5
4:0
RESERVED
SPARE[4:0]
R
00000000b
01100b
Reserved
Always reads 00000000b.
R/W
Spare bits
Provided as R/W bits as a means to check the register map section 3 CRC. Bit settings
have no effect.
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8.6.1.120 SPARE_DDh Register (Address = DDh) [Reset = 000Dh]
Return to the Summary Table.
图8-165. SPARE_DDh Register
15
14
13
12
11
10
9
1
8
0
SPARE[2:0]
R/W-000b
RESERVED
R-00000000b
7
6
5
4
3
2
RESERVED
R-00000000b
SPARE[4:0]
R/W-01101b
表8-144. SPARE_DDh Register Field Descriptions
Bit
Field
Type
Reset
Description
15:13
SPARE[2:0]
R/W
000b
Spare bits
Provided as R/W bits as a means to check the register map section 3 CRC. Bit settings
have no effect.
12:5
4:0
RESERVED
SPARE[4:0]
R
00000000b
01101b
Reserved
Always reads 00000000b.
R/W
Spare bits
Provided as R/W bits as a means to check the register map section 3 CRC. Bit settings
have no effect.
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8.6.1.121 SPARE_DEh Register (Address = DEh) [Reset = 000Eh]
Return to the Summary Table.
图8-166. SPARE_DEh Register
15
14
13
12
11
10
9
1
8
0
SPARE[2:0]
R/W-000b
RESERVED
R-00000000b
7
6
5
4
3
2
RESERVED
R-00000000b
SPARE[4:0]
R/W-01110b
表8-145. SPARE_DEh Register Field Descriptions
Bit
Field
Type
Reset
Description
15:13
SPARE[2:0]
R/W
000b
Spare bits
Provided as R/W bits as a means to check the register map section 3 CRC. Bit settings
have no effect.
12:5
4:0
RESERVED
SPARE[4:0]
R
00000000b
01110b
Reserved
Always reads 00000000b.
R/W
Spare bits
Provided as R/W bits as a means to check the register map section 3 CRC. Bit settings
have no effect.
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8.6.1.122 SPARE_DFh Register (Address = DFh) [Reset = 000Fh]
Return to the Summary Table.
图8-167. SPARE_DFh Register
15
14
13
12
11
10
9
1
8
0
SPARE[2:0]
R/W-000b
RESERVED
R-00000000b
7
6
5
4
3
2
RESERVED
R-00000000b
SPARE[4:0]
R/W-01111b
表8-146. SPARE_DFh Register Field Descriptions
Bit
Field
Type
Reset
Description
15:13
SPARE[2:0]
R/W
000b
Spare bits
Provided as R/W bits as a means to check the register map section 3 CRC. Bit settings
have no effect.
12:5
4:0
RESERVED
SPARE[4:0]
R
00000000b
01111b
Reserved
Always reads 00000000b.
R/W
Spare bits
Provided as R/W bits as a means to check the register map section 3 CRC. Bit settings
have no effect.
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8.6.1.123 SPARE_E0h Register (Address = E0h) [Reset = 0210h]
Return to the Summary Table.
图8-168. SPARE_E0h Register
15
14
13
12
11
10
2
9
1
8
0
RESERVED
R-0000b
SPARE[1:0]
R/W-00b
RESERVED
R-1000b
7
6
5
4
3
RESERVED
R-1000b
SPARE[1:0]
R/W-01b
RESERVED
R-0000b
表8-147. SPARE_E0h Register Field Descriptions
Bit
Field
Type
Reset
Description
15:12
RESERVED
R
0000b
Reserved
Always reads 0000b.
11:10
SPARE[1:0]
R/W
00b
Spare bits
Provided as R/W bits as a means to check the register map section 3 CRC. Bit settings
have no effect.
9:6
5:4
RESERVED
SPARE[1:0]
R
1000b
01b
Reserved
Always reads 1000b.
R/W
Spare bits
Provided as R/W bits as a means to check the register map section 3 CRC. Bit settings
have no effect.
3:0
RESERVED
R
0000b
Reserved
Always reads 0000b.
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8.6.1.124 SPARE_E1h Register (Address = E1h) [Reset = 0000h]
Return to the Summary Table.
图8-169. SPARE_E1h Register
15
14
13
12
11
10
2
9
1
8
0
SPARE[15:0]
R/W-0000000000000000b
7
6
5
4
3
SPARE[15:0]
R/W-0000000000000000b
表8-148. SPARE_E1h Register Field Descriptions
Bit
15:0
Field
Type
Reset
Description
SPARE[15:0]
R/W
0000000000000 Spare bits
000b
Provided as R/W bits as a means to check the register map section 3 CRC. Bit settings
have no effect.
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8.6.1.125 SPARE_E2h Register (Address = E2h) [Reset = 0000h]
Return to the Summary Table.
图8-170. SPARE_E2h Register
15
14
13
12
11
10
2
9
1
8
0
SPARE[7:0]
R/W-00000000b
7
6
5
4
3
RESERVED
R-00000000b
表8-149. SPARE_E2h Register Field Descriptions
Bit
Field
Type
Reset
Description
15:8
SPARE[7:0]
R/W
00000000b
Spare bits
Provided as R/W bits as a means to check the register map section 3 CRC. Bit settings
have no effect.
7:0
RESERVED
R
00000000b
Reserved
Always reads 0x00.
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8.6.1.126 SPARE_E3h Register (Address = E3h) [Reset = 0000h]
Return to the Summary Table.
图8-171. SPARE_E3h Register
15
14
13
12
11
10
2
9
1
8
0
SPARE[15:0]
R/W-0000000000000000b
7
6
5
4
3
SPARE[15:0]
R/W-0000000000000000b
表8-150. SPARE_E3h Register Field Descriptions
Bit
15:0
Field
Type
Reset
Description
SPARE[15:0]
R/W
0000000000000 Spare bits
000b
Provided as R/W bits as a means to check the register map section 3 CRC. Bit settings
have no effect.
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8.6.1.127 REGISTER_MAP3_CRC Register (Address = FEh) [Reset = 0000h]
Return to the Summary Table.
图8-172. REGISTER_MAP3_CRC Register
15
14
13
12
11
10
9
1
8
0
REG_MAP3_CRC_VALUE[15:0]
R/W-0000000000000000b
7
6
5
4
3
2
REG_MAP3_CRC_VALUE[15:0]
R/W-0000000000000000b
表8-151. REGISTER_MAP3_CRC Register Field Descriptions
Bit
15:0
Field
Type
Reset
Description
REG_MAP3_CRC_VALUE[15:0]
R/W
0000000000000 Register map CRC value for section 3
000b Register map CRC value for section 3.
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9 Application and Implementation
备注
以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
9.1 Application Information
9.1.1 Unused Inputs and Outputs
Follow the guidelines below for the connection of unused device pins:
• Leave any unused ADCxy analog inputs floating or connect the unused analog inputs to AGNDy.
• Tie unused GPIO pins (GPIO0 to GPIO4, GPIO0A, GPIO1A, GPIO0B, and GPIO1B) to DGND when
configured as digital inputs because excessive power-supply current can result when digital inputs are left
floating.
• Tie the CLK pin to DGND if the internal main oscillator is used.
• Tie the RESETn pin to IOVDD if the host does not drive the RESETn pin. The RESETn pin does, however,
also have an internal pullup resistor to IOVDD.
• Leave the DRDYn pin unconnected if unused or connect the pin to IOVDD using a weak pullup resistor.
9.1.2 Minimum Interface Connections
The ADS131B23 requires at a minimum four pins for communication with a host microcontroller: CSn, SCLK,
SDI, and SDO. CSn cannot be tied low permanently.
The following pins are optional, but connecting these pins to the host helps with device operation:
• DRDYn: Helps determine exactly when new conversion data on ADC1A or ADC1B are available.
• RESETn: If the SPI communication is corrupted (that is, if the RESET command cannot be sent), a hardware
reset is required to recover the device. Without controlling the RESETn pin, the only way to perform a
hardware reset on the device is through cycling the power supplies.
• GPIOs: The different special functions available on the various GPIO pins, such as FAULT, MHD, OCCA, and
OCCB, help alert the host of device or system faults.
9.2 Typical Application
This section describes a typical battery management system (BMS) application circuit using the ADS131B23.
The device serves the following primary functions in this BMS:
• Measure battery current redundantly through ADC1A and ADC1B with high resolution and accuracy using a
low-side current shunt sensor.
• Measure peak battery currents and detect overcurrent or short-circuit conditions.
• Measure battery-pack voltage through ADC2A using a high-voltage resistor divider
• Measure shunt temperature through ADC2A using a linear positive temperature coefficient (PTC) thermistor,
the TMP61
图9-1 illustrates the front-end for the battery management system circuit design.
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HV_BAT+
R1
2M
R2
2M
R3
2M
AVDD
R4
2M
R6
34k
V0A
V1A
R5
12k
C1
10nF
C2
100nF
TMP61
+5V0
U1
C3
38
37
34
28
SCLK
30
APWR
HV_BAT-
AGND
SDI
1µF
IOVDD
29
DPWR
IOVDD
SDO
31
AGND
C4
CSn
To host
27
DRDYn
1µF
AVDD
C5
DGND
40
23
AVDD
RESETn
1µF
AGND
3
4
33 R7
26 R8
10k
10k
10k
10k
10k
GPIO0A
GPIO1A
GPIO0/MHD
GPIO1
GPIO2/FAULT
GPIO3/OCCA
GPIO4/OCCB
R9
R10
R11
25
24
22
V0A
V1A
2
1
V0A
V1A
V2A
V3A
V4A
V5A
V6A
V7A
HV_BAT+
48
47
46
45
44
43
32 R12
10k
CLK
DCAP
R_LOAD
R13
100
DGND
C8
C6
36
41
20
47nF
5
6
CPA
CNA
R14 100
R15 100
220nF
C9
DGND
AGND
AGND
R_SHUNT
HV_BAT-
10
9
CPB
CNB
RCAPA
RCAPB
1µF
C10
C7
47nF
11
12
13
14
15
16
17
18
NC
NC
NC
NC
NC
NC
NC
NC
R16
100
1µF
21
39
AGND
AGND
8
7
GPIO0B
GPIO1B
42
19
35
49
AGNDA
AGNDB
DGND
AGND
ADS131B23
Thermal_Pad
DGND
NT1
AGND
Net-Tie
AGND
HV_BAT-
NT2
Net-Tie
AGND
DGND
图9-1. The ADS131B23 in a Typical Battery Management System Application
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9.2.1 Design Requirements
表9-1. Design Parameters
DESIGN PARAMETER
VALUE
Current Measurement
Current measurement range
Current shunt value
±3 kA
50 μΩ
1 ms
Update rate
Battery-Pack Voltage Measurement
Voltage measurement range
Shunt Temperature Measurement
Temperature measurement range
Thermistor type
0 V to 800 V
–40°C to +125°C
TMP61 (10-kΩPTC)
9.2.2 Detailed Design Procedure
The following sections provide guidelines for selecting the external components and the configuration of the
ADS131B23 for the various measurements in this application example.
9.2.2.1 Current Shunt Measurement
In a typical BMS, the current through the shunt resistor must be measured in both directions for charging and
discharging the battery pack. In an overcurrent or short-circuit condition, the current can be as high as IBAT_MAX
=
±3 kA in this example application. Therefore, the maximum voltage drop across the shunt is up to VSHUNT
=
RSHUNT × IBAT_MAX = 50 μΩ × ±3 kA = ±150 mV.
To measure this shunt voltage, ADC1A is configured for gain = 8, which allows differential voltage
measurements of VIN1A = VCPA – VCNA = ±VREFA / 8 = ±1.25 V / 8 = ±156 mV. The integrated charge pump in
the device allows voltage measurements 312.5 mV below AGNDA while using a unipolar analog power supply.
This bipolar voltage measurement capability is important because one side of the shunt is connected to the
same GND potential as the AGNDA pin of the ADS131B23, which means that the absolute voltage that the
device must measure is up to 150 mV below AGNDA.
To enable fast overcurrent detection within 1 ms while providing high accuracy and resolution, the ADS131B23 is
operated at 4 kSPS (OSR = 1024)) using global-chop mode. Global-chop mode enables measurements with
minimal offset error over temperature and time. The conversion time using these settings is 0.75 ms according to
方程式20. The input-referred noise is approximately 1.28 μVRMS / √2 = 0.91 μVRMS following the explanations
in the Global-Chop Mode section. Thus, currents as small as 0.91 μVRMS / 50 μΩ = 18 mA can be resolved.
The resolution can be further improved by averaging the conversion results over a longer period of time in the
microcontroller that interfaces with the ADS131B23.
The –3-dB corner frequency of the differential antialiasing filter on the analog inputs (R13, R14, and C6) is set
to 1 / (2 × ᴨ × 2 × 100 Ω × 47 nF) = 16.9 kHz to provide more then 40-dB attenuation at the ADC1A modulator
frequency. Keep the series resistor values (R13 and R14) small to avoid additional offset errors created by the
voltage drop across the resistors because of the ADC1A input currents.
ADC1B is configured identical to ADC1A to allow for simultaneous sampling of the shunt voltage with the same
digital filter response.
9.2.2.2 Battery Pack Voltage Measurement
The 800-V battery-pack voltage is divided down to the voltage range of ADC2A using a high-voltage resistor
divider, consisting of R1, R2, R3, R4, and R5. Gain = 1 is used for ADC2A in this case to allow differential
voltage measurements of VIN2A = VV0A – VAGNDA = ±1.25 V. The battery-pack voltage measurement is a
unipolar, single-ended measurement with the negative multiplexer channel of ADC2A internally connected to
AGNDA. Thus, only the voltage range from 0 V to 1.25 V of ADC2A is used. 方程式 22 calculates the resistor
divider ratio.
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VV0A / VBAT_MAX = 1.25 V / 800 V = R5 / (R1 + R2 + R3 + R4 + R5)
(22)
The leakage current drawn by the resistor divider should be less than 100 μA in this example to avoid
unnecessarily draining the battery. The resistance of the divider must therefore be larger than RTOTAL
≥
VBAT_MAX / ILEAKAGE = 800 V / 100 μA = 8 MΩ. The resistor values are chosen as R1 = R2 = R3 = R4 = 2 MΩ
and R5 = 12 kΩ. Thus, the maximum voltage across R5 is 1.2 V at VBAT_MAX = 800 V, leaving some headroom to
the maximum input voltage of 1.25 V of ADC2A.
The maximum resistance of a single resistor that can be used in an automotive circuit design is often limited to a
certain value. Also, the maximum voltage a single resistor can withstand is limited. These reasons are why the
high-side resistor of the divider is split into multiple resistors (R1, R2, R3, and R4). Another reason is that in case
a single resistor has a short-circuit fault, the remaining resistors still limit the current into the ADC2A analog input
pin, V0A, to safe levels.
9.2.2.3 Shunt Temperature Measurement
The shunt temperature in this example is measured using the TMP61, a linear 10-kΩ PTC, in a typical voltage
divider configuration using the analog supply (AVDD) as excitation. The PTC resistance is calculated using 方程
式24, which is derived from 方程式23:
VPTC = VV1A –VAGNDA = AVDD × RPTC / (R6 + RPTC
)
(23)
(24)
RPTC = R6 × VPTC / (AVDD –VPTC
)
The maximum input voltage on V1A is limited to 1.25 V when using gain = 1 for ADC2A with the negative
multiplexer channel of ADC2A internally connected to AGNDA. Therefore, the value of the precision resistor, R6,
must be chosen so that the voltage on V1A stays below 1.25 V for the value range of the PTC across the
temperature range to be measured. The TMP61 has the largest resistance at the most positive temperature,
approximately 18 kΩ at +125°C. Following 方程式 24, that means R6 ≥ 29.5 kΩ. A value of 34 kΩ is chosen
for R6 to allow variation in the AVDD supply voltage up to 3.6 V without exceeding the maximum V1A voltage of
1.25 V.
9.2.3 Application Curves
图 9-2 shows the measurement accuracy of the current measurement (ADC1A, ADC1B) over temperature for a
0-A current through the shunt. 图 9-3 shows the gain error of the current measurement (ADC1A, ADC1B) over
temperature excluding the error of the shunt. The offset and gain error are calibrated at 25°C.
15
10
5
0.3
0.2
0.1
0.0
0
-0.1
-0.2
-0.3
-5
-10
-15
-40
-20
0
20
40
60
80
100 120 140
-40
-20
0
20
40
60
80
100 120 140
Temperature (°C)
Temperature (°C)
图9-3. Gain Error vs Temperature
图9-2. Offset Current Error vs Temperature
(ADC1A, ADC1B)
(ADC1A, ADC1B)
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9.3 Power Supply Recommendations
9.3.1 Power-Supply Options
The ADS131B23 power-supply architecture shown in 图 9-4 allows multiple ways to power the device to support
different application requirements.
AVDD
APWR
AGND
IOVDD
DPWR
DGND
DCAP
AVDD
LDO
IOVDD
LDO
Negative
Charge-
Pump A
DVDD
LDO
VNCPA
VNCPB
Negative
Charge-
Pump B
AVDD
IOVDD
DVDD = 1.8 V
图9-4. Power-Supply Architecture
The AVDD LDO accepts unregulated voltages between 4 V and 16 V on the APWR pin and outputs a regulated
3.3-V AVDD supply that is available at the AVDD pin to power external circuitry. The AVDD supply powers all
analog circuitry in the device. If a regulated 3.3-V supply is available in the application, the AVDD LDO can be
bypassed by shorting the APWR and AVDD pins.
The negative charge pumps in section A and section B provide a negative supply voltage for the various gain
stages of every ADC to allow input voltage measurements below GND.
The IOVDD LDO accepts unregulated voltages between 4 V and 16 V on the DPWR pin and outputs a regulated
3.3-V IOVDD supply that is available at the IOVDD pin to power external circuitry. The IOVDD supply sets the
voltage for the digital I/Os of the device. If a regulated 3.3-V or 5-V supply is available in the application, the
IOVDD LDO can be bypassed by shorting the DPWR and IOVDD pins.
The DVDD LDO creates the 1.8-V supply for the digital core of the device.
The following sections show the three most commonly used external power-supply options, however other
combinations are possible as well.
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9.3.1.1 Single Unregulated External 4-V to 16-V Supply (3.3-V Digital I/O Levels)
A single unregulated 4-V to 16-V supply (as shown in 图 9-5) connected to both the APWR and DPWR pins can
be used to power the device. No external supply is provided at the AVDD and IOVDD pins in this case. The
AVDD LDO creates the internal 3.3-V AVDD supply, and the IOVDD LDO creates the 3.3-V I/O supply.
4 V to 16 V
1 µF
1 µF
40
39
38
37
DCAP
DGND
IOVDD
36
35
34
220 nF
1 µF
≈
图9-5. Single Unregulated External 4-V to 16-V Supply
9.3.1.2 Single Regulated External 3.3-V Supply (3.3-V Digital IO Levels)
A single regulated 3.3-V supply connected to both the APWR and DPWR pins (as shown in 图 9-6) can be used
to power the device. In this case the APWR and AVDD pins must be shorted externally, as well as the DPWR
and IOVDD pins. That way the AVDD and IOVDD LDOs are bypassed. The external 3.3-V supply is directly used
as the AVDD and IOVDD supplies.
3.3 V
1 µF
40
39
38
37
DCAP
DGND
IOVDD
36
35
34
220 nF
1 µF
≈
图9-6. Single Regulated External 3.3-V Supply
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9.3.1.3 Single Regulated External 5-V Supply (5-V Digital I/O Levels)
To allow operation of the digital I/Os with 5-V levels, a single regulated 5-V supply (shown in 图 9-7) connected
to both the APWR and DPWR pins can be used to power the device. No external supply is provided at the AVDD
pin in this case. The AVDD LDO creates the internal 3.3-V AVDD supply. The DPWR and IOVDD pins must be
shorted externally. That way the IOVDD LDO is bypassed. The external 5-V supply is directly used as the
IOVDD supply.
5 V
1 µF
1 µF
40
39
38
37
DCAP
DGND
IOVDD
36
35
34
220 nF
1 µF
≈
图9-7. Single Regulated External 5-V Supply
9.3.2 Power-Supply Sequencing
The power supplies can be sequenced in any order but the analog and digital inputs must never exceed the
respective analog or digital power-supply voltage limits.
9.3.3 Power-Supply Decoupling
Good power-supply decoupling is important to achieve optimum performance.
• APWR and AVDD must each be decoupled with a 1-µF capacitor to AGND.
If APWR and AVDD are shorted together, a single 1-µF decoupling capacitor placed close to the AVDD pin is
sufficient.
• DPWR and IOVDD must each be decoupled with a 1-µF capacitor to DGND.
If DPWR and IOVDD are shorted together, a single 1-µF decoupling capacitor placed close to the IOVDD pin
is sufficient.
• If APWR and DPWR are shorted together, a single 1-µF decoupling capacitor for the two supplies is
sufficient.
• The DVDD LDO output at the DCAP pin must be decoupled with a 220-nF capacitor to DGND.
Place the bypass capacitors as close to the power-supply pins of the device as possible with low-impedance
connections. Using multilayer ceramic chip capacitors (MLCCs) that offer low equivalent series resistance (ESR)
and inductance (ESL) characteristics are recommended for power-supply decoupling purposes. For very
sensitive systems, or for systems in harsh noise environments, avoiding the use of vias for connecting the
capacitors to the device pins can offer superior noise immunity. The use of multiple vias in parallel lowers the
overall inductance and is beneficial for connections to ground planes.
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9.4 Layout
9.4.1 Layout Guidelines
For best performance, dedicate an entire PCB layer to a ground plane and do not route any other signal traces
on this layer. However, depending on restrictions imposed by specific end equipment, a dedicated ground plane
may not be practical. If ground plane separation is necessary, make a direct connection of the planes at the
device. Do not connect individual ground planes at multiple locations because this configuration creates ground
loops.
Route digital traces away from all analog inputs and associated components in order to minimize interference.
Use C0G capacitors on the analog inputs. Use ceramic capacitors (for example, X7R grade) for the power-
supply decoupling capacitors. High-K capacitors (Y5V) are not recommended. Place the required capacitors as
close as possible to the device pins using short, direct traces. For optimum performance, use low-impedance
connections on the ground-side connections of the bypass capacitors.
When applying an external clock, be sure the clock is free of overshoot and glitches. A source-termination
resistor placed at the clock buffer often helps reduce overshoot. Glitches present on the clock input can lead to
noise within the conversion data.
9.4.2 Layout Example
图 9-8 shows an example layout for the ADS131B23, referencing the components of the circuit in 图 9-1. In
general, analog signals are partitioned to the left and digital signals to the right.
Vias connect
to GND plane
+5V0
To high-voltage
resistor divider
V1A
V0A
DCAP
DGND
IOVDD
GPIO0
CLK
CPA
CNA
CSn
SDI
To shunt
SDO
To host
To host
CNB
CPB
SCLK
DRDYn
GPIO1
GPIO2
图9-8. Layout Example
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10 Device and Documentation Support
TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device,
generate code, and develop solutions are listed below.
10.1 Documentation Support
10.1.1 Related Documentation
For related documentation see the following:
• Texas Instruments, TMP61 ±1% 10-kΩLinear Thermistor data sheet
10.2 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
10.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
10.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
10.5 静电放电警告
静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序，可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
10.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
11 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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31-Dec-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
ADS131B23PHPR
ACTIVE
HTQFP
PHP
48
1000 RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
131B23
Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
GENERIC PACKAGE VIEW
PHP 48
7 x 7, 0.5 mm pitch
TQFP - 1.2 mm max height
QUAD FLATPACK
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4226443/A
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