ADS2806Y/250 [TI]
双通道、12 位、32MSPS 模数转换器 (ADC) | PAP | 64 | -40 to 85;
| 型号： | ADS2806Y/250 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 双通道、12 位、32MSPS 模数转换器 (ADC) | PAP | 64 | -40 to 85 转换器 模数转换器 |
| 文件： | 总24页 (文件大小：1508K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ADS2806
ADS2806
SBAS178B – DECEMBER 2000 – REVISED MAY 2002
Dual, 12-Bit, 32MHz Sampling
ANALOG-TO-DIGITAL CONVERTER
FEATURES
APPLICATIONS
● SPURIOUS-FREE DYNAMIC RANGE:
● COMMUNICATIONS IF PROCESSING
● COMMUNICATIONS BASESTATIONS
● TEST EQUIPMENT
73dB at 10MHz fIN
● HIGH SNR: 67dB (2Vp-p), 69dB (3Vp-p)
● INTERNAL OR EXTERNAL REFERENCE
● LOW DLE: ±0.4LSB
● MEDICAL IMAGING
● VIDEO DIGITIZING
● FLEXIBLE INPUT RANGE: 2Vp-p to 3Vp-p
● TQFP-64 POWER PACKAGE
● CCD DIGITIZING
reference can be disabled allowing low drive, external refer-
ences to be used for improved tracking in multichannel systems.
DESCRIPTION
The ADS2806 is a dual, high-speed, high dynamic range,
12-bit pipelined Analog-to-Digital Converter (ADC). This con-
verter includes a high-bandwidth track-and-hold that gives
excellent spurious performance up to and beyond the Nyquist
rate. The differential nature of this track-and-hold and ADC
circuitry minimizes even-order harmonics and gives excel-
lent common-mode noise immunity. The track-and-hold can
also be operated single-ended.
The ADS2806 provides an over-range indicator flag to
indicate an input signal that exceeds the full-scale input
range of the converter. This flag can be used to reduce the
gain of front end gain control circuitry. There is also an
output enable pin to allow for multiplexing and testability on
a PC board.
The ADS2806 employs digital error correction techniques to
provide excellent differential linearity for demanding imag-
ing applications. The ADS2806 is available in a TQFP-64
power package.
The ADS2806 provides for setting the full-scale range of the
converter without any external reference circuitry. The internal
+VS
OEA OVRA
ADS2806
D12A
VIN
INA
12-Bit
Pipelined
A/D
Error
Correction
Logic
•
3-State
Outputs
•
•
T&H
D1A
INA
(Opt.)
INT/EXT
FSSEL
Internal
Reference
Timing
Circuitry
CLK
VIN
D12B
INB
12-Bit
Pipelined
A/D
Error
Correction
Logic
•
3-State
Outputs
•
•
T&H
D1B
INB
(Opt.)
CM
OEB
OVRB
Optional External
Reference
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2000, Texas Instruments Incorporated
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
www.ti.com
ABSOLUTE MAXIMUM RATINGS(1)
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Texas Instru-
ments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
+VS ....................................................................................................... +6V
Analog Input ........................................................... (–0.3V) to (+VS + 0.3V)
Logic Input ............................................................. (–0.3V) to (+VS + 0.3V)
Case Temperature ......................................................................... +100°C
Junction Temperature .................................................................... +150°C
Storage Temperature ..................................................................... +150°C
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.
NOTE: (1) Stresses above those listed under “Absolute Maximum Ratings”
may cause permanent damage to the device. Exposure to absolute maximum
conditions for extended periods may affect device reliability.
PACKAGE/ORDERING INFORMATION
SPECIFIED
PACKAGE
DESIGNATOR(1)
TEMPERATURE
RANGE
PACKAGE
MARKING
ORDERING
NUMBER
TRANSPORT
MEDIA, QUANTITY
PRODUCT
PACKAGE-LEAD
ADS2806Y
TQFP-64
PAP
–40°C to +85°C
ADS2806Y
ADS2806Y/1K5
ADS2806Y/250
Tape and Reel, 1500
Tape and Reel, 250
"
"
"
"
"
NOTE: (1) For the most current specifications and package information, refer to our web site at www.ti.com.
ELECTRICAL CHARACTERISTICS
At TA = full specified temperature range, VS = +5V, differential input range = 2V to 3V for each input, sampling rate = 32MSPS, unless otherwise noted.
ADS2806Y
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
RESOLUTION
12 Tested
Bits
SPECIFIED TEMPERATURE RANGE
Ambient Air
–40
+85
°C
ANALOG INPUT
2V Full-Scale Input Range (Differential)
2V Full-Scale Input Range (Single-Ended)
2Vp-p, INT or EXT Ref
2Vp-p, INT or EXT Ref
2
1.5
3
3.5
V
V
3V Full-Scale Input Range (Differential)
3V Full-Scale Input Range (Single-Ended)
Analog Input Bias Current
3Vp-p, INT or EXT Ref
3Vp-p, INT or EXT Ref
1.75
1
3.25
4
V
V
µA
1
Analog Input Bandwidth
270
MHz
MΩ || pF
Input Impedance
1.25 || 3
CONVERSION CHARACTERISTICS
Sample Rate
10k
32
Samples/s
Data Latency
6
Clock Cycles
DYNAMIC CHARACTERISTICS
Differential Linearity Error (largest code error)
f = 1MHz
f = 10MHz
No Missing Codes
Integral Linearity Error, f = 1MHz
Spurious-Free Dynamic Range(1)
f = 1MHz (–1dB input)
±0.35
±0.4
Tested
±2.5
±1.0
±4.0
LSB
LSB
LSBs
73
73
dBFS(2)
dBFS
f = 10MHz (–1dB input)
2-Tone Intermodulation Distortion(3)
f = 9MHz and 10MHz (–7dB each tone)
67
63
–74.6
dBc
Signal-to-Noise Ratio (SNR)
f = 1MHz (–1dB input)
f = 10MHz (–1dB input)
f = 1MHz (–1dB input)
f = 10MHz (–1dB input)
67
66
69
68
dBFS
dBFS
dBFS
dBFS
3Vp-p
3Vp-p
Signal-to-(Noise + Distortion) (SINAD)(4)
f = 1MHz (–1dBFS input)
f = 10MHz (–1dBFS input)
f = 1MHz (–1dBFS input)
66
65
69
69
dBFS
dBFS
dBFS
dBFS
61
3Vp-p
3Vp-p
f = 10MHz (–1dBFS Input)
ADS2806
SBAS178B
2
www.ti.com
ELECTRICAL CHARACTERISTICS (Cont.)
At TA = full specified temperature range, VS = +5V, differential input range = 2V to 3V for each input, sampling rate = 32MSPS, unless otherwise noted.
ADS2806Y
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
DYNAMIC CHARACTERISTICS (Cont.)
Channel-to-Channel Crosstalk
Output Noise
2Vp-p
Input Grounded
80
0.2
2
dBc
LSBs rms
ns
Aperture Delay Time
Aperture Jitter
Overvoltage Recovery Time
1.2
2
ps rms
ns
DIGITAL INPUTS
Logic Family
Convert Command
+3V/+5V CMOS Compatible
Rising Edge of Convert Clock
Start Conversion
High Level Input Current(5) (VIN = 5V)
Low Level Input Current (VIN = 0V)
High Level Input Voltage
Low Level Input Voltage
Input Capacitance
+50
+10
µA
µA
V
V
pF
+2.4
+1.0
5
DIGITAL OUTPUTS
Logic Family
CMOS
Logic Coding
Straight Offset Binary
Low Output Voltage (IOL = 50µA)
Low Output Voltage, (IOL = 1.6mA)
High Output Voltage, (IOH = 50µA)
High Output Voltage, (IOH = 0.5mA)
Low Output Voltage, (IOL = 50µA)
High Output Voltage, (IOH = 50µA)
3-State Enable Time
VDRV = 5V
VDRV = 5V
VDRV = 5V
VDRV = 5V
VDRV = 3V
VDRV = 3V
OE = L(5)
+0.1
+0.2
V
V
V
V
V
+4.9
+4.8
+0.4
+2.4
V
20
2
5
40
10
ns
ns
pF
3-State Disable Time
Output Capacitance
OE = H(5)
ACCURACY (Internal Reference,
2Vp-p, Unless Otherwise Noted)
Zero Error (Midscale)
at 25°C
±0.5
%FS
Zero Error Drift (Midscale)
Gain Error(6)
16
±1.5
66
±1.0
23
ppm/°C
%FS
ppm/°C
%FS
ppm/°C
dB
at 25°C
at 25°C
Gain Error Drift(6)
Gain Error(7)
Gain Error Drift(7)
Power-Supply Rejection of Gain
REFT Tolerance
2V Full Scale
∆VS = ±5%
70
Deviation From Ideal 3.0V
Deviation From Ideal 3.25V
±10
±20
±65
±65
mV
mV
3V Full Scale
REFB Tolerance
2V Full Scale
3V Full Scale
Deviation From Ideal 2.0V
Deviation From Ideal 1.75V
±10
±20
mV
mV
V
V
Ω
External REFT Voltage Range
External REFB Voltage Range
Reference Input Resistance
REFB + 0.4
1.70
3
2
375
VS – 1.70
REFT – 0.4
POWER-SUPPLY REQUIREMENTS
Supply Voltage: +VS
Supply Current: +IS
Power Dissipation: VDRV = 5V
VDRV = 3V
Operating
Operating
+4.75
+5.0
78
+5.25
475
V
mA
mW
mW
mW
mW
External Reference
External Reference
Internal Reference
Internal Reference
430
400
450
420
VDRV = 5V
VDRV = 3V
Thermal Resistance, θJA
TQFP-64
21.5
°C/W
NOTES: (1) Spurious-Free Dynamic Range refers to the magnitude of the largest harmonic. (2) dBFS means dB relative to Full-Scale. (3) 2-tone intermodulation
distortion is referred to the largest fundamental tone. This number will be 6dB higher if it is referred to the magnitude of the 2-tone fundamental envelope.
(4) Effective number of bits (ENOB) is defined by as (SINAD – 1.76)/6.02. (5) A 50kΩ pull-down resistor is inserted internally on OE pins. (6) Includes internal
reference. (7) Excludes internal reference.
ADS2806
SBAS178B
3
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TIMING DIAGRAM
N + 2
N + 1
N + 4
N + 3
Analog In
N + 7
N + 5
N
N + 6
tL
tH
tD
tCONV
Clock
6 Clock Cycles
N – 4 N – 3
t2
Data Out
N – 6
N – 5
N – 2
N – 1
N
N + 1
Data Invalid
t1
t3
Data Valid
t4
SYMBOL
tCONV
tL
DESCRIPTION
MIN
TYP
MAX
UNITS
Convert Clock Period
Clock Pulse Low
31.25
14.6
14.6
100µs
ns
ns
ns
ns
ns
ns
ns
ns
tCONV/2
tCONV/2
2
tH
Clock Pulse High
tD
Aperture Delay
(1)
t1
Data Hold Time, CL = 0pF
2.7
(1)
t2
New Data Delay Time, CL = 15pF max
Data Valid Falling Edge Delay, CL = 15pF max
Data Valid Rising Edge Delay, CL = 15pF max
8.2
7.5
5.6
12
t3
t4
NOTE: (1) t1 and t2 times are valid for VDRV voltages of +2.7V to +5V.
PIN CONFIGURATION
Top View
TQFP
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
GND
GND
+VS
1
2
3
4
5
6
7
8
9
48 GND
47 GND
46 +VS
45 SEL
44 GND
43 +VS
42 OEA
41 GND
GND
+VS
OEB
GND
VDRVB
OVRB
ADS2806Y
40 VDRVA
39 OVRA
38 A1 (MSB)
37 A2
B12 (LSB) 10
B11 11
B10 12
B9 13
36 A3
B8 14
35 A4
B7 15
34 A5
B6 16
33 A6
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
ADS2806
SBAS178B
4
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PIN DESCRIPTIONS
PIN
I/O DESIGNATOR DESCRIPTION
PIN
I/O
DESIGNATOR DESCRIPTION
1
GND
GND
+VS
Ground
34
35
36
37
38
39
40
41
42
43
44
45
O
O
O
O
O
O
A5
A4
Data Bit 5 (D7), Channel A
2
Ground
Data Bit 4 (D8), Channel A
Data Bit 3 (D9), Channel A
Data Bit 2 (D10), Channel A
Data Bit 1 (D11), Channel A
Over-Range Indicator, Channel A
Logic Driver Supply Voltage, Channel A
Ground
A3
3
+5V Supply
4
GND
+VS
Ground
A2
5
+5V Supply
A1 (MSB)
OVRA
VDRVA
GND
OEA
6
I
OEB
GND
VDRVB
OVRB
B12 (LSB)
B11
Output Enable, Channel B
GND
7
8
Logic Driver Supply Voltage, Channel B
Over-Range Indicator, Channel B
Data Bit 12 (D0), Channel B
Data Bit 11 (D1), Channel B
Data Bit 10 (D2), Channel B
Data Bit 9 (D3), Channel B
Data Bit 8 (D4), Channel B
Data Bit 7 (D5), Channel B
Data Bit 6 (D6), Channel B
Data Bit 5 (D7), Channel B
Data Bit 4 (D8), Channel B
Data Bit 3 (D9), Channel B
Data Bit 2 (D10), Channel B
Data Bit 1 (D11), Channel B
Data Valid, Channel B
Ground
I
I
Output Enable, Channel A
+5V Supply
9
O
O
O
O
O
O
O
O
O
O
O
O
O
O
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
+VS
GND
SEL
Ground
Input Range Select: HIGH = 3V, LOW = 2V
B10
B9
46
47
48
49
50
+VS
GND
GND
GND
INA
+5V Supply
Ground
Ground
B8
B7
Ground
B6
I
Analog Input, Channel A
B5
51
52
53
54
55
56
I
INA
CMA
Complementary Analog Input, Channel A
Common-Mode, Channel A
B4
O
B3
I/O
I/O
REFTA
REFBA
GND
Top Reference/Bypass, Channel A
B2
Bottom Reference/Bypass, Channel A
Ground
B1 (MSB)
DVB
GND
CLK
GND
DVA
I
INT/EXT
Reference Select: HIGH = External,
LOW = Internal 50kΩ Pull-Up Resistor
I
Clock
57
58
59
60
61
62
63
64
+VS
GND
REFBB
REFTB
CMB
+5V Supply
Ground
Ground
O
O
O
O
O
O
O
O
Data Valid, Channel A
Data Bit 12 (D0), Channel A
Data Bit 11 (D1), Channel A
Data Bit 10 (D2), Channel A
Data Bit 9 (D3), Channel A
Data Bit 8 (D4), Channel A
Data Bit 7 (D5), Channel A
Data Bit 6 (D6), Channel A
I/O
I/O
O
I
Bottom Reference/Bypass, Channel B
Top Reference/Bypass, Channel B
Common-Mode, Channel B
Complementary Analog Input, Channel B
Analog Input, Channel B
Ground
A12 (LSB)
A11
A10
INB
A9
I
INB
A8
GND
A7
A6
ADS2806
SBAS178B
5
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TYPICAL CHARACTERISTICS
At TA = full specified temperature range, VS = +5V, differential input range = 2V to 3V for each input, sampling rate = 32MSPS, unless otherwise noted.
SPECTRAL PERFORMANCE
(Differential, 2Vp-p)
SPECTRAL PERFORMANCE
(Differential, 2Vp-p)
0
–20
0
–20
fIN = 1MHz
SFDR = 73.5dBFS
SNR = 67.4dBFS
–40
–40
–60
–60
–80
–80
–100
–120
–100
–120
0
4
8
12
16
0
4
8
12
16
Frequency (MHz)
Frequency (MHz)
SPECTRAL PERFORMANCE
(Differential, 3Vp-p)
SPECTRAL PERFORMANCE
(Differential, 3Vp-p)
0
–20
0
–20
fIN = 10MHz
SFDR = 70.8dBFS
SNR = 67.9dBFS
–40
–40
–60
–60
–80
–80
–100
–120
–100
–120
0
4
8
12
16
0
4
8
12
16
Frequency (MHz)
Frequency (MHz)
DYNAMIC PERFORMANCE vs CLOCK
2-TONE INTERMODULATION DISTORTION
80
78
76
74
72
70
68
66
64
62
60
0
–20
REF = 2V
IN = 3.5MHz
f1 = 9MHz (–7dBFS)
f
f
2 = 10MHz (–7dBFS)
SFDR
SNR
IMD(3) = 74.6dBc
–40
–60
–80
–100
–120
24
26
28
30
32
34
36
0
4
8
12
16
Frequency (MHz)
Frequency (MHz)
ADS2806
SBAS178B
6
www.ti.com
TYPICALCHARACTERISTICS (Cont.)
At TA = full specified temperature range, VS = +5V, differential input range = 2V to 3V for each input, sampling rate = 32MSPS, unless otherwise noted.
DYNAMIC PERFORMANCE vs CLOCK
DYNAMIC PERFORMANCE vs INPUT FREQUENCY
80
78
76
74
72
70
68
66
64
62
60
75
70
65
60
55
50
45
40
REF = 3V
IN = 3.5MHz
SFDR
THD
f
SFDR
SNR
SINAD
SNR
Power = –1dBFS
24
26
28
30
Clock (MHz)
32
34
36
1
10
100
Frequency (MHz)
SWEPT POWER (SFDR)
DYNAMIC PERFORMANCE vs INPUT FREQUENCY
SFDR
100
85
80
75
70
65
60
55
50
45
40
90
80
70
60
50
40
30
20
10
0
THD
SNR
SINAD
Power = –6dBFS
–60
–50
–40
–30
–20
–10
0
1
10
100
Frequency (MHz)
Input Amplitude (dBFS)
INTEGRAL LINEARITY ERROR
(Differential, 2Vp-p)
DIFFERENTIAL LINEARITY ERROR
(Differential, 2Vp-p)
4
3
0.5
0.25
0
fIN = 10MHz
2
1
0
–1
–2
–3
–4
–0.25
–0.5
0
1024
2048
Code
3072
4096
0
1024
2048
Code
3072
4096
ADS2806
SBAS178B
7
www.ti.com
TYPICALCHARACTERISTICS (Cont.)
At TA = full specified temperature range, VS = +5V, differential input range = 2V to 3V for each input, sampling rate = 32MSPS, unless otherwise noted.
DIFFERENTIAL LINEARITY ERROR
(Differential, 3Vp-p)
INTEGRAL LINEARITY ERROR
(Differential, 3Vp-p)
4
3
0.5
0.25
0
fIN = 10MHz
2
1
0
–1
–2
–3
–4
–0.25
–0.5
0
1024
2048
Code
3072
4096
0
1024
2048
Code
3072
4096
OUTPUT NOISE HISTOGRAM (DC Input)
3V Full Scale
CROSSTALK (Channel A)
0
–20
500k
400k
300k
200k
100k
–40
–60
–80
–100
–120
0
4
8
12
16
N-2
N-1
N
N+1
N+2
Code
Frequency (MHz)
DYNAMIC PERFORMANCE vs TEMPERATURE
SFDR
CROSSTALK (Channel B)
0
–20
75
70
65
60
55
50
fIN = 3.5MHz
–40
SNR
–60
–80
–100
–120
f
IN = 10MHz
0
4
8
12
16
–60
–40
–20
0
20
40
60 80 100
Temperature (°C)
Frequency (MHz)
ADS2806
SBAS178B
8
www.ti.com
• The reduced signal swing allows for more headroom in
the interface circuitry and, therefore, a wider selection of
the best suitable driver op amp.
APPLICATION INFORMATION
THEORY OF OPERATION
The ADS2806 integrates two high-speed CMOS ADCs and
an internal reference. The ADCs utilize a pipelined converter
architecture consisting of 11 internal stages. Each stage
feeds its data into the digital error correction logic, ensuring
excellent differential linearity and no missing codes at the
12-bit level. The output data becomes valid after the rising
clock edge (see Timing Diagram). The pipeline architecture
results in a data latency of 6 clock cycles.
• Even-order harmonics are minimized.
• Improves the noise immunity based on the converter’s
common-mode input rejection.
Using the single-ended mode, the signal is applied to one of
the inputs, while the other input is biased with a DC voltage
to the required common-mode level. Both inputs are equal
in terms of their impedance and performance, except that
applying the signal to the complementary input (IN) instead
of the IN input will invert the input signal relative to the
output code. For example, in the case when the input driver
operates in inverting mode, using IN as the signal input will
restore the phase of the signal to its original orientation.
Time-domain applications may benefit from a single-ended
interface configuration and its reduced circuit complexity.
Driving the ADS2806 with a single-ended signal will result in
a reduction of the distortion performance, while maintaining
good Signal-to-Noise Ratio (SNR). Employing dual-supply
amplifiers and AC-coupling will usually yield the best re-
sults, while DC-coupling and/or single-supply amplifiers
impose additional design constraints due to their headroom
requirements, especially when selecting the 3Vp-p input
range. However, single-supply amplifiers have the advan-
tage of inherently limiting their output swing to within the
supply rails. Alternatively, a voltage limiting amplifier, like
the OPA688, may be considered to set fixed-signal limits
and avoid any severe over-range condition for the ADC.
The analog input of the ADS2806 consists of a differential
track-and-hold circuit. The differential topology along with
tightly matched poly-poly capacitors produce a high level of
AC performance at high sampling rates and in some under-
sampling applications.
Both inputs (IN, IN) require external biasing using a com-
mon-mode voltage that is typically at the mid-supply level
(+VS/2).
DRIVING THE ANALOG INPUTS
The analog inputs of the ADS2806 are very high impedance
and should be driven through an R-C network designed to
pass the highest frequency of interest. This prevents high-
frequency noise in the input from affecting SFDR and SNR.
The ADS2806 can be used in a wide variety of applications
and deciding on the best performing analog interface circuit
depends on the type of application. The circuit definition
should include considerations of input frequency spectrum
and amplitude, single-ended or differential drive, and avail-
able power supplies. For example, communication (fre-
quency domain) applications process frequency bands not
including DC. In imaging (time domain) applications, the
input DC component must be maintained into the ADC.
Features of the ADS2806 include full-scale select (SEL),
external reference, and CM output, providing flexibility to
accommodate a wide range of applications. The ADS2806
should be configured to meet application objectives, while
observing the headroom requirements of the driving ampli-
fiers, to yield the best overall performance.
The full-scale input range of the ADS2806 is defined by the
reference voltages. For example, setting the range select
pin to SEL = LOW, and using the internal references
(REFT = +3.0V and REFTB = +2.0V), the full-scale range is
defined as: FSR = 2 • (REFT – REFB) = 2Vp-p.
The trade-off of the differential input configuration versus
the single-ended is its higher complexity. In either case, the
selection of the driver amplifier should be such that the
amplifier’s performance will not degrade the ADC’s perfor-
mance. The ADS2806 operates on a single power supply
that requires a level shift for ground-based bipolar input
signals to comply with its input voltage range requirements.
The ADS2806 input structure allows it to be driven either
single-ended or differentially. Differential operation of the
ADS2806 requires an in-phase input signal and a 180° out-
of-phase part simultaneously applied to the inputs (IN, IN).
The differential operation offers a number of advantages
that, in most applications, will be instrumental in achieving
the best dynamic performance of the ADS2806:
The input of the ADS2806 is of a capacitive nature and the
driving source needs to provide the current to charge or
discharge the input sampling capacitor while the track-and-
hold is in track mode. This effectively results in a dynamic
input impedance that depends on the sampling frequency.
In most applications, it is recommended to add a series
resistor, typically 20Ω to 50Ω, between the drive source and
the converter inputs. This will isolate the capacitive input
from the source, which can be crucial to avoid gain peaking
when using wideband operational amplifiers. Secondly, it
• The signal swing is half of that required for the single-
ended operation and, therefore, is less demanding to
achieve while maintaining good linearity performance
from the signal source.
ADS2806
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will create a 1st-order, low-pass filter in conjunction with the
specified input capacitance of the ADS2806. Its cutoff fre-
quency can be adjusted even further by adding an external
shunt capacitor from each signal input to ground. The
optimum values of this R-C network depend on a variety of
factors that include the ADS2806 sampling rate, the se-
lected op amp, the interface configuration, and the particular
application (time domain versus frequency domain). Gener-
ally, increasing the size of the series resistor and/or capaci-
tor will improve the SNR performance, but depending on the
signal source, large resistor values may be detrimental to
achieving good harmonic distortion. In any case, optimizing
the R-C values for the specific application is encouraged.
see matched impedances. Figure 1 shows the schematic for
the suggested transformer coupled interface circuit. The
component values of the R-C low-pass may be optimized
depending on the desired roll-off frequency. The resistor
across the secondary side (RT) should be calculated using
the equation RT = n2 • RG to match the source impedance
(RG) for good power transfer and VSWR.
The circuit example of Figure 1 shows the voltage feedback
amplifier OPA680 driving the RF transformer, which con-
verts the single-ended signal into a differential. The OPA680
can be employed for either single- or dual-supply operation.
For details on how to optimize its frequency response, refer
to the OPA680 data sheet (SBOS083) on our web site at
www.ti.com. With the 49.9Ω series output resistor, the
amplifier emulates a 50Ω source (RG). Any DC content of
the signal can be easily blocked by a capacitor (0.1µF) to
avoid DC loading of the op amp’s output stage.
Transformer Coupled, Single-Ended to Differential
Configuration
If the application requires a signal conversion from a single-
ended source to drive the ADS2806 differentially, an RF
transformer might be a good solution. The selected trans-
former must have a center tap in order to apply the com-
mon-mode DC voltage necessary to bias the converter
inputs. AC grounding the center tap will generate the differ-
ential signal swing across the secondary winding. Consider
a step-up transformer to take advantage of a signal ampli-
fication without the introduction of another noise source.
Furthermore, the reduced signal swing from the source may
lead to improved distortion performance.
AC-Coupled, Single-Ended to Differential Interface
with Dual-Supply Op Amps
Some applications demand a very high dynamic range and
low levels of intermodulation distortion, but usually allow the
input signal to be AC-coupled into the ADC. Appropriate
driver amplifiers need to be selected to maintain the excellent
distortion performance of the ADS2806. Often, these op
amps deliver the lowest distortion with a small, ground-
centered signal swing that requires dual power supplies.
Because of the AC-coupling, this requirement can be easily
accomplished, and the needed level shifting of the input
signal can be implemented without affecting the driver circuit.
The differential input configuration provides the noticeable
advantage of achieving high SFDR over a wide range of
input frequencies. In this mode, both inputs of the ADS2806
RG
0.1µF
VIN
49.9Ω
24.9Ω
1:n
IN
OPA680
47pF
1/2
R1
RT
24.9Ω
ADS2806Y
CM
+2.5V
IN
R2
47pF
+
0.1µF
10µF
One Channel of Two
FIGURE 1, Converting a Single-Ended Input Signal into a Differential Signal Using an RF-Transformer.
ADS2806
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Figure 2 shows an example of such an interface circuit
specifically designed to maximize the dynamic performance.
The voltage feedback amplifier, OPA642, maintains an
excellent distortion performance for input frequencies of up
to 15MHz. The two amplifiers (A1, A2) are configured as an
inverting and noninverting gain stage to convert the input
signal from single-ended to differential. The nominal gain for
this stage is set to +2V/V. The outputs of the OPA642s are
AC-coupled to the converter’s differential inputs. This will
keep the distortion performance at its best since the signal
range stays within the linear region of the op amp and
sufficient headroom to the supply rails can be maintained.
Four resistors located between the top (REFT) and bottom
(REFB) reference shift the input signal to a common-mode
voltage of approximately +2.5V.
tion front end to the ADS2806. With a minimum gain stability
of +3, the gain resistors have to be modified, as well as
optimizing the series resistor and shunt capacitance at each
of the converter inputs.
AC-Coupled, Single-Ended-to-Differential Interface
for Single-Supply Operation
The previously discussed interface circuit can be modified if
the system only allows for a single-supply operation, e.g.,
VS = +5V. Single-supply operation requires the driver ampli-
fier to be biased as well in order to process a bipolar input
signal. Typically, single-supply amplifiers do not achieve
distortion performance as well as dual-supply op amps. The
driver amplifier’s output swing must exceed the full-scale
input range of the converter. In addition, dual op amps, such
as the current-feedback OPA2681, should be considered
since they provide the closest open-loop gain and phase
matching between the two channels. Shown in Figure 3 is
a single-supply interface circuit for an AC-coupled input
signal. With the ADS2806 set to the 2Vp-p input range, the
The interface circuit of Figure 2 can be modified to extend
the bandwidth to approximately 25MHz, by replacing the
OPA642 with its decompensated version, the OPA643. The
OPA643 provides the necessary slew rate for a low distor-
402Ω
200Ω
1.82kΩ
1.82kΩ
REFT
0.1µF
VIN
16.5Ω
A1
OPA642
IN
100pF
402Ω
1/2
402Ω
ADS2806Y
0.1µF
16.5Ω
A2
IN
OPA642
100pF
REFB
1.82kΩ
1.82kΩ
One Channel of Two
FIGURE 2. AC-Coupled Differential Driver Interface with OPA642.
RF
499Ω
RIN
249Ω
0.1µF
RS
VIN
24.9Ω
1/2
OPA2681
IN
RP
68pF
499Ω
499Ω
VCM = +2.5V
1/2
CM
ADS2806Y
0.1µF
+5V
RS
24.9Ω
1/2
OPA2681
IN
68pF
RF
499Ω
RG
249Ω
RP
499Ω
One Channel of Two
0.1µF
FIGURE 3. AC-Coupled, Differential Interface for Single-Supply Operation.
ADS2806
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each amplifier. This pulls a DC bias current out of the output
stage of the amplifier. It is set to approximately 5mA, see
Figure 3, but will vary depending on the amplifier used.
top and bottom references (REFT, REFB) provide an output
voltage of +3.0V and +2.0V, respectively. The CM output of
the ADS2806 is used to bias the inputs of the driving
amplifiers. Using the OPA2681 on a single +5V supply, its
ideal common-mode point is +2.5V, which coincides with
the recommended common-mode input level for the
ADS2806, thus eliminating the need for coupling capacitors
between the amplifiers and the converter.
Single-Ended, AC-Coupled, Dual-Supply Interface
The circuit provided in Figure 4 shows typical connections
for using the ADS2806 in a single-ended input configura-
tion. The bias requirements for AC-coupling are provided by
a single resistor to the CM output lead. The single-ended
mode of operation should be considered for ease of inter-
face complexity and applications where the dynamic perfor-
mance can be compromised. The series resistor RS, along
with the shunt capacitance, provide the means to adjust the
bandwidth and optimize the performance towards good
signal-to-noise ratio. In addition, the amplifier configuration
can be easily modified for an anti-aliasing filter based on a
2nd-order Sallen-Key or Multiple-Feedback topology.
The addition of a small series resistor (RS) between the
output of the op amps and the input of the ADS2806 will be
beneficial in almost all interface configurations. It will de-
couple the op amp’s output from the capacitive load and
avoid gain peaking that can result in increased noise. For
best spurious and distortion performance, the resistor value
should be kept below 100Ω. Furthermore, the series resis-
tor, in combination with the shunt capacitor, establishes a
passive low-pass filter limiting the bandwidth for the wideband
noise, thus improving the SNR. The spurious-free dynamic
range of this single-supply front end is limited by the 2nd-
harmonic distortion. An improvement of several dB may be
realized by adding a pull-down resistor (RP) at the output of
The interface example, shown in Figure 4, operates with the
full-scale range of the ADS2806 set to 2Vp-p, leaving
sufficient headroom for the output of the OPA642 to drive
the converter and maintain low signal distortion.
+5V
RS
16.5Ω
0.1µF
VIN
IN
OPA642
68pF
1/2
ADS2806Y
–5V
RF
402Ω
CM
1.82kΩ
IN
0.1µF
RG
402Ω
One Channel of Two
FIGURE 4. AC-Coupling the Dual-Supply Amplifier OPA642 to the ADS2806 for a 2Vp-p Full-Scale Input Range.
ADS2806
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DC-Coupled, Differential Driver with Level Shift
Several applications will require that the bandwidth of the
signal path include DC, in which case, the signal has to be
DC-coupled to the ADC. An op amp based interface circuit
can be configured to scale and level shift the input signal to
be compatible with the selected input range of the ADC. The
circuit shown in Figure 5 employs a dual op amp, OPA2681,
to drive the input of the ADS2806 differentially. The single-
supply, general-purpose op amp OPA234 is added to buffer
the common-mode voltage of +2.5V, available at the CM pin,
and apply it to the input of the driver amplifier. This sets the
correct DC voltage to bias the inputs of the ADS2806. It
should be noted that any DC voltage differences between the
IN and IN inputs of the ADS2806 will result in an offset error.
can be either hardwired to ground or left unconnected, which
will default the converter to a 2Vp-p full-scale input range
(FSR). While set for the 2Vp-p range, the top and bottom
reference voltages will be REFT = +3.0V and REFB = +2.0V.
Switching to the 3Vp-p range changes those voltages to
REFT = +3.25V and REFB = +1.75V. The reference buffers
can be utilized to supply up to 1mA/channel (2mA total, sink
and source) to external circuitry. To ensure proper operation
with any reference configuration, it is necessary to provide
solid bypassing at all reference pins in order to keep the clock
feedthrough to a minimum, as shown in Figure 6. Good
performance requires using 0.1µF low inductance capacitors.
All bypassing capacitors should be located as close to their
respective pins as possible.
Using the OPA2681, this circuit can be operated either with
a single or a dual ±5V supply.
REFERENCE OPERATION
1/2
The internal reference consists of a bandgap voltage refer-
ence, the drivers for the top and bottom reference, and the
resistive reference ladder. References are internally con-
nected, e.g.: REFTA is connected to REFTB, and REFBA is
connected to REFBB. The bandgap reference circuit includes
logic functions that allow setting the analog input swing of the
ADS2806 to a differential full-scale range of either 2Vp-p or
3Vp-p by simply tying the SEL pin to a LOW or HIGH
potential, respectively. While operating the ADS2806 in the
external reference mode, the buffer amplifiers for REFT and
REFB are disabled. The ADS2806 has an internal 50kΩ pull-
down resistor at the range select pin (SEL). Therefore, this pin
ADS2806
REFT
CM
REFB
+
+
+
10µF
0.1µF
10µF
0.1µF
10µF
0.1µF
FIGURE 6. Recommended Bypassing for the Reference Pins.
499Ω
249Ω
24.9Ω
VIN
1/2
IN
OPA2681
22pF
499Ω
499Ω
249Ω
1/2
ADS2806Y
IN
249Ω
24.9Ω
CM
1/2
OPA2681
22pF
499Ω
24.9Ω
OPA234
249Ω
0.1µF
0.1µF
0.1µF
1kΩ
One Channel of Two
FIGURE 5. DC-Coupled Input Driver with Level Shifting.
ADS2806
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The input track-and-hold amplifier is differential. A positive
1Vp-p on the IN and its compliment, a negative 1Vp-p, on
the IN (see Figure 3) results in 2Vp-p on the output of the
track-and-hold. Likewise, 2Vp-p on the IN and 0Vp-p on the
IN (see Figure 4) results in 2Vp-p on the output of the track-
and-hold. Therefore, the reference voltages, REFT and
REFB, are the same for both differential and single-ended
inputs, as shown in Table I.
USING EXTERNAL REFERENCES
For even more design flexibility, the internal reference can
be disabled and an external reference voltage used. Driving
both channels with an external reference offers the best
performance, as it allows the channels to maintain balance.
The utilization of an external reference may be considered
for applications requiring higher accuracy, improved tem-
perature performance, or a wide adjustment range of the
converter’s full-scale range. In multichannel applications,
the use of a common external reference has the benefit of
obtaining better matching and drift of the full-scale range
between converters. Figure 7 gives an example of an
external reference circuit using a single-supply, low-power,
dual op amp (OPA2234).
INPUT
REFERENCE IN (Pin-50, 63) IN (Pin-51, 62) REFT REFB
2Vp-p Differential
Internal
2V to 3V
3V to 2V
+3V
+2V
1Vp-p Times 2 Inputs
or External
2Vp-p Single-Ended
2Vp-p Times 1 Input
Internal
or External
1.5V to 3.5V
2.5VDC
+3V
+2V
3Vp-p Differential
Internal
1.75V to 3.35V 3.25V to 1.75V +3.25V +1.75V
The external references can vary as long as the value of the
external top reference (REFT) stays within the range of
VS – 1.70V and REFB + 0.4V, and the external bottom
reference (REFB) stays within 1.70V and REFT – 0.4V.
Note that the function of the range selector pin (SEL) is
disabled while the converter operates in external reference
mode. Setting the ADS2806 for external reference mode
requires the INT/EXT pin (pin 18) to be HIGH.
1.5Vp-p Times 2 Inputs
or External
3Vp-p Single-Ended
3Vp-p Times 1 Input
Internal
or External
1V to 4V
2.5VDC
+3.25V +1.75V
TABLE I. Reference Voltages for Input Signal Ranges.
The external references may be changed for different tasks.
The ADS2806 will follow the external references with a
latency of 8 to 10 clock cycles. If it is desired to use INT/EXT
and SEL to change the configuration of a circuit for different
tasks, a large amount of time must be allowed. This time
could be hundreds of microseconds. Refer to the Diagram
on the front page. Note that there is no disconnect for
external references. If it is desired to switch between inter-
nal and external references, disconnect switches must be
added between the external references and the ADS2806.
The logic level applied to the INT/EXT pin of the ADS2806
determines if the converter operates with either the built-in
reference or external reference voltages. Due to this func-
tion pin having an internal 50kΩ pull-up resistor, the default
configuration is external reference mode. Grounding this pin
will activate the internal reference option.
+5V
+5V
< 3.30V
OPA2234
Top Reference
A1
4.7kΩ
R3
R4
R1
+
REF1004
+2.5V
10µF
> 1.70V
OPA2234
Bottom Reference
0.1µF
R2
A2
One Channel of Two
FIGURE 7. Example for an External Reference Driver Using the Dual, Single-Supply Op Amp, OPA2234.
ADS2806
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DIGITAL INPUTS AND OUTPUTS
SINGLE-ENDED INPUT
IN = CM, Pins 52, 61)
STRAIGHT OFFSET BINARY
(SOB)
(
Clock Input Requirements
+FS–1LSB (IN = CMV + FSR/2)
1111 1111 1111
1100 0000 0000
1000 0000 0000
0100 0000 0000
0000 0000 0000
Both channels of the ADS2806 are controlled by the same
clock on the rising edge. Utilizing a single clock reduces
timing uncertainty in the sampling of the two channels.
Clock jitter is critical to the SNR performance of high-speed,
high-resolution ADCs. Clock jitter leads to aperture jitter (tA),
which adds noise to the signal being converted. The
ADS2806 samples the input signal on the rising edge of the
CLK input. Therefore, this edge should have the lowest
possible jitter. The jitter noise contribution to total SNR is
given by the following equation. If this value is near your
system requirements, input clock jitter must be reduced.
+1/2 FS
Bipolar Zero (IN = VCM
)
–1/2 FS
–FS (IN = CMV – FSR/2)
TABLE II. Coding Table for Single-Ended Input Configuration
with IN Tied to the Common-Mode Voltage.
STRAIGHT OFFSET BINARY
DIFFERENTIAL INPUT
(SOB)
+FS–1LSB (IN = +3V, IN = +2V)
1111 1111 1111
1100 0000 0000
1000 0000 0000
0100 0000 0000
0000 0000 0000
+1/2 FS
1
Jitter SNR = 20log
rms signal to rms noise
Bipolar Zero (IN = IN = VCM
)
2πƒIN tA
–1/2 FS
where: ƒIN is input signal frequency
–FS (IN = +2V, IN = +3V)
tA is rms clock jitter
TABLE III. Coding Table for Differential Input Configuration.
Particularly in undersampling applications, special consider-
ation should be given to clock jitter. The clock input should be
treated as an analog input in order to achieve the highest
level of performance. Any overshoot or undershoot of the
clock signal may cause degradation of the performance.
When digitizing at high sampling rates, the clock should have
50% duty cycle (tH = tL), along with fast rise and fall times of
2ns or less. The clock input of the ADS2806 can be driven
with either 3V or 5V logic levels. Using low-voltage logic (3V)
may lead to improved AC performance of the converter.
Data output is in the form of two parallel words. It is
recommended that the capacitive loading on the data lines
be as low as possible (< 15pF). Higher capacitive loading
will cause larger dynamic currents as the digital outputs are
changing. Those high current surges can feed back to the
analog portion of the ADS2806 and affect the performance.
If necessary, external buffers or latches close to the
converter’s output pins may be used to minimize the capaci-
tive loading. They also provide the added benefit of isolating
the ADS2806 from high-frequency digital noise on the bus
coupling back into the converter.
Over Range Indicator (OVR)
If the analog input voltage exceeds the set full-scale range,
an over range condition exists. The “OVR” pin of the ADS2806
can be used to monitor any such out-of-range condition. This
“OVR” output is updated along with the data output corre-
sponding to the particular sampled analog input voltage.
Therefore, the OVR data is subject to the same pipeline
delay as the digital data. The OVR output is LOW when the
input voltage is within the defined input range. It will go HIGH
if the applied signal exceeds the full-scale range.
Digital Output Driver Supply (VDRV)
Each channel of the ADS2806 has a separate dedicated
supply pin (8, 40) for the output logic drivers, VDRV, which
are not internally connected to the other supply pins. Setting
the voltage at VDRV to +5V or +3V, the ADS2806 produces
corresponding logic levels and can directly interface to the
selected logic family. The output stages are designed to
supply sufficient current to drive a variety of logic families.
However, it is recommended to use the ADS2806 with +3V
logic supply. This will lower the power dissipation in the
output stages due to the lower output swing and reduce
current glitches on the supply line that may affect the AC
performance of the converter. In some applications, it might
be advantageous to decouple the VDRV pin with additional
capacitors or a pi-filter.
Data Outputs
The digital outputs of the ADS2806 can be set to a high-
impedance state by driving OE (pins 6 and 42) with a logic
HIGH. Normal operation is achieved with pins 6 and 42
LOW due to internal pull-down resistors. This function is
provided for testability purposes and is not meant to drive
digital buses directly, or be dynamically changed during the
conversion process. The output data format of the ADS2806
is in positive Straight Offset Binary code, as shown in
Tables II and III. This format can easily be converted into the
Binary Two’s Complement code by inverting the MSB.
OUTPUT ENABLE (OE
)
The digital outputs of the ADS2806 can be set to high
impedance (tri-state) by driving OEA and OEB (pins 6, 42)
with a logic HIGH. Normal operation is achieved with the
same pins pulled LOW.
ADS2806
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GROUNDING AND DECOUPLING
it is important to keep the analog signal traces separated
from any digital lines to prevent noise coupling onto the
analog signal path. Due to its high sampling rate, the
ADS2806 generates high-frequency current transients and
noise (clock feedthrough) that are fed back into the supply
and reference lines. This requires that all supply and refer-
ence pins are sufficiently bypassed. Figure 8 shows the
recommended decoupling scheme for the ADS2806. In
most cases, 0.1µF ceramic chip capacitors at each pin are
adequate to keep the impedance low over a wide frequency
range. Their effectiveness largely depends on the proximity
to the individual supply pin. Therefore, they should be
located as close to the supply pins as possible. If system
supplies are not a low enough impedance, adding a small
tantalum capacitor will yield the best results.
Proper grounding, bypassing, short trace lengths, and the
use of power and ground planes are particularly important
for high-frequency designs. Multilayer PC boards are rec-
ommended for best performance since they offer distinct
advantages, such as minimizing ground impedance, sepa-
ration of signal layers by ground layers, etc. The ADS2806
should be treated as an analog component. Whenever
possible, the supply pins should be powered by the analog
supply. This will ensure the most consistent results, since
digital supply lines often carry high levels of noise that
otherwise would be coupled into the converter and degrade
the achievable performance. The ground pins should di-
rectly connect to an analog ground plane that covers the PC
board area under the converter. While designing the layout
ADS2806
+VS
57
+VS
3 (46)
+VS
5 (43)
GND
55, 58
GND
1, 2, 64
(47, 48, 49)
GND
4 (44)
GND
7 (41)
VDRV
8 (40)
GND
23, 25
0.1µF
0.1µF
0.1µF
0.1µF
+5V
+3V/+5V
Numbers in Parenthesis Indicate Pins for Channel A
FIGURE 8. Recommended Bypassing for the Supply Pins.
ADS2806
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
ADS2806Y/250
ACTIVE
HTQFP
PAP
64
250
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
ADS2806Y
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Sep-2015
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
ADS2806Y/250
HTQFP
PAP
64
250
180.0
24.4
13.0
13.0
1.5
16.0
24.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Sep-2015
*All dimensions are nominal
Device
Package Type Package Drawing Pins
HTQFP PAP 64
SPQ
Length (mm) Width (mm) Height (mm)
213.0 191.0 55.0
ADS2806Y/250
250
Pack Materials-Page 2
GENERIC PACKAGE VIEW
PAP 64
10 x 10, 0.5 mm pitch
HTQFP - 1.2 mm max height
QUAD FLATPACK
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4226442/A
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PACKAGE OUTLINE
TM
PAP0064F
PowerPAD TQFP - 1.2 mm max height
PLASTIC QUAD FLATPACK
10.2
9.8
B
NOTE 3
64
49
PIN 1 ID
1
48
10.2
9.8
12.2
TYP
11.8
NOTE 3
16
33
17
32
A
0.27
64X
60X 0.5
0.17
0.08
C A B
4X 7.5
C
SEATING PLANE
1.2 MAX
(0.127)
TYP
SEE DETAIL A
17
32
0.25
GAGE PLANE
(1)
8X (R0.091)
NOTE 4
33
16
0.15
0.05
0.08 C
0 -7
0.75
0.45
6.5
5.3
DETAIL A
65
A
17
TYPICAL
20X (R0.137)
NOTE 4
1
48
49
64
4226412/A 11/2020
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs.
4. Strap features may not be present.
5. Reference JEDEC registration MS-026.
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EXAMPLE BOARD LAYOUT
TM
PAP0064F
PowerPAD TQFP - 1.2 mm max height
PLASTIC QUAD FLATPACK
(8)
NOTE 8
(6.5)
SYMM
SOLDER MASK
49
64
DEFINED PAD
64X (1.5)
(R0.05)
TYP
1
48
64X (0.3)
65
(11.4)
SYMM
(1.1 TYP)
60X (0.5)
33
16
(
0.2) TYP
VIA
METAL COVERED
32
17
SEE DETAILS
BY SOLDER MASK
(1.1 TYP)
(11.4)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:6X
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4226412/A 11/2020
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. This package is designed to be soldered to a thermal pad on the board. See technical brief, Powerpad thermally enhanced package,
Texas Instruments Literature No. SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
9. Vias are optional depending on application, refer to device data sheet. It is recommended that vias under paste be filled,
plugged or tented.
10. Size of metal pad may vary due to creepage requirement.
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EXAMPLE STENCIL DESIGN
TM
PAP0064F
PowerPAD TQFP - 1.2 mm max height
PLASTIC QUAD FLATPACK
(6.5)
BASED ON
0.125 THICK STENCIL
SYMM
SEE TABLE FOR
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES
64
49
64X (1.5)
1
48
64X (0.3)
(R0.05) TYP
SYMM
65
(11.4)
60X (0.5)
33
16
METAL COVERED
BY SOLDER MASK
17
32
(11.4)
SOLDER PASTE EXAMPLE
EXPOSED PAD
100% PRINTED SOLDER COVERAGE BY AREA
SCALE:6X
STENCIL
THICKNESS
SOLDER STENCIL
OPENING
0.1
7.27 X 7.27
6.5 X 6.5 (SHOWN)
5.93 X 5.93
0.125
0.15
0.175
5.49 X 5.49
4226412/A 11/2020
NOTES: (continued)
11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
12. Board assembly site may have different recommendations for stencil design.
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Copyright © 2020, Texas Instruments Incorporated
相关型号：
ADS2807Y/1K5G4
Dual-Channel, 12-bit, 50 MSPS, Analog-to-Digital Converter (ADC) 64-HTQFP -40 to 85
TI
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