ADS4122_16 [TI]
Ultra Low-Power ADC;
| 型号： | ADS4122_16 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Ultra Low-Power ADC |
| 文件： | 总81页 (文件大小：2771K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ADS4122, ADS4125
ADS4142, ADS4145
www.ti.com
SBAS520A –FEBRUARY 2011–REVISED MARCH 2011
14-/12-Bit, 65/125MSPS, Ultralow-Power ADC
Check for Samples: ADS4122, ADS4125, ADS4142, ADS4145
1
FEATURES
DESCRIPTION
The ADS412x/4x are lower sampling speed variants
23
•
Ultralow Power with 1.8V Single Supply:
of the ADS41xx family of analog-to-digital converters
(ADCs). These devices use innovative design
techniques to achieve high dynamic performance,
while consuming extremely low power at 1.8V supply.
The devices are well-suited for multi-carrier, wide
bandwidth communications applications.
–
–
103mW Total Power at 65MSPS
153mW Total Power at 125MSPS
•
High Dynamic Performance:
–
–
SNR: 72.2dBFS at 170MHz
SFDR: 81dBc at 170MHz
The ADS412x/4x have fine gain options that can be
used to improve SFDR performance at lower
full-scale input ranges, especially at high input
frequencies. They include a dc offset correction loop
that can be used to cancel the ADC offset. At lower
sampling rates, the ADC automatically operates at
scaled down power with no loss in performance.
•
•
Dynamic Power Scaling with Sample Rate
Output Interface:
–
Double Data Rate (DDR) LVDS with
Programmable Swing and Strength
–
–
–
–
Standard Swing: 350mV
Low Swing: 200mV
The ADS412x/4x are available in a compact QFN-48
pacakge and are specified over the industrial
temperature range (–40°C to +85°C).
Default Strength: 100Ω Termination
2x Strength: 50Ω Termination
–
1.8V Parallel CMOS Interface Also
Supported
•
Programmable Gain up to 6dB for SNR/SFDR
Trade-Off
•
•
DC Offset Correction
Supports Low Input Clock Amplitude Down To
200mVPP
•
Package: QFN-48 (7mm × 7mm)
ADS412x/ADS414x Family Comparison
WITH ANALOG INPUT BUFFERS
FAMILY
65MSPS
125MSPS
160MSPS
250MSPS
200MSPS
250MSPS
ADS412x
12-Bit Family
ADS4122
ADS4125
ADS4126
ADS4129
—
ADS41B29
ADS414x
14-Bit Family
ADS4142
ADS4145
ADS4146
ADS4149
—
ADS41B49
9-Bit
—
—
—
—
—
—
—
—
—
ADS58B19
11-Bit
ADS58B18
—
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
3
PowerPAD is a trademark of Texas Instruments Incorporated.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2011, Texas Instruments Incorporated
ADS4122, ADS4125
ADS4142, ADS4145
SBAS520A –FEBRUARY 2011–REVISED MARCH 2011
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION(1)
SPECIFIED
PACKAGE-
LEAD
PACKAGE
DESIGNATOR
TEMPERATURE
RANGE
LEAD/BALL PACKAGE
ORDERING
NUMBER
TRANSPORT
MEDIA
PRODUCT
ECO PLAN(2)
FINISH
MARKING
ADS4122IRGZR
ADS4122IRGZT
ADS4125IRGZR
ADS4125IRGZT
ADS4142IRGZR
ADS4142IRGZT
ADS4145IRGZR
ADS4145IRGZT
Tape and reel
Tape and reel
Tape and reel
Tape and reel
Tape and reel
Tape and reel
Tape and reel
Tape and reel
GREEN (RoHS,
no Sb/Br)
ADS4122
QFN-48
QFN-48
QFN-48
QFN-48
RGZ
RGZ
RGZ
RGZ
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
Cu/NiPdAu
AZ4122
GREEN (RoHS,
no Sb/Br)
ADS4125
ADS4142
ADS4145
Cu/NiPdAu
Cu/NiPdAu
Cu/NiPdAu
AZ4125
AZ4142
AZ4145
GREEN (RoHS,
no Sb/Br)
GREEN (RoHS,
no Sb/Br)
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the
device product folder at www.ti.com.
(2) Eco Plan is the planned eco-friendly classification. Green (RoHS, no Sb/Br): TI defines Green to mean Pb-Free (RoHS compatible) and
free of Bromine- (Br) and Antimony- (Sb) based flame retardants. Refer to the Quality and Lead-Free (Pb-Free) Data web site for more
information.
The ADS412x/4x family is pin-compatible to the previous generation ADS6149 family; this architecture enables
easy migration. However, there are some important differences between the generations, summarized in Table 1.
Table 1. MIGRATING FROM THE ADS6149 FAMILY
ADS6149 FAMILY
ADS4145 FAMILY
PINS
Pin 21 is NC (not connected)
Pin 23 is MODE
Pin 21 is NC (not connected)
Pin 23 is RESERVED in the ADS4145 family. It is reserved as a digital control pin for an (as yet) undefined function in the
next-generation ADC series.
SUPPLY
AVDD is 3.3V
AVDD is 1.8V
No change
DRVDD is 1.8V
INPUT COMMON-MODE VOLTAGE
VCM is 1.5V
VCM is 0.95V
SERIAL INTERFACE
Protocol: 8-bit register address and 8-bit register data
No change in protocol
New serial register map
EXTERNAL REFERENCE MODE
Supported
Not supported
ADS61B49 FAMILY
PINS
ADS41B29/B49/ADS58B18 FAMILY
Pin 21 is NC (not connected)
Pin 21 is 3.3V AVDD_BUF (supply for the analog input buffers)
Pin 23 is a digital control pin for the RESERVED function.
Pin 23 functions as SNR Boost enable (B18 only).
Pin 23 is MODE
SUPPLY
AVDD is 3.3V
AVDD is 1.8V, AVDD_BUF is 3.3V
No change
DRVDD is 1.8V
INPUT COMMON-MODE VOLTAGE
VCM is 1.5V
VCM is 1.7V
SERIAL INTERFACE
No change in protocol
New serial register map
Protocol: 8-bit register address and 8-bit register data
EXTERNAL REFERENCE MODE
Supported
Not supported
2
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ADS4122, ADS4125
ADS4142, ADS4145
www.ti.com
SBAS520A –FEBRUARY 2011–REVISED MARCH 2011
ABSOLUTE MAXIMUM RATINGS(1)
Over operating free-air temperature range, unless otherwise noted.
VALUE
UNIT
V
Supply voltage range, AVDD
–0.3 to 2.1
Supply voltage range, DRVDD
–0.3 to 2.1
V
Voltage between AGND and DRGND
Voltage between AVDD to DRVDD (when AVDD leads DRVDD)
Voltage between DRVDD to AVDD (when DRVDD leads AVDD)
INP, INM
–0.3 to 0.3
V
0 to 2.1
V
0 to 2.1
V
–0.3 to minimum (1.9, AVDD + 0.3)
V
Voltage applied to input pins
CLKP, CLKM(2), DFS, OE
–0.3 to AVDD + 0.3
–0.3 to 3.9
–40 to +85
+125
V
RESET, SCLK, SDATA, SEN
V
Operating free-air temperature range, TA
Operating junction temperature range, TJ
Storage temperature range, TSTG
°C
°C
°C
kV
–65 to +150
2
ESD, human body model (HBM)
(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not implied.
(2) When AVDD is turned off, it is recommended to switch off the input clock (or ensure the voltage on CLKP, CLKM is less than |0.3V|.
This prevents the ESD protection diodes at the clock input pins from turning on.
THERMAL INFORMATION
ADS4122/25/42/45
THERMAL METRIC(1)
RGZ
48 PINS
29
UNITS
θJA
Junction-to-ambient thermal resistance
θJCtop
θJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
n/a
10
°C/W
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.3
ψJB
9
θJCbot
1.1
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
Copyright © 2011, Texas Instruments Incorporated
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ADS4122, ADS4125
ADS4142, ADS4145
SBAS520A –FEBRUARY 2011–REVISED MARCH 2011
www.ti.com
RECOMMENDED OPERATING CONDITIONS
Over operating free-air temperature range, unless otherwise noted.
ADS4122/5, ADS4142/5
MIN
TYP
MAX
UNIT
SUPPLIES
AVDD
Analog supply voltage
Digital supply voltage
1.7
1.7
1.8
1.8
1.9
1.9
V
V
DRVDD
ANALOG INPUTS
Differential input voltage range(1)
2
VPP
V
Input common-mode voltage
V
CM ± 0.05
Maximum analog input frequency with 2VPP input amplitude(2)
Maximum analog input frequency with 1VPP input amplitude(2)
CLOCK INPUT
400
MHz
MHz
800
Input clock sample rate
ADS4122/ADS4142, low-speed mode enabled by default
ADS4125/ADS4145, low-speed mode enabled
ADS4125/ADS4145, low-speed mode disabled
20
20
65
80
MSPS
MSPS
MSPS
>80
125
Input clock amplitude differential (VCLKP – VCLKM
Sine wave, ac-coupled
)
0.2
1.5
1.6
0.7
1.8
VPP
VPP
VPP
V
LVPECL, ac-coupled
LVDS, ac-coupled
LVCMOS, single-ended, ac-coupled
Input clock duty cycle
Low-speed enabled
Low-speed disabled
40
35
50
50
60
65
%
%
DIGITAL OUTPUTS
CLOAD
RLOAD
TA
Maximum external load capacitance from each output pin to DRGND
5
pF
Ω
Differential load resistance between the LVDS output pairs (LVDS
mode)
100
Operating free-air temperature
–40
+85
°C
HIGH PERFORMANCE MODES(3)(4)(5)
Set the MODE 1 register bits to get best performance across sample
clock and input signal frequencies.
Mode 1
Register address = 03h, register data = 03h
Set the MODE 2 register bit to get best performance at high input
signal frequencies greater than 230MHz.
Mode 2
Register address = 4Ah, register data = 01h
(1) With 0dB gain. See the Gain section in the Application Information for relation between input voltage range and gain.
(2) See the Theory of Operation section in the Application Information.
(3) It is recommended to use these modes to obtain best performance. These modes can be set using the serial interface only.
(4) See the Serial Interface section for details on register programming.
(5) Note that these modes cannot be set when the serial interface is not used (when the RESET pin is tied high); see the Device
Configuration section.
4
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Product Folder Link(s): ADS4122 ADS4125 ADS4142 ADS4145
ADS4122, ADS4125
ADS4142, ADS4145
www.ti.com
SBAS520A –FEBRUARY 2011–REVISED MARCH 2011
ELECTRICAL CHARACTERISTICS: ADS4122/ADS4125
Typical values are at +25°C, AVDD = 1.8V, DRVDD = 1.8V, 50% clock duty cycle, –1dBFS differential analog input, 0dB gain,
and DDR LVDS interface, unless otherwise noted. Minimum and maximum values are across the full temperature range:
TMIN = –40°C to TMAX = +85°C, AVDD = 1.8V, and DRVDD = 1.8V.
ADS4122 (65MSPS)
ADS4125 (125MSPS)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
UNIT
Bits
Resolution
12
12
fIN = 10MHz
fIN = 70MHz
fIN = 100MHz
fIN = 170MHz
fIN = 300MHz
fIN = 10MHz
fIN = 70MHz
fIN = 100MHz
fIN = 170MHz
fIN = 300MHz
fIN = 10MHz
fIN = 70MHz
fIN = 100MHz
fIN = 170MHz
fIN = 300MHz
fIN = 10MHz
fIN = 70MHz
fIN = 100MHz
fIN = 170MHz
fIN = 300MHz
fIN = 10MHz
fIN = 70MHz
fIN = 100MHz
fIN = 170MHz
fIN = 300MHz
fIN = 10MHz
fIN = 70MHz
fIN = 100MHz
fIN = 170MHz
fIN = 300MHz
fIN = 10MHz
fIN = 70MHz
fIN = 100MHz
fIN = 170MHz
fIN = 300MHz
71.1
70.9
70.7
70.2
68.8
70.8
70.8
70.6
70.1
68
71
70.8
70.6
70.1
69.6
70.7
70.7
70.3
69.8
69
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBc
SNR (signal-to-noise ratio), LVDS
67
66
68
67
SINAD (signal-to-noise and distortion ratio),
LVDS
86.5
86
86
86
dBc
Spurious-free dynamic range
Total harmonic distortion
Second-harmonic distortion
SFDR
THD
HD2
HD3
87
82
dBc
70
85
71
81
dBc
72.5
82.5
84
77
dBc
82
dBc
83.5
80.5
79.5
75.5
87
dBc
84
dBc
69.5
81
69.5
dBc
72
dBc
87
dBc
88
86
dBc
88
82
dBc
70
86
71
83
dBc
72.5
86.5
86
77
dBc
86
dBc
88
dBc
Third-harmonic distortion
87
85
dBc
70
85
71
81
dBc
85
82
dBc
96
95
dBc
96
95
dBc
Worst spur
(other than second and third harmonics)
94
95
dBc
76.5
92
76.5
91
dBc
88
88
dBc
Two-tone intermodulation
distortion
f1 = 100MHz, f2 = 105MHz,
each tone at –7dBFS
IMD
90
1
87.5
1
dBFS
Recovery to within 1% (of final
value) for 6dB overload with
sine-wave input
Clock
cycles
Input overload recovery
For 100mVPP signal on AVDD
supply, up to 10MHz
AC power-supply rejection ratio
PSRR
> 30
> 30
dB
Effective number of bits
Differential nonlinearity
Integrated nonlinearity
ENOB
DNL
INL
fIN = 170MHz
fIN = 170MHz
fIN = 170MHz
11.2
±0.2
±0.3
11.2
±0.2
LSBs
LSBs
LSBs
–0.85
1.5
3.5
–0.85
1.5
3.5
±0.35
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ADS4122, ADS4125
ADS4142, ADS4145
SBAS520A –FEBRUARY 2011–REVISED MARCH 2011
www.ti.com
ELECTRICAL CHARACTERISTICS: ADS4142/ADS4145
Typical values are at +25°C, AVDD = 1.8V, DRVDD = 1.8V, 50% clock duty cycle, –1dBFS differential analog input, 0dB gain,
and DDR LVDS interface, unless otherwise noted. Minimum and maximum values are across the full temperature range:
TMIN = –40°C to TMAX = +85°C, AVDD = 1.8V, and DRVDD = 1.8V.
ADS4142 (65MSPS)
ADS4145 (125MSPS)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
UNIT
Bits
Resolution
14
14
fIN = 10MHz
fIN = 70MHz
fIN = 100MHz
fIN = 170MHz
fIN = 300MHz
fIN = 10MHz
fIN = 70MHz
fIN = 100MHz
fIN = 170MHz
fIN = 300MHz
fIN = 10MHz
fIN = 70MHz
fIN = 100MHz
fIN = 170MHz
fIN = 300MHz
fIN = 10MHz
fIN = 70MHz
fIN = 100MHz
fIN = 170MHz
fIN = 300MHz
fIN = 10MHz
fIN = 70MHz
fIN = 100MHz
fIN = 170MHz
fIN = 300MHz
fIN = 10MHz
fIN = 70MHz
fIN = 100MHz
fIN = 170MHz
fIN = 300MHz
fIN = 10MHz
fIN = 70MHz
fIN = 100MHz
fIN = 170MHz
fIN = 300MHz
73.9
73.5
73.2
72.4
70.5
73.5
73.3
73
73.7
73.4
73.1
72.2
71.3
73.2
73
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBc
SNR (signal-to-noise ratio), LVDS
69
68
70
SINAD (signal-to-noise and distortion ratio),
LVDS
72.6
71.8
70.6
86
72.3
69.2
87
69
86.5
87
85.5
82
dBc
Spurious-free dynamic range
Total harmonic distortion
Second-harmonic distortion
SFDR
THD
HD2
HD3
dBc
71
85
72.5
70.5
72.5
72.5
78.5
81.5
77
dBc
72.5
84
dBc
83
dBc
84
83.5
81
dBc
84
dBc
69.5
82.5
72.5
88
80
dBc
75.5
87
dBc
dBc
87
85.5
82
dBc
88
dBc
71
87
84
dBc
72.5
87
77
dBc
86
dBc
86.5
87
87
dBc
Third-harmonic distortion
85
dBc
71
85
81.5
84
dBc
85
dBc
96
95
dBc
95
95
dBc
Worst spur
(other than second and third harmonics)
94
95
dBc
77.5
92
91
dBc
87
88
dBc
Two-tone intermodulation
distortion
f1 = 100MHz, f2 = 105MHz,
each tone at –7dBFS
IMD
88.5
1
87.5
1
dBFS
Recovery to within 1% (of final
value) for 6dB overload with
sine-wave input
Clock
cycles
Input overload recovery
For 100mVPP signal on AVDD
supply, up to 10MHz
AC power-supply rejection ratio
PSRR
> 30
> 30
dB
Effective number of bits
Differential nonlinearity
Integrated nonlinearity
ENOB
DNL
INL
fIN = 170MHz
fIN = 170MHz
fIN = 170MHz
11.5
±0.5
±1.5
11.3
±0.5
±1.5
LSBs
LSBs
LSBs
–0.95
1.7
–0.95
1.7
±4.5
±4.5
6
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ADS4142, ADS4145
www.ti.com
SBAS520A –FEBRUARY 2011–REVISED MARCH 2011
ELECTRICAL CHARACTERISTICS: GENERAL
Typical values are at +25°C, AVDD = 1.8V, DRVDD = 1.8V, 50% clock duty cycle, and 0dB gain, unless otherwise noted.
Minimum and maximum values are across the full temperature range: TMIN = –40°C to TMAX = +85°C, AVDD = 1.8V, and
DRVDD = 1.8V.
ADS4122/ADS4142 (65MSPS)
ADS4125/ADS4145 (125MSPS)
PARAMETER
MIN
TYP
MAX
MIN
TYP
MAX
UNIT
ANALOG INPUTS
Differential input voltage range
Differential input resistance (at dc); see Figure 102
Differential input capacitance; see Figure 103
Analog input bandwidth
2.0
> 1
4
2.0
> 1
4
VPP
MΩ
pF
550
0.6
0.95
4
550
0.6
0.95
4
MHz
µA/MSPS
V
Analog input common-mode current (per input pin)
Common-mode output voltage
VCM output current capability
VCM
mA
DC ACCURACY
Offset error
–15
–2
2.5
15
2
–15
–2
2.5
15
mV
Temperature coefficient of offset error
0.003
0.003
mV/°C
Gain error as a result of internal reference
inaccuracy alone
EGREF
2
%FS
Gain error of channel alone
Temperature coefficient of EGCHAN
POWER SUPPLY
EGCHAN
–0.2
–0.2
–1
%FS
0.001
0.001
Δ%/°C
IAVDD
Analog supply current
IDRVDD(1)
Output buffer supply current
LVDS interface with 100Ω external termination
Low LVDS swing (200mV)
42
55
53
62
75
57
mA
mA
28.5
35.5
IDRVDD
Output buffer supply current
LVDS interface with 100Ω external termination
Standard LVDS swing (350mV)
40
15
48
23
mA
mA
IDRVDD output buffer supply current(1)(2)
CMOS interface(2)
8pF external load capacitance
fIN = 2.5MHz
Analog power
76
52
112
mW
mW
Digital power, LVDS interface, low LVDS swing
66.5
Digital power
CMOS interface(2)
8pF external load capacitance
fIN = 2.5MHz
27
41.5
mW
Global power-down
Standby
10
15
10
15
mW
mW
105
130
(1) The maximum DRVDD current with CMOS interface depends on the actual load capacitance on the digital output lines. Note that the
maximum recommended load capacitance on each digital output line is 10pF.
(2) In CMOS mode, the DRVDD current scales with the sampling frequency, the load capacitance on output pins, input frequency, and the
supply voltage (see the CMOS Interface Power Dissipation section in the Application Information).
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ADS4142, ADS4145
SBAS520A –FEBRUARY 2011–REVISED MARCH 2011
www.ti.com
DIGITAL CHARACTERISTICS
Typical values are at +25°C, AVDD = 1.8V, DRVDD = 1.8V, and 50% clock duty cycle, unless otherwise noted. Minimum and
maximum values are across the full temperature range: TMIN = –40°C to TMAX = +85°C, AVDD = 1.8V, and DRVDD = 1.8V.
ADS4122, ADS4125, ADS4142, ADS4145
PARAMETER
DIGITAL INPUTS (RESET, SCLK, SDATA, SEN, OE)
High-level input voltage
TEST CONDITIONS
MIN
TYP
MAX
UNIT
RESET, SCLK, SDATA, and
SEN support 1.8V and 3.3V
CMOS logic levels
1.3
V
V
Low-level input voltage
0.4
0.4
High-level input voltage
1.3
V
OE only supports 1.8V CMOS
logic levels
Low-level input voltage
V
High-level input current: SDATA, SCLK(1)
High-level input current: SEN
Low-level input current: SDATA, SCLK
Low-level input current: SEN
VHIGH = 1.8V
VHIGH = 1.8V
VLOW = 0V
10
0
µA
µA
µA
µA
0
VLOW = 0V
–10
DIGITAL OUTPUTS (CMOS INTERFACE: D0 TO D13, OVR_SDOUT)
High-level output voltage
DRVDD – 0.1
DRVDD
0
V
V
Low-level output voltage
0.1
DIGITAL OUTPUTS (LVDS INTERFACE: DA0P/M TO DA13P/M, DB0P/M TO DB13P/M, CLKOUTP/M)
High-level output voltage(2)
Low-level output voltage(2)
High-level output voltage(2)
Low-level output voltage(2)
Output common-mode voltage
VODH
VODL
VODH
VODL
VOCM
Standard swing LVDS
Standard swing LVDS
Low swing LVDS
270
+350
–350
+200
–200
1.05
430
mV
mV
mV
mV
V
–430
–270
Low swing LVDS
0.85
1.25
(1) SDATA and SCLK have an internal 180kΩ pull-down resistor.
(2) With an external 100Ω termination.
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PIN CONFIGURATION (LVDS MODE)
RGZ PACKAGE(1)
QFN-48
(TOP VIEW)
48 47 46 45 44 43 42 41 40 39 38 37
DRGND
DRVDD
OVR_SDOUT
CLKOUTM
CLKOUTP
DFS
1
2
3
4
5
6
7
8
9
36 DRGND
35 DRVDD
34 NC
33 NC
32 NC
31 NC
OE
30 RESET
29 SCLK
28 SDATA
27 SEN
26 AVDD
25 AGND
AVDD
AGND
CLKP 10
CLKM 11
AGND 12
13 14 15 16 17 18 19 20 21 22 23 24
(1) The PowerPAD is connected to DRGND.
Figure 1. ADS412x LVDS Pinout
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RGZ PACKAGE(2)
QFN-48
(TOP VIEW)
48 47 46 45 44 43 42 41 40 39 38 37
DRGND
DRVDD
OVR_SDOUT
CLKOUTM
CLKOUTP
DFS
1
2
3
4
5
6
7
8
9
36 DRGND
35 DRVDD
34 D0_D1_P
33 D0_D1_M
32 NC
31 NC
OE
30 RESET
29 SCLK
28 SDATA
27 SEN
AVDD
AGND
CLKP 10
CLKM 11
AGND 12
26 AVDD
25 AGND
13 14 15 16 17 18 19 20 21 22 23 24
(2) The PowerPAD™ is connected to DRGND.
Figure 2. ADS414x LVDS Pinout
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ADS414x, ADS412x Pin Assignments (LVDS Mode)
PIN NAME
AVDD
AGND
CLKP
CLKM
INP
PIN NUMBER
# OF PINS
FUNCTION
DESCRIPTION
8, 18, 20, 22, 24, 26
6
6
1
1
1
1
1
I
I
1.8V analog power supply
Analog ground
9, 12, 14, 17, 19, 25
10
11
15
16
13
I
Differential clock input, positive
Differential clock input, negative
Differential analog input, positive
Differential analog input, negative
I
I
INM
I
VCM
O
Outputs the common-mode voltage (0.95V) that can be used externally to bias the analog input pins.
Serial interface RESET input.
When using the serial interface mode, the internal registers must initialize through hardware RESET by
applying a high pulse on this pin or by using the software reset option; refer to the Serial Interface
section.
RESET
30
1
I
When RESET is tied high, the internal registers are reset to the default values. In this condition, SEN
can be used as an analog control pin.
RESET has an internal 180kΩ pull-down resistor.
This pin functions as a serial interface clock input when RESET is low. When RESET is high, SCLK
has no function and should be tied to ground. This pin has an internal 180kΩ pull-down resistor.
SCLK
29
28
1
1
I
I
This pin functions as a serial interface data input when RESET is low. When RESET is high, SDATA
functions as a STANDBY control pin (see Table 7). This pin has an internal 180kΩ pull-down resistor.
SDATA
This pin functions as a serial interface enable input when RESET is low. When RESET is high, SEN
has no function and should be tied to AVDD. This pin has an internal 180kΩ pull-up resistor to AVDD.
SEN
OE
27
7
1
1
1
I
I
I
Output buffer enable input, active high; this pin has an internal 180kΩ pull-up resistor to DRVDD.
Data format select input. This pin sets the DATA FORMAT (twos complement or offset binary) and the
LVDS/CMOS output interface type. See Table 5 for detailed information.
DFS
6
RESERVED
CLKOUTP
CLKOUTM
23
5
1
1
1
I
Digital control pin, reserved for future use
Differential output clock, true
O
O
4
Differential output clock, complement
Refer to Figure 1 and
Figure 2
D0_D1_P
D0_D1_M
D2_D3_P
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
Differential output data D0 and D1 multiplexed, true
Differential output data D0 and D1 multiplexed, complement
Differential output data D2 and D3 multiplexed, true
Differential output data D2 and D3 multiplexed, complement
Differential output data D4 and D5 multiplexed, true
Differential output data D4 and D5 multiplexed, complement
Differential output data D6 and D7 multiplexed, true
Differential output data D6 and D7 multiplexed, complement
Differential output data D8 and D9 multiplexed, true
Differential output data D8 and D9 multiplexed, complement
Differential output data D10 and D11 multiplexed, true
Differential output data D10 and D11 multiplexed, complement
Differential output data D12 and D13 multiplexed, true
Differential output data D12 and D13 multiplexed, complement
Refer to Figure 1 and
Figure 2
Refer to Figure 1 and
Figure 2
Refer to Figure 1 and
Figure 2
D2_D3_M
D4_D5_P
Refer to Figure 1 and
Figure 2
Refer to Figure 1 and
Figure 2
D4_D5_M
D6_D7_P
Refer to Figure 1 and
Figure 2
Refer to Figure 1 and
Figure 2
D6_D7_M
D8_D9_P
Refer to Figure 1 and
Figure 2
Refer to Figure 1 and
Figure 2
D8_D9_M
D10_D11_P
D10_D11_M
D12_D13_P
D12_D13_M
OVR_SDOUT
Refer to Figure 1 and
Figure 2
Refer to Figure 1 and
Figure 2
Refer to Figure 1 and
Figure 2
Refer to Figure 1 and
Figure 2
This pin functions as an out-of-range indicator after reset, when register bit
READOUT = 0, and functions as a serial register readout pin when READOUT = 1.
3
DRVDD
DRGND
2, 35
2
2
I
I
1.8V digital and output buffer supply
Digital and output buffer ground
1, 36, PAD
Refer to Figure 1 and
Figure 2
NC
—
—
Do not connect
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PIN CONFIGURATION (CMOS MODE)
RGZ PACKAGE(3)
QFN-48
(TOP VIEW)
48 47 46 45 44 43 42 41 40 39 38 37
DRGND
DRVDD
OVR_SDOUT
UNUSED
CLKOUT
DFS
1
2
3
4
5
6
7
8
9
36 DRGND
35 DRVDD
34 NC
33 NC
32 NC
31 NC
OE
30 RESET
29 SCLK
28 SDATA
27 SEN
26 AVDD
25 AGND
AVDD
AGND
CLKP 10
CLKM 11
AGND 12
13 14 15 16 17 18 19 20 21 22 23 24
(3) The PowerPAD is connected to DRGND.
Figure 3. ADS412x CMOS Pinout
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RGZ PACKAGE(4)
QFN-48
(TOP VIEW)
48 47 46 45 44 43 42 41 40 39 38 37
DRGND
DRVDD
OVR_SDOUT
UNUSED
CLKOUT
DFS
1
2
3
4
5
6
7
8
9
36 DRGND
35 DRVDD
34 D1
33 D0
32 NC
31 NC
OE
30 RESET
29 SCLK
28 SDATA
27 SEN
26 AVDD
25 AGND
AVDD
AGND
CLKP 10
CLKM 11
AGND 12
13 14 15 16 17 18 19 20 21 22 23 24
(4) The PowerPAD is connected to DRGND.
Figure 4. ADS414x CMOS Pinout
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ADS414x, ADS412x Pin Assignments (CMOS Mode)
PIN NAME
AVDD
AGND
CLKP
CLKM
INP
PIN NUMBER
# OF PINS
FUNCTION
DESCRIPTION
8, 18, 20, 22, 24, 26
6
6
1
1
1
1
1
I
I
1.8V analog power supply
Analog ground
9, 12, 14, 17, 19, 25
10
11
15
16
13
I
Differential clock input, positive
Differential clock input, negative
Differential analog input, positive
Differential analog input, negative
I
I
INM
I
VCM
O
Outputs the common-mode voltage (0.95V) that can be used externally to bias the analog input pins.
Serial interface RESET input.
When using the serial interface mode, the internal registers must initialize through hardware RESET by
applying a high pulse on this pin or by using the software reset option; refer to the Serial Interface
section.
RESET
30
1
I
When RESET is tied high, the internal registers are reset to the default values. In this condition, SEN
can be used as an analog control pin.
RESET has an internal 180kΩ pull-down resistor.
This pin functions as a serial interface clock input when RESET is low. When RESET is high, SCLK
has no function and should be tied to ground. This pin has an internal 180kΩ pull-down resistor.
SCLK
29
28
1
1
I
I
This pin functions as a serial interface data input when RESET is low. When RESET is high, SDATA
functions as a STANDBY control pin (see Table 7). This pin has an internal 180kΩ pull-down resistor.
SDATA
This pin functions as a serial interface enable input when RESET is low. When RESET is high, SEN
has no function and should be tied to AVDD. This pin has an internal 180kΩ pull-up resistor to AVDD.
SEN
OE
27
7
1
1
1
I
I
I
Output buffer enable input, active high; this pin has an internal 180kΩ pull-up resistor to DRVDD.
Data format select input. This pin sets the DATA FORMAT (twos complement or offset binary) and the
LVDS/CMOS output interface type. See Table 5 for detailed information.
DFS
6
RESERVED
CLKOUT
23
5
1
1
I
Digital control pin, reserved for future use
CMOS output clock
O
Refer to Figure 3 and
Figure 4
D0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
12-bit/14-bit CMOS output data
12-bit/14-bit CMOS output data
12-bit/14-bit CMOS output data
12-bit/14-bit CMOS output data
12-bit/14-bit CMOS output data
12-bit/14-bit CMOS output data
12-bit/14-bit CMOS output data
12-bit/14-bit CMOS output data
Refer to Figure 3 and
Figure 4
D1
Refer to Figure 3 and
Figure 4
D2
Refer to Figure 3 and
Figure 4
D3
Refer to Figure 3 and
Figure 4
D4
Refer to Figure 3 and
Figure 4
D5
Refer to Figure 3 and
Figure 4
D6
Refer to Figure 3 and
Figure 4
D7
D8
Refer to Figure 3 and
Figure 4
12-bit/14-bit CMOS output data
12-bit/14-bit CMOS output data
Refer to Figure 3 and
Figure 4
D9
Refer to Figure 3 and
Figure 4
D10
12-bit/14-bit CMOS output data
12-bit/14-bit CMOS output data
12-bit/14-bit CMOS output data
12-bit/14-bit CMOS output data
Refer to Figure 3 and
Figure 4
D11
Refer to Figure 3 and
Figure 4
D12
Refer to Figure 3 and
Figure 4
D13
This pin functions as an out-of-range indicator after reset, when register bit
READOUT = 0, and functions as a serial register readout pin when READOUT = 1.
OVR_SDOUT
3
DRVDD
DRGND
UNUSED
2, 35
1, 36, PAD
4
2
2
1
I
I
1.8V digital and output buffer supply
Digital and output buffer ground
Unused pin in CMOS mode
—
Refer to Figure 3 and
Figure 4
NC
—
—
Do not connect
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FUNCTIONAL BLOCK DIAGRAM
DDR LVDS
Interface
AVDD
AGND
DRVDD DRGND
CLKP
CLKM
CLKOUTP
CLKOUTM
CLOCKGEN
D0_D1_P
D0_D1_M
D2_D3_P
D2_D3_M
Low-Latency Mode
(Default After Reset)
D4_D5_P
D4_D5_M
INP
INM
12-Bit
ADC
DDR
Serializer
Sampling
Circuit
Common
Digital Functions
D6_D7_P
D6_D7_M
D8_D9_P
D8_D9_M
Control
Interface
VCM
Reference
D10_D11_P
D10_D11_M
OVR_SDOUT
ADS412x
OE
Figure 5. ADS412x Block Diagram
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DDR LVDS
Interface
AVDD
AGND
DRVDD DRGND
CLKP
CLKM
CLKOUTP
CLOCKGEN
CLKOUTM
D0_D1_P
D0_D1_M
D2_D3_P
D2_D3_M
D4_D5_P
D4_D5_M
Low-Latency Mode
(Default After Reset)
D6_D7_P
D6_D7_M
INP
INM
14-Bit
ADC
DDR
Serializer
Sampling
Circuit
Common
Digital Functions
D8_D9_P
D8_D9_M
D10_D11_P
D10_D11_M
Control
Interface
D12_D13_P
D12_D13_M
VCM
Reference
OVR_SDOUT
ADS414x
OE
Figure 6. ADS414x Block Diagram
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TIMING CHARACTERISTICS
Dn_Dn + 1_P
Logic 0
VODL
Logic 1
VODH
Dn_Dn + 1_M
VOCM
GND
(1) With external 100Ω termination.
Figure 7. LVDS Output Voltage Levels
TIMING REQUIREMENTS: LVDS and CMOS Modes(1)
Typical values are at +25°C, AVDD = 1.8V, DRVDD = 1.8V, sampling frequency = 125 MSPS, sine wave input clock,
CLOAD = 5pF(2), and RLOAD = 100Ω(3), unless otherwise noted. Minimum and maximum values are across the full temperature
range: TMIN = –40°C to TMAX = +85°C, AVDD = 1.8V, and DRVDD = 1.7V to 1.9V.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
tA
Aperture delay
0.6
0.8
1.2
ns
Variation of aperture
delay
Between two devices at the same temperature and
DRVDD supply
±100
100
5
ps
fS rms
µs
tJ
Aperture jitter
Time to valid data after coming out of STANDBY
mode
25
Wakeup time
Time to valid data after coming out of PDN GLOBAL
mode
100
10
500
µs
Clock
cycles
Low-latency mode (default after reset)
Low-latency mode disabled (gain enabled, offset
correction disabled)
Clock
cycles
ADC latency(4)
16
Low-latency mode disabled (gain and offset
correction enabled)
Clock
cycles
17
DDR LVDS MODE(5)(6)
tSU
Data setup time(3)
Data valid(7) to zero-crossing of CLKOUTP
2.3
3.0
ns
ns
Zero-crossing of CLKOUTP to data becoming
invalid(7)
tH
Data hold time(3)
0.35
0.60
Input clock rising edge cross-over to output clock
rising edge cross-over
Clock propagation
delay
tPDI
3
4.2
5.4
ns
ns
Sampling frequency ≤ 125MSPS
Between two devices at the same temperature and
DRVDD supply
Variation of tPDI
±0.6
(1) Timing parameters are ensured by design and characterization but are not production tested.
(2) CLOAD is the effective external single-ended load capacitance between each output pin and ground.
(3) RLOAD is the differential load resistance between the LVDS output pair.
(4) At higher frequencies, tPDI is greater than one clock period and overall latency = ADC latency + 1.
(5) Measurements are done with a transmission line of 100Ω characteristic impedance between the device and the load. Setup and hold
time specifications take into account the effect of jitter on the output data and clock.
(6) The LVDS timings are unchanged for low latency disabled and enabled.
(7) Data valid refers to a logic high of +100mV and a logic low of –100mV.
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TIMING REQUIREMENTS: LVDS and CMOS Modes(1) (continued)
Typical values are at +25°C, AVDD = 1.8V, DRVDD = 1.8V, sampling frequency = 125 MSPS, sine wave input clock,
CLOAD = 5pF(2), and RLOAD = 100Ω(3), unless otherwise noted. Minimum and maximum values are across the full temperature
range: TMIN = –40°C to TMAX = +85°C, AVDD = 1.8V, and DRVDD = 1.7V to 1.9V.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
DDR LVDS MODE (continued)
Duty cycle of differential clock, (CLKOUTP –
CLKOUTM)
LVDS bit clock duty
cycle
48
%
Sampling frequency ≤ 125MSPS
Rise time measured from –100mV to +100mV
Fall time measured from +100mV to –100mV
Sampling frequency ≤ 125MSPS
Data rise time,
tRISE, tFALL
0.14
ns
Data fall time
Output clock rise
time,
Output clock fall time
Rise time measured from –100mV to +100mV
Fall time measured from +100mV to –100mV
Sampling frequency ≤ 125MSPS
tCLKRISE
tCLKFALL
,
0.14
50
ns
ns
Output enable (OE) to
data delay
tOE
Time to valid data after OE becomes active
100
PARALLEL CMOS MODE(8)
tSETUP
Data setup time
Data valid(9) to 50% of CLKOUT rising edge
3.1
3.2
3.7
4.0
ns
ns
50% of of CLKOUT rising edge to data becoming
invalid(9)
tHOLD
Data hold time
Input clock rising edge cross-over to 50% of output
clock rising edge
Clock propagation
delay
tPDI
4
5.5
47
7
ns
%
Sampling frequency ≤ 125MSPS
Output clock duty
cycle
Duty cycle of output clock, CLKOUT
Sampling frequency ≤ 125MSPS
Rise time measured from 20% to 80% of DRVDD
Fall time measured from 80% to 20% of DRVDD
Sampling frequency ≤ 125MSPS
Data rise time,
Data fall time
tRISE, tFALL
0.35
ns
Output clock rise
time,
Output clock fall time
Rise time measured from 20% to 80% of DRVDD
Fall time measured from 80% to 20% of DRVDD
Sampling frequency ≤ 125MSPS
tCLKRISE
tCLKFALL
,
0.35
20
ns
ns
Output enable (OE) to
data delay
tOE
Time to valid data after OE becomes active
40
(8) Low latency mode enabled.
(9) Data valid refers to a logic high of 1.25V and a logic low of 0.54V.
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Table 2. LVDS Timing Across Sampling Frequencies
SAMPLING
SETUP TIME (ns)
HOLD TIME (ns)
FREQUENCY
(MSPS)
MIN
5.5
TYP
6.5
MAX
MIN
0.35
0.35
TYP
0.60
0.60
MAX
65
80
4.50
5.20
Table 3. CMOS Timing Across Sampling Frequencies (Low Latency Enabled)
TIMING SPECIFIED WITH RESPECT TO OUTPUT CLOCK
SAMPLING
FREQUENCY
(MSPS)
tSETUP (ns)
TYP
tHOLD (ns)
TYP
tPDI (ns)
TYP
5.5
MIN
6.5
MAX
MIN
6.5
MAX
MIN
4.0
MAX
65
80
7.5
7.5
7.0
7.0
5.4
6.0
5.4
6.0
4.0
5.5
Table 4. CMOS Timing Across Sampling Frequencies (Low Latency Disabled)
TIMING SPECIFIED WITH RESPECT TO OUTPUT CLOCK
SAMPLING
FREQUENCY
(MSPS)
tSETUP (ns)
tHOLD (ns)
tPDI (ns)
TYP
5.5
MIN
6
TYP
7
MAX
MIN
7
TYP
8
MAX
MIN
4.0
4.0
4.0
MAX
7.0
65
80
4.8
2.5
5.5
3.2
5.7
3.5
6.5
4.3
5.5
7.0
125
5.5
7.0
N + 12
N + 3
N + 4
N + 11
N + 2
N + 1
N + 10
Sample N
Input Signal
Input Clock
tA
CLKP
CLKM
CLKOUTM
CLKOUTP
tPDI
tH
10 Clock Cycles(1)
tSU
DDR LVDS
Output Data(2)
(DXP, DXM)
E
O
E
O
E
O
E
O
E
O
E
O
E
O
E
O
E
O
E
O
N - 10
N - 9
N - 8
N - 7
N - 6
N + 1
N + 2
N
tPDI
CLKOUT
tSU
Parallel CMOS
10 Clock Cycles(1)
tH
Output Data
N - 10
N - 9
N - 8
N - 7
N - 1
N
N + 1
(1) ADC latency in low-latency mode. At higher sampling frequencies, tDPI is greater than one clock cycle which then makes the overall
latency = ADC latency + 1.
(2) E = Even bits (D0, D2, D4, etc). O = Odd bits (D1, D3, D5, etc).
Figure 8. Latency Diagram
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CLKM
Input
Clock
CLKP
tPDI
CLKOUTP
Output
Clock
CLKOUTM
tSU
tH
tSU
tH
Dn_Dn + 1_P
Dn_Dn + 1_M
Output
Data Pair
Dn(1)
Dn + 1(1)
(1) Dn = bits D0, D2, D4, etc. Dn + 1 = Bits D1, D3, D5, etc.
Figure 9. LVDS Mode Timing
CLKM
Input
Clock
CLKP
tPDI
Output
Clock
CLKOUT
tSU
tH
Output
Data
Dn(1)
Dn
CLKM
CLKP
Input
Clock
tSTART
tDV
Output
Data
Dn(1)
Dn
Dn = bits D0, D1, D2, etc.
Figure 10. CMOS Mode Timing
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DEVICE CONFIGURATION
The ADS412x/4x have several modes that can be configured using a serial programming interface, as described
in Table 5, Table 6, and Table 7. In addition, the devices have two dedicated parallel pins for quickly configuring
commonly used functions. The parallel pins are DFS (analog 4-level control pin) and OE (digital control pin). The
analog control pins can be easily configured using a simple resistor divider (with 10% tolerance resistors).
Table 5. DFS: Analog Control Pin
DESCRIPTION
VOLTAGE APPLIED ON DFS
0, +100mV/–0mV
(Data Format/Output Interface)
Twos complement/DDR LVDS
Twos complement/parallel CMOS
Offset binary/parallel CMOS
Offset binary/DDR LVDS
(3/8) AVDD ± 100mV
(5/8) AVDD ± 100mV
AVDD, +0mV/–100mV
Table 6. OE: Digital Control Pin
VOLTAGE APPLIED ON OE
DESCRIPTION
0
Output data buffers disabled
Output data buffers enabled
AVDD
When the serial interface is not used, the SDATA pin can also be used as a digital control pin to place the device
in standby mode. To enable this, the RESET pin must be tied high. In this mode, SEN and SCLK do not have
any alternative functions. Keep SEN tied high and SCLK tied low on the board.
Table 7. SDATA: Digital Control Pin
VOLTAGE APPLIED ON SDATA
DESCRIPTION
Normal operation
0
Logic high
Device enters standby
AVDD
(5/8) AVDD
3R
(5/8) AVDD
(3/8) AVDD
GND
AVDD
2R
3R
(3/8) AVDD
To Parallel Pin
Figure 11. Simplified Diagram to Configure DFS Pin
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SERIAL INTERFACE
The analog-to-digital converter (ADC) has a set of internal registers that can be accessed by the serial interface
formed by the SEN (serial interface enable), SCLK (serial interface clock), and SDATA (serial interface data)
pins. Serial shift of bits into the device is enabled when SEN is low. Serial data SDATA are latched at every
falling edge of SCLK when SEN is active (low). The serial data are loaded into the register at every 16th SCLK
falling edge when SEN is low. If the word length exceeds a multiple of 16 bits, the excess bits are ignored. Data
can be loaded in multiples of 16-bit words within a single active SEN pulse. The first eight bits form the register
address and the remaining eight bits are the register data. The interface can work with SCLK frequency from
20MHz down to very low speeds (a few hertz) and also with non-50% SCLK duty cycle.
Register Initialization
After power-up, the internal registers must be initialized to the default values. This initialization can be
accomplished in one of two ways:
1. Either through hardware reset by applying a high pulse on RESET pin (of width greater than 10ns), as shown
in Figure 12; or
2. By applying a software reset. When using the serial interface, set the RESET bit (D7 in register 00h) high.
This setting initializes the internal registers to the default values and then self-resets the RESET bit low. In
this case, the RESET pin is kept low.
Register Address
A4
A3
Register Data
SDATA
SCLK
A7
A6
A5
A2
A1
A0
D7
D6
D5
D4
D3
D2
tDH
D1
D0
tSCLK
tDSU
tSLOADS
tSLOADH
SEN
RESET
Figure 12. Serial Interface Timing
SERIAL INTERFACE TIMING CHARACTERISTICS
Typical values at +25°C, minimum and maximum values across the full temperature range: TMIN = –40°C to TMAX = +85°C,
AVDD = 1.8V, and DRVDD = 1.8V, unless otherwise noted.
PARAMETER
SCLK frequency (equal to 1/tSCLK
SEN to SCLK setup time
SCLK to SEN hold time
SDATA setup time
MIN
> DC
25
TYP
MAX
UNIT
MHz
ns
fSCLK
tSLOADS
tSLOADH
tDSU
)
20
25
ns
25
ns
tDH
SDATA hold time
25
ns
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Serial Register Readout
The serial register readout function allows the contents of the internal registers to be read back on the
OVR_SDOUT pin. This readback may be useful as a diagnostic check to verify the serial interface
communication between the external controller and the ADC.
After power-up and device reset, the OVR_SDOUT pin functions as an over-range indicator pin by default. When
the readout mode is enabled, OVR_SDOUT outputs the contents of the selected register serially:
1. Set the READOUT register bit to '1'. This setting puts the device in serial readout mode and disables any
further writes to the internal registers except the register at address 0. Note that the READOUT bit itself is
also located in register 0. The device can exit readout mode by writing READOUT = 0. Only the contents of
the register at address 0 cannot be read in the register readout mode.
2. Initiate a serial interface cycle specifying the address of the register (A7 to A0) whose content has to be
read.
3. The device serially outputs the contents (D7 to D0) of the selected register on the OVR_SDOUT pin.
4. The external controller can latch the contents at the falling edge of SCLK.
5. To exit the serial readout mode, the reset register bit READOUT = 0 enables writes into all registers of the
device. At this point, the OVR_SDOUT pin becomes an over-range indicator pin.
Register Address A[7:0] = 0x00
Register Data D[7:0] = 0x01
SDATA
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
SCLK
SEN
OVR_SDOUT(1)
a) Enable Serial Readout (READOUT = 1)
Register Address A[7:0] = 0x43
A4 A2
A5 A3
Register Data D[7:0] = XX (don’t care)
D4 D2 D1
D6 D5 D3
SDATA
SCLK
A7
A6
A1
A0
D7
D0
SEN
OVR_SDOUT(2)
0
1
0
0
0
0
0
0
b) Read Contents of Register 0x43. This Register Has Been Initialized with 0x40 (device is put into global power-down mode).
(1) The OVR_SDOUT pin finctions as OVR (READOUT = 0).
(2) The OVR_SDOUT pin finctions as a serial readout (READOUT = 1).
Figure 13. Serial Readout Timing Diagram
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RESET TIMING CHARACTERISTICS
Power Supply
AVDD, DRVDD
t1
RESET
t2
t3
SEN
NOTE: A high pulse on the RESET pin is required in the serial interface mode in case of initialization through hardware reset. For parallel
interface operation, RESET must be permanently tied high.
Figure 14. Reset Timing Diagram
RESET TIMING REQUIREMENTS
Typical values at +25°C and minimum and maximum values across the full temperature range: TMIN = –40°C to TMAX = +85°C,
unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
1
TYP
MAX
UNIT
Delay from power-up of AVDD and DRVDD to RESET
pulse active
t1
Power-on delay
ms
10
ns
µs
ns
Pulse width of active RESET signal that resets the
serial registers
t2
t3
Reset pulse width
1(1)
Delay from RESET disable to SEN active
100
(1) The reset pulse is needed only when using the serial interface configuration. If the pulse width is greater than 1µs, the device could
enter the parallel configuration mode briefly and then return back to serial interface mode.
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SERIAL REGISTER MAP
Table 8 summarizes the functions supported by the serial interface.
Table 8. Serial Interface Register Map(1)
REGISTER
ADDRESS
DEFAULT VALUE
AFTER RESET
REGISTER DATA
A[7:0] (Hex)
D[7:0] (Hex)
D7
D6
D5
D4
D3
D2
D1
RESET
0
D0
READOUT
0
00
01
03
00
00
00
0
0
0
0
0
0
LVDS SWING
0
0
0
0
0
0
0
0
0
HIGH PERF MODE 1
TEST PATTERNS
DISABLE
GAIN
25
26
00
00
GAIN
LVDS
CLKOUT
STRENGTH
LVDS DATA
STRENGTH
0
0
0
0
0
0
EN
OFFSET
CORR
3D
00
DATA FORMAT
0
0
0
3F
40
00
00
CUSTOM PATTERN HIGH D[13:6]
CUSTOM PATTERN D[5:0]
0
EN
CLKOUT
RISE
EN
CLKOUT
FALL
CMOS CLKOUT
STRENGTH
41
00
LVDS CMOS
CLKOUT RISE POSN
DIS LOW
LATENCY
42
43
00
00
CLKOUT FALL POSN
0
0
0
0
STBY
0
0
PDN
GLOBAL
0
PDN OBUF
0
0
0
0
0
EN LVDS SWING
HIGH PERF
MODE 2
4A
BF
00
00
0
0
0
0
OFFSET PEDESTAL
OFFSET CORR TIME CONSTANT
LOW SPEED
0
FREEZE
OFFSET
CORR
CF
DF
00
00
0
0
0
0
0
0
0
0
0
(1) Multiple functions in a register can be programmed in a single write operation.
DESCRIPTION OF SERIAL REGISTERS
For best performance, two special mode register bits must be enabled: HI PERF MODE 1 and HI PERF MODE
2.
Register Address 00h (Default = 00h)
7
0
6
0
5
0
4
3
2
0
1
0
0
0
RESET
READOUT
Bits[7:2]
Bit 1
Always write '0'
RESET: Software reset applied
This bit resets all internal registers to the default values and self-clears to 0 (default = 1).
READOUT: Serial readout
Bit 0
This bit sets the serial readout of the registers.
0 = Serial readout of registers disabled; the OVR_SDOUT pin functions as an over-voltage
indicator.
1 = Serial readout enabled; the OVR_SDOUT pin functions as a serial data readout.
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Register Address 01h (Default = 00h)
7
6
5
4
3
2
1
0
0
0
LVDS SWING
Bits[7:2]
LVDS SWING: LVDS swing programmability(1)
000000 = Default LVDS swing; ±350mV with external 100Ω termination
011011 = LVDS swing increases to ±410mV
110010 = LVDS swing increases to ±465mV
010100 = LVDS swing increases to ±570mV
111110 = LVDS swing decreases to ±200mV
001111 = LVDS swing decreases to ±125mV
Bits[1:0]
Always write '0'
(1) The EN LVDS SWING register bits must be set to enable LVDS swing control.
Register Address 03h (Default = 00h)
7
0
6
0
5
0
4
3
2
0
1
0
0
0
HI PERF MODE 1
Bits[7:2]
Bits[1:0]
Always write '0'
HI PERF MODE 1: High performance mode 1
00 = Default performance after reset
01 = Do not use
10 = Do not use
11 = For best performance across sampling clock and input signal frequencies, set the HIGH PERF
MODE 1 bits
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Register Address 25h (Default = 00h)
7
6
5
4
3
2
1
0
GAIN
DISABLE GAIN
TEST PATTERNS
Bits[7:4]
GAIN: Gain programmability
These bits set the gain programmability in 0.5dB steps.
0000 = 0dB gain (default after reset)
0001 = 0.5dB gain
0010 = 1.0dB gain
0011 = 1.5dB gain
0100 = 2.0dB gain
0111 = 3.5dB gain
1000 = 4.0dB gain
1001 = 4.5dB gain
1010 = 5.0dB gain
1011 = 5.5dB gain
1100 = 6dB gain
0101 = 2.5dB gain
0110 = 3.0dB gain
Bit 3
DISABLE GAIN: Gain setting
This bit sets the gain.
0 = Gain enabled; gain is set by the GAIN bits only if low-latency mode is disabled
1 = Gain disabled
Bits[2:0]
TEST PATTERNS: Data capture
These bits verify data capture.
000 = Normal operation
001 = Outputs all 0s
010 = Outputs all 1s
011 = Outputs toggle pattern
In the ADS4122/25, output data D[11:0] is an alternating sequence of 010101010101 and
101010101010.
In the ADS4142/45, output data D[13:0] is an alternating sequence of 01010101010101 and
10101010101010.
100 = Outputs digital ramp
In ADS4122/25, output data increments by one LSB (12-bit) every fourth clock cycle from code 0
to code 4095
In ADS4142/45, output data increments by one LSB (14-bit) every clock cycle from code 0 to
code 16383
101 = Output custom pattern (use registers 3Fh and 40h for setting the custom pattern)
110 = Unused
111 = Unused
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Register Address 26h (Default = 00h)
7
0
6
0
5
0
4
3
2
0
1
0
LVDS CLKOUT
STRENGTH
LVDS DATA
STRENGTH
0
0
Bits[7:2]
Bit 1
Always write '0'
LVDS CLKOUT STRENGTH: LVDS output clock buffer strength
This bit determines the external termination to be used with the LVDS output clock buffer.
0 = 100Ω external termination (default strength)
1 = 50Ω external termination (2x strength)
Bit 0
LVDS DATA STRENGTH: LVDS data buffer strength
This bit determines the external termination to be used with all of the LVDS data buffers.
0 = 100Ω external termination (default strength)
1 = 50Ω external termination (2x strength)
Register Address 3Dh (Default = 00h)
7
6
5
4
3
2
0
1
0
0
0
EN OFFSET
CORR
DATA FORMAT
0
0
Bits[7:6]
DATA FORMAT: Data format selection
These bits selects the data format.
00 = The DFS pin controls data format selection
10 = Twos complement
11 = Offset binary
Bit 5
ENABLE OFFSET CORR: Offset correction setting
This bit sets the offset correction.
0 = Offset correction disabled
1 = Offset correction enabled
Bits[4:0]
Always write '0'
Register Address 3Fh (Default = 00h)
7
6
5
4
3
2
1
0
CUSTOM
CUSTOM
CUSTOM
CUSTOM
CUSTOM
CUSTOM
CUSTOM
CUSTOM
PATTERN D13 PATTERN D12 PATTERN D11 PATTERN D10 PATTERN D9
PATTERN D8
PATTERN D7
PATTERN D6
Bits[7:0]
CUSTOM PATTERN(1)
These bits set the custom pattern.
(1) For the ADS414x, output data bits 13 to 0 are CUSTOM PATTERN D[13:0]. For the ADS412x, output data bits 11 to 0 are CUSTOM
PATTERN D[13:2].
Register Address 40h (Default = 00h)
7
6
5
4
3
2
1
0
0
0
CUSTOM
PATTERN D5
CUSTOM
PATTERN D4
CUSTOM
PATTERN D3
CUSTOM
PATTERN D2
CUSTOM
PATTERN D1
CUSTOM
PATTERN D0
Bits[7:2]
CUSTOM PATTERN(1)
These bits set the custom pattern.
Bits[1:0]
Always write '0'
(1) For the ADS414x, output data bits 13 to 0 are CUSTOM PATTERN D[13:0]. For the ADS412x, output data bits 11 to 0 are CUSTOM
PATTERN D[13:2].
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Register Address 41h (Default = 00h)
7
6
5
4
3
2
1
0
EN CLKOUT
RISE
EN CLKOUT
FALL
LVDS CMOS
CMOS CLKOUT STRENGTH
CLKOUT RISE POSN
Bits[7:6]
LVDS CMOS: Interface selection
These bits select the interface.
00 = The DFS pin controls the selection of either LVDS or CMOS interface
10 = The DFS pin controls the selection of either LVDS or CMOS interface
01 = DDR LVDS interface
11 = Parallel CMOS interface
Bits[5:4]
CMOS CLKOUT STRENGTH
Controls strength of CMOS output clock only.
00 = Maximum strength (recommended and used for specified timings)
01 = Medium strength
10 = Low strength
11 = Very low strength
Bit 3
ENABLE CLKOUT RISE
0 = Disables control of output clock rising edge
1 = Enables control of output clock rising edge
Bits[2:1]
CLKOUT RISE POSN: CLKOUT rise control
Controls position of output clock rising edge
LVDS interface:
00 = Default position (timings are specified in this condition)
01 = Setup reduces by 500ps, hold increases by 500ps
10 = Data transition is aligned with rising edge
11 = Setup reduces by 200ps, hold increases by 200ps
CMOS interface:
00 = Default position (timings are specified in this condition)
01 = Setup reduces by 100ps, hold increases by 100ps
10 = Setup reduces by 200ps, hold increases by 200ps
11 = Setup reduces by 1.5ns, hold increases by 1.5ns
Bit 0
ENABLE CLKOUT FALL
0 = Disables control of output clock fall edge
1 = Enables control of output clock fall edge
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Register Address 42h (Default = 00h)
7
6
5
0
4
3
2
1
0
0
0
DIS LOW
LATENCY
CLKOUT FALL CTRL
0
STBY
Bits[7:6]
CLKOUT FALL CTRL
Controls position of output clock falling edge
LVDS interface:
00 = Default position (timings are specified in this condition)
01 = Setup reduces by 400ps, hold increases by 400ps
10 = Data transition is aligned with rising edge
11 = Setup reduces by 200ps, hold increases by 200ps
CMOS interface:
00 = Default position (timings are specified in this condition)
01 = Falling edge is advanced by 100ps
10 = Falling edge is advanced by 200ps
11 = Falling edge is advanced by 1.5ns
Bits[5:4]
Bit 3
Always write '0'
DIS LOW LATENCY: Disable low latency
This bit disables low-latency mode,
0 = Low-latency mode is enabled. Digital functions such as gain, test patterns and offset correction
are disabled
1 = Low-latency mode is disabled. This setting enables the digital functions. See the Digital
Functions and Low Latency Mode section.
Bit 2
STBY: Standby mode
This bit sets the standby mode.
0 = Normal operation
1 = Only the ADC and output buffers are powered down; internal reference is active; wake-up time
from standby is fast
Bits[1:0]
Always write '0'
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Register Address 43h (Default = 00h)
7
0
6
5
0
4
3
2
0
1
0
PDN GLOBAL
PDN OBUF
0
EN LVDS SWING
Bit 0
Bit 6
Always write '0'
PDN GLOBAL: Power-down
This bit sets the state of operation.
0 = Normal operation
1 = Total power down; the ADC, internal references, and output buffers are powered down; slow
wake-up time.
Bit 5
Bit 4
Always write '0'
PDN OBUF: Power-down output buffer
This bit set the output data and clock pins.
0 = Output data and clock pins enabled
1 = Output data and clock pins powered down and put in high- impedance state
Bits[3:2]
Bits[1:0]
Always write '0'
EN LVDS SWING: LVDS swing control
00 = LVDS swing control using LVDS SWING register bits is disabled
01 = Do not use
10 = Do not use
11 = LVDS swing control using LVDS SWING register bits is enabled
Register Address 4Ah (Default = 00h)
7
0
6
0
5
0
4
3
2
0
1
0
0
HI PERF
MODE 2
0
0
Bits[7:1]
Bit[0]
Always write '0'
HI PERF MODE 2: High performance mode 2
This bit is recommended for high input signal frequencies greater than 230MHz.
0 = Default performance after reset
1 = For best performance with high-frequency input signals, set the HIGH PERF MODE 2 bit
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Register Address BFh (Default = 00h)
7
6
5
4
3
2
1
0
0
0
OFFSET PEDESTAL
Bits[7:2]
OFFSET PEDESTAL
These bits set the offset pedestal.
When the offset correction is enabled, the final converged value after the offset is corrected is the
ADC mid-code value. A pedestal can be added to the final converged value by programming these
bits.
ADS414x VALUE
PEDESTAL
011111
011110
011101
—
31LSB
30LSB
29LSB
—
000000
—
0LSB
—
111111
111110
—
–1LSB
–2LSB
—
100000
–32LSB
Bits[1:0]
Always write '0'
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Register Address CFh (Default = 00h)
7
6
0
5
4
3
2
1
0
0
0
FREEZE
OFFSET
CORR
OFFSET CORR TIME CONSTANT
Bit 7
FREEZE OFFSET CORR
This bit sets the freeze offset correction.
0 = Estimation of offset correction is not frozen (bit EN OFFSET CORR must be set)
1 = Estimation of offset correction is frozen (bit EN OFFSET CORR must be set). When frozen, the
last estimated value is used for offset correction every clock cycle. See the Offset Correction
section.
Bit 6
Always write '0'
Bits[5:2]
OFFSET CORR TIME CONSTANT
These bits set the offset correction time constant for the correction loop time constant in number of
clock cycles.
VALUE
TIME CONSTANT (Number of Clock Cycles)
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1M
2M
4M
8M
16M
32M
64M
128M
256M
512M
1G
2G
Bits[1:0]
Always write '0'
Register Address DFh (Default = 00h)
7
0
6
0
5
4
3
2
0
1
0
0
0
LOW SPEED
0
Bits[7:6]
Bits[5:4]
Always write '0'
LOW SPEED: Low-speed mode
For the ADS4122/42, the low-speed mode is enabled by default after reset.
00, 01, 10, 11 = Do not use
For the ADS4125/55 only:
00, 01, 10 = Low-speed mode disabled (default state after reset); this setting is recommended for
sampling rates greater than 80MSPS.
11 = Low-speed mode enabled; this setting is recommended for sampling rates less than or equal
to 80MSPS.
Bits[3:0]
Always write '0'
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TYPICAL CHARACTERISTICS: ADS4122
At +25°C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential clock
amplitude, 50% clock duty cycle, –1dBFS differential analog input, 0dB gain, low-latency mode, DDR LVDS output interface,
and 32k-point FFT, unless otherwise noted.
FFT FOR 20MHz INPUT SIGNAL
FFT FOR 170MHz INPUT SIGNAL
0
−20
0
−20
SFDR = 85.1dBc
SFDR = 84.3dBc
SNR = 71.3dBFS
SINAD = 71.1dBFS
THD = 83dBc
SNR = 70.5dBFS
SINAD = 70.3dBFS
THD = 82.7dBc
−40
−40
−60
−60
−80
−80
−100
−120
−100
−120
0
5
10
15
20
25
30 32.5
0
5
10
15
20
25
30 32.5
Frequency (MHz)
Frequency (MHz)
Figure 15.
Figure 16.
FFT FOR 300MHz INPUT SIGNAL
FFT FOR TWO-TONE INPUT SIGNAL
0
−20
0
−20
SFDR = 71.9dBc
Each Tone at
−7dBFS Amplitude
fIN1 = 100MHz
fIN2 = 105MHz
SNR = 69.3dBFS
SINAD = 67.7dBFS
THD = 71.7dBc
Two−Tone IMD = 90.1dBFS
SFDR = 97.3dBFS
−40
−40
−60
−60
−80
−80
−100
−120
−100
−120
0
5
10
15
20
25
30 32.5
0
5
10
15
20
25
30 32.5
Frequency (MHz)
Frequency (MHz)
Figure 17.
Figure 18.
34
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ADS4142, ADS4145
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SBAS520A –FEBRUARY 2011–REVISED MARCH 2011
TYPICAL CHARACTERISTICS: ADS4122 (continued)
At +25°C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential clock
amplitude, 50% clock duty cycle, –1dBFS differential analog input, 0dB gain, low-latency mode, DDR LVDS output interface,
and 32k-point FFT, unless otherwise noted.
FFT FOR TWO-TONE INPUT SIGNAL
SFDR vs INPUT FREQUENCY
0
−20
88
83
78
73
68
63
58
Each Tone at
−36dBFS Amplitude
fIN1 = 100MHz
fIN2 = 105MHz
Two−Tone IMD = 99.5dBFS
SFDR = 106.9dBFS
−40
−60
−80
−100
−120
0
5
10
15
20
25
30 32.5
0
50
100
150
200
250
300
350
400
Frequency (MHz)
Input Frequency (MHz)
Figure 19.
Figure 20.
SNR vs INPUT FREQUENCY
SFDR ACROSS GAIN AND INPUT FREQUENCY
71.5
71
98
94
90
86
82
78
74
70
66
62
58
High Perf MODE1 Enabled
Default
170MHz
220MHz
300MHz
400MHz
70.5
70
69.5
69
68.5
68
67.5
0
50
100
150
200
250
300
350
400
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
Input Frequency (MHz)
Gain (dB)
Figure 21.
Figure 22.
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ADS4122, ADS4125
ADS4142, ADS4145
SBAS520A –FEBRUARY 2011–REVISED MARCH 2011
www.ti.com
TYPICAL CHARACTERISTICS: ADS4122 (continued)
At +25°C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential clock
amplitude, 50% clock duty cycle, –1dBFS differential analog input, 0dB gain, low-latency mode, DDR LVDS output interface,
and 32k-point FFT, unless otherwise noted.
PERFORMANCE ACROSS INPUT AMPLITUDE
SINAD ACROSS GAIN AND INPUT FREQUENCY
(Single Tone)
120
110
100
90
74
72
71
70
69
68
67
66
65
64
63
62
61
60
59
Input Frequency = 40MHz
SFDR (dBFS)
SFDR (dBc)
SNR
170MHz
220MHz
300MHz
400MHz
73.5
73
72.5
72
80
70
71.5
71
60
50
70.5
70
40
30
69.5
69
20
−45 −40 −35 −30 −25 −20 −15 −10
−5
0
Amplitude (dBFS)
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
Gain (dB)
Figure 23.
Figure 24.
PERFORMANCE ACROSS INPUT AMPLITUDE
(Single Tone)
PERFORMANCE vs INPUT COMMON-MODE VOLTAGE
120
110
100
90
74
94
71.5
Input Frequency = 150MHz
SFDR (dBFS)
SFDR (dBc)
SNR
Input Frequency = 150MHz
SFDR
SNR
73.5
73
90
86
82
78
74
71
72.5
72
80
70.5
70
70
71.5
71
60
50
70.5
70
40
69.5
30
69.5
69
20
69
1.1
−45 −40 −35 −30 −25 −20 −15 −10
−5
0
0.8
0.85
0.9
0.95
1
1.05
Amplitude (dBFS)
Input Common−Mode Voltage (V)
Figure 25.
Figure 26.
36
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ADS4142, ADS4145
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SBAS520A –FEBRUARY 2011–REVISED MARCH 2011
TYPICAL CHARACTERISTICS: ADS4122 (continued)
At +25°C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential clock
amplitude, 50% clock duty cycle, –1dBFS differential analog input, 0dB gain, low-latency mode, DDR LVDS output interface,
and 32k-point FFT, unless otherwise noted.
SFDR ACROSS TEMPERATURE vs AVDD SUPPLY
SNR ACROSS TEMPERATURE vs AVDD SUPPLY
100
96
92
88
84
80
76
72
68
64
60
73
72
71
70
69
68
67
Input Frequency = 150MHz
1.65
1.7
1.75
1.8
1.85
1.9
1.95
Input Frequency = 150MHz
1.65
1.7
1.75
1.8
1.85
1.9
1.95
−40
−15
10
35
60
85
−40
−15
10
35
60
85
Temperature (°C)
Temperature (°C)
Figure 27.
Figure 28.
PERFORMANCE ACROSS DRVDD SUPPLY VOLTAGE
PERFORMANCE ACROSS INPUT CLOCK AMPLITUDE
94
72
89
73
72
71
70
69
68
67
66
65
64
63
Input Frequency =150MHz
SNR
SFDR
Input Frequency = 40MHz
SFDR
SNR
88
87
86
85
84
83
82
81
80
79
92
90
88
86
84
82
71.5
71
70.5
70
69.5
69
1.65
1.7
1.75
1.8
1.85
1.9
1.95
0
0.5
1
1.5
2
2.5
3
3.5
DRVDD Supply (V)
Differential Clock Amplitude (VPP
)
Figure 29.
Figure 30.
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ADS4142, ADS4145
SBAS520A –FEBRUARY 2011–REVISED MARCH 2011
www.ti.com
TYPICAL CHARACTERISTICS: ADS4122 (continued)
At +25°C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential clock
amplitude, 50% clock duty cycle, –1dBFS differential analog input, 0dB gain, low-latency mode, DDR LVDS output interface,
and 32k-point FFT, unless otherwise noted.
PERFORMANCE ACROSS INPUT CLOCK AMPLITUDE
PERFORMANCE ACROSS INPUT CLOCK DUTY CYCLE
95
75
73
71
69
67
65
63
61
59
57
55
94
72
Input Frequency = 150MHz
SFDR
SNR
Input Frequency = 10MHz
THD
SNR
93
91
89
87
85
83
81
79
77
75
90
86
82
78
71.5
71
70.5
70
0
0.5
1
1.5
2
2.5
3
3.5
40
45
50
55
60
Input Clock Duty Cycle (%)
Differential Clock Amplitude (VPP
)
Figure 31.
Figure 32.
38
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ADS4142, ADS4145
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SBAS520A –FEBRUARY 2011–REVISED MARCH 2011
TYPICAL CHARACTERISTICS: ADS4125
At +25°C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential clock
amplitude, 50% clock duty cycle, –1dBFS differential analog input, 0dB gain, low-latency mode, DDR LVDS output interface,
and 32k-point FFT, unless otherwise noted.
FFT FOR 20MHz INPUT SIGNAL
FFT FOR 170MHz INPUT SIGNAL
0
−20
0
−20
SFDR = 86.9dBc
SFDR = 82.4dBc
SNR = 71.2dBFS
SINAD = 71dBFS
THD = 83.9dBc
SNR = 70.5dBFS
SINAD = 70.1dBFS
THD = 80.5dBc
−40
−40
−60
−60
−80
−80
−100
−120
−100
−120
0
10
20
30
40
50
60
0
10
20
30
40
50
60
Frequency (MHz)
Frequency (MHz)
Figure 33.
Figure 34.
FFT FOR 300MHz INPUT SIGNAL
FFT FOR TWO-TONE INPUT SIGNAL
0
−20
0
−20
SFDR = 79.7dBc
Each Tone at
−7dBFS Amplitude
fIN1 = 100MHz
fIN2 = 105MHz
SNR = 70dBFS
SINAD = 69.5dBFS
THD = 78.3dBc
Two−Tone IMD = 87.7dBFS
SFDR = 96.7dBFS
−40
−40
−60
−60
−80
−80
−100
−120
−100
−120
0
10
20
30
40
50
60
0
10
20
30
40
50
60
Frequency (MHz)
Frequency (MHz)
Figure 35.
Figure 36.
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ADS4122, ADS4125
ADS4142, ADS4145
SBAS520A –FEBRUARY 2011–REVISED MARCH 2011
www.ti.com
TYPICAL CHARACTERISTICS: ADS4125 (continued)
At +25°C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential clock
amplitude, 50% clock duty cycle, –1dBFS differential analog input, 0dB gain, low-latency mode, DDR LVDS output interface,
and 32k-point FFT, unless otherwise noted.
FFT FOR TWO-TONE INPUT SIGNAL
SFDR vs INPUT FREQUENCY
0
−20
90
85
80
75
70
65
60
Each Tone at
−36dBFS Amplitude
fIN1 = 100MHz
fIN2 = 105MHz
Two−Tone IMD = 99.4dBFS
SFDR = 106.3dBFS
−40
−60
−80
−100
−120
0
10
20
30
40
50
60
0
50
100
150
200
250
300
350
400
Frequency (MHz)
Input Frequency (MHz)
Figure 37.
Figure 38.
SNR vs INPUT FREQUENCY
SFDR ACROSS GAIN AND INPUT FREQUENCY
71.5
71
96
92
88
84
80
76
72
68
64
High Perf MODE1 Enabled
Default
170MHz
220MHz
300MHz
400MHz
70.5
70
69.5
69
68.5
0
50
100
150
200
250
300
350
400
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
Input Frequency (MHz)
Gain (dB)
Figure 39.
Figure 40.
40
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ADS4142, ADS4145
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SBAS520A –FEBRUARY 2011–REVISED MARCH 2011
TYPICAL CHARACTERISTICS: ADS4125 (continued)
At +25°C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential clock
amplitude, 50% clock duty cycle, –1dBFS differential analog input, 0dB gain, low-latency mode, DDR LVDS output interface,
and 32k-point FFT, unless otherwise noted.
PERFORMANCE ACROSS INPUT AMPLITUDE
SINAD ACROSS GAIN AND INPUT FREQUENCY
(Single Tone)
120
110
100
90
74
72
71
70
69
68
67
66
65
64
63
Input Frequency = 40MHz
SFDR (dBFS)
SFDR (dBc)
SNR
170MHz
220MHz
300MHz
400MHz
73.5
73
72.5
72
80
70
71.5
71
60
50
70.5
70
40
30
69.5
69
20
10
68.5
−45 −40 −35 −30 −25 −20 −15 −10
−5
0
Amplitude (dBFS)
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
Gain (dB)
Figure 41.
Figure 42.
PERFORMANCE ACROSS INPUT AMPLITUDE
(Single Tone)
PERFORMANCE vs INPUT COMMON-MODE VOLTAGE
120
110
100
90
74
90
71
Input Frequency = 150MHz
SFDR (dBFS)
SFDR (dBc)
SNR
Input Frequency = 150MHz
SFDR
SNR
73.5
73
86
82
78
74
70
70.5
70
72.5
72
80
70
71.5
71
60
69.5
69
50
70.5
70
40
30
69.5
69
20
68.5
1.1
−45 −40 −35 −30 −25 −20 −15 −10
−5
0
0.8
0.85
0.9
0.95
1
1.05
Amplitude (dBFS)
Input Common−Mode Voltage (V)
Figure 43.
Figure 44.
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ADS4142, ADS4145
SBAS520A –FEBRUARY 2011–REVISED MARCH 2011
www.ti.com
TYPICAL CHARACTERISTICS: ADS4125 (continued)
At +25°C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential clock
amplitude, 50% clock duty cycle, –1dBFS differential analog input, 0dB gain, low-latency mode, DDR LVDS output interface,
and 32k-point FFT, unless otherwise noted.
SFDR ACROSS TEMPERATURE vs AVDD SUPPLY
SNR ACROSS TEMPERATURE vs AVDD SUPPLY
100
96
92
88
84
80
76
72
68
64
60
73
72
71
70
69
68
67
Input Frequency = 150MHz
1.65
1.7
1.75
1.8
1.85
1.9
1.95
Input Frequency = 150MHz
1.65
1.7
1.75
1.8
1.85
1.9
1.95
−40
−15
10
35
60
85
−40
−15
10
35
60
85
Temperature (°C)
Temperature (°C)
Figure 45.
Figure 46.
PERFORMANCE ACROSS DRVDD SUPPLY VOLTAGE
PERFORMANCE ACROSS INPUT CLOCK AMPLITUDE
88
72
89
74
73
72
71
70
69
68
67
66
65
64
Input Frequency =150MHz
SNR
SFDR
Input Frequency = 40MHz
SFDR
SNR
88
87
86
85
84
83
82
81
80
79
86
84
82
80
78
76
71.5
71
70.5
70
69.5
69
1.65
1.7
1.75
1.8
1.85
1.9
1.95
0
0.5
1
1.5
2
2.5
3
3.5
DRVDD Supply (V)
Differential Clock Amplitude (VPP
)
Figure 47.
Figure 48.
42
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ADS4142, ADS4145
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SBAS520A –FEBRUARY 2011–REVISED MARCH 2011
TYPICAL CHARACTERISTICS: ADS4125 (continued)
At +25°C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential clock
amplitude, 50% clock duty cycle, –1dBFS differential analog input, 0dB gain, low-latency mode, DDR LVDS output interface,
and 32k-point FFT, unless otherwise noted.
PERFORMANCE ACROSS INPUT CLOCK AMPLITUDE
SNR ACROSS INPUT CLOCK DUTY CYCLE
95
73
72
71
70
69
68
67
66
65
64
63
62
73
72
71
70
69
68
67
66
65
64
63
Input Frequency = 150MHz
SFDR
SNR
Default
Low−Speed Mode Enabled
93
91
89
87
85
83
81
79
77
75
73
0
0.5
1
1.5
2
2.5
3
3.5
4
Input Frequency = 10MHz
Differential Clock Amplitude (VPP
)
30
35
40
45
50
55
60
65
70
Input Clock Duty Cycle (%)
Figure 49.
Figure 50.
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ADS4142, ADS4145
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www.ti.com
TYPICAL CHARACTERISTICS: ADS4142
At +25°C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential clock
amplitude, 50% clock duty cycle, –1dBFS differential analog input, 0dB gain, low-latency mode, DDR LVDS output interface,
and 32k-point FFT, unless otherwise noted.
FFT FOR 20MHz INPUT SIGNAL
FFT FOR 170MHz INPUT SIGNAL
0
−20
0
−20
SFDR = 83.4dBc
SFDR = 83dBc
SNR = 74.3dBFS
SINAD = 73.7dBFS
THD = 82dBc
SNR = 72.8dBFS
SINAD = 72.4dBFS
THD = 81.6dBc
−40
−40
−60
−60
−80
−80
−100
−120
−100
−120
0
5
10
15
20
25
30 32.5
0
5
10
15
20
25
30 32.5
Frequency (MHz)
Frequency (MHz)
Figure 51.
Figure 52.
FFT FOR 300MHz INPUT SIGNAL
FFT FOR TWO-TONE INPUT SIGNAL
0
−20
0
−20
SFDR = 70.7dBc
Each Tone at
−7dBFS Amplitude
fIN1 = 100MHz
fIN2 = 105MHz
SNR = 68.4dBFS
SINAD = 66.3dBFS
THD = 69.3dBc
Two−Tone IMD = 88.7dBFS
SFDR = 96.6dBFS
−40
−40
−60
−60
−80
−80
−100
−120
−100
−120
0
5
10
15
20
25
30 32.5
0
5
10
15
20
25
30 32.5
Frequency (MHz)
Frequency (MHz)
Figure 53.
Figure 54.
44
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ADS4142, ADS4145
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SBAS520A –FEBRUARY 2011–REVISED MARCH 2011
TYPICAL CHARACTERISTICS: ADS4142 (continued)
At +25°C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential clock
amplitude, 50% clock duty cycle, –1dBFS differential analog input, 0dB gain, low-latency mode, DDR LVDS output interface,
and 32k-point FFT, unless otherwise noted.
FFT FOR TWO-TONE INPUT SIGNAL
SFDR vs INPUT FREQUENCY
0
−20
93
88
83
78
73
68
63
58
Each Tone at
−36dBFS Amplitude
fIN1 = 100MHz
fIN2 = 105MHz
Two−Tone IMD = 99dBFS
SFDR = 105.3dBFS
−40
−60
−80
−100
−120
0
5
10
15
20
25
30 32.5
0
50
100
150
200
250
300
350
400
Frequency (MHz)
Input Frequency (MHz)
Figure 55.
Figure 56.
SNR vs INPUT FREQUENCY
SFDR ACROSS GAIN AND INPUT FREQUENCY
74
73.5
73
98
94
90
86
82
78
74
70
66
62
58
High Perf MODE1 Enabled
Default
170MHz
220MHz
300MHz
400MHz
72.5
72
71.5
71
70.5
70
69.5
69
0
50
100
150
200
250
300
350
400
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
Input Frequency (MHz)
Gain (dB)
Figure 57.
Figure 58.
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Product Folder Link(s): ADS4122 ADS4125 ADS4142 ADS4145
ADS4122, ADS4125
ADS4142, ADS4145
SBAS520A –FEBRUARY 2011–REVISED MARCH 2011
www.ti.com
TYPICAL CHARACTERISTICS: ADS4142 (continued)
At +25°C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential clock
amplitude, 50% clock duty cycle, –1dBFS differential analog input, 0dB gain, low-latency mode, DDR LVDS output interface,
and 32k-point FFT, unless otherwise noted.
PERFORMANCE ACROSS INPUT AMPLITUDE
SINAD ACROSS GAIN AND INPUT FREQUENCY
(Single Tone)
120
110
100
90
77
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
Input Frequency = 40MHz
SFDR (dBFS)
SFDR (dBc)
SNR
170MHz
220MHz
300MHz
400MHz
76.5
76
75.5
75
80
70
74.5
74
60
50
73.5
73
40
30
72.5
72
20
−70
−60
−50
−40
−30
−20
−10
0
Amplitude (dBFS)
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
Gain (dB)
Figure 59.
Figure 60.
PERFORMANCE ACROSS INPUT AMPLITUDE
(Single Tone)
PERFORMANCE vs INPUT COMMON-MODE VOLTAGE
120
110
100
90
77
90
74
Input Frequency = 150MHz
SFDR (dBFS)
SFDR (dBc)
SNR
Input Frequency = 150MHz
SFDR
SNR
76.5
76
86
82
78
74
70
73.5
73
75.5
75
80
70
74.5
74
60
72.5
72
50
73.5
73
40
30
72.5
72
20
−70
71.5
1.1
−60
−50
−40
−30
−20
−10
0
0.8
0.85
0.9
0.95
1
1.05
Amplitude (dBFS)
Input Common−Mode Voltage (V)
Figure 61.
Figure 62.
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TYPICAL CHARACTERISTICS: ADS4142 (continued)
At +25°C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential clock
amplitude, 50% clock duty cycle, –1dBFS differential analog input, 0dB gain, low-latency mode, DDR LVDS output interface,
and 32k-point FFT, unless otherwise noted.
SFDR ACROSS TEMPERATURE vs AVDD SUPPLY
SNR ACROSS TEMPERATURE vs AVDD SUPPLY
100
96
92
88
84
80
76
72
68
64
75
74
73
72
71
70
69
Input Frequency = 150MHz
1.65
1.7
1.75
1.8
1.85
1.9
1.95
Input Frequency = 150MHz
1.65
1.7
1.75
1.8
1.85
1.9
1.95
−40
−15
10
35
60
85
−40
−15
10
35
60
85
Temperature (°C)
Temperature (°C)
Figure 63.
Figure 64.
PERFORMANCE ACROSS DRVDD SUPPLY VOLTAGE
PERFORMANCE ACROSS INPUT CLOCK AMPLITUDE
94
74
90
76
75
74
73
72
71
70
69
68
Input Frequency =150MHz
SNR
SFDR
Input Frequency = 40MHz
SFDR
SNR
89
88
87
86
85
84
83
82
92
90
88
86
84
82
73.5
73
72.5
72
71.5
71
1.65
1.7
1.75
1.8
1.85
1.9
1.95
0
0.5
1
1.5
2
2.5
3
3.5
DRVDD Supply (V)
Differential Clock Amplitude (VPP
)
Figure 65.
Figure 66.
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TYPICAL CHARACTERISTICS: ADS4142 (continued)
At +25°C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential clock
amplitude, 50% clock duty cycle, –1dBFS differential analog input, 0dB gain, low-latency mode, DDR LVDS output interface,
and 32k-point FFT, unless otherwise noted.
PERFORMANCE ACROSS INPUT CLOCK AMPLITUDE
PERFORMANCE ACROSS INPUT CLOCK DUTY CYCLE
91
76
74
72
70
68
66
64
62
60
58
94
74.5
Input Frequency = 150MHz
SFDR
SNR
Input Frequency = 10MHz
THD
SNR
89
87
85
83
81
79
77
75
73
90
86
82
78
74
73.5
73
72.5
0
0.5
1
1.5
2
2.5
3
3.5
40
45
50
55
60
Input Clock Duty Cycle (%)
Differential Clock Amplitude (VPP
)
Figure 67.
Figure 68.
OUTPUT NOISE HISTOGRAM
(with Inputs Shorted to VCM)
INTEGRAL NONLINEARITY
50
45
40
35
30
25
20
15
10
5
1.5
1
0.5
0
−0.5
−1
−1.5
0
0
2048 4096 6144 8192 10240 12288 14336 16384
Output Code (LSB)
8168 8169 8170 8171 8172 8173 8174 8175 8176
Output Code (LSB)
Figure 69.
Figure 70.
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SBAS520A –FEBRUARY 2011–REVISED MARCH 2011
TYPICAL CHARACTERISTICS: ADS4145
At +25°C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential clock
amplitude, 50% clock duty cycle, –1dBFS differential analog input, 0dB gain, low-latency mode, DDR LVDS output interface,
and 32k-point FFT, unless otherwise noted.
FFT FOR 20MHz INPUT SIGNAL
FFT FOR 170MHz INPUT SIGNAL
0
−20
0
−20
SFDR = 86dBc
SFDR = 82.5dBc
SNR = 74dBFS
SINAD =73.7dBFS
THD = 83.5dBc
SNR = 72.8dBFS
SINAD = 72.2dBFS
THD = 80.1dBc
−40
−40
−60
−60
−80
−80
−100
−120
−100
−120
0
10
20
30
40
50
60
0
10
20
30
40
50
60
Frequency (MHz)
Frequency (MHz)
Figure 71.
Figure 72.
FFT FOR 300MHz INPUT SIGNAL
FFT FOR TWO-TONE INPUT SIGNAL
0
−20
0
−20
SFDR = 80dBc
Each Tone at
−7dBFS Amplitude
fIN1 = 100MHz
fIN2 = 105MHz
SNR = 72dBFS
SINAD = 71.3dBFS
THD = 78.5dBc
Two−Tone IMD = 87.7dBFS
SFDR = 97.5dBFS
−40
−40
−60
−60
−80
−80
−100
−120
−100
−120
0
10
20
30
40
50
60
0
10
20
30
40
50
60
Frequency (MHz)
Frequency (MHz)
Figure 73.
Figure 74.
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TYPICAL CHARACTERISTICS: ADS4145 (continued)
At +25°C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential clock
amplitude, 50% clock duty cycle, –1dBFS differential analog input, 0dB gain, low-latency mode, DDR LVDS output interface,
and 32k-point FFT, unless otherwise noted.
FFT FOR TWO-TONE INPUT SIGNAL
SFDR vs INPUT FREQUENCY
0
−20
90
85
80
75
70
65
60
Each Tone at
−36dBFS Amplitude
fIN1 = 100MHz
fIN2 = 105MHz
Two−Tone IMD = 99.2dBFS
SFDR = 106.6dBFS
−40
−60
−80
−100
−120
0
10
20
30
40
50
60
0
50
100
150
200
250
300
350
400
Frequency (MHz)
Input Frequency (MHz)
Figure 75.
Figure 76.
SNR vs INPUT FREQUENCY
SFDR ACROSS GAIN AND INPUT FREQUENCY
74
73.5
73
96
92
88
84
80
76
72
68
64
High Perf MODE1 Enabled
Default
170MHz
220MHz
300MHz
400MHz
72.5
72
71.5
71
70.5
70
0
50
100
150
200
250
300
350
400
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
Input Frequency (MHz)
Gain (dB)
Figure 77.
Figure 78.
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SBAS520A –FEBRUARY 2011–REVISED MARCH 2011
TYPICAL CHARACTERISTICS: ADS4145 (continued)
At +25°C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential clock
amplitude, 50% clock duty cycle, –1dBFS differential analog input, 0dB gain, low-latency mode, DDR LVDS output interface,
and 32k-point FFT, unless otherwise noted.
PERFORMANCE ACROSS INPUT AMPLITUDE
SINAD ACROSS GAIN AND INPUT FREQUENCY
(Single Tone)
120
110
100
90
76.5
76
74
73
72
71
70
69
68
67
66
65
64
63
62
Input Frequency = 40MHz
SFDR (dBFS)
SFDR (dBc)
SNR
170MHz
220MHz
300MHz
400MHz
75.5
75
80
74.5
74
70
60
73.5
73
50
40
72.5
72
30
−70
−60
−50
−40
−30
−20
−10
0
Amplitude (dBFS)
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
Gain (dB)
Figure 79.
Figure 80.
PERFORMANCE ACROSS INPUT AMPLITUDE
(Single Tone)
PERFORMANCE vs INPUT COMMON-MODE VOLTAGE
120
110
100
90
76.5
90
74
Input Frequency = 150MHz
SFDR (dBFS)
SFDR (dBc)
SNR
Input Frequency = 150MHz
SFDR
SNR
76
75.5
75
86
82
78
74
70
73.5
73
80
74.5
74
70
60
73.5
73
72.5
72
50
40
72.5
72
30
20
−70
71.5
71.5
1.1
−60
−50
−40
−30
−20
−10
0
0.8
0.85
0.9
0.95
1
1.05
Amplitude (dBFS)
Input Common−Mode Voltage (V)
Figure 81.
Figure 82.
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TYPICAL CHARACTERISTICS: ADS4145 (continued)
At +25°C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential clock
amplitude, 50% clock duty cycle, –1dBFS differential analog input, 0dB gain, low-latency mode, DDR LVDS output interface,
and 32k-point FFT, unless otherwise noted.
SFDR ACROSS TEMPERATURE vs AVDD SUPPLY
SNR ACROSS TEMPERATURE vs AVDD SUPPLY
100
96
92
88
84
80
76
72
68
64
60
75
74
73
72
71
70
69
Input Frequency = 150MHz
1.65
1.7
1.75
1.8
1.85
1.9
1.95
Input Frequency = 150MHz
1.65
1.7
1.75
1.8
1.85
1.9
1.95
−40
−15
10
35
60
85
−40
−15
10
35
60
85
Temperature (°C)
Temperature (°C)
Figure 83.
Figure 84.
PERFORMANCE ACROSS DRVDD SUPPLY VOLTAGE
PERFORMANCE ACROSS INPUT CLOCK AMPLITUDE
90
73
90
76
75
74
73
72
71
70
69
68
67
66
Input Frequency =150MHz
SNR
SFDR
Input Frequency = 40MHz
SFDR
SNR
89
88
87
86
85
84
83
82
81
80
88
86
84
82
80
78
72.5
72
71.5
71
70.5
70
1.65
1.7
1.75
1.8
1.85
1.9
1.95
0
0.5
1
1.5
2
2.5
3
3.5
4
DRVDD Supply (V)
Differential Clock Amplitude (VPP
)
Figure 85.
Figure 86.
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SBAS520A –FEBRUARY 2011–REVISED MARCH 2011
TYPICAL CHARACTERISTICS: ADS4145 (continued)
At +25°C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential clock
amplitude, 50% clock duty cycle, –1dBFS differential analog input, 0dB gain, low-latency mode, DDR LVDS output interface,
and 32k-point FFT, unless otherwise noted.
PERFORMANCE ACROSS INPUT CLOCK AMPLITUDE
SNR ACROSS INPUT CLOCK DUTY CYCLE
92
76
74
72
70
68
66
64
62
60
75
74
73
72
71
70
69
68
67
66
Input Frequency = 150MHz
SFDR
SNR
Default
Low−Speed Mode Enabled
89
86
83
80
77
74
71
68
0
0.5
1
1.5
2
2.5
3
3.5
4
Input Frequency = 10MHz
Differential Clock Amplitude (VPP
)
30
35
40
45
50
55
60
65
70
Input Clock Duty Cycle (%)
Figure 87.
Figure 88.
OUTPUT NOISE HISTOGRAM
(with Inputs Shorted to VCM)
INTEGRAL NONLINEARITY
35
30
25
20
15
10
5
1.5
1
0.5
0
−0.5
−1
−1.5
0
0
2048 4096 6144 8192 10240 12288 14336 16384
Output Code (LSB)
8170 8171 8172 8173 8174 8175 8176 8177 8178 8179
Output Code (LSB)
Figure 89.
Figure 90.
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TYPICAL CHARACTERISTICS: COMMON
At +25°C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential clock
amplitude, 50% clock duty cycle, –1dBFS differential analog input, 0dB gain, low-latency mode, DDR LVDS output interface,
and 32k-point FFT, unless otherwise noted.
CMRR vs FREQUENCY
PSRR vs FREQUENCY
0
−10
−20
−30
−40
−50
−60
0
−10
−20
−30
−40
−50
−60
Input Frequency = 70MHz
50mVPP Signal Superimposed
on Input Common−Mode Voltage (0.95V)
PSRR on AVDD Supply 50mVPP
0
50
100
150
200
250
300
0
10
20
30
40
50
60
70
80
90 100
Frequency of Input Common−Mode Signal (MHz)
Frequency of Signal on Supply (MHz)
Figure 91.
Figure 92.
POWER vs SAMPLE RATE
DRVDD CURRENT vs SAMPLE RATE
130
120
110
100
90
70
65
60
55
50
45
40
35
30
25
20
15
10
5
AVDD Power
DRVDD Power 200mV Swing
DRVDD Power 350mV Swing
LVDS, 200mV Swing
LVDS, 350mV Swing
CMOS, 6pF Load Capacitance
CMOS, 8pF Load Capacitance
80
70
60
50
40
30
0
5
25
45
65
85
105
125
5
25
45
65
85
105
125
Sampling Frequency (MSPS)
Sampling Frequency (MSPS)
Figure 93.
Figure 94.
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SBAS520A –FEBRUARY 2011–REVISED MARCH 2011
TYPICAL CHARACTERISTICS: CONTOUR
At +25°C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential clock
amplitude, 50% clock duty cycle, –1dBFS differential analog input, 0dB gain, low-latency mode, DDR LVDS output interface,
and 32k-point FFT, unless otherwise noted.
SFDR ACROSS INPUT AND SAMPLING FREQUENCIES (0dB Gain)
125
120
84
67
110
100
90
80
70
60
50
40
30
75
71
84
81
87
78
63
84
84
87
87
81
75
67
71
78
84
63
84
87
84
75
71
84
78
81
87
59
63
75
67
84
55
20
20
50
55
100
150
200
250
300
350
400
Input Frequency (MHz)
70
60
65
75
80
85
SFDR (dBc)
Figure 95.
SFDR ACROSS INPUT AND SAMPLING FREQUENCIES (6dB Gain)
125
120
87
87
87
87
84
110
100
90
80
70
60
50
40
30
77
90
73
81
87
90
69
84
73
77
87
69
87
87
81
73
81
87
50
77
65
69
84
87
61
20
20
100
65
150
200
250
300
350
400
90
Input Frequency (MHz)
75
60
70
80
85
SFDR (dBc)
Figure 96.
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TYPICAL CHARACTERISTICS: CONTOUR (continued)
At +25°C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential clock
amplitude, 50% clock duty cycle, –1dBFS differential analog input, 0dB gain, low-latency mode, DDR LVDS output interface,
and 32k-point FFT, unless otherwise noted.
ADS414x: SNR ACROSS INPUT AND SAMPLING FREQUENCIES (0dB Gain)
125
120
73
72.5
72
73.5
110
100
90
80
70
60
50
40
30
71
70
72
72.5
73
73.5
71
69
70
69
72
68
72.5
70
71
73.5
50
67
69
68
300
73
66
20
20
100
67
150
68
200
250
350
400
Input Frequency (MHz)
66
69
70
71
72
73
SNR (dBFS)
Figure 97.
ADS414x: SNR ACROSS INPUT AND SAMPLING FREQUENCIES (6dB Gain)
125
120
67.5
67
110
100
90
80
70
60
50
40
30
67
68
67.5
66.5
67
66.5
66
67
67.5
68
66.5
65.5
65
66
300
20
20
64
50
100
150
200
250
350
400
68
Input Frequency (MHz)
66 66.5
64.5
65
65.5
67
67.5
SNR (dBFS)
Figure 98.
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SBAS520A –FEBRUARY 2011–REVISED MARCH 2011
TYPICAL CHARACTERISTICS: CONTOUR (continued)
At +25°C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential clock
amplitude, 50% clock duty cycle, –1dBFS differential analog input, 0dB gain, low-latency mode, DDR LVDS output interface,
and 32k-point FFT, unless otherwise noted.
ADS412x SNR ACROSS INPUT AND SAMPLING FREQUENCIES (0dB Gain)
125
120
70.5
71
70
110
100
90
80
70
60
50
40
30
69.5
69
69.5
69
70.5
71
70
68
69.5
69
67
66
68
70
70.5
100
71
65
67
20
20
50
150
200
250
300
350
400
71
Input Frequency (MHz)
68
66
67
69
70
SNR (dBFS)
Figure 99.
ADS412x SNR ACROSS INPUT AND SAMPLING FREQUENCIES (6dB Gain)
125
120
66.5
110
100
90
80
70
60
50
40
30
67
67
66
66.5
65.5
66
65.5
300
65
67
66.5
66
64.5
64
20
20
50
100
150
200
250
350
400
Input Frequency (MHz)
65.5
64
64.5
65
66
66.5
67
SNR (dBFS)
Figure 100.
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APPLICATION INFORMATION
THEORY OF OPERATION
The ADS412x/4x are lower sampling speed members of the ADS41xx family of ultralow power analog-to-digital
converters (ADCs). The conversion process is initiated by a rising edge of the external input clock and the analog
input signal is sampled. The sampled signal is sequentially converted by a series of small resolution stages, with
the outputs combined in a digital correction logic block. At every clock edge the sample propagates through the
pipeline, resulting in a data latency of 10 clock cycles. The output is available as 14-bit data or 12-bit data, in
DDR LVDS mode or CMOS mode, and coded in either straight offset binary or binary twos complement format.
ANALOG INPUT
The analog input consists of a switched-capacitor-based, differential, sample-and-hold architecture. This
differential topology results in very good ac performance even for high input frequencies at high sampling rates.
The INP and INM pins must be externally biased around a common-mode voltage of 0.95V, available on the
VCM pin. For a full-scale differential input, each input INP and INM pin must swing symmetrically between (VCM
+ 0.5V) and (VCM – 0.5V), resulting in a 2VPP differential input swing. The input sampling circuit has a high 3dB
bandwidth that extends up to 550MHz (measured from the input pins to the sampled voltage). Figure 101 shows
an equivalent circuit for the analog input.
Sampling
Switch
LPKG
Sampling
Capacitor
2nH
10W
RCR Filter
INP
RON
CBOND
1pF
CPAR2
1pF
CSAMP
2pF
100W
15W
RESR
3pF
200W
CPAR1
0.5pF
RON
15W
3pF
LPKG
2nH
CSAMP
2pF
100W
RON
15W
INM
CBOND
1pF
CPAR2
1pF
Sampling
Capacitor
RESR
Sampling
Switch
200W
Figure 101. Analog Input Equivalent Circuit
Drive Circuit Requirements
For optimum performance, the analog inputs must be driven differentially. This technique improves the
common-mode noise immunity and even-order harmonic rejection. A 5Ω to 15Ω resistor in series with each input
pin is recommended to damp out ringing caused by package parasitics. It is also necessary to present low
impedance (less than 50Ω) for the common-mode switching currents. This impedance can be achieved by using
two resistors from each input terminated to the common-mode voltage (VCM).
Note that the device includes an internal R-C filter from each input to ground. The purpose of this filter is to
absorb the glitches caused by the opening and closing of the sampling capacitors. The cutoff frequency of the
R-C filter involves a trade-off. A lower cutoff frequency (larger C) absorbs glitches better, but also reduces the
input bandwidth and the maximum input frequency that can be supported. On the other hand, with no internal
R-C filter, high input frequency can be supported but now the sampling glitches must be supplied by the external
driving circuit. The inductance of the package bond wires limits the ability of the external driving circuit to support
the sampling glitches.
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In the ADS412x/4x, the R-C component values have been optimized while supporting high input bandwidth
(550MHz). However, in applications where very high input frequency support is not required, filtering of the
glitches can be improved further with an external R-C-R filter; see Figure 104 and Figure 105).
In addition, the drive circuit may have to be designed to provide a low insertion loss over the desired frequency
range and matched impedance to the source. While designing the drive circuit, the ADC impedance must be
considered. Figure 102 and Figure 103 show the impedance (ZIN = RIN || CIN) looking into the ADC input pins.
100.00
10.00
1.00
0.10
0.01
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
Input Frequency (GHz)
Figure 102. ADC Analog Input Resistance (RIN) Across Frequency
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
Input Frequency (GHz)
Figure 103. ADC Analog Input Capacitance (CIN) Across Frequency
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Driving Circuit
Two example driving circuit configurations are shown in Figure 104 and Figure 105—one optimized for low
bandwidth (tlow input frequencies) and the other one for high bandwidth to support higher input frequencies. In
Figure 104, an external R-C-R filter with 3.3pF is used to help absorb sampling glitches. The R-C-R filter limits
the bandwidth of the drive circuit, making it suitable for low input frequencies (up to 250MHz). Transformers such
as ADT1-1WT or WBC1-1 can be used up to 250MHz.
For higher input frequencies, the R-C-R filter can be dropped. Together with the lower series resistors (5Ω to
10Ω), this drive circuit provides higher bandwidth to support frequencies up to 500MHz (as shown in Figure 105).
A transmission line transformer such as ADTL2-18 can be used.
Note that both the drive circuits have been terminated by 50Ω near the ADC side. The termination is
accomplished by a 25Ω resistor from each input to the 0.95V common-mode (VCM) from the device. This
termination allows the analog inputs to be biased around the required common-mode voltage.
3.6nH
10W to 15W
INP
T2
T1
0.1mF
25W
25W
50W
0.1mF
RIN
CIN
3.3pF
50W
INM
VCM
1:1
1:1
10W to 15W
3.6nH
ADS41xx
Figure 104. Drive Circuit with Low Bandwidth (for Low Input Frequencies)
5W to 10W
INP
T2
T1
0.1mF
25W
25W
0.1mF
RIN
CIN
INM
1:1
1:1
5W to 10W
VCM
ADS41xx
Figure 105. Drive Circuit with High Bandwidth (for High Input Frequencies)
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The mismatch in the transformer parasitic capacitance (between the windings) results in degraded even-order
harmonic performance. Connecting two identical RF transformers back-to-back helps minimize this mismatch and
good performance is obtained for high-frequency input signals. An additional termination resistor pair may be
required between the two transformers, as shown in Figure 104 and Figure 105. The center point of this
termination is connected to ground to improve the balance between the P (positive) and M (negative) sides. The
values of the terminations between the transformers and on the secondary side must be chosen to obtain an
effective 50Ω (for a 50Ω source impedance).
Figure 104 and Figure 105 use 1:1 transformers with a 50Ω source. As explained in the Drive Circuit
Requirements section, this architecture helps to present a low source impedance to absorb sampling glitches.
With a 1:4 transformer, the source impedance is 200Ω. The higher source impedance is unable to absorb the
sampling glitches effectively and can lead to degradation in performance (compared to using 1:1 transformers).
In almost all cases, either a bandpass or low-pass filter is needed to obtain the desired dynamic performance, as
shown in Figure 106. Such a filter presents low source impedance at the high frequencies corresponding to the
sampling glitch and helps avoid the performance loss with the high source impedance.
10W
INP
100W
0.1mF
Bandpass or
Low-Pass
Filter
Differential
Input Signal
ADS41xx
100W
INM
10W
VCM
Figure 106. Drive Circuit with 1:4 Transformer
Input Common-Mode
To ensure a low-noise, common-mode reference, the VCM pin is filtered with a 0.1µF low-inductance capacitor
connected to ground. The VCM pin is designed to directly drive the ADC inputs. Each ADC input pin sinks a
common-mode current of approximately 0.6µA per MSPS of clock frequency.
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CLOCK INPUT
The ADS412x/4x clock inputs can be driven differentially (sine, LVPECL, or LVDS) or single-ended (LVCMOS),
with little or no difference in performance between them. The common-mode voltage of the clock inputs is set to
VCM using internal 5kΩ resistors. This setting allows the use of transformer-coupled drive circuits for sine-wave
clock or ac-coupling for LVPECL and LVDS clock sources. Figure 107 shows an equivalent circuit for the input
clock.
Clock Buffer
LPKG
1nH
20W
CLKP
CBOND
CEQ
CEQ
5kW
1pF
RESR
100W
2pF
VCM
LPKG
1nH
5kW
20W
CLKM
CBOND
1pF
RESR
100W
NOTE: CEQ is 1pF to 3pF and is the equivalent input capacitance of the clock buffer.
Figure 107. Input Clock Equivalent Circuit
A single-ended CMOS clock can be ac-coupled to the CLKP input, with CLKM connected to ground with a 0.1μF
capacitor, as shown in Figure 108. For best performance, the clock inputs must be driven differentially, reducing
susceptibility to common-mode noise. For high input frequency sampling, it is recommended to use a clock
source with very low jitter. Band-pass filtering of the clock source can help reduce the effects of jitter. There is no
change in performance with a non-50% duty cycle clock input. Figure 109 shows a differential circuit.
0.1mF
CMOS
0.1mF
CLKP
Clock Input
CLKP
Differential Sine-Wave,
PECL, or LVDS
Clock Input
VCM
0.1mF
0.1mF
CLKM
CLKM
Figure 108. Single-Ended Clock Driving Circuit
Figure 109. Differential Clock Driving Circuit
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DIGITAL FUNCTIONS AND LOW LATENCY MODE
The device has several useful digital functions such as test patterns, gain, and offset correction. All of these
functions require extra clock cycles for operation and increase the overall latency and power of the device.
Alternately, the device has a low-latency mode in which the raw ADC output is routed to the output data pins with
a latency of 10 clock cycles. In this mode, the digital functions are bypassed. Figure 110 shows more details of
the processing after the ADC.
The device is in low-latency mode after reset. In order to use any of the digital functions, the low-latency mode
must first be disabled by setting the DIS LOW LATENCY register bit to '1'. After this, the respective register bits
must be programmed as described in the following sections and in the Serial Register Map section.
Output
Interface
14-Bit
ADC
14b
14b
Digital Functions
(Gain, Offset Correction, Test Patterns)
DDR LVDS
or CMOS
DIS LOW LATENCY Pin
Figure 110. Digital Processing Block Diagram
GAIN FOR SFDR/SNR TRADE-OFF
The ADS412x/4x include gain settings that can be used to improve SFDR performance. The gain is
programmable from 0dB to 6dB (in 0.5dB steps) using the GAIN register bits. For each gain setting, the analog
input full-scale range scales proportionally, as shown in Table 9.
The SFDR improvement is achieved at the expense of SNR; for each gain setting, the SNR degrades
approximately between 0.5dB and 1dB. The SNR degradation is reduced at high input frequencies. As a result,
the gain is very useful at high input frequencies because the SFDR improvement is significant with marginal
degradation in SNR. Therefore, the gain can be used to trade-off between SFDR and SNR.
After a reset, the device is in low-latency mode and gain function is disabled. To use gain:
•
•
•
First, disable the low-latency mode (DIS LOW LATENCY = 1).
This setting enables the gain and puts the device in a 0dB gain mode.
For other gain settings, program the GAIN bits.
Table 9. Full-Scale Range Across Gains
GAIN (dB)
TYPE
FULL-SCALE (VPP)
0
1
2
3
4
5
6
Default after reset
Programmable
Programmable
Programmable
Programmable
Programmable
Programmable
2
1.78
1.59
1.42
1.26
1.12
1.00
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OFFSET CORRECTION
The ADS412x/4x has an internal offset corretion algorithm that estimates and corrects dc offset up to ±10mV.
The correction can be enabled using the EN OFFSET CORR serial register bit. Once enabled, the algorithm
estimates the channel offset and applies the correction every clock cycle. The time constant of the correction
loop is a function of the sampling clock frequency. The time constant can be controlled using the OFFSET CORR
TIME CONSTANT register bits, as described in Table 10.
Table 10. Time Constant of Offset Correction Loop
TIME CONSTANT, TCCLK
(Number of Clock Cycles)
OFFSET CORR TIME CONSTANT
TIME CONSTANT, TCCLK × 1/fS (sec)(1)
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
1M
2M
8ms
16ms
33.4ms
67ms
134ms
268ms
537ms
1.08s
2.15s
4.3s
4M
8M
16M
32M
64M
128M
256M
512M
1G
8.6s
2G
17.2s
—
Reserved
Reserved
Reserved
Reserved
—
—
—
(1) Sampling frequency, fS = 125MSPS.
After the offset is estimated, the correction can be frozen by setting FREEZE OFFSET CORR = 1. Once frozen,
the last estimated value is used for the offset correction of every clock cycle. Note that offset correction is
disabled by a default after reset.
After a reset, the device is in low-latency mode and offset correction is disabled. To use offset correction:
•
•
First, disable the low-latency mode (DIS LOW LATENCY = 1).
Then set EN OFFSET CORR to '1' and program the required time constant.
Figure 111 shows the time response of the offset correction algorithm after it is enabled.
OFFSET CORRECTION
Time Response
8200
8190
8181
Offset of
10 LSBs
8192
8180
8170
8160
8150
8140
8130
8120
8110
8100
8090
8080
8070
8060
8050
Final converged value
Offset correction
converges to output
code of 8192
Offset correction
begins
-5
5
15 25 35 45 55 65 75 85 95 105
Time (ms)
Figure 111. Time Response of Offset Correction
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POWER DOWN
The ADS412x/4x has three power-down modes: power-down global, standby, and output buffer disable.
Power-Down Global
In this mode, the entire chip (including the ADC, internal reference, and the output buffers) are powered down,
resulting in reduced total power dissipation of about 10mW. The output buffers are in a high-impedance state.
The wake-up time from the global power-down to data becoming valid in normal mode is typically 100µs. To
enter the global power-down mode, set the PDN GLOBAL register bit.
Standby
In this mode, only the ADC is powered down and the internal references are active, resulting in a fast wake-up
time of 5µs. The total power dissipation in standby mode is approximately 130mW at 125MSPS. To enter the
standby mode, set the STBY register bit.
Output Buffer Disable
The output buffers can be disabled and put in a high-impedance state; wakeup time from this mode is fast,
approximately 100ns. This can be controlled using the PDN OBUF register bit or using the OE pin.
Input Clock Stop
In addition, the converter enters a low-power mode when the input clock frequency falls below 1MSPS. The
power dissipation is approximately 80mW.
POWER-SUPPLY SEQUENCE
During power-up, the AVDD and DRVDD supplies can come up in any sequence. The two supplies are
separated in the device. Externally, they can be driven from separate supplies or from a single supply.
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DIGITAL OUTPUT INFORMATION
The ADS412x/4x provide either 14-bit data or 12-bit data, respectively, and an output clock synchronized with the
data.
Output Interface
Two output interface options are available: double data rate (DDR) LVDS and parallel CMOS. They can be
selected using the LVDS CMOS serial interface register bit or using the DFS pin.
DDR LVDS Outputs
In this mode, the data bits and clock are output using low voltage differential signal (LVDS) levels. Two data bits
are multiplexed and output on each LVDS differential pair, as shown in Figure 112 and Figure 113.
Pins
Pins
CLKOUTP
Output Clock
CLKOUTP
CLKOUTM
Output Clock
CLKOUTM
D0_D1_P
D0_D1_M
Data Bits D0, D1
Data Bits D2, D3
Data Bits D4, D5
Data Bits D6, D7
Data Bits D8, D9
Data Bits D10, D11
D0_D1_P
D0_D1_M
Data Bits D0, D1
Data Bits D2, D3
Data Bits D4, D5
Data Bits D6, D7
Data Bits D8, D9
Data Bits D10, D11
Data Bits D12, D13
D2_D3_P
D2_D3_M
D2_D3_P
D2_D3_M
D4_D5_P
D4_D5_M
D4_D5_P
D4_D5_M
12-Bit
ADC Data
14-Bit
ADC Data
D6_D7_P
D6_D7_M
D6_D7_P
D6_D7_M
D8_D9_P
D8_D9_M
D8_D9_P
D8_D9_M
D10_D11_P
D10_D11_M
D10_D11_P
D10_D11_M
ADS412x
D12_D13_P
D12_D13_M
Figure 112. ADS412x LVDS Data Outputs
ADS414x
Figure 113. ADS414x LVDS Data Outputs
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Even data bits (D0, D2, D4, etc.) are output at the falling edge of CLKOUTP and the odd data bits (D1, D3, D5,
etc.) are output at the rising edge of CLKOUTP. Both the rising and falling edges of CLKOUTP must be used to
capture all 14 data bits, as shown in Figure 114.
CLKOUTP
CLKOUTM
D0_D1_P,
D0_D1_M
D0
D2
D4
D1
D3
D5
D0
D2
D4
D1
D3
D5
D2_D3_P,
D2_D3_M
D4_D5_P,
D4_D5_M
D6_D7_P,
D6_D7_M
D6
D8
D7
D9
D6
D8
D7
D9
D8_D9_P,
D8_D9_M
D10_D11_P,
D10_D11_M
D10
D11
D10
D11
D12_D13_P,
D12_D13_M
D12
D13
D12
D13
Sample N
Sample N + 1
Figure 114. DDR LVDS Interface
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LVDS Output Data and Clock Buffers
The equivalent circuit of each LVDS output buffer is shown in Figure 115. After reset, the buffer presents an
output impedance of 100Ω to match with the external 100Ω termination.
The VDIFF voltage is nominally 350mV, resulting in an output swing of ±350mV with 100Ω external termination.
The VDIFF voltage is programmable using the LVDS SWING register bits from ±125mV to ±570mV.
Additionally, a mode exists to double the strength of the LVDS buffer to support 50Ω differential termination. This
mode can be used when the output LVDS signal is routed to two separate receiver chips, each using a 100Ω
termination. The mode can be enabled using the LVDS DATA STRENGTH and LVDS CLKOUT STRENGTH
register bits for data and output clock buffers, respectively.
The buffer output impedance behaves in the same way as a source-side series termination. By absorbing
reflections from the receiver end, it helps to improve signal integrity.
VDIFF
High
Low
OUTP
OUTM
External
100W Load
1.1V
ROUT
VDIFF
High
Low
NOTE: Use the default buffer strength to match 100Ω external termination (ROUT = 100Ω). To match with a 50Ω external termination, set the
LVDS STRENGTH bit (ROUT = 50Ω).
Figure 115. LVDS Buffer Equivalent Circuit
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Parallel CMOS Interface
In CMOS mode, each data bit is output on a separate pin as the CMOS voltage level, for every clock cycle. The
rising edge of the output clock CLKOUT can be used to latch data in the receiver. Figure 116 depicts the CMOS
output interface.
Switching noise (caused by CMOS output data transitions) can couple into the analog inputs and degrade SNR.
The coupling and SNR degradation increases as the output buffer drive is made stronger. To minimize this
degradation, the CMOS output buffers are designed with controlled drive strength. The default drive strength
ensures a wide data stable window. It is recommended to use short traces (one to two inches or 2,54cm to
5,08cm) terminated with less than 5pF load capacitance, as shown in Figure 117.
Pins
OVR
CLKOUT
D0
D1
D2
D3
14-Bit
ADC Data
D11
D12
D13
ADS414x
Figure 116. CMOS Output Interface
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Use External Clock Buffer
(> 200MSPS)
Input Clock
Receiver (FPGA, ASIC, etc.)
Flip-Flops
CLKOUT
CLKIN
D0
D1
D2
D0_In
D1_In
D2_In
14-Bit ADC Data
D12
D13
D12_In
D13_In
ADS414x
Use short traces between
ADC output and receiver pins (1 to 2 inches).
Figure 117. Using the CMOS Data Outputs
CMOS Interface Power Dissipation
With CMOS outputs, the DRVDD current scales with the sampling frequency and the load capacitance on every
output pin. The maximum DRVDD current occurs when each output bit toggles between '0' and '1' every clock
cycle. In actual applications, this condition is unlikely to occur. The actual DRVDD current would be determined
by the average number of output bits switching, which is a function of the sampling frequency and the nature of
the analog input signal.
Digital Current as a Result of CMOS Output Switching = CL × DRVDD × (N × fAVG
)
where:
CL = load capacitance,
N × FAVG = average number of output bits switching.
(1)
Figure 94 details the current across sampling frequencies at 2 MHz analog input frequency.
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Input Over-Voltage Indication (OVR Pin)
The device has an OVR pin that provides information about analog input overload. At any clock cycle, if the
sampled input voltage exceeds the positive or negative full-scale range, the OVR pin goes high. The OVR
remains high as long as the overload condition persists. The OVR pin is a CMOS output buffer (running off
DRVDD supply), independent of the type of output data interface (DDR LVDS or CMOS).
For a positive overload, the D[13:0] output data bits are 3FFFh in offset binary output format and 1FFFh in twos
complement output format. For a negative input overload, the output code is 0000h in offset binary output format
and 2000h in twos complement output format.
Output Data Format
Two output data formats are supported: twos complement and offset binary. Each mode can be selected using
the DATA FORMAT serial interface register bit or controlling the DFS pin in parallel configuration mode. In the
event of an input voltage overdrive, the digital outputs go to the appropriate full-scale level.
BOARD DESIGN CONSIDERATIONS
Grounding
A single ground plane is sufficient to give good performance, provided the analog, digital, and clock sections of
the board are cleanly partitioned. See the ADS414x, ADS412x EVM User Guide (SLWU067) for details on layout
and grounding.
Supply Decoupling
Because the ADS412x/4x already include internal decoupling, minimal external decoupling can be used without
loss in performance. Note that decoupling capacitors can help filter external power-supply noise, so the optimum
number of capacitors depends on the actual application. The decoupling capacitors should be placed very close
to the converter supply pins.
Exposed Pad
In addition to providing a path for heat dissipation, the PowerPAD is also electrically internally connected to the
digital ground. Therefore, it is necessary to solder the exposed pad to the ground plane for best thermal and
electrical performance. For detailed information, see application notes QFN Layout Guidelines (SLOA122) and
QFN/SON PCB Attachment (SLUA271), both available for download at the TI web site (www.ti.com).
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DEFINITION OF SPECIFICATIONS
Analog Bandwidth – The analog input frequency at which the power of the fundamental is reduced by 3 dB with
respect to the low-frequency value.
Aperture Delay – The delay in time between the rising edge of the input sampling clock and the actual time at
which the sampling occurs. This delay is different across channels. The maximum variation is specified as
aperture delay variation (channel-to-channel).
Aperture Uncertainty (Jitter) – The sample-to-sample variation in aperture delay.
Clock Pulse Width/Duty Cycle – The duty cycle of a clock signal is the ratio of the time the clock signal remains
at a logic high (clock pulse width) to the period of the clock signal. Duty cycle is typically expressed as a
percentage. A perfect differential sine-wave clock results in a 50% duty cycle.
Maximum Conversion Rate – The maximum sampling rate at which specified operation is given. All parametric
testing is performed at this sampling rate unless otherwise noted.
Minimum Conversion Rate – The minimum sampling rate at which the ADC functions.
Differential Nonlinearity (DNL) – An ideal ADC exhibits code transitions at analog input values spaced exactly
1 LSB apart. The DNL is the deviation of any single step from this ideal value, measured in units of LSBs.
Integral Nonlinearity (INL) – The INL is the deviation of the ADC transfer function from a best fit line determined
by a least squares curve fit of that transfer function, measured in units of LSBs.
Gain Error – Gain error is the deviation of the ADC actual input full-scale range from its ideal value. The gain
error is given as a percentage of the ideal input full-scale range. Gain error has two components: error as a
result of reference inaccuracy and error as a result of the channel. Both errors are specified independently as
EGREF and EGCHAN
To a first-order approximation, the total gain error is ETOTAL ~ EGREF + EGCHAN
For example, if ETOTAL = ±0.5%, the full-scale input varies from (1 – 0.5/100) x FSideal to (1 + 0.5/100) x FSideal
.
.
.
Offset Error – The offset error is the difference, given in number of LSBs, between the ADC actual average idle
channel output code and the ideal average idle channel output code. This quantity is often mapped into millivolts.
Temperature Drift – The temperature drift coefficient (with respect to gain error and offset error) specifies the
change per degree Celsius of the parameter from TMIN to TMAX. It is calculated by dividing the maximum deviation
of the parameter across the TMIN to TMAX range by the difference TMAX – TMIN
.
Signal-to-Noise Ratio – SNR is the ratio of the power of the fundamental (PS) to the noise floor power (PN),
excluding the power at dc and the first nine harmonics.
PS
SNR = 10Log10
PN
(2)
SNR is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the
reference, or dBFS (dB to full-scale) when the power of the fundamental is extrapolated to the converter
full-scale range.
Signal-to-Noise and Distortion (SINAD) – SINAD is the ratio of the power of the fundamental (PS) to the power
of all the other spectral components including noise (PN) and distortion (PD), but excluding dc.
PS
SINAD = 10Log10
PN + PD
(3)
SINAD is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the
reference, or dBFS (dB to full-scale) when the power of the fundamental is extrapolated to the converter
full-scale range.
72
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Copyright © 2011, Texas Instruments Incorporated
Product Folder Link(s): ADS4122 ADS4125 ADS4142 ADS4145
ADS4122, ADS4125
ADS4142, ADS4145
www.ti.com
SBAS520A –FEBRUARY 2011–REVISED MARCH 2011
Effective Number of Bits (ENOB) – ENOB is a measure of the converter performance as compared to the
theoretical limit based on quantization noise.
SINAD - 1.76
ENOB =
6.02
(4)
Total Harmonic Distortion (THD) – THD is the ratio of the power of the fundamental (PS) to the power of the
first nine harmonics (PD).
PS
THD = 10Log10
PN
(5)
THD is typically given in units of dBc (dB to carrier).
Spurious-Free Dynamic Range (SFDR) – The ratio of the power of the fundamental to the highest other
spectral component (either spur or harmonic). SFDR is typically given in units of dBc (dB to carrier).
Two-Tone Intermodulation Distortion – IMD3 is the ratio of the power of the fundamental (at frequencies f1
and f2) to the power of the worst spectral component at either frequency 2f1 – f2 or 2f2 – f1. IMD3 is either given
in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the reference, or dBFS (dB
to full-scale) when the power of the fundamental is extrapolated to the converter full-scale range.
DC Power-Supply Rejection Ratio (DC PSRR) – DC PSSR is the ratio of the change in offset error to a change
in analog supply voltage. The dc PSRR is typically given in units of mV/V.
AC Power-Supply Rejection Ratio (AC PSRR) – AC PSRR is the measure of rejection of variations in the
supply voltage by the ADC. If ΔVSUP is the change in supply voltage and ΔVOUT is the resultant change of the
ADC output code (referred to the input), then:
DVOUT
PSRR = 20Log10
(Expressed in dBc)
DVSUP
(6)
Voltage Overload Recovery – The number of clock cycles taken to recover to less than 1% error after an
overload on the analog inputs. This is tested by separately applying a sine wave signal with 6dB positive and
negative overload. The deviation of the first few samples after the overload (from the expected values) is noted.
Common-Mode Rejection Ratio (CMRR) – CMRR is the measure of rejection of variation in the analog input
common-mode by the ADC. If ΔVCM_IN is the change in the common-mode voltage of the input pins and ΔVOUT is
the resulting change of the ADC output code (referred to the input), then:
DVOUT
10
CMRR = 20Log
(Expressed in dBc)
DVCM
(7)
Crosstalk (only for multi-channel ADCs) – This is a measure of the internal coupling of a signal from an
adjacent channel into the channel of interest. It is specified separately for coupling from the immediate
neighboring channel (near-channel) and for coupling from channel across the package (far-channel). It is usually
measured by applying a full-scale signal in the adjacent channel. Crosstalk is the ratio of the power of the
coupling signal (as measured at the output of the channel of interest) to the power of the signal applied at the
adjacent channel input. It is typically expressed in dBc.
Copyright © 2011, Texas Instruments Incorporated
Submit Documentation Feedback
73
Product Folder Link(s): ADS4122 ADS4125 ADS4142 ADS4145
PACKAGE OPTION ADDENDUM
www.ti.com
26-Mar-2011
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
ADS4122IRGZR
ADS4122IRGZT
ADS4125IRGZR
ADS4125IRGZT
ADS4142IRGZR
ADS4142IRGZT
ADS4145IRGZ25
ADS4145IRGZR
ADS4145IRGZT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
RGZ
RGZ
RGZ
RGZ
RGZ
RGZ
RGZ
RGZ
RGZ
48
48
48
48
48
48
48
48
48
2500
250
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
CU NIPDAU Level-3-260C-168 HR
CU NIPDAU Level-3-260C-168 HR
CU NIPDAU Level-3-260C-168 HR
CU NIPDAU Level-3-260C-168 HR
CU NIPDAU Level-3-260C-168 HR
CU NIPDAU Level-3-260C-168 HR
CU NIPDAU Level-3-260C-168 HR
2500
250
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
2500
250
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
25
Green (RoHS
& no Sb/Br)
2500
250
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
26-Mar-2011
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Mar-2011
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
ADS4122IRGZR
ADS4122IRGZT
ADS4125IRGZR
ADS4125IRGZT
ADS4142IRGZR
ADS4142IRGZT
ADS4145IRGZR
ADS4145IRGZT
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
RGZ
RGZ
RGZ
RGZ
RGZ
RGZ
RGZ
RGZ
48
48
48
48
48
48
48
48
2500
250
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
16.4
16.4
16.4
16.4
16.4
16.4
16.4
16.4
7.3
7.3
7.3
7.3
7.3
7.3
7.3
7.3
7.3
7.3
7.3
7.3
7.3
7.3
7.3
7.3
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
16.0
16.0
16.0
16.0
16.0
16.0
16.0
16.0
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
2500
250
2500
250
2500
250
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Mar-2011
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
ADS4122IRGZR
ADS4122IRGZT
ADS4125IRGZR
ADS4125IRGZT
ADS4142IRGZR
ADS4142IRGZT
ADS4145IRGZR
ADS4145IRGZT
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
RGZ
RGZ
RGZ
RGZ
RGZ
RGZ
RGZ
RGZ
48
48
48
48
48
48
48
48
2500
250
333.2
333.2
333.2
333.2
333.2
333.2
333.2
333.2
345.9
345.9
345.9
345.9
345.9
345.9
345.9
345.9
28.6
28.6
28.6
28.6
28.6
28.6
28.6
28.6
2500
250
2500
250
2500
250
Pack Materials-Page 2
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