ADS4245-EP [TI]
双通道、14 位、125MSPS 模数转换器 (ADC) - 增强型产品;
| 型号： | ADS4245-EP |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 双通道、14 位、125MSPS 模数转换器 (ADC) - 增强型产品 转换器 模数转换器 |
| 文件： | 总61页 (文件大小：3033K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ADS4245-EP
ZHCSCA6B – APRIL 2014 – REVISED OCTOBER 2020
ADS4245-EP 双通道，14 位，125MSPS 超低功率模数转换器 (ADC)
1 特性
3 说明
•
超低功耗，采用 1.8V 单电源供电：
CMOS 输出：
– 125MSPS 时总体功耗 277mW
ADS4245 是 ADS42xx 双通道 14 位模数转换器 (ADC)
超低功耗系列产品的一款低速型号。采用创新设计技术
实现高动态性能，同时在由 1.8V 电源供电时功耗极
低。该拓扑结构使得 ADS4245 非常适合多载波、宽带
宽通信应用。
•
高动态性能：
– 170MHz 时无杂散动态范围 (SFDR) 为 88dBc
– 170MHz 时信噪比 (SNR) 为 71.4dBFS
串扰：185MHz 时大于 90dB
高达 6dB 的可编程增益支持
SNR/SFDR 平衡
ADS4245 具有可被用于在较低满量程输入范围内改进
SFDR 性能的增益选项。这个器件还包括一个直流偏移
校正环路，此环路可被用于消除 ADC 偏移。DDR（双
倍数据速率）LVDS 与并行 CMOS 数字输出接口都采
用紧凑型 QFN-64 PowerPAD™ 封装。
•
•
•
•
直流偏移校正
此器件包含内部基准，而删除了传统基准引脚和相关的
去耦合电容器。ADS4245 可在军用温度范围（-55°C
至 125°C）内额定运行。
输出接口选项：
– 1.8V 并行 CMOS 接口
– 支持可编程摆幅的双倍数据速率 (DDR) 低压差
分信令 (LVDS)：
器件信息
封装(1)
•
标准摆幅：350mV
低摆幅：200mV
订货编号
封装尺寸
9mm x 9mm
ADS4245MRGC25EP VQFN (64)
•
•
•
支持低至 200mVPP 的低输入时钟幅度
支持国防、航天和医疗应用
– 受控基线
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
AVDD
AGND
DRVDD DRGND
LVDS Interface
– 同一组装和测试场所
– 同一制造场所
DA0P
DA0M
DA2P
DA2M
DA4P
– 支持军用（-55°C 至 125°C）温度范围
– 延长的产品生命周期
– 延长的产品变更通知
– 产品可追溯性
INP_A
INM_A
Digital and
DDR
Serializer
DA4M
DA6P
Sampling
Circuit
14-Bit
ADC
DA6M
DA8P
DA8M
DA10P
DA10M
DA12P
DA12M
CLKP
CLKM
CLKOUTP
CLKOUTM
2 应用
Output
Clock Buffer
CLOCKGEN
DB0P
•
•
•
无线通信基础设施
DB0M
DB2P
由软件定义的无线电
功率放大器线性化
DB2M
DB4P
INP_B
INM_B
Digital and
DDR
Serializer
DB4M
DB6P
Sampling
Circuit
14-Bit
ADC
DB6M
DB8P
DB8M
DB10P
DB10M
DB12P
DB12M
Control
Interface
VCM
Reference
SDOUT
ADS424x
方框图
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SBAS653
ADS4245-EP
ZHCSCA6B – APRIL 2014 – REVISED OCTOBER 2020
www.ti.com.cn
Table of Contents
7.2 Functional Block Diagram.........................................23
7.3 Feature Description...................................................24
7.4 Device Functional Modes..........................................24
7.5 Serial Register Map.................................................. 37
7.6 Description Of Serial Registers.................................38
8 Application and Implementation..................................44
8.1 Application Information............................................. 44
8.2 Typical Applications.................................................. 45
9 Power Supply Recommendations................................49
10 Layout...........................................................................50
10.1 Layout Guidelines................................................... 50
10.2 Layout Example...................................................... 51
11 Device and Documentation Support..........................52
11.1 Device Support........................................................52
11.2 Receiving Notification of Documentation Updates..54
11.3 Support Resources................................................. 54
11.4 Trademarks............................................................. 54
11.5 Electrostatic Discharge Caution..............................54
11.6 Glossary..................................................................54
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 7
6.1 Absolute Maximum Ratings........................................ 7
6.2 ESD Ratings............................................................... 7
6.3 Recommended Operating Conditions.........................8
6.4 Thermal Information....................................................8
6.5 Electrical Characteristics:............................................9
6.6 Electrical Characteristics: General............................10
6.7 Digital Characteristics............................................... 11
6.8 Timing Characteristics: LVDS And CMOS Modes.... 13
6.9 Typical Characteristics:.............................................17
6.10 Typical Characteristics: General............................. 21
6.11 Typical Characteristics: Contour............................. 22
7 Detailed Description......................................................23
7.1 Overview...................................................................23
4 Revision History
Changes from Revision A (September 2018) to Revision B (October 2020)
Page
• Changed 图 6-4 ............................................................................................................................................... 13
Changes from Revision * (April 2014) to Revision A (September 2018)
Page
• Moved Storage temperature, Tstg From the ESD Ratings table to the Absolute Maximum Ratings table..........7
• Changed Handling Rating To: ESD Ratings ...................................................................................................... 7
• Added a MIN value of 1 MSPS to Low-speed mode enabled in the Recommended Operating Conditions ......8
• Added NOTE to the Application and Implementation ...................................................................................... 44
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5 Pin Configuration and Functions
DRVDD
DB4M
DB4P
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
DRVDD
DA6P
DA6M
DA4P
DA4M
DA2P
DA2M
DA0P
DA0M
NC
2
3
DB6M
DB6P
4
5
DB8M
DB8P
6
7
DB10M
DB10P
DB12M
DB12P
RESET
SCLK
8
Thermal
Pad
9
10
11
12
13
14
15
16
NC
CTRL3
CTRL2
CTRL1
AVDD
AVDD
SDATA
SEN
AVDD
Not to scale
A. The PowerPAD™ is connected to DRGND.
NOTE: NC = do not connect; must float.
图 5-1. RGC Package (LVDS Mode) (1), VQFN-64, (Top View)
表 5-1. Pin Functions: LVDS Mode
NO.
NAME
# OF PINS
FUNCTION
DESCRIPTION
1, 48
DRVDD
2
Input
Output buffer supply
Serial interface RESET input.
When using the serial interface mode, the internal registers must be initialized through
a hardware RESET by applying a high pulse on this terminal or by using the software
reset option; refer to the Serial Interface Configuration section.
12
RESET
1
Input
In parallel interface mode, the RESET terminal must be permanently tied high. SCLK
and SEN are used as parallel control terminals in this mode. This terminal has an
internal 150kΩ pull-down resistor.
This terminal functions as a serial interface clock input when RESET is low. It controls
the low-speed mode selection when RESET is tied high; see 表 7-6 for detailed
information. This terminal has an internal 150kΩ pull-down resistor.
13
SCLK
SDATA
SEN
1
1
1
Input
Input
Input
14
15
Serial interface data input; this terminal has an internal 150kΩ pull-down resistor.
This terminal functions as a serial interface enable input when RESET is low. It controls
the output interface and data format selection when RESET is tied high; see 表 7-7 for
detailed information. This terminal has an internal 150kΩ pull-up resistor to AVDD.
16, 22, 33, 34
AVDD
AGND
4
8
Input
Input
Analog power supply
Analog ground
17, 18, 21, 24,
27, 28, 31, 32
19
20
INP_B
INM_B
1
1
Input
Input
Differential analog positive input, channel B
Differential analog negative input, channel B
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表 5-1. Pin Functions: LVDS Mode (continued)
NO.
NAME
# OF PINS
FUNCTION
DESCRIPTION
This terminal outputs the common-mode voltage (0.95V) that can be used externally to
bias the analog input terminals
23
VCM
1
Output
25
26
29
30
35
36
37
49
56
57
CLKP
CLKM
1
1
1
1
1
1
1
2
1
1
Input
Input
Input
Input
Input
Input
Input
Input
Output
Output
Differential clock positive input
Differential clock negative input
INP_A
Differential analog positive input, channel A
INM_A
Differential analog negative input, channel A
CTRL1
Digital control input terminals. Together, they control the various power-down modes.
Digital control input terminals. Together, they control the various power-down modes.
Digital control input terminals. Together, they control the various power-down modes.
Output buffer ground
CTRL2
CTRL3
DRGND
CLKOUTM
CLKOUTP
Differential output clock, complement
Differential output clock, true
This terminal functions as a serial interface register readout when the READOUT bit is
enabled. When READOUT = 0, this terminal is in high-impedance state.
64
SDOUT
1
2
Output
Output
40
DA0M
DA0P
DA2M
DA2P
DA4M
DA4P
DA6M
DA6P
DA8M
DA8P
DA10M
DA10P
DA12M
DA12P
DB0M
DB0P
DB2M
DB2P
DB4M
DB4P
DB6M
DB6P
DB8M
DB8P
DB10M
DB10P
DB12M
DB12P
NC
Channel A differential output data pair, D0 and D1 multiplexed
Channel A differential output data D2 and D3 multiplexed
Channel A differential output data D4 and D5 multiplexed
Channel A differential output data D6 and D7 multiplexed
Channel A differential output data D8 and D9 multiplexed
Channel A differential output data D10 and D11 multiplexed
Channel A differential output data D12 and D13 multiplexed
Channel B differential output data pair, D0 and D1 multiplexed
Channel B differential output data D2 and D3 multiplexed
Channel B differential output data D4 and D5 multiplexed
Channel B differential output data D6 and D7 multiplexed
Channel B differential output data D8 and D9 multiplexed
Channel B differential output data D10 and D11 multiplexed
41
42
2
2
2
2
2
2
2
2
2
2
2
2
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
43
44
45
46
47
50
51
52
53
54
55
60
61
62
63
2
3
4
5
6
7
8
9
10
11
2
4
Output
Channel B differential output data D12 and D13 multiplexed
Do not connect, must be floated
38, 39, 58, 59
—
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DRVDD
DB4
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
DRVDD
DA7
2
DB5
3
DA6
DB6
4
DA5
DB7
5
DA4
DB8
6
DA3
DB8
7
DA2
DB10
DB11
DB12
DB13
RESET
SCLK
SDATA
SEN
8
DA1
Thermal
Pad
9
DA0
10
11
12
13
14
15
16
NC
NC
CTRL3
CTRL2
CTRL1
AVDD
AVDD
AVDD
Not to scale
A. The PowerPAD™ is connected to DRGND.
NOTE: NC = do not connect; must float.
图 5-2. RGC Package (CMOS Mode), (1) VQFN-64, (Top View)
表 5-2. Pin Functions: CMOS Mode
NO.
NAME
# OF PINS
FUNCTION
DESCRIPTION
1, 48
DRVDD
2
Input
Output buffer supply
Serial interface RESET input.
When using the serial interface mode, the internal registers must be initialized
through a hardware RESET by applying a high pulse on this terminal or by using
the software reset option; refer to the Serial Interface Configuration section.
In parallel interface mode, the RESET terminal must be permanently tied high.
SDATA and SEN are used as parallel control terminals in this mode. This terminal
has an internal 150kΩ pull-down resistor.
12
RESET
1
Input
This terminal functions as a serial interface clock input when RESET is low. It
controls the low-speed mode when RESET is tied high; see 表 7-6 for detailed
information. This terminal has an internal 150kΩ pull-down resistor.
13
14
SCLK
1
1
Input
Input
SDATA
Serial interface data input; this terminal has an internal 150kΩ pull-down resistor.
This terminal functions as a serial interface enable input when RESET is low. It
controls the output interface and data format selection when RESET is tied high;
see 表 7-7 for detailed information. This terminal has an internal 150kΩ pull-up
resistor to AVDD.
15
SEN
1
Input
16, 22, 33, 34
AVDD
AGND
4
8
Input
Input
Analog power supply
Analog ground
17, 18, 21, 24,
27, 28, 31, 32
19
20
INP_B
INM_B
1
1
Input
Input
Differential analog positive input, channel B
Differential analog negative input, channel B
This terminal outputs the common-mode voltage (0.95V) that can be used
externally to bias the analog input terminals
23
VCM
1
Output
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表 5-2. Pin Functions: CMOS Mode (continued)
NO.
25
26
29
30
35
36
37
49
56
57
NAME
CLKP
# OF PINS
FUNCTION
DESCRIPTION
1
1
1
1
1
1
1
2
1
1
Input
Differential clock positive input
Differential clock negative input
CLKM
Input
INP_A
Input
Differential analog positive input, channel A
Differential analog negative input, channel A
INM_A
CTRL1
CTRL2
CTRL3
DRGND
UNUSED
CLKOUT
Input
Input
Digital control input terminals. Together, they control various power-down modes.
Digital control input terminals. Together, they control various power-down modes.
Digital control input terminals. Together, they control various power-down modes.
Output buffer ground
Input
Input
Input
This terminal is not used in the CMOS interface
—
Output
CMOS output clock
This terminal functions as a serial interface register readout when the READOUT
bit is enabled. When READOUT = 0, this terminal is in high-impedance state.
64
SDOUT
1
Output
40
DA0
DA1
DA2
DA3
DA4
DA5
DA6
DA7
DA8
DA9
DA10
DA11
DA12
DA13
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
DB8
DB8
DB10
DB11
DB12
DB13
NC
41
42
43
44
45
12
Output
Channel A ADC output data bits, CMOS levels
Channel A ADC output data bits, CMOS levels
Channel B ADC output data bits, CMOS levels
46
47
50
51
52
53
54
2
Output
55
60
61
62
63
2
3
12
Output
4
5
6
7
8
9
10
11
2
1
Output
Channel B ADC output data bits, CMOS levels
Do not connect, must be floated
38, 39, 58, 59
—
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.3
–0.3
–2.4
–2.4
MAX
2.1
2.1
0.3
2.4
2.4
UNIT
Supply voltage, AVDD
V
V
V
V
V
Supply voltage, DRVDD
Voltage between AGND and DRGND
Voltage between AVDD to DRVDD (when AVDD leads DRVDD)
Voltage between DRVDD to AVDD (when DRVDD leads AVDD)
Minimum
(1.9, AVDD + 0.3)
INP_A, INM_A, INP_B, INM_B
V
V
V
–0.3
–0.3
–0.3
Voltage applied to input terminals
CLKP, CLKM(2)
AVDD + 0.3
3.9
RESET, SCLK, SDATA, SEN,
CTRL1, CTRL2, CTRL3
Junction temperature, TJ
Storage temperature, Tstg
+150
+150
°C
°C
–55
–65
(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not implied.
(2) When AVDD is turned off, it is recommended to switch off the input clock (or ensure the voltage on CLKP, CLKM is less than |0.3V|).
This configuration prevents the ESD protection diodes at the clock input terminals from turning on.
6.2 ESD Ratings
VALUE
±2000
UNIT
(1)
VESD
Human body model (HBM)(2)
V
(1) Electrostatic discharge (ESD) to measure device sensitivity and immunity to damage caused by assembly line electrostatic discharges
in to the device.
(2) Level listed above is the passing level per ANSI, ESDA, and JEDEC JS-001. JEDEC document JEP155 states that 500-V HBM allows
safe manufacturing with a standard ESD control process.
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6.3 Recommended Operating Conditions
Over operating free-air temperature range, unless otherwise noted.
PARAMETER
MIN
NOM
MAX
UNIT
SUPPLIES
Analog supply voltage, AVDD
1.7
1.7
1.8
1.8
1.9
1.9
V
V
Digital supply voltage, DRVDD
ANALOG INPUTS
Differential input voltage
2
VPP
V
Input common-mode voltage
VCM ±0.05
400
Maximum analog input frequency with 2VPP input amplitude(1)
Maximum analog input frequency with 1VPP input amplitude(1)
CLOCK INPUT
MHz
MHz
600
Input clock sample rate
Low-speed mode enabled(2)
1
80
MSPS
MSPS
Low-speed mode disabled(2) (by default after reset)
Input clock duty cycle
80
125
Low-speed mode disabled(3)
35%
40%
50%
50%
65%
60%
Low-speed mode enabled(3)
DIGITAL OUTPUTS
Maximum external load capacitance from each output terminal to DRGND, CLOAD
Differential load resistance between the LVDS output pairs (LVDS mode), RLOAD
Operating junction temperature, TJ
5
pF
100
Ω
+125
°C
–55
(1) See the Theory of Operation section in the Application Information.
(2) See the Serial Interface Configuration section for details on programming the low-speed mode.
(3) Ensured by design for temperature range -40°C to 85°C.
6.4 Thermal Information
ADS4245-EP
THERMAL METRIC(1)
RGC
UNIT
64 TERMINAL
Rθ JA
Rθ JCtop
Rθ JB
ψJT
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
23.9
10.9
4.3
°C/W
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.1
4.4
ψJB
Rθ JCbot
0.6
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC package thermal metrics application
report.
表 6-1. High-Performance Modes
PARAMETER(1) (2)
High-performance mode
DESCRIPTION
Set the HIGH PERF MODE register bit to obtain best performance across sample clock and
input signal frequencies.
Register address = 03h, data = 03h
Set the HIGH FREQ MODE CH A and HIGH FREQ MODE CH B register bits for high input
signal frequencies greater than 200MHz.
Register address = 4Ah, data = 01h
High-frequency mode
Register address = 58h, data = 01h
(1) It is recommended to use these modes to obtain best performance.
(2) See the Serial Interface Configuration section for details on register programming.
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6.5 Electrical Characteristics:
Typical values are at +25°C, AVDD = 1.8V, DRVDD = 1.8V, 50% clock duty cycle, –1dBFS differential analog input, LVDS
interface, and 0dB gain (unless otherwise noted). Minimum and maximum values are across the recommended operating
condition (unless otherwise noted), AVDD = 1.8V, and DRVDD = 1.8V.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Resolution
14
Bits
fIN = 20MHz
fIN = 70MHz
fIN = 100MHz
fIN = 170MHz
fIN = 300MHz
fIN = 20MHz
fIN = 70MHz
fIN = 100MHz
fIN = 170MHz
fIN = 300MHz
fIN = 20MHz
fIN = 70MHz
fIN = 100MHz
fIN = 170MHz
fIN = 300MHz
fIN = 20MHz
fIN = 70MHz
fIN = 100MHz
fIN = 170MHz
fIN = 300MHz
fIN = 20MHz
fIN = 70MHz
fIN = 100MHz
fIN = 170MHz
fIN = 300MHz
fIN = 20MHz
fIN = 70MHz
fIN = 100MHz
fIN = 170MHz
fIN = 300MHz
fIN = 20MHz
fIN = 70MHz
fIN = 100MHz
fIN = 170MHz
fIN = 300MHz
73.4
72.9
72.6
71.4
69.3
73.2
72.6
72.3
71.2
68.5
88
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBc
68
Signal-to-noise ratio
SNR
SINAD
SFDR
THD
68
71
Signal-to-noise and
distortion ratio
86
dBc
Spurious-free dynamic range
Total harmonic distortion
Second-harmonic distortion
Third-harmonic distortion
85
dBc
88
dBc
78
dBc
86
dBc
68
84
dBc
83
dBc
84
dBc
75
dBc
88
dBc
66.5
72.5
73
86
dBc
HD2
85
dBc
88
dBc
78
dBc
93
dBc
89
dBc
HD3
89
dBc
90
dBc
81
dBc
95
dBc
94
dBc
Worst spur
(other than second and third harmonics)
93
dBc
91
dBc
89
dBc
f1 = 46MHz, f2 = 50MHz,
each tone at –7dBFS
96
92
dBFS
dBFS
Two-tone intermodulation distortion
Crosstalk
IMD
f1 = 185MHz, f2 = 190MHz,
each tone at –7dBFS
20-MHz full-scale signal on channel under
observation; 170-MHz full-scale signal on other
channel
95
dB
Recovery to within 1%
(of full-scale) for 6dB overload with sine-wave
input
Input overload recovery
1
Clock cycle
dB
For 100mVPP signal on AVDD supply, up to
10MHz
AC power-supply rejection ratio
PSRR
> 30
Effective number of bits
Differential nonlinearity
Integrated nonlinearity
ENOB
DNL
INL
fIN = 70MHz
fIN = 70MHz
fIN = 70MHz
11.5
±0.5
±2
LSBs
LSBs
LSBs
1.9
±5
–0.97
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6.6 Electrical Characteristics: General
Typical values are at +25°C, AVDD = 1.8V, DRVDD = 1.8V, 50% clock duty cycle, and –1dBFS differential analog input
(unless otherwise noted). Minimum and maximum values are across the recommended operating condition (unless otherwise
noted), AVDD = 1.8V, and DRVDD = 1.8V.
PARAMETER
MIN
TYP
MAX
UNIT
ANALOG INPUTS
Differential input voltage range (0dB gain)
Differential input resistance (at 200MHz)
Differential input capacitance (at 200MHz)
2
0.75
3.7
VPP
kΩ
pF
Analog input bandwidth
(with 50Ω source impedance, and 50Ω termination)
550
1.5
MHz
Analog input common-mode current
(per input terminal of each channel)
µA/MSPS
Common-mode output voltage
VCM output current capability
DC ACCURACY
VCM
0.95
4
V
mA
Offset error
2.5
25
4
mV
–25
–4
Temperature coefficient of offset error
0.003
mV/°C
Gain error as a result of internal reference inaccuracy
alone
EGREF
%FS
Gain error of channel alone
Temperature coefficient of EGCHAN
POWER SUPPLY
EGCHAN
±0.1
%FS
0.002
Δ%/°C
IAVDD
Analog supply current
105
99
130
120
mA
mA
IDRVDD
Output buffer supply current
LVDS interface, 350mV swing with 100Ω external termination, fIN = 2.5MHz
IDRVDD
Output buffer supply current
CMOS interface, no load capacitance(1)
fIN = 2.5MHz
49
mA
Analog power
189
179
mW
mW
Digital power
LVDS interface, 350mV swing with 100Ω external termination, fIN = 2.5MHz
Digital power
CMOS interface, no load capacitance(1)
fIN = 2.5MHz
88
mW
mW
Global power-down
25
(1) In CMOS mode, the DRVDD current scales with the sampling frequency, the load capacitance on output terminals, input frequency,
and the supply voltage (see the CMOS Interface Power Dissipation section in the Application Information).
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6.7 Digital Characteristics
At AVDD = 1.8V and DRVDD = 1.8V (unless otherwise noted). DC specifications refer to the condition where the digital
outputs do not switch, but are permanently at a valid logic level '0' or '1'.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DIGITAL INPUTS (RESET, SCLK, SDATA, SEN, CTRL1, CTRL2, CTRL3)(1)
High-level input voltage
1.3
V
All digital inputs support 1.8V
and 3.3V CMOS logic levels
Low-level input voltage
0.4
V
SDATA, SCLK(2)
SEN(3)
VHIGH = 1.8V
VHIGH = 1.8V
VLOW = 0V
10
0
µA
µA
µA
µA
High-level input current
SDATA, SCLK
SEN
0
Low-level input current
VLOW = 0V
10
DIGITAL OUTPUTS, CMOS INTERFACE (DA[13:0], DB[13:0], CLKOUT, SDOUT)
High-level output voltage
DRVDD
0
V
V
DRVDD – 0.1
Low-level output voltage
0.1
Output capacitance (internal to device)
DIGITAL OUTPUTS, LVDS INTERFACE
pF
With an external
100Ω termination
High-level output
differential voltage
VODH
220
350
490
mV
With an external
100Ω termination
Low-level output
differential voltage
VODL
VOCM
mV
V
–490
–350
–220
Output common-mode voltage
0.9
1.05
1.25
(1) SCLK, SDATA, and SEN function as digital input terminals in serial configuration mode.
(2) SDATA, SCLK have internal 150kΩ pull-down resistor.
(3) SEN has an internal 150kΩ pull-up resistor to AVDD. Because the pull-up is weak, SEN can also be driven by 1.8V or 3.3V CMOS
buffers.
DAn_P
DBn_P
Logic 0
VODL = -350mV(1)
Logic 1
V
ODH = +350mV(1)
DAn_M
DBn_M
VOCM
GND
A. With external 100Ω termination.
图 6-1. LVDS Output Voltage Levels
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100.00
10.00
1.00
85
95
105
115
125
Operating Junction Temperature (°C)
A. See datasheet for absolute maximum and minimum recommended operating conditions.
B. Silicon operating life design goal is 10 years at 105°C junction temperature (does not include package interconnect life).
C. Enhanced plastic product disclaimer applies.
图 6-2. ADS4245-EP Electromigration Fail Mode Chart
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6.8 Timing Characteristics: LVDS And CMOS Modes
Typical values are at +25°C, AVDD = 1.8 V, DRVDD = 1.8V, sampling frequency = 160MSPS, sine wave input clock, 1.5VPP
clock amplitude, CLOAD = 5pF(2), and RLOAD = 100Ω(3), unless otherwise noted. Minimum and maximum values are across
the full temperature range: TMIN = –55°C to TMAX = +125°C, AVDD = 1.8V, and DRVDD = 1.7V to 1.9V.
PARAMETER(1)
DESCRIPTION
MIN
TYP
MAX
UNIT
tA
Aperture delay
0.8
ns
Aperture delay matching
Between the two channels of the same device
±70
ps
Between two devices at the same temperature and
DRVDD supply
Variation of aperture delay
Aperture jitter
±150
140
50
ps
fS rms
µs
tJ
Time to valid data after coming out of STANDBY
mode
100
500
Wakeup time
Time to valid data after coming out of GLOBAL
power-down mode
100
16
µs
Clock
cycles
Default latency after reset
ADC latency(7)
Clock
cycles
Digital functions enabled (EN DIGITAL = 1)
24
DDR LVDS MODE(4)
tSU Data setup time
Data valid(5) to zero-crossing of CLKOUTP
1.5
2.0
0.6
ns
ns
Zero-crossing of CLKOUTP to data becoming
invalid(5)
tH
Data hold time
0.35
Input clock rising edge cross-over to output clock
rising edge cross-over
tPDI
Clock propagation delay
LVDS bit clock duty cycle
5.0
6.1
49
7.5
ns
%
Duty cycle of differential clock, (CLKOUTP-
CLKOUTM)
Rise time measured from –100mV to +100mV
Fall time measured from +100mV to –100mV
1MSPS ≤ Sampling frequency ≤ 160MSPS
tRISE
tFALL
,
Data rise time,
Data fall time
0.13
0.13
ns
ns
Rise time measured from –100mV to +100mV
Fall time measured from +100mV to –100mV
1MSPS ≤ Sampling frequency ≤ 160MSPS
tCLKRISE
tCLKFALL
,
Output clock rise time,
Output clock fall time
PARALLEL CMOS MODE
tSU
tH
Data setup time
Data hold time
Data valid(6) to zero-crossing of CLKOUT
1.6
2.3
2.5
2.7
ns
ns
Zero-crossing of CLKOUT to data becoming invalid(6)
Input clock rising edge cross-over to output clock
rising edge cross-over
tPDI
Clock propagation delay
Output clock duty cycle
4.5
6.4
46
8.5
ns
%
Duty cycle of output clock, CLKOUT
1MSPS ≤ Sampling frequency ≤ 160MSPS
Rise time measured from 20% to 80% of DRVDD
Fall time measured from 80% to 20% of DRVDD
1MSPS ≤ Sampling frequency ≤ 160MSPS
tRISE
tFALL
,
Data rise time,
Data fall time
1
1
ns
ns
Rise time measured from 20% to 80% of DRVDD
Fall time measured from 80% to 20% of DRVDD
1MSPS ≤ Sampling frequency ≤ 160MSPS
tCLKRISE
tCLKFALL
,
Output clock rise time
Output clock fall time
(1) Timing parameters are ensured by design and characterization and not tested in production.
(2) CLOAD is the effective external single-ended load capacitance between each output terminal and ground
(3) RLOAD is the differential load resistance between the LVDS output pair.
(4) Measurements are done with a transmission line of 100Ω characteristic impedance between the device and the load. Setup and hold
time specifications take into account the effect of jitter on the output data and clock.
(5) Data valid refers to a logic high of +100mV and a logic low of –100mV.
(6) Data valid refers to a logic high of 1.26V and a logic low of 0.54V
(7) At higher frequencies, tPDI is greater than one clock period and overall latency = ADC latency + 1.
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表 6-2. LVDS Timings At Lower Sampling Frequencies
tPDI, CLOCK PROPAGATION
SAMPLING
FREQUENCY
(MSPS)
SETUP TIME (ns)
HOLD TIME (ns)
DELAY (ns)
MIN
5.9
4.5
2.3
TYP
6.6
5.2
2.9
MAX
MIN
0.35
0.35
0.35
TYP
0.6
0.6
0.6
MAX
MIN
5.0
5.0
5.0
TYP
6.1
6.1
6.1
MAX
7.5
65
80
7.5
125
7.5
表 6-3. CMOS Timings At Lower Sampling Frequencies
TIMINGS SPECIFIED WITH RESPECT TO CLKOUT
SAMPLING
FREQUENCY
(MSPS)
tPDI, CLOCK PROPAGATION
DELAY (ns)
SETUP TIME (ns)
HOLD TIME (ns)
MIN
6.1
4.7
2.7
TYP
7.2
5.8
3.6
MAX
MIN
6.7
5.3
3.1
TYP
7.1
5.8
3.6
MAX
MIN
4.5
4.5
4.5
TYP
6.4
6.4
6.4
MAX
8.5
65
80
8.5
125
8.5
CLKM
CLKP
Input
Clock
tPDI
Output
Clock
CLKOUT
tSU
tH
DAn,
DBn
Output
Data
Dn(1)
A. Dn = bits D0, D1, D2, etc. of channels A and B.
图 6-3. CMOS Interface Timing Diagram
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A. ADC latency after reset. At higher sampling frequencies, tPDI is greater than one clock cycle, which then makes the overall latency =
ADC latency + 1.
B. E = even bits (D0, D2, D4, etc.); O = odd bits (D1, D3, D5, etc.).
图 6-4. Latency Timing Diagram
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CLKOUTM
CLKOUTP
DA0, DB0
D0
D2
D4
D1
D3
D5
D0
D2
D4
D1
D3
D5
DA2, DB2
DA4, DB4
DA6, DB6
DA8, DB8
D6
D8
D7
D9
D6
D8
D7
D9
DA10, DB10
DA12, DB12
D10
D12
D11
D13
D10
D12
D11
D13
Sample N
Sample N + 1
图 6-5. ADS4245 LVDS Interface Timing Diagram
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6.9 Typical Characteristics:
At TA = +25°C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential
clock amplitude, 50% clock duty cycle, –1dBFS differential analog input, High-Performance Mode disabled, 0dB gain, DDR
LVDS output interface, and 32k point FFT, unless otherwise noted.
0
0
−20
−20
−40
−40
−60
−60
−80
−80
−100
−120
−100
−120
0
10
20
30
40
50
60
0
10
20
30
40
50
60
Frequency (MHz)
Frequency (MHz)
SFDR = 89.7dBc
THD = 88.4dBc
SINAD = 73dBFS
SNR = 73.1dBFS
SFDR = 86.7dBc SINAD = 71.2dBFS
THD = 83.8dBc
SNR = 71.4dBFS
图 6-6. FFT For 20MHz Input Signal
图 6-7. FFT For 170MHz Input Signal
0
−20
0
−20
−40
−40
−60
−60
−80
−80
−100
−120
−100
−120
0
10
20
30
40
50
60
0
10
20
30
40
50
60
Frequency (MHz)
Frequency (MHz)
fIN1 = 185MHz
fIN2 = 190MHz
Each Tone at −7dBFS Amplitude
SFDR = 92.8dBFS
SFDR = 73.4dBc SINAD = 67.7dBFS
THD = 72.3dBc
SNR = 69.2dBFS
Two−Tone IMD = 94dBFS
图 6-9. FFT For Two-Tone Input Signal
图 6-8. FFT For 300MHz Input Signal
0
−20
90
85
80
75
70
65
−40
−60
−80
−100
−120
Gain = 0dB
Gain = 6dB
0
10
20
30
40
50
60
0
50 100 150 200 250 300 350 400 450 500
Input Frequency (MHz)
Frequency (MHz)
fIN1 = 46MHz
fIN2 = 50MHz
Each Tone at −7dBFS Amplitude
SFDR=105.3dBFS
图 6-11. SFDR vs Input Frequency
Two−Tone IMD=96.9dBFS
图 6-10. FFT For Two-Tone Input Signal
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6.9 Typical Characteristics: (continued)
At TA = +25°C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential
clock amplitude, 50% clock duty cycle, –1dBFS differential analog input, High-Performance Mode disabled, 0dB gain, DDR
LVDS output interface, and 32k point FFT, unless otherwise noted.
74
73
72
71
70
69
68
67
66
65
64
63
74
73
72
71
70
69
68
67
66
65
64
63
Gain = 0dB
Gain = 6dB
Gain = 0dB
Gain = 6dB
0
50 100 150 200 250 300 350 400 450 500
Input Frequency (MHz)
0
50 100 150 200 250 300 350 400 450 500
Input Frequency (MHz)
图 6-12. SNR vs Input Frequency
图 6-13. SNR vs Input Frequency (CMOS)
94
92
90
88
86
84
82
80
78
76
74
72
70
68
66
72
71
70
69
68
67
66
65
64
63
62
150MHz
170MHz
220MHz
300MHz
400MHz
470MHz
150MHz
170MHz
220MHz
300MHz
400MHz
470MHz
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
Digital Gain (dB)
Digital Gain (dB)
图 6-15. SINAD vs Gain And Input Frequency
图 6-14. SFDR vs Gain And Input Frequency
110
100
90
76.5
76
110
100
90
77
76
75
74
73
72
71
70
69
75.5
75
80
80
70
74.5
74
70
60
60
50
73.5
73
50
SFDR(dBc)
SFDR(dBFS)
SNR
SFDR(dBc)
SFDR(dBFS)
SNR
40
40
30
−70
72.5
0
30
−70
−60
−50
−40
−30
−20
−10
−60
−50
−40
−30
−20
−10
0
Amplitude (dBFS)
Amplitude (dBFS)
Input Frequency = 40MHz
Input Frequency = 150MHz
图 6-16. Performance vs Input Amplitude
图 6-17. Performance vs Input Amplitude
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6.9 Typical Characteristics: (continued)
At TA = +25°C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential
clock amplitude, 50% clock duty cycle, –1dBFS differential analog input, High-Performance Mode disabled, 0dB gain, DDR
LVDS output interface, and 32k point FFT, unless otherwise noted.
90
89
88
87
86
85
84
83
82
73.8
73.7
73.6
73.5
73.4
73.3
73.2
73.1
73
89
87
85
83
81
79
77
75
73
73
72.75
72.5
72.25
72
71.75
71.5
71.25
71
SFDR
SNR
SFDR
SNR
0.8
0.85
0.9
0.95
1
1.05
1.1
0.8
0.85
0.9
0.95
1
1.05
1.1
Input CommonMode (V)
Input CommonMode Voltage (V)
Input Frequency = 40MHz
Input Frequency = 150MHz
图 6-18. Performance vs Input Common-Mode Voltage
图 6-19. Performance vs Input Common-Mode Voltage
91
73
AVDD = 1.65
AVDD = 1.7
AVDD = 1.75
AVDD = 1.80
AVDD = 1.85
AVDD = 1.9
AVDD = 1.95
AVDD = 1.65
AVDD = 1.70
AVDD = 1.75
AVDD = 1.80
AVDD = 1.85
AVDD = 1.90
AVDD = 1.95
89
87
85
83
81
79
77
75
73
71
72.5
72
71.5
71
70.5
70
−40
−40
−15
10
35
60
85
−15
10
35
60
85
Temperature (°C)
Temperature (°C)
Input Frequency = 150MHz
Input Frequency = 150MHz
图 6-20. SFDR vs Temperature And AVDD Supply
图 6-21. SNR vs Temperature And AVDD Supply
88
87
86
85
84
83
82
73
90
89
88
87
86
85
84
74.5
74
72.5
72
73.5
73
71.5
71
72.5
72
70.5
SFDR
SNR
SFDR
SNR
70
1.95
71.5
2.2
1.65
1.7
1.75
1.8
1.85
1.9
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6 1.8
2
DRVDD Supply (V)
Differential Clock Amplitude (VPP
)
Input Frequency = 150MHz
Input Frequency = 40MHz
图 6-22. Performance vs DRVDD Supply Voltage
图 6-23. Performance vs Input Clock Amplitude
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6.9 Typical Characteristics: (continued)
At TA = +25°C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential
clock amplitude, 50% clock duty cycle, –1dBFS differential analog input, High-Performance Mode disabled, 0dB gain, DDR
LVDS output interface, and 32k point FFT, unless otherwise noted.
90
88
86
84
82
80
78
76
74
72
70
68
75
74
73
72
71
70
69
68
67
66
65
64
89
75
88
87
86
85
84
83
74.5
74
73.5
73
72.5
72
SFDR
SNR
SNR
THD
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6 1.8
2
2.2
25
30
35
40
45
50
55
60
65
70
75
Input Clock Duty Cycle (%)
Differential Clock Amplitude (VPP
)
Input Frequency = 10MHz
Input Frequency = 150MHz
图 6-25. Performance vs Input Clock Duty Cycle
图 6-24. Performance vs Input Clock Amplitude
1.5
40
1.2
0.9
0.6
0.3
0
35
30
25
20
15
10
5
33.31
28.49
18.26
−0.3
−0.6
−0.9
−1.2
−1.5
12.23
4.52
2.46
0.47
0.23
0.01
0
0
4000
8000
12000
16000
8212 8213 8214 8215 8216 8217 8218 8219 8220 8221
Output Code (LSB)
Output Code (LSB)
Input Frequency = 20MHz
RMS Noise = 1.1LSB
图 6-26. Integrated Nonlinearity
图 6-27. Output Noise Histogram (With Inputs Shorted To VCM)
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6.10 Typical Characteristics: General
At TA = +25°C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP
differential clock amplitude, 50% clock duty cycle, –1dBFS differential analog input, High-Performance Mode
disabled, 0dB gain, DDR LVDS output interface, and 32k point FFT, unless otherwise noted.
0
0
−5
−5
−10
−15
−20
−25
−30
−35
−40
−45
−50
−55
−60
−10
−15
−20
−25
−30
−35
−40
−45
−50
0
50
100
150
200
250
300
0
50
100
150
200
250
300
Frequency of Input Common−Mode Signal (MHz)
Frequency of Signal on Supply (MHz)
Input Frequency = 40MHz
50mVPP Signal Superimposed
Input Frequency = 10MHz
50mVPP Signal Superimposed on AVDD Supply
on Input Common−Mode Voltage 0.95V
图 6-29. PSRR vs Test Signal Frequency
图 6-28. CMRR vs Test Signal Frequency
240
220
200
180
160
140
120
100
80
240
220
200
180
160
140
120
100
80
60
40
LVDS, 350mV Swing
CMOS
20
60
0
0
20
40
60
80
100
120
140
160
0
20
40
60
80
100
120
140
160
Sampling Speed (MSPS)
Sampling Speed (MSPS)
AVDD = 1.8V
Input Frequency = 2.5MHz
fIN = 2.5 MHz
图 6-30. Analog Power vs Sampling Frequency
图 6-31. Digital Power LVDS CMOS
260
Default
EN Digital = 1
EN Digital = 1, Offset Correction Enabled
240
220
200
180
160
140
120
100
80
0
20
40
60
80
100
120
140
160
Sampling Speed (MSPS)
图 6-32. Digital Power In Various Modes (LVDS)
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6.11 Typical Characteristics: Contour
All graphs are at +25°C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input
clock. 1.5VPP differential clock amplitude, 50% clock duty cycle, –1dBFS differential analog input, High-
Performance Mode disabled, 0dB gain, DDR LVDS output interface, and 32k point FFT, unless otherwise noted.
160
150
140
130
120
110
100
90
160
150
140
130
120
110
100
90
79
77
79
76
83
73
83
87
83
81
83
87
86
83
86
86
87
79
79
83
81
83
76
79
73
86
83
87
87
89
79
89
79
79
83
81
76
80
80
89
83
83
73
73
86
79
83
87
100
70
65
70
65
79
92
91
10
50
150
200
250
300
350
400
450
90
10
50
100
150
200
250
300
86
350
400
450
Input Frequency (MHz)
80
Input Frequency (MHz)
84
70
75
85
78
80
82
88
90
92
SFDR (dBc)
SFDR (dBc)
图 6-33. Spurious-Free Dynamic Range (0dB Gain) 图 6-34. Spurious-Free Dynamic Range (6dB Gain)
160
150
140
130
120
110
100
90
160
150
140
130
120
110
100
90
67
64.5
65
65
65
66.5
66.75
67
71
65.5
66
66.25
73
72
70
67
69
67
68
68
67.25
66.75
73
71
72
66
65.5
65.5
66.5
70
66.25
69
67
67.25
67
67.5
66.75
71
72
66
73
66.25
68
66.5
70
80
80
67.25
64.5
67
69
67
67.5
50
70
65
70
65
10
50
100
150
200
250
300
350
400
72
450
10
100
150
200
250
300
350
400
67
450
Input Frequency (MHz)
70
Input Frequency (MHz)
66
67
68
69
71
73
64.5
65
65.5
66.5
67.5
SNR (dBFS)
SNR (dBFS)
图 6-35. Signal-To-Noise Ratio (0dB Gain)
图 6-36. Signal-To-Noise Ratio (6dB Gain)
160
150
140
130
120
110
100
90
160
150
140
130
120
110
100
90
65.75
70
67
70.5
69
67.5
68
66.5
68.5
66
69.5
66.25
65.75
65.5
64.5
65
66.25
66.5
66
69.5
70
67
68
67.5
68.5
69
66
66.5
70.5
65.75
65.5
66.5
65
65
64.5
66
67
66.25
150
69.5
150
69
65.5
80
80
66.75
70
66.5
68.5
70.5
67.5
68
65.75
64.5
400
66.5
66
69
70
65
70
65
10
50
100
200
250
300
350
400
450
10
64
50
100
200
250
300
350
66
450
Input Frequency (MHz)
Input Frequency (MHz)
65.5
66
66.5
67
67.5
68
68.5
69
69.5
70
70.5
64.5
65
66.5
SNR (dBFS)
SNR (dBFS)
图 6-37. Signal-To-Noise Ratio (0dB Gain)
图 6-38. Signal-To-Noise Ratio (6dB Gain)
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7 Detailed Description
7.1 Overview
The ADS4245 is a low-speed variant of the ADS42xx ultralow-power family of dual-channel, 14-bit analog- to-
digital converters (ADCs). Innovative design techniques are used to achieve high-dynamic performance, while
consuming extremely low power with 1.8V supply.
The ADS4245 has gain options that can be used to improve SFDR performance at lower full-scale input ranges.
This device includes a dc offset correction loop that can be used to cancel the ADC offset.
7.2 Functional Block Diagram
AVDD
AGND
DRVDD DRGND
LVDS Interface
DA0P
DA0M
DA2P
DA2M
DA4P
INP_A
INM_A
Digital and
DDR
Serializer
DA4M
DA6P
14-Bit
ADC
Sampling
Circuit
DA6M
DA8P
DA8M
DA10P
DA10M
DA12P
DA12M
CLKP
CLKM
CLKOUTP
CLKOUTM
Output
Clock Buffer
CLOCKGEN
DB0P
DB0M
DB2P
DB2M
DB4P
INP_B
INM_B
Digital and
DDR
Serializer
DB4M
DB6P
14-Bit
ADC
Sampling
Circuit
DB6M
DB8P
DB8M
DB10P
DB10M
DB12P
DB12M
Control
Interface
VCM
Reference
SDOUT
ADS424x
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7.3 Feature Description
The ADS4245 is terminal-compatible with the previous generation ADS62P49 family of data converters; this
architecture enables easy migration. However, there are some important differences between the two device
generations, summarized in 表 7-1.
表 7-1. Migrating From The ADS62P49
ADS62P49 FAMILY
ADS4245 FAMILY
TERMINALS
Terminal 22 is NC (not connected)
Terminals 38 and 58 are DRVDD
Terminals 39 and 59 are DRGND
SUPPLY
Terminal 22 is AVDD
Terminals 38 and 58 are NC (do not connect, must be floated)
Terminals 39 and 59 are NC (do not connect, must be floated)
AVDD is 3.3V
AVDD is 1.8V
No change
DRVDD is 1.8V
INPUT COMMON-MODE VOLTAGE
VCM is 1.5V
VCM is 0.95V
SERIAL INTERFACE
No change in protocol
New serial register map
Protocol: 8-bit register address and 8-bit register data
EXTERNAL REFERENCE
Supported
Not supported
7.4 Device Functional Modes
7.4.1 Digital Functions
The device has several useful digital functions (such as test patterns, gain, and offset correction). These
functions require extra clock cycles for operation and increase the overall latency and power of the device.
These digital functions are disabled by default after reset and the raw ADC output is routed to the output data
terminals with a latency of 16 clock cycles. 图 7-1 shows more details of the processing after the ADC. In order
to use any of the digital functions, the EN DIGITAL bit must be set to '1'. After this, the respective register bits
must be programmed as described in the following sections and in the Serial Register Map section.
Output
Interface
12-/14-Bit
ADC
12-Bit (ADS422x)
14-Bit (ADS424x)
Digital Functions
(Gain, Offset Correction, Test Patterns)
DDR LVDS
or CMOS
EN DIGITAL Bit
图 7-1. Digital Processing Block
7.4.2 Gain For SFDR/SNR Trade-Off
The ADS4245 includes gain settings that can be used to get improved SFDR performance (compared to no
gain). The gain is programmable from 0dB to 6dB (in 0.5dB steps). For each gain setting, the analog input full-
scale range scales proportionally, as shown in 表 7-2.
The SFDR improvement is achieved at the expense of SNR; for each gain setting, the SNR degrades
approximately between 0.5dB and 1dB. The SNR degradation is reduced at high input frequencies. As a result,
the gain is very useful at high input frequencies because the SFDR improvement is significant with marginal
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degradation in SNR. Therefore, the gain can be used as a trade-off between SFDR and SNR. Note that the
default gain after reset is 0dB.
表 7-2. Full-Scale Range Across Gains
GAIN (dB)
TYPE
FULL-SCALE (VPP)
0
1
2
3
4
5
6
Default after reset
Fine, programmable
Fine, programmable
Fine, programmable
Fine, programmable
Fine, programmable
Fine, programmable
2
1.78
1.59
1.42
1.26
1.12
1
7.4.3 Offset Correction
The ADS4245 has an internal offset corretion algorithm that estimates and corrects dc offset up to ±10mV. The
correction can be enabled using the ENABLE OFFSET CORR serial register bit. Once enabled, the algorithm
estimates the channel offset and applies the correction every clock cycle. The time constant of the correction
loop is a function of the sampling clock frequency. The time constant can be controlled using the OFFSET
CORR TIME CONSTANT register bits, as described in 表 7-3.
After the offset is estimated, the correction can be frozen by setting FREEZE OFFSET CORR = 0. Once frozen,
the last estimated value is used for the offset correction of every clock cycle. Note that offset correction is
disabled by default after reset.
表 7-3. Time Constant Of Offset Correction Algorithm
TIME CONSTANT, TCCLK
(Number of Clock Cycles)
OFFSET CORR TIME CONSTANT
TIME CONSTANT, TCCLK × 1/fS (ms)(1)
0000
0001
0010
0011
0100
0101
0110
f0111
1000
1001
1010
1011
1100
1101
1110
1111
1M
2M
7
13
4M
26
8M
52
16M
105
210
419
839
1678
3355
6711
13422
—
32M
64M
128M
256M
512M
1G
2G
Reserved
Reserved
Reserved
Reserved
—
—
—
(1) Sampling frequency, fS = 160MSPS.
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7.4.4 Power-Down
The ADS4245 has two power-down modes: global power-down and channel standby. These modes can be set
using either the serial register bits or using the control terminals CTRL1 to CTRL3 (as shown in 表 7-4).
表 7-4. Power-Down Settings
CTRL1
Low
CTRL2
Low
CTRL3
DESCRIPTION
Low
Default
Low
Low
High
Low
Not available
Not available
Not available
Global power-down
Low
High
High
Low
Low
High
Low
High
High
High
Low
High
Low
Channel A powered down, channel B is active
Not available
High
MUX mode of operation, channel A and B data is
multiplexed and output on DB[10:0] terminals
High
High
High
7.4.4.1 Global Power-Down
In this mode, the entire chip (including ADCs, internal reference, and output buffers) are powered down, resulting
in reduced total power dissipation of approximately 20mW when the CTRL terminals are used and 3mW when
the PDN GLOBAL serial register bit is used. The output buffers are in high-impedance state. The wake-up time
from global power-down to data becoming valid in normal mode is typically 100µs.
7.4.4.2 Channel Standby
In this mode, each ADC channel can be powered down. The internal references are active, resulting in a quick
wake-up time of 50µs. The total power dissipation in standby is approximately 200mW at 160MSPS.
7.4.4.3 Input Clock Stop
In addition to the previous modes, the converter enters a low-power mode when the input clock frequency falls
below 1MSPS. The power dissipation is approximately 160mW.
7.4.5 Digital Output Information
The ADS4245 provides 14-bit digital data for each channel and an output clock synchronized with the data.
7.4.5.1 Output Interface
Two output interface options are available: double data rate (DDR) LVDS and parallel CMOS. They can be
selected using the serial interface register bit or by setting the proper voltage on the SEN terminal in parallel
configuration mode.
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7.4.5.2 DDR LVDS Outputs
In this mode, the data bits and clock are output using low-voltage differential signal (LVDS) levels. Two data bits
are multiplexed and output on each LVDS differential pair, as shown in 图 7-2.
Pins
CLKOUTP
Output
Clock
CLKOUTM
DB0_P
Data Bits
D0, D1
DB0_M
DB2_P
Data Bits
D2, D3
DB2_M
DB4_P
Data Bits
D4, D5
14-Bit ADC Data,
Channel B
DB4_M
DB6_P
DB6_M
Data Bits
D6, D7
DB8_P
DB8_M
Data Bits
D8, D9
DB10_P
DB10_M
Data Bits
D10, D11
DB12_P
DB12_M
Data Bits
D12, D13
图 7-2. LVDS Interface
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Even data bits (D0, D2, D4, etc.) are output at the CLKOUTP rising edge and the odd data bits (D1, D3, D5, etc.)
are output at the CLKOUTP falling edge. Both the CLKOUTP rising and falling edges must be used to capture all
the data bits, as shown in 图 7-3.
CLKOUTM
CLKOUTP
DA0P/M, DB0P/M
DA2P/M, DB2P/M
DA4P/M, DB4P/M
D0
D2
D4
D1
D3
D5
D0
D2
D4
D1
D3
D5
DA6P/M, DB6P/M
DA8P/M, DB8P/M
D6
D8
D7
D9
D6
D8
D7
D9
DA10P/M, DB10P/M
DA12P/M, DB12P/M
D10
D12
D11
D13
D10
D12
D11
D13
Sample N
Sample N + 1
图 7-3. DDR LVDS Interface Timing
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7.4.5.3 LVDS Buffer
The equivalent circuit of each LVDS output buffer is shown in 图 7-4. After reset, the buffer presents an output
impedance of 100Ω to match with the external 100Ω termination.
VDIFF
High
Low
OUTP
OUTM
External
100W Load
VOCM
ROUT
VDIFF
High
Low
NOTE: Default swing across 100Ω load is ±350mV. Use the LVDS SWING bits to change the swing.
图 7-4. LVDS Buffer Equivalent Circuit
The VDIFF voltage is nominally 350mV, resulting in an output swing of ±350mV with 100Ω external termination.
The VDIFF voltage is programmable using the LVDS SWING register bits from ±125mV to ±570mV.
Additionally, a mode exists to double the strength of the LVDS buffer to support 50Ω differential termination, as
shown in 图 7-5. This mode can be used when the output LVDS signal is routed to two separate receiver chips,
each using a 100Ω termination. The mode can be enabled using the LVDS DATA STRENGTH and LVDS
CLKOUT STRENGTH register bits for data and output clock buffers, respectively.
The buffer output impedance behaves in the same way as a source-side series termination. By absorbing
reflections from the receiver end, it helps to improve signal integrity.
Receiver Chip # 1
(for example, GC5330)
DAnP/M
CLKIN1
100W
CLKOUTP
CLKOUTM
CLKIN2
100W
DBnP/M
Receiver Chip # 2
ADS42xx
Make LVDS CLKOUT STRENGTH = 1
图 7-5. LVDS Buffer Differential Termination
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7.4.5.4 Parallel CMOS Interface
In the CMOS mode, each data bit is output on separate terminals as CMOS voltage level, every clock cycle, as
图 7-6 shows. The rising edge of the output clock CLKOUT can be used to latch data in the receiver. It is
recommended to minimize the load capacitance of the data and clock output terminals by using short traces to
the receiver. Furthermore, match the output data and clock traces to minimize the skew between them.
DB0
DB1
DB2
14-Bit ADC Data,
Channel B
DB11
DB12
DB13
SDOUT
CLKOUT
DA0
DA1
DA2
14-Bit ADC Data,
Channel A
DA11
DA12
DA13
图 7-6. CMOS Outputs
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7.4.5.5 CMOS Interface Power Dissipation
With CMOS outputs, the DRVDD current scales with the sampling frequency and the load capacitance on every
output terminal. The maximum DRVDD current occurs when each output bit toggles between 0 and 1 every
clock cycle. In actual applications, this condition is unlikely to occur. The actual DRVDD current would be
determined by the average number of output bits switching, which is a function of the sampling frequency and
the nature of the analog input signal. This relationship is shown by the formula:
Digital current as a result of CMOS output switching = CL × DRVDD × (N × FAVG),
where CL = load capacitance, N × FAVG = average number of output bits switching.
7.4.5.6 Multiplexed Mode Of Operation
In this mode, the digital outputs of both channels are multiplexed and output on a single bus (DB[13:0]
terminals), as shown in 图 7-7. The channel A output terminals (DA[13:0]) are in 3-state. Because the output
data rate on the DB bus is effectively doubled, this mode is recommended only for low sampling frequencies
(less than 80MSPS). This mode can be enabled using the POWER-DOWN MODE register bits or using the
CTRL[3:1] parallel terminals.
CLKM
Input
Clock
CLKP
tPDI
Output
CLKOUT
Clock
tSU
tH
Channel A
DAn(2)
Channel B
DBn(2)
Channel A
DAn(2)
Output
Data
DBn(1)
A. In multiplexed mode, both channels outputs come on the channel B output terminals.
B. Dn = bits D0, D1, D2, etc.
图 7-7. Multiplexed Mode Timing Diagram
7.4.5.7 Output Data Format
Two output data formats are supported: twos complement and offset binary. The format can be selected using
the DATA FORMAT serial interface register bit or by controlling the DFS terminal in parallel configuration mode.
In the event of an input voltage overdrive, the digital outputs go to the appropriate full-scale level. For a positive
overdrive, the output code is FFFh for the ADS422x and 3FFFh for the ADS424x in offset binary output format;
the output code is 7FFh for the ADS422x and 1FFFh for the ADS424x in twos complement output format. For a
negative input overdrive, the output code is 0000h in offset binary output format and 800h for the ADS422x and
2000h for the ADS424x in twos complement output format.
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7.4.6 Device Configuration
The ADS4245 can be configured independently using either parallel interface control or serial interface
programming.
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7.4.6.1 Parallel Configuration Only
To put the device into parallel configuration mode, keep RESET tied high (AVDD). Then, use the SEN, SCLK,
CTRL1, CTRL2, and CTRL3 terminals to directly control certain modes of the ADC. The device can be easily
configured by connecting the parallel terminals to the correct voltage levels (as described in 表 7-5 to 表 7-8).
There is no need to apply a reset and SDATA can be connected to ground.
In this mode, SEN and SCLK function as parallel interface control terminals. Some frequently-used functions can
be controlled using these terminals. 表 7-5 describes the modes controlled by the parallel terminals.
表 7-5. Parallel Terminal Definition
TERMINAL
SCLK
CONTROL MODE
Low-speed mode selection
SEN
Output data format and output interface selection
CTRL1
CTRL2
CTRL3
Together, these terminals control the power-down modes
7.4.6.2 Serial Interface Configuration Only
To enable this mode, the serial registers must first be reset to the default values and the RESET terminal must
be kept low. SEN, SDATA, and SCLK function as serial interface terminals in this mode and can be used to
access the internal registers of the ADC. The registers can be reset either by applying a pulse on the RESET
terminal or by setting the RESET bit high. The Serial Register Map section describes the register programming
and the register reset process in more detail.
7.4.6.3 Using Both Serial Interface And Parallel Controls
For increased flexibility, a combination of serial interface registers and parallel terminal controls (CTRL1 to
CTRL3) can also be used to configure the device. To enable this option, keep RESET low. The parallel interface
control terminals CTRL1 to CTRL3 are available. After power-up, the device is automatically configured
according to the voltage settings on these terminals (see 表 7-8). SEN, SDATA, and SCLK function as serial
interface digital terminals and are used to access the internal registers of the ADC. The registers must first be
reset to the default values either by applying a pulse on the RESET terminal or by setting the RESET bit to '1'.
After reset, the RESET terminal must be kept low. The Serial Register Map section describes register
programming and the register reset process in more detail.
7.4.6.4 Parallel Configuration Details
The functions controlled by each parallel terminal are described in 表 7-6, 表 7-7, and 表 7-8. A simple way of
configuring the parallel terminals is shown in 图 7-8.
表 7-6. SCLK Control Terminal
VOLTAGE APPLIED ON SCLK
DESCRIPTION
Low
Low-speed mode is disabled
Low-speed mode is enabled(1)
High
(1) Low-speed mode is enabled in the ADS4222/42 by default.
表 7-7. SEN Control Terminal
VOLTAGE APPLIED ON SEN
DESCRIPTION
Twos complement and parallel CMOS output
Offset binary and parallel CMOS output
0
(+50mV/0mV)
(3/8) AVDD
(±50mV)
(5/8) 2AVDD
(±50mV)
Offset binary and DDR LVDS output
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表 7-7. SEN Control Terminal (continued)
VOLTAGE APPLIED ON SEN
DESCRIPTION
AVDD
(0mV/–50mV)
Twos complement and DDR LVDS output
表 7-8. CTRL1, CTRL2, And CTRL3 Terminals
CTRL1
Low
CTRL2
CTRL3
DESCRIPTION
Low
Low
High
High
Low
Low
High
Low
Normal operation
Not available
Low
High
Low
Low
Not available
Low
High
Low
Not available
High
High
High
Global power-down
High
Low
Channel A standby, channel B is active
Not available
MUX mode of operation, channel A and B data are
multiplexed and output on the DB[13:0] terminals.
High
High
High
AVDD
(5/8) AVDD
3R
(5/8) AVDD
(3/8) AVDD
GND
AVDD
2R
3R
(3/8) AVDD
To Parallel Terminal
图 7-8. Simple Scheme To Configure The Parallel Terminals
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7.4.6.5 Serial Interface Details
The ADC has a set of internal registers that can be accessed by the serial interface formed by the SEN (serial
interface enable), SCLK (serial interface clock), and SDATA (serial interface data) terminals. Serial shift of bits
into the device is enabled when SEN is low. Serial data SDATA are latched at every SCLK falling edge when
SEN is active (low). The serial data are loaded into the register at every 16th SCLK falling edge when SEN is
low. When the word length exceeds a multiple of 16 bits, the excess bits are ignored. Data can be loaded in
multiples of 16-bit words within a single active SEN pulse. The first eight bits form the register address and the
remaining eight bits are the register data. The interface can work with SCLK frequencies from 20MHz down to
very low speeds (of a few hertz) and also with non-50% SCLK duty cycle.
7.4.6.5.1 Register Initialization
After power-up, the internal registers must be initialized to the default values. Initialization can be accomplished
in one of two ways:
1. Either through hardware reset by applying a high pulse on the RESET terminal (of width greater than 10ns),
as shown in 图 7-9; or
2. By applying a software reset. When using the serial interface, set the RESET bit high. This setting initializes
the internal registers to the default values and then self-resets the RESET bit low. In this case, the RESET
terminal is kept low.
Register Address
Register Data
SDATA
SCLK
A7
A6
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
tDH
D1
D0
tSCLK
tDSU
tSLOADS
tSLOADH
SEN
RESET
图 7-9. Serial Interface Timing
表 7-9. Serial Interface Timing Characteristics
PARAMETER(1)
SCLK frequency (equal to 1/tSCLK
SEN to SCLK setup time
SCLK to SEN hold time
SDATA setup time
MIN
> DC
30
TYP
MAX
UNIT
fSCLK
tSLOADS
tSLOADH
tDSU
)
20
MHz
ns
30
ns
30
ns
tDH
SDATA hold time
30
ns
(1) Typical values at +25°C; minimum and maximum values across the full temperature range: TMIN = –55°C to TMAX = +125°C,
AVDD = 1.8V, and DRVDD = 1.8V, unless otherwise noted.
7.4.6.5.2 Serial Register Readout
The device includes a mode where the contents of the internal registers can be read back. This readback mode
may be useful as a diagnostic check to verify the serial interface communication between the external controller
and the ADC. To use readback mode, follow this procedure:
1. Set the READOUT register bit to '1'. This setting disables any further writes to the registers.
2. Initiate a serial interface cycle specifying the address of the register (A7 to A0) whose content has to be read.
3. The device outputs the contents (D7 to D0) of the selected register on the SDOUT terminal (terminal 64).
4. The external controller can latch the contents at the SCLK falling edge.
5. To enable register writes, reset the READOUT register bit to '0'.
The serial register readout works with both CMOS and LVDS interfaces on terminal 64.
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When READOUT is disabled, the SDOUT terminal is in high-impedance state. If serial readout is not used, the
SDOUT terminal must float.
Register Address A[7:0] = 00h
Register Data D[7:0] = 01h
SDATA
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
SCLK
SEN
The SDOUT pin is in high-impedance state.
SDOUT
a) Enable serial readout (READOUT = 1)
Register Address A[7:0] = 45h
A4 A2
A5 A3
Register Data D[7:0] = XX (don’t care)
D4 D2 D1
D6 D5 D3
SDATA
SCLK
A7
A6
A1
A0
D7
D0
SEN
0
0
0
0
0
1
0
0
SDOUT
The SDOUT pin functions as serial readout (READOUT = 1).
b) Read contents of Register 45h. This register has been initialized with 04h (device is put into global power-down mode.)
图 7-10. Serial Readout Timing Diagram
表 7-10. Reset Timing (Only When Serial Interface Is Used)
PARAMETER(1)
CONDITIONS
MIN
TYP MAX UNIT
Delay from AVDD and DRVDD power-up to active RESET
pulse
1
ms
t1
Power-on delay
100
350
ns
t2
t3
Reset pulse width
Active RESET signal pulse width
1
µs
ns
Register write delay
Delay from RESET disable to SEN active
(1) Typical values at +25°C; minimum and maximum values across the full temperature range: TMIN = –55°C to TMAX = +125°C, unless
otherwise noted.
Power Supply
AVDD, DRVDD
t1
RESET
t2
t3
SEN
NOTE: A high pulse on the RESET terminal is required in the serial interface mode when initialized through a hardware reset. For
parallel interface operation, RESET must be permanently tied high.
图 7-11. Reset Timing Diagram
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7.5 Serial Register Map
表 7-11 summarizes the functions supported by the serial interface.
表 7-11. Serial Interface Register Map
REGISTER
ADDRESS(1)
REGISTER DATA
A[7:0] (Hex)
D7
D6
D5
D4
D3
D2
D1
RESET
0
D0
READOUT
0
00
01
03
25
29
2B
0
0
0
0
0
0
LVDS SWING
0
0
0
0
0
0
0
0
0
0
0
0
HIGH PERF MODE
CH A GAIN
CH B GAIN
CH A TEST PATTERNS
DATA FORMAT
0
0
0
0
CH B TEST PATTERNS
ENABLE
OFFSET
CORR
3D
0
0
0
0
0
0
0
3F
40
41
42
CUSTOM PATTERN D[13:8]
CUSTOM PATTERN D[7:0]
LVDS CMOS
CMOS CLKOUT STRENGTH
CLKOUT RISE POSN
0
0
0
DIS OBUF
0
CLKOUT FALL POSN
EN DIGITAL
0
0
LVDS CLKOUT LVDS DATA
STRENGTH
45
4A
58
STBY
0
0
0
0
0
0
PDN GLOBAL
0
0
0
STRENGTH
HIGH FREQ
0
0
0
0
0
0
MODE CH B(2)
HIGH FREQ
0
0
MODE CH A(2)
BF
C1
CH A OFFSET PEDESTAL
CH B OFFSET PEDESTAL
0
0
0
0
FREEZE
OFFSET
CORR
CF
DB
EF
0
0
0
OFFSET CORR TIME CONSTANT
0
0
0
0
LOW SPEED
MODE CH B
0
0
0
0
0
0
0
0
EN LOW
SPEED
0
0
0
MODE(2)
F1
F2
0
0
0
0
0
0
0
0
0
0
EN LVDS SWING
LOW SPEED
0
0
MODE CH A(2)
(1) Multiple functions in a register can be programmed in a single write operation. All registers default to '0' after reset.
(2) These bits improve SFDR on high frequencies. The frequency limit is 200MHz.
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7.6 Description Of Serial Registers
7
0
6
0
5
0
4
0
3
0
2
0
1
0
RESET
READOUT
Bits[7:2]
Bit 1
Always write '0'
RESET: Software reset applied
This bit resets all internal registers to the default values and self-clears to 0 (default = 1).
READOUT: Serial readout
Bit 0
This bit sets the serial readout of the registers.
0 = Serial readout of registers disabled; the SDOUT terminal is placed in high-impedance state.
1 = Serial readout enabled; the SDOUT terminal functions as a serial data readout with CMOS logic levels running from the
DRVDD supply. See the Serial Register Readout section.
7
6
5
4
3
2
1
0
0
0
LVDS SWING
Bits[7:2]
LVDS SWING: LVDS swing programmability
These bits program the LVDS swing. Set the EN LVDS SWING bit to '1' before programming swing.
000000 = Default LVDS swing; ±350mV with external 100Ω termination
011011 = LVDS swing increases to ±410mV
110010 = LVDS swing increases to ±465mV
010100 = LVDS swing increases to ±570mV
111110 = LVDS swing decreases to ±200mV
001111 = LVDS swing decreases to ±125mV
Bits[1:0]
Always write '0'
7
0
6
0
5
0
4
0
3
0
2
0
1
0
HIGH PERF MODE
Bits[7:2]
Bits[1:0]
Always write '0'
HIGH PERF MODE: High-performance mode
00 = Default performance
01 = Do not use
10 = Do not use
11 = Obtain best performance across sample clock and input signal frequencies
7
6
5
4
3
0
2
1
0
CH A GAIN
CH A TEST PATTERNS
Bits[7:4]
CH A GAIN: Channel A gain programmability
These bits set the gain programmability in 0.5dB steps for channel A.
0000 = 0dB gain (default after reset)
0001 = 0.5dB gain
0010 = 1dB gain
0011 = 1.5dB gain
0100 = 2dB gain
0101 = 2.5dB gain
0110 = 3dB gain
0111 = 3.5dB gain
1000 = 4dB gain
1001 = 4.5dB gain
1010 = 5dB gain
1011 = 5.5dB gain
1100 = 6dB gain
Bit 3
Always write '0'
Bits[2:0]
CH A TEST PATTERNS: Channel A data capture
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These bits verify data capture for channel A.
000 = Normal operation
001 = Outputs all 0s
010 = Outputs all 1s
011 = Outputs toggle pattern.
Output data D[13:0] are an alternating sequence of 10101010101010 and 01010101010101.
100 = Outputs digital ramp.
Output data increment by one LSB (14-bit) every clock cycle from code 0 to code 16383.
101 = Outputs custom pattern; use registers 3Fh and 40h to set the custom pattern
110 = Unused
111 = Unused
7
0
6
0
5
0
4
3
2
0
1
0
0
0
DATA FORMAT
Bits[7:5]
Bits[4:3]
Always write '0'
DATA FORMAT: Data format selection
00 = Twos complement
01 = Twos complement
10 = Twos complement
11 = Offset binary
Bits[2:0]
Always write '0'
7
6
5
4
3
0
2
1
0
CH B GAIN
CH B TEST PATTERNS
Bits[7:4]
CH B GAIN: Channel B gain programmability
These bits set the gain programmability in 0.5dB steps for channel B.
0000 = 0dB gain (default after reset)
0001 = 0.5dB gain
0010 = 1dB gain
0011 = 1.5dB gain
0100 = 2dB gain
0101 = 2.5dB gain
0110 = 3dB gain
0111 = 3.5dB gain
1000 = 4dB gain
1001 = 4.5dB gain
1010 = 5dB gain
1011 = 5.5dB gain
1100 = 6dB gain
Bit 3
Always write '0'
Bits[2:0]
CH B TEST PATTERNS: Channel B data capture
These bits verify data capture for channel B.
000 = Normal operation
001 = Outputs all 0s
010 = Outputs all 1s
011 = Outputs toggle pattern.
Output data D[13:0] are an alternating sequence of 10101010101010 and 01010101010101.
100 = Outputs digital ramp.
Output data increment by one LSB (14-bit) every clock cycle from code 0 to code 16383.
101 = Outputs custom pattern; use registers 3Fh and 40h to set the custom pattern
110 = Unused
111 = Unused
7
0
6
0
5
4
0
3
0
2
0
1
0
0
0
ENABLE
OFFSET CORR
Bits[7:6]
Bit 5
Always write '0'
ENABLE OFFSET CORR: Offset correction setting
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This bit enables the offset correction.
0 = Offset correction disabled
1 = Offset correction enabled
Bits[4:0]
Always write '0'
7
0
6
0
5
4
3
2
1
0
CUSTOM
CUSTOM
CUSTOM
CUSTOM
CUSTOM
CUSTOM
PATTERN D8
PATTERN D13 PATTERN D12 PATTERN D11 PATTERN D10 PATTERN D9
Bits[7:6]
Bits[5:0]
Always write '0'
CUSTOM PATTERN D[13:8]
These are the six upper bits of the custom pattern available at the output instead of ADC data.
7
6
5
4
3
2
1
1
0
0
Bits[7:0]
CUSTOM PATTERN D[7:0]
These are the eight upper bits of the custom pattern available at the output instead of ADC data.
7
6
5
4
3
0
2
0
LVDS CMOS
CMOS CLKOUT STRENGTH
DIS OBUF
Bits[7:6]
LVDS CMOS: Interface selection
These bits select the interface.
00 = DDR LVDS interface
01 = DDR LVDS interface
10 = DDR LVDS interface
11 = Parallel CMOS interface
Bits[5:4]
CMOS CLKOUT STRENGTH
These bits control the strength of the CMOS output clock.
00 = Maximum strength (recommended)
01 = Medium strength
10 = Low strength
11 = Very low strength
Bits[3:2]
Bits[1:0]
Always write '0'
DIS OBUF
These bits power down data and clock output buffers for both the CMOS and LVDS output interface. When powered down,
the output buffers are in 3-state.
00 = Default
01 = Power-down data output buffers for channel B
10 = Power-down data output buffers for channel A
11 = Power-down data output buffers for both channels as well as the clock output buffer
7
6
5
4
3
2
0
1
0
0
0
CLKOUT FALL POSN
CLKOUT RISE POSN
EN DIGITAL
Bits[7:6] CLKOUT FALL POSN
In LVDS mode:
00 = Default
01 = The falling edge of the output clock advances by 450 ps
10 = The falling edge of the output clock advances by 150 ps
11 = The falling edge of the output clock is delayed by 550 ps
In CMOS mode:
00 = Default
01 = The falling edge of the output clock is delayed by 150 ps
10 = Do not use
11 = The falling edge of the output clock advances by 100 ps
Bits[5:6]
CLKOUT RISE POSN
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In LVDS mode:
00 = Default
01 = The rising edge of the output clock advances by 450 ps
10 = The rising edge of the output clock advances by 150 ps
11 = The rising edge of the output clock is delayed by 250 ps
In CMOS mode:
00 = Default
01 = The rising edge of the output clock is delayed by 150 ps
10 = Do not use
11 = The rising edge of the output clock advances by 100 ps
Bit 3
EN DIGITAL: Digital function enable
0 = All digital functions disabled
1 = All digital functions (such as test patterns, gain, and offset correction) enabled
Bits[2:0]
Always write '0'
7
6
5
4
0
3
0
2
1
0
0
0
LVDS CLKOUT
STRENGTH
LVDS DATA
STRENGTH
STBY
PDN GLOBAL
Bit 7
Bit 6
STBY: Standby setting
0 = Normal operation
1 = Both channels are put in standby; wakeup time from this mode is fast (typically 50µs).
LVDS CLKOUT STRENGTH: LVDS output clock buffer strength setting
0 = LVDS output clock buffer at default strength to be used with 100Ω external termination
1 = LVDS output clock buffer has double strength to be used with 50Ω external termination
Bit 5
LVDS DATA STRENGTH
0 = All LVDS data buffers at default strength to be used with 100Ω external termination
1 = All LVDS data buffers have double strength to be used with 50Ω external termination
Bits[4:3]
Bit 2
Always write '0'
PDN GLOBAL
0 = Normal operation
1 = Total power down; all ADC channels, internal references, and output buffers are powered down. Wakeup time from this
mode is slow (typically 100µs).
Bits[1:0]
Always write '0'
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
HIGH FREQ
MODE CH B
Bits[7:1]
Bit 0
Always write '0'
HIGH FREQ MODE CH B: High-frequency mode for channel B
0 = Default
1 = Use this mode for high input frequencies
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
HIGH FREQ
MODE CH A
Bits[7:1]
Bit 0
Always write '0'
HIGH FREQ MODE CH A: High-frequency mode for channel A
0 = Default
1 = Use this mode for high input frequencies
7
6
5
4
3
2
1
0
0
0
CH A OFFSET PEDESTAL
Bits[7:2]
CH A OFFSET PEDESTAL: Channel A offset pedestal selection
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When the offset correction is enabled, the final converged value after the offset is corrected is the ADC midcode value. A
pedestal can be added to the final converged value by programming these bits. See the Offset Correction section. Channels
can be independently programmed for different offset pedestals by choosing the relevant register address.
The pedestal ranges from –32 to +31, so the output code can vary from midcode-32 to midcode+32 by adding pedestal
D7-D2.
ADS4245 (Program Bits D[7:2])
011111 = Midcode+31
011110 = Midcode+30
011101 = Midcode+29
…
000000 = Midcode
111111 = Midcode-1
111110 = Midcode-2
111101 = Midcode-3
…
100000 = Midcode-32
Bits[1:0]
Always write '0'
7
6
5
4
3
2
1
0
0
0
CH B OFFSET PEDESTAL
Bits[7:2]
CH B OFFSET PEDESTAL: Channel B offset pedestal selection
When offset correction is enabled, the final converged value after the offset is corrected is the ADC midcode value. A
pedestal can be added to the final converged value by programming these bits; see the Offset Correction section. Channels
can be independently programmed for different offset pedestals by choosing the relevant register address.
The pedestal ranges from –32 to +31, so the output code can vary from midcode-32 to midcode+32 by adding pedestal
D[7:2].
ADS424x (Program Bits D[7:2])
011111 = Midcode+31
011110 = Midcode+30
011101 = Midcode+29
…
000000 = Midcode
111111 = Midcode-1
111110 = Midcode-2
111101 = Midcode-3
…
100000 = Midcode-32
Bits[1:0]
Always write '0'
7
6
0
5
4
3
2
1
0
0
0
FREEZE
OFFSET CORR
OFFSET CORR TIME CONSTANT
Bit 7
FREEZE OFFSET CORR: Freeze offset correction setting
This bit sets the freeze offset correction estimation.
0 = Estimation of offset correction is not frozen (the EN OFFSET CORR bit must be set)
1 = Estimation of offset correction is frozen (the EN OFFSET CORR bit must be set); when frozen, the last estimated value
is used for offset correction of every clock cycle. See the Offset Correction section.
Bit 6
Always write '0'
Bits[5:2]
OFFSET CORR TIME CONSTANT
The offset correction loop time constant in number of clock cycles. Refer to the Offset Correction section.
Bits[1:0]
Always write '0'
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
LOW SPEED
MODE CH B
Bits[7:1]
Always write '0'
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Bit 0
LOW SPEED MODE CH B: Channel B low-speed mode enable
This bit enables the low-speed mode for channel B. Set the EN LOW SPEED MODE bit to '1' before using this bit.
0 = Low-speed mode is disabled for channel B
1 = Low-speed mode is enabled for channel B
7
0
6
0
5
0
4
3
0
2
0
1
0
0
0
EN LOW
SPEED MODE
Bits[7:5]
Bit 4
Always write '0'
EN LOW SPEED MODE: Enable control of low-speed mode through serial register bits (ADS42x5 and ADS42x6
only)
This bit enables the control of the low-speed mode using the LOW SPEED MODE CH B and LOW SPEED MODE CH A
register bits.
0 = Low-speed mode is disabled
1 = Low-speed mode is controlled by serial register bits
Bits[3:0]
Always write '0'
7
0
6
0
5
0
4
0
3
0
2
0
1
0
EN LVDS SWING
Bits[7:2]
Bits[1:0]
Always write '0'
EN LVDS SWING: LVDS swing enable
These bits enable LVDS swing control using the LVDS SWING register bits.
00 = LVDS swing control using the LVDS SWING register bits is disabled
01 = Do not use
10 = Do not use
11 = LVDS swing control using the LVDS SWING register bits is enabled
7
0
6
0
5
0
4
0
3
2
0
1
0
0
0
LOW SPEED
MODE CH A
Bits[7:4]
Bit 3
Always write '0'
LOW SPEED MODE CH A: Channel A low-speed mode enable
This bit enables the low-speed mode for channel A. Set the EN LOW SPEED MODE bit to '1' before using this bit.
0 = Low-speed mode is disabled for channel A
1 = Low-speed mode is enabled for channel A
Bits[2:0]
Always write '0'
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8 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
8.1 Application Information
The ADS4245 belongs to TI's ultralow-power family of dual-channel 14-bit analog-to-digital converters (ADCs).
At every rising edge of the input clock, the analog input signal of each channel is simultaneously sampled. The
sampled signal in each channel is converted by a pipeline of low-resolution stages. In each stage, the sampled/
held signal is converted by a high-speed, low-resolution, flash sub-ADC. The difference between the stage input
and the quantized equivalent is gained and propagates to the next stage. At every clock, each succeeding stage
resolves the sampled input with greater accuracy. The digital outputs from all stages are combined in a digital
correction logic block and digitally processed to create the final code after a data latency of 16 clock cycles. The
digital output is available as either DDR LVDS or parallel CMOS and coded in either straight offset binary or
binary twos complement format. The dynamic offset of the first stage sub-ADC limits the maximum analog input
frequency to approximately 400MHz (with 2VPP amplitude) or approximately 600MHz (with 1VPP amplitude).
8.1.1 Clock Input
The ADS4245 clock inputs can be driven differentially (sine, LVPECL, or LVDS) or single-ended (LVCMOS), with
little or no difference in performance between them. The common-mode voltage of the clock inputs is set to VCM
using internal 5kΩ resistors. This setting allows the use of transformer-coupled drive circuits for sine-wave clock
or ac-coupling for LVPECL and LVDS clock sources are shown in 图 8-1, 图 8-2 and 图 8-3. The internal clock
buffer is shown in 图 8-4.
0.1mF
0.1mF
Zo
CLKP
CLKP
Differential
Sine-Wave
Clock Input
RT
Typical LVDS
Clock Input
100W
0.1mF
CLKM
ADS42xx
0.1mF
Zo
CLKM
A. RT = termination resister, if necessary.
ADS42xx
图 8-1. Differential Sine-Wave Clock Driving Circuit
图 8-2. LVDS Clock Driving Circuit
0.1mF
Zo
CLKP
150W
Typical LVPECL
Clock Input
100W
0.1mF
Zo
CLKM
ADS42xx
150W
图 8-3. LVPECL Clock Driving Circuit
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Clock Buffer
LPKG
2nH
20W
CLKP
CBOND
1pF
CEQ
CEQ
5kW
5kW
RESR
100W
2pF
VCM
LPKG
2nH
20W
CLKM
CBOND
1pF
RESR
100W
NOTE: CEQ is 1pF to 3pF and is the equivalent input capacitance of the clock buffer.
图 8-4. Internal Clock Buffer
A single-ended CMOS clock can be ac-coupled to the CLKP input, with CLKM connected to ground with a
0.1μF capacitor, as shown in 图 8-5. For best performance, the clock inputs must be driven differentially,
thereby reducing susceptibility to common-mode noise. For high input frequency sampling, it is recommended to
use a clock source with very low jitter. Band-pass filtering of the clock source can help reduce the effects of jitter.
There is no change in performance with a non-50% duty cycle clock input.
0.1mF
CMOS
Clock Input
CLKP
VCM
0.1mF
CLKM
ADS42xx
图 8-5. Single-Ended Clock Driving Circuit
8.2 Typical Applications
8.2.1 Analog Input
The analog input consists of a switched-capacitor based, differential sample-and-hold (S/H) architecture. This
differential topology results in very good ac performance even for high input frequencies at high sampling rates.
The INP and INM terminals must be externally biased around a common-mode voltage of 0.95V, available on the
VCM terminal. For a full-scale differential input, each input terminal (INP and INM) must swing symmetrically
between VCM + 0.5V and VCM – 0.5V, resulting in a 2VPP differential input swing. The input sampling circuit
has a high 3dB bandwidth that extends up to 550MHz (measured from the input terminals to the sampled
voltage). 图 8-6 shows an equivalent circuit for the analog input.
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Sampling
Switch
LPKG
2nH
Sampling
Capacitor
10W
RCR Filter
INP
RON
CBOND
1pF
CPAR2
1pF
CSAMP
2pF
100W
15W
RESR
3pF
200W
CPAR1
0.5pF
RON
10W
3pF
LPKG
2nH
CSAMP
2pF
100W
RON
10W
15W
INM
CBOND
1pF
CPAR2
1pF
Sampling
Capacitor
RESR
Sampling
Switch
200W
图 8-6. Analog Input Equivalent Circuit
8.2.1.1 Design Requirements for Drive Circuits
For optimum performance, the analog inputs must be driven differentially. This operation improves the common-
mode noise immunity and even-order harmonic rejection. A 5Ω to 15Ω resistor in series with each input terminal
is recommended to damp out ringing caused by package parasitics.
SFDR performance can be limited as a result of several reasons, including the effects of sampling glitches;
nonlinearity of the sampling circuit; and nonlinearity of the quantizer that follows the sampling circuit. Depending
on the input frequency, sample rate, and input amplitude, one of these factors plays a dominant part in limiting
performance. At very high input frequencies (greater than approximately 300MHz), SFDR is determined largely
by the device sampling circuit nonlinearity. At low input amplitudes, the quantizer nonlinearity usually limits
performance.
Glitches are caused by the opening and closing of the sampling switches. The driving circuit should present a
low source impedance to absorb these glitches. Otherwise, glitches could limit performance, primarily at low
input frequencies (up to approximately 200MHz). It is also necessary to present low impedance (less than 50Ω)
for the common-mode switching currents. This configuration can be achieved by using two resistors from each
input terminated to the common-mode voltage (VCM).
The device includes an internal R-C filter from each input to ground. The purpose of this filter is to absorb the
sampling glitches inside the device itself. The cutoff frequency of the R-C filter involves a trade-off. A lower cutoff
frequency (larger C) absorbs glitches better, but it reduces the input bandwidth. On the other hand, with a higher
cutoff frequency (smaller C), bandwidth support is maximized. However, the sampling glitches now must be
supplied by the external drive circuit. This tradeoff has limitations as a result of the presence of the package
bond-wire inductance.
In the ADS4245, the R-C component values have been optimized while supporting high input bandwidth (up to
550MHz). However, in applications with input frequencies up to 200MHz to 300MHz, the filtering of the glitches
can be improved further using an external R-C-R filter; see 图 8-7 and 图 8-8.
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8.2.1.2 Detailed Design Procedure
Two example driving circuit configurations are shown in 图 8-7 and 图 8-8—one optimized for low bandwidth (low
input frequencies) and the other one for high bandwidth to support higher input frequencies. Note that both of the
drive circuits have been terminated by 50Ω near the ADC side. The termination is accomplished by a 25Ω
resistor from each input to the 1.5V common-mode (VCM) from the device. This architecture allows the analog
inputs to be biased around the required common-mode voltage.
The mismatch in the transformer parasitic capacitance (between the windings) results in degraded even-order
harmonic performance. Connecting two identical RF transformers back-to-back helps minimize this mismatch;
good performance is obtained for high-frequency input signals. An additional termination resistor pair may be
required between the two transformers, as shown in 图 8-7, 图 8-8, and 图 8-9. The center point of this
termination is connected to ground to improve the balance between the P and M sides. The values of the
terminations between the transformers and on the secondary side must be chosen to obtain an effective 50Ω (in
the case of 50Ω source impedance).
0.1mF
15W
INx_P
T1
T2
0.1mF
25W
25W
25W
0.1mF
3.3pF
25W
RIN
CIN
INx_M
VCM
1:1
1:1
15W
0.1mF
ADS42xx
图 8-7. Drive Circuit With Low Bandwidth (For Low Input Frequencies Less Than 150MHz)
0.1mF
5W
INx_P
T1
T2
0.1mF
25W
25W
50W
0.1mF
3.3pF
50W
RIN
CIN
INx_M
VCM
1:1
1:1
5W
0.1mF
ADS42xx
图 8-8. Drive Circuit With High Bandwidth (For High Input Frequencies Greater Than 150MHz And Less
Than 270MHz)
0.1mF
5W
INx_P
T1
T2
0.1mF
25W
25W
0.1mF
RIN
CIN
INx_M
VCM
1:1
1:1
5W
0.1mF
ADS42xx
图 8-9. Drive Circuit With Very High Bandwidth (Greater Than 270MHz)
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All of these examples show 1:1 transformers being used with a 50Ω source. As explained in the Drive Circuit
Requirements section, this configuration helps to present a low source impedance to absorb the sampling
glitches. With a 1:4 transformer, the source impedance is 200Ω. The higher source impedance is unable to
absorb the sampling glitches effectively and can lead to degradation in performance (compared to using 1:1
transformers).
In almost all cases, either a band-pass or low-pass filter is required to obtain the desired dynamic performance,
as shown in 图 8-10. Such filters present low source impedance at the high frequencies corresponding to the
sampling glitch and help avoid the performance loss with the high source impedance.
5W
INx_P
T1
100W
Band-Pass
or
0.1mF
0.1mF
Differential
Input Signal
RIN
CIN
Low-Pass
Filter
100W
INx_M
VCM
1:4
5W
ADS42xx
图 8-10. Drive Circuit With A 1:4 Transformer
8.2.1.3 Application Curves
In addition, the drive circuit may have to be designed to provide a low insertion loss over the desired frequency
range and matched impedance to the source. Furthermore, the ADC input impedance must be considered. 图
8-11 and 图 8-12 show the impedance (ZIN = RIN || CIN) looking into the ADC input terminals.
100
5
4.5
4
10
3.5
3
1
2.5
2
0.1
0.01
1.5
1
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
Input Frequency (GHz)
1
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
Input Frequency (GHz)
1
图 8-11. ADC Analog Input Resistance (RIN) Across
图 8-12. ADC Analog Input Capacitance (CIN)
Frequency
Across Frequency
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9 Power Supply Recommendations
The recommended analog/digital power supply range for ADS4245 is 1.7V to 1.9V.
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10 Layout
10.1 Layout Guidelines
10.1.1 Grounding
A single ground plane is sufficient to give good performance, provided the analog, digital, and clock sections of
the board are cleanly partitioned. See the ADS4226 Evaluation Module (SLAU333) for details on layout and
grounding.
10.1.2 Supply Decoupling
Because the ADS4245 already includes internal decoupling, minimal external decoupling can be used without
loss in performance. Note that decoupling capacitors can help filter external power-supply noise; thus, the
optimum number of capacitors depends on the actual application. The decoupling capacitors should be placed
very close to the converter supply terminals.
10.1.3 Exposed Pad
In addition to providing a path for heat dissipation, the PowerPAD is also electrically connected internally to the
digital ground. Therefore, it is necessary to solder the exposed pad to the ground plane for best thermal and
electrical performance. For detailed information, see application notes QFN Layout Guidelines (SLOA122) and
QFN/SON PCB Attachment (SLUA271).
10.1.4 Routing Analog Inputs
It is advisable to route differential analog input pairs (INP_x and INM_x) close to each other. To minimize the
possibility of coupling from a channel analog input to the sampling clock, the analog input pairs of both channels
should be routed perpendicular to the sampling clock. See the ADS4226 Evaluation Module (SLAU333) for
reference routing.
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10.2 Layout Example
图 10-1 shows a snapshot of the PCB layout from the ADS424x EVM.
图 10-1. ADS42XX EVM PCB Layout
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Device Support
11.1.1.1 Definition Of Specifications
Analog Bandwidth – The analog input frequency at which the power of the fundamental is reduced by 3 dB
with respect to the low-frequency value.
Aperture Delay – The delay in time between the rising edge of the input sampling clock and the actual time at
which the sampling occurs. This delay is different across channels. The maximum variation is specified as
aperture delay variation (channel-to-channel).
Aperture Uncertainty (Jitter) – The sample-to-sample variation in aperture delay.
Clock Pulse Width/Duty Cycle – The duty cycle of a clock signal is the ratio of the time the clock signal
remains at a logic high (clock pulse width) to the period of the clock signal. Duty cycle is typically expressed as a
percentage. A perfect differential sine-wave clock results in a 50% duty cycle.
Maximum Conversion Rate – The maximum sampling rate at which specified operation is given. All
parametric testing is performed at this sampling rate unless otherwise noted.
Minimum Conversion Rate – The minimum sampling rate at which the ADC functions.
Differential Nonlinearity (DNL) – An ideal ADC exhibits code transitions at analog input values spaced exactly
1LSB apart. The DNL is the deviation of any single step from this ideal value, measured in units of LSBs.
Integral Nonlinearity (INL) – The INL is the deviation of the ADC transfer function from a best fit line
determined by a least squares curve fit of that transfer function, measured in units of LSBs.
Gain Error – Gain error is the deviation of the ADC actual input full-scale range from its ideal value. The gain
error is given as a percentage of the ideal input full-scale range. Gain error has two components: error as a
result of reference inaccuracy (EGREF) and error as a result of the channel (EGCHAN). Both errors are specified
independently as EGREF and EGCHAN
To a first-order approximation, the total gain error is ETOTAL ~ EGREF + EGCHAN
For example, if ETOTAL = ±0.5%, the full-scale input varies from (1 – 0.5/100) x FSideal to (1 + 0.5/100) x FSideal
.
.
.
Offset Error – The offset error is the difference, given in number of LSBs, between the ADC actual average idle
channel output code and the ideal average idle channel output code. This quantity is often mapped into
millivolts.
Temperature Drift – The temperature drift coefficient (with respect to gain error and offset error) specifies the
change per degree Celsius of the parameter from TMIN to TMAX. It is calculated by dividing the maximum
deviation of the parameter across the TMIN to TMAX range by the difference TMAX – TMIN
.
Signal-to-Noise Ratio – SNR is the ratio of the power of the fundamental (PS) to the noise floor power (PN),
excluding the power at dc and the first nine harmonics.
PS
SNR = 10Log10
PN
(1)
SNR is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the
reference, or dBFS (dB to full-scale) when the power of the fundamental is extrapolated to the converter full-
scale range.
Signal-to-Noise and Distortion (SINAD) – SINAD is the ratio of the power of the fundamental (PS) to the
power of all the other spectral components including noise (PN) and distortion (PD), but excluding dc.
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PS
SINAD = 10Log10
PN + PD
(2)
SINAD is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the
reference, or dBFS (dB to full-scale) when the power of the fundamental is extrapolated to the converter full-
scale range.
Effective Number of Bits (ENOB) – ENOB is a measure of the converter performance as compared to the
theoretical limit based on quantization noise.
SINAD - 1.76
ENOB =
6.02
(3)
Total Harmonic Distortion (THD) – THD is the ratio of the power of the fundamental (PS) to the power of the
first nine harmonics (PD).
PS
THD = 10Log10
PN
(4)
THD is typically given in units of dBc (dB to carrier).
Spurious-Free Dynamic Range (SFDR) – The ratio of the power of the fundamental to the highest other
spectral component (either spur or harmonic). SFDR is typically given in units of dBc (dB to carrier).
Two-Tone Intermodulation Distortion – IMD3 is the ratio of the power of the fundamental (at frequencies f1
and f2) to the power of the worst spectral component at either frequency 2f1 – f2 or 2f2 – f1. IMD3 is either
given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the reference, or
dBFS (dB to full-scale) when the power of the fundamental is extrapolated to the converter full-scale range.
DC Power-Supply Rejection Ratio (DC PSRR) – DC PSSR is the ratio of the change in offset error to a
change in analog supply voltage. The dc PSRR is typically given in units of mV/V.
AC Power-Supply Rejection Ratio (AC PSRR) – AC PSRR is the measure of rejection of variations in the
supply voltage by the ADC. If ΔVSUP is the change in supply voltage and ΔVOUT is the resultant change of the
ADC output code (referred to the input), then:
DVOUT
PSRR = 20Log10
(Expressed in dBc)
DVSUP
(5)
Voltage Overload Recovery – The number of clock cycles taken to recover to less than 1% error after an
overload on the analog inputs. This is tested by separately applying a sine wave signal with 6 dB positive and
negative overload. The deviation of the first few samples after the overload (from the expected values) is noted.
Common-Mode Rejection Ratio (CMRR) – CMRR is the measure of rejection of variation in the analog input
common-mode by the ADC. If ΔVCM_IN is the change in the common-mode voltage of the input terminals and
ΔVOUT is the resulting change of the ADC output code (referred to the input), then:
DVOUT
10
CMRR = 20Log
(Expressed in dBc)
DVCM
(6)
Crosstalk (only for multi-channel ADCs) – This is a measure of the internal coupling of a signal from an
adjacent channel into the channel of interest. It is specified separately for coupling from the immediate
neighboring channel (near-channel) and for coupling from channel across the package (far-channel). It is usually
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measured by applying a full-scale signal in the adjacent channel. Crosstalk is the ratio of the power of the
coupling signal (as measured at the output of the channel of interest) to the power of the signal applied at the
adjacent channel input. It is typically expressed in dBc.
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.4 Trademarks
PowerPAD™ is a trademark of Texas Instruments Incorporated.
TI E2E™ are trademarks of Texas Instruments.
所有商标均为其各自所有者的财产。
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.6 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
ADS4245MRGC25EP
V62/14609-01XE
ACTIVE
ACTIVE
VQFN
VQFN
RGC
RGC
64
64
250
250
RoHS & Green
RoHS & Green
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
-55 to 125
-55 to 125
AZ4245EP
AZ4245EP
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
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10-Dec-2020
Addendum-Page 2
GENERIC PACKAGE VIEW
RGC 64
9 x 9, 0.5 mm pitch
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224597/A
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PACKAGE OUTLINE
RGC0064H
VQFN - 1 mm max height
S
C
A
L
E
1
.
5
0
0
PLASTIC QUAD FLATPACK - NO LEAD
9.15
8.85
A
B
PIN 1 INDEX AREA
9.15
8.85
1.0
0.8
C
SEATING PLANE
0.08 C
0.05
0.00
2X 7.5
SYMM
EXPOSED
THERMAL PAD
(0.2) TYP
17
32
16
33
65
SYMM
2X 7.5
7.4 0.1
60X
0.5
1
48
0.30
0.18
64X
49
64
PIN 1 ID
0.1
C A B
0.5
0.3
64X
0.05
4219011/A 05/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
RGC0064H
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
7.4)
SEE SOLDER MASK
DETAIL
SYMM
64X (0.6)
49
64
64X (0.24)
1
48
60X (0.5)
(3.45) TYP
(R0.05) TYP
(1.16) TYP
65
SYMM
(8.8)
(
0.2) TYP
VIA
33
16
32
17
(1.16) TYP
(3.45) TYP
(8.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
METAL UNDER
SOLDER MASK
METAL EDGE
EXPOSED METAL
SOLDER MASK
OPENING
EXPOSED
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4219011/A 05/2018
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
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EXAMPLE STENCIL DESIGN
RGC0064H
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
SYMM
64X (0.6)
64
49
64X (0.24)
1
48
60X (0.5)
(R0.05) TYP
(1.16) TYP
65
SYMM
(8.8)
(0.58)
36X ( 0.96)
33
16
17
32
(0.58)
(1.16)
TYP
(8.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 MM THICK STENCIL
SCALE: 10X
EXPOSED PAD 65
61% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
4219011/A 05/2018
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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