ADS42JB46IRGC25 [TI]
Dual-Channel, 14-Bit, 160-MSPS Analog-to-Digital Converter;
| 型号： | ADS42JB46IRGC25 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Dual-Channel, 14-Bit, 160-MSPS Analog-to-Digital Converter 转换器 |
| 文件： | 总70页 (文件大小：4357K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ADS42JB49
ADS42JB69
www.ti.com
SLAS900C –OCTOBER 2012–REVISED JULY 2013
Dual-Channel, 14- and 16-Bit, 250-MSPS Analog-to-Digital Converters
Check for Samples: ADS42JB49, ADS42JB69
1
FEATURES
APPLICATIONS
2
•
•
•
•
Dual-Channel ADCs
•
•
•
•
•
•
•
•
•
Communication and Cable Infrastructure
14- and 16-Bit Resolution
Maximum Clock Rate: 250 MSPS
JESD204B Serial Interface
Multi-Carrier, Multimode Cellular Receivers
Radar and Smart Antenna Arrays
Broadband Wireless
–
–
–
Subclass 0, 1, 2 Compliant
Up to 3.125 Gbps
Test and Measurement Systems
Software-Defined and Diversity Radios
Microwave and Dual-Channel I/Q Receivers
Repeaters
Two and Four Lanes Support
•
•
Analog Input Buffer with High-Impedance Input
Flexible Input Clock Buffer:
Divide-by-1, -2, and -4
Power Amplifier Linearization
DESCRIPTION
•
Differential Full-Scale Input: 2 VPP and 2.5 VPP
(Register Programmable)
The ADS42JB69 and ADS42JB49 are high-linearity,
dual-channel, 16- and 14-bit, 250-MSPS, analog-to-
digital converters (ADCs). These devices support the
JESD204B serial interface with data rates up to
3.125 Gbps. The buffered analog input provides
uniform input impedance across a wide frequency
range while minimizing sample-and-hold glitch energy
making it easy to drive analog inputs up to very high
input frequencies. A sampling clock divider allows
more flexibility for system clock architecture design.
The devices employ internal dither algorithms to
provide excellent spurious-free dynamic range
(SFDR) over a large input frequency range.
•
•
•
•
•
•
Package: 9-mm × 9-mm QFN-64
Power Dissipation: 850 mW/Ch
Aperture Jitter: 85 fS rms
Internal Dither
Channel Isolation: 100 dB
Performance:
–
fIN = 170 MHz at 2 VPP, –1 dBFS
–
–
–
SNR: 73.3 dBFS
SFDR: 93 dBc for HD2, HD3
SFDR: 100 dBc for Non HD2, HD3
RELATED PRODUCTS
–
fIN = 170 MHz at 2.5 VPP, –1 dBFS
INTERFACE
OPTION
14-BIT,
160 MSPS
14-BIT,
250 MSPS
16-BIT,
250 MSPS
–
–
SNR: 74.7 dBFS
SFDR: 89 dBc for HD2, HD3 and
95 dBc for Non HD2, HD3
DDR,
QDR LVDS
—
ADS42LB49
ADS42JB49
ADS42LB69
ADS42JB69
JESD204B
ADS42JB46
Device
FFT for 170MHz Input Signal
OVRA
Digital
Block
0
DA0P,
DA0M
INAP,
14-, 16-Bit
Fs = 250Msps
JESD204B
Digital
ADC
Gain
INAM
Fin= 170MHz
Ain =-1dBFS
HD2 = 90dBc
HD3 = 89dBc
DA1P,
DA1M
Test Modes
-20
-40
CLKINP,
CLKINM
Divide
by 1, 2, 4
PLL
x10, x20
SYNCP,
SYNCM
Non HD2,3 = 100dBc
SYSREFP,
SYSREFM
Delay
-60
DB0P,
DB0M
Digital
Block
JESD204B
Digital
INBP,
INBM
14-, 16-Bit
ADC
DB1P,
DB1M
-80
Gain
Test Modes
OVRB
Common
Mode
-100
-120
Device Configuration
VCM
0
25
50
75
100
125
Frequency(MHz)
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
All trademarks are the property of their respective owners.
UNLESS OTHERWISE NOTED this document contains
PRODUCTION DATA information current as of publication date.
Products conform to specifications per the terms of Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2012–2013, Texas Instruments Incorporated
ADS42JB49
ADS42JB69
SLAS900C –OCTOBER 2012–REVISED JULY 2013
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION(1)
PRODUCT
ADS42JB49(2)
ADS42JB69
PACKAGE-LEAD
PACKAGE DESIGNATOR
SPECIFIED TEMPERATURE RANGE
–40°C to +85°C
QFN-64
RGC
RGC
QFN-64
–40°C to +85°C
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the
device product folder at www.ti.com.
(2) Product preview device.
ABSOLUTE MAXIMUM RATINGS
Over operating free-air temperature range, unless otherwise noted.
VALUE
–0.3 to 3.6
UNIT
AVDD3V
AVDD
V
V
V
V
V
V
V
V
V
–0.3 to 2.1
Supply voltage range
DRVDD
IOVDD
–0.3 to 2.1
–0.3 to 2.1
Voltage between AGND and DGND
–0.3 to 0.3
INAP, INBP, INAM, INBM
CLKINP, CLKINM
–0.3 to 3
–0.3 to minimum (2.1, AVDD + 0.3)
–0.3 to minimum (2.1, AVDD + 0.3)
–0.3 to minimum (2.1, AVDD + 0.3)
SYNC~P, SYNC~M
SYSREFP, SYSREFM
Voltage applied to input pins
Temperature range
SCLK, SEN, SDATA, RESET, PDN_GBL,
CTRL1, CTRL2, STBY, MODE
–0.3 to 3.9
V
Operating free-air, TA
Operating junction, TJ
Storage, Tstg
–40 to +85
+125
°C
°C
°C
kV
–65 to +150
2
Electrostatic discharge (ESD) rating Human body model (HBM)
THERMAL INFORMATION
ADS42JB49,
ADS42JB69
THERMAL METRIC(1)
UNITS
RGC (QFN)
64 PINS
22.9
θJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
θJCtop
θJB
7.1
2.5
°C/W
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.1
ψJB
2.5
θJCbot
0.2
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
2
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Product Folder Links: ADS42JB49 ADS42JB69
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ADS42JB69
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SLAS900C –OCTOBER 2012–REVISED JULY 2013
RECOMMENDED OPERATING CONDITIONS(1)
Over operating free-air temperature range, unless otherwise noted.
PARAMETER
MIN NOM
MAX
UNIT
SUPPLIES
AVDD
Analog supply voltage
1.7
3.15
1.7
1.8
3.3
1.8
1.8
1.9
3.45
1.9
V
V
V
V
AVDD3V
DRVDD
Analog buffer supply voltage
Digital supply voltage
IOVDD
Output buffer supply voltage
1.7
1.9
ANALOG INPUTS
Default after reset
Register programmable(2)
2
VPP
VPP
V
VID
Differential input voltage range
Input common-mode voltage
2.5
VICR
VCM ± 0.025
250
Maximum analog input frequency with 2.5-VPP input amplitude
Maximum analog input frequency with 2-VPP input amplitude
MHz
MHz
400
CLOCK INPUT
10x mode
Input clock sample rate
60
40
250
MSPS
MSPS
VPP
20x mode
156.25
Sine wave, ac-coupled
0.3(3)
35%
–40
1.5
1.6
LVPECL, ac-coupled
VPP
Input clock amplitude differential
(VCLKP – VCLKM
)
LVDS, ac-coupled
0.7
VPP
LVCMOS, single-ended, ac-coupled
1.5
V
Input clock duty cycle
DIGITAL OUTPUTS
50%
65%
+85
CLOAD
RLOAD
TA
Maximum external load capacitance from each output pin to DRGND
Single-ended load resistance
3.3
pF
Ω
+50
Operating free-air temperature
°C
(1) After power-up, to reset the device for the first time, use the RESET pin only. Refer to the Register Initialization section.
(2) For details, refer to the Digital Gain section.
(3) Refer to the Performance vs Clock Amplitude curves, Figure 32 and Figure 33.
Table 1. High-Frequency Modes Summary
REGISTER
ADDRESS
VALUE
90h
DESCRIPTION
Dh
Eh
High-frequency modes should be enabled for input frequencies greater than 250 MHz.
High-frequency modes should be enabled for input frequencies greater than 250 MHz.
90h
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ADS42JB69
SLAS900C –OCTOBER 2012–REVISED JULY 2013
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ELECTRICAL CHARACTERISTICS: ADS42JB69 (16-Bit)
Typical values are at TA = +25°C, AVDD = 1.8 V, AVDD3V = 3.3 V, DRVDD = 1.8 V, IOVDD = 1.8 V, 50% clock duty cycle,
–1-dBFS differential analog input, and sampling rate = 250 MSPS, unless otherwise noted. Minimum and maximum values
are across the full temperature range of TMIN = –40°C to TMAX = +85°C, AVDD = 1.8 V, AVDD3V = 3.3 V, DRVDD = 1.8 V,
and IOVDD = 1.8 V.
2-VPP FULL-SCALE
2.5-VPP FULL-SCALE
PARAMETER
TEST CONDITIONS
UNITS
MIN
TYP
74
MAX
MIN
TYP
75.9
75.6
74.7
74
MAX
fIN = 10 MHz
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBc
fIN = 70 MHz
fIN = 170 MHz
fIN = 230 MHz
fIN = 10 MHz
fIN = 70 MHz
fIN = 170 MHz
fIN = 230 MHz
fIN = 10 MHz
fIN = 70 MHz
fIN = 170 MHz
fIN = 230 MHz
fIN = 10 MHz
fIN = 70 MHz
fIN = 170 MHz
fIN = 230 MHz
fIN = 10 MHz
fIN = 70 MHz
fIN = 170 MHz
fIN = 230 MHz
fIN = 10 MHz
fIN = 70 MHz
fIN = 170 MHz
fIN = 230 MHz
fIN = 10 MHz
fIN = 70 MHz
fIN = 170 MHz
fIN = 230 MHz
73.8
73.3
72.6
73.9
73.7
73.2
72.2
95
SNR
Signal-to-noise ratio
70.8
75.7
75.3
74.5
73.1
90
SINAD Signal-to-noise and distortion ratio
69.6
81
Spurious-free dynamic range
SFDR (including second and third
harmonic distortion)
91
88
dBc
93
89
dBc
84
82
dBc
92
88
dBc
89
86
dBc
THD
HD2
HD3
Total harmonic distortion
78
91
86
dBc
82
80
dBc
95
95
dBc
91
88
dBc
2nd-order harmonic distortion
3rd-order harmonic distortion
81
93
94
dBc
84
82
dBc
95
90
dBc
96
93
dBc
81
94
89
dBc
86
84
dBc
102
103
100
99
102
103
95
dBc
Worst spur
(other than second and third
harmonics)
dBc
87
dBc
93
dBc
f1 = 46 MHz, f2 = 50 MHz,
each tone at –7 dBFS
97
90
95
89
dBFS
dBFS
Two-tone intermodulation
distortion
IMD
f1 = 185 MHz, f2 = 190 MHz,
each tone at –7 dBFS
20-MHz, full-scale signal on
channel under observation;
170-MHz, full-scale signal on
other channel
Crosstalk
100
100
dB
Recovery to within 1% (of full-
scale) for 6-dB overload with sine-
wave input
Clock
cycle
Input overload recovery
1
1
For 50-mVPP signal on AVDD
supply, up to 10 MHz
PSRR AC power-supply rejection ratio
ENOB Effective number of bits
> 40
> 40
dB
fIN = 170 MHz
fIN = 170 MHz
fIN = 170 MHz
11.9
±0.6
±3
12.1
±0.6
±3.5
LSBs
LSBs
LSBs
DNL
INL
Differential nonlinearity
Integrated nonlinearity
±8
4
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Product Folder Links: ADS42JB49 ADS42JB69
ADS42JB49
ADS42JB69
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SLAS900C –OCTOBER 2012–REVISED JULY 2013
ELECTRICAL CHARACTERISTICS: ADS42JB49 (14-Bit)
Typical values are at TA = +25°C, AVDD = 1.8 V, AVDD3V = 3.3 V, DRVDD = 1.8 V, IOVDD = 1.8 V, 50% clock duty cycle,
–1-dBFS differential analog input, and sampling rate = 250 MSPS, unless otherwise noted. Minimum and maximum values
are across the full temperature range of TMIN = –40°C to TMAX = +85°C, AVDD = 1.8 V, AVDD3V = 3.3 V, DRVDD = 1.8 V,
and IOVDD = 1.8 V.
2-VPP FULL-SCALE
2.5-VPP FULL-SCALE
PARAMETER
TEST CONDITIONS
UNITS
MIN
TYP
73.4
73.2
72.7
72.2
73.3
73.1
72.7
71.8
95
MAX
MIN
TYP
75
MAX
fIN = 10 MHz
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBc
fIN = 70 MHz
fIN = 170 MHz
fIN = 230 MHz
fIN = 10 MHz
fIN = 70 MHz
fIN = 170 MHz
fIN = 230 MHz
fIN = 10 MHz
fIN = 70 MHz
fIN = 170 MHz
fIN = 230 MHz
fIN = 10 MHz
fIN = 70 MHz
fIN = 170 MHz
fIN = 230 MHz
fIN = 10 MHz
fIN = 70 MHz
fIN = 170 MHz
fIN = 230 MHz
fIN = 10 MHz
fIN = 70 MHz
fIN = 170 MHz
fIN = 230 MHz
fIN = 10 MHz
fIN = 70 MHz
fIN = 170 MHz
fIN = 230 MHz
74.7
74
SNR
Signal-to-noise ratio
69.5
73.4
74.8
74.5
73.8
72.6
90
SINAD Signal-to-noise and distortion ratio
68.5
79
Spurious-free dynamic range
SFDR (including second and third
harmonic distortion)
91
88
dBc
93
89
dBc
84
82
dBc
92
88
dBc
89
86
dBc
THD
HD2
HD3
Total harmonic distortion
76
90
86
dBc
82
80
dBc
95
95
dBc
91
88
dBc
2nd-order harmonic distortion
3rd-order harmonic distortion
79
93
94
dBc
84
82
dBc
95
90
dBc
96
93
dBc
79
94
89
dBc
86
84
dBc
102
103
101
99
102
103
95
dBc
Worst spur
(other than second and third
harmonics)
dBc
87
dBc
93
dBc
f1 = 46 MHz, f2 = 50 MHz,
each tone at –7 dBFS
97
90
95
89
dBFS
dBFS
Two-tone intermodulation
distortion
IMD
f1 = 185 MHz, f2 = 190 MHz,
each tone at –7 dBFS
20-MHz, full-scale signal on
channel under observation;
170-MHz, full-scale signal on
other channel
Crosstalk
100
100
dB
Recovery to within 1% (of full-
scale) for 6-dB overload with sine-
wave input
Clock
cycle
Input overload recovery
1
1
For a 50-mVPP signal on AVDD
supply, up to 10 MHz
PSRR AC power-supply rejection ratio
ENOB Effective number of bits
> 40
> 40
dB
fIN = 170 MHz
fIN = 170 MHz
fIN = 170 MHz
11.8
±0.15
±0.75
12
±0.15
±0.9
LSBs
LSBs
LSBs
DNL
INL
Differential nonlinearity
Integrated nonlinearity
±2
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ELECTRICAL CHARACTERISTICS: GENERAL
Typical values are at +25°C, AVDD = 1.8 V, AVDD3V = 3.3 V, DRVDD = 1.8 V, IOVDD = 1.8 V, 50% clock duty cycle, –1-
dBFS differential analog input, and sampling rate = 250 MSPS, unless otherwise noted. Minimum and maximum values are
across the full temperature range: TMIN = –40°C to TMAX = +85°C, AVDD = 1.8 V, AVDD3V = 3.3 V, DRVDD = 1.8 V, and
IOVDD = 1.8 V.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ANALOG INPUTS
Default (after reset)
Register programmed(1)
2
2.5
1.2
4
VPP
VPP
kΩ
Differential input voltage
range
VID
Differential input resistance (at 170 MHz)
Differential input capacitance (at 170 MHz)
pF
With 50-Ω source impedance, and 50-Ω
termination
Analog input bandwidth
900
MHz
VCM
Common-mode output voltage
VCM output current capability
1.9
10
V
mA
DC ACCURACY
Offset error
–20
20
mV
Gain error as a result of
internal reference inaccuracy
alone
EGREF
±2
%FS
EGCHAN
Gain error of channel alone
–5
%FS
Temperature coefficient of
EGCHAN
0.01
Δ%/°C
POWER SUPPLY
IAVDD
Analog supply current
128
290
228
160
330
252
mA
mA
mA
IAVDD3V
IDRVDD
Analog buffer supply current
Digital supply current
50-Ω external termination from pin to IOVDD,
fIN = 2.5 MHz
IOVDD
Output buffer supply current
60
100
mA
Analog power
231
957
410
mW
mW
mW
Analog buffer power
Digital power
Power consumption by output 50-Ω external termination from pin to IOVDD,
109
1.7
mW
buffer
fIN = 2.5 MHz
Total power
Global power-down
1.96
160
W
mW
(1) Refer to the Serial Interface section.
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SLAS900C –OCTOBER 2012–REVISED JULY 2013
TIMING CHARACTERISTICS
Typical values are at +25°C, AVDD = 1.8 V, AVDD3V = 3.3 V, DRVDD = 1.8 V, IOVDD = 1.8 V, 50% clock duty cycle, –1-
dBFS differential analog input, and sampling rate = 250 MSPS, unless otherwise noted. Minimum and maximum values are
across the full temperature range: TMIN = –40°C to TMAX = +85°C, AVDD = 1.8 V, AVDD3V = 3.3 V, DRVDD = 1.8 V, and
IOVDD = 1.8 V. See Figure 1.
PARAMETER
SAMPLE TIMING CHARACTERISTICS
Aperture delay
TEST CONDITIONS
MIN
TYP
MAX
UNITS
0.4
0.7
1.1
ns
ps
Between two channels on the same device
±70
Aperture delay matching
Between two devices at the same temperature and supply
voltage
±150
ps
Aperture jitter
Wake-up time
85
50
fS rms
µs
Time to valid data after coming out of STANDBY mode
Time to valid data after coming out of global power-down
Referenced to input clock rising edge
200
250
1000
µs
tSU_SYNC~
tH_SYNC~
tSU_SYSREF
tH_SYSREF
Setup time for SYNC~
Hold time for SYNC~
Setup time for SYSREF
Hold time for SYSREF
400
100
400
100
ps
Referenced to input clock rising edge
ps
Referenced to input clock rising edge
ps
Referenced to input clock rising edge
ps
CML OUTPUT TIMING CHARACTERISTICS
Unit interval
320
1667
ps
Serial output data rate
3.125
Gbps
P-PUI
P-PUI
2.5 Gbps (10x mode, fS = 250 MSPS)
0.28
0.3
Total jitter
3.125 Gbps (20x mode, fS = 156.25 MSPS)
Rise and fall times measured from 20% to 80%,
differential output waveform,
600 Mbps ≤ bit rate ≤ 3.125 Gbps
Data rise time,
data fall time
tR, tF
105
ps
Table 2. Latency in Different Modes(1)(2)
MODE
PARAMETER
LATENCY (N Cycles)
TYPICAL DATA DELAY (tD, ns)
ADC latency
23
14
9
0.65 × tS + 3
6.7
Normal OVR latency
10x
Fast OVR latency
6.7
from SYNC~ falling edge to CGS phase(3)
from SYNC~ rising edge to ILA sequence(4)
16
25
0.65 × tS + 3
0.65 × tS + 3
ADC latency
22
14
9
0.85 × tS + 3
6.7
Normal OVR latency
20x
Fast OVR latency
6.7
from SYNC~ falling edge to CGS phase(3)
from SYNC~ rising edge to ILA sequence(4)
15
16
0.85 × tS + 3
0.85 × tS + 3
(1) Overall latency = latency + tD.
(2) tS is the time period of the ADC conversion clock.
(3) Latency is specified for subclass 2. In subclass 0, the SYNC~ falling edge to CGS phase latency is 16 clock cycles in 10x mode and 15
clock cycles in 20x mode.
(4) Latency is specified for subclass 2. In subclass 0, the SYNC~ rising edge to ILA sequence latency is 11 clock cycles in 10x mode and
11 clock cycles in 20x mode.
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TIMING DIAGRAMS
N + Latency + 2
N + 4
N + 3
N + Latency + 1
N + Latency
N + 2
Sample
N
N + 1
tA
CLKP
CLKM
Input
Clock
ADC Latency(1)
tD
Dx0P, Dx0M(2)
N - Latency-1
N + Latency
N - Latency+1 N - Latency+2 N - Latency+3
N - Latency+1 N - Latency+2 N - Latency+3
Figure 1. ADC Latency
N - 1
N
N + 1
N + 1
Dx1P, Dx1M(2)
N - Latency-1
N + Latency
N - 1
N
N + 1
N + 1
(1) Overall latency = ADC latency + tD.
(2) x = A for channel A and B for channel B.
CLKINP
Input
Clock
CLKINM
tSU_SYNC~
tH_SYNC~
SYNC~
tD
SYNC~ Asserted Latency
CGS Phase
Dx0P, Dx0M(1)
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
K28.5
K28.5
Dx1P, Dx1M(1)
Data
(1) x = A for channel A and B for channel B.
Figure 2. SYNC~ Latency in CGS Phase (Two-Lane Mode)
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TIMING DIAGRAMS (continued)
CLKINP
Input
Clock
CLKINM
tSU_SYNC~
tH_SYNC~
SYNC~
tD
SYNC~ Deasserted Latency
ILA Sequence
Dx0P, Dx0M(1)
K28.5
K28.5
K28.5
K28.5
K28.5
K28.5
K28.5
K28.5
K28.5
K28.5
K28.5
K28.5
K28.5
K28.5
K28.5
K28.0
K28.0
K28.0
K28.0
Dx1P, Dx1M(1)
K28.5
(1) x = A for channel A and B for channel B.
Figure 3. SYNC~ Latency in ILAS Phase (Two-Lane Mode)
Sample N
Sample N
tSU_SYSREF
tSU_SYNC~
tH_SYSREF
tH_SYNC~
CLKIN
CLKIN
SYSREF
SYNC~
Figure 4. SYSREF Timing (Subclass 1)
Figure 5. SYNC~ Timing (Subclass 2)
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DIGITAL CHARACTERISTICS
The dc specifications refer to the condition where the digital outputs are not switching, but are permanently at a valid logic
level '0' or '1'. AVDD = 1.8 V, AVDD3V = 3.3 V, DRVDD = 1.8 V, and IOVDD = 1.8 V, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNITS
DIGITAL INPUTS (RESET, SCLK, SEN, SDATA, PDN_GBL, STBY, CTRL1, CTRL2, MODE)(1)
All digital inputs support 1.8-V and 3.3-V logic
High-level input voltage
levels
1.2
V
All digital inputs support 1.8-V and 3.3-V logic
Low-level input voltage
levels
0.4
V
SEN
0
10
10
0
µA
µA
µA
µA
High-level input current
Low-level input current
RESET, SCLK, SDATA, PDN_GBL, STBY,
CTRL1, CTRL2, MODE
SEN
RESET, SCLK, SDATA, PDN_GBL, STBY,
CTRL1, CTRL2, MODE
DIGITAL INPUTS (SYNC~P, SYNC~M, SYSREFP, SYSREFM)
High-level input voltage
1.3
0.5
0.9
V
V
V
Low-level input voltage
VCM_DIG
Input common-mode voltage
DIGITAL OUTPUTS (SDOUT, OVRA, OVRB)
DRVDD
– 0.1
High-level output voltage
DRVDD
V
V
Low-level output voltage
DIGITAL OUTPUTS (JESD204B Interface: DA[0,1], DB[0,1])(2)
High-level output voltage
0.1
IOVDD
V
V
V
V
Low-level output voltage
IOVDD – 0.4
0.4
|VOD
|
Output differential voltage
VOCM
Output common-mode voltage
IOVDD – 0.2
Transmitter terminals shorted to any voltage
between –0.25 V and 1.45 V
Transmitter short-circuit current
Single-ended output impedance
Output capacitance
–100
100
mA
Ω
50
2
Output capacitance inside the device,
from either output to ground
pF
(1) RESET, SCLK, SDATA, PDN_GBL, STBY, CTRL1, CTRL2 and MODE pins have 150-kΩ (typical) internal pull-down resistor to ground,
while SEN pin has 150-kΩ (typical) pull-up resistor to AVDD.
(2) 50-Ω, single-ended external termination to IOVDD.
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PINOUT INFORMATION
RGC PACKAGE
QFN-64
(Top View)
DGND
DRVDD
DGND
1
2
48 DGND
47 DRVDD
46 DGND
45 SDOUT
44 RESET
43 SCLK
42 SDATA
41 SEN
3
MODE
STBY
4
5
6
PDN_GBL
DRVDD
SYNC~M
SYNC~P
CTRL2
AVDD
7
8
Thermal Pad
9
40 AVDD
39 CTRL1
38 AVDD
37 AGND
36 INAP
10
11
12
13
14
15
16
AGND
INBP
35 INAM
34 AGND
33 AVDD
INBM
AGND
AVDD
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PIN ASSIGNMENTS: JESD204B Output Interface
NAME
PIN NO.
I/O
FUNCTION
DESCRIPTION
12, 15, 19, 20,
23, 26, 28, 34,
37
AGND
I
Supply
Analog ground
11, 16, 18, 22,
27, 31, 33, 38,
40
AVDD
I
Supply
1.8-V analog power supply
AVDD3V
CLKINM
CLKINP
CTRL1
17, 32
24
I
I
Supply
Clock
3.3-V analog supply for analog buffer
Differential ADC clock input
25
I
Clock
Differential ADC clock input
39
I
Control
Control
Interface
Interface
Interface
Interface
Power-down control with an internal 150-kΩ pull-down resistor
Power-down control with an internal 150-kΩ pull-down resistor
JESD204B serial data output for channel A, lane 0
JESD204B serial data output for channel A, lane 1
JESD204B serial data output for channel B, lane 0
JESD204B serial data output for channel B, lane 1
CTRL2
10
I
DA0P/M
DA1P/M
DB0P/M
DB1P/M
54, 53
52,51
56,57
58,59
O
O
O
O
1, 3, 46, 48,
50, 63
DGND
I
I
Supply
Supply
Digital ground
2, 7, 47, 49,
60, 64
DRVDD
Digital 1.8-V power supply
INAM
INAP
35
36
14
13
55
4
I
Input
Input
Differential analog input for channel A
I
Differential analog input for channel A
INBM
I
Input
Differential analog input for channel B
INBP
I
Input
Differential analog input for channel B
IOVDD
MODE
I
Supply
Control
Interface
Interface
Control
Control
Control
Control
Control
Control
Control
Interface
Interface
Clock
Digital 1.8-V power supply for the JESD204B transmitter
Connect to GND
I
OVRA
61
62
6
O
Overrange indication channel A in CMOS output format.
Overrange indication channel B in CMOS output format.
OVRB
O
PDN_GBL
RESET
SCLK
I
Global power down. Active high with an internal 150-kΩ pull-down resistor.
Hardware reset; active high. This pin has an internal 150-kΩ pull-down resistor.
Serial interface clock input. This pin has an internal 150-kΩ pull-down resistor.
Serial interface data input. This pin has an internal 150-kΩ pull-down resistor.
Serial interface data output
44
43
42
45
41
5
I
I
SDATA
SDOUT
SEN
I
O
I
Serial interface enable. This pin has an internal 150-kΩ pull-up resistor.
Standby. Active high with an internal 150-kΩ pull-down resistor.
Synchronization input for JESD204B port
STBY
I
SYNC~P
SYNC~M
SYSREFM
SYSREFP
VCM
9
I
8
I
Synchronization input for JESD204B port
30
29
21
65
I
I
External SYSREF input (subclass 1)
Clock
External SYSREF input (subclass 1)
O
Output
Ground
1.9-V common-mode output voltage for analog inputs
Connect to ground plane
Thermal Pad
GND
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TYPICAL CHARACTERISTICS: ADS42JB69
Typical values are at TA = +25°C, ADC sampling rate = 250 MSPS, 50% clock duty cycle, AVDD = 1.8 V, AVDD3V = 3.3 V,
DRVDD = 1.8 V, IOVDD = 1.8 V, –1-dBFS differential input, 2-VPP full-scale, and 32k-point FFT, unless otherwise noted.
0
0
fIN = 10 MHz
fIN = 170 MHz
SFDR = 96 dBc
SNR = 74 dBFS
SINAD = 73.9 dBFS
THD = 94 dBc
SFDR = 88 dBc
SNR = 73.3 dBFS
SINAD = 73 dBFS
THD = 87 dBc
−20
−20
SFDR Non HD2, HD3
SFDR Non HD2, HD3
= 102 dBc
= 101 dBc
−40
−40
−60
−60
−80
−80
−100
−120
−100
−120
0
25
50
75
100
125
0
25
50
75
100
125
Frequency (MHz)
Frequency (MHz)
G001
G002
Figure 6. FFT FOR 10-MHz INPUT SIGNAL
Figure 7. FFT FOR 170-MHz INPUT SIGNAL
0
−20
0
−20
fIN = 300 MHz
fIN = 10 MHz
SFDR = 74 dBc
SNR = 72.4 dBFS
SINAD = 69.9 dBFS
THD = 73 dBc
SFDR Non HD2,HD3
= 96
SFDR = 90 dBc
SNR = 75.8 dBFS
SINAD = 75.7 dBFS
THD = 89 dBc
SFDR Non HD2, HD3
= 105 dBc
−40
−40
−60
−60
−80
−80
−100
−120
−100
−120
0
25
50
75
100
125
0
25
50
75
100
125
Frequency (MHz)
Frequency (MHz)
G003
G004
Figure 8. FFT FOR 300-MHz INPUT SIGNAL
Figure 9. FFT FOR 10-MHz INPUT SIGNAL
(2.5-VPP Full-Scale)
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TYPICAL CHARACTERISTICS: ADS42JB69 (continued)
Typical values are at TA = +25°C, ADC sampling rate = 250 MSPS, 50% clock duty cycle, AVDD = 1.8 V, AVDD3V = 3.3 V,
DRVDD = 1.8 V, IOVDD = 1.8 V, –1-dBFS differential input, 2-VPP full-scale, and 32k-point FFT, unless otherwise noted.
0
0
fIN = 170 MHz
fIN = 300 MHz
SFDR = 87 dBc
SNR = 74.7 dBFS
SINAD = 74.4 dBFS
THD = 84 dBc
SFDR = 71 dBc
SNR = 73.4 dBFS
SINAD = 69 dBFS
THD = 70 dBc
−20
−20
SFDR Non HD2, HD3
SFDR Non HD2, HD3
= 94 dBc
= 94 dBc
−40
−40
−60
−60
−80
−80
−100
−120
−100
−120
0
25
50
75
100
125
0
25
50
75
100
125
Frequency (MHz)
Frequency (MHz)
G005
G006
Figure 10. FFT FOR 170-MHz INPUT SIGNAL
(2.5-VPP Full-Scale)
Figure 11. FFT FOR 300-MHz INPUT SIGNAL
(2.5-VPP Full-Scale)
0
−20
0
−20
Each Tone at
−7 dBFS Amplitude
fIN1 = 46 MHz
fIN2 = 50 MHz
Each Tone at
−36 dBFS Amplitude
fIN1 = 46 MHz
fIN2 = 50 MHz
2−Tone IMD = 98 dBFS
SFDR = 105 dBFS
2−Tone IMD = 101 dBFS
SFDR = 106 dBFS
−40
−40
−60
−60
−80
−80
−100
−120
−100
−120
0
25
50
75
100
125
0
25
50
75
100
125
Frequency (MHz)
Frequency (MHz)
G007
G007
Figure 12. FFT FOR TWO-TONE INPUT SIGNAL
(–7 dBFS at 46 MHz and 50 MHz)
Figure 13. FFT FOR TWO-TONE INPUT SIGNAL
(–36 dBFS at 46 MHz and 50 MHz)
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TYPICAL CHARACTERISTICS: ADS42JB69 (continued)
Typical values are at TA = +25°C, ADC sampling rate = 250 MSPS, 50% clock duty cycle, AVDD = 1.8 V, AVDD3V = 3.3 V,
DRVDD = 1.8 V, IOVDD = 1.8 V, –1-dBFS differential input, 2-VPP full-scale, and 32k-point FFT, unless otherwise noted.
0
0
Each Tone at
Each Tone at
−7 dBFS Amplitude
fIN1 = 185 MHz
fIN2 = 190 MHz
−36 dBFS Amplitude
fIN1 = 185 MHz
fIN2 = 190 MHz
−20
−20
2−Tone IMD = 90 dBFS
SFDR = 102 dBFS
2−Tone IMD = 101 dBFS
SFDR = 104 dBFS
−40
−40
−60
−60
−80
−80
−100
−120
−100
−120
0
25
50
75
100
125
0
25
50
75
100
125
Frequency (MHz)
Frequency (MHz)
G009
G010
Figure 14. FFT FOR TWO-TONE INPUT SIGNAL
(–7 dBFS at 185 MHz and 190 MHz)
Figure 15. FFT FOR TWO-TONE INPUT SIGNAL
(–36 dBFS at 185 MHz and 190 MHz)
−98
−100
−102
−104
−106
−108
−110
−90
−92
fIN1 = 46 MHz
fIN2 = 50 MHz
fIN1 = 185 MHz
fIN2 = 190 MHz
−94
−96
−98
−100
−102
−104
−106
−108
−110
−36 −33 −30 −27 −24 −21 −18 −15 −12 −9 −7
−36 −33 −30 −27 −24 −21 −18 −15 −12 −9 −7
Each Tone Amplitude (dBFS)
Each Tone Amplitude (dBFS)
G011
G001
Figure 16. INTERMODULATION DISTORTION vs
INPUT AMPLITUDE (46 MHz and 50 MHz)
Figure 17. INTERMODULATION DISTORTION vs
INPUT AMPLITUDE (185 MHz and 190 MHz)
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TYPICAL CHARACTERISTICS: ADS42JB69 (continued)
Typical values are at TA = +25°C, ADC sampling rate = 250 MSPS, 50% clock duty cycle, AVDD = 1.8 V, AVDD3V = 3.3 V,
DRVDD = 1.8 V, IOVDD = 1.8 V, –1-dBFS differential input, 2-VPP full-scale, and 32k-point FFT, unless otherwise noted.
100
95
90
85
80
75
70
65
60
55
77
76
75
74
73
72
71
70
2−VPP Full−Scale
2.5−VPP Full−Scale
2−VPP Full−Scale
2.5−VPP Full−Scale
0
50
100
150
200
250
300
350
400
0
50
100
150
200
250
300
350
400
Input Frequency (MHz)
Input Frequency (MHz)
G013
G014
Figure 18. SPURIOUS-FREE DYNAMIC RANGE vs
INPUT FREQUENCY
Figure 19. SIGNAL-TO-NOISE RATIO vs
INPUT FREQUENCY
120
110
100
90
80
78
76
74
72
70
68
66
10 MHz
70 MHz
100 MHz
130 MHz
170 MHz
230 MHz
270 MHz
350 MHz
400 MHz
491 MHz
10 MHz
70 MHz
100 MHz
130 MHz
170 MHz
230 MHz
270 MHz
350 MHz
400 MHz
491 MHz
80
70
60
−2−1.5−1−0.5 0 0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
−2−1.5−1−0.5 0 0.5
1
1.5
2 2.5 3 3.5 4 4.5 5 5.5 6
Digital Gain (dB)
Digital Gain (dB)
G015
G016
Figure 20. SPURIOUS-FREE DYNAMIC RANGE vs
DIGITAL GAIN
Figure 21. SIGNAL-TO-NOISE RATIO vs
DIGITAL GAIN
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TYPICAL CHARACTERISTICS: ADS42JB69 (continued)
Typical values are at TA = +25°C, ADC sampling rate = 250 MSPS, 50% clock duty cycle, AVDD = 1.8 V, AVDD3V = 3.3 V,
DRVDD = 1.8 V, IOVDD = 1.8 V, –1-dBFS differential input, 2-VPP full-scale, and 32k-point FFT, unless otherwise noted.
77
76.5
76
130
120
110
100
90
77.5
130
120
110
100
90
Input Frequency = 70 MHz
SNR(dBFS)
SFDR(dBc)
SFDR(dBFS)
Input Frequency = 170 MHz
SNR(dBFS)
SFDR(dBc)
SFDR(dBFS)
77
76.5
76
75.5
75
75.5
75
74.5
74
80
80
70
74.5
74
70
73.5
73
60
60
50
73.5
73
50
72.5
72
40
40
30
72.5
30
71.5
20
72
−70
20
−70
−60
−50
−40
−30
−20
−10
0
−60
−50
−40
−30
−20
−10
0
Amplitude (dBFS)
Amplitude (dBFS)
G017
G018
Figure 22. PERFORMANCE vs INPUT AMPLITUDE
(70 MHz)
Figure 23. PERFORMANCE vs INPUT AMPLITUDE
(170 MHz)
99
96
94
92
89
86
84
82
76
101
98
95
92
89
86
83
80
75.5
Input Frequency = 70 MHz
SFDR
SNR
Input Frequency = 170 MHz
SFDR
SNR
75.5
75
75
74.5
74
74.5
74
73.5
73
73.5
73
72.5
72.5
1.95
72
1.95
1.85
1.87
1.9
1.93
1.85
1.87
1.9
1.93
Input Common−Mode Voltage (V)
Input Common−Mode Voltage (V)
G019
G020
Figure 24. PERFORMANCE vs
INPUT COMMON-MODE VOLTAGE (70 MHz)
Figure 25. PERFORMANCE vs
INPUT COMMON-MODE VOLTAGE (170 MHz)
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TYPICAL CHARACTERISTICS: ADS42JB69 (continued)
Typical values are at TA = +25°C, ADC sampling rate = 250 MSPS, 50% clock duty cycle, AVDD = 1.8 V, AVDD3V = 3.3 V,
DRVDD = 1.8 V, IOVDD = 1.8 V, –1-dBFS differential input, 2-VPP full-scale, and 32k-point FFT, unless otherwise noted.
99
98
97
96
95
94
93
92
91
90
89
88
87
75
74.5
74
AVDD = 1.7 V
AVDD = 1.75 V
AVDD = 1.8 V
AVDD = 1.85 V
AVDD = 1.9 V
AVDD = 1.7 V
AVDD = 1.75V
AVDD = 1.8 V
AVDD = 1.85 V
AVDD = 1.9 V
73.5
73
72.5
72
Input Frequency = 170 MHz
−15 10
Temperature (°C)
Input Frequency = 170 MHz
−15 10
Temperature (°C)
−40
35
60
85
−40
35
60
85
G021
G022
Figure 26. SPURIOUS-FREE DYNAMIC RANGE vs
AVDD SUPPLY AND TEMPERATURE (170 MHz)
Figure 27. SIGNAL-TO-NOISE RATIO vs
AVDD SUPPLY AND TEMPERATURE (170 MHz)
98
97
96
95
94
93
92
91
90
89
88
87
75
74.5
74
AVDD3V = 3.15 V
AVDD3V = 3.2 V
AVDD3V = 3.25 V
AVDD3V = 3.3 V
AVDD3V = 3.35 V
AVDD3V = 3.4 V
AVDD3V = 3.45 V
AVDD3V = 3.15 V
AVDD3V = 3.2 V
AVDD3V = 3.25 V
AVDD3V = 3.3 V
AVDD3V = 3.35 V
AVDD3V = 3.4 V
AVDD3V = 3.45 V
73.5
73
72.5
72
Input Frequency = 170 MHz
−15 10
Temperature (°C)
Input Frequency = 170 MHz
−15 10
Temperature (°C)
−40
35
60
85
−40
35
60
85
G023
G024
Figure 28. SPURIOUS-FREE DYNAMIC RANGE vs
AVDD_BUF SUPPLY AND TEMPERATURE (170 MHz)
Figure 29. SIGNAL-TO-NOISE RATIO vs
AVDD_BUF SUPPLY AND TEMPERATURE (170 MHz)
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TYPICAL CHARACTERISTICS: ADS42JB69 (continued)
Typical values are at TA = +25°C, ADC sampling rate = 250 MSPS, 50% clock duty cycle, AVDD = 1.8 V, AVDD3V = 3.3 V,
DRVDD = 1.8 V, IOVDD = 1.8 V, –1-dBFS differential input, 2-VPP full-scale, and 32k-point FFT, unless otherwise noted.
97
96
95
94
93
92
91
90
89
88
75
74.5
74
DRVDD = 1.7 V
DRVDD = 1.75 V
DRVDD = 1.8 V
DRVDD = 1.85 V
DRVDD = 1.9 V
DRVDD = 1.7 V
DRVDD = 1.75 V
DRVDD = 1.8 V
DRVDD = 1.85 V
DRVDD = 1.9 V
73.5
73
72.5
72
Input Frequency = 170 MHz
−15 10
Temperature (°C)
Input Frequency = 170 MHz
−15 10
Temperature (°C)
−40
35
60
85
−40
35
60
85
G025
G026
Figure 30. SPURIOUS-FREE DYNAMIC RANGE vs
DRVDD SUPPLY AND TEMPERATURE (170 MHz)
Figure 31. SIGNAL-TO-NOISE RATIO vs
DRVDD SUPPLY AND TEMPERATURE (170 MHz)
96
94
92
90
88
86
84
77
96
94
92
90
88
86
84
82
80
Input Frequency = 70 MHz
SFDR
SNR
Input Frequency =170 MHz
SFDR
SNR
78
76
74
72
70
68
66
76
75
74
73
72
71
0.1 0.3 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 2.1
0.1 0.3 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 2.1
Differential Clock Amplitudes (Vpp)
Differential Clock Amplitudes (Vpp)
G027
G028
Figure 32. PERFORMANCE vs CLOCK AMPLITUDE
(70 MHz)
Figure 33. PERFORMANCE vs CLOCK AMPLITUDE
(170 MHz)
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TYPICAL CHARACTERISTICS: ADS42JB69 (continued)
Typical values are at TA = +25°C, ADC sampling rate = 250 MSPS, 50% clock duty cycle, AVDD = 1.8 V, AVDD3V = 3.3 V,
DRVDD = 1.8 V, IOVDD = 1.8 V, –1-dBFS differential input, 2-VPP full-scale, and 32k-point FFT, unless otherwise noted.
96
94
92
90
88
86
84
82
78
77
76
75
74
73
72
71
96
94
92
90
88
86
84
77
76
75
74
73
72
71
Input Frequency = 70 MHz
SNR
SFDR
Input Frequency = 170 MHz
SNR
SFDR
30
40
50
Input Clock Duty Cycle (%)
60
70
30
40
50
Input Clock Duty Cycle (%)
60
70
G029
G030
Figure 34. PERFORMANCE vs CLOCK DUTY CYCLE
(70 MHz)
Figure 35. PERFORMANCE vs CLOCK DUTY CYCLE
(170 MHz)
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SLAS900C –OCTOBER 2012–REVISED JULY 2013
TYPICAL CHARACTERISTICS: ADS42JB49
Typical values are at TA = +25°C, full temperature range is TMIN = –40°C to TMAX = +85°C, ADC sampling rate = 250 MSPS,
50% clock duty cycle, AVDD = 1.8 V, AVDD3V = 3.3 V, DRVDD = 1.8 V, IOVDD = 1.8 V, –1-dBFS differential input, 2-VPP
full-scale, and 32k-point FFT, unless otherwise noted.
0
0
fIN = 10 MHz
fIN = 170 MHz
SFDR = 97 dBc
SNR = 73.4 dBFS
SINAD = 73.3 dBFS
THD = 95 dBc
SFDR = 89 dBc
SNR = 72.8 dBFS
SINAD = 72.5 dBFS
THD = 88 dBc
−20
−20
SFDR Non HD2, HD3
SFDR Non HD2, HD3
= 103 dBc
= 100 dBc
−40
−40
−60
−60
−80
−80
−100
−120
−100
−120
0
25
50
75
100
125
0
25
50
75
100
125
Frequency (MHz)
Frequency (MHz)
G031
G032
Figure 36. FFT FOR 10-MHz INPUT SIGNAL
Figure 37. FFT FOR 170-MHz INPUT SIGNAL
0
−20
0
±20
fIN = 10 MHz
fIN = 300 MHz
SFDR = 74 dBc
SNR = 72.1 dBFS
SINAD = 69.8 dBFS
THD = 72 dBc
SFDR = 89 dBc
SNR = 75 dBFS
SINAD = 74.8 dBFS
THD = 88 dBc
SFDR Non HD2, HD3
SFDR Non HD2, HD3 =
= 103 dBc
−40
±40
−60
±60
−80
±80
−100
−120
±100
±120
0
25
50
75
100
125
0
25
50
75
100
125
Frequency (MHz)
Frequency (Mhz)
G034
C033
Figure 38. FFT FOR 300-MHz INPUT SIGNAL
Figure 39. FFT FOR 10-MHz INPUT SIGNAL
(2.5-VPP Full-Scale)
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TYPICAL CHARACTERISTICS: ADS42JB49 (continued)
Typical values are at TA = +25°C, full temperature range is TMIN = –40°C to TMAX = +85°C, ADC sampling rate = 250 MSPS,
50% clock duty cycle, AVDD = 1.8 V, AVDD3V = 3.3 V, DRVDD = 1.8 V, IOVDD = 1.8 V, –1-dBFS differential input, 2-VPP
full-scale, and 32k-point FFT, unless otherwise noted.
0
0
fIN = 170 MHz
fIN = 300 MHz
SFDR = 87 dBc
SNR = 73.9 dBFS
SINAD = 73.7 dBFS
THD = 85 dBc
SFDR = 71 dBc
SNR = 73.1 dBFS
SINAD = 68.4 dBFS
THD = 69 dBc
−20
−20
SFDR Non HD2, HD3
SFDR Non HD2, HD3
= 94 dBc
= 93 dBc
−40
−40
−60
−60
−80
−80
−100
−120
−100
−120
0
25
50
75
100
125
0
25
50
75
100
125
Frequency (MHz)
Frequency (MHz)
G035
G036
Figure 40. FFT FOR 170-MHz INPUT SIGNAL
(2.5-VPP Full-Scale)
Figure 41. FFT FOR 300-MHz INPUT SIGNAL
(2.5-VPP Full-Scale)
0
−20
0
−20
Each Tone at
−7 dBFS Amplitude
fIN1 = 46 MHz
fIN2 = 50 MHz
Each Tone at
−36 dBFS Amplitude
fIN1 = 46 MHz
fIN2 = 50 MHz
2−Tone IMD = 98 dBFS
SFDR = 105 dBFS
2−Tone IMD = 101 dBFS
SFDR = 106 dBFS
−40
−40
−60
−60
−80
−80
−100
−120
−100
−120
0
25
50
75
100
125
0
25
50
75
100
125
Frequency (MHz)
Frequency (MHz)
G037
G038
Figure 42. FFT FOR TWO-TONE INPUT SIGNAL
(–7 dBFS at 46 MHz and 50 MHz)
Figure 43. FFT FOR TWO-TONE INPUT SIGNAL
(–36 dBFS at 46 MHz and 50 MHz)
22
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SLAS900C –OCTOBER 2012–REVISED JULY 2013
TYPICAL CHARACTERISTICS: ADS42JB49 (continued)
Typical values are at TA = +25°C, full temperature range is TMIN = –40°C to TMAX = +85°C, ADC sampling rate = 250 MSPS,
50% clock duty cycle, AVDD = 1.8 V, AVDD3V = 3.3 V, DRVDD = 1.8 V, IOVDD = 1.8 V, –1-dBFS differential input, 2-VPP
full-scale, and 32k-point FFT, unless otherwise noted.
0
0
Each Tone at
Each Tone at
−7 dBFS Amplitude
fIN1 = 185 MHz
fIN2 = 190 MHz
−36 dBFS Amplitude
fIN1 = 185 MHz
fIN2 = 190 MHz
−20
−20
2−Tone IMD = 90 dBFS
SFDR = 102 dBFS
2−Tone IMD = 101 dBFS
SFDR = 104 dBFS
−40
−40
−60
−60
−80
−80
−100
−120
−100
−120
0
25
50
75
100
125
0
25
50
75
100
125
Frequency (MHz)
Frequency (MHz)
G039
G040
Figure 44. FFT FOR TWO-TONE INPUT SIGNAL
(–7 dBFS at 185 MHz and 190 MHz)
Figure 45. FFT FOR TWO-TONE INPUT SIGNAL
(–36 dBFS at 185 MHz and 190 MHz)
−98
−100
−102
−104
−106
−108
−110
−90
−92
fIN1 = 46 MHz
fIN2 = 50 MHz
fIN1 = 185 MHz
fIN2 = 190 MHz
−94
−96
−98
−100
−102
−104
−106
−108
−110
−36 −33 −30 −27 −24 −21 −18 −15 −12 −9 −7
−36 −33 −30 −27 −24 −21 −18 −15 −12 −9 −7
Each Tone Amplitude (dBFS)
Each Tone Amplitude (dBFS)
G041
G042
Figure 46. INTERMODULATION DISTORTION vs
INPUT AMPLITUDE (46 MHz and 50 MHz)
Figure 47. INTERMODULATION DISTORTION vs
INPUT AMPLITUDE (185 MHz and 190 MHz)
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TYPICAL CHARACTERISTICS: ADS42JB49 (continued)
Typical values are at TA = +25°C, full temperature range is TMIN = –40°C to TMAX = +85°C, ADC sampling rate = 250 MSPS,
50% clock duty cycle, AVDD = 1.8 V, AVDD3V = 3.3 V, DRVDD = 1.8 V, IOVDD = 1.8 V, –1-dBFS differential input, 2-VPP
full-scale, and 32k-point FFT, unless otherwise noted.
100
95
90
85
80
75
70
65
60
76
75
74
73
72
71
70
69
2−VPP Full−Scale
2.5−VPP Full−Scale
2−VPP Full−Scale
2.5−VPP Full−Scale
0
50
100
150
200
250
300
350
400
0
50
100
150
200
250
300
350
400
Input Frequency (MHz)
Input Frequency (MHz)
G043
G044
Figure 48. SPURIOUS-FREE DYNAMIC RANGE vs
INPUT FREQUENCY
Figure 49. SIGNAL-TO-NOISE RATIO vs
INPUT FREQUENCY
120
110
100
90
77
76
75
74
73
72
71
70
69
68
67
66
10 MHz
70 MHz
100 MHz
130 MHz
170 MHz
230 MHz
270 MHz
350 MHz
400 MHz
491 MHz
10 MHz
70 MHz
100 MHz
130 MHz
170 MHz
230 MHz
270 MHz
350 MHz
400 MHz
491 MHz
80
70
60
−2−1.5−1−0.5 0 0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
−2−1.5−1−0.5 0 0.5
1
1.5
2 2.5 3 3.5 4 4.5 5 5.5 6
Digital Gain (dB)
Digital Gain (dB)
G045
G046
Figure 50. SPURIOUS-FREE DYNAMIC RANGE vs
DIGITAL GAIN
Figure 51. SIGNAL-TO-NOISE RATIO vs
DIGITAL GAIN
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SLAS900C –OCTOBER 2012–REVISED JULY 2013
TYPICAL CHARACTERISTICS: ADS42JB49 (continued)
Typical values are at TA = +25°C, full temperature range is TMIN = –40°C to TMAX = +85°C, ADC sampling rate = 250 MSPS,
50% clock duty cycle, AVDD = 1.8 V, AVDD3V = 3.3 V, DRVDD = 1.8 V, IOVDD = 1.8 V, –1-dBFS differential input, 2-VPP
full-scale, and 32k-point FFT, unless otherwise noted.
77
76.5
76
130
120
110
100
90
76.5
130
120
110
100
90
Input Frequency = 70 MHz
SNR(dBFS)
SFDR(dBc)
SFDR(dBFS)
Input Frequency = 170 MHz
SNR(dBFS)
SFDR(dBc)
SFDR(dBFS)
76
75.5
75
75.5
75
74.5
74
74.5
74
80
80
70
73.5
73
70
73.5
73
60
60
50
72.5
72
50
72.5
72
40
40
30
71.5
30
71.5
20
71
−70
20
−70
−60
−50
−40
−30
−20
−10
0
−60
−50
−40
−30
−20
−10
0
Amplitude (dBFS)
Amplitude (dBFS)
G047
G048
Figure 52. PERFORMANCE vs INPUT AMPLITUDE
(70 MHz)
Figure 53. PERFORMANCE vs INPUT AMPLITUDE
(170 MHz)
99
96
94
92
89
86
84
82
75.5
101
98
95
92
89
86
83
80
75
Input Frequency = 70 MHz
SFDR
SNR
Input Frequency = 170 MHz
SFDR
SNR
75
74.5
74
74.5
74
73.5
73
73.5
73
72.5
72
72.5
72
1.95
71.5
1.95
1.85
1.87
1.9
1.93
1.85
1.87
1.9
1.93
Input Common−Mode Voltage (V)
Input Common−Mode Voltage (V)
G049
G050
Figure 54. PERFORMANCE vs
INPUT COMMON-MODE VOLTAGE (70 MHz)
Figure 55. PERFORMANCE vs
INPUT COMMON-MODE VOLTAGE (170 MHz)
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TYPICAL CHARACTERISTICS: ADS42JB49 (continued)
Typical values are at TA = +25°C, full temperature range is TMIN = –40°C to TMAX = +85°C, ADC sampling rate = 250 MSPS,
50% clock duty cycle, AVDD = 1.8 V, AVDD3V = 3.3 V, DRVDD = 1.8 V, IOVDD = 1.8 V, –1-dBFS differential input, 2-VPP
full-scale, and 32k-point FFT, unless otherwise noted.
99
98
97
96
95
94
93
92
91
90
89
88
87
74.5
AVDD = 1.7 V
AVDD = 1.75 V
AVDD = 1.8 V
AVDD = 1.85 V
AVDD = 1.9 V
AVDD = 1.7 V
AVDD = 1.75V
AVDD = 1.8 V
AVDD = 1.85 V
AVDD = 1.9 V
74
73.5
73
72.5
72
71.5
Input Frequency = 170 MHz
−15 10
Temperature (°C)
Input Frequency = 170 MHz
−15 10
Temperature (°C)
71
−40
−40
35
60
85
35
60
85
G051
G052
Figure 56. SPURIOUS-FREE DYNAMIC RANGE vs
AVDD SUPPLY AND TEMPERATURE (170 MHz)
Figure 57. SIGNAL-TO-NOISE RATIO vs
AVDD SUPPLY AND TEMPERATURE (170 MHz)
98
97
96
95
94
93
92
91
90
89
88
87
74.5
74
AVDD3V = 3.15 V
AVDD3V = 3.2 V
AVDD3V = 3.25 V
AVDD3V = 3.3 V
AVDD3V = 3.35 V
AVDD3V = 3.4 V
AVDD3V = 3.45 V
AVDD3V = 3.15 V
AVDD3V = 3.2 V
AVDD3V = 3.25 V
AVDD3V = 3.3 V
AVDD3V = 3.35 V
AVDD3V = 3.4 V
AVDD3V = 3.45 V
73.5
73
72.5
72
Input Frequency = 170 MHz
−15 10
Temperature (°C)
Input Frequency = 170 MHz
−15 10
Temperature (°C)
71.5
−40
35
60
85
−40
35
60
85
G053
G054
Figure 58. SPURIOUS-FREE DYNAMIC RANGE vs
AVDD_BUF SUPPLY AND TEMPERATURE (170 MHz)
Figure 59. SIGNAL-TO-NOISE RATIO vs AVDD_BUF
SUPPLY AND TEMPERATURE (170 MHz)
26
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SLAS900C –OCTOBER 2012–REVISED JULY 2013
TYPICAL CHARACTERISTICS: ADS42JB49 (continued)
Typical values are at TA = +25°C, full temperature range is TMIN = –40°C to TMAX = +85°C, ADC sampling rate = 250 MSPS,
50% clock duty cycle, AVDD = 1.8 V, AVDD3V = 3.3 V, DRVDD = 1.8 V, IOVDD = 1.8 V, –1-dBFS differential input, 2-VPP
full-scale, and 32k-point FFT, unless otherwise noted.
97
96
95
94
93
92
91
90
89
88
74.5
DRVDD = 1.7 V
DRVDD = 1.75 V
DRVDD = 1.8 V
DRVDD = 1.85 V
DRVDD = 1.9 V
DRVDD = 1.7 V
DRVDD = 1.75 V
DRVDD = 1.8 V
DRVDD = 1.85 V
DRVDD = 1.9 V
74
73.5
73
72.5
72
71.5
Input Frequency = 170 MHz
−15 10
Temperature (°C)
Input Frequency = 170 MHz
−15 10
Temperature (°C)
71
−40
−40
35
60
85
35
60
85
G055
G056
Figure 60. SPURIOUS-FREE DYNAMIC RANGE vs
DRVDD SUPPLY AND TEMPERATURE (170 MHz)
Figure 61. SIGNAL-TO-NOISE RATIO vs
DRVDD SUPPLY AND TEMPERATURE (170 MHz)
96
94
92
90
88
86
84
77
98
96
94
92
90
88
86
84
82
82
Input Frequency = 70 MHz
SFDR
SNR
Input Frequency = 170 MHz
SFDR
SNR
80
78
76
74
72
70
68
66
76
75
74
73
72
71
0.1 0.3 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 2.1
0.1 0.3 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 2.1
Differential Clock Amplitudes (Vpp)
Differential Clock Amplitudes (Vpp)
G057
G058
Figure 62. PERFORMANCE vs CLOCK AMPLITUDE
(70 MHz)
Figure 63. PERFORMANCE vs CLOCK AMPLITUDE
(170 MHz)
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TYPICAL CHARACTERISTICS: ADS42JB49 (continued)
Typical values are at TA = +25°C, full temperature range is TMIN = –40°C to TMAX = +85°C, ADC sampling rate = 250 MSPS,
50% clock duty cycle, AVDD = 1.8 V, AVDD3V = 3.3 V, DRVDD = 1.8 V, IOVDD = 1.8 V, –1-dBFS differential input, 2-VPP
full-scale, and 32k-point FFT, unless otherwise noted.
96
94
92
90
88
86
84
82
75
96
94
92
90
88
86
84
82
74.5
Input Frequency = 70 MHz
SNR
SFDR
Input Frequency = 170 MHz
SNR
SFDR
74.5
74
74
73.5
73
73.5
73
72.5
72
72.5
72
71.5
71
71.5
30
40
50
Input Clock Duty Cycle (%)
60
70
30
40
50
Input Clock Duty Cycle (%)
60
70
G059
G060
Figure 64. PERFORMANCE vs CLOCK DUTY CYCLE
(70 MHz)
Figure 65. PERFORMANCE vs CLOCK DUTY CYCLE
(170 MHz)
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SLAS900C –OCTOBER 2012–REVISED JULY 2013
TYPICAL CHARACTERISTICS: COMMON
Typical values are at TA = +25°C, full temperature range is TMIN = –40°C to TMAX = +85°C, ADC sampling rate = 250 MSPS,
50% clock duty cycle, AVDD = 1.8 V, AVDD3V = 3.3 V, DRVDD = 1.8 V, IOVDD = 1.8 V, –1-dBFS differential input, 2-VPP
full-scale, and 64k-point FFT, unless otherwise noted.
0
0
−5
fIN = 100 MHz
SFDR = 86 dBc
Input Frequency = 10MHz
50−mVPP Signal Superimposed on VCM
fCM = 5 MHz, 50 mVPP
Amplitude (fIN) = -1 dBFS
Amplitude (fCM) = -105 dBFS
Amplitude (fIN + fCM) = -90 dBFS
Amplitude (fIN - fCM) = -87 dBFS
−10
−15
−20
−25
−30
−35
−40
−45
−50
−55
−60
−65
±20
±40
±60
±80
±100
±120
0
50
100
150
200
250
300
0
20
40
60
80
100
120
Common−Mode Test Signal Frequency (MHz)
Frequency (Mhz)
G062
C061
Figure 66. COMMON-MODE REJECTION RATIO FFT
Figure 67. COMMON-MODE REJECTION RATIO vs
TEST SIGNAL FREQUENCY
−20
0
±20
fIN = 20 MHz
SFDR = 87 dBc
50−mVPP Signal Superimposed on AVDD
100−mVPP Signal Superimposed on AVDD3V
fPSRR = 5 MHz, 50 mVPP
Amplitude (fIN) = -1 dBFS
Amplitude (fPSRR) = -88 dBFS
Amplitude (fIN + fPSRR) = -97.8
dBFS
−30
−40
−50
−60
−70
−80
−90
±40
±60
±80
±100
±120
Input Frequency = 20MHz
0
50
100
150
200
250
300
0
20
40
60
80
100
120
Test Signal Frequency on Supply (MHz)
Frequency (Mhz)
G064
C063
Figure 68. POWER-SUPPLY REJECTION RATIO FFT FOR
AVDD SUPPLY
Figure 69. POWER-SUPPLY REJECTION RATIO vs
TEST SIGNAL FREQUENCY
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TYPICAL CHARACTERISTICS: COMMON (continued)
Typical values are at TA = +25°C, full temperature range is TMIN = –40°C to TMAX = +85°C, ADC sampling rate = 250 MSPS,
50% clock duty cycle, AVDD = 1.8 V, AVDD3V = 3.3 V, DRVDD = 1.8 V, IOVDD = 1.8 V, –1-dBFS differential input, 2-VPP
full-scale, and 64k-point FFT, unless otherwise noted.
2
1.8
1.6
1.4
1.2
1
0.18
0.15
0.12
0.09
0.06
0.03
0
AVDD Power
DVDD Power
IOVDD Power
AVDD3V Power
Total Power
20X Mode
10X Mode
0.8
0.6
0.4
0.2
0
0
50
100
150
200
250
0
50
100
150
200
250
Sampling Speed (MSPS)
Sampling Speed (MSPS)
G065
G066
Figure 70. TOTAL POWER vs SAMPLING FREQUENCY
Figure 71. IOVDD POWER vs SAMPLING FREQUENCY
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SLAS900C –OCTOBER 2012–REVISED JULY 2013
TYPICAL CHARACTERISTICS: CONTOUR
Typical values are at TA = +25°C, full temperature range is TMIN = –40°C to TMAX = +85°C, ADC sampling rate = 250 MSPS,
50% clock duty cycle, AVDD = 1.8 V, AVDD3V = 3.3 V, DRVDD = 1.8 V, IOVDD = 1.8 V, –1-dBFS differential input, 2-VPP
full-scale, and 64k-point FFT, unless otherwise noted.
Spurious-Free Dynamic Range (SFDR): General
240
75
70
85
80
95
90
220
200
180
160
140
120
100
80
80
85
75
70
65
90
95
90
95
90
80
85
75
70
50
100
150
200
250
300
350
400
95
fIN - Input Frequency - MHz
80
65
70
75
85
90
SFDR - dBc
Figure 72. 0-dB GAIN (SFDR)
95
240
75
95
90
80
70
85
220
200
180
95
95
95
75
70
90
80
85
160
140
120
100
80
95
95
75
70
85
90
80
95
200
300
400
500
600
95
100
fIN - Input Frequency - MHz
80
70
75
85
90
SFDR - dBc
Figure 73. 6-dB GAIN (SFDR)
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TYPICAL CHARACTERISTICS: CONTOUR (continued)
Typical values are at TA = +25°C, full temperature range is TMIN = –40°C to TMAX = +85°C, ADC sampling rate = 250 MSPS,
50% clock duty cycle, AVDD = 1.8 V, AVDD3V = 3.3 V, DRVDD = 1.8 V, IOVDD = 1.8 V, –1-dBFS differential input, 2-VPP
full-scale, and 64k-point FFT, unless otherwise noted.
Signal-to-Noise Ratio (SNR): ADS42JB69
240
73.2
73.6
72.8
72.4
72
71.5
220
200
180
160
140
120
100
80
74
73.2
73.6
72.8
72.4
72
71.5
71
74
72.4
73.6
72.8
73.2
72
71.5
70.5
71
350
74
50
100
71
150
200
250
300
400
fIN - Input Frequency - MHz
70.5
71.5
72
72.5
73
73.5
74
SNR - dBFS
Figure 74. 0-dB GAIN (SNR, ADS42JB69)
240
67.5
67.2
66.9
66.4
68.1
67.8
220
200
180
68.1
68.1
67.5
67.2
66.9
66.4
67.8
160
140
120
100
80
67.8
68.1
65.9
66.4
500
68.4
50
66.9
67.2
67.5
100
150
200
250
300
350
400
450
550
600
fIN - Input Frequency - MHz
67
65.5
66
66.5
67.5
68
SNR - dBFS
Figure 75. 6-dB GAIN (SNR, ADS42JB69)
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TYPICAL CHARACTERISTICS: CONTOUR (continued)
Typical values are at TA = +25°C, full temperature range is TMIN = –40°C to TMAX = +85°C, ADC sampling rate = 250 MSPS,
50% clock duty cycle, AVDD = 1.8 V, AVDD3V = 3.3 V, DRVDD = 1.8 V, IOVDD = 1.8 V, –1-dBFS differential input, 2-VPP
full-scale, and 64k-point FFT, unless otherwise noted.
Signal-to-Noise Ratio (SNR): ADS42JB49
240
72.6
72.2
73
71.3
71.8
220
200
180
160
140
120
100
80
73.4
70.8
72.6
73
72.2
71.3
71.8
73.4
70.8
73
71.8
71.3
70.3
72.6
72.2
73.4
70.5
71
350
50
100
150
200
250
300
400
fIN - Input Frequency - MHz
71
71.5
72
72.5
73
70
SNR - dBFS
Figure 76. 0-dB GAIN (SNR, ADS42JB49)
240
67.3
67
66.7
66.4
67.6
67.9
220
200
180
67.9
67.3
67
66.7
66.4
67.6
160
140
120
100
80
67.9
67.9
65.9
67.6
66.4
66.7
67.3
67
68.2
200
300
fIN - Input Frequency - MHz
400
500
600
100
65.5
66
66.5
67
67.5
68
SNR - dBFS
Figure 77. 6-dB GAIN (SNR, ADS42JB49)
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DEVICE CONFIGURATION
The ADS42JB49 and ADS42JB69 can be configured using a serial programming interface, as described in the
Serial Interface section. In addition, the device has four dedicated parallel pins (PDN_GBL, STBY, CTRL1, and
CTRL2) for controlling the power-down modes.
SERIAL INTERFACE
The ADC has a set of internal registers that can be accessed by the serial interface formed by the SEN (serial
interface enable), SCLK (serial interface clock), SDATA (serial interface data), and SDOUT (serial interface data
output) pins. Serially shifting bits into the device is enabled when SEN is low. SDATA serial data are latched at
every SCLK rising edge when SEN is active (low). The serial data are loaded into the register at every 16th
SCLK rising edge when SEN is low. When the word length exceeds a multiple of 16 bits, the excess bits are
ignored. Data can be loaded in multiples of 16-bit words within a single active SEN pulse. The interface functions
with SCLK frequencies from 20 MHz down to very low speeds (of a few hertz) and also with non-50% SCLK duty
cycle.
Register Initialization
After power-up, the internal registers must be initialized to their default values through a hardware reset by
applying a high pulse on the RESET pin (of widths greater than 10 ns), as shown in Figure 78. Later during
operation, if required serial interface registers can be cleared by:
1. Either through a hardware reset or
2. By applying a software reset. When using the serial interface, set the RESET bit (D0 in register address 08h)
high. This setting initializes the internal registers to the default values and then self-resets the RESET bit low.
In this case, the RESET pin is kept low.
Power Supply
AVDD, DRVDD
t1
RESET
t2
t3
SEN
NOTE: After power-up, the internal registers must be initialized to their default values through a hardware reset by applying a high pulse on
the RESET pin.
Figure 78. Reset Timing Diagram
(1)
Table 3. Reset Timing
PARAMETER
Power-on delay
CONDITIONS
MIN
TYP MAX UNIT
Delay from AVDD and DRVDD power-up to active RESET
pulse
1
ms
t1
10
ns
t2
t3
Reset pulse width
Active RESET signal pulse width
1
µs
ns
Register write delay
Delay from RESET disable to SEN active
100
(1) Typical values at +25°C; minimum and maximum values across the full temperature range: TMIN = –40°C to TMAX = +85°C, unless
otherwise noted.
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Serial Register Write
The internal device register can be programmed following these steps:
1. Drive the SEN pin low.
2. Set the R/W bit to ‘0’ (bit A7 of the 8-bit address).
3. Set bit A6 in the address field to ‘0’.
4. Initiate a serial interface cycle specifying the address of the register (A5 to A0) whose content must be
written (as shown in Figure 79 and Table 4).
5. Write the 8-bit data that is latched on the SCLK rising edge.
Register Address <5:0>
Register Data <7:0>
SDATA
R/W
= 0
0
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
tDH
D0
tSCLK
tDSU
SCLK
SEN
tSLOADS
tSLOADH
RESET
Figure 79. Serial Register Write Timing Diagram
Table 4. Serial Interface Timing(1)
PARAMETER
MIN
TYP
MAX
UNIT
MHz
ns
fSCLK
SCLK frequency (equal to 1 / tSCLK
SEN to SCLK setup time
SCLK to SEN hold time
SDIO setup time
)
> dc
25
20
tSLOADS
tSLOADH
tDSU
25
ns
25
ns
tDH
SDIO hold time
25
ns
(1) Typical values are at +25°C, minimum and maximum values are across the full temperature range of TMIN = –40°C to TMAX = +85°C,
AVDD3V = 3.3 V, and AVDD = DRVDD = IOVDD = 1.8 V, unless otherwise noted.
Serial Register Readout
The device includes a mode where the contents of the internal registers can be read back. This readback mode
may be useful as a diagnostic check to verify the serial interface communication between the external controller
and the ADC.
1. Set bit A7 (MSB) of 8 bit address to '1'.
2. Write the address of register on bits A5 through A0 whose contents must be read. See Figure 80
3. The device outputs the contents (D7 to D0) of the selected register on the SDOUT pin (pin 45).
4. The external controller can latch the contents at the SCLK rising edge.
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When serial registers are enabled for writing (bit A7 of 8-bit address bus is 0), the SDOUT pin is in a high-
impedance mode. If serial readout is not used, the SDOUT pin must float. Figure 80 shows a timing diagram of
this readout mode. SDOUT comes out at the SCLK falling edge with an approximate delay (tSD_DELAY) of 20 ns,
as shown in Figure 81.
Register Address <5:0>
Register Data: don’t care
SDATA
R/W
= 1
A5
A4
A3
A2
A1
A0
D7
D7
D6
D6
D5
D4
D3
D2
D1
D1
D0
D0
0
Register Read Data <7:0>
SDOUT
SCLK
D5
D4
D3
D2
SEN
Figure 80. Serial Register Readout Timing Diagram
SCLK
tSD_DELAY
SDOUT
Figure 81. SDOUT Timing Diagram
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PIN CONTROLS
The device power-down functions can be controlled either through the parallel control pins (STBY, PDN_GBL,
CTRL1, and CTRL2) or through an SPI register setting.
STBY places the device in a standby power-down mode. PDN_GBL places the device in global power-down
mode.
Table 5. CTRL1, CTRL2 Pin Functions
CTRL1
Low
CTRL2
Low
DESCRIPTION
Normal operation
High
Low
Low
Channel A powered down
Channel B powered down
Global power-down
High
High
High
Table 6. PDN_GBL Pin Function
PDN_GBL
DESCRIPTION
Low
Normal operation
High
Global power-down. Wake-up from this mode is slow.
Table 7. STBY Pin Function
STBY
DESCRIPTION
Low
Normal operation
ADCs are powered down while the input clock buffer and
output CML buffers are alive. Wake-up from this mode is
fast.
High
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SUMMARY OF SERIAL INTERFACE REGISTERS
REGISTER
ADDRESS
REGISTER DATA
A[7:0]
(Hex)
D7
D6
D5
D4
D3
D2
D1
D0
06
07
0
0
0
0
0
0
0
0
0
0
0
CLK DIV
SYSREF DELAY
DATA
FORMAT
Always write
1
08
0B
0C
0D
0E
PDN CHA
PDN CHB
STDBY
0
0
RESET
CHA GAIN
EN
CHA GAIN
0
0
0
0
0
CHB GAIN
EN
CHBGAIN
0
HIGH FREQ
1
HIGH FREQ 1
HIGH FREQ 2
0
0
0
0
0
0
0
0
FAST OVR EN
0
HIGH FREQ
2
0F
10
11
12
13
1F
CHA TEST PATTERNS
CHB TEST PATTERNS
CUSTOM PATTERN (15:8)
CUSTOM PATTERN (15:8)
CUSTOM PATTERN (15:8)
CUSTOM PATTERN (15:8)
Always write 0
FAST OVR THRESHOLD
TX LINK
CONFIG
DATA0
TESTMODE FLIP ADC
FRAME
ALIGN
26
SERDES TEST PATTERN
IDLE SYNC
LAN ALIGN
EN
0
DATA
27
2B
0
0
0
0
0
0
0
0
0
CTRLK
0
CTRLF
SCRAMBLE
EN
0
0
OCTETS PER
FRAME
2C
0
0
0
0
0
0
0
0
0
2D
30
0
FRAMES PER MULTIFRAME
SUBCLASS
0
0
0
0
0
0
0
LMFC
RESET
MASK
36
SYNC REQ
0
OUTPUT CURRENT SEL
LINK LAYER
RPAT
37
38
LINK LAYER TESTMODE
PULSE DET MODES
RELEASE ILANE SEQ
FORCE LMFC
COUNT
LMFC COUNT INIT
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DESCRIPTION OF SERIAL INTERFACE REGISTERS
REGISTER
REGISTER DATA
ADDRESS
A[7:0] (Hex)
6
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
CLK DIV
Default: 00h
D[1:0]
00
CLK DIV
Internal clock divider for input sample clock
Divide-by-1 (clock divider bypassed)
Divide-by-2
01
10
Divide-by-1
11
Divide-by-4
REGISTER
ADDRESS
REGISTER DATA
A[7:0] (Hex)
D7
D6
D5
D4
D3
D2
D1
D0
7
0
0
0
0
0
0
SYSREF DELAY
Default: 00h
Controls the delay of the SYSREF input with respect to the input clock. Typical
values for the expected delay of different settings are:
D[2:0] SYSREF DELAY
000
001
010
011
100
101
110
111
0-ps delay
60-ps delay
120-ps delay
180-ps delay
240-ps delay
300-ps delay
360-ps delay
420-ps delay
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REGISTER
ADDRESS
REGISTER DATA
A[7:0] (Hex)
D7
D6
D5
D4
D3
D2
D1
D0
DATA
FORMAT
Always write
1
8
PDN CHA
PDN CHB
STDBY
0
0
RESET
Default: 00h
D7
0
PDN CHA
Normal operation
Channel A power down
Power-down channel A
1
D6
0
PDN CHB
Power-down channel B
Normal operation
Channel B power down
1
D5
0
STBY
Dual ADC is placed into standby mode
Normal operation
Both ADCs are powered down (input clock buffer and CML output
buffers are alive)
1
DATA
D4
Digital output data format
FORMAT
0
1
Twos complement
Offset binary
D3
Always write 1
Default value of this bit is 0. It must always be set to 1
D0
RESET
Software reset applied
This bit resets all internal registers to the default values and self-clears to ‘0’.
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REGISTER
ADDRESS
REGISTER DATA
D4 D3
A[7:0] (Hex)
D7
D6
D5
D2
D1
D0
B
CHA GAIN
CHA GAIN EN
0
0
Default: 00h
D[7:3]
CHA GAIN Digital gain for channel A (must set the CHA GAIN EN bit first, bit D2)
Table 8. Digital Gain for Channel A
FULL-SCALE
FULL-SCALE
INPUT VOLTAGE
REGISTER VALUE
DIGITAL GAIN
REGISTER VALUE
DIGITAL GAIN
INPUT VOLTAGE
2.0 VPP
—
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
0 dB
Do not use
Do not use
–2.0 dB
–1.5 dB
–1.0 dB
–0.5 dB
0 dB
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
1.5 dB
2 dB
1.7 VPP
1.6 VPP
—
2.5 dB
3 dB
1.5 VPP
2.5 VPP
2.4 VPP
2.2 VPP
2.1 VPP
2.0 VPP
1.9 VPP
1.8 VPP
1.4 VPP
3.5 dB
4 dB
1.3 VPP
1.25 VPP
1.2 VPP
4.5 dB
5 dB
1.1 VPP
0.5 dB
5.5 dB
6 dB
1.05 VPP
1.0 VPP
1 dB
D2
0
CHA GAIN EN
Digital gain enable bit for channel A
Digital gain disabled
Digital gain enabled
1
REGISTER
ADDRESS
REGISTER DATA
A[7:0] (Hex)
D7
D6
D5
D4
D3
D2
D1
D0
CHB GAIN
C
CHB GAIN
0
0
EN
Default: 00h
D[7:3]
CHB GAIN Digital gain for channel B (must set the CHA GAIN EN bit first, bit D2)
Table 9. Digital Gain for Channel B
FULL-SCALE
FULL-SCALE
INPUT VOLTAGE
REGISTER VALUE
DIGITAL GAIN
REGISTER VALUE
DIGITAL GAIN
INPUT VOLTAGE
2.0 VPP
—
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
0 dB
Do not use
Do not use
–2.0 dB
–1.5 dB
–1.0 dB
–0.5 dB
0 dB
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
1.5 dB
2 dB
1.7 VPP
1.6 VPP
1.5 VPP
1.4 VPP
1.3 VPP
1.25 VPP
1.2 VPP
1.1 VPP
1.05 VPP
1.0 VPP
—
2.5 dB
3 dB
2.5 VPP
2.4 VPP
2.2 VPP
2.1 VPP
2.0 VPP
1.9 VPP
1.8 VPP
3.5 dB
4 dB
4.5 dB
5 dB
0.5 dB
5.5 dB
6 dB
1 dB
D2
0
CHB GAIN EN
Digital gain enable bit for channel B
Digital gain disabled
Digital gain enabled
1
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REGISTER
ADDRESS
REGISTER DATA
A[7:0] (Hex)
D7
D6
D5
D4
D3
D2
D1
D0
HIGH FREQ
1
HIGH FREQ
1
D
0
0
0
0
0
FAST OVR EN
D7, D4 HIGH FREQ 1
High frequency mode 1
00
11
D0
0
Default
Use for input frequencies > 250 MHz along with HIGH FREQ 2
FAST OVR EN Selects if normal or fast OVR signal is presented on OVRA, OVRB pins
Normal OVR on OVRA, OVRB pins
Fast OVR on OVRA, OVRB pins
1
REGISTER
ADDRESS
REGISTER DATA
A[7:0] (Hex)
D7
D6
D5
D4
D3
D2
D1
D0
HIGH FREQ
2
HIGH FREQ
2
E
0
0
0
0
0
0
D7, D4 HIGH FREQ 2
High frequency mode 2
00
11
Default
Use for input frequencies > 250 MHz along with HIGH FREQ 1
REGISTER
ADDRESS
REGISTER DATA
D4 D3
A[7:0] (Hex)
D7
D6
D5
D2
D1
D0
F
CHA TEST PATTERNS
CHB TEST PATTERNS
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Default: 00h
D[7:4]
CHA TEST PATTERNS
Channel A test pattern programmability
16-bit test pattern data is selected as input to JESD block (in ADS42JB49, last two LSBs of 16-bit data are replaced by 00)
0000
0001
0010
0011
Normal operation
All '0's
All '1's
Toggle pattern:
In ADS42JB69, data is an alternating sequence of 1010101010101010 and 0101010101010101.
In ADS42JB49, data alternates between 10101010101010 and 01010101010101.
0100
Digital ramp:
In ADS42JB69, data increments by 1 LSB every clock cycle from code 0 to 65535. In ADS42JB49
data increments by 1 LSB every 4th clock cycle from code 0 to 16383.
0101
0110
Do not use
Single pattern:
In ADS42JB69, data is same as programmed by registers bits CUSTOM PATTERN 1 [15:0]. In
ADS42JB49, data is same as programmed by register bits CUSTOM PATTERN 1 [15:2].
0111
Double pattern:
In ADS42JB69, data alternates between CUSTOM PATTERN 1[15:0] and CUSTOM PATTERN
2[15:0] .In ADS42JB49 data alternates between CUSTOM PATTERN 1[15:2] and CUSTOM
PATTERN 2[15:2].
1000
1001
1010
1011
Deskew pattern:
Do not use
In ADS42JB69, data is AAAAh. In ADS42JB49, data is 3AAAh.
PRBS pattern:
8-Point sine wave:
Data is a sequence of pseudo random numbers.
In ADS42JB69, data is a repetitive sequence of following 8 numbers forming a sine-wave in 2s
complement format:
1, 9598, 32768, 55938, 65535, 55938, 32768, 9598.
In ADS42JB49, data is a repetitive sequence of following 8 numbers forming a sine-wave in 2s
complement format:
0, 2399, 8192, 13984, 16383, 13984, 8192, 2399.
D3-D0
CHB TEST PATTERNS
Channel B test pattern programmability
16-bit test pattern data is selected as input to JESD block (in ADS42JB49, last two LSBs of 16-bit data are replaced by 00)
0000
0001
0010
0011
Normal operation
All '0's
All '1's
Toggle pattern:
In ADS42JB69, data is an alternating sequence of 1010101010101010 and 0101010101010101.
In ADS42JB49, data alternates between 10101010101010 and 01010101010101.
0100
Digital ramp:
In ADS42JB69, data increments by 1 LSB every clock cycle from code 0 to 65535. In ADS42JB49
data increments by 1 LSB every 4th clock cycle from code 0 to 16383.
0101
0110
Do not use
Single pattern:
In ADS42JB69, data is same as programmed by registers bits CUSTOM PATTERN 1 [15:0]. In
ADS42JB49, data is same as programmed by register bits CUSTOM PATTERN 1 [15:2].
0111
Double pattern:
In ADS42JB69, data alternates between CUSTOM PATTERN 1[15:0] and CUSTOM PATTERN
2[15:0] .In ADS42JB49 data alternates between CUSTOM PATTERN 1[15:2] and CUSTOM
PATTERN 2[15:2].
1000
1001
1010
1011
Deskew pattern:
Do not use
In ADS42JB69, data is AAAAh. In ADS42JB49, data is 3AAAh.
PRBS pattern:
8-Point sine wave:
Data is a sequence of pseudo random numbers.
In ADS42JB69, data is a repetitive sequence of following 8 numbers forming a sine-wave in 2s
complement format:
1, 9598, 32768, 55938, 65535, 55938, 32768, 9598.
In ADS42JB49, data is a repetitive sequence of following 8 numbers forming a sine-wave in 2s
complement format:
0, 2399, 8192, 13984, 16383, 13984, 8192, 2399.
REGISTER
REGISTER DATA
ADDRESS
A[7:0] (Hex)
10
D7
D6
D5
D4
D3
D2
D1
D0
CUSTOM PATTERN 1 (15:8)
Default: 00h
D[7:0]
CUSTOM PATTERN 1 (15:8) Sets custom pattern 1 (15:8) using these bits for both channels
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REGISTER
ADDRESS
REGISTER DATA
D4 D3
CUSTOM PATTERN 1 (7:0)
A[7:0] (Hex)
D7
D6
D5
D2
D1
D1
D1
D1
D0
11
Default: 00h
D[7:0]
CUSTOM PATTERN 1 (7:0) Sets custom pattern 1 (7:0) using these bits for both channels
REGISTER
ADDRESS
REGISTER DATA
D4 D3
CUSTOM PATTERN 2 (15:8)
A[7:0] (Hex)
D7
D6
D5
D2
D0
D0
D0
12
Default: 00h
D[7:0]
CUSTOM PATTERN 2 (15:8) Sets custom pattern 2 (15:8) using these bits for both channels
REGISTER
ADDRESS
REGISTER DATA
D4 D3
CUSTOM PATTERN 2 (7:0)
A[7:0] (Hex)
D7
D6
D5
D2
13
Default: 00h
D[7:0]
CUSTOM PATTERN 2 (7:0) Sets custom pattern 2 (7:0) using these bits for both channels
REGISTER
ADDRESS
REGISTER DATA
A[7:0] (Hex)
D7
D6
D5
D4
D3
D2
1F
Always write 0
FAST OVR THRESHOLD
Default: FFh
D7
Always write 0
Default value of this bit is '1'. Always write this bit to '0' when fast OVR thresholds are programmed.
D[6:0]
FAST OVR THRESHOLD
The device has a fast OVR mode that indicates an overload condition at the ADC input. The input voltage level at which the
overload is detected is referred to as the threshold and is programmable using the FAST OVR THRESHOLD bits. FAST OVR is
triggered nine output clock cycles after the overload condition occurs. The threshold at which fast OVR is triggered is (full-scale ×
[the decimal value of the FAST OVR THRESHOLD bits] / 127). See section OVERRANGE INDICATION for details.
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REGISTER
ADDRESS
REGISTER DATA
D3
A[7:0] (Hex)
D7
D6
D5
D4
D2
D1
D0
SERDES TEST
PATTERN
TESTMODE
EN
FLIP ADC
DATA
FRANE
ALIGN
TX LINK CONFIG
DATA
26
IDLE SYNC
LANE ALIGN
Default: 00h
D[7:6]
00
SERDES TEST PATTERN
Normal operation
Sets test patterns in the transport layer of the JESD204B interface
01
Outputs clock pattern:
Encoded pattern:
Output is 10101010 pattern
Output is 1111111100000000
Output is 215 – 1
10
11
PRBS sequence:
D5
0
IDLE SYNC
Sets output pattern when SYNC~ is asserted
Sync code is k28.5 (0xBCBC)
Sync code is 0xBC50
1
D4
TESTMODE EN
Generates long transport layer test pattern mode according to 5.1.63 clause of JESD204B
specification
0
1
Test mode disabled
Test mode enabled
D3
0
FLIP ADC DATA
Normal operation
1
Output data order is
reversed:
MSB – LSB
D2
0
LANE ALIGN
Inserts lane alignment character (K28.3) for the receiver to align to lane boundary per section 5.3.3.5
of the JESD204B specification.
Lane Alignment
characters are not
inserted.
1
Inserts lane alignment characters
D1
FRAME ALIGN
Inserts frame alignment character (K28.7) for the receiver to align to frame boundary per section
5.3.3.4 of the JESD204B specification.
0
1
Frame Alignment
characters are not
inserted.
Inserts frame alignment
characters
D0
0
TX LINK CONFIG DATA Disables sending initial link alignment (ILA) sequence when SYNC~ is de-asserted, '0'
ILA Enabled
ILA disabled
1
REGISTER
ADDRESS
REGISTER DATA
A[7:0] (Hex)
D7
D6
D5
D4
D3
D2
D1
D0
27
0
0
0
0
0
0
CTRL K
CTRL F
Default: 00h
D1
0
CTRL K
Default
Frames per multiframe can be set in register 2Dh
Enables bit for number of frames per multiframe
1
D0
0
CTRL F
Enables bit for number of octets per frame
Default
1
Octets per frame can be specified in register 2Ch
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REGISTER
ADDRESS
REGISTER DATA
A[7:0] (Hex)
D7
D6
D5
D4
D3
D2
D1
D0
2B
SCRAMBLE EN
0
0
0
0
0
0
0
Default: 00h
D7
0
SCRAMBLE EN
Scramble enable bit in the JESD204B interface
Scrambling disabled
Scrambling enabled
1
REGISTER
ADDRESS
REGISTER DATA
A[7:0] (Hex)
D7
D6
D5
D4
D3
D2
D1
D0
OCTETS PER
2C
0
0
0
0
0
0
0
FRAME
Default: 00h
D[7:0]
OCTETS PER FRAME
Sets number of octets per frame (F)
0
1
10x mode using two lanes per ADC
20x mode using one lane per ADC
REGISTER
REGISTER DATA
ADDRESS
A[7:0] (Hex)
2D
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
FRAMES PER MULTIFRAME
Default: 00h
D[4:0] FRAMES PER MULTIFRAME
After reset, the default settings for frames per multiframe are:
Sets number of frames per multiframe
10x
20x
K = 16
K = 8
For each mode, K should not be set to a lower value.
REGISTER
ADDRESS
REGISTER DATA
A[7:0] (Hex)
D7
D6
D5
D4
D3
D2
D1
D0
30
SUBCLASS
0
0
0
0
0
Default: 40h
D[7:5]
SUBCLASS
Sets JESD204B subclass. Note that the default value of these bits after reset is '010', which makes subclass 2
the default class.
000
001
010
Subclass 0
Subclass 1
Subclass 2
Backward compatibility with JESD204A
Deterministic latency using SYSREF signal
Deterministic latency using SYNC~ detection (default subclass after reset)
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REGISTER
ADDRESS
REGISTER DATA
A[7:0] (Hex)
D7
D6
D5
D4
D3
D2
D1
D0
36
SYNC REQ
LMFC RESET MASK
0
0
OUTPUT CURRENT SEL
Default: 00h
D7
0
SYNC REQ
Generates synchronization request
Mask LMFC reset coming to digital
Normal operation
1
Generates sync request
D6
0
LMFC RESET MASK
LMFC reset is not
masked
1
Ignores LMFC reset
D3-D0
OUTPUT CURRENT
SEL
Changes JESD output buffer current
0000
0001
0010
0011
0100
0101
0110
0111
16 mA
15 mA
14 mA
13 mA
20 mA
19 mA
18 mA
17 mA
1000
1001
1010
1011
1100
1101
1110
1111
8 mA
7 mA
6 mA
5 mA
12 mA
11 mA
10 mA
9 mA
REGISTER
ADDRESS
REGISTER DATA
D4
A[7:0] (Hex)
D7
D6
D5
D3
D2
D1
D0
37
LINK LAYER TESTMODE
LINK LAYER RPAT
0
PULSE DET MODES
Default: 00h
D[7:5] LINK LAYER TESTMODE
Generates pattern according to clause 5.3.3.8.2 of the JESD204B document
000
001
010
011
Normal ADC data
D21.5 (high-frequency jitter pattern)
K28.5 (mixed-frequency jitter pattern)
Repeats initial lane alignment (generates K28.5 character and repeats lane alignment
sequences continuously)
100
D4
12-octet RPAT jitter pattern
LINK LAYER RPAT
Changes the running disparity in modified RPAT pattern test mode
(only when link layer test mode = 100)
0
1
Normal operation
Changes disparity
D[2:0] PULSE DET MODES
Selects different detection modes for SYSREF (subclass 1) and SYNC (subclass 2)
D2
D1
D0
0
FUNCTIONALITY
0
1
Don’t care
Don’t care
Allows all pulses to reset input clock dividers
Do not allow reset of analog clock dividers
Allows one pulse immediately after the 0 -> 1 transition to reset the divider
0
Don’t care
0 -> 1
1
transition
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REGISTER
ADDRESS
REGISTER DATA
A[7:0] (Hex)
D7
D6
D5
D4
D3
D2
D1
D0
38
FORCE LMFC COUNT
LMFC COUNT INIT
RELEASE ILANE SEQ
Default: 00h
D7
0
FORCE LMFC COUNT
Normal operation
Enables using a different starting value for the LMFC counter
Forces LMFC count
1
D[6:2]
LMFC COUNT INIT
SYSREF receives the digital block and resets the LMFC count to '0'. K28.5 stops transmitting when
the LMFC count reaches 31. The initial value that the LMFC count resets to can be set using LMFC
COUNT INIT. In this manner, the Rx can be synchronized early because the Rx gets the LANE
ALIGNMENT SEQUENCE early. The FORCE LMFC COUNT register bit must be enabled.
D[1:0]
RELEASE ILANE SEQ
Delays the generation of lane alignment sequence by 0, 1, 2, or 3 multiframes after the code group
synchronization.
00
01
10
11
0
1
2
3
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APPLICATION INFORMATION
THEORY OF OPERATION
The ADS42JB69 and ADS42JB49 is a family of high linearity, buffered analog input, dual-channel ADCs with
maximum sampling rates up to 250 MSPS employing JESD204B interface. The conversion process is initiated by
a rising edge of the external input clock and the analog input signal is sampled. The sampled signal is
sequentially converted by a series of small resolution stages, with the outputs combined in a digital correction
logic block. At every clock edge the sample propagates through the pipeline, resulting in a data latency of 23
clock cycles. The output is available in CML logic levels following JESD204B standard.
ANALOG INPUT
The analog input pins have analog buffers (running from the AVDD3V supply) that internally drive the differential
sampling circuit. As a result of the analog buffer, the input pins present high input impedance to the external
driving source (10-kΩ dc resistance and 4-pF input capacitance). The buffer helps isolate the external driving
source from the switching currents of the sampling circuit. This buffering makes driving the buffered inputs easier
than when compared to an ADC without the buffer.
The input common-mode is set internally using a 5-kΩ resistor from each input pin to VCM so the input signal
can be ac-coupled to the pins. Each input pin (INP, INM) must swing symmetrically between VCM + 0.5 V and
VCM – 0.5 V, resulting in a 2-V
differential input swing. When programmed for 2.5-V
full-scale, each input
PP
PP
pin must swing symmetrically between VCM + 0.625 V and VCM – 0.625 V.
The input sampling circuit has a high 3-dB bandwidth that extends up to 900 MHz (measured with a 50-Ω source
driving a 50-Ω termination between INP and INM). The dynamic offset of the first-stage sub-ADC limits the
maximum analog input frequency to approximately 250 MHz (with a 2.5-VPP full-scale amplitude) and to
approximately 400 MHz (with a 2-VPP full-scale amplitude). This 3-dB bandwidth is different than the analog
bandwidth of 900 MHz, which is only an indicator of signal amplitude versus frequency.
Drive Circuit Requirements
For optimum performance, the analog inputs must be driven differentially. This technique improves the common-
mode noise immunity and even-order harmonic rejection. A small resistor (5 Ω to 10 Ω) in series with each input
pin is recommended to damp out ringing caused by package parasitics.
Figure 82, Figure 83, and Figure 84 show the differential impedance (ZIN = RIN || CIN) at the ADC input pins. The
presence of the analog input buffer results in an almost constant input capacitance up to 1 GHz.
INxP(1)
(2)
RIN
ZIN
CIN
INxM
(1) X = A or B.
(2) ZIN = RIN || (1 / jωCIN).
Figure 82. ADC Equivalent Input Impedance
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10
5
4
3
2
1
0
1
0.1
0.05
0
200
400
600
800
1000
0
200
400
600
800
1000
Frequency (MHz)
Frequency (MHz)
G064
G064
Figure 83. ADC Analog Input Resistance (RIN)
Across Frequency
Figure 84. ADC Analog Input Capacitance (CIN)
Across Frequency
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Driving Circuit
An example driving circuit configuration is shown in Figure 85. To optimize even-harmonic performance at high
input frequencies (greater than the first Nyquist), the use of back-to-back transformers is recommended, as
shown in Figure 85. Note that the drive circuit is terminated by 50 Ω near the ADC side. The ac-coupling
capacitors allow the analog inputs to self-bias around the required common-mode voltage. An additional R-C-R
(39 Ω - 6.8 pF - 39 Ω) circuit placed near device pins helps further improve HD3.
0.1µF
0.1µF
5Q
INP
INM
RINT
39
25
25
0.1µF
6.8 pF
RINT
39
5
0.1µF
1:1
1:1
Device
Figure 85. Drive Circuit for Input Frequencies upto 250MHz
The mismatch in the transformer parasitic capacitance (between the windings) results in degraded even-order
harmonic performance. Connecting two identical RF transformers back-to-back helps minimize this mismatch and
good performance is obtained for high-frequency input signals. An additional termination resistor pair may be
required between the two transformers, as shown in Figure 85. The center point of this termination is connected
to ground to improve the balance between the P (positive) and M (negative) sides. The values of the terminations
between the transformers and on the secondary side must be chosen to obtain an effective 50 Ω (for a 50-Ω
source impedance). For high input frequencies (>250MHz), the R-C-R circuit can be removed as indicated in
Figure 86.
0.1µF
0.1µF
5Q
INP
INM
RINT
25
25
0.1µF
RINT
5
0.1µF
1:1
1:1
Device
Figure 86. Drive Circuit for Input Frequencies > 250MHz
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CLOCK INPUT
The device clock inputs can be driven differentially (sine, LVPECL, or LVDS) or single-ended (LVCMOS), with
little or no difference in performance between them. The common-mode voltage of the clock inputs is set to 1.4 V
using internal 5-kΩ resistors. The self-bias clock inputs of the ADS42JB69 and ADS42JB49 can be driven by the
transformer-coupled, sine-wave clock source or by the ac-coupled, LVPECL and LVDS clock sources, as shown
in Figure 87, Figure 88, and Figure 89. See Figure 90 for details regarding the internal clock buffer.
0.1 mF
0.1 mF
Zo
CLKP
CLKP
Differential
Sine-Wave
Clock Input
RT
Typical LVDS
Clock Input
100 W
0.1 mF
CLKM
Device
0.1 mF
Zo
CLKM
NOTE: RT = termination resistor, if necessary.
Device
Figure 87. Differential Sine-Wave Clock Driving
Circuit
Figure 88. LVDS Clock Driving Circuit
0.1 mF
Zo
CLKP
150 W
Typical LVPECL
Clock Input
100 W
0.1 mF
Zo
CLKM
Device
150 W
Figure 89. LVPECL Clock Driving Circuit
Clock Buffer
LPKG
2 nH
20 W
CLKP
CBOND
1 pF
CEQ
CEQ
5 kW
RESR
100 W
1.4 V
LPKG
2 nH
5 kW
20 W
CLKM
CBOND
1 pF
RESR
100 W
NOTE: CEQ is 1 pF to 3 pF and is the equivalent input capacitance of the clock buffer.
Figure 90. Internal Clock Buffer
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A single-ended CMOS clock can be ac-coupled to the CLKP input, with CLKM connected to ground with a 0.1-μF
capacitor, as shown in Figure 91. However, for best performance the clock inputs must be driven differentially,
thereby reducing susceptibility to common-mode noise. For high input frequency sampling, TI recommends using
a clock source with very low jitter. Band-pass filtering of the clock source can help reduce the effects of jitter.
There is no change in performance with a non-50% duty cycle clock input.
0.1 mF
CMOS
Clock Input
CLKP
0.1 mF
CLKM
Device
Figure 91. Single-Ended Clock Driving Circuit
DIGITAL GAIN
The device includes gain settings that can be used to obtain improved SFDR performance (compared to no
gain). Gain is programmable from –2 dB to 6 dB (in 0.5-dB steps). For each gain setting, the analog input full-
scale range scales proportionally. Table 10 shows how full-scale input voltage changes when digital gain are
programmed in 1-dB steps. Refer to Table 8 to set digital gain using a serial interface register.
SFDR improvement is achieved at the expense of SNR; for 1 dB increase in digital gain, SNR degrades
approximately between 0.5 dB and 1 dB. Therefore, gain can be used as a trade-off between SFDR and SNR.
Note that the default gain after reset is 0 dB with a 2.0-VPP full-scale voltage.
Table 10. Full-Scale Range Across Gains
DIGITAL GAIN
–2 dB
FULL-SCALE INPUT VOLTAGE
(1)
2.5 VPP
–1 dB
2.2 VPP
2.0 VPP
1.8 VPP
1.6 VPP
1.4 VPP
1.25 VPP
1.1 VPP
1.0 VPP
0 dB (default)
1 dB
2 dB
3 dB
4 dB
5 dB
6 dB
(1) Shaded cells indicate performance settings used in the Electrical
Characteristics and Typical Characteristics.
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OVERRANGE INDICATION
The device provides two different overrange indications. Normal OVR (default) is triggered if the final 16-bit data
output exceeds the maximum code value. Fast OVR is triggered if the input voltage exceeds the programmable
overrange threshold and is presented after only nine clock cycles, thus enabling a quicker reaction to an
overrange event. By default, the normal overrange indication is output on the OVRA and OVRB pins. Using the
register bit FAST OVR EN, the fast OVR indication can be presented on the overrange pins instead.
The input voltage level at which the overload is detected is referred to as the threshold and is programmable
using the FAST OVR THRESHOLD bits. FAST OVR is triggered nine output clock cycles after the overload
condition occurs. The threshold voltage amplitude at which fast OVR is triggered is:
1 × [the decimal value of the FAST OVR THRESH bits] / 127
When digital is programmed (for gain values
>
0-dB ), the threshold voltage amplitude is:
10-Gain/20 x [the decimal value of the FAST OVR THRESH bits] / 127
SNR AND CLOCK JITTER
The signal-to-noise ratio (SNR) of the ADC is limited by three different factors, as shown in Equation 1.
Quantization noise is typically not noticeable in pipeline converters and is 96 dBFS for a 16-bit ADC. Thermal
noise limits SNR at low input frequencies and clock jitter sets SNR for higher input frequencies.
2
2
2
ö
SNRQuantization _Noise
æ
ö
SNRThermalNoise
SNRJitter
20
æ
ö
æ
SNRADC[dBc] = -20´log 10 -
ç
è
+ 10 -
ç
è
+ 10 -
ç
è
÷
÷
÷
÷
ç
20
20
ø
ø
ø
(1)
(2)
SNR limitation is a result of sample clock jitter and can be calculated by Equation 2:
SNRJitter [dBc] = -20 ´ log(2p ´ fIN ´ tJitter
)
The total clock jitter (TJitter) has three components: the internal aperture jitter (85 fS for the device) is set by the
noise of the clock input buffer, the external clock jitter, and the jitter from the analog input signal. TJitter can be
calculated by Equation 3:
2
TJitter
=
(TJitter,Ext.Clock_Input)2 + (TAperture_ADC
)
(3)
External clock jitter can be minimized by using high-quality clock sources and jitter cleaners as well as band-pass
filters at the clock input while a faster clock slew rate improves ADC aperture jitter. The device has a 74.1-dBFS
thermal noise and an 85-fS internal aperture jitter. The SNR value depends on the amount of external jitter for
different input frequencies, as shown in Figure 92.
76
74
72
35 fs
70
50 fs
68
66
64
100 fs
150 fs
200 fs
10
100
1000
Fin (MHz)
Figure 92. SNR versus Input Frequency and External Clock Jitter
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INPUT CLOCK DIVIDER
The device is equipped with an internal divider on the clock input. This divider allows operation with a faster input
clock, simplifying the system clock distribution design. The clock divider can be bypassed (divide-by-1) for
operation with a 250-MHz clock. The divide-by-2 option supports a maximum 500-MHz input clock and the
divide-by-4 option supports a maximum 1-GHz input clock frequency.
JESD204B INTERFACE
The JESD interface of ADS42JB49 and ADS42JB69, as shown in Figure 93 , supports device subclasses 0, 1,
and 2 with a maximum output data rate (per lane) of 3.125 Gbps.
An external SYSREF (subclass 1) or SYNC~ (subclass 2) signal is used to align all internal clock phases and the
local multiframe clock to a specific sampling clock edge. This alignment allows synchronization of multiple
devices in a system and minimizes timing and alignment uncertainty.
SYSREF SYNC~
JESD204B
D0, D1
JESD
204B
INA
INB
JESD204B
D0, D1
JESD
204B
Sample
Clock
Figure 93. JESD204B Interface
Depending on the ADC sampling rate, the JESD204B output interface can be operated with either one or two
lanes per ADC. The JESD204B interface can be configured using serial registers.
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The JESD204B transmitter block (Figure 94) consists of the transport layer, the data scrambler, and the link
layer. The transport layer maps the ADC output data into the selected JESD204B frame data format and
manages if the ADC output data or test patterns are transmittied. The link layer performs the 8b and 10b data
encoding as well as the synchronization and initial lane alignment using the SYNC~ input signal. Optionally, data
from the transport layer can be scrambled.
JESD204B Block
Transport Layer
Link Layer
Frame Data
Mapping
8b,10b
encoding
D0
D1
Scrambler
1+x14+x15
Comma characters
Initial lane alignment
Test Patterns
SYNC~
Figure 94. JESD204B Block
JESD204B Initial Lane Alignment (ILA)
When receiving device asserts the SYNC~ signal ( i.e a logic low signal is applied on SYNC~P - SYNC~M), the
device begins transmitting comma (K28.5) characters to establish code group synchronization (CGS).
When synchronization is complete, the receiving device de-asserts the SYNC~ signal and the ADS42JB49 and
ADS42JB69 begin the initial lane alignment (ILA) sequence with the next local multiframe clock boundary. The
device transmits four multiframes, each containing K frames (where K is SPI programmable). Each multiframe
contains the frame start and end symbols; the second multiframe also contains the JESD204 link configuration
data.
JESD204B Test Patterns
There are three different test patterns available in the transport layer of the JESD204B interface. The device
supports a clock output, an encoded, and a PRBS (215 – 1) pattern. These patterns can be enabled by serial
register write in address 26h, bits D[7:6].
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JESD204B Frame Assembly
The JESD204B standard defines the following parameters:
•
•
•
•
L is the number of lanes per Lane.
M is the number of converters per device.
F is the number of octets per frame clock period.
S is the number of samples per frame.
Table 11 lists the available JESD204B formats and valid device ranges. Ranges are limited by the maximum
ADC sample frequency and the SERDES line rate.
Table 11. JESD240B Ranges
L
4
2
M
2
F
1
2
S
1
1
MAX ADC SAMPLING RATE (MSPS)
MAX fSERDES (Gbps)
250
2.5
2
156.25
3.125
The detailed frame assembly in 10x and 20x modes for dual-channel operation is shown in Table 12. Note that
unused lanes in 10x mode become 3-stated.
Table 12. Frame Assembly for Dual-Channel Mode(1)
LANE
DA0
DA1
DB0
DB1
LMF = 421
A1[15:8]
A1[7:0]
LMF = 222
A0[15:8]
A0[7:0]
B0[15:8]
B0[7:0]
A2[15:8]
A2[7:0]
B2[15:8]
B2[7:0]
A0[15:8]
—
A0[7:0]
—
A1[15:8]
A1[7:0]
—
A2[15:8]
—
A2[7:0]
—
—
B1[15:8]
—
B1[15:8]
B1[7:0]
B0[15:8]
—
B0[7:0]
—
B1[7:0]
—
B2[15:8]
—
B2[7:0]
—
(1) In ADS42JB49 two LSBs of 16-bit data are padded with 00.
JESD LINK CONFIGURATION
During the lane alignment sequence, the ADS42JB69 and ADS42JB49 transmit JESD204B configuration
parameters in the second multi-frame of the ILA sequence. Configuration bits are mapped in octets, as per the
JESD204B standard described in Figure 95 and Table 13.
Figure 95. Initial Lane Alignment Sequence
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LSB
Table 13. Mapping of Configuration Bits to Octets
Octet
No
MSB
D6
D5
D4
D3
D2
D1
0
1
DID [7:0]
ADJCNT[3:0]
BID[3:0]
ADJDI
R[0]
2
X
PHADJ[0]
LID[4:0]
L[4:0]
3
4
SCR[0]
F[7:0]
M[7:0]
5
K[4:0]
6
7
CS[1:0]
X
X
N[4:0]
N'[4:0]
S[4:0]
8
SUBCLASSV[2:0]
9
JESDV[2:0]
X
10
11
12
13
HD[0]
CF[4:0]
RES1[7:0]
RES2[7:0]
FCHK[7:0]
Configuration for 2-Lane (20x) SERDES Mode
Table 14 lists the values of the JESD204B configuration bits applicable for the 2-lane SERDES Mode. The
default value of these bits after reset is also specified in the table.
Table 14. Configuration for 2-Lane SERDES Mode
PARAMETER
RANGE
DEFAULT VALUE
AFTER RESET
PARAMETER
DESCRIPTION
FIELD
ENCODING
Number of
adjustment resolution
steps to adjust DAC
LMFC. Applies to
subclass 2 operation
only.
ADJCNT
0 ... 15
ADJCNT[3:0]
Binary value
0
0
Direction to adjust
DAC LMFC
0 – Advance
1 – Delay applies to
subclass 2 operation
only
ADJDIR
0 … 1
ADJDIR[0]
Binary value
Bank ID – extension
to DID
BID
CF
0 ... 15
0 ... 32
BID[3:0]
CF[4:0]
Binary value
Binary value
0
0
No. of control words
per frame clock
period per link
No. of control bits per
sample
CS
0 ... 3
CS[1:0]
DID[7:0]
Binary value
Binary value
0
0
Device (= link)
identification no.
DID
0 ... 255
No. of octets per
frame
F
1 ... 256
0 ... 1
F[7:0]
HD[0]
Binary value minus 1
Binary value
1
0
HD
High-density format
JESD204 version
000 – JESD204A
001 – JESD204B
JESDV
K
0 … 7
JESDV[2:0]
K[4:0]
Binary value
1
8
No. of frames per
multi-frame
1 ... 32
Binary value minus 1
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Table 14. Configuration for 2-Lane SERDES Mode (continued)
PARAMETER
RANGE
DEFAULT VALUE
AFTER RESET
PARAMETER
DESCRIPTION
FIELD
ENCODING
Binary value minus 1
Binary value
No. of lanes per
converter device
(link)
L
1 ... 32
0 ... 31
L[4:0]
0
Lane identification
no. (within link)
LID
LID[4:0]
LID[0] = 0, LID[1] = 1
No. of converters per
device
M
N
1 ... 256
1 ... 32
1 ... 32
M[7:0]
N[4:0]
N'[4:0]
Binary value minus 1
Binary value minus 1
Binary value minus 1
1
Converter resolution
15
15
Total no. of bits per
sample
N’
Phase adjustment
request to DAC
subclass 2 only.
PHADJ
0 ... 1
PHADJ[0]
Binary value
0
No. of samples per
converter per frame
cycle
S
1 ... 32
0 ... 1
S[4:0]
Binary value minus 1
Binary value
0
0
SCR
Scrambling enabled
SCR[0]
Device subclass
version
SUBCLASSV
RES1
000 – Subclass 0
001 – Subclass 1
010 – Subclass 2
0 … 7
SUBCLASSV[2:0]
RES1[7:0]
Binary value
Binary value
2
0
Device subclass
version
000 – Subclass 0
001 – Subclass 1
010 – Subclass 2
0 ... 255
RES2
Reserved field 2
0 ... 255
0 ... 255
RES2[7:0]
FCHK[7:0]
Binary value
Binary value
0
Checksum Σ (all
above fields) mod
256
CHKSUM
44, 45
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Configuration for 4-Lane (10x) SERDES Mode
Table 15 lists the values of the JESD204 configuration bits applicable for the 4-lane SERDES Mode. The default
value of these bits after reset is also specified in the table.
Table 15. Configuration for 4-Lane SERDES Mode
PARAMETER
RANGE
DEFAULT VALUE
AFTER RESET
PARAMETER
DESCRIPTION
FIELD
ENCODING
Number of
adjustment resolution
steps to adjust DAC
LMFC. Applies to
subclass 2 operation
only.
ADJCNT
0 ... 15
ADJCNT[3:0]
Binary value
0
0
Direction to adjust
DAC LMFC
0 – Advance
1 – Delay applies to
subclass 2 operation
only
ADJDIR
0 … 1
ADJDIR[0]
Binary value
Bank ID – extension
to DID
BID
CF
0 ... 15
0 ... 32
BID[3:0]
CF[4:0]
Binary value
Binary value
0
0
No. of control words
per frame clock
period per link
No. of control bits per
sample
CS
0 ... 3
CS[1:0]
DID[7:0]
Binary value
Binary value
0
0
Device (= link)
identification no.
DID
0 ... 255
No. of octets per
frame
F
1 ... 256
0 ... 1
F[7:0]
HD[0]
Binary value minus 1
Binary value
0
1
HD
High-density format
JESD204 version
000 – JESD204A
001 – JESD204B
JESDV
0 … 7
1 ... 32
1 ... 32
0 ... 31
JESDV[2:0]
K[4:0]
Binary value
Binary value minus 1
Binary value minus 1
Binary value
1
16
3
No. of frames per
multi-frame
K
L
No. of lanes per
converter device
(link)
L[4:0]
Lane identification no
(within link)
LID[0] = 0, LID[1] = 1,
LID[2] = 2, LID[3] = 3
LID
LID[4:0]
No. of converters per
device
M
N
1 ... 256
1 ... 32
1 ... 32
M[7:0]
N[4:0]
N'[4:0]
Binary value minus 1
Binary value minus 1
Binary value minus 1
1
Converter resolution
15
15
Total no. of bits per
sample
N’
Phase adjustment
request to DAC
subclass 2 only.
PHADJ
0 ... 1
PHADJ[0]
Binary value
0
No. of samples per
converter per frame
cycle
S
1 ... 32
0 ... 1
S[4:0]
Binary value minus 1
Binary value
0
0
SCR
Scrambling enabled
SCR[0]
Device subclass
version
SUBCLASSV
000 – Subclass 0
001 – Subclass 1
010 – Subclass 2
0 … 7
SUBCLASSV[2:0]
Binary value
2
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Table 15. Configuration for 4-Lane SERDES Mode (continued)
PARAMETER
RANGE
DEFAULT VALUE
AFTER RESET
PARAMETER
DESCRIPTION
FIELD
ENCODING
Device subclass
version
RES1
000 – Subclass 0
001 – Subclass 1
010 – Subclass 2
0 ... 255
RES1[7:0]
Binary value
0
RES2
Reserved field 2
0 ... 255
0 ... 255
RES2[7:0]
FCHK[7:0]
Binary value
Binary value
0
Checksum Σ(all
above fields)mod 256
CHKSUM
54, 55, 56, 57
CML Outputs
The device JESD204B transmitter uses differential CML output drivers. The CML output current is programmable
from 5 mA to 20 mA using register settings.
The output driver includes an internal 50-Ω termination to IOVDD supply. External 50-Ω termination resistors
connected to receiver common-mode voltage should be placed close to receiver pins. AC coupling can be used
to avoid the common-mode mismatch between transmitter and receiver, as shown in Figure 96.
Vterm
Rt= ZO
0.1uF
Rt= ZO
Transmission Line
Zo
DA/B[0,1]P
DA/B[0,1]M
Receiver
0.1uF
Figure 96. CML Output Connections
Figure 97 and Figure 98 show the data eye measurements of the device JESD204B transmitter against the
JESD204B transmitter mask at 2.5 GBPS (10x mode) and 3.125 GBPS (20x mode), respectively.
300
300
150
150
0
0
-150
-150
-300
-300
-200
-150
-100
-50
0
50
100
150
200
-300
-200
-100
0
100
200
300
Time (ps)
Time (ps)
Figure 97. Eye Diagram: 2.5 Gbps
Figure 98. Eye Diagram: 3.125 Gbps
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DEFINITION OF SPECIFICATIONS
Analog Bandwidth: The analog input frequency at which the power of the fundamental is reduced by 3 dB with
respect to the low-frequency value.
Aperture Delay: The delay in time between the rising edge of the input sampling clock and the actual time at
which the sampling occurs. This delay is different across channels. The maximum variation is specified as
aperture delay variation (channel-to-channel).
Aperture Uncertainty (Jitter): The sample-to-sample variation in aperture delay.
Clock Pulse Width and Duty Cycle: The duty cycle of a clock signal is the ratio of the time the clock signal
remains at a logic high (clock pulse width) to the period of the clock signal. Duty cycle is typically expressed as a
percentage. A perfect differential sine-wave clock results in a 50% duty cycle.
Maximum Conversion Rate: The maximum sampling rate at which specified operation is given. All parametric
testing is performed at this sampling rate unless otherwise noted.
Minimum Conversion Rate: The minimum sampling rate at which the ADC functions.
Differential Nonlinearity (DNL): An ideal ADC exhibits code transitions at analog input values spaced exactly 1
LSB apart. The DNL is the deviation of any single step from this ideal value, measured in units of LSBs.
Integral Nonlinearity (INL): The INL is the deviation of the ADC transfer function from a best fit line determined
by a least squares curve fit of that transfer function, measured in units of LSBs.
Gain Error: Gain error is the deviation of the ADC actual input full-scale range from its ideal value. The gain
error is given as a percentage of the ideal input full-scale range. Gain error has two components: error as a
result of reference inaccuracy (EGREF) and error as a result of the channel (EGCHAN). Both errors are specified
independently as EGREF and EGCHAN
To a first-order approximation, the total gain error is ETOTAL ~ EGREF + EGCHAN
For example, if ETOTAL = ±0.5%, the full-scale input varies from (1 – 0.5 / 100) x FSideal to (1 + 0.5 / 100) x FSideal
.
.
.
Offset Error: The offset error is the difference, given in number of LSBs, between the ADC actual average idle
channel output code and the ideal average idle channel output code. This quantity is often mapped into millivolts.
Temperature Drift: The temperature drift coefficient (with respect to gain error and offset error) specifies the
change per degree Celsius of the parameter from TMIN to TMAX. Temperature drift is calculated by dividing the
maximum deviation of the parameter across the TMIN to TMAX range by the difference TMAX – TMIN
.
Signal-to-Noise Ratio (SNR): SNR is the ratio of the power of the fundamental (PS) to the noise floor power
(PN), excluding the power at dc and the first nine harmonics.
PS
SNR = 10Log10
PN
(4)
SNR is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the
reference, or dBFS (dB to full-scale) when the power of the fundamental is extrapolated to the converter full-
scale range.
Signal-to-Noise and Distortion (SINAD): SINAD is the ratio of the power of the fundamental (PS) to the power
of all the other spectral components including noise (PN) and distortion (PD), but excluding dc.
PS
SINAD = 10Log10
PN + PD
(5)
SINAD is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the
reference, or dBFS (dB to full-scale) when the power of the fundamental is extrapolated to the converter full-
scale range.
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Effective Number of Bits (ENOB): ENOB is a measure of the converter performance as compared to the
theoretical limit based on quantization noise.
SINAD - 1.76
ENOB =
6.02
(6)
Total Harmonic Distortion (THD): THD is the ratio of the power of the fundamental (PS) to the power of the first
nine harmonics (PD).
PS
THD = 10Log10
PN
(7)
THD is typically given in units of dBc (dB to carrier).
Spurious-Free Dynamic Range (SFDR): The ratio of the power of the fundamental to the highest other spectral
component (either spur or harmonic). SFDR is typically given in units of dBc (dB to carrier).
Two-Tone Intermodulation Distortion (IMD3): IMD3 is the ratio of the power of the fundamental (at frequencies
f1 and f2) to the power of the worst spectral component at either frequency 2f1 – f2 or 2f2 – f1. IMD3 is either given
in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the reference, or dBFS (dB
to full-scale) when the power of the fundamental is extrapolated to the converter full-scale range.
DC Power-Supply Rejection Ratio (DC PSRR): DC PSSR is the ratio of the change in offset error to a change
in analog supply voltage. The dc PSRR is typically given in units of mV/V.
AC Power-Supply Rejection Ratio (AC PSRR): AC PSRR is the measure of rejection of variations in the supply
voltage by the ADC. If ΔVSUP is the change in supply voltage and ΔVOUT is the resultant change of the ADC
output code (referred to the input), then:
DVOUT
PSRR = 20Log10
(Expressed in dBc)
DVSUP
(8)
Voltage Overload Recovery: The number of clock cycles taken to recover to less than 1% error after an
overload on the analog inputs. This is tested by separately applying a sine wave signal with 6 dB positive and
negative overload. The deviation of the first few samples after the overload (from the expected values) is noted.
Common-Mode Rejection Ratio (CMRR): CMRR is the measure of rejection of variation in the analog input
common-mode by the ADC. If ΔVCM_IN is the change in the common-mode voltage of the input pins and ΔVOUT is
the resulting change of the ADC output code (referred to the input), then:
DVOUT
10
CMRR = 20Log
(Expressed in dBc)
DVCM
(9)
Crosstalk (only for multichannel ADCs): Crosstalk is a measure of the internal coupling of a signal from an
adjacent channel into the channel of interest. Crosstalk is specified separately for coupling from the immediate
neighboring channel (near-channel) and for coupling from channel across the package (far-channel). Crosstalk is
usually measured by applying a full-scale signal in the adjacent channel. Crosstalk is the ratio of the power of the
coupling signal (as measured at the output of the channel of interest) to the power of the signal applied at the
adjacent channel input. Crosstalk is typically expressed in dBc.
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REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (July 2013) to Revision C
Page
•
•
•
•
•
•
•
Added Internal Dither in Features Section ............................................................................................................................ 1
Changed From "The devices provide excellent" to "The devices employ internal dither algorithms to provide" ................. 1
Changed 2-VPP Full-Scale INL maximum specification in ADS42JB69 Electrical Characteristics table .............................. 4
Deleted 2.5-VPP Full-Scale INL maximum specification in ADS42JB69 Electrical Characteristics table .............................. 4
Changed 2-VPP Full-Scale INL maximum specification in ADS42JB49 Electrical Characteristics table .............................. 5
Deleted 2.5-VPP Full-Scale INL maximum specification in ADS42JB49 Electrical Characteristics table .............................. 5
Changed EGREF specifications in General Electrical Characteristics table ........................................................................... 6
Changes from Revision A (November 2012) to Revision B
Page
•
Moved document status to Mixed Status .............................................................................................................................. 1
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PACKAGE OPTION ADDENDUM
www.ti.com
12-Jul-2013
PACKAGING INFORMATION
Orderable Device
ADS42JB49IRGCR
ADS42JB49IRGCT
ADS42JB69IRGC25
ADS42JB69IRGCR
ADS42JB69IRGCT
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 85
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
PREVIEW
VQFN
VQFN
VQFN
VQFN
VQFN
RGC
64
64
64
64
64
2000
Green (RoHS
& no Sb/Br)
Call TI
Call TI
Call TI
Call TI
Call TI
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
AZ42JB49
PREVIEW
PREVIEW
PREVIEW
PREVIEW
RGC
RGC
RGC
RGC
250
25
Green (RoHS
& no Sb/Br)
-40 to 85
AZ42JB49
AZ42JB69
AZ42JB69
AZ42JB69
Green (RoHS
& no Sb/Br)
-40 to 85
2000
250
Green (RoHS
& no Sb/Br)
-40 to 85
Green (RoHS
& no Sb/Br)
-40 to 85
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
12-Jul-2013
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
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相关型号：
ADS42JB46IRGCR
Dual-Channel, 14-Bit, 160-MSPS Analog-to-Digital Converter (ADC) 64-VQFN -40 to 85
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ADS42JB46IRGCT
Dual-Channel, 14-Bit, 160-MSPS Analog-to-Digital Converter (ADC) 64-VQFN -40 to 85
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